[clang] [llvm] [RISCV][MC] Add experimental Smcsps and Sscsps support (PR #211712)

[Sam Elliott via cfe-commits]

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@@ -133,10 +133,16 @@ void RISCVInstPrinter::printCSRSystemRegister(const MCInst *MI, unsigned OpNo,
                                               raw_ostream &O) {
   unsigned Imm = MI->getOperand(OpNo).getImm();
   auto Range = RISCVSysReg::lookupSysRegByEncoding(Imm);
+  bool PreferFeatureSpecific = llvm::any_of(Range, [&](const auto &Reg) {
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lenary wrote:

I think i'd have to do a deeper dive on this specific case.

Broadly: `sf.mscratchcsw` was upstreamed by me, to support the sifive CLIC implementation, which I think was based on an early draft of what's trying to be standardised by fast interrupts. It is in a standard part of the CSR encodings, despite being a vendor name. I would have to closely read the fast interrupts spec to see where the rename came from and whether it came with a change of meaning.

So maybe this actually is an altname or a deprecated name, I'm not sure.

That said, it's also referenced in the sifive codegen for interrupts, and I don't recall if the alt/deprecated names make it into the enum used by codegen.

I think your change probably is reasonable anyway, and maybe the quickest and easiest way to support the new version of the fast interrupts spec, and future places where we have collisions.

/cc @topperc @kito-cheng  who might have an opinion here.

https://github.com/llvm/llvm-project/pull/211712