[clang] 22116c9 - clang/AMDGPU: Migrate cc1 tests to subarch triples (2) (#211823)
via cfe-commits
cfe-commits at lists.llvm.org
Fri Jul 24 08:53:29 PDT 2026
Author: Matt Arsenault
Date: 2026-07-24T17:53:24+02:00
New Revision: 22116c946aa8078cee8d0c5efa49874c6264e92e
URL: https://github.com/llvm/llvm-project/commit/22116c946aa8078cee8d0c5efa49874c6264e92e
DIFF: https://github.com/llvm/llvm-project/commit/22116c946aa8078cee8d0c5efa49874c6264e92e.diff
LOG: clang/AMDGPU: Migrate cc1 tests to subarch triples (2) (#211823)
Rewrite CodeGenCUDA cc1 test RUN lines from `-triple amdgcn...
-target-cpu gfxNNN` to the new subarch triple form, dropping the redundant
-target-cpu.
Autogenerated CHECK lines are regenerated. Tests that intentionally
assert the "target-cpu" function attribute are left unchanged.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
Added:
Modified:
clang/test/CodeGenCUDA/amdgpu-atomic-ops.cu
clang/test/CodeGenCUDA/atomics-remarks-gfx90a.cu
clang/test/CodeGenCUDA/builtins-amdgcn.cu
clang/test/CodeGenCUDA/builtins-unsafe-atomics-gfx90a.cu
clang/test/CodeGenCUDA/cluster_dims.cu
clang/test/CodeGenCUDA/correctly-rounded-div.cu
clang/test/CodeGenCUDA/flush-denormals.cu
clang/test/CodeGenCUDA/fp-contract.cu
clang/test/CodeGenCUDA/host-used-extern-determinism.cu
clang/test/CodeGenCUDA/host-used-extern.cu
clang/test/CodeGenCUDA/implicit-host-device-fun.cu
clang/test/CodeGenCUDA/increment-index-for-thunks.cu
clang/test/CodeGenCUDA/long-double.cu
clang/test/CodeGenCUDA/record-layout.cu
clang/test/CodeGenCUDA/struct-mangling-number.cu
clang/test/CodeGenCUDA/unused-global-var.cu
clang/test/CodeGenCUDA/vtbl.cu
Removed:
################################################################################
diff --git a/clang/test/CodeGenCUDA/amdgpu-atomic-ops.cu b/clang/test/CodeGenCUDA/amdgpu-atomic-ops.cu
index b8819b8e550ea..4255b28cb23eb 100644
--- a/clang/test/CodeGenCUDA/amdgpu-atomic-ops.cu
+++ b/clang/test/CodeGenCUDA/amdgpu-atomic-ops.cu
@@ -1,17 +1,17 @@
-// RUN: %clang_cc1 -x hip %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa \
-// RUN: -fcuda-is-device -target-cpu gfx906 -fnative-half-type \
+// RUN: %clang_cc1 -x hip %s -emit-llvm -o - -triple=amdgpu9.06-amd-amdhsa \
+// RUN: -fcuda-is-device -fnative-half-type \
// RUN: -fnative-half-arguments-and-returns | FileCheck -check-prefixes=FUN,CHECK,SAFEIR %s
-// RUN: %clang_cc1 -x hip %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa \
-// RUN: -fcuda-is-device -target-cpu gfx906 -fnative-half-type \
+// RUN: %clang_cc1 -x hip %s -emit-llvm -o - -triple=amdgpu9.06-amd-amdhsa \
+// RUN: -fcuda-is-device -fnative-half-type \
// RUN: -fnative-half-arguments-and-returns -munsafe-fp-atomics | FileCheck -check-prefixes=FUN,CHECK,UNSAFEIR %s
-// RUN: %clang_cc1 -x hip %s -O3 -S -o - -triple=amdgcn-amd-amdhsa \
-// RUN: -fcuda-is-device -target-cpu gfx1100 -fnative-half-type \
+// RUN: %clang_cc1 -x hip %s -O3 -S -o - -triple=amdgpu11.00-amd-amdhsa \
+// RUN: -fcuda-is-device -fnative-half-type \
// RUN: -fnative-half-arguments-and-returns | FileCheck -check-prefixes=FUN,SAFE %s
-// RUN: %clang_cc1 -x hip %s -O3 -S -o - -triple=amdgcn-amd-amdhsa \
-// RUN: -fcuda-is-device -target-cpu gfx942 -fnative-half-type \
+// RUN: %clang_cc1 -x hip %s -O3 -S -o - -triple=amdgpu9.42-amd-amdhsa \
+// RUN: -fcuda-is-device -fnative-half-type \
// RUN: -fnative-half-arguments-and-returns -munsafe-fp-atomics \
// RUN: | FileCheck -check-prefixes=FUN,UNSAFE %s
diff --git a/clang/test/CodeGenCUDA/atomics-remarks-gfx90a.cu b/clang/test/CodeGenCUDA/atomics-remarks-gfx90a.cu
index 946927d88a1ee..92869a96d6e8c 100644
--- a/clang/test/CodeGenCUDA/atomics-remarks-gfx90a.cu
+++ b/clang/test/CodeGenCUDA/atomics-remarks-gfx90a.cu
@@ -1,5 +1,5 @@
-// RUN: %clang_cc1 %s -triple=amdgcn-amd-amdhsa -fcuda-is-device \
-// RUN: -target-cpu gfx90a -Rpass=atomic-expand -S -o - 2>&1 | \
+// RUN: %clang_cc1 %s -triple=amdgpu9.0a-amd-amdhsa -fcuda-is-device \
+// RUN: -Rpass=atomic-expand -S -o - 2>&1 | \
// RUN: FileCheck %s --check-prefix=GFX90A-CAS
// REQUIRES: amdgpu-registered-target
diff --git a/clang/test/CodeGenCUDA/builtins-amdgcn.cu b/clang/test/CodeGenCUDA/builtins-amdgcn.cu
index 47c6ba57ec2f2..5925b7ab65b01 100644
--- a/clang/test/CodeGenCUDA/builtins-amdgcn.cu
+++ b/clang/test/CodeGenCUDA/builtins-amdgcn.cu
@@ -1,9 +1,9 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx906 -x hip \
+// RUN: %clang_cc1 -triple amdgpu9.06-amd-amdhsa -x hip \
// RUN: -aux-triple x86_64-unknown-linux-gnu -fcuda-is-device -emit-llvm %s \
// RUN: -o - | FileCheck %s
-// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx906 -x hip \
+// RUN: %clang_cc1 -triple amdgpu9.06-amd-amdhsa -x hip \
// RUN: -aux-triple x86_64-pc-windows-msvc -fcuda-is-device -emit-llvm %s \
// RUN: -o - | FileCheck %s
diff --git a/clang/test/CodeGenCUDA/builtins-unsafe-atomics-gfx90a.cu b/clang/test/CodeGenCUDA/builtins-unsafe-atomics-gfx90a.cu
index 03b39cd1291c7..84f313504e63d 100644
--- a/clang/test/CodeGenCUDA/builtins-unsafe-atomics-gfx90a.cu
+++ b/clang/test/CodeGenCUDA/builtins-unsafe-atomics-gfx90a.cu
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx90a -x hip \
+// RUN: %clang_cc1 -triple amdgpu9.0a-amd-amdhsa -x hip \
// RUN: -aux-triple x86_64-unknown-linux-gnu -fcuda-is-device -emit-llvm %s \
// RUN: -o - | FileCheck %s
diff --git a/clang/test/CodeGenCUDA/cluster_dims.cu b/clang/test/CodeGenCUDA/cluster_dims.cu
index 00635e3572a7f..68b514c6a5bc3 100644
--- a/clang/test/CodeGenCUDA/cluster_dims.cu
+++ b/clang/test/CodeGenCUDA/cluster_dims.cu
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx1250 -fcuda-is-device -emit-llvm -x hip -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple amdgpu12.50-amd-amdhsa -fcuda-is-device -emit-llvm -x hip -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -aux-triple amdgcn-amd-amdhsa -emit-llvm -x hip -o - %s | FileCheck --check-prefix=HOST %s
#include "Inputs/cuda.h"
diff --git a/clang/test/CodeGenCUDA/correctly-rounded-div.cu b/clang/test/CodeGenCUDA/correctly-rounded-div.cu
index 9451922060597..058cbce08ba37 100644
--- a/clang/test/CodeGenCUDA/correctly-rounded-div.cu
+++ b/clang/test/CodeGenCUDA/correctly-rounded-div.cu
@@ -1,8 +1,8 @@
-// RUN: %clang_cc1 %s -emit-llvm -o - -triple -amdgcn-amd-amdhsa \
-// RUN: -target-cpu gfx906 -fcuda-is-device -x hip \
+// RUN: %clang_cc1 %s -emit-llvm -o - -triple amdgpu9.06-amd-amdhsa \
+// RUN: -fcuda-is-device -x hip \
// RUN: | FileCheck --check-prefixes=COMMON,CRDIV %s
-// RUN: %clang_cc1 %s -emit-llvm -o - -triple -amdgcn-amd-amdhsa \
-// RUN: -target-cpu gfx906 -fcuda-is-device -x hip \
+// RUN: %clang_cc1 %s -emit-llvm -o - -triple amdgpu9.06-amd-amdhsa \
+// RUN: -fcuda-is-device -x hip \
// RUN: -fno-hip-fp32-correctly-rounded-divide-sqrt \
// RUN: | FileCheck --check-prefixes=COMMON,NCRDIV %s
diff --git a/clang/test/CodeGenCUDA/flush-denormals.cu b/clang/test/CodeGenCUDA/flush-denormals.cu
index c6a4046fdc965..5890ddd3166e1 100644
--- a/clang/test/CodeGenCUDA/flush-denormals.cu
+++ b/clang/test/CodeGenCUDA/flush-denormals.cu
@@ -11,15 +11,15 @@
// RUN: FileCheck -check-prefixes=FTZ,PTXFTZ %s
// RUN: %clang_cc1 -fcuda-is-device -x hip \
-// RUN: -triple amdgcn-amd-amdhsa -target-cpu gfx900 -emit-llvm -o - %s | \
+// RUN: -triple amdgpu9.00-amd-amdhsa -emit-llvm -o - %s | \
// RUN: FileCheck -check-prefix=NOFTZ %s
// RUN: %clang_cc1 -fcuda-is-device -x hip \
-// RUN: -triple amdgcn-amd-amdhsa -target-cpu gfx900 -fdenormal-fp-math-f32=ieee -emit-llvm -o - %s | \
+// RUN: -triple amdgpu9.00-amd-amdhsa -fdenormal-fp-math-f32=ieee -emit-llvm -o - %s | \
// RUN: FileCheck -check-prefix=NOFTZ %s
// RUN: %clang_cc1 -fcuda-is-device -x hip -fdenormal-fp-math-f32=preserve-sign \
-// RUN: -triple amdgcn-amd-amdhsa -target-cpu gfx900 -emit-llvm -o - %s | \
+// RUN: -triple amdgpu9.00-amd-amdhsa -emit-llvm -o - %s | \
// RUN: FileCheck -check-prefix=FTZ %s
#include "Inputs/cuda.h"
diff --git a/clang/test/CodeGenCUDA/fp-contract.cu b/clang/test/CodeGenCUDA/fp-contract.cu
index e5fec7bda1d5d..8e2942fc8104d 100644
--- a/clang/test/CodeGenCUDA/fp-contract.cu
+++ b/clang/test/CodeGenCUDA/fp-contract.cu
@@ -14,23 +14,23 @@
// RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \
// RUN: -disable-llvm-passes -o - %s \
// RUN: | FileCheck -check-prefixes=COMMON,NV-ON %s
-// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -S \
-// RUN: -O1 -target-cpu gfx906 -disable-llvm-passes -o - -x hip %s \
+// RUN: %clang_cc1 -fcuda-is-device -triple amdgpu9.06-amd-amdhsa -S \
+// RUN: -O1 -disable-llvm-passes -o - -x hip %s \
// RUN: | FileCheck -check-prefixes=COMMON,AMD-ON %s
// RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \
// RUN: -O3 -o - %s \
// RUN: | FileCheck -check-prefixes=COMMON,NV-OPT-FAST %s
-// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -S \
-// RUN: -O3 -target-cpu gfx906 -o - -x hip %s \
+// RUN: %clang_cc1 -fcuda-is-device -triple amdgpu9.06-amd-amdhsa -S \
+// RUN: -O3 -o - -x hip %s \
// RUN: | FileCheck -check-prefixes=COMMON,AMD-OPT-FASTSTD %s
// Check separate compile/backend steps corresponding to -save-temps.
-// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -emit-llvm \
-// RUN: -O3 -disable-llvm-passes -target-cpu gfx906 -o %t.ll -x hip %s
+// RUN: %clang_cc1 -fcuda-is-device -triple amdgpu9.06-amd-amdhsa -emit-llvm \
+// RUN: -O3 -disable-llvm-passes -o %t.ll -x hip %s
// RUN: cat %t.ll | FileCheck -check-prefixes=COMMON,AMD-OPT-FAST-IR %s
-// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -S \
-// RUN: -O3 -target-cpu gfx906 -o - -x ir %t.ll \
+// RUN: %clang_cc1 -triple amdgpu9.06-amd-amdhsa -S \
+// RUN: -O3 -o - -x ir %t.ll \
// RUN: | FileCheck -check-prefixes=COMMON,AMD-OPT-FASTSTD %s
// Explicit -ffp-contract=fast
@@ -43,16 +43,16 @@
// RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \
// RUN: -ffp-contract=fast -disable-llvm-passes -o - %s \
// RUN: | FileCheck -check-prefixes=COMMON,NV-ON %s
-// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -S \
-// RUN: -O1 -target-cpu gfx906 -disable-llvm-passes -o - -x hip %s \
+// RUN: %clang_cc1 -fcuda-is-device -triple amdgpu9.06-amd-amdhsa -S \
+// RUN: -O1 -disable-llvm-passes -o - -x hip %s \
// RUN: -ffp-contract=fast \
// RUN: | FileCheck -check-prefixes=COMMON,AMD-ON %s
// RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \
// RUN: -O3 -o - %s \
// RUN: -ffp-contract=fast \
// RUN: | FileCheck -check-prefixes=COMMON,NV-OPT-FAST %s
-// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -S \
-// RUN: -O3 -target-cpu gfx906 -o - -x hip %s \
+// RUN: %clang_cc1 -fcuda-is-device -triple amdgpu9.06-amd-amdhsa -S \
+// RUN: -O3 -o - -x hip %s \
// RUN: -ffp-contract=fast \
// RUN: | FileCheck -check-prefixes=COMMON,AMD-OPT-FAST %s
@@ -60,12 +60,12 @@
// When input is IR, -ffp-contract has no effect. Backend uses default
// default FP fuse option.
-// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -emit-llvm \
+// RUN: %clang_cc1 -fcuda-is-device -triple amdgpu9.06-amd-amdhsa -emit-llvm \
// RUN: -ffp-contract=fast \
-// RUN: -O3 -disable-llvm-passes -target-cpu gfx906 -o %t.ll -x hip %s
+// RUN: -O3 -disable-llvm-passes -o %t.ll -x hip %s
// RUN: cat %t.ll | FileCheck -check-prefixes=COMMON,AMD-OPT-FAST-IR %s
-// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -S \
-// RUN: -O3 -target-cpu gfx906 -o - -x ir %t.ll \
+// RUN: %clang_cc1 -triple amdgpu9.06-amd-amdhsa -S \
+// RUN: -O3 -o - -x ir %t.ll \
// RUN: | FileCheck -check-prefixes=COMMON,AMD-OPT-FASTSTD %s
// Explicit -ffp-contract=fast-honor-pragmas
@@ -78,16 +78,16 @@
// RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \
// RUN: -ffp-contract=fast-honor-pragmas -disable-llvm-passes -o - %s \
// RUN: | FileCheck -check-prefixes=COMMON,NV-ON %s
-// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -S \
-// RUN: -O1 -target-cpu gfx906 -disable-llvm-passes -o - -x hip %s \
+// RUN: %clang_cc1 -fcuda-is-device -triple amdgpu9.06-amd-amdhsa -S \
+// RUN: -O1 -disable-llvm-passes -o - -x hip %s \
// RUN: -ffp-contract=fast-honor-pragmas \
// RUN: | FileCheck -check-prefixes=COMMON,AMD-ON %s
// RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \
// RUN: -O3 -o - %s \
// RUN: -ffp-contract=fast-honor-pragmas \
// RUN: | FileCheck -check-prefixes=COMMON,NV-OPT-FASTSTD %s
-// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -S \
-// RUN: -O3 -target-cpu gfx906 -o - -x hip %s \
+// RUN: %clang_cc1 -fcuda-is-device -triple amdgpu9.06-amd-amdhsa -S \
+// RUN: -O3 -o - -x hip %s \
// RUN: -ffp-contract=fast-honor-pragmas \
// RUN: | FileCheck -check-prefixes=COMMON,AMD-OPT-FASTSTD %s
@@ -95,12 +95,12 @@
// When input is IR, -ffp-contract has no effect. Backend uses default
// default FP fuse option.
-// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -emit-llvm \
+// RUN: %clang_cc1 -fcuda-is-device -triple amdgpu9.06-amd-amdhsa -emit-llvm \
// RUN: -ffp-contract=fast-honor-pragmas \
-// RUN: -O3 -disable-llvm-passes -target-cpu gfx906 -o %t.ll -x hip %s
+// RUN: -O3 -disable-llvm-passes -o %t.ll -x hip %s
// RUN: cat %t.ll | FileCheck -check-prefixes=COMMON,AMD-OPT-FAST-IR %s
-// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -S \
-// RUN: -O3 -target-cpu gfx906 -o - -x ir %t.ll \
+// RUN: %clang_cc1 -triple amdgpu9.06-amd-amdhsa -S \
+// RUN: -O3 -o - -x ir %t.ll \
// RUN: | FileCheck -check-prefixes=COMMON,AMD-OPT-FASTSTD %s
// Explicit -ffp-contract=on -- fusing by front-end.
@@ -116,27 +116,27 @@
// RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \
// RUN: -ffp-contract=on -disable-llvm-passes -o - %s \
// RUN: | FileCheck -check-prefixes=COMMON,NV-ON %s
-// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -S \
-// RUN: -O1 -target-cpu gfx906 -disable-llvm-passes -o - -x hip %s \
+// RUN: %clang_cc1 -fcuda-is-device -triple amdgpu9.06-amd-amdhsa -S \
+// RUN: -O1 -disable-llvm-passes -o - -x hip %s \
// RUN: -ffp-contract=on \
// RUN: | FileCheck -check-prefixes=COMMON,AMD-ON %s
// RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \
// RUN: -O3 -o - %s \
// RUN: -ffp-contract=on \
// RUN: | FileCheck -check-prefixes=COMMON,NV-OPT-ON %s
-// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -S \
-// RUN: -O3 -target-cpu gfx906 -o - -x hip %s \
+// RUN: %clang_cc1 -fcuda-is-device -triple amdgpu9.06-amd-amdhsa -S \
+// RUN: -O3 -o - -x hip %s \
// RUN: -ffp-contract=on \
// RUN: | FileCheck -check-prefixes=COMMON,AMD-OPT-ON %s
// Check separate compile/backend steps corresponding to -save-temps.
-// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -emit-llvm \
+// RUN: %clang_cc1 -fcuda-is-device -triple amdgpu9.06-amd-amdhsa -emit-llvm \
// RUN: -ffp-contract=on \
-// RUN: -O3 -disable-llvm-passes -target-cpu gfx906 -o %t.ll -x hip %s
+// RUN: -O3 -disable-llvm-passes -o %t.ll -x hip %s
// RUN: cat %t.ll | FileCheck -check-prefixes=COMMON,AMD-OPT-ON-IR %s
-// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -S \
-// RUN: -O3 -target-cpu gfx906 -o - -x ir %t.ll \
+// RUN: %clang_cc1 -triple amdgpu9.06-amd-amdhsa -S \
+// RUN: -O3 -o - -x ir %t.ll \
// RUN: | FileCheck -check-prefixes=COMMON,AMD-OPT-ON %s
// Explicit -ffp-contract=off should disable instruction fusing.
@@ -149,27 +149,27 @@
// RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \
// RUN: -ffp-contract=off -disable-llvm-passes -o - %s \
// RUN: | FileCheck -check-prefixes=COMMON,NV-OFF %s
-// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -S \
-// RUN: -target-cpu gfx906 -disable-llvm-passes -o - -x hip %s \
+// RUN: %clang_cc1 -fcuda-is-device -triple amdgpu9.06-amd-amdhsa -S \
+// RUN: -disable-llvm-passes -o - -x hip %s \
// RUN: -ffp-contract=off \
// RUN: | FileCheck -check-prefixes=COMMON,AMD-OFF %s
// RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \
// RUN: -O3 -o - %s \
// RUN: -ffp-contract=off \
// RUN: | FileCheck -check-prefixes=COMMON,NV-OPT-OFF %s
-// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -S \
-// RUN: -O3 -target-cpu gfx906 -o - -x hip %s \
+// RUN: %clang_cc1 -fcuda-is-device -triple amdgpu9.06-amd-amdhsa -S \
+// RUN: -O3 -o - -x hip %s \
// RUN: -ffp-contract=off \
// RUN: | FileCheck -check-prefixes=COMMON,AMD-OPT-OFF %s
// Check separate compile/backend steps corresponding to -save-temps.
-// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -emit-llvm \
+// RUN: %clang_cc1 -fcuda-is-device -triple amdgpu9.06-amd-amdhsa -emit-llvm \
// RUN: -ffp-contract=off \
-// RUN: -O3 -disable-llvm-passes -target-cpu gfx906 -o %t.ll -x hip %s
+// RUN: -O3 -disable-llvm-passes -o %t.ll -x hip %s
// RUN: cat %t.ll | FileCheck -check-prefixes=COMMON,AMD-OPT-OFF-IR %s
-// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -S \
-// RUN: -O3 -target-cpu gfx906 -o - -x ir %t.ll \
+// RUN: %clang_cc1 -triple amdgpu9.06-amd-amdhsa -S \
+// RUN: -O3 -o - -x ir %t.ll \
// RUN: | FileCheck -check-prefixes=COMMON,AMD-OPT-OFF %s
#include "Inputs/cuda.h"
diff --git a/clang/test/CodeGenCUDA/host-used-extern-determinism.cu b/clang/test/CodeGenCUDA/host-used-extern-determinism.cu
index 1e52887b894b1..faaac540b8ec4 100644
--- a/clang/test/CodeGenCUDA/host-used-extern-determinism.cu
+++ b/clang/test/CodeGenCUDA/host-used-extern-determinism.cu
@@ -1,5 +1,5 @@
-// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -fcuda-is-device -x hip %s \
-// RUN: -fgpu-rdc -std=c++11 -emit-llvm -o - -target-cpu gfx906 | FileCheck %s
+// RUN: %clang_cc1 -triple amdgpu9.06-amd-amdhsa -fcuda-is-device -x hip %s \
+// RUN: -fgpu-rdc -std=c++11 -emit-llvm -o - | FileCheck %s
#include "Inputs/cuda.h"
diff --git a/clang/test/CodeGenCUDA/host-used-extern.cu b/clang/test/CodeGenCUDA/host-used-extern.cu
index 1ae644ae981aa..2eeb84435e2b4 100644
--- a/clang/test/CodeGenCUDA/host-used-extern.cu
+++ b/clang/test/CodeGenCUDA/host-used-extern.cu
@@ -1,12 +1,12 @@
-// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -fcuda-is-device -x hip %s \
-// RUN: -fgpu-rdc -std=c++11 -emit-llvm -o - -target-cpu gfx906 | FileCheck %s
+// RUN: %clang_cc1 -triple amdgpu9.06-amd-amdhsa -fcuda-is-device -x hip %s \
+// RUN: -fgpu-rdc -std=c++11 -emit-llvm -o - | FileCheck %s
-// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -fcuda-is-device -x hip %s \
-// RUN: -fgpu-rdc -std=c++11 -emit-llvm -o - -target-cpu gfx906 \
+// RUN: %clang_cc1 -triple amdgpu9.06-amd-amdhsa -fcuda-is-device -x hip %s \
+// RUN: -fgpu-rdc -std=c++11 -emit-llvm -o - \
// RUN: | FileCheck -check-prefix=NEG %s
-// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -fcuda-is-device -x hip %s \
-// RUN: -std=c++11 -emit-llvm -o - -target-cpu gfx906 \
+// RUN: %clang_cc1 -triple amdgpu9.06-amd-amdhsa -fcuda-is-device -x hip %s \
+// RUN: -std=c++11 -emit-llvm -o - \
// RUN: | FileCheck -check-prefixes=NEG,NORDC %s
// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -x hip %s \
diff --git a/clang/test/CodeGenCUDA/implicit-host-device-fun.cu b/clang/test/CodeGenCUDA/implicit-host-device-fun.cu
index 19c13b38b5096..d0916053d7112 100644
--- a/clang/test/CodeGenCUDA/implicit-host-device-fun.cu
+++ b/clang/test/CodeGenCUDA/implicit-host-device-fun.cu
@@ -2,13 +2,13 @@
// RUN: -foffload-implicit-host-device-templates \
// RUN: -emit-llvm -o - -x hip %s 2>&1 | \
// RUN: FileCheck -check-prefixes=COMM,HOST %s
-// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -fcuda-is-device \
-// RUN: -target-cpu gfx1100 \
+// RUN: %clang_cc1 -triple amdgpu11.00-amd-amdhsa -fcuda-is-device \
+// RUN: \
// RUN: -foffload-implicit-host-device-templates \
// RUN: -emit-llvm -o - -x hip %s 2>&1 | \
// RUN: FileCheck -check-prefixes=COMM,DEV %s
-// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -fcuda-is-device \
-// RUN: -target-cpu gfx1100 \
+// RUN: %clang_cc1 -triple amdgpu11.00-amd-amdhsa -fcuda-is-device \
+// RUN: \
// RUN: -foffload-implicit-host-device-templates \
// RUN: -emit-llvm -o - -x hip %s 2>&1 | \
// RUN: FileCheck -check-prefixes=DEV-NEG %s
diff --git a/clang/test/CodeGenCUDA/increment-index-for-thunks.cu b/clang/test/CodeGenCUDA/increment-index-for-thunks.cu
index 48dbf6ef82b7d..9988ac63d9435 100644
--- a/clang/test/CodeGenCUDA/increment-index-for-thunks.cu
+++ b/clang/test/CodeGenCUDA/increment-index-for-thunks.cu
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -target-cpu gfx942 \
+// RUN: %clang_cc1 -fcuda-is-device -triple amdgpu9.42-amd-amdhsa \
// RUN: -emit-llvm -xhip %s -o - | FileCheck %s --check-prefix=GCN
// RUN: %clang_cc1 -fcuda-is-device -triple spirv64-amd-amdhsa \
// RUN: -emit-llvm -xhip %s -o - | FileCheck %s --check-prefix=SPIRV
diff --git a/clang/test/CodeGenCUDA/long-double.cu b/clang/test/CodeGenCUDA/long-double.cu
index 2e669ad7de8f8..b4116c0b81594 100644
--- a/clang/test/CodeGenCUDA/long-double.cu
+++ b/clang/test/CodeGenCUDA/long-double.cu
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx906 \
+// RUN: %clang_cc1 -triple amdgpu9.06-amd-amdhsa \
// RUN: -aux-triple x86_64-unknown-gnu-linux -fcuda-is-device \
// RUN: -emit-llvm -o - -x hip %s 2>&1 | FileCheck %s
diff --git a/clang/test/CodeGenCUDA/record-layout.cu b/clang/test/CodeGenCUDA/record-layout.cu
index 4e27321452ee7..1f4dd4bcd9ed2 100644
--- a/clang/test/CodeGenCUDA/record-layout.cu
+++ b/clang/test/CodeGenCUDA/record-layout.cu
@@ -1,7 +1,7 @@
// RUN: %clang_cc1 -triple x86_64-pc-windows-msvc -fdump-record-layouts \
// RUN: -emit-llvm -o %t -xhip %s 2>&1 | FileCheck %s --check-prefix=AST
// RUN: cat %t | FileCheck --check-prefixes=CHECK,HOST %s
-// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -target-cpu gfx1100 \
+// RUN: %clang_cc1 -fcuda-is-device -triple amdgpu11.00-amd-amdhsa \
// RUN: -emit-llvm -fdump-record-layouts -aux-triple x86_64-pc-windows-msvc \
// RUN: -o %t -xhip %s | FileCheck %s --check-prefix=AST
// RUN: cat %t | FileCheck --check-prefixes=CHECK,DEV %s
diff --git a/clang/test/CodeGenCUDA/struct-mangling-number.cu b/clang/test/CodeGenCUDA/struct-mangling-number.cu
index e9e80671c28c0..f5d7e3008eb28 100644
--- a/clang/test/CodeGenCUDA/struct-mangling-number.cu
+++ b/clang/test/CodeGenCUDA/struct-mangling-number.cu
@@ -1,6 +1,6 @@
// RUN: %clang_cc1 -emit-llvm -o - -aux-triple x86_64-pc-windows-msvc \
-// RUN: -fms-extensions -triple amdgcn-amd-amdhsa \
-// RUN: -target-cpu gfx1030 -fcuda-is-device -x hip %s \
+// RUN: -fms-extensions -triple amdgpu10.30-amd-amdhsa \
+// RUN: -fcuda-is-device -x hip %s \
// RUN: | FileCheck -check-prefix=DEV %s
// RUN: %clang_cc1 -emit-llvm -o - -triple x86_64-pc-windows-msvc \
diff --git a/clang/test/CodeGenCUDA/unused-global-var.cu b/clang/test/CodeGenCUDA/unused-global-var.cu
index c091e83eda70a..47fab27bb0cad 100644
--- a/clang/test/CodeGenCUDA/unused-global-var.cu
+++ b/clang/test/CodeGenCUDA/unused-global-var.cu
@@ -1,10 +1,10 @@
// REQUIRES: amdgpu-registered-target
-// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -fcuda-is-device -x hip %s \
+// RUN: %clang_cc1 -triple amdgpu9.06-amd-amdhsa -fcuda-is-device -x hip %s \
// RUN: -std=c++11 -O3 -mllvm -amdgpu-internalize-symbols -emit-llvm -o - \
-// RUN: -target-cpu gfx906 | FileCheck %s
-// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -fcuda-is-device -x hip %s \
+// RUN: | FileCheck %s
+// RUN: %clang_cc1 -triple amdgpu9.06-amd-amdhsa -fcuda-is-device -x hip %s \
// RUN: -std=c++11 -O3 -mllvm -amdgpu-internalize-symbols -emit-llvm -o - \
-// RUN: -target-cpu gfx906 | FileCheck -check-prefix=NEGCHK %s
+// RUN: | FileCheck -check-prefix=NEGCHK %s
#include "Inputs/cuda.h"
diff --git a/clang/test/CodeGenCUDA/vtbl.cu b/clang/test/CodeGenCUDA/vtbl.cu
index 4c3bb8436c49f..d535d976ae2de 100644
--- a/clang/test/CodeGenCUDA/vtbl.cu
+++ b/clang/test/CodeGenCUDA/vtbl.cu
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -target-cpu gfx906 \
+// RUN: %clang_cc1 -fcuda-is-device -triple amdgpu9.06-amd-amdhsa \
// RUN: -emit-llvm -o - %s | FileCheck %s
#include "Inputs/cuda.h"
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