[clang] [llvm] [mlir] [IR] Make semantics of strictfp consistent v2 (PR #211769)
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Fri Jul 24 04:25:18 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-powerpc
Author: Ramkumar Ramachandra (artagnon)
<details>
<summary>Changes</summary>
Changes: The patch was originally landed as af0c933e (#<!-- -->209465), but there was an issue with strictfp functions being inlined into non-strictfp functions. The issue has since been resolved by a2b42b10a ([IR] Reject inlining strictfp alwaysinline callee into non-strictfp caller, #<!-- -->210701) and the re-land is identical.
Although the section on constrainedfp in the LangRef clearly states "All function definitions that use constrained floating point intrinsics must have the strictfp attribute", indicating that a function with strictfp calls must be marked with strictfp, the general description of strictfp does not specify this. Refine its semantics and make it so, eliminating the inconsistency.
---
Patch is 49.67 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/211769.diff
23 Files Affected:
- (modified) clang/lib/CodeGen/TargetInfo.cpp (+3)
- (modified) clang/test/CodeGenOpenCL/cl20-device-side-enqueue-attributes.cl (+2-2)
- (modified) llvm/docs/LangRef.md (+2-4)
- (modified) llvm/include/llvm/IR/Function.h (+3)
- (modified) llvm/lib/IR/Verifier.cpp (+5)
- (modified) llvm/test/CodeGen/AArch64/is_fpclass.ll (+2-2)
- (modified) llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions1.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-fp-to-int.ll (+2-2)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-int-to-fp.ll (+2-2)
- (modified) llvm/test/CodeGen/PowerPC/milicode32.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll (+2-14)
- (modified) llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll (+1-1)
- (modified) llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll (+1-1)
- (modified) llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll (+1-1)
- (modified) llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll (+1-1)
- (modified) llvm/test/CodeGen/SPIRV/llvm-intrinsics/constrained-fmuladd.ll (+6-6)
- (modified) llvm/test/Transforms/EarlyCSE/replace-calls-def-attrs.ll (+35-32)
- (modified) llvm/test/Transforms/InstCombine/erf.ll (+22-18)
- (modified) llvm/test/Transforms/InstCombine/fdim.ll (+4-3)
- (modified) llvm/test/Transforms/InstSimplify/disable_folding.ll (+8-6)
- (modified) llvm/test/Transforms/SimplifyCFG/X86/merge-compatible-invokes-of-landingpad.ll (+16-14)
- (modified) llvm/unittests/IR/VerifierTest.cpp (+24)
- (modified) mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir (+25-25)
``````````diff
diff --git a/clang/lib/CodeGen/TargetInfo.cpp b/clang/lib/CodeGen/TargetInfo.cpp
index 641caf6d5cd4b..2f89154c2d2d9 100644
--- a/clang/lib/CodeGen/TargetInfo.cpp
+++ b/clang/lib/CodeGen/TargetInfo.cpp
@@ -195,6 +195,9 @@ llvm::Value *TargetCodeGenInfo::createEnqueuedBlockKernel(
CGF.CGM.addDefaultFunctionDefinitionAttributes(KernelAttrs);
F->addFnAttrs(KernelAttrs);
+ if (CGF.Builder.getIsFPConstrained())
+ F->addFnAttr(llvm::Attribute::StrictFP);
+
auto IP = CGF.Builder.saveIP();
auto *BB = llvm::BasicBlock::Create(C, "entry", F);
auto &Builder = CGF.Builder;
diff --git a/clang/test/CodeGenOpenCL/cl20-device-side-enqueue-attributes.cl b/clang/test/CodeGenOpenCL/cl20-device-side-enqueue-attributes.cl
index 962ac4afa4991..c93f623016660 100644
--- a/clang/test/CodeGenOpenCL/cl20-device-side-enqueue-attributes.cl
+++ b/clang/test/CodeGenOpenCL/cl20-device-side-enqueue-attributes.cl
@@ -188,7 +188,7 @@ kernel void device_side_enqueue(global float *a, global float *b, int i) {
// STRICTFP-NEXT: ret void
//
//
-// STRICTFP: Function Attrs: convergent nounwind
+// STRICTFP: Function Attrs: convergent nounwind strictfp
// STRICTFP-LABEL: define spir_kernel void @__device_side_enqueue_block_invoke_kernel(
// STRICTFP-SAME: ptr addrspace(4) [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] {
// STRICTFP-NEXT: [[ENTRY:.*:]]
@@ -207,7 +207,7 @@ kernel void device_side_enqueue(global float *a, global float *b, int i) {
// STRICTFP: attributes #[[ATTR1:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
// STRICTFP: attributes #[[ATTR2]] = { convergent noinline nounwind optnone strictfp "stack-protector-buffer-size"="8" }
// STRICTFP: attributes #[[ATTR3:[0-9]+]] = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) }
-// STRICTFP: attributes #[[ATTR4]] = { convergent nounwind "stack-protector-buffer-size"="8" }
+// STRICTFP: attributes #[[ATTR4]] = { convergent nounwind strictfp "stack-protector-buffer-size"="8" }
// STRICTFP: attributes #[[ATTR5]] = { convergent nounwind strictfp }
// STRICTFP: attributes #[[ATTR6]] = { strictfp }
//.
diff --git a/llvm/docs/LangRef.md b/llvm/docs/LangRef.md
index d6477b61bcb0e..ed46430ae979b 100644
--- a/llvm/docs/LangRef.md
+++ b/llvm/docs/LangRef.md
@@ -2800,7 +2800,8 @@ fn -> other_fn -> other_fn ; fn is norecurse
optimizations that require assumptions about the floating-point rounding
mode or that might alter the state of floating-point status flags that
might otherwise be set or cleared by calling this function. LLVM will
- not introduce any new floating-point instructions that may trap.
+ not introduce any new floating-point instructions that may trap. All
+ function definitions that contain strictfp calls must be marked strictfp.
(denormal_fpenv)=
@@ -26632,9 +26633,6 @@ point intrinsics must have the `strictfp` attribute either on the
calling instruction or on the declaration or definition of the function
being called.
-All function *definitions* that use constrained floating point intrinsics
-must have the `strictfp` attribute.
-
#### '`llvm.experimental.constrained.fadd`' Intrinsic
##### Syntax:
diff --git a/llvm/include/llvm/IR/Function.h b/llvm/include/llvm/IR/Function.h
index bd28f0d9902da..0238c9b352f5f 100644
--- a/llvm/include/llvm/IR/Function.h
+++ b/llvm/include/llvm/IR/Function.h
@@ -632,6 +632,9 @@ class LLVM_ABI Function : public GlobalObject, public ilist_node<Function> {
addFnAttr(Attribute::NoRecurse);
}
+ /// Determine if the function has strict floating point sematics.
+ bool isStrictFP() const { return hasFnAttribute(Attribute::StrictFP); }
+
/// Determine if the function is required to make forward progress.
bool mustProgress() const {
return hasFnAttribute(Attribute::MustProgress) ||
diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
index c663b1ec440ea..a7682ee246fe0 100644
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -3897,6 +3897,11 @@ void Verifier::visitCallBase(CallBase &Call) {
Check(!Attrs.hasFnAttr(Attribute::DenormalFPEnv),
"denormal_fpenv attribute may not apply to call sites", Call);
+ Check(!Attrs.hasFnAttr(Attribute::StrictFP) ||
+ Call.getFunction()->isStrictFP(),
+ "call site marked strictfp without caller function marked strictfp",
+ Call);
+
// Verify call attributes.
verifyFunctionAttrs(FTy, Attrs, &Call, IsIntrinsic, Call.isInlineAsm());
diff --git a/llvm/test/CodeGen/AArch64/is_fpclass.ll b/llvm/test/CodeGen/AArch64/is_fpclass.ll
index 71a8f42a7b4db..19ce95641fe98 100644
--- a/llvm/test/CodeGen/AArch64/is_fpclass.ll
+++ b/llvm/test/CodeGen/AArch64/is_fpclass.ll
@@ -249,7 +249,7 @@ entry:
ret i1 %0
}
-define i1 @isfinite_d_strictfp(double %x) {
+define i1 @isfinite_d_strictfp(double %x) strictfp {
; CHECK-SD-LABEL: isfinite_d_strictfp:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: fmov x8, d0
@@ -278,7 +278,7 @@ entry:
ret i1 %0
}
-define i1 @not_isfinite_d_strictfp(double %x) {
+define i1 @not_isfinite_d_strictfp(double %x) strictfp {
; CHECK-SD-LABEL: not_isfinite_d_strictfp:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: fmov x8, d0
diff --git a/llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions1.mir b/llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions1.mir
index 878f7b782a9a1..4d3552a056df5 100644
--- a/llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions1.mir
+++ b/llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions1.mir
@@ -23,7 +23,7 @@
--- |
@x = dso_local global i32 0, align 4
- define dso_local void @f(ptr nocapture noundef writeonly %a, float noundef %y, i32 noundef %n) {
+ define dso_local void @f(ptr nocapture noundef writeonly %a, float noundef %y, i32 noundef %n) #2 {
entry:
%cmp6 = icmp sgt i32 %n, 0
br i1 %cmp6, label %for.body.preheader, label %for.cond.cleanup
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-fp-to-int.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-fp-to-int.ll
index cfdc1baf8c282..9320908403679 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-fp-to-int.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-fp-to-int.ll
@@ -209,7 +209,7 @@ define i64 @f64_to_u64(double %x) {
ret i64 %cvt
}
-define i32 @strict_convert_signed(double %x) {
+define i32 @strict_convert_signed(double %x) #0 {
; CHECK-LABEL: strict_convert_signed:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtzs w0, d0
@@ -224,7 +224,7 @@ define i32 @strict_convert_signed(double %x) {
ret i32 %cvt
}
-define i32 @strict_convert_unsigned(float %x) {
+define i32 @strict_convert_unsigned(float %x) #0 {
; CHECK-LABEL: strict_convert_unsigned:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtzu w0, s0
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-int-to-fp.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-int-to-fp.ll
index 83403fc4ad86f..9e96355fd598d 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-int-to-fp.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-cvt-int-to-fp.ll
@@ -209,7 +209,7 @@ entry:
ret double %cvt
}
-define float @strict_convert_signed(i32 %x) {
+define float @strict_convert_signed(i32 %x) #0 {
; CHECK-LABEL: strict_convert_signed:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: scvtf s0, w0
@@ -224,7 +224,7 @@ entry:
ret float %cvt
}
-define float @strict_convert_unsigned(i64 %x) {
+define float @strict_convert_unsigned(i64 %x) #0 {
; CHECK-LABEL: strict_convert_unsigned:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ucvtf s0, x0
diff --git a/llvm/test/CodeGen/PowerPC/milicode32.ll b/llvm/test/CodeGen/PowerPC/milicode32.ll
index 2c7e5c9867137..f2caec7e0045f 100644
--- a/llvm/test/CodeGen/PowerPC/milicode32.ll
+++ b/llvm/test/CodeGen/PowerPC/milicode32.ll
@@ -68,7 +68,7 @@ entry:
ret i32 %call
}
-define i32 @strlen_test_fp_strict(ptr noundef %str) nounwind {
+define i32 @strlen_test_fp_strict(ptr noundef %str) strictfp nounwind {
; CHECK-AIX-32-P9-LABEL: strlen_test_fp_strict:
; CHECK-AIX-32-P9: # %bb.0: # %entry
; CHECK-AIX-32-P9-NEXT: mflr r0
diff --git a/llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll b/llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll
index c1ee436a40c55..756cc6dc9408c 100644
--- a/llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll
+++ b/llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll
@@ -1972,14 +1972,12 @@ entry:
ret ppc_fp128 %conv
}
-define i1 @ppcq_to_s1(ppc_fp128 %a) {
+define i1 @ppcq_to_s1(ppc_fp128 %a) #0 {
; PC64LE-LABEL: ppcq_to_s1:
; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
-; PC64LE-NEXT: .cfi_def_cfa_offset 32
-; PC64LE-NEXT: .cfi_offset lr, 16
; PC64LE-NEXT: bl __gcc_qtou
; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32
@@ -1992,8 +1990,6 @@ define i1 @ppcq_to_s1(ppc_fp128 %a) {
; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
-; PC64LE9-NEXT: .cfi_def_cfa_offset 32
-; PC64LE9-NEXT: .cfi_offset lr, 16
; PC64LE9-NEXT: bl __gcc_qtou
; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32
@@ -2006,8 +2002,6 @@ define i1 @ppcq_to_s1(ppc_fp128 %a) {
; PC64-NEXT: mflr 0
; PC64-NEXT: stdu 1, -112(1)
; PC64-NEXT: std 0, 128(1)
-; PC64-NEXT: .cfi_def_cfa_offset 112
-; PC64-NEXT: .cfi_offset lr, 16
; PC64-NEXT: bl __gcc_qtou
; PC64-NEXT: nop
; PC64-NEXT: addi 1, 1, 112
@@ -2019,14 +2013,12 @@ entry:
ret i1 %conv
}
-define i1 @ppcq_to_u1(ppc_fp128 %a) {
+define i1 @ppcq_to_u1(ppc_fp128 %a) #0 {
; PC64LE-LABEL: ppcq_to_u1:
; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: mflr 0
; PC64LE-NEXT: stdu 1, -32(1)
; PC64LE-NEXT: std 0, 48(1)
-; PC64LE-NEXT: .cfi_def_cfa_offset 32
-; PC64LE-NEXT: .cfi_offset lr, 16
; PC64LE-NEXT: bl __fixunstfsi
; PC64LE-NEXT: nop
; PC64LE-NEXT: addi 1, 1, 32
@@ -2039,8 +2031,6 @@ define i1 @ppcq_to_u1(ppc_fp128 %a) {
; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: stdu 1, -32(1)
; PC64LE9-NEXT: std 0, 48(1)
-; PC64LE9-NEXT: .cfi_def_cfa_offset 32
-; PC64LE9-NEXT: .cfi_offset lr, 16
; PC64LE9-NEXT: bl __fixunstfsi
; PC64LE9-NEXT: nop
; PC64LE9-NEXT: addi 1, 1, 32
@@ -2053,8 +2043,6 @@ define i1 @ppcq_to_u1(ppc_fp128 %a) {
; PC64-NEXT: mflr 0
; PC64-NEXT: stdu 1, -112(1)
; PC64-NEXT: std 0, 128(1)
-; PC64-NEXT: .cfi_def_cfa_offset 112
-; PC64-NEXT: .cfi_offset lr, 16
; PC64-NEXT: bl __fixunstfsi
; PC64-NEXT: nop
; PC64-NEXT: addi 1, 1, 112
diff --git a/llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll b/llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
index 53fcfa19725db..654d99948bd40 100644
--- a/llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
+++ b/llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
@@ -1989,7 +1989,7 @@ define i64 @llround_f64(double %a) nounwind strictfp {
ret i64 %1
}
-define double @ldexp_f64(double %x, i32 signext %y) nounwind {
+define double @ldexp_f64(double %x, i32 signext %y) nounwind strictfp {
; RV32IFD-LABEL: ldexp_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
diff --git a/llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll b/llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll
index 3a4acfd8a41ee..b22661976e727 100644
--- a/llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll
+++ b/llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll
@@ -1955,7 +1955,7 @@ define i64 @llround_f32(float %a) nounwind strictfp {
ret i64 %1
}
-define float @ldexp_f32(float %x, i32 signext %y) nounwind {
+define float @ldexp_f32(float %x, i32 signext %y) nounwind strictfp {
; RV32IF-LABEL: ldexp_f32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16
diff --git a/llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll b/llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll
index eb1848965a9ba..c876b76b8f0d9 100644
--- a/llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll
+++ b/llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll
@@ -714,7 +714,7 @@ define i64 @llround_f16(half %a) nounwind strictfp {
ret i64 %1
}
-define half @ldexp_f16(half %x, i32 signext %y) nounwind {
+define half @ldexp_f16(half %x, i32 signext %y) nounwind strictfp {
; RV32IZFH-LABEL: ldexp_f16:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16
diff --git a/llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll b/llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll
index 0529819a4f4e2..891ffa0a0c96b 100644
--- a/llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll
+++ b/llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll
@@ -744,7 +744,7 @@ define i64 @llround_f16(half %a) nounwind strictfp {
ret i64 %1
}
-define half @ldexp_f16(half %x, i32 signext %y) nounwind {
+define half @ldexp_f16(half %x, i32 signext %y) nounwind strictfp {
; RV32IZFHMIN-LABEL: ldexp_f16:
; RV32IZFHMIN: # %bb.0:
; RV32IZFHMIN-NEXT: addi sp, sp, -16
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/constrained-fmuladd.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/constrained-fmuladd.ll
index b2d4f570afbd9..67eed241354d2 100644
--- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/constrained-fmuladd.ll
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/constrained-fmuladd.ll
@@ -10,7 +10,7 @@
; CHECK: OpFMul %[[#]] %[[#]] %[[#]]
; CHECK: OpFAdd %[[#]] %[[#]] %[[#]]
-define spir_kernel void @test_f32(float %a) {
+define spir_kernel void @test_f32(float %a) strictfp {
entry:
%r = tail call float @llvm.experimental.constrained.fmuladd.f32(
float %a, float %a, float %a,
@@ -18,9 +18,9 @@ entry:
ret void
}
-; CHECK: OpFMul %[[#]] %[[#]] %[[#]]
+; CHECK: OpFMul %[[#]] %[[#]] %[[#]]
; CHECK: OpFAdd %[[#]] %[[#]] %[[#]]
-define spir_kernel void @test_f64(double %a) {
+define spir_kernel void @test_f64(double %a) strictfp {
entry:
%r = tail call double @llvm.experimental.constrained.fmuladd.f64(
double %a, double %a, double %a,
@@ -30,7 +30,7 @@ entry:
; CHECK: OpFMul %[[#]] %[[#]] %[[#]]
; CHECK: OpFAdd %[[#]] %[[#]] %[[#]]
-define spir_kernel void @test_v2f32(<2 x float> %a) {
+define spir_kernel void @test_v2f32(<2 x float> %a) strictfp {
entry:
%r = tail call <2 x float> @llvm.experimental.constrained.fmuladd.v2f32(
<2 x float> %a, <2 x float> %a, <2 x float> %a,
@@ -40,7 +40,7 @@ entry:
; CHECK: OpFMul %[[#]] %[[#]] %[[#]]
; CHECK: OpFAdd %[[#]] %[[#]] %[[#]]
-define spir_kernel void @test_v4f32(<4 x float> %a) {
+define spir_kernel void @test_v4f32(<4 x float> %a) strictfp {
entry:
%r = tail call <4 x float> @llvm.experimental.constrained.fmuladd.v4f32(
<4 x float> %a, <4 x float> %a, <4 x float> %a,
@@ -50,7 +50,7 @@ entry:
; CHECK: OpFMul %[[#]] %[[#]] %[[#]]
; CHECK: OpFAdd %[[#]] %[[#]] %[[#]]
-define spir_kernel void @test_v2f64(<2 x double> %a) {
+define spir_kernel void @test_v2f64(<2 x double> %a) strictfp {
entry:
%r = tail call <2 x double> @llvm.experimental.constrained.fmuladd.v2f64(
<2 x double> %a, <2 x double> %a, <2 x double> %a,
diff --git a/llvm/test/Transforms/EarlyCSE/replace-calls-def-attrs.ll b/llvm/test/Transforms/EarlyCSE/replace-calls-def-attrs.ll
index 1dbffd962a638..b8854e3061dbf 100644
--- a/llvm/test/Transforms/EarlyCSE/replace-calls-def-attrs.ll
+++ b/llvm/test/Transforms/EarlyCSE/replace-calls-def-attrs.ll
@@ -13,7 +13,7 @@ declare i8 @buz.fp(float, float)
define i8 @same_parent_combine_diff_attrs(i8 %x, i8 %y) {
; CHECK-LABEL: define i8 @same_parent_combine_diff_attrs(
; CHECK-SAME: i8 [[X:%.*]], i8 [[Y:%.*]]) {
-; CHECK-NEXT: [[C1:%.*]] = call i8 @baz(i8 [[X]], i8 noundef [[Y]]) #[[ATTR1:[0-9]+]]
+; CHECK-NEXT: [[C1:%.*]] = call i8 @baz(i8 [[X]], i8 noundef [[Y]]) #[[ATTR2:[0-9]+]]
; CHECK-NEXT: [[R:%.*]] = call i8 @buz(i8 [[C1]], i8 [[C1]])
; CHECK-NEXT: ret i8 [[R]]
;
@@ -27,7 +27,7 @@ define i8 @same_parent_combine_diff_attrs(i8 %x, i8 %y) {
define i8 @same_parent_combine_diff_attrs_needs_intersect(i8 %x, i8 %y) {
; CHECK-LABEL: define i8 @same_parent_combine_diff_attrs_needs_intersect(
; CHECK-SAME: i8 [[X:%.*]], i8 [[Y:%.*]]) {
-; CHECK-NEXT: [[C1:%.*]] = call ptr @baz.ptr(i8 [[X]], i8 noundef [[Y]]) #[[ATTR1]]
+; CHECK-NEXT: [[C1:%.*]] = call ptr @baz.ptr(i8 [[X]], i8 noundef [[Y]]) #[[ATTR2]]
; CHECK-NEXT: [[R:%.*]] = call i8 @buz.ptr(ptr [[C1]], ptr [[C1]])
; CHECK-NEXT: ret i8 [[R]]
;
@@ -41,7 +41,7 @@ define i8 @same_parent_combine_diff_attrs_needs_intersect(i8 %x, i8 %y) {
define i8 @same_parent_combine_diff_attrs_fmf(float %x, float %y) {
; CHECK-LABEL: define i8 @same_parent_combine_diff_attrs_fmf(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: [[C1:%.*]] = call nnan float @baz.fp(float [[X]], float noundef [[Y]]) #[[ATTR2:[0-9]+]]
+; CHECK-NEXT: [[C1:%.*]] = call nnan float @baz.fp(float [[X]], float noundef [[Y]]) #[[ATTR3:[0-9]+]]
; CHECK-NEXT: [[R:%.*]] = call i8 @buz.fp(float [[C1]], float [[C1]])
; CHECK-NEXT: ret i8 [[R]]
;
@@ -55,7 +55,7 @@ define i8 @same_parent_combine_diff_attrs_fmf(float %x, float %y) {
define i8 @same_parent_combine_diff_attrs_fmf2(float %x, float %y) {
; CHECK-LABEL: define i8 @same_parent_combine_diff_attrs_fmf2(
; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: [[C1:%.*]] = call nnan float @baz.fp(float [[X]], float noundef [[Y]]) #[[ATTR1]]
+; CHECK-NEXT: [[C1:%.*]] = call nnan float @baz.fp(float [[X]], float noundef [[Y]]) #[[ATTR2]]
; CHECK-NEXT: [[R:%.*]] = call i8 @buz.fp(float [[C1]], float [[C1]])
; CHECK-NEXT: ret i8 [[R]]
;
@@ -69,7 +69,7 @@ define i8 @same_parent_combine_diff_attrs_fmf2(float %x, float %y) {
define i8 @same_parent_combine_diff_attrs_needs_intersect2(i8 %x, i8 %y) {
; CHECK-LABEL: define i8 @same_parent_combine_diff_attrs_needs_intersect2(
; CHECK-SAME: i8 [[X:%.*]], i8 [[Y:%.*]]) {
-; CHECK-NEXT: [[C1:%.*]] = call ptr @baz.ptr(i8 [[X]], i8 noundef [[Y]]) #[[ATTR2]]
+; CHECK-NEXT: [[C1:%.*]] = call ptr @baz.ptr(i8 [[X]], i8 noundef [[Y]]) #[[ATTR3]]
; CHECK-NEXT: [[R:%.*]] = call i8 @buz.ptr(ptr [[C1]], ptr [[C1]])
; CHECK-NEXT: ret i8 [[R]]
;
@@ -83,7 +83,7 @@ define i8 @same_parent_combine_diff_attrs_needs_intersect2(i8 %x, i8 %y) {
define i8 @same_parent_combine_diff_attrs_really_needs_intersect(i8 %x, i8 %y) {
; CHECK-LABEL: define i8 @same_parent_combine_diff_attrs_really_needs_intersect(
; CHECK-SAME: i8 [[X:%.*]], i8 [[Y:%.*]]) {
-; CHECK-NEXT: [[C1:%.*]] = call ptr @baz.ptr(i8 [[X]], i8 noundef [[Y]]) #[[ATTR2]]
+; CHECK-NEXT: [[C1:%.*]] = call ptr @baz.ptr(i8 [[X]], i8 noundef [[Y]]) #[[ATTR3]]
; CHECK-NEXT: [[R:%.*]] = call i8 @buz.ptr(ptr [[C1]], ptr noundef [[C1]])
; CHECK-NEXT: ret i8 [[R]]
;
@@ -112,7 +112,7 @@ define i8 @same_parent_combine_diff_attrs_fail_side_effects(i8 %x, i8 %y) {
define i8 @same_parent_combine_diff_attrs_quasi_side_effects2(i8 %x, i8 %y) {
; CHECK-LABEL: define i8 @same_parent_combine_diff_attrs_quasi_side_effects2(
; CHECK-SAME: i8 [[X:%.*]], i8 [[Y:%.*]]) {
-; CHECK-NEXT: [[C1:%.*]] = call i8 @baz(i8 noundef [[X]], i8 noundef [[Y]]) #[[ATTR1]]
+; CHECK-NEXT: [[C1:%.*]] = call i8 @baz(i8 noundef [[X]], i8 noundef [[Y]]) #[[ATTR2]]
; CHECK-NEXT: [[C0:%.*]] = call i8 @baz(i8 [[X]], i8 noundef [[Y]])
; CHECK-NEXT: [[R:%.*]] = call i8 @buz(i8 [[C0]], i8 [[C1]])
; CHECK-NEXT: ret i8 [[R]]
@@ -127,10 +127,10 @@ define i8 @same_parent_combine_diff_attrs_quasi_side_effects2(i8 %x, i8 %y) {
define i8 @diff_parent_combine_diff_attrs(i1 %c, i8 %x, i8 %y) {
; CHECK-LABEL: define i8 @diff_parent_combine_diff_attrs(
; CHECK-SAME: i1 [[C:%.*]], i8 [[X:%.*]], i8 [[Y:%.*]]) {
-; CHECK-NEXT: [[C1:%.*]] = call i8 @baz(i8 [[X]], i8 noundef [[Y]]) #[[ATTR1]]
+; CHECK-NEXT: [[C1:%.*]] = call i8 @baz(i8 [[X]], i8 noundef [[Y]]) #[[ATTR2]]
; CHECK-NEXT: br i1 [[C]], label %[[T:.*]], label %[[F:.*]]
; CHECK: [[T]]:
-; CHECK-NEXT: [[C0:%.*]] = call i8 @baz(i8 noundef [[X]], i8 noundef [[Y]]) #[[ATTR2]]
+; CHECK-NEXT: [[C0:%.*]] = call i8 @baz(i8 noundef [[X]], i8 noundef [[Y]]) #[[ATTR3]]
; CHECK-NEXT: [[R:%.*]] = call i8 @buz(i8 [[C0]], i8 [[C1]])
; CHECK-NEXT: ret i8 [[R]]
; CHECK: ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/211769
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