[clang] [CIR][RISCV] Add new builtins, NFC (PR #211555)

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llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-clang

Author: Jianjian Guan (jacquesguan)

<details>
<summary>Changes</summary>

Leave them NYI now.

---
Full diff: https://github.com/llvm/llvm-project/pull/211555.diff


1 Files Affected:

- (modified) clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp (+44-1) 


``````````diff
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
index 25e714a612147..ea04fddc1b710 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
@@ -100,7 +100,25 @@ CIRGenFunction::emitRISCVBuiltinExpr(unsigned builtinID, const CallExpr *e) {
     intrinsicName = "riscv.unzip";
     break;
   }
-  // Zknh
+  // Zknd
+  case RISCV::BI__builtin_riscv_aes32dsi:
+  case RISCV::BI__builtin_riscv_aes32dsmi:
+  case RISCV::BI__builtin_riscv_aes64ds:
+  case RISCV::BI__builtin_riscv_aes64dsm:
+  case RISCV::BI__builtin_riscv_aes64im:
+  // Zknd & Zkne
+  case RISCV::BI__builtin_riscv_aes64ks1i:
+  case RISCV::BI__builtin_riscv_aes64ks2:
+  // Zkne
+  case RISCV::BI__builtin_riscv_aes32esi:
+  case RISCV::BI__builtin_riscv_aes32esmi:
+  case RISCV::BI__builtin_riscv_aes64es:
+  case RISCV::BI__builtin_riscv_aes64esm: {
+    cgm.errorNYI(e->getSourceRange(),
+                 std::string("unimplemented RISC-V builtin call: ") +
+                     getContext().BuiltinInfo.getName(builtinID));
+    return mlir::Value{};
+  }
   case RISCV::BI__builtin_riscv_sha256sig0: {
     intrinsicName = "riscv.sha256sig0";
     break;
@@ -117,6 +135,21 @@ CIRGenFunction::emitRISCVBuiltinExpr(unsigned builtinID, const CallExpr *e) {
     intrinsicName = "riscv.sha256sum1";
     break;
   }
+  case RISCV::BI__builtin_riscv_sha512sig0h:
+  case RISCV::BI__builtin_riscv_sha512sig0l:
+  case RISCV::BI__builtin_riscv_sha512sig1h:
+  case RISCV::BI__builtin_riscv_sha512sig1l:
+  case RISCV::BI__builtin_riscv_sha512sum0r:
+  case RISCV::BI__builtin_riscv_sha512sum1r:
+  case RISCV::BI__builtin_riscv_sha512sig0:
+  case RISCV::BI__builtin_riscv_sha512sig1:
+  case RISCV::BI__builtin_riscv_sha512sum0:
+  case RISCV::BI__builtin_riscv_sha512sum1: {
+    cgm.errorNYI(e->getSourceRange(),
+                 std::string("unimplemented RISC-V builtin call: ") +
+                     getContext().BuiltinInfo.getName(builtinID));
+    return mlir::Value{};
+  }
   // Zksed
   case RISCV::BI__builtin_riscv_sm4ks: {
     intrinsicName = "riscv.sm4ks";
@@ -282,6 +315,16 @@ CIRGenFunction::emitRISCVBuiltinExpr(unsigned builtinID, const CallExpr *e) {
     return mlir::Value{};
   }
 
+  // XMIPS execution control
+  case RISCV::BI__builtin_riscv_mips_pause:
+  case RISCV::BI__builtin_riscv_mips_ehb:
+  case RISCV::BI__builtin_riscv_mips_ihb: {
+    cgm.errorNYI(e->getSourceRange(),
+                 std::string("unimplemented RISC-V builtin call: ") +
+                     getContext().BuiltinInfo.getName(builtinID));
+    return mlir::Value{};
+  }
+
     // TODO: Handle vector builtins in tablegen.
   }
 

``````````

</details>


https://github.com/llvm/llvm-project/pull/211555