[clang] [llvm] [RISCV][P-ext] Support Packed Multiply High (PR #211236)
via cfe-commits
cfe-commits at lists.llvm.org
Wed Jul 22 04:18:33 PDT 2026
https://github.com/TelGome created https://github.com/llvm/llvm-project/pull/211236
This pr support RISC-V P extension intrinsics [Packed Multiply High](https://github.com/riscv/riscv-p-spec/blob/master/P-ext-intrinsics.adoc#packed-multiply-high)
>From b33227a1ec96577eaf6bff3634c006243cebafef Mon Sep 17 00:00:00 2001
From: Dongyan Chen <chendongyan at isrc.iscas.ac.cn>
Date: Wed, 22 Jul 2026 19:07:46 +0800
Subject: [PATCH] [RISCV][P-ext] Support Packed Multiply High
---
clang/include/clang/Basic/BuiltinsRISCV.td | 22 +
clang/lib/CodeGen/TargetBuiltins/RISCV.cpp | 51 ++-
clang/lib/Headers/riscv_packed_simd.h | 208 ++++-----
clang/test/CodeGen/RISCV/rvp-intrinsics.c | 400 ++++++++++++++++++
.../riscv_packed_simd.c | 132 ++++++
llvm/include/llvm/IR/IntrinsicsRISCV.td | 8 +
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 88 +++-
llvm/test/CodeGen/RISCV/rvp-simd-32.ll | 54 +++
llvm/test/CodeGen/RISCV/rvp-simd-64.ll | 180 ++++++++
9 files changed, 1045 insertions(+), 98 deletions(-)
diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td b/clang/include/clang/Basic/BuiltinsRISCV.td
index 3814958d81f8b..238db03cb24e7 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.td
+++ b/clang/include/clang/Basic/BuiltinsRISCV.td
@@ -265,6 +265,28 @@ def psabs_i16x2 : RISCVBuiltin<"_Vector<2, short>(_Vector<2, short>)">;
def psabs_i8x8 : RISCVBuiltin<"_Vector<8, signed char>(_Vector<8, signed char>)">;
def psabs_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<4, short>)">;
+// Packed Multiply High (32-bit)
+def pmulh_i16x2 : RISCVBuiltin<"_Vector<2, short>(_Vector<2, short>, _Vector<2, short>)">;
+def pmulhu_u16x2 : RISCVBuiltin<"_Vector<2, unsigned short>(_Vector<2, unsigned short>, _Vector<2, unsigned short>)">;
+def pmulhsu_i16x2 : RISCVBuiltin<"_Vector<2, short>(_Vector<2, short>, _Vector<2, unsigned short>)">;
+def pmulhr_i16x2 : RISCVBuiltin<"_Vector<2, short>(_Vector<2, short>, _Vector<2, short>)">;
+def pmulhru_u16x2 : RISCVBuiltin<"_Vector<2, unsigned short>(_Vector<2, unsigned short>, _Vector<2, unsigned short>)">;
+def pmulhrsu_i16x2 : RISCVBuiltin<"_Vector<2, short>(_Vector<2, short>, _Vector<2, unsigned short>)">;
+
+// Packed Multiply High (64-bit)
+def pmulh_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<4, short>, _Vector<4, short>)">;
+def pmulhu_u16x4 : RISCVBuiltin<"_Vector<4, unsigned short>(_Vector<4, unsigned short>, _Vector<4, unsigned short>)">;
+def pmulhsu_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<4, short>, _Vector<4, unsigned short>)">;
+def pmulhr_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<4, short>, _Vector<4, short>)">;
+def pmulhru_u16x4 : RISCVBuiltin<"_Vector<4, unsigned short>(_Vector<4, unsigned short>, _Vector<4, unsigned short>)">;
+def pmulhrsu_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<4, short>, _Vector<4, unsigned short>)">;
+def pmulh_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<2, int>)">;
+def pmulhu_u32x2 : RISCVBuiltin<"_Vector<2, unsigned int>(_Vector<2, unsigned int>, _Vector<2, unsigned int>)">;
+def pmulhsu_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<2, unsigned int>)">;
+def pmulhr_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<2, int>)">;
+def pmulhru_u32x2 : RISCVBuiltin<"_Vector<2, unsigned int>(_Vector<2, unsigned int>, _Vector<2, unsigned int>)">;
+def pmulhrsu_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<2, unsigned int>)">;
+
} // Features = "experimental-p"
//===----------------------------------------------------------------------===//
diff --git a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
index a3b1db1732af9..df1c8790ef232 100644
--- a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
@@ -1263,7 +1263,26 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
case RISCV::BI__builtin_riscv_psabs_i8x4:
case RISCV::BI__builtin_riscv_psabs_i16x2:
case RISCV::BI__builtin_riscv_psabs_i8x8:
- case RISCV::BI__builtin_riscv_psabs_i16x4: {
+ case RISCV::BI__builtin_riscv_psabs_i16x4:
+ // Packed Multiply High
+ case RISCV::BI__builtin_riscv_pmulh_i16x2:
+ case RISCV::BI__builtin_riscv_pmulhu_u16x2:
+ case RISCV::BI__builtin_riscv_pmulhsu_i16x2:
+ case RISCV::BI__builtin_riscv_pmulhr_i16x2:
+ case RISCV::BI__builtin_riscv_pmulhru_u16x2:
+ case RISCV::BI__builtin_riscv_pmulhrsu_i16x2:
+ case RISCV::BI__builtin_riscv_pmulh_i16x4:
+ case RISCV::BI__builtin_riscv_pmulhu_u16x4:
+ case RISCV::BI__builtin_riscv_pmulhsu_i16x4:
+ case RISCV::BI__builtin_riscv_pmulhr_i16x4:
+ case RISCV::BI__builtin_riscv_pmulhru_u16x4:
+ case RISCV::BI__builtin_riscv_pmulhrsu_i16x4:
+ case RISCV::BI__builtin_riscv_pmulh_i32x2:
+ case RISCV::BI__builtin_riscv_pmulhu_u32x2:
+ case RISCV::BI__builtin_riscv_pmulhsu_i32x2:
+ case RISCV::BI__builtin_riscv_pmulhr_i32x2:
+ case RISCV::BI__builtin_riscv_pmulhru_u32x2:
+ case RISCV::BI__builtin_riscv_pmulhrsu_i32x2: {
switch (BuiltinID) {
default:
llvm_unreachable("unexpected builtin ID");
@@ -1355,6 +1374,36 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
case RISCV::BI__builtin_riscv_psabs_i16x4:
ID = Intrinsic::riscv_psabs;
break;
+ case RISCV::BI__builtin_riscv_pmulh_i16x2:
+ case RISCV::BI__builtin_riscv_pmulh_i16x4:
+ case RISCV::BI__builtin_riscv_pmulh_i32x2:
+ ID = Intrinsic::riscv_pmulh;
+ break;
+ case RISCV::BI__builtin_riscv_pmulhu_u16x2:
+ case RISCV::BI__builtin_riscv_pmulhu_u16x4:
+ case RISCV::BI__builtin_riscv_pmulhu_u32x2:
+ ID = Intrinsic::riscv_pmulhu;
+ break;
+ case RISCV::BI__builtin_riscv_pmulhsu_i16x2:
+ case RISCV::BI__builtin_riscv_pmulhsu_i16x4:
+ case RISCV::BI__builtin_riscv_pmulhsu_i32x2:
+ ID = Intrinsic::riscv_pmulhsu;
+ break;
+ case RISCV::BI__builtin_riscv_pmulhr_i16x2:
+ case RISCV::BI__builtin_riscv_pmulhr_i16x4:
+ case RISCV::BI__builtin_riscv_pmulhr_i32x2:
+ ID = Intrinsic::riscv_pmulhr;
+ break;
+ case RISCV::BI__builtin_riscv_pmulhru_u16x2:
+ case RISCV::BI__builtin_riscv_pmulhru_u16x4:
+ case RISCV::BI__builtin_riscv_pmulhru_u32x2:
+ ID = Intrinsic::riscv_pmulhru;
+ break;
+ case RISCV::BI__builtin_riscv_pmulhrsu_i16x2:
+ case RISCV::BI__builtin_riscv_pmulhrsu_i16x4:
+ case RISCV::BI__builtin_riscv_pmulhrsu_i32x2:
+ ID = Intrinsic::riscv_pmulhrsu;
+ break;
}
IntrinsicTypes = {ResultType};
diff --git a/clang/lib/Headers/riscv_packed_simd.h b/clang/lib/Headers/riscv_packed_simd.h
index 7d40f046eba80..91215aa2f039d 100644
--- a/clang/lib/Headers/riscv_packed_simd.h
+++ b/clang/lib/Headers/riscv_packed_simd.h
@@ -66,9 +66,10 @@ typedef uint32_t uint32x2_t __attribute__((__vector_size__(8)));
return op __rs1; \
}
-#define __packed_binary_builtin(name, ty, builtin) \
- static __inline__ ty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, ty __rs2) { \
- return builtin(__rs1, __rs2); \
+#define __packed_binary_builtin(name, rty, ty1, ty2, builtin) \
+ static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty1 __rs1, \
+ ty2 __rs2) { \
+ return (rty)builtin(__rs1, __rs2); \
}
#define __packed_sh1add(name, ty) \
@@ -97,12 +98,6 @@ typedef uint32_t uint32x2_t __attribute__((__vector_size__(8)));
return (rty)__builtin_elementwise_abs(__rs1); \
}
-#define __packed_binary_builtin_cast(name, ty, rty, builtin) \
- static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \
- ty __rs2) { \
- return (rty)builtin(__rs1, __rs2); \
- }
-
#define __packed_reduction(name, rty, ty, builtin) \
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \
rty __rs2) { \
@@ -320,28 +315,28 @@ __packed_scalar_binary_op(padd_s_i32x2, int32x2_t, int32_t, +,
__packed_splat2)
/* Packed Saturating Addition and Subtraction (32-bit) */
-__packed_binary_builtin(psadd_i8x4, int8x4_t, __builtin_elementwise_add_sat)
-__packed_binary_builtin(psadd_i16x2, int16x2_t, __builtin_elementwise_add_sat)
-__packed_binary_builtin(psaddu_u8x4, uint8x4_t, __builtin_elementwise_add_sat)
-__packed_binary_builtin(psaddu_u16x2, uint16x2_t, __builtin_elementwise_add_sat)
-__packed_binary_builtin(pssub_i8x4, int8x4_t, __builtin_elementwise_sub_sat)
-__packed_binary_builtin(pssub_i16x2, int16x2_t, __builtin_elementwise_sub_sat)
-__packed_binary_builtin(pssubu_u8x4, uint8x4_t, __builtin_elementwise_sub_sat)
-__packed_binary_builtin(pssubu_u16x2, uint16x2_t, __builtin_elementwise_sub_sat)
+__packed_binary_builtin(psadd_i8x4, int8x4_t, int8x4_t, int8x4_t, __builtin_elementwise_add_sat)
+__packed_binary_builtin(psadd_i16x2, int16x2_t, int16x2_t, int16x2_t, __builtin_elementwise_add_sat)
+__packed_binary_builtin(psaddu_u8x4, uint8x4_t, uint8x4_t, uint8x4_t, __builtin_elementwise_add_sat)
+__packed_binary_builtin(psaddu_u16x2, uint16x2_t, uint16x2_t, uint16x2_t, __builtin_elementwise_add_sat)
+__packed_binary_builtin(pssub_i8x4, int8x4_t, int8x4_t, int8x4_t, __builtin_elementwise_sub_sat)
+__packed_binary_builtin(pssub_i16x2, int16x2_t, int16x2_t, int16x2_t, __builtin_elementwise_sub_sat)
+__packed_binary_builtin(pssubu_u8x4, uint8x4_t, uint8x4_t, uint8x4_t, __builtin_elementwise_sub_sat)
+__packed_binary_builtin(pssubu_u16x2, uint16x2_t, uint16x2_t, uint16x2_t, __builtin_elementwise_sub_sat)
/* Packed Saturating Addition and Subtraction (64-bit) */
-__packed_binary_builtin(psadd_i8x8, int8x8_t, __builtin_elementwise_add_sat)
-__packed_binary_builtin(psadd_i16x4, int16x4_t, __builtin_elementwise_add_sat)
-__packed_binary_builtin(psadd_i32x2, int32x2_t, __builtin_elementwise_add_sat)
-__packed_binary_builtin(psaddu_u8x8, uint8x8_t, __builtin_elementwise_add_sat)
-__packed_binary_builtin(psaddu_u16x4, uint16x4_t, __builtin_elementwise_add_sat)
-__packed_binary_builtin(psaddu_u32x2, uint32x2_t, __builtin_elementwise_add_sat)
-__packed_binary_builtin(pssub_i8x8, int8x8_t, __builtin_elementwise_sub_sat)
-__packed_binary_builtin(pssub_i16x4, int16x4_t, __builtin_elementwise_sub_sat)
-__packed_binary_builtin(pssub_i32x2, int32x2_t, __builtin_elementwise_sub_sat)
-__packed_binary_builtin(pssubu_u8x8, uint8x8_t, __builtin_elementwise_sub_sat)
-__packed_binary_builtin(pssubu_u16x4, uint16x4_t, __builtin_elementwise_sub_sat)
-__packed_binary_builtin(pssubu_u32x2, uint32x2_t, __builtin_elementwise_sub_sat)
+__packed_binary_builtin(psadd_i8x8, int8x8_t, int8x8_t, int8x8_t, __builtin_elementwise_add_sat)
+__packed_binary_builtin(psadd_i16x4, int16x4_t, int16x4_t, int16x4_t, __builtin_elementwise_add_sat)
+__packed_binary_builtin(psadd_i32x2, int32x2_t, int32x2_t, int32x2_t, __builtin_elementwise_add_sat)
+__packed_binary_builtin(psaddu_u8x8, uint8x8_t, uint8x8_t, uint8x8_t, __builtin_elementwise_add_sat)
+__packed_binary_builtin(psaddu_u16x4, uint16x4_t, uint16x4_t, uint16x4_t, __builtin_elementwise_add_sat)
+__packed_binary_builtin(psaddu_u32x2, uint32x2_t, uint32x2_t, uint32x2_t, __builtin_elementwise_add_sat)
+__packed_binary_builtin(pssub_i8x8, int8x8_t, int8x8_t, int8x8_t, __builtin_elementwise_sub_sat)
+__packed_binary_builtin(pssub_i16x4, int16x4_t, int16x4_t, int16x4_t, __builtin_elementwise_sub_sat)
+__packed_binary_builtin(pssub_i32x2, int32x2_t, int32x2_t, int32x2_t, __builtin_elementwise_sub_sat)
+__packed_binary_builtin(pssubu_u8x8, uint8x8_t, uint8x8_t, uint8x8_t, __builtin_elementwise_sub_sat)
+__packed_binary_builtin(pssubu_u16x4, uint16x4_t, uint16x4_t, uint16x4_t, __builtin_elementwise_sub_sat)
+__packed_binary_builtin(pssubu_u32x2, uint32x2_t, uint32x2_t, uint32x2_t, __builtin_elementwise_sub_sat)
/* Packed Shift-Add (32-bit) */
__packed_sh1add(psh1add_i16x2, int16x2_t)
@@ -357,50 +352,50 @@ __packed_sh1sadd(pssh1sadd_i16x4, int16x4_t)
__packed_sh1sadd(pssh1sadd_i32x2, int32x2_t)
/* Packed Exchanged Addition and Subtraction (32-bit) */
-__packed_binary_builtin(pas_x_i16x2, int16x2_t, __builtin_riscv_pas_x_i16x2)
-__packed_binary_builtin(psa_x_i16x2, int16x2_t, __builtin_riscv_psa_x_i16x2)
-__packed_binary_builtin(psas_x_i16x2, int16x2_t, __builtin_riscv_psas_x_i16x2)
-__packed_binary_builtin(pssa_x_i16x2, int16x2_t, __builtin_riscv_pssa_x_i16x2)
-__packed_binary_builtin(paas_x_i16x2, int16x2_t, __builtin_riscv_paas_x_i16x2)
-__packed_binary_builtin(pasa_x_i16x2, int16x2_t, __builtin_riscv_pasa_x_i16x2)
+__packed_binary_builtin(pas_x_i16x2, int16x2_t, int16x2_t, int16x2_t, __builtin_riscv_pas_x_i16x2)
+__packed_binary_builtin(psa_x_i16x2, int16x2_t, int16x2_t, int16x2_t, __builtin_riscv_psa_x_i16x2)
+__packed_binary_builtin(psas_x_i16x2, int16x2_t, int16x2_t, int16x2_t, __builtin_riscv_psas_x_i16x2)
+__packed_binary_builtin(pssa_x_i16x2, int16x2_t, int16x2_t, int16x2_t, __builtin_riscv_pssa_x_i16x2)
+__packed_binary_builtin(paas_x_i16x2, int16x2_t, int16x2_t, int16x2_t, __builtin_riscv_paas_x_i16x2)
+__packed_binary_builtin(pasa_x_i16x2, int16x2_t, int16x2_t, int16x2_t, __builtin_riscv_pasa_x_i16x2)
/* Packed Exchanged Addition and Subtraction (64-bit) */
-__packed_binary_builtin(pas_x_i16x4, int16x4_t, __builtin_riscv_pas_x_i16x4)
-__packed_binary_builtin(psa_x_i16x4, int16x4_t, __builtin_riscv_psa_x_i16x4)
-__packed_binary_builtin(psas_x_i16x4, int16x4_t, __builtin_riscv_psas_x_i16x4)
-__packed_binary_builtin(pssa_x_i16x4, int16x4_t, __builtin_riscv_pssa_x_i16x4)
-__packed_binary_builtin(paas_x_i16x4, int16x4_t, __builtin_riscv_paas_x_i16x4)
-__packed_binary_builtin(pasa_x_i16x4, int16x4_t, __builtin_riscv_pasa_x_i16x4)
-__packed_binary_builtin(pas_x_i32x2, int32x2_t, __builtin_riscv_pas_x_i32x2)
-__packed_binary_builtin(psa_x_i32x2, int32x2_t, __builtin_riscv_psa_x_i32x2)
-__packed_binary_builtin(psas_x_i32x2, int32x2_t, __builtin_riscv_psas_x_i32x2)
-__packed_binary_builtin(pssa_x_i32x2, int32x2_t, __builtin_riscv_pssa_x_i32x2)
-__packed_binary_builtin(paas_x_i32x2, int32x2_t, __builtin_riscv_paas_x_i32x2)
-__packed_binary_builtin(pasa_x_i32x2, int32x2_t, __builtin_riscv_pasa_x_i32x2)
+__packed_binary_builtin(pas_x_i16x4, int16x4_t, int16x4_t, int16x4_t, __builtin_riscv_pas_x_i16x4)
+__packed_binary_builtin(psa_x_i16x4, int16x4_t, int16x4_t, int16x4_t, __builtin_riscv_psa_x_i16x4)
+__packed_binary_builtin(psas_x_i16x4, int16x4_t, int16x4_t, int16x4_t, __builtin_riscv_psas_x_i16x4)
+__packed_binary_builtin(pssa_x_i16x4, int16x4_t, int16x4_t, int16x4_t, __builtin_riscv_pssa_x_i16x4)
+__packed_binary_builtin(paas_x_i16x4, int16x4_t, int16x4_t, int16x4_t, __builtin_riscv_paas_x_i16x4)
+__packed_binary_builtin(pasa_x_i16x4, int16x4_t, int16x4_t, int16x4_t, __builtin_riscv_pasa_x_i16x4)
+__packed_binary_builtin(pas_x_i32x2, int32x2_t, int32x2_t, int32x2_t, __builtin_riscv_pas_x_i32x2)
+__packed_binary_builtin(psa_x_i32x2, int32x2_t, int32x2_t, int32x2_t, __builtin_riscv_psa_x_i32x2)
+__packed_binary_builtin(psas_x_i32x2, int32x2_t, int32x2_t, int32x2_t, __builtin_riscv_psas_x_i32x2)
+__packed_binary_builtin(pssa_x_i32x2, int32x2_t, int32x2_t, int32x2_t, __builtin_riscv_pssa_x_i32x2)
+__packed_binary_builtin(paas_x_i32x2, int32x2_t, int32x2_t, int32x2_t, __builtin_riscv_paas_x_i32x2)
+__packed_binary_builtin(pasa_x_i32x2, int32x2_t, int32x2_t, int32x2_t, __builtin_riscv_pasa_x_i32x2)
/* Packed Minimum and Maximum (32-bit) */
-__packed_binary_builtin(pmin_i8x4, int8x4_t, __builtin_elementwise_min)
-__packed_binary_builtin(pmin_i16x2, int16x2_t, __builtin_elementwise_min)
-__packed_binary_builtin(pminu_u8x4, uint8x4_t, __builtin_elementwise_min)
-__packed_binary_builtin(pminu_u16x2, uint16x2_t, __builtin_elementwise_min)
-__packed_binary_builtin(pmax_i8x4, int8x4_t, __builtin_elementwise_max)
-__packed_binary_builtin(pmax_i16x2, int16x2_t, __builtin_elementwise_max)
-__packed_binary_builtin(pmaxu_u8x4, uint8x4_t, __builtin_elementwise_max)
-__packed_binary_builtin(pmaxu_u16x2, uint16x2_t, __builtin_elementwise_max)
+__packed_binary_builtin(pmin_i8x4, int8x4_t, int8x4_t, int8x4_t, __builtin_elementwise_min)
+__packed_binary_builtin(pmin_i16x2, int16x2_t, int16x2_t, int16x2_t, __builtin_elementwise_min)
+__packed_binary_builtin(pminu_u8x4, uint8x4_t, uint8x4_t, uint8x4_t, __builtin_elementwise_min)
+__packed_binary_builtin(pminu_u16x2, uint16x2_t, uint16x2_t, uint16x2_t, __builtin_elementwise_min)
+__packed_binary_builtin(pmax_i8x4, int8x4_t, int8x4_t, int8x4_t, __builtin_elementwise_max)
+__packed_binary_builtin(pmax_i16x2, int16x2_t, int16x2_t, int16x2_t, __builtin_elementwise_max)
+__packed_binary_builtin(pmaxu_u8x4, uint8x4_t, uint8x4_t, uint8x4_t, __builtin_elementwise_max)
+__packed_binary_builtin(pmaxu_u16x2, uint16x2_t, uint16x2_t, uint16x2_t, __builtin_elementwise_max)
/* Packed Minimum and Maximum (64-bit) */
-__packed_binary_builtin(pmin_i8x8, int8x8_t, __builtin_elementwise_min)
-__packed_binary_builtin(pmin_i16x4, int16x4_t, __builtin_elementwise_min)
-__packed_binary_builtin(pmin_i32x2, int32x2_t, __builtin_elementwise_min)
-__packed_binary_builtin(pminu_u8x8, uint8x8_t, __builtin_elementwise_min)
-__packed_binary_builtin(pminu_u16x4, uint16x4_t, __builtin_elementwise_min)
-__packed_binary_builtin(pminu_u32x2, uint32x2_t, __builtin_elementwise_min)
-__packed_binary_builtin(pmax_i8x8, int8x8_t, __builtin_elementwise_max)
-__packed_binary_builtin(pmax_i16x4, int16x4_t, __builtin_elementwise_max)
-__packed_binary_builtin(pmax_i32x2, int32x2_t, __builtin_elementwise_max)
-__packed_binary_builtin(pmaxu_u8x8, uint8x8_t, __builtin_elementwise_max)
-__packed_binary_builtin(pmaxu_u16x4, uint16x4_t, __builtin_elementwise_max)
-__packed_binary_builtin(pmaxu_u32x2, uint32x2_t, __builtin_elementwise_max)
+__packed_binary_builtin(pmin_i8x8, int8x8_t, int8x8_t, int8x8_t, __builtin_elementwise_min)
+__packed_binary_builtin(pmin_i16x4, int16x4_t, int16x4_t, int16x4_t, __builtin_elementwise_min)
+__packed_binary_builtin(pmin_i32x2, int32x2_t, int32x2_t, int32x2_t, __builtin_elementwise_min)
+__packed_binary_builtin(pminu_u8x8, uint8x8_t, uint8x8_t, uint8x8_t, __builtin_elementwise_min)
+__packed_binary_builtin(pminu_u16x4, uint16x4_t, uint16x4_t, uint16x4_t, __builtin_elementwise_min)
+__packed_binary_builtin(pminu_u32x2, uint32x2_t, uint32x2_t, uint32x2_t, __builtin_elementwise_min)
+__packed_binary_builtin(pmax_i8x8, int8x8_t, int8x8_t, int8x8_t, __builtin_elementwise_max)
+__packed_binary_builtin(pmax_i16x4, int16x4_t, int16x4_t, int16x4_t, __builtin_elementwise_max)
+__packed_binary_builtin(pmax_i32x2, int32x2_t, int32x2_t, int32x2_t, __builtin_elementwise_max)
+__packed_binary_builtin(pmaxu_u8x8, uint8x8_t, uint8x8_t, uint8x8_t, __builtin_elementwise_max)
+__packed_binary_builtin(pmaxu_u16x4, uint16x4_t, uint16x4_t, uint16x4_t, __builtin_elementwise_max)
+__packed_binary_builtin(pmaxu_u32x2, uint32x2_t, uint32x2_t, uint32x2_t, __builtin_elementwise_max)
/* Packed Comparison (32-bit) */
__packed_cmp(pmseq_i8x4_u8x4, int8x4_t, uint8x4_t, ==)
@@ -601,44 +596,44 @@ __packed_nziph2(pnziph_i16x4, int16x4_t, int32x2_t)
__packed_nziph2(pnziph_u16x4, uint16x4_t, uint32x2_t)
/* Packed Averaging Addition and Subtraction (32-bit) */
-__packed_binary_builtin(paadd_i8x4, int8x4_t, __builtin_riscv_paadd_i8x4)
-__packed_binary_builtin(paadd_i16x2, int16x2_t, __builtin_riscv_paadd_i16x2)
-__packed_binary_builtin(paaddu_u8x4, uint8x4_t, __builtin_riscv_paaddu_u8x4)
-__packed_binary_builtin(paaddu_u16x2, uint16x2_t, __builtin_riscv_paaddu_u16x2)
-__packed_binary_builtin(pasub_i8x4, int8x4_t, __builtin_riscv_pasub_i8x4)
-__packed_binary_builtin(pasub_i16x2, int16x2_t, __builtin_riscv_pasub_i16x2)
-__packed_binary_builtin(pasubu_u8x4, uint8x4_t, __builtin_riscv_pasubu_u8x4)
-__packed_binary_builtin(pasubu_u16x2, uint16x2_t, __builtin_riscv_pasubu_u16x2)
+__packed_binary_builtin(paadd_i8x4, int8x4_t, int8x4_t, int8x4_t, __builtin_riscv_paadd_i8x4)
+__packed_binary_builtin(paadd_i16x2, int16x2_t, int16x2_t, int16x2_t, __builtin_riscv_paadd_i16x2)
+__packed_binary_builtin(paaddu_u8x4, uint8x4_t, uint8x4_t, uint8x4_t, __builtin_riscv_paaddu_u8x4)
+__packed_binary_builtin(paaddu_u16x2, uint16x2_t, uint16x2_t, uint16x2_t, __builtin_riscv_paaddu_u16x2)
+__packed_binary_builtin(pasub_i8x4, int8x4_t, int8x4_t, int8x4_t, __builtin_riscv_pasub_i8x4)
+__packed_binary_builtin(pasub_i16x2, int16x2_t, int16x2_t, int16x2_t, __builtin_riscv_pasub_i16x2)
+__packed_binary_builtin(pasubu_u8x4, uint8x4_t, uint8x4_t, uint8x4_t, __builtin_riscv_pasubu_u8x4)
+__packed_binary_builtin(pasubu_u16x2, uint16x2_t, uint16x2_t, uint16x2_t, __builtin_riscv_pasubu_u16x2)
/* Packed Averaging Addition and Subtraction (64-bit) */
-__packed_binary_builtin(paadd_i8x8, int8x8_t, __builtin_riscv_paadd_i8x8)
-__packed_binary_builtin(paadd_i16x4, int16x4_t, __builtin_riscv_paadd_i16x4)
-__packed_binary_builtin(paadd_i32x2, int32x2_t, __builtin_riscv_paadd_i32x2)
-__packed_binary_builtin(paaddu_u8x8, uint8x8_t, __builtin_riscv_paaddu_u8x8)
-__packed_binary_builtin(paaddu_u16x4, uint16x4_t, __builtin_riscv_paaddu_u16x4)
-__packed_binary_builtin(paaddu_u32x2, uint32x2_t, __builtin_riscv_paaddu_u32x2)
-__packed_binary_builtin(pasub_i8x8, int8x8_t, __builtin_riscv_pasub_i8x8)
-__packed_binary_builtin(pasub_i16x4, int16x4_t, __builtin_riscv_pasub_i16x4)
-__packed_binary_builtin(pasub_i32x2, int32x2_t, __builtin_riscv_pasub_i32x2)
-__packed_binary_builtin(pasubu_u8x8, uint8x8_t, __builtin_riscv_pasubu_u8x8)
-__packed_binary_builtin(pasubu_u16x4, uint16x4_t, __builtin_riscv_pasubu_u16x4)
-__packed_binary_builtin(pasubu_u32x2, uint32x2_t, __builtin_riscv_pasubu_u32x2)
+__packed_binary_builtin(paadd_i8x8, int8x8_t, int8x8_t, int8x8_t, __builtin_riscv_paadd_i8x8)
+__packed_binary_builtin(paadd_i16x4, int16x4_t, int16x4_t, int16x4_t, __builtin_riscv_paadd_i16x4)
+__packed_binary_builtin(paadd_i32x2, int32x2_t, int32x2_t, int32x2_t, __builtin_riscv_paadd_i32x2)
+__packed_binary_builtin(paaddu_u8x8, uint8x8_t, uint8x8_t, uint8x8_t, __builtin_riscv_paaddu_u8x8)
+__packed_binary_builtin(paaddu_u16x4, uint16x4_t, uint16x4_t, uint16x4_t, __builtin_riscv_paaddu_u16x4)
+__packed_binary_builtin(paaddu_u32x2, uint32x2_t, uint32x2_t, uint32x2_t, __builtin_riscv_paaddu_u32x2)
+__packed_binary_builtin(pasub_i8x8, int8x8_t, int8x8_t, int8x8_t, __builtin_riscv_pasub_i8x8)
+__packed_binary_builtin(pasub_i16x4, int16x4_t, int16x4_t, int16x4_t, __builtin_riscv_pasub_i16x4)
+__packed_binary_builtin(pasub_i32x2, int32x2_t, int32x2_t, int32x2_t, __builtin_riscv_pasub_i32x2)
+__packed_binary_builtin(pasubu_u8x8, uint8x8_t, uint8x8_t, uint8x8_t, __builtin_riscv_pasubu_u8x8)
+__packed_binary_builtin(pasubu_u16x4, uint16x4_t, uint16x4_t, uint16x4_t, __builtin_riscv_pasubu_u16x4)
+__packed_binary_builtin(pasubu_u32x2, uint32x2_t, uint32x2_t, uint32x2_t, __builtin_riscv_pasubu_u32x2)
/* Packed Absolute Value and Absolute Difference (32-bit) */
__packed_pabs(pabs_i8x4, int8x4_t, uint8x4_t)
__packed_pabs(pabs_i16x2, int16x2_t, uint16x2_t)
-__packed_binary_builtin_cast(pabd_i8x4, int8x4_t, uint8x4_t, __builtin_riscv_pabd_i8x4)
-__packed_binary_builtin_cast(pabd_i16x2, int16x2_t, uint16x2_t, __builtin_riscv_pabd_i16x2)
-__packed_binary_builtin_cast(pabdu_u8x4, uint8x4_t, uint8x4_t, __builtin_riscv_pabdu_u8x4)
-__packed_binary_builtin_cast(pabdu_u16x2, uint16x2_t, uint16x2_t, __builtin_riscv_pabdu_u16x2)
+__packed_binary_builtin(pabd_i8x4, uint8x4_t, int8x4_t, int8x4_t, __builtin_riscv_pabd_i8x4)
+__packed_binary_builtin(pabd_i16x2, uint16x2_t, int16x2_t, int16x2_t, __builtin_riscv_pabd_i16x2)
+__packed_binary_builtin(pabdu_u8x4, uint8x4_t, uint8x4_t, uint8x4_t, __builtin_riscv_pabdu_u8x4)
+__packed_binary_builtin(pabdu_u16x2, uint16x2_t, uint16x2_t, uint16x2_t, __builtin_riscv_pabdu_u16x2)
/* Packed Absolute Value and Absolute Difference (64-bit) */
__packed_pabs(pabs_i8x8, int8x8_t, uint8x8_t)
__packed_pabs(pabs_i16x4, int16x4_t, uint16x4_t)
-__packed_binary_builtin_cast(pabd_i8x8, int8x8_t, uint8x8_t, __builtin_riscv_pabd_i8x8)
-__packed_binary_builtin_cast(pabd_i16x4, int16x4_t, uint16x4_t, __builtin_riscv_pabd_i16x4)
-__packed_binary_builtin_cast(pabdu_u8x8, uint8x8_t, uint8x8_t, __builtin_riscv_pabdu_u8x8)
-__packed_binary_builtin_cast(pabdu_u16x4, uint16x4_t, uint16x4_t, __builtin_riscv_pabdu_u16x4)
+__packed_binary_builtin(pabd_i8x8, uint8x8_t, int8x8_t, int8x8_t, __builtin_riscv_pabd_i8x8)
+__packed_binary_builtin(pabd_i16x4, uint16x4_t, int16x4_t, int16x4_t, __builtin_riscv_pabd_i16x4)
+__packed_binary_builtin(pabdu_u8x8, uint8x8_t, uint8x8_t, uint8x8_t, __builtin_riscv_pabdu_u8x8)
+__packed_binary_builtin(pabdu_u16x4, uint16x4_t, uint16x4_t, uint16x4_t, __builtin_riscv_pabdu_u16x4)
/* Packed Reduction Sum (32-bit) */
__packed_reduction(predsum_i8x4_i32, int32_t, int8x4_t, __builtin_riscv_predsum_i8x4_i32)
@@ -690,6 +685,28 @@ __packed_psabs(psabs_i16x2, int16x2_t, __builtin_riscv_psabs_i16x2)
__packed_psabs(psabs_i8x8, int8x8_t, __builtin_riscv_psabs_i8x8)
__packed_psabs(psabs_i16x4, int16x4_t, __builtin_riscv_psabs_i16x4)
+/* Packed Multiply High (32-bit) */
+__packed_binary_builtin(pmulh_i16x2, int16x2_t, int16x2_t, int16x2_t, __builtin_riscv_pmulh_i16x2)
+__packed_binary_builtin(pmulhu_u16x2, uint16x2_t, uint16x2_t, uint16x2_t, __builtin_riscv_pmulhu_u16x2)
+__packed_binary_builtin(pmulhsu_i16x2, int16x2_t, int16x2_t, uint16x2_t, __builtin_riscv_pmulhsu_i16x2)
+__packed_binary_builtin(pmulhr_i16x2, int16x2_t, int16x2_t, int16x2_t, __builtin_riscv_pmulhr_i16x2)
+__packed_binary_builtin(pmulhru_u16x2, uint16x2_t, uint16x2_t, uint16x2_t, __builtin_riscv_pmulhru_u16x2)
+__packed_binary_builtin(pmulhrsu_i16x2, int16x2_t, int16x2_t, uint16x2_t, __builtin_riscv_pmulhrsu_i16x2)
+
+/* Packed Multiply High (64-bit) */
+__packed_binary_builtin(pmulh_i16x4, int16x4_t, int16x4_t, int16x4_t, __builtin_riscv_pmulh_i16x4)
+__packed_binary_builtin(pmulhu_u16x4, uint16x4_t, uint16x4_t, uint16x4_t, __builtin_riscv_pmulhu_u16x4)
+__packed_binary_builtin(pmulhsu_i16x4, int16x4_t, int16x4_t, uint16x4_t, __builtin_riscv_pmulhsu_i16x4)
+__packed_binary_builtin(pmulhr_i16x4, int16x4_t, int16x4_t, int16x4_t, __builtin_riscv_pmulhr_i16x4)
+__packed_binary_builtin(pmulhru_u16x4, uint16x4_t, uint16x4_t, uint16x4_t, __builtin_riscv_pmulhru_u16x4)
+__packed_binary_builtin(pmulhrsu_i16x4, int16x4_t, int16x4_t, uint16x4_t, __builtin_riscv_pmulhrsu_i16x4)
+__packed_binary_builtin(pmulh_i32x2, int32x2_t, int32x2_t, int32x2_t, __builtin_riscv_pmulh_i32x2)
+__packed_binary_builtin(pmulhu_u32x2, uint32x2_t, uint32x2_t, uint32x2_t, __builtin_riscv_pmulhu_u32x2)
+__packed_binary_builtin(pmulhsu_i32x2, int32x2_t, int32x2_t, uint32x2_t, __builtin_riscv_pmulhsu_i32x2)
+__packed_binary_builtin(pmulhr_i32x2, int32x2_t, int32x2_t, int32x2_t, __builtin_riscv_pmulhr_i32x2)
+__packed_binary_builtin(pmulhru_u32x2, uint32x2_t, uint32x2_t, uint32x2_t, __builtin_riscv_pmulhru_u32x2)
+__packed_binary_builtin(pmulhrsu_i32x2, int32x2_t, int32x2_t, uint32x2_t, __builtin_riscv_pmulhrsu_i32x2)
+
/* Reinterpret Casts, Packed <-> Scalar (32-bit) */
__packed_reinterpret(u8x4_u32, uint32_t, uint8x4_t)
__packed_reinterpret(u16x2_u32, uint32_t, uint16x2_t)
@@ -798,7 +815,6 @@ __packed_reinterpret(u32x2_i32x2, int32x2_t, uint32x2_t)
#undef __packed_sh1sadd
#undef __packed_cmp
#undef __packed_pabs
-#undef __packed_binary_builtin_cast
#undef __packed_reduction
#undef __packed_merge_builtin
#undef __packed_psabs
diff --git a/clang/test/CodeGen/RISCV/rvp-intrinsics.c b/clang/test/CodeGen/RISCV/rvp-intrinsics.c
index 816409268ce02..2b70b6cc3f25d 100644
--- a/clang/test/CodeGen/RISCV/rvp-intrinsics.c
+++ b/clang/test/CodeGen/RISCV/rvp-intrinsics.c
@@ -7352,6 +7352,406 @@ uint16x2_t test_pncvth_u16x2(uint32x2_t rs1) {
return __riscv_pncvth_u16x2(rs1);
}
+/* Packed Multiply High (32-bit) */
+
+// RV32-LABEL: define dso_local i32 @test_pmulh_i16x2(
+// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulh.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// RV32-NEXT: ret i32 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i32 @test_pmulh_i16x2(
+// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulh.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// RV64-NEXT: ret i32 [[TMP3]]
+//
+int16x2_t test_pmulh_i16x2(int16x2_t rs1, int16x2_t rs2) {
+ return __riscv_pmulh_i16x2(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pmulhu_u16x2(
+// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulhu.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// RV32-NEXT: ret i32 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i32 @test_pmulhu_u16x2(
+// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulhu.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// RV64-NEXT: ret i32 [[TMP3]]
+//
+uint16x2_t test_pmulhu_u16x2(uint16x2_t rs1, uint16x2_t rs2) {
+ return __riscv_pmulhu_u16x2(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pmulhsu_i16x2(
+// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulhsu.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// RV32-NEXT: ret i32 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i32 @test_pmulhsu_i16x2(
+// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulhsu.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// RV64-NEXT: ret i32 [[TMP3]]
+//
+int16x2_t test_pmulhsu_i16x2(int16x2_t rs1, uint16x2_t rs2) {
+ return __riscv_pmulhsu_i16x2(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pmulhr_i16x2(
+// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulhr.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// RV32-NEXT: ret i32 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i32 @test_pmulhr_i16x2(
+// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulhr.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// RV64-NEXT: ret i32 [[TMP3]]
+//
+int16x2_t test_pmulhr_i16x2(int16x2_t rs1, int16x2_t rs2) {
+ return __riscv_pmulhr_i16x2(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pmulhru_u16x2(
+// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulhru.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// RV32-NEXT: ret i32 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i32 @test_pmulhru_u16x2(
+// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulhru.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// RV64-NEXT: ret i32 [[TMP3]]
+//
+uint16x2_t test_pmulhru_u16x2(uint16x2_t rs1, uint16x2_t rs2) {
+ return __riscv_pmulhru_u16x2(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pmulhrsu_i16x2(
+// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulhrsu.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// RV32-NEXT: ret i32 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i32 @test_pmulhrsu_i16x2(
+// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulhrsu.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// RV64-NEXT: ret i32 [[TMP3]]
+//
+int16x2_t test_pmulhrsu_i16x2(int16x2_t rs1, uint16x2_t rs2) {
+ return __riscv_pmulhrsu_i16x2(rs1, rs2);
+}
+
+/* Packed Multiply High (64-bit) */
+
+// RV32-LABEL: define dso_local i64 @test_pmulh_i16x4(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulh.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV32-NEXT: ret i64 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i64 @test_pmulh_i16x4(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulh.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV64-NEXT: ret i64 [[TMP3]]
+//
+int16x4_t test_pmulh_i16x4(int16x4_t rs1, int16x4_t rs2) {
+ return __riscv_pmulh_i16x4(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pmulhu_u16x4(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulhu.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV32-NEXT: ret i64 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i64 @test_pmulhu_u16x4(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulhu.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV64-NEXT: ret i64 [[TMP3]]
+//
+uint16x4_t test_pmulhu_u16x4(uint16x4_t rs1, uint16x4_t rs2) {
+ return __riscv_pmulhu_u16x4(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pmulhsu_i16x4(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulhsu.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV32-NEXT: ret i64 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i64 @test_pmulhsu_i16x4(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulhsu.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV64-NEXT: ret i64 [[TMP3]]
+//
+int16x4_t test_pmulhsu_i16x4(int16x4_t rs1, uint16x4_t rs2) {
+ return __riscv_pmulhsu_i16x4(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pmulhr_i16x4(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulhr.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV32-NEXT: ret i64 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i64 @test_pmulhr_i16x4(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulhr.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV64-NEXT: ret i64 [[TMP3]]
+//
+int16x4_t test_pmulhr_i16x4(int16x4_t rs1, int16x4_t rs2) {
+ return __riscv_pmulhr_i16x4(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pmulhru_u16x4(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulhru.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV32-NEXT: ret i64 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i64 @test_pmulhru_u16x4(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulhru.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV64-NEXT: ret i64 [[TMP3]]
+//
+uint16x4_t test_pmulhru_u16x4(uint16x4_t rs1, uint16x4_t rs2) {
+ return __riscv_pmulhru_u16x4(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pmulhrsu_i16x4(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulhrsu.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV32-NEXT: ret i64 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i64 @test_pmulhrsu_i16x4(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulhrsu.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV64-NEXT: ret i64 [[TMP3]]
+//
+int16x4_t test_pmulhrsu_i16x4(int16x4_t rs1, uint16x4_t rs2) {
+ return __riscv_pmulhrsu_i16x4(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pmulh_i32x2(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
+// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulh.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// RV32-NEXT: ret i64 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i64 @test_pmulh_i32x2(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
+// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulh.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// RV64-NEXT: ret i64 [[TMP3]]
+//
+int32x2_t test_pmulh_i32x2(int32x2_t rs1, int32x2_t rs2) {
+ return __riscv_pmulh_i32x2(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pmulhu_u32x2(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
+// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulhu.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// RV32-NEXT: ret i64 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i64 @test_pmulhu_u32x2(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
+// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulhu.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// RV64-NEXT: ret i64 [[TMP3]]
+//
+uint32x2_t test_pmulhu_u32x2(uint32x2_t rs1, uint32x2_t rs2) {
+ return __riscv_pmulhu_u32x2(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pmulhsu_i32x2(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
+// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulhsu.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// RV32-NEXT: ret i64 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i64 @test_pmulhsu_i32x2(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
+// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulhsu.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// RV64-NEXT: ret i64 [[TMP3]]
+//
+int32x2_t test_pmulhsu_i32x2(int32x2_t rs1, uint32x2_t rs2) {
+ return __riscv_pmulhsu_i32x2(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pmulhr_i32x2(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
+// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulhr.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// RV32-NEXT: ret i64 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i64 @test_pmulhr_i32x2(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
+// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulhr.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// RV64-NEXT: ret i64 [[TMP3]]
+//
+int32x2_t test_pmulhr_i32x2(int32x2_t rs1, int32x2_t rs2) {
+ return __riscv_pmulhr_i32x2(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pmulhru_u32x2(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
+// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulhru.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// RV32-NEXT: ret i64 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i64 @test_pmulhru_u32x2(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
+// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulhru.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// RV64-NEXT: ret i64 [[TMP3]]
+//
+uint32x2_t test_pmulhru_u32x2(uint32x2_t rs1, uint32x2_t rs2) {
+ return __riscv_pmulhru_u32x2(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pmulhrsu_i32x2(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
+// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulhrsu.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// RV32-NEXT: ret i64 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i64 @test_pmulhrsu_i32x2(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
+// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulhrsu.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
+// RV64-NEXT: ret i64 [[TMP3]]
+//
+int32x2_t test_pmulhrsu_i32x2(int32x2_t rs1, uint32x2_t rs2) {
+ return __riscv_pmulhrsu_i32x2(rs1, rs2);
+}
+
/* Reinterpret Casts, Packed <-> Scalar (32-bit) */
// RV32-LABEL: define dso_local i32 @test_preinterpret_u8x4_u32(
// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
diff --git a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
index 2af196cdaadc0..c87c59098ff12 100644
--- a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+++ b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
@@ -2495,6 +2495,138 @@ int8x8_t test_psabs_i8x8(int8x8_t a) { return __riscv_psabs_i8x8(a); }
// RV64: psabs.h
int16x4_t test_psabs_i16x4(int16x4_t a) { return __riscv_psabs_i16x4(a); }
+// Packed Multiply High
+// CHECK-LABEL: test_pmulh_i16x2:
+// CHECK: pmulh.h
+int16x2_t test_pmulh_i16x2(int16x2_t a, int16x2_t b) {
+ return __riscv_pmulh_i16x2(a, b);
+}
+
+// CHECK-LABEL: test_pmulhu_u16x2:
+// CHECK: pmulhu.h
+uint16x2_t test_pmulhu_u16x2(uint16x2_t a, uint16x2_t b) {
+ return __riscv_pmulhu_u16x2(a, b);
+}
+
+// CHECK-LABEL: test_pmulhsu_i16x2:
+// CHECK: pmulhsu.h
+int16x2_t test_pmulhsu_i16x2(int16x2_t a, uint16x2_t b) {
+ return __riscv_pmulhsu_i16x2(a, b);
+}
+
+// CHECK-LABEL: test_pmulhr_i16x2:
+// CHECK: pmulhr.h
+int16x2_t test_pmulhr_i16x2(int16x2_t a, int16x2_t b) {
+ return __riscv_pmulhr_i16x2(a, b);
+}
+
+// CHECK-LABEL: test_pmulhru_u16x2:
+// CHECK: pmulhru.h
+uint16x2_t test_pmulhru_u16x2(uint16x2_t a, uint16x2_t b) {
+ return __riscv_pmulhru_u16x2(a, b);
+}
+
+// CHECK-LABEL: test_pmulhrsu_i16x2:
+// CHECK: pmulhrsu.h
+int16x2_t test_pmulhrsu_i16x2(int16x2_t a, uint16x2_t b) {
+ return __riscv_pmulhrsu_i16x2(a, b);
+}
+// CHECK-LABEL: test_pmulh_i16x4:
+// RV32: pmulh.h
+// RV32: pmulh.h
+// RV64: pmulh.h
+int16x4_t test_pmulh_i16x4(int16x4_t a, int16x4_t b) {
+ return __riscv_pmulh_i16x4(a, b);
+}
+
+// CHECK-LABEL: test_pmulhu_u16x4:
+// RV32: pmulhu.h
+// RV32: pmulhu.h
+// RV64: pmulhu.h
+uint16x4_t test_pmulhu_u16x4(uint16x4_t a, uint16x4_t b) {
+ return __riscv_pmulhu_u16x4(a, b);
+}
+
+// CHECK-LABEL: test_pmulhsu_i16x4:
+// RV32: pmulhsu.h
+// RV32: pmulhsu.h
+// RV64: pmulhsu.h
+int16x4_t test_pmulhsu_i16x4(int16x4_t a, uint16x4_t b) {
+ return __riscv_pmulhsu_i16x4(a, b);
+}
+
+// CHECK-LABEL: test_pmulhr_i16x4:
+// RV32: pmulhr.h
+// RV32: pmulhr.h
+// RV64: pmulhr.h
+int16x4_t test_pmulhr_i16x4(int16x4_t a, int16x4_t b) {
+ return __riscv_pmulhr_i16x4(a, b);
+}
+
+// CHECK-LABEL: test_pmulhru_u16x4:
+// RV32: pmulhru.h
+// RV32: pmulhru.h
+// RV64: pmulhru.h
+uint16x4_t test_pmulhru_u16x4(uint16x4_t a, uint16x4_t b) {
+ return __riscv_pmulhru_u16x4(a, b);
+}
+
+// CHECK-LABEL: test_pmulhrsu_i16x4:
+// RV32: pmulhrsu.h
+// RV32: pmulhrsu.h
+// RV64: pmulhrsu.h
+int16x4_t test_pmulhrsu_i16x4(int16x4_t a, uint16x4_t b) {
+ return __riscv_pmulhrsu_i16x4(a, b);
+}
+
+// CHECK-LABEL: test_pmulh_i32x2:
+// RV32: mulh
+// RV32: mulh
+// RV64: pmulh.w
+int32x2_t test_pmulh_i32x2(int32x2_t a, int32x2_t b) {
+ return __riscv_pmulh_i32x2(a, b);
+}
+
+// CHECK-LABEL: test_pmulhu_u32x2:
+// RV32: mulhu
+// RV32: mulhu
+// RV64: pmulhu.w
+uint32x2_t test_pmulhu_u32x2(uint32x2_t a, uint32x2_t b) {
+ return __riscv_pmulhu_u32x2(a, b);
+}
+
+// CHECK-LABEL: test_pmulhsu_i32x2:
+// RV32: mulhsu
+// RV32: mulhsu
+// RV64: pmulhsu.w
+int32x2_t test_pmulhsu_i32x2(int32x2_t a, uint32x2_t b) {
+ return __riscv_pmulhsu_i32x2(a, b);
+}
+
+// CHECK-LABEL: test_pmulhr_i32x2:
+// RV32: mulhr
+// RV32: mulhr
+// RV64: pmulhr.w
+int32x2_t test_pmulhr_i32x2(int32x2_t a, int32x2_t b) {
+ return __riscv_pmulhr_i32x2(a, b);
+}
+
+// CHECK-LABEL: test_pmulhru_u32x2:
+// RV32: mulhru
+// RV32: mulhru
+// RV64: pmulhru.w
+uint32x2_t test_pmulhru_u32x2(uint32x2_t a, uint32x2_t b) {
+ return __riscv_pmulhru_u32x2(a, b);
+}
+
+// CHECK-LABEL: test_pmulhrsu_i32x2:
+// RV32: mulhrsu
+// RV32: mulhrsu
+// RV64: pmulhrsu.w
+int32x2_t test_pmulhrsu_i32x2(int32x2_t a, uint32x2_t b) {
+ return __riscv_pmulhrsu_i32x2(a, b);
+}
+
// CHECK-LABEL: test_pnzip_i8x4:
// CHECK: ppaire.b
int8x4_t test_pnzip_i8x4(int16x2_t rs1, int16x2_t rs2) {
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index fca28455f2117..b65b763fc38a8 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -2061,6 +2061,14 @@ class RVPBinaryIntrinsic
def int_riscv_pabd : RVPBinaryIntrinsic;
def int_riscv_pabdu : RVPBinaryIntrinsic;
+ // Packed Multiply High
+ def int_riscv_pmulh : RVPBinaryIntrinsic;
+ def int_riscv_pmulhu : RVPBinaryIntrinsic;
+ def int_riscv_pmulhsu : RVPBinaryIntrinsic;
+ def int_riscv_pmulhr : RVPBinaryIntrinsic;
+ def int_riscv_pmulhru : RVPBinaryIntrinsic;
+ def int_riscv_pmulhrsu: RVPBinaryIntrinsic;
+
// Packed Saturating and Rounding Shifts.
class RVPShiftIntrinsic
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 45f292a4dbb47..39928f993aa04 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -12144,6 +12144,68 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
return DAG.getNode(Opc, DL, Op.getValueType(), Op.getOperand(1),
Op.getOperand(2));
}
+ case Intrinsic::riscv_pmulh:
+ case Intrinsic::riscv_pmulhu:
+ case Intrinsic::riscv_pmulhsu:
+ case Intrinsic::riscv_pmulhr:
+ case Intrinsic::riscv_pmulhru:
+ case Intrinsic::riscv_pmulhrsu: {
+ unsigned Opc;
+ switch (IntNo) {
+ case Intrinsic::riscv_pmulh:
+ Opc = ISD::MULHS;
+ break;
+ case Intrinsic::riscv_pmulhu:
+ Opc = ISD::MULHU;
+ break;
+ case Intrinsic::riscv_pmulhsu:
+ Opc = RISCVISD::MULHSU;
+ break;
+ case Intrinsic::riscv_pmulhr:
+ Opc = RISCVISD::MULHR;
+ break;
+ case Intrinsic::riscv_pmulhru:
+ Opc = RISCVISD::MULHRU;
+ break;
+ case Intrinsic::riscv_pmulhrsu:
+ Opc = RISCVISD::MULHRSU;
+ break;
+ }
+
+ EVT VT = Op.getValueType();
+ SDValue Rs1 = Op.getOperand(1);
+ SDValue Rs2 = Op.getOperand(2);
+
+ // On RV32 the 64-bit packed vectors (v2i32, v4i16) have no single multiply
+ // high instruction. Split v4i16 into two v2i16 halves (each lowered to a
+ // single pmulh.h via the existing patterns), and v2i32 into two scalar
+ // mulh/mulhu/mulhsu/mulhr* (matched by the generic PatGprGpr patterns).
+ if (!Subtarget.is64Bit()) {
+ if (VT == MVT::v2i32) {
+ MVT XLenVT = Subtarget.getXLenVT();
+ SDValue Lo1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, XLenVT, Rs1,
+ DAG.getVectorIdxConstant(0, DL));
+ SDValue Lo2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, XLenVT, Rs2,
+ DAG.getVectorIdxConstant(0, DL));
+ SDValue Hi1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, XLenVT, Rs1,
+ DAG.getVectorIdxConstant(1, DL));
+ SDValue Hi2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, XLenVT, Rs2,
+ DAG.getVectorIdxConstant(1, DL));
+ SDValue LoRes = DAG.getNode(Opc, DL, XLenVT, Lo1, Lo2);
+ SDValue HiRes = DAG.getNode(Opc, DL, XLenVT, Hi1, Hi2);
+ return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, LoRes, HiRes);
+ }
+ if (VT == MVT::v4i16) {
+ auto [Rs1Lo, Rs1Hi] = DAG.SplitVector(Rs1, DL);
+ auto [Rs2Lo, Rs2Hi] = DAG.SplitVector(Rs2, DL);
+ SDValue LoRes = DAG.getNode(Opc, DL, MVT::v2i16, Rs1Lo, Rs2Lo);
+ SDValue HiRes = DAG.getNode(Opc, DL, MVT::v2i16, Rs1Hi, Rs2Hi);
+ return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoRes, HiRes);
+ }
+ }
+
+ return DAG.getNode(Opc, DL, VT, Rs1, Rs2);
+ }
case Intrinsic::riscv_pssha:
case Intrinsic::riscv_psshar:
case Intrinsic::riscv_psshl:
@@ -16236,7 +16298,13 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
case Intrinsic::riscv_paas:
case Intrinsic::riscv_pasa:
case Intrinsic::riscv_pmerge:
- case Intrinsic::riscv_psabs: {
+ case Intrinsic::riscv_psabs:
+ case Intrinsic::riscv_pmulh:
+ case Intrinsic::riscv_pmulhu:
+ case Intrinsic::riscv_pmulhsu:
+ case Intrinsic::riscv_pmulhr:
+ case Intrinsic::riscv_pmulhru:
+ case Intrinsic::riscv_pmulhrsu: {
EVT VT = N->getValueType(0);
if (!Subtarget.is64Bit() || (VT != MVT::v4i8 && VT != MVT::v2i16))
return;
@@ -16264,6 +16332,24 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
case Intrinsic::riscv_psabs:
Opc = RISCVISD::PSABS;
break;
+ case Intrinsic::riscv_pmulh:
+ Opc = ISD::MULHS;
+ break;
+ case Intrinsic::riscv_pmulhu:
+ Opc = ISD::MULHU;
+ break;
+ case Intrinsic::riscv_pmulhsu:
+ Opc = RISCVISD::MULHSU;
+ break;
+ case Intrinsic::riscv_pmulhr:
+ Opc = RISCVISD::MULHR;
+ break;
+ case Intrinsic::riscv_pmulhru:
+ Opc = RISCVISD::MULHRU;
+ break;
+ case Intrinsic::riscv_pmulhrsu:
+ Opc = RISCVISD::MULHRSU;
+ break;
default:
// pas/psa/psas/pssa/paas/pasa and pmerge: re-emit at the widened type
// rather than lowering to a generic node.
diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
index 8cd7d29dbf7c3..18409cb55be9c 100644
--- a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
@@ -2736,3 +2736,57 @@ define <2 x i16> @test_undef_v2i16() {
; CHECK-NEXT: ret
ret <2 x i16> undef
}
+
+define <2 x i16> @test_pmulh_v2i16(<2 x i16> %a, <2 x i16> %b) {
+; CHECK-LABEL: test_pmulh_v2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pmulh.h a0, a0, a1
+; CHECK-NEXT: ret
+ %res = call <2 x i16> @llvm.riscv.pmulh.v2i16(<2 x i16> %a, <2 x i16> %b)
+ ret <2 x i16> %res
+}
+
+define <2 x i16> @test_pmulhu_v2i16(<2 x i16> %a, <2 x i16> %b) {
+; CHECK-LABEL: test_pmulhu_v2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pmulhu.h a0, a0, a1
+; CHECK-NEXT: ret
+ %res = call <2 x i16> @llvm.riscv.pmulhu.v2i16(<2 x i16> %a, <2 x i16> %b)
+ ret <2 x i16> %res
+}
+
+define <2 x i16> @test_pmulhsu_v2i16(<2 x i16> %a, <2 x i16> %b) {
+; CHECK-LABEL: test_pmulhsu_v2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pmulhsu.h a0, a0, a1
+; CHECK-NEXT: ret
+ %res = call <2 x i16> @llvm.riscv.pmulhsu.v2i16(<2 x i16> %a, <2 x i16> %b)
+ ret <2 x i16> %res
+}
+
+define <2 x i16> @test_pmulhr_v2i16(<2 x i16> %a, <2 x i16> %b) {
+; CHECK-LABEL: test_pmulhr_v2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pmulhr.h a0, a0, a1
+; CHECK-NEXT: ret
+ %res = call <2 x i16> @llvm.riscv.pmulhr.v2i16(<2 x i16> %a, <2 x i16> %b)
+ ret <2 x i16> %res
+}
+
+define <2 x i16> @test_pmulhru_v2i16(<2 x i16> %a, <2 x i16> %b) {
+; CHECK-LABEL: test_pmulhru_v2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pmulhru.h a0, a0, a1
+; CHECK-NEXT: ret
+ %res = call <2 x i16> @llvm.riscv.pmulhru.v2i16(<2 x i16> %a, <2 x i16> %b)
+ ret <2 x i16> %res
+}
+
+define <2 x i16> @test_pmulhrsu_v2i16(<2 x i16> %a, <2 x i16> %b) {
+; CHECK-LABEL: test_pmulhrsu_v2i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pmulhrsu.h a0, a0, a1
+; CHECK-NEXT: ret
+ %res = call <2 x i16> @llvm.riscv.pmulhrsu.v2i16(<2 x i16> %a, <2 x i16> %b)
+ ret <2 x i16> %res
+}
diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
index 3088f49a27396..8fdf057f67ff4 100644
--- a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
@@ -5930,6 +5930,186 @@ define <4 x i16> @test_psabs_v4i16(<4 x i16> %a) {
ret <4 x i16> %res
}
+define <4 x i16> @test_pmulh_v4i16(<4 x i16> %a, <4 x i16> %b) {
+; RV32-LABEL: test_pmulh_v4i16:
+; RV32: # %bb.0:
+; RV32-NEXT: pmulh.h a1, a1, a3
+; RV32-NEXT: pmulh.h a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pmulh_v4i16:
+; RV64: # %bb.0:
+; RV64-NEXT: pmulh.h a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <4 x i16> @llvm.riscv.pmulh.v4i16(<4 x i16> %a, <4 x i16> %b)
+ ret <4 x i16> %res
+}
+
+define <4 x i16> @test_pmulhu_v4i16(<4 x i16> %a, <4 x i16> %b) {
+; RV32-LABEL: test_pmulhu_v4i16:
+; RV32: # %bb.0:
+; RV32-NEXT: pmulhu.h a1, a1, a3
+; RV32-NEXT: pmulhu.h a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pmulhu_v4i16:
+; RV64: # %bb.0:
+; RV64-NEXT: pmulhu.h a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <4 x i16> @llvm.riscv.pmulhu.v4i16(<4 x i16> %a, <4 x i16> %b)
+ ret <4 x i16> %res
+}
+
+define <4 x i16> @test_pmulhsu_v4i16(<4 x i16> %a, <4 x i16> %b) {
+; RV32-LABEL: test_pmulhsu_v4i16:
+; RV32: # %bb.0:
+; RV32-NEXT: pmulhsu.h a1, a1, a3
+; RV32-NEXT: pmulhsu.h a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pmulhsu_v4i16:
+; RV64: # %bb.0:
+; RV64-NEXT: pmulhsu.h a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <4 x i16> @llvm.riscv.pmulhsu.v4i16(<4 x i16> %a, <4 x i16> %b)
+ ret <4 x i16> %res
+}
+
+define <4 x i16> @test_pmulhr_v4i16(<4 x i16> %a, <4 x i16> %b) {
+; RV32-LABEL: test_pmulhr_v4i16:
+; RV32: # %bb.0:
+; RV32-NEXT: pmulhr.h a1, a1, a3
+; RV32-NEXT: pmulhr.h a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pmulhr_v4i16:
+; RV64: # %bb.0:
+; RV64-NEXT: pmulhr.h a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <4 x i16> @llvm.riscv.pmulhr.v4i16(<4 x i16> %a, <4 x i16> %b)
+ ret <4 x i16> %res
+}
+
+define <4 x i16> @test_pmulhru_v4i16(<4 x i16> %a, <4 x i16> %b) {
+; RV32-LABEL: test_pmulhru_v4i16:
+; RV32: # %bb.0:
+; RV32-NEXT: pmulhru.h a1, a1, a3
+; RV32-NEXT: pmulhru.h a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pmulhru_v4i16:
+; RV64: # %bb.0:
+; RV64-NEXT: pmulhru.h a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <4 x i16> @llvm.riscv.pmulhru.v4i16(<4 x i16> %a, <4 x i16> %b)
+ ret <4 x i16> %res
+}
+
+define <4 x i16> @test_pmulhrsu_v4i16(<4 x i16> %a, <4 x i16> %b) {
+; RV32-LABEL: test_pmulhrsu_v4i16:
+; RV32: # %bb.0:
+; RV32-NEXT: pmulhrsu.h a1, a1, a3
+; RV32-NEXT: pmulhrsu.h a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pmulhrsu_v4i16:
+; RV64: # %bb.0:
+; RV64-NEXT: pmulhrsu.h a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <4 x i16> @llvm.riscv.pmulhrsu.v4i16(<4 x i16> %a, <4 x i16> %b)
+ ret <4 x i16> %res
+}
+
+define <2 x i32> @test_pmulh_v2i32(<2 x i32> %a, <2 x i32> %b) {
+; RV32-LABEL: test_pmulh_v2i32:
+; RV32: # %bb.0:
+; RV32-NEXT: mulh a1, a1, a3
+; RV32-NEXT: mulh a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pmulh_v2i32:
+; RV64: # %bb.0:
+; RV64-NEXT: pmulh.w a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <2 x i32> @llvm.riscv.pmulh.v2i32(<2 x i32> %a, <2 x i32> %b)
+ ret <2 x i32> %res
+}
+
+define <2 x i32> @test_pmulhu_v2i32(<2 x i32> %a, <2 x i32> %b) {
+; RV32-LABEL: test_pmulhu_v2i32:
+; RV32: # %bb.0:
+; RV32-NEXT: mulhu a1, a1, a3
+; RV32-NEXT: mulhu a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pmulhu_v2i32:
+; RV64: # %bb.0:
+; RV64-NEXT: pmulhu.w a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <2 x i32> @llvm.riscv.pmulhu.v2i32(<2 x i32> %a, <2 x i32> %b)
+ ret <2 x i32> %res
+}
+
+define <2 x i32> @test_pmulhsu_v2i32(<2 x i32> %a, <2 x i32> %b) {
+; RV32-LABEL: test_pmulhsu_v2i32:
+; RV32: # %bb.0:
+; RV32-NEXT: mulhsu a1, a1, a3
+; RV32-NEXT: mulhsu a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pmulhsu_v2i32:
+; RV64: # %bb.0:
+; RV64-NEXT: pmulhsu.w a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <2 x i32> @llvm.riscv.pmulhsu.v2i32(<2 x i32> %a, <2 x i32> %b)
+ ret <2 x i32> %res
+}
+
+define <2 x i32> @test_pmulhr_v2i32(<2 x i32> %a, <2 x i32> %b) {
+; RV32-LABEL: test_pmulhr_v2i32:
+; RV32: # %bb.0:
+; RV32-NEXT: mulhr a1, a1, a3
+; RV32-NEXT: mulhr a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pmulhr_v2i32:
+; RV64: # %bb.0:
+; RV64-NEXT: pmulhr.w a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <2 x i32> @llvm.riscv.pmulhr.v2i32(<2 x i32> %a, <2 x i32> %b)
+ ret <2 x i32> %res
+}
+
+define <2 x i32> @test_pmulhru_v2i32(<2 x i32> %a, <2 x i32> %b) {
+; RV32-LABEL: test_pmulhru_v2i32:
+; RV32: # %bb.0:
+; RV32-NEXT: mulhru a1, a1, a3
+; RV32-NEXT: mulhru a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pmulhru_v2i32:
+; RV64: # %bb.0:
+; RV64-NEXT: pmulhru.w a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <2 x i32> @llvm.riscv.pmulhru.v2i32(<2 x i32> %a, <2 x i32> %b)
+ ret <2 x i32> %res
+}
+
+define <2 x i32> @test_pmulhrsu_v2i32(<2 x i32> %a, <2 x i32> %b) {
+; RV32-LABEL: test_pmulhrsu_v2i32:
+; RV32: # %bb.0:
+; RV32-NEXT: mulhrsu a1, a1, a3
+; RV32-NEXT: mulhrsu a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pmulhrsu_v2i32:
+; RV64: # %bb.0:
+; RV64-NEXT: pmulhrsu.w a0, a0, a1
+; RV64-NEXT: ret
+ %res = call <2 x i32> @llvm.riscv.pmulhrsu.v2i32(<2 x i32> %a, <2 x i32> %b)
+ ret <2 x i32> %res
+}
+
define <2 x i32> @test_return_zero() {
; RV32-LABEL: test_return_zero:
; RV32: # %bb.0:
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