[clang] [llvm] [RISCV] Update Zvzip support to v0.2 (PR #210603)
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cfe-commits at lists.llvm.org
Mon Jul 20 21:02:23 PDT 2026
https://github.com/renndong updated https://github.com/llvm/llvm-project/pull/210603
>From 714dc83a260c6b4e0fc3bd560ae6339ac31e3a57 Mon Sep 17 00:00:00 2001
From: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: Tue, 7 Jul 2026 16:30:22 +0800
Subject: [PATCH 1/3] [RISCV] Update Zvzip support to 0.2 spec
Spec: https://github.com/riscv/riscv-isa-manual/pull/3233.
Zvzip 0.2 changes `vzip/vunzip` so that `vtype/vl` describe the
interleaved operand. This makes `vzip` produce the current LMUL
result from two half-LMUL sources, and makes `vunzipe/vunzipo`
consume the current LMUL source and produce half-LMUL results.
Update the LLVM IR intrinsics, SelectionDAG patterns, lowering
helpers, Clang RVV builtin generation, and generated intrinsic
tests for that shape. In particular, masked `vunzipe/vunzipo`
APIs are removed because the masked encodings are illegal, and
make masked `vzip` use a mask with one bit per result/interleaved
element.
---
clang/include/clang/Basic/riscv_vector.td | 24 +-
.../clang/Basic/riscv_vector_common.td | 5 +
.../clang/Support/RISCVVIntrinsicUtils.h | 2 +
clang/lib/Sema/SemaRISCV.cpp | 7 +
clang/lib/Support/RISCVVIntrinsicUtils.cpp | 8 +
.../non-policy/non-overloaded/vunzipe.c | 54 -
.../non-policy/non-overloaded/vunzipo.c | 54 -
.../zvfbfmin/non-policy/non-overloaded/vzip.c | 30 +-
.../zvfbfmin/non-policy/overloaded/vunzipe.c | 54 -
.../zvfbfmin/non-policy/overloaded/vunzipo.c | 54 -
.../zvfbfmin/non-policy/overloaded/vzip.c | 30 +-
.../zvfbfmin/policy/non-overloaded/vunzipe.c | 164 --
.../zvfbfmin/policy/non-overloaded/vunzipo.c | 164 --
.../zvfbfmin/policy/non-overloaded/vzip.c | 90 +-
.../zvfbfmin/policy/overloaded/vunzipe.c | 164 --
.../zvfbfmin/policy/overloaded/vunzipo.c | 164 --
.../zvfbfmin/policy/overloaded/vzip.c | 90 +-
.../zvzip/non-policy/non-overloaded/vunzipe.c | 482 -----
.../zvzip/non-policy/non-overloaded/vunzipo.c | 482 -----
.../zvzip/non-policy/non-overloaded/vzip.c | 288 +--
.../zvzip/non-policy/overloaded/vunzipe.c | 482 -----
.../zvzip/non-policy/overloaded/vunzipo.c | 482 -----
.../zvzip/non-policy/overloaded/vzip.c | 288 +--
.../zvzip/policy/non-overloaded/vunzipe.c | 1583 -----------------
.../zvzip/policy/non-overloaded/vunzipo.c | 1583 -----------------
.../zvzip/policy/non-overloaded/vzip.c | 864 ++++-----
.../zvzip/policy/overloaded/vunzipe.c | 1583 -----------------
.../zvzip/policy/overloaded/vunzipo.c | 1583 -----------------
.../zvzip/policy/overloaded/vzip.c | 864 ++++-----
.../Driver/print-supported-extensions-riscv.c | 2 +-
.../test/Preprocessor/riscv-target-features.c | 6 +-
clang/utils/TableGen/RISCVVEmitter.cpp | 12 +
llvm/docs/RISCVUsage.rst | 2 +-
llvm/include/llvm/IR/IntrinsicsRISCV.td | 12 +-
llvm/lib/Target/RISCV/RISCVFeatures.td | 2 +-
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 44 +-
llvm/lib/Target/RISCV/RISCVInstrInfoZvzip.td | 105 +-
llvm/test/CodeGen/RISCV/attributes.ll | 4 +-
.../fixed-vectors-shuffle-deinterleave2.ll | 33 +-
.../fixed-vectors-shuffle-int-interleave.ll | 131 +-
.../RISCV/rvv/vector-deinterleave-fixed.ll | 30 +-
.../CodeGen/RISCV/rvv/vector-deinterleave.ll | 110 +-
.../RISCV/rvv/vector-interleave-fixed.ll | 33 +-
.../CodeGen/RISCV/rvv/vector-interleave.ll | 86 +-
llvm/test/CodeGen/RISCV/rvv/vunzipe.ll | 525 +-----
llvm/test/CodeGen/RISCV/rvv/vunzipo.ll | 525 +-----
llvm/test/CodeGen/RISCV/rvv/vzip.ll | 256 +--
llvm/test/MC/RISCV/attribute-arch.s | 4 +-
llvm/test/MC/RISCV/rvv/zvzip-invalid.s | 16 +-
llvm/test/MC/RISCV/rvv/zvzip.s | 8 -
.../TargetParser/RISCVISAInfoTest.cpp | 2 +-
51 files changed, 1861 insertions(+), 11809 deletions(-)
diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
index c5ce8b7ae8fc1..8bc68888edd52 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -2149,15 +2149,27 @@ let RequiredFeatures = ["zvdot4a8i"] in {
let UnMaskedPolicyScheme = HasPassthruOperand in {
let RequiredFeatures = ["zvzip"] in {
// Signed and floating type
- defm vzip : RVVOutOp0BuiltinSet<"vzip", "csilxfdy", [["vv", "d", "dvv"]]>;
- defm vunzipe : RVVOutOp0BuiltinSet<"vunzipe", "csilxfdy", [["v", "v", "vd"]]>;
- defm vunzipo : RVVOutOp0BuiltinSet<"vunzipo", "csilxfdy", [["v", "v", "vd"]]>;
+ let MaskedPrototypeHasResultMask = true in
+ defm vzip : RVVOutOp0BuiltinSet<"vzip", "csilxfdy",
+ [["vv", "d", "dvv"]]>;
+ let HasMasked = false in {
+ defm vunzipe : RVVOutOp0BuiltinSet<"vunzipe", "csilxfdy",
+ [["v", "v", "vd"]]>;
+ defm vunzipo : RVVOutOp0BuiltinSet<"vunzipo", "csilxfdy",
+ [["v", "v", "vd"]]>;
+ }
defm vpaire : RVVOutBuiltinSet<"vpaire", "csilxfdy", [["vv", "v", "vvv"]]>;
defm vpairo : RVVOutBuiltinSet<"vpairo", "csilxfdy", [["vv", "v", "vvv"]]>;
// Unsigned
- defm vzip : RVVOutOp0BuiltinSet<"vzip", "csil", [["vv", "Ud", "UdUvUv"]]>;
- defm vunzipe : RVVOutOp0BuiltinSet<"vunzipe", "csil", [["v", "Uv", "UvUd"]]>;
- defm vunzipo : RVVOutOp0BuiltinSet<"vunzipo", "csil", [["v", "Uv", "UvUd"]]>;
+ let MaskedPrototypeHasResultMask = true in
+ defm vzip : RVVOutOp0BuiltinSet<"vzip", "csil",
+ [["vv", "Ud", "UdUvUv"]]>;
+ let HasMasked = false in {
+ defm vunzipe : RVVOutOp0BuiltinSet<"vunzipe", "csil",
+ [["v", "Uv", "UvUd"]]>;
+ defm vunzipo : RVVOutOp0BuiltinSet<"vunzipo", "csil",
+ [["v", "Uv", "UvUd"]]>;
+ }
defm vpaire : RVVOutBuiltinSet<"vpaire", "csil", [["vv", "Uv", "UvUvUv"]]>;
defm vpairo : RVVOutBuiltinSet<"vpairo", "csil", [["vv", "Uv", "UvUvUv"]]>;
}
diff --git a/clang/include/clang/Basic/riscv_vector_common.td b/clang/include/clang/Basic/riscv_vector_common.td
index 739bbdd6f66e6..bef07556634fa 100644
--- a/clang/include/clang/Basic/riscv_vector_common.td
+++ b/clang/include/clang/Basic/riscv_vector_common.td
@@ -186,6 +186,11 @@ class RVVBuiltin<string suffix, string prototype, string type_range,
// This builtin has a masked form.
bit HasMasked = true;
+ // The masked form's predicate operand normally has the same LMUL as the
+ // unmasked base type. Some mixed-LMUL instructions instead predicate the
+ // result elements.
+ bit MaskedPrototypeHasResultMask = false;
+
// This is used by intrinsics that need vtype.altfmt
bit AltFmt = false;
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
index 3ea5725057f05..d7c8a2de16b3b 100644
--- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -37,6 +37,7 @@ enum class VectorTypeModifier : uint8_t {
Widening8XVector,
DoubleLMULVector,
MaskVector,
+ DoubleLMULMaskVector,
Log2EEW3,
Log2EEW4,
Log2EEW5,
@@ -543,6 +544,7 @@ struct RVVIntrinsicRecord {
bool HasTailPolicy : 1;
bool HasMaskPolicy : 1;
bool HasFRMRoundModeOp : 1;
+ bool MaskedPrototypeHasResultMask : 1;
bool AltFmt : 1;
bool IsTuple : 1;
LLVM_PREFERRED_TYPE(PolicyScheme)
diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp
index 9647a7d913744..e263d88bb914c 100644
--- a/clang/lib/Sema/SemaRISCV.cpp
+++ b/clang/lib/Sema/SemaRISCV.cpp
@@ -273,6 +273,9 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
BasicProtoSeq, /*IsMasked=*/true, Record.HasMaskedOffOperand,
Record.HasVL, Record.NF, MaskedPolicyScheme, DefaultPolicy,
Record.IsTuple);
+ if (Record.HasMasked && Record.MaskedPrototypeHasResultMask)
+ ProtoMaskSeq[1] = PrototypeDescriptor(
+ BaseTypeModifier::Vector, VectorTypeModifier::DoubleLMULMaskVector);
bool UnMaskedHasPolicy = UnMaskedPolicyScheme != PolicyScheme::SchemeNone;
bool MaskedHasPolicy = MaskedPolicyScheme != PolicyScheme::SchemeNone;
@@ -343,6 +346,10 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
BasicProtoSeq, /*IsMasked=*/true, Record.HasMaskedOffOperand,
Record.HasVL, Record.NF, MaskedPolicyScheme, P,
Record.IsTuple);
+ if (Record.MaskedPrototypeHasResultMask)
+ PolicyPrototype[1] =
+ PrototypeDescriptor(BaseTypeModifier::Vector,
+ VectorTypeModifier::DoubleLMULMaskVector);
std::optional<RVVTypes> PolicyTypes = TypeCache.computeTypes(
BaseType, Log2LMUL, Record.NF, PolicyPrototype);
InitRVVIntrinsic(Record, SuffixStr, OverloadedSuffixStr,
diff --git a/clang/lib/Support/RISCVVIntrinsicUtils.cpp b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
index 5031bf5a1a8ff..a01a39a3b5f4c 100644
--- a/clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -774,6 +774,12 @@ void RVVType::applyModifier(const PrototypeDescriptor &Transformer) {
Scale = LMUL.getScale(ElementBitwidth);
ElementBitwidth = 1;
break;
+ case VectorTypeModifier::DoubleLMULMaskVector:
+ ScalarType = ScalarTypeKind::Boolean;
+ LMUL.MulLog2LMUL(1);
+ Scale = LMUL.getScale(ElementBitwidth);
+ ElementBitwidth = 1;
+ break;
case VectorTypeModifier::Log2EEW3:
applyLog2EEW(3);
break;
@@ -1301,6 +1307,8 @@ raw_ostream &operator<<(raw_ostream &OS, const RVVIntrinsicRecord &Record) {
OS << "/*HasTailPolicy=*/" << (int)Record.HasTailPolicy << ", ";
OS << "/*HasMaskPolicy=*/" << (int)Record.HasMaskPolicy << ", ";
OS << "/*HasFRMRoundModeOp=*/" << (int)Record.HasFRMRoundModeOp << ", ";
+ OS << "/*MaskedPrototypeHasResultMask=*/"
+ << (int)Record.MaskedPrototypeHasResultMask << ", ";
OS << "/*AltFmt=*/" << (int)Record.AltFmt << ",";
OS << "/*IsTuple=*/" << (int)Record.IsTuple << ", ";
OS << "/*UnMaskedPolicyScheme=*/" << (PolicyScheme)Record.UnMaskedPolicyScheme
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c
index 27da4aab99204..e87a2ac6d7818 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c
@@ -59,57 +59,3 @@ vbfloat16m4_t test_vunzipe_v_bf16m4(vbfloat16m8_t vs, size_t vl) {
return __riscv_vunzipe_v_bf16m4(vs, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vunzipe_v_bf16mf4_m(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vunzipe.mask.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 2 x bfloat> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
-//
-vbfloat16mf4_t test_vunzipe_v_bf16mf4_m(vbool64_t vm, vbfloat16mf2_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_bf16mf4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vunzipe_v_bf16mf2_m(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vunzipe.mask.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 4 x bfloat> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
-//
-vbfloat16mf2_t test_vunzipe_v_bf16mf2_m(vbool32_t vm, vbfloat16m1_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_bf16mf2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vunzipe_v_bf16m1_m(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vunzipe.mask.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 8 x bfloat> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
-//
-vbfloat16m1_t test_vunzipe_v_bf16m1_m(vbool16_t vm, vbfloat16m2_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_bf16m1_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vunzipe_v_bf16m2_m(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vunzipe.mask.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 16 x bfloat> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
-//
-vbfloat16m2_t test_vunzipe_v_bf16m2_m(vbool8_t vm, vbfloat16m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_bf16m2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vunzipe_v_bf16m4_m(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vunzipe.mask.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 32 x bfloat> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
-//
-vbfloat16m4_t test_vunzipe_v_bf16m4_m(vbool4_t vm, vbfloat16m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_bf16m4_m(vm, vs, vl);
-}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c
index d901e5cc6f8dc..cdd036aae8907 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c
@@ -59,57 +59,3 @@ vbfloat16m4_t test_vunzipo_v_bf16m4(vbfloat16m8_t vs, size_t vl) {
return __riscv_vunzipo_v_bf16m4(vs, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vunzipo_v_bf16mf4_m(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vunzipo.mask.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 2 x bfloat> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
-//
-vbfloat16mf4_t test_vunzipo_v_bf16mf4_m(vbool64_t vm, vbfloat16mf2_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_bf16mf4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vunzipo_v_bf16mf2_m(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vunzipo.mask.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 4 x bfloat> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
-//
-vbfloat16mf2_t test_vunzipo_v_bf16mf2_m(vbool32_t vm, vbfloat16m1_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_bf16mf2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vunzipo_v_bf16m1_m(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vunzipo.mask.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 8 x bfloat> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
-//
-vbfloat16m1_t test_vunzipo_v_bf16m1_m(vbool16_t vm, vbfloat16m2_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_bf16m1_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vunzipo_v_bf16m2_m(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vunzipo.mask.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 16 x bfloat> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
-//
-vbfloat16m2_t test_vunzipo_v_bf16m2_m(vbool8_t vm, vbfloat16m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_bf16m2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vunzipo_v_bf16m4_m(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vunzipo.mask.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 32 x bfloat> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
-//
-vbfloat16m4_t test_vunzipo_v_bf16m4_m(vbool4_t vm, vbfloat16m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_bf16m4_m(vm, vs, vl);
-}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c
index 6b36bc7347772..c6fe3cff4ee9b 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c
@@ -65,56 +65,56 @@ vbfloat16m8_t test_vzip_vv_bf16m8(vbfloat16m4_t vs2, vbfloat16m4_t vs1,
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_m(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], <vscale x 1 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], <vscale x 1 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x bfloat> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x bfloat> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
//
-vbfloat16mf2_t test_vzip_vv_bf16mf2_m(vbool64_t vm, vbfloat16mf4_t vs2,
+vbfloat16mf2_t test_vzip_vv_bf16mf2_m(vbool32_t vm, vbfloat16mf4_t vs2,
vbfloat16mf4_t vs1, size_t vl) {
return __riscv_vzip_vv_bf16mf2_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_m(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], <vscale x 2 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], <vscale x 2 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x bfloat> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x bfloat> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
//
-vbfloat16m1_t test_vzip_vv_bf16m1_m(vbool32_t vm, vbfloat16mf2_t vs2,
+vbfloat16m1_t test_vzip_vv_bf16m1_m(vbool16_t vm, vbfloat16mf2_t vs2,
vbfloat16mf2_t vs1, size_t vl) {
return __riscv_vzip_vv_bf16m1_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_m(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], <vscale x 4 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], <vscale x 4 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x bfloat> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x bfloat> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
//
-vbfloat16m2_t test_vzip_vv_bf16m2_m(vbool16_t vm, vbfloat16m1_t vs2,
+vbfloat16m2_t test_vzip_vv_bf16m2_m(vbool8_t vm, vbfloat16m1_t vs2,
vbfloat16m1_t vs1, size_t vl) {
return __riscv_vzip_vv_bf16m2_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4_m(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], <vscale x 8 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], <vscale x 8 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vzip.mask.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x bfloat> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vzip.mask.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x bfloat> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
//
-vbfloat16m4_t test_vzip_vv_bf16m4_m(vbool8_t vm, vbfloat16m2_t vs2,
+vbfloat16m4_t test_vzip_vv_bf16m4_m(vbool4_t vm, vbfloat16m2_t vs2,
vbfloat16m2_t vs1, size_t vl) {
return __riscv_vzip_vv_bf16m4_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vzip_vv_bf16m8_m(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], <vscale x 16 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 32 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], <vscale x 16 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vzip.mask.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x bfloat> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vzip.mask.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x bfloat> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]]
//
-vbfloat16m8_t test_vzip_vv_bf16m8_m(vbool4_t vm, vbfloat16m4_t vs2,
+vbfloat16m8_t test_vzip_vv_bf16m8_m(vbool2_t vm, vbfloat16m4_t vs2,
vbfloat16m4_t vs1, size_t vl) {
return __riscv_vzip_vv_bf16m8_m(vm, vs2, vs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c
index bc8d13f0d7998..e52d503c695a1 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c
@@ -59,57 +59,3 @@ vbfloat16m4_t test_vunzipe_v_bf16m4(vbfloat16m8_t vs, size_t vl) {
return __riscv_vunzipe(vs, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vunzipe_v_bf16mf4_m(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vunzipe.mask.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 2 x bfloat> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
-//
-vbfloat16mf4_t test_vunzipe_v_bf16mf4_m(vbool64_t vm, vbfloat16mf2_t vs,
- size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vunzipe_v_bf16mf2_m(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vunzipe.mask.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 4 x bfloat> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
-//
-vbfloat16mf2_t test_vunzipe_v_bf16mf2_m(vbool32_t vm, vbfloat16m1_t vs,
- size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vunzipe_v_bf16m1_m(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vunzipe.mask.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 8 x bfloat> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
-//
-vbfloat16m1_t test_vunzipe_v_bf16m1_m(vbool16_t vm, vbfloat16m2_t vs,
- size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vunzipe_v_bf16m2_m(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vunzipe.mask.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 16 x bfloat> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
-//
-vbfloat16m2_t test_vunzipe_v_bf16m2_m(vbool8_t vm, vbfloat16m4_t vs,
- size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vunzipe_v_bf16m4_m(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vunzipe.mask.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 32 x bfloat> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
-//
-vbfloat16m4_t test_vunzipe_v_bf16m4_m(vbool4_t vm, vbfloat16m8_t vs,
- size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c
index 9608f3e71e12c..d7db120dcefc3 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c
@@ -59,57 +59,3 @@ vbfloat16m4_t test_vunzipo_v_bf16m4(vbfloat16m8_t vs, size_t vl) {
return __riscv_vunzipo(vs, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vunzipo_v_bf16mf4_m(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vunzipo.mask.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 2 x bfloat> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
-//
-vbfloat16mf4_t test_vunzipo_v_bf16mf4_m(vbool64_t vm, vbfloat16mf2_t vs,
- size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vunzipo_v_bf16mf2_m(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vunzipo.mask.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 4 x bfloat> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
-//
-vbfloat16mf2_t test_vunzipo_v_bf16mf2_m(vbool32_t vm, vbfloat16m1_t vs,
- size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vunzipo_v_bf16m1_m(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vunzipo.mask.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 8 x bfloat> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
-//
-vbfloat16m1_t test_vunzipo_v_bf16m1_m(vbool16_t vm, vbfloat16m2_t vs,
- size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vunzipo_v_bf16m2_m(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vunzipo.mask.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 16 x bfloat> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
-//
-vbfloat16m2_t test_vunzipo_v_bf16m2_m(vbool8_t vm, vbfloat16m4_t vs,
- size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vunzipo_v_bf16m4_m(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vunzipo.mask.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 32 x bfloat> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
-//
-vbfloat16m4_t test_vunzipo_v_bf16m4_m(vbool4_t vm, vbfloat16m8_t vs,
- size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c
index e758fb13516b2..2cc6a23634eb9 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c
@@ -65,56 +65,56 @@ vbfloat16m8_t test_vzip_vv_bf16m8(vbfloat16m4_t vs2, vbfloat16m4_t vs1,
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_m(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], <vscale x 1 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], <vscale x 1 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x bfloat> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x bfloat> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
//
-vbfloat16mf2_t test_vzip_vv_bf16mf2_m(vbool64_t vm, vbfloat16mf4_t vs2,
+vbfloat16mf2_t test_vzip_vv_bf16mf2_m(vbool32_t vm, vbfloat16mf4_t vs2,
vbfloat16mf4_t vs1, size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_m(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], <vscale x 2 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], <vscale x 2 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x bfloat> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x bfloat> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
//
-vbfloat16m1_t test_vzip_vv_bf16m1_m(vbool32_t vm, vbfloat16mf2_t vs2,
+vbfloat16m1_t test_vzip_vv_bf16m1_m(vbool16_t vm, vbfloat16mf2_t vs2,
vbfloat16mf2_t vs1, size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_m(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], <vscale x 4 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], <vscale x 4 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x bfloat> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x bfloat> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
//
-vbfloat16m2_t test_vzip_vv_bf16m2_m(vbool16_t vm, vbfloat16m1_t vs2,
+vbfloat16m2_t test_vzip_vv_bf16m2_m(vbool8_t vm, vbfloat16m1_t vs2,
vbfloat16m1_t vs1, size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4_m(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], <vscale x 8 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], <vscale x 8 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vzip.mask.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x bfloat> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vzip.mask.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x bfloat> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
//
-vbfloat16m4_t test_vzip_vv_bf16m4_m(vbool8_t vm, vbfloat16m2_t vs2,
+vbfloat16m4_t test_vzip_vv_bf16m4_m(vbool4_t vm, vbfloat16m2_t vs2,
vbfloat16m2_t vs1, size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vzip_vv_bf16m8_m(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], <vscale x 16 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 32 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], <vscale x 16 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vzip.mask.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x bfloat> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vzip.mask.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x bfloat> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]]
//
-vbfloat16m8_t test_vzip_vv_bf16m8_m(vbool4_t vm, vbfloat16m4_t vs2,
+vbfloat16m8_t test_vzip_vv_bf16m8_m(vbool2_t vm, vbfloat16m4_t vs2,
vbfloat16m4_t vs1, size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c
index 2b5d070be15c8..aee02bcb8ebfb 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c
@@ -64,167 +64,3 @@ vbfloat16m4_t test_vunzipe_v_bf16m4_tu(vbfloat16m4_t vd, vbfloat16m8_t vs,
return __riscv_vunzipe_v_bf16m4_tu(vd, vs, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vunzipe_v_bf16mf4_tum(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x bfloat> [[VD:%.*]], <vscale x 2 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vunzipe.mask.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> [[VD]], <vscale x 2 x bfloat> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
-//
-vbfloat16mf4_t test_vunzipe_v_bf16mf4_tum(vbool64_t vm, vbfloat16mf4_t vd,
- vbfloat16mf2_t vs, size_t vl) {
- return __riscv_vunzipe_v_bf16mf4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vunzipe_v_bf16mf2_tum(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], <vscale x 4 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vunzipe.mask.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 4 x bfloat> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
-//
-vbfloat16mf2_t test_vunzipe_v_bf16mf2_tum(vbool32_t vm, vbfloat16mf2_t vd,
- vbfloat16m1_t vs, size_t vl) {
- return __riscv_vunzipe_v_bf16mf2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vunzipe_v_bf16m1_tum(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], <vscale x 8 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vunzipe.mask.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 8 x bfloat> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
-//
-vbfloat16m1_t test_vunzipe_v_bf16m1_tum(vbool16_t vm, vbfloat16m1_t vd,
- vbfloat16m2_t vs, size_t vl) {
- return __riscv_vunzipe_v_bf16m1_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vunzipe_v_bf16m2_tum(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], <vscale x 16 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vunzipe.mask.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 16 x bfloat> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
-//
-vbfloat16m2_t test_vunzipe_v_bf16m2_tum(vbool8_t vm, vbfloat16m2_t vd,
- vbfloat16m4_t vs, size_t vl) {
- return __riscv_vunzipe_v_bf16m2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vunzipe_v_bf16m4_tum(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], <vscale x 32 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vunzipe.mask.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 32 x bfloat> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
-//
-vbfloat16m4_t test_vunzipe_v_bf16m4_tum(vbool4_t vm, vbfloat16m4_t vd,
- vbfloat16m8_t vs, size_t vl) {
- return __riscv_vunzipe_v_bf16m4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vunzipe_v_bf16mf4_tumu(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x bfloat> [[VD:%.*]], <vscale x 2 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vunzipe.mask.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> [[VD]], <vscale x 2 x bfloat> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
-//
-vbfloat16mf4_t test_vunzipe_v_bf16mf4_tumu(vbool64_t vm, vbfloat16mf4_t vd,
- vbfloat16mf2_t vs, size_t vl) {
- return __riscv_vunzipe_v_bf16mf4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vunzipe_v_bf16mf2_tumu(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], <vscale x 4 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vunzipe.mask.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 4 x bfloat> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
-//
-vbfloat16mf2_t test_vunzipe_v_bf16mf2_tumu(vbool32_t vm, vbfloat16mf2_t vd,
- vbfloat16m1_t vs, size_t vl) {
- return __riscv_vunzipe_v_bf16mf2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vunzipe_v_bf16m1_tumu(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], <vscale x 8 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vunzipe.mask.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 8 x bfloat> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
-//
-vbfloat16m1_t test_vunzipe_v_bf16m1_tumu(vbool16_t vm, vbfloat16m1_t vd,
- vbfloat16m2_t vs, size_t vl) {
- return __riscv_vunzipe_v_bf16m1_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vunzipe_v_bf16m2_tumu(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], <vscale x 16 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vunzipe.mask.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 16 x bfloat> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
-//
-vbfloat16m2_t test_vunzipe_v_bf16m2_tumu(vbool8_t vm, vbfloat16m2_t vd,
- vbfloat16m4_t vs, size_t vl) {
- return __riscv_vunzipe_v_bf16m2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vunzipe_v_bf16m4_tumu(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], <vscale x 32 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vunzipe.mask.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 32 x bfloat> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
-//
-vbfloat16m4_t test_vunzipe_v_bf16m4_tumu(vbool4_t vm, vbfloat16m4_t vd,
- vbfloat16m8_t vs, size_t vl) {
- return __riscv_vunzipe_v_bf16m4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vunzipe_v_bf16mf4_mu(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x bfloat> [[VD:%.*]], <vscale x 2 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vunzipe.mask.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> [[VD]], <vscale x 2 x bfloat> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
-//
-vbfloat16mf4_t test_vunzipe_v_bf16mf4_mu(vbool64_t vm, vbfloat16mf4_t vd,
- vbfloat16mf2_t vs, size_t vl) {
- return __riscv_vunzipe_v_bf16mf4_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vunzipe_v_bf16mf2_mu(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], <vscale x 4 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vunzipe.mask.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 4 x bfloat> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
-//
-vbfloat16mf2_t test_vunzipe_v_bf16mf2_mu(vbool32_t vm, vbfloat16mf2_t vd,
- vbfloat16m1_t vs, size_t vl) {
- return __riscv_vunzipe_v_bf16mf2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vunzipe_v_bf16m1_mu(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], <vscale x 8 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vunzipe.mask.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 8 x bfloat> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
-//
-vbfloat16m1_t test_vunzipe_v_bf16m1_mu(vbool16_t vm, vbfloat16m1_t vd,
- vbfloat16m2_t vs, size_t vl) {
- return __riscv_vunzipe_v_bf16m1_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vunzipe_v_bf16m2_mu(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], <vscale x 16 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vunzipe.mask.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 16 x bfloat> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
-//
-vbfloat16m2_t test_vunzipe_v_bf16m2_mu(vbool8_t vm, vbfloat16m2_t vd,
- vbfloat16m4_t vs, size_t vl) {
- return __riscv_vunzipe_v_bf16m2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vunzipe_v_bf16m4_mu(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], <vscale x 32 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vunzipe.mask.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 32 x bfloat> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
-//
-vbfloat16m4_t test_vunzipe_v_bf16m4_mu(vbool4_t vm, vbfloat16m4_t vd,
- vbfloat16m8_t vs, size_t vl) {
- return __riscv_vunzipe_v_bf16m4_mu(vm, vd, vs, vl);
-}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c
index a672a95c6305e..04c60232ee1e4 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c
@@ -64,167 +64,3 @@ vbfloat16m4_t test_vunzipo_v_bf16m4_tu(vbfloat16m4_t vd, vbfloat16m8_t vs,
return __riscv_vunzipo_v_bf16m4_tu(vd, vs, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vunzipo_v_bf16mf4_tum(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x bfloat> [[VD:%.*]], <vscale x 2 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vunzipo.mask.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> [[VD]], <vscale x 2 x bfloat> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
-//
-vbfloat16mf4_t test_vunzipo_v_bf16mf4_tum(vbool64_t vm, vbfloat16mf4_t vd,
- vbfloat16mf2_t vs, size_t vl) {
- return __riscv_vunzipo_v_bf16mf4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vunzipo_v_bf16mf2_tum(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], <vscale x 4 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vunzipo.mask.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 4 x bfloat> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
-//
-vbfloat16mf2_t test_vunzipo_v_bf16mf2_tum(vbool32_t vm, vbfloat16mf2_t vd,
- vbfloat16m1_t vs, size_t vl) {
- return __riscv_vunzipo_v_bf16mf2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vunzipo_v_bf16m1_tum(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], <vscale x 8 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vunzipo.mask.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 8 x bfloat> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
-//
-vbfloat16m1_t test_vunzipo_v_bf16m1_tum(vbool16_t vm, vbfloat16m1_t vd,
- vbfloat16m2_t vs, size_t vl) {
- return __riscv_vunzipo_v_bf16m1_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vunzipo_v_bf16m2_tum(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], <vscale x 16 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vunzipo.mask.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 16 x bfloat> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
-//
-vbfloat16m2_t test_vunzipo_v_bf16m2_tum(vbool8_t vm, vbfloat16m2_t vd,
- vbfloat16m4_t vs, size_t vl) {
- return __riscv_vunzipo_v_bf16m2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vunzipo_v_bf16m4_tum(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], <vscale x 32 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vunzipo.mask.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 32 x bfloat> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
-//
-vbfloat16m4_t test_vunzipo_v_bf16m4_tum(vbool4_t vm, vbfloat16m4_t vd,
- vbfloat16m8_t vs, size_t vl) {
- return __riscv_vunzipo_v_bf16m4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vunzipo_v_bf16mf4_tumu(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x bfloat> [[VD:%.*]], <vscale x 2 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vunzipo.mask.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> [[VD]], <vscale x 2 x bfloat> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
-//
-vbfloat16mf4_t test_vunzipo_v_bf16mf4_tumu(vbool64_t vm, vbfloat16mf4_t vd,
- vbfloat16mf2_t vs, size_t vl) {
- return __riscv_vunzipo_v_bf16mf4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vunzipo_v_bf16mf2_tumu(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], <vscale x 4 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vunzipo.mask.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 4 x bfloat> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
-//
-vbfloat16mf2_t test_vunzipo_v_bf16mf2_tumu(vbool32_t vm, vbfloat16mf2_t vd,
- vbfloat16m1_t vs, size_t vl) {
- return __riscv_vunzipo_v_bf16mf2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vunzipo_v_bf16m1_tumu(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], <vscale x 8 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vunzipo.mask.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 8 x bfloat> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
-//
-vbfloat16m1_t test_vunzipo_v_bf16m1_tumu(vbool16_t vm, vbfloat16m1_t vd,
- vbfloat16m2_t vs, size_t vl) {
- return __riscv_vunzipo_v_bf16m1_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vunzipo_v_bf16m2_tumu(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], <vscale x 16 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vunzipo.mask.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 16 x bfloat> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
-//
-vbfloat16m2_t test_vunzipo_v_bf16m2_tumu(vbool8_t vm, vbfloat16m2_t vd,
- vbfloat16m4_t vs, size_t vl) {
- return __riscv_vunzipo_v_bf16m2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vunzipo_v_bf16m4_tumu(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], <vscale x 32 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vunzipo.mask.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 32 x bfloat> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
-//
-vbfloat16m4_t test_vunzipo_v_bf16m4_tumu(vbool4_t vm, vbfloat16m4_t vd,
- vbfloat16m8_t vs, size_t vl) {
- return __riscv_vunzipo_v_bf16m4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vunzipo_v_bf16mf4_mu(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x bfloat> [[VD:%.*]], <vscale x 2 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vunzipo.mask.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> [[VD]], <vscale x 2 x bfloat> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
-//
-vbfloat16mf4_t test_vunzipo_v_bf16mf4_mu(vbool64_t vm, vbfloat16mf4_t vd,
- vbfloat16mf2_t vs, size_t vl) {
- return __riscv_vunzipo_v_bf16mf4_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vunzipo_v_bf16mf2_mu(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], <vscale x 4 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vunzipo.mask.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 4 x bfloat> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
-//
-vbfloat16mf2_t test_vunzipo_v_bf16mf2_mu(vbool32_t vm, vbfloat16mf2_t vd,
- vbfloat16m1_t vs, size_t vl) {
- return __riscv_vunzipo_v_bf16mf2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vunzipo_v_bf16m1_mu(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], <vscale x 8 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vunzipo.mask.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 8 x bfloat> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
-//
-vbfloat16m1_t test_vunzipo_v_bf16m1_mu(vbool16_t vm, vbfloat16m1_t vd,
- vbfloat16m2_t vs, size_t vl) {
- return __riscv_vunzipo_v_bf16m1_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vunzipo_v_bf16m2_mu(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], <vscale x 16 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vunzipo.mask.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 16 x bfloat> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
-//
-vbfloat16m2_t test_vunzipo_v_bf16m2_mu(vbool8_t vm, vbfloat16m2_t vd,
- vbfloat16m4_t vs, size_t vl) {
- return __riscv_vunzipo_v_bf16m2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vunzipo_v_bf16m4_mu(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], <vscale x 32 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vunzipo.mask.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 32 x bfloat> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
-//
-vbfloat16m4_t test_vunzipo_v_bf16m4_mu(vbool4_t vm, vbfloat16m4_t vd,
- vbfloat16m8_t vs, size_t vl) {
- return __riscv_vunzipo_v_bf16m4_mu(vm, vd, vs, vl);
-}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c
index 90e8952297c6a..a92301ae0a84f 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c
@@ -65,180 +65,180 @@ vbfloat16m8_t test_vzip_vv_bf16m8_tu(vbfloat16m8_t vd, vbfloat16m4_t vs2,
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_tum(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], <vscale x 1 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], <vscale x 1 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x bfloat> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x bfloat> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
//
-vbfloat16mf2_t test_vzip_vv_bf16mf2_tum(vbool64_t vm, vbfloat16mf2_t vd,
+vbfloat16mf2_t test_vzip_vv_bf16mf2_tum(vbool32_t vm, vbfloat16mf2_t vd,
vbfloat16mf4_t vs2, vbfloat16mf4_t vs1,
size_t vl) {
return __riscv_vzip_vv_bf16mf2_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_tum(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], <vscale x 2 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], <vscale x 2 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x bfloat> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x bfloat> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
//
-vbfloat16m1_t test_vzip_vv_bf16m1_tum(vbool32_t vm, vbfloat16m1_t vd,
+vbfloat16m1_t test_vzip_vv_bf16m1_tum(vbool16_t vm, vbfloat16m1_t vd,
vbfloat16mf2_t vs2, vbfloat16mf2_t vs1,
size_t vl) {
return __riscv_vzip_vv_bf16m1_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_tum(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], <vscale x 4 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], <vscale x 4 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x bfloat> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x bfloat> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
//
-vbfloat16m2_t test_vzip_vv_bf16m2_tum(vbool16_t vm, vbfloat16m2_t vd,
+vbfloat16m2_t test_vzip_vv_bf16m2_tum(vbool8_t vm, vbfloat16m2_t vd,
vbfloat16m1_t vs2, vbfloat16m1_t vs1,
size_t vl) {
return __riscv_vzip_vv_bf16m2_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4_tum(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], <vscale x 8 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], <vscale x 8 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vzip.mask.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x bfloat> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vzip.mask.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x bfloat> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
//
-vbfloat16m4_t test_vzip_vv_bf16m4_tum(vbool8_t vm, vbfloat16m4_t vd,
+vbfloat16m4_t test_vzip_vv_bf16m4_tum(vbool4_t vm, vbfloat16m4_t vd,
vbfloat16m2_t vs2, vbfloat16m2_t vs1,
size_t vl) {
return __riscv_vzip_vv_bf16m4_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vzip_vv_bf16m8_tum(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x bfloat> [[VD:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], <vscale x 16 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x bfloat> [[VD:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], <vscale x 16 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vzip.mask.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> [[VD]], <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x bfloat> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vzip.mask.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> [[VD]], <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x bfloat> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]]
//
-vbfloat16m8_t test_vzip_vv_bf16m8_tum(vbool4_t vm, vbfloat16m8_t vd,
+vbfloat16m8_t test_vzip_vv_bf16m8_tum(vbool2_t vm, vbfloat16m8_t vd,
vbfloat16m4_t vs2, vbfloat16m4_t vs1,
size_t vl) {
return __riscv_vzip_vv_bf16m8_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_tumu(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], <vscale x 1 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], <vscale x 1 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x bfloat> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x bfloat> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
//
-vbfloat16mf2_t test_vzip_vv_bf16mf2_tumu(vbool64_t vm, vbfloat16mf2_t vd,
+vbfloat16mf2_t test_vzip_vv_bf16mf2_tumu(vbool32_t vm, vbfloat16mf2_t vd,
vbfloat16mf4_t vs2, vbfloat16mf4_t vs1,
size_t vl) {
return __riscv_vzip_vv_bf16mf2_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_tumu(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], <vscale x 2 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], <vscale x 2 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x bfloat> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x bfloat> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
//
-vbfloat16m1_t test_vzip_vv_bf16m1_tumu(vbool32_t vm, vbfloat16m1_t vd,
+vbfloat16m1_t test_vzip_vv_bf16m1_tumu(vbool16_t vm, vbfloat16m1_t vd,
vbfloat16mf2_t vs2, vbfloat16mf2_t vs1,
size_t vl) {
return __riscv_vzip_vv_bf16m1_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_tumu(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], <vscale x 4 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], <vscale x 4 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x bfloat> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x bfloat> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
//
-vbfloat16m2_t test_vzip_vv_bf16m2_tumu(vbool16_t vm, vbfloat16m2_t vd,
+vbfloat16m2_t test_vzip_vv_bf16m2_tumu(vbool8_t vm, vbfloat16m2_t vd,
vbfloat16m1_t vs2, vbfloat16m1_t vs1,
size_t vl) {
return __riscv_vzip_vv_bf16m2_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4_tumu(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], <vscale x 8 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], <vscale x 8 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vzip.mask.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x bfloat> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vzip.mask.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x bfloat> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
//
-vbfloat16m4_t test_vzip_vv_bf16m4_tumu(vbool8_t vm, vbfloat16m4_t vd,
+vbfloat16m4_t test_vzip_vv_bf16m4_tumu(vbool4_t vm, vbfloat16m4_t vd,
vbfloat16m2_t vs2, vbfloat16m2_t vs1,
size_t vl) {
return __riscv_vzip_vv_bf16m4_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vzip_vv_bf16m8_tumu(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x bfloat> [[VD:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], <vscale x 16 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x bfloat> [[VD:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], <vscale x 16 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vzip.mask.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> [[VD]], <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x bfloat> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vzip.mask.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> [[VD]], <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x bfloat> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]]
//
-vbfloat16m8_t test_vzip_vv_bf16m8_tumu(vbool4_t vm, vbfloat16m8_t vd,
+vbfloat16m8_t test_vzip_vv_bf16m8_tumu(vbool2_t vm, vbfloat16m8_t vd,
vbfloat16m4_t vs2, vbfloat16m4_t vs1,
size_t vl) {
return __riscv_vzip_vv_bf16m8_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_mu(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], <vscale x 1 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], <vscale x 1 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x bfloat> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x bfloat> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
//
-vbfloat16mf2_t test_vzip_vv_bf16mf2_mu(vbool64_t vm, vbfloat16mf2_t vd,
+vbfloat16mf2_t test_vzip_vv_bf16mf2_mu(vbool32_t vm, vbfloat16mf2_t vd,
vbfloat16mf4_t vs2, vbfloat16mf4_t vs1,
size_t vl) {
return __riscv_vzip_vv_bf16mf2_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_mu(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], <vscale x 2 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], <vscale x 2 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x bfloat> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x bfloat> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
//
-vbfloat16m1_t test_vzip_vv_bf16m1_mu(vbool32_t vm, vbfloat16m1_t vd,
+vbfloat16m1_t test_vzip_vv_bf16m1_mu(vbool16_t vm, vbfloat16m1_t vd,
vbfloat16mf2_t vs2, vbfloat16mf2_t vs1,
size_t vl) {
return __riscv_vzip_vv_bf16m1_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_mu(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], <vscale x 4 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], <vscale x 4 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x bfloat> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x bfloat> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
//
-vbfloat16m2_t test_vzip_vv_bf16m2_mu(vbool16_t vm, vbfloat16m2_t vd,
+vbfloat16m2_t test_vzip_vv_bf16m2_mu(vbool8_t vm, vbfloat16m2_t vd,
vbfloat16m1_t vs2, vbfloat16m1_t vs1,
size_t vl) {
return __riscv_vzip_vv_bf16m2_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4_mu(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], <vscale x 8 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], <vscale x 8 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vzip.mask.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x bfloat> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vzip.mask.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x bfloat> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
//
-vbfloat16m4_t test_vzip_vv_bf16m4_mu(vbool8_t vm, vbfloat16m4_t vd,
+vbfloat16m4_t test_vzip_vv_bf16m4_mu(vbool4_t vm, vbfloat16m4_t vd,
vbfloat16m2_t vs2, vbfloat16m2_t vs1,
size_t vl) {
return __riscv_vzip_vv_bf16m4_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vzip_vv_bf16m8_mu(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x bfloat> [[VD:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], <vscale x 16 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x bfloat> [[VD:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], <vscale x 16 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vzip.mask.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> [[VD]], <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x bfloat> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vzip.mask.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> [[VD]], <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x bfloat> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]]
//
-vbfloat16m8_t test_vzip_vv_bf16m8_mu(vbool4_t vm, vbfloat16m8_t vd,
+vbfloat16m8_t test_vzip_vv_bf16m8_mu(vbool2_t vm, vbfloat16m8_t vd,
vbfloat16m4_t vs2, vbfloat16m4_t vs1,
size_t vl) {
return __riscv_vzip_vv_bf16m8_mu(vm, vd, vs2, vs1, vl);
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c
index bfad6b6093683..345f9bfa76837 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c
@@ -64,167 +64,3 @@ vbfloat16m4_t test_vunzipe_v_bf16m4_tu(vbfloat16m4_t vd, vbfloat16m8_t vs,
return __riscv_vunzipe_tu(vd, vs, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vunzipe_v_bf16mf4_tum(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x bfloat> [[VD:%.*]], <vscale x 2 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vunzipe.mask.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> [[VD]], <vscale x 2 x bfloat> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
-//
-vbfloat16mf4_t test_vunzipe_v_bf16mf4_tum(vbool64_t vm, vbfloat16mf4_t vd,
- vbfloat16mf2_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vunzipe_v_bf16mf2_tum(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], <vscale x 4 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vunzipe.mask.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 4 x bfloat> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
-//
-vbfloat16mf2_t test_vunzipe_v_bf16mf2_tum(vbool32_t vm, vbfloat16mf2_t vd,
- vbfloat16m1_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vunzipe_v_bf16m1_tum(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], <vscale x 8 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vunzipe.mask.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 8 x bfloat> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
-//
-vbfloat16m1_t test_vunzipe_v_bf16m1_tum(vbool16_t vm, vbfloat16m1_t vd,
- vbfloat16m2_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vunzipe_v_bf16m2_tum(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], <vscale x 16 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vunzipe.mask.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 16 x bfloat> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
-//
-vbfloat16m2_t test_vunzipe_v_bf16m2_tum(vbool8_t vm, vbfloat16m2_t vd,
- vbfloat16m4_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vunzipe_v_bf16m4_tum(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], <vscale x 32 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vunzipe.mask.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 32 x bfloat> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
-//
-vbfloat16m4_t test_vunzipe_v_bf16m4_tum(vbool4_t vm, vbfloat16m4_t vd,
- vbfloat16m8_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vunzipe_v_bf16mf4_tumu(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x bfloat> [[VD:%.*]], <vscale x 2 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vunzipe.mask.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> [[VD]], <vscale x 2 x bfloat> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
-//
-vbfloat16mf4_t test_vunzipe_v_bf16mf4_tumu(vbool64_t vm, vbfloat16mf4_t vd,
- vbfloat16mf2_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vunzipe_v_bf16mf2_tumu(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], <vscale x 4 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vunzipe.mask.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 4 x bfloat> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
-//
-vbfloat16mf2_t test_vunzipe_v_bf16mf2_tumu(vbool32_t vm, vbfloat16mf2_t vd,
- vbfloat16m1_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vunzipe_v_bf16m1_tumu(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], <vscale x 8 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vunzipe.mask.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 8 x bfloat> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
-//
-vbfloat16m1_t test_vunzipe_v_bf16m1_tumu(vbool16_t vm, vbfloat16m1_t vd,
- vbfloat16m2_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vunzipe_v_bf16m2_tumu(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], <vscale x 16 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vunzipe.mask.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 16 x bfloat> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
-//
-vbfloat16m2_t test_vunzipe_v_bf16m2_tumu(vbool8_t vm, vbfloat16m2_t vd,
- vbfloat16m4_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vunzipe_v_bf16m4_tumu(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], <vscale x 32 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vunzipe.mask.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 32 x bfloat> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
-//
-vbfloat16m4_t test_vunzipe_v_bf16m4_tumu(vbool4_t vm, vbfloat16m4_t vd,
- vbfloat16m8_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vunzipe_v_bf16mf4_mu(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x bfloat> [[VD:%.*]], <vscale x 2 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vunzipe.mask.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> [[VD]], <vscale x 2 x bfloat> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
-//
-vbfloat16mf4_t test_vunzipe_v_bf16mf4_mu(vbool64_t vm, vbfloat16mf4_t vd,
- vbfloat16mf2_t vs, size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vunzipe_v_bf16mf2_mu(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], <vscale x 4 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vunzipe.mask.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 4 x bfloat> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
-//
-vbfloat16mf2_t test_vunzipe_v_bf16mf2_mu(vbool32_t vm, vbfloat16mf2_t vd,
- vbfloat16m1_t vs, size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vunzipe_v_bf16m1_mu(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], <vscale x 8 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vunzipe.mask.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 8 x bfloat> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
-//
-vbfloat16m1_t test_vunzipe_v_bf16m1_mu(vbool16_t vm, vbfloat16m1_t vd,
- vbfloat16m2_t vs, size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vunzipe_v_bf16m2_mu(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], <vscale x 16 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vunzipe.mask.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 16 x bfloat> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
-//
-vbfloat16m2_t test_vunzipe_v_bf16m2_mu(vbool8_t vm, vbfloat16m2_t vd,
- vbfloat16m4_t vs, size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vunzipe_v_bf16m4_mu(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], <vscale x 32 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vunzipe.mask.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 32 x bfloat> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
-//
-vbfloat16m4_t test_vunzipe_v_bf16m4_mu(vbool4_t vm, vbfloat16m4_t vd,
- vbfloat16m8_t vs, size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c
index d6c67069a3e88..7be11f5e83d65 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c
@@ -64,167 +64,3 @@ vbfloat16m4_t test_vunzipo_v_bf16m4_tu(vbfloat16m4_t vd, vbfloat16m8_t vs,
return __riscv_vunzipo_tu(vd, vs, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vunzipo_v_bf16mf4_tum(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x bfloat> [[VD:%.*]], <vscale x 2 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vunzipo.mask.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> [[VD]], <vscale x 2 x bfloat> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
-//
-vbfloat16mf4_t test_vunzipo_v_bf16mf4_tum(vbool64_t vm, vbfloat16mf4_t vd,
- vbfloat16mf2_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vunzipo_v_bf16mf2_tum(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], <vscale x 4 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vunzipo.mask.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 4 x bfloat> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
-//
-vbfloat16mf2_t test_vunzipo_v_bf16mf2_tum(vbool32_t vm, vbfloat16mf2_t vd,
- vbfloat16m1_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vunzipo_v_bf16m1_tum(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], <vscale x 8 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vunzipo.mask.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 8 x bfloat> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
-//
-vbfloat16m1_t test_vunzipo_v_bf16m1_tum(vbool16_t vm, vbfloat16m1_t vd,
- vbfloat16m2_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vunzipo_v_bf16m2_tum(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], <vscale x 16 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vunzipo.mask.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 16 x bfloat> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
-//
-vbfloat16m2_t test_vunzipo_v_bf16m2_tum(vbool8_t vm, vbfloat16m2_t vd,
- vbfloat16m4_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vunzipo_v_bf16m4_tum(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], <vscale x 32 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vunzipo.mask.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 32 x bfloat> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
-//
-vbfloat16m4_t test_vunzipo_v_bf16m4_tum(vbool4_t vm, vbfloat16m4_t vd,
- vbfloat16m8_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vunzipo_v_bf16mf4_tumu(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x bfloat> [[VD:%.*]], <vscale x 2 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vunzipo.mask.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> [[VD]], <vscale x 2 x bfloat> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
-//
-vbfloat16mf4_t test_vunzipo_v_bf16mf4_tumu(vbool64_t vm, vbfloat16mf4_t vd,
- vbfloat16mf2_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vunzipo_v_bf16mf2_tumu(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], <vscale x 4 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vunzipo.mask.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 4 x bfloat> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
-//
-vbfloat16mf2_t test_vunzipo_v_bf16mf2_tumu(vbool32_t vm, vbfloat16mf2_t vd,
- vbfloat16m1_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vunzipo_v_bf16m1_tumu(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], <vscale x 8 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vunzipo.mask.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 8 x bfloat> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
-//
-vbfloat16m1_t test_vunzipo_v_bf16m1_tumu(vbool16_t vm, vbfloat16m1_t vd,
- vbfloat16m2_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vunzipo_v_bf16m2_tumu(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], <vscale x 16 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vunzipo.mask.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 16 x bfloat> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
-//
-vbfloat16m2_t test_vunzipo_v_bf16m2_tumu(vbool8_t vm, vbfloat16m2_t vd,
- vbfloat16m4_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vunzipo_v_bf16m4_tumu(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], <vscale x 32 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vunzipo.mask.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 32 x bfloat> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
-//
-vbfloat16m4_t test_vunzipo_v_bf16m4_tumu(vbool4_t vm, vbfloat16m4_t vd,
- vbfloat16m8_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vunzipo_v_bf16mf4_mu(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x bfloat> [[VD:%.*]], <vscale x 2 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vunzipo.mask.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> [[VD]], <vscale x 2 x bfloat> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
-//
-vbfloat16mf4_t test_vunzipo_v_bf16mf4_mu(vbool64_t vm, vbfloat16mf4_t vd,
- vbfloat16mf2_t vs, size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vunzipo_v_bf16mf2_mu(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], <vscale x 4 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vunzipo.mask.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 4 x bfloat> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
-//
-vbfloat16mf2_t test_vunzipo_v_bf16mf2_mu(vbool32_t vm, vbfloat16mf2_t vd,
- vbfloat16m1_t vs, size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vunzipo_v_bf16m1_mu(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], <vscale x 8 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vunzipo.mask.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 8 x bfloat> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
-//
-vbfloat16m1_t test_vunzipo_v_bf16m1_mu(vbool16_t vm, vbfloat16m1_t vd,
- vbfloat16m2_t vs, size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vunzipo_v_bf16m2_mu(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], <vscale x 16 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vunzipo.mask.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 16 x bfloat> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
-//
-vbfloat16m2_t test_vunzipo_v_bf16m2_mu(vbool8_t vm, vbfloat16m2_t vd,
- vbfloat16m4_t vs, size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vunzipo_v_bf16m4_mu(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], <vscale x 32 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vunzipo.mask.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 32 x bfloat> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
-//
-vbfloat16m4_t test_vunzipo_v_bf16m4_mu(vbool4_t vm, vbfloat16m4_t vd,
- vbfloat16m8_t vs, size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c
index 1a51ee84cb5ab..31e2f9c913946 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c
@@ -65,180 +65,180 @@ vbfloat16m8_t test_vzip_vv_bf16m8_tu(vbfloat16m8_t vd, vbfloat16m4_t vs2,
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_tum(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], <vscale x 1 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], <vscale x 1 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x bfloat> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x bfloat> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
//
-vbfloat16mf2_t test_vzip_vv_bf16mf2_tum(vbool64_t vm, vbfloat16mf2_t vd,
+vbfloat16mf2_t test_vzip_vv_bf16mf2_tum(vbool32_t vm, vbfloat16mf2_t vd,
vbfloat16mf4_t vs2, vbfloat16mf4_t vs1,
size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_tum(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], <vscale x 2 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], <vscale x 2 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x bfloat> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x bfloat> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
//
-vbfloat16m1_t test_vzip_vv_bf16m1_tum(vbool32_t vm, vbfloat16m1_t vd,
+vbfloat16m1_t test_vzip_vv_bf16m1_tum(vbool16_t vm, vbfloat16m1_t vd,
vbfloat16mf2_t vs2, vbfloat16mf2_t vs1,
size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_tum(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], <vscale x 4 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], <vscale x 4 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x bfloat> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x bfloat> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
//
-vbfloat16m2_t test_vzip_vv_bf16m2_tum(vbool16_t vm, vbfloat16m2_t vd,
+vbfloat16m2_t test_vzip_vv_bf16m2_tum(vbool8_t vm, vbfloat16m2_t vd,
vbfloat16m1_t vs2, vbfloat16m1_t vs1,
size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4_tum(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], <vscale x 8 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], <vscale x 8 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vzip.mask.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x bfloat> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vzip.mask.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x bfloat> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
//
-vbfloat16m4_t test_vzip_vv_bf16m4_tum(vbool8_t vm, vbfloat16m4_t vd,
+vbfloat16m4_t test_vzip_vv_bf16m4_tum(vbool4_t vm, vbfloat16m4_t vd,
vbfloat16m2_t vs2, vbfloat16m2_t vs1,
size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vzip_vv_bf16m8_tum(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x bfloat> [[VD:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], <vscale x 16 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x bfloat> [[VD:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], <vscale x 16 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vzip.mask.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> [[VD]], <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x bfloat> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vzip.mask.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> [[VD]], <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x bfloat> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]]
//
-vbfloat16m8_t test_vzip_vv_bf16m8_tum(vbool4_t vm, vbfloat16m8_t vd,
+vbfloat16m8_t test_vzip_vv_bf16m8_tum(vbool2_t vm, vbfloat16m8_t vd,
vbfloat16m4_t vs2, vbfloat16m4_t vs1,
size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_tumu(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], <vscale x 1 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], <vscale x 1 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x bfloat> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x bfloat> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
//
-vbfloat16mf2_t test_vzip_vv_bf16mf2_tumu(vbool64_t vm, vbfloat16mf2_t vd,
+vbfloat16mf2_t test_vzip_vv_bf16mf2_tumu(vbool32_t vm, vbfloat16mf2_t vd,
vbfloat16mf4_t vs2, vbfloat16mf4_t vs1,
size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_tumu(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], <vscale x 2 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], <vscale x 2 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x bfloat> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x bfloat> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
//
-vbfloat16m1_t test_vzip_vv_bf16m1_tumu(vbool32_t vm, vbfloat16m1_t vd,
+vbfloat16m1_t test_vzip_vv_bf16m1_tumu(vbool16_t vm, vbfloat16m1_t vd,
vbfloat16mf2_t vs2, vbfloat16mf2_t vs1,
size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_tumu(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], <vscale x 4 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], <vscale x 4 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x bfloat> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x bfloat> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
//
-vbfloat16m2_t test_vzip_vv_bf16m2_tumu(vbool16_t vm, vbfloat16m2_t vd,
+vbfloat16m2_t test_vzip_vv_bf16m2_tumu(vbool8_t vm, vbfloat16m2_t vd,
vbfloat16m1_t vs2, vbfloat16m1_t vs1,
size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4_tumu(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], <vscale x 8 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], <vscale x 8 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vzip.mask.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x bfloat> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vzip.mask.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x bfloat> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
//
-vbfloat16m4_t test_vzip_vv_bf16m4_tumu(vbool8_t vm, vbfloat16m4_t vd,
+vbfloat16m4_t test_vzip_vv_bf16m4_tumu(vbool4_t vm, vbfloat16m4_t vd,
vbfloat16m2_t vs2, vbfloat16m2_t vs1,
size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vzip_vv_bf16m8_tumu(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x bfloat> [[VD:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], <vscale x 16 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x bfloat> [[VD:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], <vscale x 16 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vzip.mask.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> [[VD]], <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x bfloat> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vzip.mask.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> [[VD]], <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x bfloat> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]]
//
-vbfloat16m8_t test_vzip_vv_bf16m8_tumu(vbool4_t vm, vbfloat16m8_t vd,
+vbfloat16m8_t test_vzip_vv_bf16m8_tumu(vbool2_t vm, vbfloat16m8_t vd,
vbfloat16m4_t vs2, vbfloat16m4_t vs1,
size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_mu(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], <vscale x 1 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VD:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], <vscale x 1 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x bfloat> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> [[VD]], <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x bfloat> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
//
-vbfloat16mf2_t test_vzip_vv_bf16mf2_mu(vbool64_t vm, vbfloat16mf2_t vd,
+vbfloat16mf2_t test_vzip_vv_bf16mf2_mu(vbool32_t vm, vbfloat16mf2_t vd,
vbfloat16mf4_t vs2, vbfloat16mf4_t vs1,
size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_mu(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], <vscale x 2 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VD:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], <vscale x 2 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x bfloat> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> [[VD]], <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x bfloat> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
//
-vbfloat16m1_t test_vzip_vv_bf16m1_mu(vbool32_t vm, vbfloat16m1_t vd,
+vbfloat16m1_t test_vzip_vv_bf16m1_mu(vbool16_t vm, vbfloat16m1_t vd,
vbfloat16mf2_t vs2, vbfloat16mf2_t vs1,
size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vzip_vv_bf16m2_mu(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], <vscale x 4 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VD:%.*]], <vscale x 4 x bfloat> [[VS2:%.*]], <vscale x 4 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x bfloat> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(<vscale x 8 x bfloat> [[VD]], <vscale x 4 x bfloat> [[VS2]], <vscale x 4 x bfloat> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
//
-vbfloat16m2_t test_vzip_vv_bf16m2_mu(vbool16_t vm, vbfloat16m2_t vd,
+vbfloat16m2_t test_vzip_vv_bf16m2_mu(vbool8_t vm, vbfloat16m2_t vd,
vbfloat16m1_t vs2, vbfloat16m1_t vs1,
size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vzip_vv_bf16m4_mu(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], <vscale x 8 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VD:%.*]], <vscale x 8 x bfloat> [[VS2:%.*]], <vscale x 8 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vzip.mask.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x bfloat> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vzip.mask.nxv16bf16.nxv8bf16.i64(<vscale x 16 x bfloat> [[VD]], <vscale x 8 x bfloat> [[VS2]], <vscale x 8 x bfloat> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
//
-vbfloat16m4_t test_vzip_vv_bf16m4_mu(vbool8_t vm, vbfloat16m4_t vd,
+vbfloat16m4_t test_vzip_vv_bf16m4_mu(vbool4_t vm, vbfloat16m4_t vd,
vbfloat16m2_t vs2, vbfloat16m2_t vs1,
size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vzip_vv_bf16m8_mu(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x bfloat> [[VD:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], <vscale x 16 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x bfloat> [[VD:%.*]], <vscale x 16 x bfloat> [[VS2:%.*]], <vscale x 16 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vzip.mask.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> [[VD]], <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x bfloat> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vzip.mask.nxv32bf16.nxv16bf16.i64(<vscale x 32 x bfloat> [[VD]], <vscale x 16 x bfloat> [[VS2]], <vscale x 16 x bfloat> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]]
//
-vbfloat16m8_t test_vzip_vv_bf16m8_mu(vbool4_t vm, vbfloat16m8_t vd,
+vbfloat16m8_t test_vzip_vv_bf16m8_mu(vbool2_t vm, vbfloat16m8_t vd,
vbfloat16m4_t vs2, vbfloat16m4_t vs1,
size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c
index c80e4e2a8332d..9e4df25777be3 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c
@@ -489,485 +489,3 @@ vuint64m4_t test_vunzipe_v_u64m4(vuint64m8_t vs, size_t vl) {
return __riscv_vunzipe_v_u64m4(vs, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vunzipe_v_f16mf4_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vunzipe.mask.nxv1f16.nxv2f16.i64(<vscale x 1 x half> poison, <vscale x 2 x half> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
-//
-vfloat16mf4_t test_vunzipe_v_f16mf4_m(vbool64_t vm, vfloat16mf2_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_f16mf4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vunzipe_v_f16mf2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vunzipe.mask.nxv2f16.nxv4f16.i64(<vscale x 2 x half> poison, <vscale x 4 x half> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
-//
-vfloat16mf2_t test_vunzipe_v_f16mf2_m(vbool32_t vm, vfloat16m1_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_f16mf2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vunzipe_v_f16m1_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vunzipe.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
-//
-vfloat16m1_t test_vunzipe_v_f16m1_m(vbool16_t vm, vfloat16m2_t vs, size_t vl) {
- return __riscv_vunzipe_v_f16m1_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vunzipe_v_f16m2_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vunzipe.mask.nxv8f16.nxv16f16.i64(<vscale x 8 x half> poison, <vscale x 16 x half> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
-//
-vfloat16m2_t test_vunzipe_v_f16m2_m(vbool8_t vm, vfloat16m4_t vs, size_t vl) {
- return __riscv_vunzipe_v_f16m2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vunzipe_v_f16m4_m
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vunzipe.mask.nxv16f16.nxv32f16.i64(<vscale x 16 x half> poison, <vscale x 32 x half> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
-//
-vfloat16m4_t test_vunzipe_v_f16m4_m(vbool4_t vm, vfloat16m8_t vs, size_t vl) {
- return __riscv_vunzipe_v_f16m4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vunzipe_v_f32mf2_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vunzipe.mask.nxv1f32.nxv2f32.i64(<vscale x 1 x float> poison, <vscale x 2 x float> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
-//
-vfloat32mf2_t test_vunzipe_v_f32mf2_m(vbool64_t vm, vfloat32m1_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_f32mf2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vunzipe_v_f32m1_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vunzipe.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
-//
-vfloat32m1_t test_vunzipe_v_f32m1_m(vbool32_t vm, vfloat32m2_t vs, size_t vl) {
- return __riscv_vunzipe_v_f32m1_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vunzipe_v_f32m2_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vunzipe.mask.nxv4f32.nxv8f32.i64(<vscale x 4 x float> poison, <vscale x 8 x float> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
-//
-vfloat32m2_t test_vunzipe_v_f32m2_m(vbool16_t vm, vfloat32m4_t vs, size_t vl) {
- return __riscv_vunzipe_v_f32m2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vunzipe_v_f32m4_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vunzipe.mask.nxv8f32.nxv16f32.i64(<vscale x 8 x float> poison, <vscale x 16 x float> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
-//
-vfloat32m4_t test_vunzipe_v_f32m4_m(vbool8_t vm, vfloat32m8_t vs, size_t vl) {
- return __riscv_vunzipe_v_f32m4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vunzipe_v_f64m1_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vunzipe.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
-//
-vfloat64m1_t test_vunzipe_v_f64m1_m(vbool64_t vm, vfloat64m2_t vs, size_t vl) {
- return __riscv_vunzipe_v_f64m1_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vunzipe_v_f64m2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vunzipe.mask.nxv2f64.nxv4f64.i64(<vscale x 2 x double> poison, <vscale x 4 x double> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
-//
-vfloat64m2_t test_vunzipe_v_f64m2_m(vbool32_t vm, vfloat64m4_t vs, size_t vl) {
- return __riscv_vunzipe_v_f64m2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vunzipe_v_f64m4_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vunzipe.mask.nxv4f64.nxv8f64.i64(<vscale x 4 x double> poison, <vscale x 8 x double> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
-//
-vfloat64m4_t test_vunzipe_v_f64m4_m(vbool16_t vm, vfloat64m8_t vs, size_t vl) {
- return __riscv_vunzipe_v_f64m4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vunzipe_v_i8mf8_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vunzipe.mask.nxv1i8.nxv2i8.i64(<vscale x 1 x i8> poison, <vscale x 2 x i8> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
-//
-vint8mf8_t test_vunzipe_v_i8mf8_m(vbool64_t vm, vint8mf4_t vs, size_t vl) {
- return __riscv_vunzipe_v_i8mf8_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vunzipe_v_i8mf4_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vunzipe.mask.nxv2i8.nxv4i8.i64(<vscale x 2 x i8> poison, <vscale x 4 x i8> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
-//
-vint8mf4_t test_vunzipe_v_i8mf4_m(vbool32_t vm, vint8mf2_t vs, size_t vl) {
- return __riscv_vunzipe_v_i8mf4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vunzipe_v_i8mf2_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vunzipe.mask.nxv4i8.nxv8i8.i64(<vscale x 4 x i8> poison, <vscale x 8 x i8> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
-//
-vint8mf2_t test_vunzipe_v_i8mf2_m(vbool16_t vm, vint8m1_t vs, size_t vl) {
- return __riscv_vunzipe_v_i8mf2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vunzipe_v_i8m1_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vunzipe.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
-//
-vint8m1_t test_vunzipe_v_i8m1_m(vbool8_t vm, vint8m2_t vs, size_t vl) {
- return __riscv_vunzipe_v_i8m1_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vunzipe_v_i8m2_m
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vunzipe.mask.nxv16i8.nxv32i8.i64(<vscale x 16 x i8> poison, <vscale x 32 x i8> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-vint8m2_t test_vunzipe_v_i8m2_m(vbool4_t vm, vint8m4_t vs, size_t vl) {
- return __riscv_vunzipe_v_i8m2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vunzipe_v_i8m4_m
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vunzipe.mask.nxv32i8.nxv64i8.i64(<vscale x 32 x i8> poison, <vscale x 64 x i8> [[VS]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
-//
-vint8m4_t test_vunzipe_v_i8m4_m(vbool2_t vm, vint8m8_t vs, size_t vl) {
- return __riscv_vunzipe_v_i8m4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vunzipe_v_i16mf4_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vunzipe.mask.nxv1i16.nxv2i16.i64(<vscale x 1 x i16> poison, <vscale x 2 x i16> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
-//
-vint16mf4_t test_vunzipe_v_i16mf4_m(vbool64_t vm, vint16mf2_t vs, size_t vl) {
- return __riscv_vunzipe_v_i16mf4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vunzipe_v_i16mf2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vunzipe.mask.nxv2i16.nxv4i16.i64(<vscale x 2 x i16> poison, <vscale x 4 x i16> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
-//
-vint16mf2_t test_vunzipe_v_i16mf2_m(vbool32_t vm, vint16m1_t vs, size_t vl) {
- return __riscv_vunzipe_v_i16mf2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vunzipe_v_i16m1_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vunzipe.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> poison, <vscale x 8 x i16> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
-//
-vint16m1_t test_vunzipe_v_i16m1_m(vbool16_t vm, vint16m2_t vs, size_t vl) {
- return __riscv_vunzipe_v_i16m1_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vunzipe_v_i16m2_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vunzipe.mask.nxv8i16.nxv16i16.i64(<vscale x 8 x i16> poison, <vscale x 16 x i16> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-vint16m2_t test_vunzipe_v_i16m2_m(vbool8_t vm, vint16m4_t vs, size_t vl) {
- return __riscv_vunzipe_v_i16m2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vunzipe_v_i16m4_m
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vunzipe.mask.nxv16i16.nxv32i16.i64(<vscale x 16 x i16> poison, <vscale x 32 x i16> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
-//
-vint16m4_t test_vunzipe_v_i16m4_m(vbool4_t vm, vint16m8_t vs, size_t vl) {
- return __riscv_vunzipe_v_i16m4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vunzipe_v_i32mf2_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vunzipe.mask.nxv1i32.nxv2i32.i64(<vscale x 1 x i32> poison, <vscale x 2 x i32> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vunzipe_v_i32mf2_m(vbool64_t vm, vint32m1_t vs, size_t vl) {
- return __riscv_vunzipe_v_i32mf2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vunzipe_v_i32m1_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vunzipe.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> poison, <vscale x 4 x i32> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vunzipe_v_i32m1_m(vbool32_t vm, vint32m2_t vs, size_t vl) {
- return __riscv_vunzipe_v_i32m1_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vunzipe_v_i32m2_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vunzipe.mask.nxv4i32.nxv8i32.i64(<vscale x 4 x i32> poison, <vscale x 8 x i32> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vunzipe_v_i32m2_m(vbool16_t vm, vint32m4_t vs, size_t vl) {
- return __riscv_vunzipe_v_i32m2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vunzipe_v_i32m4_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vunzipe.mask.nxv8i32.nxv16i32.i64(<vscale x 8 x i32> poison, <vscale x 16 x i32> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vunzipe_v_i32m4_m(vbool8_t vm, vint32m8_t vs, size_t vl) {
- return __riscv_vunzipe_v_i32m4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vunzipe_v_i64m1_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vunzipe.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> poison, <vscale x 2 x i64> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
-//
-vint64m1_t test_vunzipe_v_i64m1_m(vbool64_t vm, vint64m2_t vs, size_t vl) {
- return __riscv_vunzipe_v_i64m1_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vunzipe_v_i64m2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vunzipe.mask.nxv2i64.nxv4i64.i64(<vscale x 2 x i64> poison, <vscale x 4 x i64> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-vint64m2_t test_vunzipe_v_i64m2_m(vbool32_t vm, vint64m4_t vs, size_t vl) {
- return __riscv_vunzipe_v_i64m2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vunzipe_v_i64m4_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vunzipe.mask.nxv4i64.nxv8i64.i64(<vscale x 4 x i64> poison, <vscale x 8 x i64> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
-//
-vint64m4_t test_vunzipe_v_i64m4_m(vbool16_t vm, vint64m8_t vs, size_t vl) {
- return __riscv_vunzipe_v_i64m4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vunzipe_v_u8mf8_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vunzipe.mask.nxv1i8.nxv2i8.i64(<vscale x 1 x i8> poison, <vscale x 2 x i8> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
-//
-vuint8mf8_t test_vunzipe_v_u8mf8_m(vbool64_t vm, vuint8mf4_t vs, size_t vl) {
- return __riscv_vunzipe_v_u8mf8_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vunzipe_v_u8mf4_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vunzipe.mask.nxv2i8.nxv4i8.i64(<vscale x 2 x i8> poison, <vscale x 4 x i8> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
-//
-vuint8mf4_t test_vunzipe_v_u8mf4_m(vbool32_t vm, vuint8mf2_t vs, size_t vl) {
- return __riscv_vunzipe_v_u8mf4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vunzipe_v_u8mf2_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vunzipe.mask.nxv4i8.nxv8i8.i64(<vscale x 4 x i8> poison, <vscale x 8 x i8> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
-//
-vuint8mf2_t test_vunzipe_v_u8mf2_m(vbool16_t vm, vuint8m1_t vs, size_t vl) {
- return __riscv_vunzipe_v_u8mf2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vunzipe_v_u8m1_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vunzipe.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
-//
-vuint8m1_t test_vunzipe_v_u8m1_m(vbool8_t vm, vuint8m2_t vs, size_t vl) {
- return __riscv_vunzipe_v_u8m1_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vunzipe_v_u8m2_m
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vunzipe.mask.nxv16i8.nxv32i8.i64(<vscale x 16 x i8> poison, <vscale x 32 x i8> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-vuint8m2_t test_vunzipe_v_u8m2_m(vbool4_t vm, vuint8m4_t vs, size_t vl) {
- return __riscv_vunzipe_v_u8m2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vunzipe_v_u8m4_m
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vunzipe.mask.nxv32i8.nxv64i8.i64(<vscale x 32 x i8> poison, <vscale x 64 x i8> [[VS]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
-//
-vuint8m4_t test_vunzipe_v_u8m4_m(vbool2_t vm, vuint8m8_t vs, size_t vl) {
- return __riscv_vunzipe_v_u8m4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vunzipe_v_u16mf4_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vunzipe.mask.nxv1i16.nxv2i16.i64(<vscale x 1 x i16> poison, <vscale x 2 x i16> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
-//
-vuint16mf4_t test_vunzipe_v_u16mf4_m(vbool64_t vm, vuint16mf2_t vs, size_t vl) {
- return __riscv_vunzipe_v_u16mf4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vunzipe_v_u16mf2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vunzipe.mask.nxv2i16.nxv4i16.i64(<vscale x 2 x i16> poison, <vscale x 4 x i16> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
-//
-vuint16mf2_t test_vunzipe_v_u16mf2_m(vbool32_t vm, vuint16m1_t vs, size_t vl) {
- return __riscv_vunzipe_v_u16mf2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vunzipe_v_u16m1_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vunzipe.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> poison, <vscale x 8 x i16> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
-//
-vuint16m1_t test_vunzipe_v_u16m1_m(vbool16_t vm, vuint16m2_t vs, size_t vl) {
- return __riscv_vunzipe_v_u16m1_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vunzipe_v_u16m2_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vunzipe.mask.nxv8i16.nxv16i16.i64(<vscale x 8 x i16> poison, <vscale x 16 x i16> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-vuint16m2_t test_vunzipe_v_u16m2_m(vbool8_t vm, vuint16m4_t vs, size_t vl) {
- return __riscv_vunzipe_v_u16m2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vunzipe_v_u16m4_m
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vunzipe.mask.nxv16i16.nxv32i16.i64(<vscale x 16 x i16> poison, <vscale x 32 x i16> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
-//
-vuint16m4_t test_vunzipe_v_u16m4_m(vbool4_t vm, vuint16m8_t vs, size_t vl) {
- return __riscv_vunzipe_v_u16m4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vunzipe_v_u32mf2_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vunzipe.mask.nxv1i32.nxv2i32.i64(<vscale x 1 x i32> poison, <vscale x 2 x i32> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vuint32mf2_t test_vunzipe_v_u32mf2_m(vbool64_t vm, vuint32m1_t vs, size_t vl) {
- return __riscv_vunzipe_v_u32mf2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vunzipe_v_u32m1_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vunzipe.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> poison, <vscale x 4 x i32> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vuint32m1_t test_vunzipe_v_u32m1_m(vbool32_t vm, vuint32m2_t vs, size_t vl) {
- return __riscv_vunzipe_v_u32m1_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vunzipe_v_u32m2_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vunzipe.mask.nxv4i32.nxv8i32.i64(<vscale x 4 x i32> poison, <vscale x 8 x i32> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vuint32m2_t test_vunzipe_v_u32m2_m(vbool16_t vm, vuint32m4_t vs, size_t vl) {
- return __riscv_vunzipe_v_u32m2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vunzipe_v_u32m4_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vunzipe.mask.nxv8i32.nxv16i32.i64(<vscale x 8 x i32> poison, <vscale x 16 x i32> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vuint32m4_t test_vunzipe_v_u32m4_m(vbool8_t vm, vuint32m8_t vs, size_t vl) {
- return __riscv_vunzipe_v_u32m4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vunzipe_v_u64m1_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vunzipe.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> poison, <vscale x 2 x i64> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
-//
-vuint64m1_t test_vunzipe_v_u64m1_m(vbool64_t vm, vuint64m2_t vs, size_t vl) {
- return __riscv_vunzipe_v_u64m1_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vunzipe_v_u64m2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vunzipe.mask.nxv2i64.nxv4i64.i64(<vscale x 2 x i64> poison, <vscale x 4 x i64> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-vuint64m2_t test_vunzipe_v_u64m2_m(vbool32_t vm, vuint64m4_t vs, size_t vl) {
- return __riscv_vunzipe_v_u64m2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vunzipe_v_u64m4_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vunzipe.mask.nxv4i64.nxv8i64.i64(<vscale x 4 x i64> poison, <vscale x 8 x i64> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
-//
-vuint64m4_t test_vunzipe_v_u64m4_m(vbool16_t vm, vuint64m8_t vs, size_t vl) {
- return __riscv_vunzipe_v_u64m4_m(vm, vs, vl);
-}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c
index d1235cd1700c0..a608961aee981 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c
@@ -489,485 +489,3 @@ vuint64m4_t test_vunzipo_v_u64m4(vuint64m8_t vs, size_t vl) {
return __riscv_vunzipo_v_u64m4(vs, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vunzipo_v_f16mf4_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vunzipo.mask.nxv1f16.nxv2f16.i64(<vscale x 1 x half> poison, <vscale x 2 x half> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
-//
-vfloat16mf4_t test_vunzipo_v_f16mf4_m(vbool64_t vm, vfloat16mf2_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_f16mf4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vunzipo_v_f16mf2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vunzipo.mask.nxv2f16.nxv4f16.i64(<vscale x 2 x half> poison, <vscale x 4 x half> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
-//
-vfloat16mf2_t test_vunzipo_v_f16mf2_m(vbool32_t vm, vfloat16m1_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_f16mf2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vunzipo_v_f16m1_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vunzipo.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
-//
-vfloat16m1_t test_vunzipo_v_f16m1_m(vbool16_t vm, vfloat16m2_t vs, size_t vl) {
- return __riscv_vunzipo_v_f16m1_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vunzipo_v_f16m2_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vunzipo.mask.nxv8f16.nxv16f16.i64(<vscale x 8 x half> poison, <vscale x 16 x half> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
-//
-vfloat16m2_t test_vunzipo_v_f16m2_m(vbool8_t vm, vfloat16m4_t vs, size_t vl) {
- return __riscv_vunzipo_v_f16m2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vunzipo_v_f16m4_m
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vunzipo.mask.nxv16f16.nxv32f16.i64(<vscale x 16 x half> poison, <vscale x 32 x half> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
-//
-vfloat16m4_t test_vunzipo_v_f16m4_m(vbool4_t vm, vfloat16m8_t vs, size_t vl) {
- return __riscv_vunzipo_v_f16m4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vunzipo_v_f32mf2_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vunzipo.mask.nxv1f32.nxv2f32.i64(<vscale x 1 x float> poison, <vscale x 2 x float> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
-//
-vfloat32mf2_t test_vunzipo_v_f32mf2_m(vbool64_t vm, vfloat32m1_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_f32mf2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vunzipo_v_f32m1_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vunzipo.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
-//
-vfloat32m1_t test_vunzipo_v_f32m1_m(vbool32_t vm, vfloat32m2_t vs, size_t vl) {
- return __riscv_vunzipo_v_f32m1_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vunzipo_v_f32m2_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vunzipo.mask.nxv4f32.nxv8f32.i64(<vscale x 4 x float> poison, <vscale x 8 x float> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
-//
-vfloat32m2_t test_vunzipo_v_f32m2_m(vbool16_t vm, vfloat32m4_t vs, size_t vl) {
- return __riscv_vunzipo_v_f32m2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vunzipo_v_f32m4_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vunzipo.mask.nxv8f32.nxv16f32.i64(<vscale x 8 x float> poison, <vscale x 16 x float> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
-//
-vfloat32m4_t test_vunzipo_v_f32m4_m(vbool8_t vm, vfloat32m8_t vs, size_t vl) {
- return __riscv_vunzipo_v_f32m4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vunzipo_v_f64m1_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vunzipo.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
-//
-vfloat64m1_t test_vunzipo_v_f64m1_m(vbool64_t vm, vfloat64m2_t vs, size_t vl) {
- return __riscv_vunzipo_v_f64m1_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vunzipo_v_f64m2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vunzipo.mask.nxv2f64.nxv4f64.i64(<vscale x 2 x double> poison, <vscale x 4 x double> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
-//
-vfloat64m2_t test_vunzipo_v_f64m2_m(vbool32_t vm, vfloat64m4_t vs, size_t vl) {
- return __riscv_vunzipo_v_f64m2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vunzipo_v_f64m4_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vunzipo.mask.nxv4f64.nxv8f64.i64(<vscale x 4 x double> poison, <vscale x 8 x double> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
-//
-vfloat64m4_t test_vunzipo_v_f64m4_m(vbool16_t vm, vfloat64m8_t vs, size_t vl) {
- return __riscv_vunzipo_v_f64m4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vunzipo_v_i8mf8_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vunzipo.mask.nxv1i8.nxv2i8.i64(<vscale x 1 x i8> poison, <vscale x 2 x i8> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
-//
-vint8mf8_t test_vunzipo_v_i8mf8_m(vbool64_t vm, vint8mf4_t vs, size_t vl) {
- return __riscv_vunzipo_v_i8mf8_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vunzipo_v_i8mf4_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vunzipo.mask.nxv2i8.nxv4i8.i64(<vscale x 2 x i8> poison, <vscale x 4 x i8> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
-//
-vint8mf4_t test_vunzipo_v_i8mf4_m(vbool32_t vm, vint8mf2_t vs, size_t vl) {
- return __riscv_vunzipo_v_i8mf4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vunzipo_v_i8mf2_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vunzipo.mask.nxv4i8.nxv8i8.i64(<vscale x 4 x i8> poison, <vscale x 8 x i8> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
-//
-vint8mf2_t test_vunzipo_v_i8mf2_m(vbool16_t vm, vint8m1_t vs, size_t vl) {
- return __riscv_vunzipo_v_i8mf2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vunzipo_v_i8m1_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vunzipo.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
-//
-vint8m1_t test_vunzipo_v_i8m1_m(vbool8_t vm, vint8m2_t vs, size_t vl) {
- return __riscv_vunzipo_v_i8m1_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vunzipo_v_i8m2_m
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vunzipo.mask.nxv16i8.nxv32i8.i64(<vscale x 16 x i8> poison, <vscale x 32 x i8> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-vint8m2_t test_vunzipo_v_i8m2_m(vbool4_t vm, vint8m4_t vs, size_t vl) {
- return __riscv_vunzipo_v_i8m2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vunzipo_v_i8m4_m
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vunzipo.mask.nxv32i8.nxv64i8.i64(<vscale x 32 x i8> poison, <vscale x 64 x i8> [[VS]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
-//
-vint8m4_t test_vunzipo_v_i8m4_m(vbool2_t vm, vint8m8_t vs, size_t vl) {
- return __riscv_vunzipo_v_i8m4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vunzipo_v_i16mf4_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vunzipo.mask.nxv1i16.nxv2i16.i64(<vscale x 1 x i16> poison, <vscale x 2 x i16> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
-//
-vint16mf4_t test_vunzipo_v_i16mf4_m(vbool64_t vm, vint16mf2_t vs, size_t vl) {
- return __riscv_vunzipo_v_i16mf4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vunzipo_v_i16mf2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vunzipo.mask.nxv2i16.nxv4i16.i64(<vscale x 2 x i16> poison, <vscale x 4 x i16> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
-//
-vint16mf2_t test_vunzipo_v_i16mf2_m(vbool32_t vm, vint16m1_t vs, size_t vl) {
- return __riscv_vunzipo_v_i16mf2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vunzipo_v_i16m1_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vunzipo.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> poison, <vscale x 8 x i16> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
-//
-vint16m1_t test_vunzipo_v_i16m1_m(vbool16_t vm, vint16m2_t vs, size_t vl) {
- return __riscv_vunzipo_v_i16m1_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vunzipo_v_i16m2_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vunzipo.mask.nxv8i16.nxv16i16.i64(<vscale x 8 x i16> poison, <vscale x 16 x i16> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-vint16m2_t test_vunzipo_v_i16m2_m(vbool8_t vm, vint16m4_t vs, size_t vl) {
- return __riscv_vunzipo_v_i16m2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vunzipo_v_i16m4_m
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vunzipo.mask.nxv16i16.nxv32i16.i64(<vscale x 16 x i16> poison, <vscale x 32 x i16> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
-//
-vint16m4_t test_vunzipo_v_i16m4_m(vbool4_t vm, vint16m8_t vs, size_t vl) {
- return __riscv_vunzipo_v_i16m4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vunzipo_v_i32mf2_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vunzipo.mask.nxv1i32.nxv2i32.i64(<vscale x 1 x i32> poison, <vscale x 2 x i32> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vunzipo_v_i32mf2_m(vbool64_t vm, vint32m1_t vs, size_t vl) {
- return __riscv_vunzipo_v_i32mf2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vunzipo_v_i32m1_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vunzipo.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> poison, <vscale x 4 x i32> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vunzipo_v_i32m1_m(vbool32_t vm, vint32m2_t vs, size_t vl) {
- return __riscv_vunzipo_v_i32m1_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vunzipo_v_i32m2_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vunzipo.mask.nxv4i32.nxv8i32.i64(<vscale x 4 x i32> poison, <vscale x 8 x i32> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vunzipo_v_i32m2_m(vbool16_t vm, vint32m4_t vs, size_t vl) {
- return __riscv_vunzipo_v_i32m2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vunzipo_v_i32m4_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vunzipo.mask.nxv8i32.nxv16i32.i64(<vscale x 8 x i32> poison, <vscale x 16 x i32> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vunzipo_v_i32m4_m(vbool8_t vm, vint32m8_t vs, size_t vl) {
- return __riscv_vunzipo_v_i32m4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vunzipo_v_i64m1_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vunzipo.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> poison, <vscale x 2 x i64> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
-//
-vint64m1_t test_vunzipo_v_i64m1_m(vbool64_t vm, vint64m2_t vs, size_t vl) {
- return __riscv_vunzipo_v_i64m1_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vunzipo_v_i64m2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vunzipo.mask.nxv2i64.nxv4i64.i64(<vscale x 2 x i64> poison, <vscale x 4 x i64> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-vint64m2_t test_vunzipo_v_i64m2_m(vbool32_t vm, vint64m4_t vs, size_t vl) {
- return __riscv_vunzipo_v_i64m2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vunzipo_v_i64m4_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vunzipo.mask.nxv4i64.nxv8i64.i64(<vscale x 4 x i64> poison, <vscale x 8 x i64> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
-//
-vint64m4_t test_vunzipo_v_i64m4_m(vbool16_t vm, vint64m8_t vs, size_t vl) {
- return __riscv_vunzipo_v_i64m4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vunzipo_v_u8mf8_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vunzipo.mask.nxv1i8.nxv2i8.i64(<vscale x 1 x i8> poison, <vscale x 2 x i8> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
-//
-vuint8mf8_t test_vunzipo_v_u8mf8_m(vbool64_t vm, vuint8mf4_t vs, size_t vl) {
- return __riscv_vunzipo_v_u8mf8_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vunzipo_v_u8mf4_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vunzipo.mask.nxv2i8.nxv4i8.i64(<vscale x 2 x i8> poison, <vscale x 4 x i8> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
-//
-vuint8mf4_t test_vunzipo_v_u8mf4_m(vbool32_t vm, vuint8mf2_t vs, size_t vl) {
- return __riscv_vunzipo_v_u8mf4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vunzipo_v_u8mf2_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vunzipo.mask.nxv4i8.nxv8i8.i64(<vscale x 4 x i8> poison, <vscale x 8 x i8> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
-//
-vuint8mf2_t test_vunzipo_v_u8mf2_m(vbool16_t vm, vuint8m1_t vs, size_t vl) {
- return __riscv_vunzipo_v_u8mf2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vunzipo_v_u8m1_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vunzipo.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
-//
-vuint8m1_t test_vunzipo_v_u8m1_m(vbool8_t vm, vuint8m2_t vs, size_t vl) {
- return __riscv_vunzipo_v_u8m1_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vunzipo_v_u8m2_m
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vunzipo.mask.nxv16i8.nxv32i8.i64(<vscale x 16 x i8> poison, <vscale x 32 x i8> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-vuint8m2_t test_vunzipo_v_u8m2_m(vbool4_t vm, vuint8m4_t vs, size_t vl) {
- return __riscv_vunzipo_v_u8m2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vunzipo_v_u8m4_m
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vunzipo.mask.nxv32i8.nxv64i8.i64(<vscale x 32 x i8> poison, <vscale x 64 x i8> [[VS]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
-//
-vuint8m4_t test_vunzipo_v_u8m4_m(vbool2_t vm, vuint8m8_t vs, size_t vl) {
- return __riscv_vunzipo_v_u8m4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vunzipo_v_u16mf4_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vunzipo.mask.nxv1i16.nxv2i16.i64(<vscale x 1 x i16> poison, <vscale x 2 x i16> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
-//
-vuint16mf4_t test_vunzipo_v_u16mf4_m(vbool64_t vm, vuint16mf2_t vs, size_t vl) {
- return __riscv_vunzipo_v_u16mf4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vunzipo_v_u16mf2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vunzipo.mask.nxv2i16.nxv4i16.i64(<vscale x 2 x i16> poison, <vscale x 4 x i16> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
-//
-vuint16mf2_t test_vunzipo_v_u16mf2_m(vbool32_t vm, vuint16m1_t vs, size_t vl) {
- return __riscv_vunzipo_v_u16mf2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vunzipo_v_u16m1_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vunzipo.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> poison, <vscale x 8 x i16> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
-//
-vuint16m1_t test_vunzipo_v_u16m1_m(vbool16_t vm, vuint16m2_t vs, size_t vl) {
- return __riscv_vunzipo_v_u16m1_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vunzipo_v_u16m2_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vunzipo.mask.nxv8i16.nxv16i16.i64(<vscale x 8 x i16> poison, <vscale x 16 x i16> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-vuint16m2_t test_vunzipo_v_u16m2_m(vbool8_t vm, vuint16m4_t vs, size_t vl) {
- return __riscv_vunzipo_v_u16m2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vunzipo_v_u16m4_m
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vunzipo.mask.nxv16i16.nxv32i16.i64(<vscale x 16 x i16> poison, <vscale x 32 x i16> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
-//
-vuint16m4_t test_vunzipo_v_u16m4_m(vbool4_t vm, vuint16m8_t vs, size_t vl) {
- return __riscv_vunzipo_v_u16m4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vunzipo_v_u32mf2_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vunzipo.mask.nxv1i32.nxv2i32.i64(<vscale x 1 x i32> poison, <vscale x 2 x i32> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vuint32mf2_t test_vunzipo_v_u32mf2_m(vbool64_t vm, vuint32m1_t vs, size_t vl) {
- return __riscv_vunzipo_v_u32mf2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vunzipo_v_u32m1_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vunzipo.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> poison, <vscale x 4 x i32> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vuint32m1_t test_vunzipo_v_u32m1_m(vbool32_t vm, vuint32m2_t vs, size_t vl) {
- return __riscv_vunzipo_v_u32m1_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vunzipo_v_u32m2_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vunzipo.mask.nxv4i32.nxv8i32.i64(<vscale x 4 x i32> poison, <vscale x 8 x i32> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vuint32m2_t test_vunzipo_v_u32m2_m(vbool16_t vm, vuint32m4_t vs, size_t vl) {
- return __riscv_vunzipo_v_u32m2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vunzipo_v_u32m4_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vunzipo.mask.nxv8i32.nxv16i32.i64(<vscale x 8 x i32> poison, <vscale x 16 x i32> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vuint32m4_t test_vunzipo_v_u32m4_m(vbool8_t vm, vuint32m8_t vs, size_t vl) {
- return __riscv_vunzipo_v_u32m4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vunzipo_v_u64m1_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vunzipo.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> poison, <vscale x 2 x i64> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
-//
-vuint64m1_t test_vunzipo_v_u64m1_m(vbool64_t vm, vuint64m2_t vs, size_t vl) {
- return __riscv_vunzipo_v_u64m1_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vunzipo_v_u64m2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vunzipo.mask.nxv2i64.nxv4i64.i64(<vscale x 2 x i64> poison, <vscale x 4 x i64> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-vuint64m2_t test_vunzipo_v_u64m2_m(vbool32_t vm, vuint64m4_t vs, size_t vl) {
- return __riscv_vunzipo_v_u64m2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vunzipo_v_u64m4_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vunzipo.mask.nxv4i64.nxv8i64.i64(<vscale x 4 x i64> poison, <vscale x 8 x i64> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
-//
-vuint64m4_t test_vunzipo_v_u64m4_m(vbool16_t vm, vuint64m8_t vs, size_t vl) {
- return __riscv_vunzipo_v_u64m4_m(vm, vs, vl);
-}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c
index 895d47666ff64..1f7905d9e1bc1 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c
@@ -494,529 +494,529 @@ vuint64m8_t test_vzip_vv_u64m8(vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) {
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vzip_vv_f16mf2_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vzip.mask.nxv2f16.nxv1f16.i64(<vscale x 2 x half> poison, <vscale x 1 x half> [[VS2]], <vscale x 1 x half> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vzip.mask.nxv2f16.nxv1f16.i64(<vscale x 2 x half> poison, <vscale x 1 x half> [[VS2]], <vscale x 1 x half> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
-vfloat16mf2_t test_vzip_vv_f16mf2_m(vbool64_t vm, vfloat16mf4_t vs2,
+vfloat16mf2_t test_vzip_vv_f16mf2_m(vbool32_t vm, vfloat16mf4_t vs2,
vfloat16mf4_t vs1, size_t vl) {
return __riscv_vzip_vv_f16mf2_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vzip_vv_f16m1_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vzip.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> [[VS2]], <vscale x 2 x half> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vzip.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> [[VS2]], <vscale x 2 x half> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
-vfloat16m1_t test_vzip_vv_f16m1_m(vbool32_t vm, vfloat16mf2_t vs2,
+vfloat16m1_t test_vzip_vv_f16m1_m(vbool16_t vm, vfloat16mf2_t vs2,
vfloat16mf2_t vs1, size_t vl) {
return __riscv_vzip_vv_f16m1_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vzip_vv_f16m2_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vzip.mask.nxv8f16.nxv4f16.i64(<vscale x 8 x half> poison, <vscale x 4 x half> [[VS2]], <vscale x 4 x half> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vzip.mask.nxv8f16.nxv4f16.i64(<vscale x 8 x half> poison, <vscale x 4 x half> [[VS2]], <vscale x 4 x half> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
-vfloat16m2_t test_vzip_vv_f16m2_m(vbool16_t vm, vfloat16m1_t vs2,
+vfloat16m2_t test_vzip_vv_f16m2_m(vbool8_t vm, vfloat16m1_t vs2,
vfloat16m1_t vs1, size_t vl) {
return __riscv_vzip_vv_f16m2_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vzip_vv_f16m4_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vzip.mask.nxv16f16.nxv8f16.i64(<vscale x 16 x half> poison, <vscale x 8 x half> [[VS2]], <vscale x 8 x half> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vzip.mask.nxv16f16.nxv8f16.i64(<vscale x 16 x half> poison, <vscale x 8 x half> [[VS2]], <vscale x 8 x half> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
-vfloat16m4_t test_vzip_vv_f16m4_m(vbool8_t vm, vfloat16m2_t vs2,
+vfloat16m4_t test_vzip_vv_f16m4_m(vbool4_t vm, vfloat16m2_t vs2,
vfloat16m2_t vs1, size_t vl) {
return __riscv_vzip_vv_f16m4_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vzip_vv_f16m8_m
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vzip.mask.nxv32f16.nxv16f16.i64(<vscale x 32 x half> poison, <vscale x 16 x half> [[VS2]], <vscale x 16 x half> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vzip.mask.nxv32f16.nxv16f16.i64(<vscale x 32 x half> poison, <vscale x 16 x half> [[VS2]], <vscale x 16 x half> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
-vfloat16m8_t test_vzip_vv_f16m8_m(vbool4_t vm, vfloat16m4_t vs2,
+vfloat16m8_t test_vzip_vv_f16m8_m(vbool2_t vm, vfloat16m4_t vs2,
vfloat16m4_t vs1, size_t vl) {
return __riscv_vzip_vv_f16m8_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vzip_vv_f32m1_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x float> [[VS2:%.*]], <vscale x 1 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 1 x float> [[VS2:%.*]], <vscale x 1 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vzip.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> [[VS2]], <vscale x 1 x float> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vzip.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> [[VS2]], <vscale x 1 x float> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
-vfloat32m1_t test_vzip_vv_f32m1_m(vbool64_t vm, vfloat32mf2_t vs2,
+vfloat32m1_t test_vzip_vv_f32m1_m(vbool32_t vm, vfloat32mf2_t vs2,
vfloat32mf2_t vs1, size_t vl) {
return __riscv_vzip_vv_f32m1_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vzip_vv_f32m2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VS2:%.*]], <vscale x 2 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 2 x float> [[VS2:%.*]], <vscale x 2 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vzip.mask.nxv4f32.nxv2f32.i64(<vscale x 4 x float> poison, <vscale x 2 x float> [[VS2]], <vscale x 2 x float> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vzip.mask.nxv4f32.nxv2f32.i64(<vscale x 4 x float> poison, <vscale x 2 x float> [[VS2]], <vscale x 2 x float> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
-vfloat32m2_t test_vzip_vv_f32m2_m(vbool32_t vm, vfloat32m1_t vs2,
+vfloat32m2_t test_vzip_vv_f32m2_m(vbool16_t vm, vfloat32m1_t vs2,
vfloat32m1_t vs1, size_t vl) {
return __riscv_vzip_vv_f32m2_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vzip_vv_f32m4_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VS2:%.*]], <vscale x 4 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 4 x float> [[VS2:%.*]], <vscale x 4 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vzip.mask.nxv8f32.nxv4f32.i64(<vscale x 8 x float> poison, <vscale x 4 x float> [[VS2]], <vscale x 4 x float> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vzip.mask.nxv8f32.nxv4f32.i64(<vscale x 8 x float> poison, <vscale x 4 x float> [[VS2]], <vscale x 4 x float> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
-vfloat32m4_t test_vzip_vv_f32m4_m(vbool16_t vm, vfloat32m2_t vs2,
+vfloat32m4_t test_vzip_vv_f32m4_m(vbool8_t vm, vfloat32m2_t vs2,
vfloat32m2_t vs1, size_t vl) {
return __riscv_vzip_vv_f32m4_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vzip_vv_f32m8_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VS2:%.*]], <vscale x 8 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 8 x float> [[VS2:%.*]], <vscale x 8 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vzip.mask.nxv16f32.nxv8f32.i64(<vscale x 16 x float> poison, <vscale x 8 x float> [[VS2]], <vscale x 8 x float> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vzip.mask.nxv16f32.nxv8f32.i64(<vscale x 16 x float> poison, <vscale x 8 x float> [[VS2]], <vscale x 8 x float> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
-vfloat32m8_t test_vzip_vv_f32m8_m(vbool8_t vm, vfloat32m4_t vs2,
+vfloat32m8_t test_vzip_vv_f32m8_m(vbool4_t vm, vfloat32m4_t vs2,
vfloat32m4_t vs1, size_t vl) {
return __riscv_vzip_vv_f32m8_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vzip_vv_f64m2_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x double> [[VS2:%.*]], <vscale x 1 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 1 x double> [[VS2:%.*]], <vscale x 1 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vzip.mask.nxv2f64.nxv1f64.i64(<vscale x 2 x double> poison, <vscale x 1 x double> [[VS2]], <vscale x 1 x double> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vzip.mask.nxv2f64.nxv1f64.i64(<vscale x 2 x double> poison, <vscale x 1 x double> [[VS2]], <vscale x 1 x double> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
-vfloat64m2_t test_vzip_vv_f64m2_m(vbool64_t vm, vfloat64m1_t vs2,
+vfloat64m2_t test_vzip_vv_f64m2_m(vbool32_t vm, vfloat64m1_t vs2,
vfloat64m1_t vs1, size_t vl) {
return __riscv_vzip_vv_f64m2_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vzip_vv_f64m4_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x double> [[VS2:%.*]], <vscale x 2 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 2 x double> [[VS2:%.*]], <vscale x 2 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vzip.mask.nxv4f64.nxv2f64.i64(<vscale x 4 x double> poison, <vscale x 2 x double> [[VS2]], <vscale x 2 x double> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vzip.mask.nxv4f64.nxv2f64.i64(<vscale x 4 x double> poison, <vscale x 2 x double> [[VS2]], <vscale x 2 x double> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
-vfloat64m4_t test_vzip_vv_f64m4_m(vbool32_t vm, vfloat64m2_t vs2,
+vfloat64m4_t test_vzip_vv_f64m4_m(vbool16_t vm, vfloat64m2_t vs2,
vfloat64m2_t vs1, size_t vl) {
return __riscv_vzip_vv_f64m4_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vzip_vv_f64m8_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x double> [[VS2:%.*]], <vscale x 4 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 4 x double> [[VS2:%.*]], <vscale x 4 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vzip.mask.nxv8f64.nxv4f64.i64(<vscale x 8 x double> poison, <vscale x 4 x double> [[VS2]], <vscale x 4 x double> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vzip.mask.nxv8f64.nxv4f64.i64(<vscale x 8 x double> poison, <vscale x 4 x double> [[VS2]], <vscale x 4 x double> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
-vfloat64m8_t test_vzip_vv_f64m8_m(vbool16_t vm, vfloat64m4_t vs2,
+vfloat64m8_t test_vzip_vv_f64m8_m(vbool8_t vm, vfloat64m4_t vs2,
vfloat64m4_t vs1, size_t vl) {
return __riscv_vzip_vv_f64m8_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vzip_vv_i8mf4_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> poison, <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> poison, <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
-vint8mf4_t test_vzip_vv_i8mf4_m(vbool64_t vm, vint8mf8_t vs2, vint8mf8_t vs1,
+vint8mf4_t test_vzip_vv_i8mf4_m(vbool32_t vm, vint8mf8_t vs2, vint8mf8_t vs1,
size_t vl) {
return __riscv_vzip_vv_i8mf4_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vzip_vv_i8mf2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> poison, <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> poison, <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
-vint8mf2_t test_vzip_vv_i8mf2_m(vbool32_t vm, vint8mf4_t vs2, vint8mf4_t vs1,
+vint8mf2_t test_vzip_vv_i8mf2_m(vbool16_t vm, vint8mf4_t vs2, vint8mf4_t vs1,
size_t vl) {
return __riscv_vzip_vv_i8mf2_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vzip_vv_i8m1_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
-vint8m1_t test_vzip_vv_i8m1_m(vbool16_t vm, vint8mf2_t vs2, vint8mf2_t vs1,
+vint8m1_t test_vzip_vv_i8m1_m(vbool8_t vm, vint8mf2_t vs2, vint8mf2_t vs1,
size_t vl) {
return __riscv_vzip_vv_i8m1_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vzip_vv_i8m2_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> poison, <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> poison, <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
-vint8m2_t test_vzip_vv_i8m2_m(vbool8_t vm, vint8m1_t vs2, vint8m1_t vs1,
+vint8m2_t test_vzip_vv_i8m2_m(vbool4_t vm, vint8m1_t vs2, vint8m1_t vs1,
size_t vl) {
return __riscv_vzip_vv_i8m2_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vzip_vv_i8m4_m
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> poison, <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> poison, <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
-vint8m4_t test_vzip_vv_i8m4_m(vbool4_t vm, vint8m2_t vs2, vint8m2_t vs1,
+vint8m4_t test_vzip_vv_i8m4_m(vbool2_t vm, vint8m2_t vs2, vint8m2_t vs1,
size_t vl) {
return __riscv_vzip_vv_i8m4_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vzip_vv_i8m8_m
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 64 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> poison, <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> poison, <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 64 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
-vint8m8_t test_vzip_vv_i8m8_m(vbool2_t vm, vint8m4_t vs2, vint8m4_t vs1,
+vint8m8_t test_vzip_vv_i8m8_m(vbool1_t vm, vint8m4_t vs2, vint8m4_t vs1,
size_t vl) {
return __riscv_vzip_vv_i8m8_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vzip_vv_i16mf2_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> poison, <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> poison, <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
-vint16mf2_t test_vzip_vv_i16mf2_m(vbool64_t vm, vint16mf4_t vs2,
+vint16mf2_t test_vzip_vv_i16mf2_m(vbool32_t vm, vint16mf4_t vs2,
vint16mf4_t vs1, size_t vl) {
return __riscv_vzip_vv_i16mf2_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vzip_vv_i16m1_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
-vint16m1_t test_vzip_vv_i16m1_m(vbool32_t vm, vint16mf2_t vs2, vint16mf2_t vs1,
+vint16m1_t test_vzip_vv_i16m1_m(vbool16_t vm, vint16mf2_t vs2, vint16mf2_t vs1,
size_t vl) {
return __riscv_vzip_vv_i16m1_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vzip_vv_i16m2_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> poison, <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> poison, <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
-vint16m2_t test_vzip_vv_i16m2_m(vbool16_t vm, vint16m1_t vs2, vint16m1_t vs1,
+vint16m2_t test_vzip_vv_i16m2_m(vbool8_t vm, vint16m1_t vs2, vint16m1_t vs1,
size_t vl) {
return __riscv_vzip_vv_i16m2_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vzip_vv_i16m4_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> poison, <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> poison, <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
-vint16m4_t test_vzip_vv_i16m4_m(vbool8_t vm, vint16m2_t vs2, vint16m2_t vs1,
+vint16m4_t test_vzip_vv_i16m4_m(vbool4_t vm, vint16m2_t vs2, vint16m2_t vs1,
size_t vl) {
return __riscv_vzip_vv_i16m4_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vzip_vv_i16m8_m
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> poison, <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> poison, <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
-vint16m8_t test_vzip_vv_i16m8_m(vbool4_t vm, vint16m4_t vs2, vint16m4_t vs1,
+vint16m8_t test_vzip_vv_i16m8_m(vbool2_t vm, vint16m4_t vs2, vint16m4_t vs1,
size_t vl) {
return __riscv_vzip_vv_i16m8_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vzip_vv_i32m1_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> poison, <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> poison, <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vzip_vv_i32m1_m(vbool64_t vm, vint32mf2_t vs2, vint32mf2_t vs1,
+vint32m1_t test_vzip_vv_i32m1_m(vbool32_t vm, vint32mf2_t vs2, vint32mf2_t vs1,
size_t vl) {
return __riscv_vzip_vv_i32m1_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vzip_vv_i32m2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> poison, <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> poison, <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vzip_vv_i32m2_m(vbool32_t vm, vint32m1_t vs2, vint32m1_t vs1,
+vint32m2_t test_vzip_vv_i32m2_m(vbool16_t vm, vint32m1_t vs2, vint32m1_t vs1,
size_t vl) {
return __riscv_vzip_vv_i32m2_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vzip_vv_i32m4_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> poison, <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> poison, <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vzip_vv_i32m4_m(vbool16_t vm, vint32m2_t vs2, vint32m2_t vs1,
+vint32m4_t test_vzip_vv_i32m4_m(vbool8_t vm, vint32m2_t vs2, vint32m2_t vs1,
size_t vl) {
return __riscv_vzip_vv_i32m4_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vzip_vv_i32m8_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> poison, <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> poison, <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vzip_vv_i32m8_m(vbool8_t vm, vint32m4_t vs2, vint32m4_t vs1,
+vint32m8_t test_vzip_vv_i32m8_m(vbool4_t vm, vint32m4_t vs2, vint32m4_t vs1,
size_t vl) {
return __riscv_vzip_vv_i32m8_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vzip_vv_i64m2_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> poison, <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> poison, <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
-vint64m2_t test_vzip_vv_i64m2_m(vbool64_t vm, vint64m1_t vs2, vint64m1_t vs1,
+vint64m2_t test_vzip_vv_i64m2_m(vbool32_t vm, vint64m1_t vs2, vint64m1_t vs1,
size_t vl) {
return __riscv_vzip_vv_i64m2_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vzip_vv_i64m4_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> poison, <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> poison, <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
-vint64m4_t test_vzip_vv_i64m4_m(vbool32_t vm, vint64m2_t vs2, vint64m2_t vs1,
+vint64m4_t test_vzip_vv_i64m4_m(vbool16_t vm, vint64m2_t vs2, vint64m2_t vs1,
size_t vl) {
return __riscv_vzip_vv_i64m4_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vzip_vv_i64m8_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> poison, <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> poison, <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
-vint64m8_t test_vzip_vv_i64m8_m(vbool16_t vm, vint64m4_t vs2, vint64m4_t vs1,
+vint64m8_t test_vzip_vv_i64m8_m(vbool8_t vm, vint64m4_t vs2, vint64m4_t vs1,
size_t vl) {
return __riscv_vzip_vv_i64m8_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vzip_vv_u8mf4_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> poison, <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> poison, <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
-vuint8mf4_t test_vzip_vv_u8mf4_m(vbool64_t vm, vuint8mf8_t vs2, vuint8mf8_t vs1,
+vuint8mf4_t test_vzip_vv_u8mf4_m(vbool32_t vm, vuint8mf8_t vs2, vuint8mf8_t vs1,
size_t vl) {
return __riscv_vzip_vv_u8mf4_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vzip_vv_u8mf2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> poison, <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> poison, <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
-vuint8mf2_t test_vzip_vv_u8mf2_m(vbool32_t vm, vuint8mf4_t vs2, vuint8mf4_t vs1,
+vuint8mf2_t test_vzip_vv_u8mf2_m(vbool16_t vm, vuint8mf4_t vs2, vuint8mf4_t vs1,
size_t vl) {
return __riscv_vzip_vv_u8mf2_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vzip_vv_u8m1_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
-vuint8m1_t test_vzip_vv_u8m1_m(vbool16_t vm, vuint8mf2_t vs2, vuint8mf2_t vs1,
+vuint8m1_t test_vzip_vv_u8m1_m(vbool8_t vm, vuint8mf2_t vs2, vuint8mf2_t vs1,
size_t vl) {
return __riscv_vzip_vv_u8m1_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vzip_vv_u8m2_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> poison, <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> poison, <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
-vuint8m2_t test_vzip_vv_u8m2_m(vbool8_t vm, vuint8m1_t vs2, vuint8m1_t vs1,
+vuint8m2_t test_vzip_vv_u8m2_m(vbool4_t vm, vuint8m1_t vs2, vuint8m1_t vs1,
size_t vl) {
return __riscv_vzip_vv_u8m2_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vzip_vv_u8m4_m
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> poison, <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> poison, <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
-vuint8m4_t test_vzip_vv_u8m4_m(vbool4_t vm, vuint8m2_t vs2, vuint8m2_t vs1,
+vuint8m4_t test_vzip_vv_u8m4_m(vbool2_t vm, vuint8m2_t vs2, vuint8m2_t vs1,
size_t vl) {
return __riscv_vzip_vv_u8m4_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vzip_vv_u8m8_m
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 64 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> poison, <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> poison, <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 64 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
-vuint8m8_t test_vzip_vv_u8m8_m(vbool2_t vm, vuint8m4_t vs2, vuint8m4_t vs1,
+vuint8m8_t test_vzip_vv_u8m8_m(vbool1_t vm, vuint8m4_t vs2, vuint8m4_t vs1,
size_t vl) {
return __riscv_vzip_vv_u8m8_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vzip_vv_u16mf2_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> poison, <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> poison, <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
-vuint16mf2_t test_vzip_vv_u16mf2_m(vbool64_t vm, vuint16mf4_t vs2,
+vuint16mf2_t test_vzip_vv_u16mf2_m(vbool32_t vm, vuint16mf4_t vs2,
vuint16mf4_t vs1, size_t vl) {
return __riscv_vzip_vv_u16mf2_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vzip_vv_u16m1_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
-vuint16m1_t test_vzip_vv_u16m1_m(vbool32_t vm, vuint16mf2_t vs2,
+vuint16m1_t test_vzip_vv_u16m1_m(vbool16_t vm, vuint16mf2_t vs2,
vuint16mf2_t vs1, size_t vl) {
return __riscv_vzip_vv_u16m1_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vzip_vv_u16m2_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> poison, <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> poison, <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
-vuint16m2_t test_vzip_vv_u16m2_m(vbool16_t vm, vuint16m1_t vs2, vuint16m1_t vs1,
+vuint16m2_t test_vzip_vv_u16m2_m(vbool8_t vm, vuint16m1_t vs2, vuint16m1_t vs1,
size_t vl) {
return __riscv_vzip_vv_u16m2_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vzip_vv_u16m4_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> poison, <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> poison, <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
-vuint16m4_t test_vzip_vv_u16m4_m(vbool8_t vm, vuint16m2_t vs2, vuint16m2_t vs1,
+vuint16m4_t test_vzip_vv_u16m4_m(vbool4_t vm, vuint16m2_t vs2, vuint16m2_t vs1,
size_t vl) {
return __riscv_vzip_vv_u16m4_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vzip_vv_u16m8_m
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> poison, <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> poison, <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
-vuint16m8_t test_vzip_vv_u16m8_m(vbool4_t vm, vuint16m4_t vs2, vuint16m4_t vs1,
+vuint16m8_t test_vzip_vv_u16m8_m(vbool2_t vm, vuint16m4_t vs2, vuint16m4_t vs1,
size_t vl) {
return __riscv_vzip_vv_u16m8_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vzip_vv_u32m1_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> poison, <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> poison, <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vzip_vv_u32m1_m(vbool64_t vm, vuint32mf2_t vs2,
+vuint32m1_t test_vzip_vv_u32m1_m(vbool32_t vm, vuint32mf2_t vs2,
vuint32mf2_t vs1, size_t vl) {
return __riscv_vzip_vv_u32m1_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vzip_vv_u32m2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> poison, <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> poison, <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vzip_vv_u32m2_m(vbool32_t vm, vuint32m1_t vs2, vuint32m1_t vs1,
+vuint32m2_t test_vzip_vv_u32m2_m(vbool16_t vm, vuint32m1_t vs2, vuint32m1_t vs1,
size_t vl) {
return __riscv_vzip_vv_u32m2_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vzip_vv_u32m4_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> poison, <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> poison, <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vzip_vv_u32m4_m(vbool16_t vm, vuint32m2_t vs2, vuint32m2_t vs1,
+vuint32m4_t test_vzip_vv_u32m4_m(vbool8_t vm, vuint32m2_t vs2, vuint32m2_t vs1,
size_t vl) {
return __riscv_vzip_vv_u32m4_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vzip_vv_u32m8_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> poison, <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> poison, <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vzip_vv_u32m8_m(vbool8_t vm, vuint32m4_t vs2, vuint32m4_t vs1,
+vuint32m8_t test_vzip_vv_u32m8_m(vbool4_t vm, vuint32m4_t vs2, vuint32m4_t vs1,
size_t vl) {
return __riscv_vzip_vv_u32m8_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vzip_vv_u64m2_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> poison, <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> poison, <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
-vuint64m2_t test_vzip_vv_u64m2_m(vbool64_t vm, vuint64m1_t vs2, vuint64m1_t vs1,
+vuint64m2_t test_vzip_vv_u64m2_m(vbool32_t vm, vuint64m1_t vs2, vuint64m1_t vs1,
size_t vl) {
return __riscv_vzip_vv_u64m2_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vzip_vv_u64m4_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> poison, <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> poison, <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
-vuint64m4_t test_vzip_vv_u64m4_m(vbool32_t vm, vuint64m2_t vs2, vuint64m2_t vs1,
+vuint64m4_t test_vzip_vv_u64m4_m(vbool16_t vm, vuint64m2_t vs2, vuint64m2_t vs1,
size_t vl) {
return __riscv_vzip_vv_u64m4_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vzip_vv_u64m8_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> poison, <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> poison, <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
-vuint64m8_t test_vzip_vv_u64m8_m(vbool16_t vm, vuint64m4_t vs2, vuint64m4_t vs1,
+vuint64m8_t test_vzip_vv_u64m8_m(vbool8_t vm, vuint64m4_t vs2, vuint64m4_t vs1,
size_t vl) {
return __riscv_vzip_vv_u64m8_m(vm, vs2, vs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c
index c6ca796db8704..fbd2d54bdf6db 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c
@@ -489,485 +489,3 @@ vuint64m4_t test_vunzipe_v_u64m4(vuint64m8_t vs, size_t vl) {
return __riscv_vunzipe(vs, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vunzipe_v_f16mf4_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vunzipe.mask.nxv1f16.nxv2f16.i64(<vscale x 1 x half> poison, <vscale x 2 x half> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
-//
-vfloat16mf4_t test_vunzipe_v_f16mf4_m(vbool64_t vm, vfloat16mf2_t vs,
- size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vunzipe_v_f16mf2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vunzipe.mask.nxv2f16.nxv4f16.i64(<vscale x 2 x half> poison, <vscale x 4 x half> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
-//
-vfloat16mf2_t test_vunzipe_v_f16mf2_m(vbool32_t vm, vfloat16m1_t vs,
- size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vunzipe_v_f16m1_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vunzipe.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
-//
-vfloat16m1_t test_vunzipe_v_f16m1_m(vbool16_t vm, vfloat16m2_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vunzipe_v_f16m2_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vunzipe.mask.nxv8f16.nxv16f16.i64(<vscale x 8 x half> poison, <vscale x 16 x half> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
-//
-vfloat16m2_t test_vunzipe_v_f16m2_m(vbool8_t vm, vfloat16m4_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vunzipe_v_f16m4_m
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vunzipe.mask.nxv16f16.nxv32f16.i64(<vscale x 16 x half> poison, <vscale x 32 x half> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
-//
-vfloat16m4_t test_vunzipe_v_f16m4_m(vbool4_t vm, vfloat16m8_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vunzipe_v_f32mf2_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vunzipe.mask.nxv1f32.nxv2f32.i64(<vscale x 1 x float> poison, <vscale x 2 x float> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
-//
-vfloat32mf2_t test_vunzipe_v_f32mf2_m(vbool64_t vm, vfloat32m1_t vs,
- size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vunzipe_v_f32m1_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vunzipe.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
-//
-vfloat32m1_t test_vunzipe_v_f32m1_m(vbool32_t vm, vfloat32m2_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vunzipe_v_f32m2_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vunzipe.mask.nxv4f32.nxv8f32.i64(<vscale x 4 x float> poison, <vscale x 8 x float> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
-//
-vfloat32m2_t test_vunzipe_v_f32m2_m(vbool16_t vm, vfloat32m4_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vunzipe_v_f32m4_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vunzipe.mask.nxv8f32.nxv16f32.i64(<vscale x 8 x float> poison, <vscale x 16 x float> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
-//
-vfloat32m4_t test_vunzipe_v_f32m4_m(vbool8_t vm, vfloat32m8_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vunzipe_v_f64m1_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vunzipe.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
-//
-vfloat64m1_t test_vunzipe_v_f64m1_m(vbool64_t vm, vfloat64m2_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vunzipe_v_f64m2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vunzipe.mask.nxv2f64.nxv4f64.i64(<vscale x 2 x double> poison, <vscale x 4 x double> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
-//
-vfloat64m2_t test_vunzipe_v_f64m2_m(vbool32_t vm, vfloat64m4_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vunzipe_v_f64m4_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vunzipe.mask.nxv4f64.nxv8f64.i64(<vscale x 4 x double> poison, <vscale x 8 x double> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
-//
-vfloat64m4_t test_vunzipe_v_f64m4_m(vbool16_t vm, vfloat64m8_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vunzipe_v_i8mf8_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vunzipe.mask.nxv1i8.nxv2i8.i64(<vscale x 1 x i8> poison, <vscale x 2 x i8> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
-//
-vint8mf8_t test_vunzipe_v_i8mf8_m(vbool64_t vm, vint8mf4_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vunzipe_v_i8mf4_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vunzipe.mask.nxv2i8.nxv4i8.i64(<vscale x 2 x i8> poison, <vscale x 4 x i8> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
-//
-vint8mf4_t test_vunzipe_v_i8mf4_m(vbool32_t vm, vint8mf2_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vunzipe_v_i8mf2_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vunzipe.mask.nxv4i8.nxv8i8.i64(<vscale x 4 x i8> poison, <vscale x 8 x i8> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
-//
-vint8mf2_t test_vunzipe_v_i8mf2_m(vbool16_t vm, vint8m1_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vunzipe_v_i8m1_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vunzipe.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
-//
-vint8m1_t test_vunzipe_v_i8m1_m(vbool8_t vm, vint8m2_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vunzipe_v_i8m2_m
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vunzipe.mask.nxv16i8.nxv32i8.i64(<vscale x 16 x i8> poison, <vscale x 32 x i8> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-vint8m2_t test_vunzipe_v_i8m2_m(vbool4_t vm, vint8m4_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vunzipe_v_i8m4_m
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vunzipe.mask.nxv32i8.nxv64i8.i64(<vscale x 32 x i8> poison, <vscale x 64 x i8> [[VS]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
-//
-vint8m4_t test_vunzipe_v_i8m4_m(vbool2_t vm, vint8m8_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vunzipe_v_i16mf4_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vunzipe.mask.nxv1i16.nxv2i16.i64(<vscale x 1 x i16> poison, <vscale x 2 x i16> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
-//
-vint16mf4_t test_vunzipe_v_i16mf4_m(vbool64_t vm, vint16mf2_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vunzipe_v_i16mf2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vunzipe.mask.nxv2i16.nxv4i16.i64(<vscale x 2 x i16> poison, <vscale x 4 x i16> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
-//
-vint16mf2_t test_vunzipe_v_i16mf2_m(vbool32_t vm, vint16m1_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vunzipe_v_i16m1_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vunzipe.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> poison, <vscale x 8 x i16> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
-//
-vint16m1_t test_vunzipe_v_i16m1_m(vbool16_t vm, vint16m2_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vunzipe_v_i16m2_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vunzipe.mask.nxv8i16.nxv16i16.i64(<vscale x 8 x i16> poison, <vscale x 16 x i16> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-vint16m2_t test_vunzipe_v_i16m2_m(vbool8_t vm, vint16m4_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vunzipe_v_i16m4_m
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vunzipe.mask.nxv16i16.nxv32i16.i64(<vscale x 16 x i16> poison, <vscale x 32 x i16> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
-//
-vint16m4_t test_vunzipe_v_i16m4_m(vbool4_t vm, vint16m8_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vunzipe_v_i32mf2_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vunzipe.mask.nxv1i32.nxv2i32.i64(<vscale x 1 x i32> poison, <vscale x 2 x i32> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vunzipe_v_i32mf2_m(vbool64_t vm, vint32m1_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vunzipe_v_i32m1_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vunzipe.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> poison, <vscale x 4 x i32> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vunzipe_v_i32m1_m(vbool32_t vm, vint32m2_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vunzipe_v_i32m2_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vunzipe.mask.nxv4i32.nxv8i32.i64(<vscale x 4 x i32> poison, <vscale x 8 x i32> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vunzipe_v_i32m2_m(vbool16_t vm, vint32m4_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vunzipe_v_i32m4_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vunzipe.mask.nxv8i32.nxv16i32.i64(<vscale x 8 x i32> poison, <vscale x 16 x i32> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vunzipe_v_i32m4_m(vbool8_t vm, vint32m8_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vunzipe_v_i64m1_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vunzipe.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> poison, <vscale x 2 x i64> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
-//
-vint64m1_t test_vunzipe_v_i64m1_m(vbool64_t vm, vint64m2_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vunzipe_v_i64m2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vunzipe.mask.nxv2i64.nxv4i64.i64(<vscale x 2 x i64> poison, <vscale x 4 x i64> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-vint64m2_t test_vunzipe_v_i64m2_m(vbool32_t vm, vint64m4_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vunzipe_v_i64m4_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vunzipe.mask.nxv4i64.nxv8i64.i64(<vscale x 4 x i64> poison, <vscale x 8 x i64> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
-//
-vint64m4_t test_vunzipe_v_i64m4_m(vbool16_t vm, vint64m8_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vunzipe_v_u8mf8_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vunzipe.mask.nxv1i8.nxv2i8.i64(<vscale x 1 x i8> poison, <vscale x 2 x i8> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
-//
-vuint8mf8_t test_vunzipe_v_u8mf8_m(vbool64_t vm, vuint8mf4_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vunzipe_v_u8mf4_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vunzipe.mask.nxv2i8.nxv4i8.i64(<vscale x 2 x i8> poison, <vscale x 4 x i8> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
-//
-vuint8mf4_t test_vunzipe_v_u8mf4_m(vbool32_t vm, vuint8mf2_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vunzipe_v_u8mf2_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vunzipe.mask.nxv4i8.nxv8i8.i64(<vscale x 4 x i8> poison, <vscale x 8 x i8> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
-//
-vuint8mf2_t test_vunzipe_v_u8mf2_m(vbool16_t vm, vuint8m1_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vunzipe_v_u8m1_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vunzipe.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
-//
-vuint8m1_t test_vunzipe_v_u8m1_m(vbool8_t vm, vuint8m2_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vunzipe_v_u8m2_m
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vunzipe.mask.nxv16i8.nxv32i8.i64(<vscale x 16 x i8> poison, <vscale x 32 x i8> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-vuint8m2_t test_vunzipe_v_u8m2_m(vbool4_t vm, vuint8m4_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vunzipe_v_u8m4_m
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vunzipe.mask.nxv32i8.nxv64i8.i64(<vscale x 32 x i8> poison, <vscale x 64 x i8> [[VS]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
-//
-vuint8m4_t test_vunzipe_v_u8m4_m(vbool2_t vm, vuint8m8_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vunzipe_v_u16mf4_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vunzipe.mask.nxv1i16.nxv2i16.i64(<vscale x 1 x i16> poison, <vscale x 2 x i16> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
-//
-vuint16mf4_t test_vunzipe_v_u16mf4_m(vbool64_t vm, vuint16mf2_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vunzipe_v_u16mf2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vunzipe.mask.nxv2i16.nxv4i16.i64(<vscale x 2 x i16> poison, <vscale x 4 x i16> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
-//
-vuint16mf2_t test_vunzipe_v_u16mf2_m(vbool32_t vm, vuint16m1_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vunzipe_v_u16m1_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vunzipe.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> poison, <vscale x 8 x i16> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
-//
-vuint16m1_t test_vunzipe_v_u16m1_m(vbool16_t vm, vuint16m2_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vunzipe_v_u16m2_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vunzipe.mask.nxv8i16.nxv16i16.i64(<vscale x 8 x i16> poison, <vscale x 16 x i16> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-vuint16m2_t test_vunzipe_v_u16m2_m(vbool8_t vm, vuint16m4_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vunzipe_v_u16m4_m
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vunzipe.mask.nxv16i16.nxv32i16.i64(<vscale x 16 x i16> poison, <vscale x 32 x i16> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
-//
-vuint16m4_t test_vunzipe_v_u16m4_m(vbool4_t vm, vuint16m8_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vunzipe_v_u32mf2_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vunzipe.mask.nxv1i32.nxv2i32.i64(<vscale x 1 x i32> poison, <vscale x 2 x i32> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vuint32mf2_t test_vunzipe_v_u32mf2_m(vbool64_t vm, vuint32m1_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vunzipe_v_u32m1_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vunzipe.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> poison, <vscale x 4 x i32> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vuint32m1_t test_vunzipe_v_u32m1_m(vbool32_t vm, vuint32m2_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vunzipe_v_u32m2_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vunzipe.mask.nxv4i32.nxv8i32.i64(<vscale x 4 x i32> poison, <vscale x 8 x i32> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vuint32m2_t test_vunzipe_v_u32m2_m(vbool16_t vm, vuint32m4_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vunzipe_v_u32m4_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vunzipe.mask.nxv8i32.nxv16i32.i64(<vscale x 8 x i32> poison, <vscale x 16 x i32> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vuint32m4_t test_vunzipe_v_u32m4_m(vbool8_t vm, vuint32m8_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vunzipe_v_u64m1_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vunzipe.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> poison, <vscale x 2 x i64> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
-//
-vuint64m1_t test_vunzipe_v_u64m1_m(vbool64_t vm, vuint64m2_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vunzipe_v_u64m2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vunzipe.mask.nxv2i64.nxv4i64.i64(<vscale x 2 x i64> poison, <vscale x 4 x i64> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-vuint64m2_t test_vunzipe_v_u64m2_m(vbool32_t vm, vuint64m4_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vunzipe_v_u64m4_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vunzipe.mask.nxv4i64.nxv8i64.i64(<vscale x 4 x i64> poison, <vscale x 8 x i64> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
-//
-vuint64m4_t test_vunzipe_v_u64m4_m(vbool16_t vm, vuint64m8_t vs, size_t vl) {
- return __riscv_vunzipe(vm, vs, vl);
-}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c
index e3fca9a6485ce..ce0589c1e50f5 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c
@@ -489,485 +489,3 @@ vuint64m4_t test_vunzipo_v_u64m4(vuint64m8_t vs, size_t vl) {
return __riscv_vunzipo(vs, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vunzipo_v_f16mf4_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vunzipo.mask.nxv1f16.nxv2f16.i64(<vscale x 1 x half> poison, <vscale x 2 x half> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
-//
-vfloat16mf4_t test_vunzipo_v_f16mf4_m(vbool64_t vm, vfloat16mf2_t vs,
- size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vunzipo_v_f16mf2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vunzipo.mask.nxv2f16.nxv4f16.i64(<vscale x 2 x half> poison, <vscale x 4 x half> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
-//
-vfloat16mf2_t test_vunzipo_v_f16mf2_m(vbool32_t vm, vfloat16m1_t vs,
- size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vunzipo_v_f16m1_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vunzipo.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> poison, <vscale x 8 x half> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
-//
-vfloat16m1_t test_vunzipo_v_f16m1_m(vbool16_t vm, vfloat16m2_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vunzipo_v_f16m2_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vunzipo.mask.nxv8f16.nxv16f16.i64(<vscale x 8 x half> poison, <vscale x 16 x half> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
-//
-vfloat16m2_t test_vunzipo_v_f16m2_m(vbool8_t vm, vfloat16m4_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vunzipo_v_f16m4_m
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vunzipo.mask.nxv16f16.nxv32f16.i64(<vscale x 16 x half> poison, <vscale x 32 x half> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
-//
-vfloat16m4_t test_vunzipo_v_f16m4_m(vbool4_t vm, vfloat16m8_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vunzipo_v_f32mf2_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vunzipo.mask.nxv1f32.nxv2f32.i64(<vscale x 1 x float> poison, <vscale x 2 x float> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
-//
-vfloat32mf2_t test_vunzipo_v_f32mf2_m(vbool64_t vm, vfloat32m1_t vs,
- size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vunzipo_v_f32m1_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vunzipo.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> poison, <vscale x 4 x float> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
-//
-vfloat32m1_t test_vunzipo_v_f32m1_m(vbool32_t vm, vfloat32m2_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vunzipo_v_f32m2_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vunzipo.mask.nxv4f32.nxv8f32.i64(<vscale x 4 x float> poison, <vscale x 8 x float> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
-//
-vfloat32m2_t test_vunzipo_v_f32m2_m(vbool16_t vm, vfloat32m4_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vunzipo_v_f32m4_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vunzipo.mask.nxv8f32.nxv16f32.i64(<vscale x 8 x float> poison, <vscale x 16 x float> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
-//
-vfloat32m4_t test_vunzipo_v_f32m4_m(vbool8_t vm, vfloat32m8_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vunzipo_v_f64m1_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vunzipo.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> poison, <vscale x 2 x double> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
-//
-vfloat64m1_t test_vunzipo_v_f64m1_m(vbool64_t vm, vfloat64m2_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vunzipo_v_f64m2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vunzipo.mask.nxv2f64.nxv4f64.i64(<vscale x 2 x double> poison, <vscale x 4 x double> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
-//
-vfloat64m2_t test_vunzipo_v_f64m2_m(vbool32_t vm, vfloat64m4_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vunzipo_v_f64m4_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vunzipo.mask.nxv4f64.nxv8f64.i64(<vscale x 4 x double> poison, <vscale x 8 x double> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
-//
-vfloat64m4_t test_vunzipo_v_f64m4_m(vbool16_t vm, vfloat64m8_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vunzipo_v_i8mf8_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vunzipo.mask.nxv1i8.nxv2i8.i64(<vscale x 1 x i8> poison, <vscale x 2 x i8> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
-//
-vint8mf8_t test_vunzipo_v_i8mf8_m(vbool64_t vm, vint8mf4_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vunzipo_v_i8mf4_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vunzipo.mask.nxv2i8.nxv4i8.i64(<vscale x 2 x i8> poison, <vscale x 4 x i8> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
-//
-vint8mf4_t test_vunzipo_v_i8mf4_m(vbool32_t vm, vint8mf2_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vunzipo_v_i8mf2_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vunzipo.mask.nxv4i8.nxv8i8.i64(<vscale x 4 x i8> poison, <vscale x 8 x i8> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
-//
-vint8mf2_t test_vunzipo_v_i8mf2_m(vbool16_t vm, vint8m1_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vunzipo_v_i8m1_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vunzipo.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
-//
-vint8m1_t test_vunzipo_v_i8m1_m(vbool8_t vm, vint8m2_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vunzipo_v_i8m2_m
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vunzipo.mask.nxv16i8.nxv32i8.i64(<vscale x 16 x i8> poison, <vscale x 32 x i8> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-vint8m2_t test_vunzipo_v_i8m2_m(vbool4_t vm, vint8m4_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vunzipo_v_i8m4_m
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vunzipo.mask.nxv32i8.nxv64i8.i64(<vscale x 32 x i8> poison, <vscale x 64 x i8> [[VS]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
-//
-vint8m4_t test_vunzipo_v_i8m4_m(vbool2_t vm, vint8m8_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vunzipo_v_i16mf4_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vunzipo.mask.nxv1i16.nxv2i16.i64(<vscale x 1 x i16> poison, <vscale x 2 x i16> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
-//
-vint16mf4_t test_vunzipo_v_i16mf4_m(vbool64_t vm, vint16mf2_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vunzipo_v_i16mf2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vunzipo.mask.nxv2i16.nxv4i16.i64(<vscale x 2 x i16> poison, <vscale x 4 x i16> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
-//
-vint16mf2_t test_vunzipo_v_i16mf2_m(vbool32_t vm, vint16m1_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vunzipo_v_i16m1_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vunzipo.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> poison, <vscale x 8 x i16> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
-//
-vint16m1_t test_vunzipo_v_i16m1_m(vbool16_t vm, vint16m2_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vunzipo_v_i16m2_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vunzipo.mask.nxv8i16.nxv16i16.i64(<vscale x 8 x i16> poison, <vscale x 16 x i16> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-vint16m2_t test_vunzipo_v_i16m2_m(vbool8_t vm, vint16m4_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vunzipo_v_i16m4_m
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vunzipo.mask.nxv16i16.nxv32i16.i64(<vscale x 16 x i16> poison, <vscale x 32 x i16> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
-//
-vint16m4_t test_vunzipo_v_i16m4_m(vbool4_t vm, vint16m8_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vunzipo_v_i32mf2_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vunzipo.mask.nxv1i32.nxv2i32.i64(<vscale x 1 x i32> poison, <vscale x 2 x i32> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vunzipo_v_i32mf2_m(vbool64_t vm, vint32m1_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vunzipo_v_i32m1_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vunzipo.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> poison, <vscale x 4 x i32> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vunzipo_v_i32m1_m(vbool32_t vm, vint32m2_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vunzipo_v_i32m2_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vunzipo.mask.nxv4i32.nxv8i32.i64(<vscale x 4 x i32> poison, <vscale x 8 x i32> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vunzipo_v_i32m2_m(vbool16_t vm, vint32m4_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vunzipo_v_i32m4_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vunzipo.mask.nxv8i32.nxv16i32.i64(<vscale x 8 x i32> poison, <vscale x 16 x i32> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vunzipo_v_i32m4_m(vbool8_t vm, vint32m8_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vunzipo_v_i64m1_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vunzipo.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> poison, <vscale x 2 x i64> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
-//
-vint64m1_t test_vunzipo_v_i64m1_m(vbool64_t vm, vint64m2_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vunzipo_v_i64m2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vunzipo.mask.nxv2i64.nxv4i64.i64(<vscale x 2 x i64> poison, <vscale x 4 x i64> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-vint64m2_t test_vunzipo_v_i64m2_m(vbool32_t vm, vint64m4_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vunzipo_v_i64m4_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vunzipo.mask.nxv4i64.nxv8i64.i64(<vscale x 4 x i64> poison, <vscale x 8 x i64> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
-//
-vint64m4_t test_vunzipo_v_i64m4_m(vbool16_t vm, vint64m8_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vunzipo_v_u8mf8_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vunzipo.mask.nxv1i8.nxv2i8.i64(<vscale x 1 x i8> poison, <vscale x 2 x i8> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
-//
-vuint8mf8_t test_vunzipo_v_u8mf8_m(vbool64_t vm, vuint8mf4_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vunzipo_v_u8mf4_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vunzipo.mask.nxv2i8.nxv4i8.i64(<vscale x 2 x i8> poison, <vscale x 4 x i8> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
-//
-vuint8mf4_t test_vunzipo_v_u8mf4_m(vbool32_t vm, vuint8mf2_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vunzipo_v_u8mf2_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vunzipo.mask.nxv4i8.nxv8i8.i64(<vscale x 4 x i8> poison, <vscale x 8 x i8> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
-//
-vuint8mf2_t test_vunzipo_v_u8mf2_m(vbool16_t vm, vuint8m1_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vunzipo_v_u8m1_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vunzipo.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> poison, <vscale x 16 x i8> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
-//
-vuint8m1_t test_vunzipo_v_u8m1_m(vbool8_t vm, vuint8m2_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vunzipo_v_u8m2_m
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vunzipo.mask.nxv16i8.nxv32i8.i64(<vscale x 16 x i8> poison, <vscale x 32 x i8> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-vuint8m2_t test_vunzipo_v_u8m2_m(vbool4_t vm, vuint8m4_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vunzipo_v_u8m4_m
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vunzipo.mask.nxv32i8.nxv64i8.i64(<vscale x 32 x i8> poison, <vscale x 64 x i8> [[VS]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
-//
-vuint8m4_t test_vunzipo_v_u8m4_m(vbool2_t vm, vuint8m8_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vunzipo_v_u16mf4_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vunzipo.mask.nxv1i16.nxv2i16.i64(<vscale x 1 x i16> poison, <vscale x 2 x i16> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
-//
-vuint16mf4_t test_vunzipo_v_u16mf4_m(vbool64_t vm, vuint16mf2_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vunzipo_v_u16mf2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vunzipo.mask.nxv2i16.nxv4i16.i64(<vscale x 2 x i16> poison, <vscale x 4 x i16> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
-//
-vuint16mf2_t test_vunzipo_v_u16mf2_m(vbool32_t vm, vuint16m1_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vunzipo_v_u16m1_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vunzipo.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> poison, <vscale x 8 x i16> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
-//
-vuint16m1_t test_vunzipo_v_u16m1_m(vbool16_t vm, vuint16m2_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vunzipo_v_u16m2_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vunzipo.mask.nxv8i16.nxv16i16.i64(<vscale x 8 x i16> poison, <vscale x 16 x i16> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-vuint16m2_t test_vunzipo_v_u16m2_m(vbool8_t vm, vuint16m4_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vunzipo_v_u16m4_m
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vunzipo.mask.nxv16i16.nxv32i16.i64(<vscale x 16 x i16> poison, <vscale x 32 x i16> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
-//
-vuint16m4_t test_vunzipo_v_u16m4_m(vbool4_t vm, vuint16m8_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vunzipo_v_u32mf2_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vunzipo.mask.nxv1i32.nxv2i32.i64(<vscale x 1 x i32> poison, <vscale x 2 x i32> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vuint32mf2_t test_vunzipo_v_u32mf2_m(vbool64_t vm, vuint32m1_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vunzipo_v_u32m1_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vunzipo.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> poison, <vscale x 4 x i32> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vuint32m1_t test_vunzipo_v_u32m1_m(vbool32_t vm, vuint32m2_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vunzipo_v_u32m2_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vunzipo.mask.nxv4i32.nxv8i32.i64(<vscale x 4 x i32> poison, <vscale x 8 x i32> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vuint32m2_t test_vunzipo_v_u32m2_m(vbool16_t vm, vuint32m4_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vunzipo_v_u32m4_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vunzipo.mask.nxv8i32.nxv16i32.i64(<vscale x 8 x i32> poison, <vscale x 16 x i32> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vuint32m4_t test_vunzipo_v_u32m4_m(vbool8_t vm, vuint32m8_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vunzipo_v_u64m1_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vunzipo.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> poison, <vscale x 2 x i64> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
-//
-vuint64m1_t test_vunzipo_v_u64m1_m(vbool64_t vm, vuint64m2_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vunzipo_v_u64m2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vunzipo.mask.nxv2i64.nxv4i64.i64(<vscale x 2 x i64> poison, <vscale x 4 x i64> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-vuint64m2_t test_vunzipo_v_u64m2_m(vbool32_t vm, vuint64m4_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vunzipo_v_u64m4_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vunzipo.mask.nxv4i64.nxv8i64.i64(<vscale x 4 x i64> poison, <vscale x 8 x i64> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
-//
-vuint64m4_t test_vunzipo_v_u64m4_m(vbool16_t vm, vuint64m8_t vs, size_t vl) {
- return __riscv_vunzipo(vm, vs, vl);
-}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c
index d08189b0ec7b9..8fcdf202d492f 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c
@@ -494,529 +494,529 @@ vuint64m8_t test_vzip_vv_u64m8(vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) {
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vzip_vv_f16mf2_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vzip.mask.nxv2f16.nxv1f16.i64(<vscale x 2 x half> poison, <vscale x 1 x half> [[VS2]], <vscale x 1 x half> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vzip.mask.nxv2f16.nxv1f16.i64(<vscale x 2 x half> poison, <vscale x 1 x half> [[VS2]], <vscale x 1 x half> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
-vfloat16mf2_t test_vzip_vv_f16mf2_m(vbool64_t vm, vfloat16mf4_t vs2,
+vfloat16mf2_t test_vzip_vv_f16mf2_m(vbool32_t vm, vfloat16mf4_t vs2,
vfloat16mf4_t vs1, size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vzip_vv_f16m1_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vzip.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> [[VS2]], <vscale x 2 x half> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vzip.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> poison, <vscale x 2 x half> [[VS2]], <vscale x 2 x half> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
-vfloat16m1_t test_vzip_vv_f16m1_m(vbool32_t vm, vfloat16mf2_t vs2,
+vfloat16m1_t test_vzip_vv_f16m1_m(vbool16_t vm, vfloat16mf2_t vs2,
vfloat16mf2_t vs1, size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vzip_vv_f16m2_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vzip.mask.nxv8f16.nxv4f16.i64(<vscale x 8 x half> poison, <vscale x 4 x half> [[VS2]], <vscale x 4 x half> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vzip.mask.nxv8f16.nxv4f16.i64(<vscale x 8 x half> poison, <vscale x 4 x half> [[VS2]], <vscale x 4 x half> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
-vfloat16m2_t test_vzip_vv_f16m2_m(vbool16_t vm, vfloat16m1_t vs2,
+vfloat16m2_t test_vzip_vv_f16m2_m(vbool8_t vm, vfloat16m1_t vs2,
vfloat16m1_t vs1, size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vzip_vv_f16m4_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vzip.mask.nxv16f16.nxv8f16.i64(<vscale x 16 x half> poison, <vscale x 8 x half> [[VS2]], <vscale x 8 x half> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vzip.mask.nxv16f16.nxv8f16.i64(<vscale x 16 x half> poison, <vscale x 8 x half> [[VS2]], <vscale x 8 x half> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
-vfloat16m4_t test_vzip_vv_f16m4_m(vbool8_t vm, vfloat16m2_t vs2,
+vfloat16m4_t test_vzip_vv_f16m4_m(vbool4_t vm, vfloat16m2_t vs2,
vfloat16m2_t vs1, size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vzip_vv_f16m8_m
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vzip.mask.nxv32f16.nxv16f16.i64(<vscale x 32 x half> poison, <vscale x 16 x half> [[VS2]], <vscale x 16 x half> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vzip.mask.nxv32f16.nxv16f16.i64(<vscale x 32 x half> poison, <vscale x 16 x half> [[VS2]], <vscale x 16 x half> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
-vfloat16m8_t test_vzip_vv_f16m8_m(vbool4_t vm, vfloat16m4_t vs2,
+vfloat16m8_t test_vzip_vv_f16m8_m(vbool2_t vm, vfloat16m4_t vs2,
vfloat16m4_t vs1, size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vzip_vv_f32m1_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x float> [[VS2:%.*]], <vscale x 1 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 1 x float> [[VS2:%.*]], <vscale x 1 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vzip.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> [[VS2]], <vscale x 1 x float> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vzip.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> poison, <vscale x 1 x float> [[VS2]], <vscale x 1 x float> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
-vfloat32m1_t test_vzip_vv_f32m1_m(vbool64_t vm, vfloat32mf2_t vs2,
+vfloat32m1_t test_vzip_vv_f32m1_m(vbool32_t vm, vfloat32mf2_t vs2,
vfloat32mf2_t vs1, size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vzip_vv_f32m2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VS2:%.*]], <vscale x 2 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 2 x float> [[VS2:%.*]], <vscale x 2 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vzip.mask.nxv4f32.nxv2f32.i64(<vscale x 4 x float> poison, <vscale x 2 x float> [[VS2]], <vscale x 2 x float> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vzip.mask.nxv4f32.nxv2f32.i64(<vscale x 4 x float> poison, <vscale x 2 x float> [[VS2]], <vscale x 2 x float> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
-vfloat32m2_t test_vzip_vv_f32m2_m(vbool32_t vm, vfloat32m1_t vs2,
+vfloat32m2_t test_vzip_vv_f32m2_m(vbool16_t vm, vfloat32m1_t vs2,
vfloat32m1_t vs1, size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vzip_vv_f32m4_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VS2:%.*]], <vscale x 4 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 4 x float> [[VS2:%.*]], <vscale x 4 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vzip.mask.nxv8f32.nxv4f32.i64(<vscale x 8 x float> poison, <vscale x 4 x float> [[VS2]], <vscale x 4 x float> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vzip.mask.nxv8f32.nxv4f32.i64(<vscale x 8 x float> poison, <vscale x 4 x float> [[VS2]], <vscale x 4 x float> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
-vfloat32m4_t test_vzip_vv_f32m4_m(vbool16_t vm, vfloat32m2_t vs2,
+vfloat32m4_t test_vzip_vv_f32m4_m(vbool8_t vm, vfloat32m2_t vs2,
vfloat32m2_t vs1, size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vzip_vv_f32m8_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VS2:%.*]], <vscale x 8 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 8 x float> [[VS2:%.*]], <vscale x 8 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vzip.mask.nxv16f32.nxv8f32.i64(<vscale x 16 x float> poison, <vscale x 8 x float> [[VS2]], <vscale x 8 x float> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vzip.mask.nxv16f32.nxv8f32.i64(<vscale x 16 x float> poison, <vscale x 8 x float> [[VS2]], <vscale x 8 x float> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
-vfloat32m8_t test_vzip_vv_f32m8_m(vbool8_t vm, vfloat32m4_t vs2,
+vfloat32m8_t test_vzip_vv_f32m8_m(vbool4_t vm, vfloat32m4_t vs2,
vfloat32m4_t vs1, size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vzip_vv_f64m2_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x double> [[VS2:%.*]], <vscale x 1 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 1 x double> [[VS2:%.*]], <vscale x 1 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vzip.mask.nxv2f64.nxv1f64.i64(<vscale x 2 x double> poison, <vscale x 1 x double> [[VS2]], <vscale x 1 x double> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vzip.mask.nxv2f64.nxv1f64.i64(<vscale x 2 x double> poison, <vscale x 1 x double> [[VS2]], <vscale x 1 x double> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
-vfloat64m2_t test_vzip_vv_f64m2_m(vbool64_t vm, vfloat64m1_t vs2,
+vfloat64m2_t test_vzip_vv_f64m2_m(vbool32_t vm, vfloat64m1_t vs2,
vfloat64m1_t vs1, size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vzip_vv_f64m4_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x double> [[VS2:%.*]], <vscale x 2 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 2 x double> [[VS2:%.*]], <vscale x 2 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vzip.mask.nxv4f64.nxv2f64.i64(<vscale x 4 x double> poison, <vscale x 2 x double> [[VS2]], <vscale x 2 x double> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vzip.mask.nxv4f64.nxv2f64.i64(<vscale x 4 x double> poison, <vscale x 2 x double> [[VS2]], <vscale x 2 x double> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
-vfloat64m4_t test_vzip_vv_f64m4_m(vbool32_t vm, vfloat64m2_t vs2,
+vfloat64m4_t test_vzip_vv_f64m4_m(vbool16_t vm, vfloat64m2_t vs2,
vfloat64m2_t vs1, size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vzip_vv_f64m8_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x double> [[VS2:%.*]], <vscale x 4 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 4 x double> [[VS2:%.*]], <vscale x 4 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vzip.mask.nxv8f64.nxv4f64.i64(<vscale x 8 x double> poison, <vscale x 4 x double> [[VS2]], <vscale x 4 x double> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vzip.mask.nxv8f64.nxv4f64.i64(<vscale x 8 x double> poison, <vscale x 4 x double> [[VS2]], <vscale x 4 x double> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
-vfloat64m8_t test_vzip_vv_f64m8_m(vbool16_t vm, vfloat64m4_t vs2,
+vfloat64m8_t test_vzip_vv_f64m8_m(vbool8_t vm, vfloat64m4_t vs2,
vfloat64m4_t vs1, size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vzip_vv_i8mf4_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> poison, <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> poison, <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
-vint8mf4_t test_vzip_vv_i8mf4_m(vbool64_t vm, vint8mf8_t vs2, vint8mf8_t vs1,
+vint8mf4_t test_vzip_vv_i8mf4_m(vbool32_t vm, vint8mf8_t vs2, vint8mf8_t vs1,
size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vzip_vv_i8mf2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> poison, <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> poison, <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
-vint8mf2_t test_vzip_vv_i8mf2_m(vbool32_t vm, vint8mf4_t vs2, vint8mf4_t vs1,
+vint8mf2_t test_vzip_vv_i8mf2_m(vbool16_t vm, vint8mf4_t vs2, vint8mf4_t vs1,
size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vzip_vv_i8m1_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
-vint8m1_t test_vzip_vv_i8m1_m(vbool16_t vm, vint8mf2_t vs2, vint8mf2_t vs1,
+vint8m1_t test_vzip_vv_i8m1_m(vbool8_t vm, vint8mf2_t vs2, vint8mf2_t vs1,
size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vzip_vv_i8m2_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> poison, <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> poison, <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
-vint8m2_t test_vzip_vv_i8m2_m(vbool8_t vm, vint8m1_t vs2, vint8m1_t vs1,
+vint8m2_t test_vzip_vv_i8m2_m(vbool4_t vm, vint8m1_t vs2, vint8m1_t vs1,
size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vzip_vv_i8m4_m
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> poison, <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> poison, <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
-vint8m4_t test_vzip_vv_i8m4_m(vbool4_t vm, vint8m2_t vs2, vint8m2_t vs1,
+vint8m4_t test_vzip_vv_i8m4_m(vbool2_t vm, vint8m2_t vs2, vint8m2_t vs1,
size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vzip_vv_i8m8_m
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 64 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> poison, <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> poison, <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 64 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
-vint8m8_t test_vzip_vv_i8m8_m(vbool2_t vm, vint8m4_t vs2, vint8m4_t vs1,
+vint8m8_t test_vzip_vv_i8m8_m(vbool1_t vm, vint8m4_t vs2, vint8m4_t vs1,
size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vzip_vv_i16mf2_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> poison, <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> poison, <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
-vint16mf2_t test_vzip_vv_i16mf2_m(vbool64_t vm, vint16mf4_t vs2,
+vint16mf2_t test_vzip_vv_i16mf2_m(vbool32_t vm, vint16mf4_t vs2,
vint16mf4_t vs1, size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vzip_vv_i16m1_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
-vint16m1_t test_vzip_vv_i16m1_m(vbool32_t vm, vint16mf2_t vs2, vint16mf2_t vs1,
+vint16m1_t test_vzip_vv_i16m1_m(vbool16_t vm, vint16mf2_t vs2, vint16mf2_t vs1,
size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vzip_vv_i16m2_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> poison, <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> poison, <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
-vint16m2_t test_vzip_vv_i16m2_m(vbool16_t vm, vint16m1_t vs2, vint16m1_t vs1,
+vint16m2_t test_vzip_vv_i16m2_m(vbool8_t vm, vint16m1_t vs2, vint16m1_t vs1,
size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vzip_vv_i16m4_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> poison, <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> poison, <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
-vint16m4_t test_vzip_vv_i16m4_m(vbool8_t vm, vint16m2_t vs2, vint16m2_t vs1,
+vint16m4_t test_vzip_vv_i16m4_m(vbool4_t vm, vint16m2_t vs2, vint16m2_t vs1,
size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vzip_vv_i16m8_m
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> poison, <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> poison, <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
-vint16m8_t test_vzip_vv_i16m8_m(vbool4_t vm, vint16m4_t vs2, vint16m4_t vs1,
+vint16m8_t test_vzip_vv_i16m8_m(vbool2_t vm, vint16m4_t vs2, vint16m4_t vs1,
size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vzip_vv_i32m1_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> poison, <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> poison, <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vzip_vv_i32m1_m(vbool64_t vm, vint32mf2_t vs2, vint32mf2_t vs1,
+vint32m1_t test_vzip_vv_i32m1_m(vbool32_t vm, vint32mf2_t vs2, vint32mf2_t vs1,
size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vzip_vv_i32m2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> poison, <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> poison, <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vzip_vv_i32m2_m(vbool32_t vm, vint32m1_t vs2, vint32m1_t vs1,
+vint32m2_t test_vzip_vv_i32m2_m(vbool16_t vm, vint32m1_t vs2, vint32m1_t vs1,
size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vzip_vv_i32m4_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> poison, <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> poison, <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vzip_vv_i32m4_m(vbool16_t vm, vint32m2_t vs2, vint32m2_t vs1,
+vint32m4_t test_vzip_vv_i32m4_m(vbool8_t vm, vint32m2_t vs2, vint32m2_t vs1,
size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vzip_vv_i32m8_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> poison, <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> poison, <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vzip_vv_i32m8_m(vbool8_t vm, vint32m4_t vs2, vint32m4_t vs1,
+vint32m8_t test_vzip_vv_i32m8_m(vbool4_t vm, vint32m4_t vs2, vint32m4_t vs1,
size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vzip_vv_i64m2_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> poison, <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> poison, <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
-vint64m2_t test_vzip_vv_i64m2_m(vbool64_t vm, vint64m1_t vs2, vint64m1_t vs1,
+vint64m2_t test_vzip_vv_i64m2_m(vbool32_t vm, vint64m1_t vs2, vint64m1_t vs1,
size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vzip_vv_i64m4_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> poison, <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> poison, <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
-vint64m4_t test_vzip_vv_i64m4_m(vbool32_t vm, vint64m2_t vs2, vint64m2_t vs1,
+vint64m4_t test_vzip_vv_i64m4_m(vbool16_t vm, vint64m2_t vs2, vint64m2_t vs1,
size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vzip_vv_i64m8_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> poison, <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> poison, <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
-vint64m8_t test_vzip_vv_i64m8_m(vbool16_t vm, vint64m4_t vs2, vint64m4_t vs1,
+vint64m8_t test_vzip_vv_i64m8_m(vbool8_t vm, vint64m4_t vs2, vint64m4_t vs1,
size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vzip_vv_u8mf4_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> poison, <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> poison, <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
-vuint8mf4_t test_vzip_vv_u8mf4_m(vbool64_t vm, vuint8mf8_t vs2, vuint8mf8_t vs1,
+vuint8mf4_t test_vzip_vv_u8mf4_m(vbool32_t vm, vuint8mf8_t vs2, vuint8mf8_t vs1,
size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vzip_vv_u8mf2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> poison, <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> poison, <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
-vuint8mf2_t test_vzip_vv_u8mf2_m(vbool32_t vm, vuint8mf4_t vs2, vuint8mf4_t vs1,
+vuint8mf2_t test_vzip_vv_u8mf2_m(vbool16_t vm, vuint8mf4_t vs2, vuint8mf4_t vs1,
size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vzip_vv_u8m1_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> poison, <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
-vuint8m1_t test_vzip_vv_u8m1_m(vbool16_t vm, vuint8mf2_t vs2, vuint8mf2_t vs1,
+vuint8m1_t test_vzip_vv_u8m1_m(vbool8_t vm, vuint8mf2_t vs2, vuint8mf2_t vs1,
size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vzip_vv_u8m2_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> poison, <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> poison, <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
-vuint8m2_t test_vzip_vv_u8m2_m(vbool8_t vm, vuint8m1_t vs2, vuint8m1_t vs1,
+vuint8m2_t test_vzip_vv_u8m2_m(vbool4_t vm, vuint8m1_t vs2, vuint8m1_t vs1,
size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vzip_vv_u8m4_m
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> poison, <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> poison, <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
-vuint8m4_t test_vzip_vv_u8m4_m(vbool4_t vm, vuint8m2_t vs2, vuint8m2_t vs1,
+vuint8m4_t test_vzip_vv_u8m4_m(vbool2_t vm, vuint8m2_t vs2, vuint8m2_t vs1,
size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vzip_vv_u8m8_m
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 64 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> poison, <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> poison, <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 64 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
-vuint8m8_t test_vzip_vv_u8m8_m(vbool2_t vm, vuint8m4_t vs2, vuint8m4_t vs1,
+vuint8m8_t test_vzip_vv_u8m8_m(vbool1_t vm, vuint8m4_t vs2, vuint8m4_t vs1,
size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vzip_vv_u16mf2_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> poison, <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> poison, <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
-vuint16mf2_t test_vzip_vv_u16mf2_m(vbool64_t vm, vuint16mf4_t vs2,
+vuint16mf2_t test_vzip_vv_u16mf2_m(vbool32_t vm, vuint16mf4_t vs2,
vuint16mf4_t vs1, size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vzip_vv_u16m1_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> poison, <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
-vuint16m1_t test_vzip_vv_u16m1_m(vbool32_t vm, vuint16mf2_t vs2,
+vuint16m1_t test_vzip_vv_u16m1_m(vbool16_t vm, vuint16mf2_t vs2,
vuint16mf2_t vs1, size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vzip_vv_u16m2_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> poison, <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> poison, <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
-vuint16m2_t test_vzip_vv_u16m2_m(vbool16_t vm, vuint16m1_t vs2, vuint16m1_t vs1,
+vuint16m2_t test_vzip_vv_u16m2_m(vbool8_t vm, vuint16m1_t vs2, vuint16m1_t vs1,
size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vzip_vv_u16m4_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> poison, <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> poison, <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
-vuint16m4_t test_vzip_vv_u16m4_m(vbool8_t vm, vuint16m2_t vs2, vuint16m2_t vs1,
+vuint16m4_t test_vzip_vv_u16m4_m(vbool4_t vm, vuint16m2_t vs2, vuint16m2_t vs1,
size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vzip_vv_u16m8_m
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> poison, <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> poison, <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
-vuint16m8_t test_vzip_vv_u16m8_m(vbool4_t vm, vuint16m4_t vs2, vuint16m4_t vs1,
+vuint16m8_t test_vzip_vv_u16m8_m(vbool2_t vm, vuint16m4_t vs2, vuint16m4_t vs1,
size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vzip_vv_u32m1_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> poison, <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> poison, <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vzip_vv_u32m1_m(vbool64_t vm, vuint32mf2_t vs2,
+vuint32m1_t test_vzip_vv_u32m1_m(vbool32_t vm, vuint32mf2_t vs2,
vuint32mf2_t vs1, size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vzip_vv_u32m2_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> poison, <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> poison, <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vzip_vv_u32m2_m(vbool32_t vm, vuint32m1_t vs2, vuint32m1_t vs1,
+vuint32m2_t test_vzip_vv_u32m2_m(vbool16_t vm, vuint32m1_t vs2, vuint32m1_t vs1,
size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vzip_vv_u32m4_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> poison, <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> poison, <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vzip_vv_u32m4_m(vbool16_t vm, vuint32m2_t vs2, vuint32m2_t vs1,
+vuint32m4_t test_vzip_vv_u32m4_m(vbool8_t vm, vuint32m2_t vs2, vuint32m2_t vs1,
size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vzip_vv_u32m8_m
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> poison, <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> poison, <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vzip_vv_u32m8_m(vbool8_t vm, vuint32m4_t vs2, vuint32m4_t vs1,
+vuint32m8_t test_vzip_vv_u32m8_m(vbool4_t vm, vuint32m4_t vs2, vuint32m4_t vs1,
size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vzip_vv_u64m2_m
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> poison, <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> poison, <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
-vuint64m2_t test_vzip_vv_u64m2_m(vbool64_t vm, vuint64m1_t vs2, vuint64m1_t vs1,
+vuint64m2_t test_vzip_vv_u64m2_m(vbool32_t vm, vuint64m1_t vs2, vuint64m1_t vs1,
size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vzip_vv_u64m4_m
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> poison, <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> poison, <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
-vuint64m4_t test_vzip_vv_u64m4_m(vbool32_t vm, vuint64m2_t vs2, vuint64m2_t vs1,
+vuint64m4_t test_vzip_vv_u64m4_m(vbool16_t vm, vuint64m2_t vs2, vuint64m2_t vs1,
size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vzip_vv_u64m8_m
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> poison, <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> poison, <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
-vuint64m8_t test_vzip_vv_u64m8_m(vbool16_t vm, vuint64m4_t vs2, vuint64m4_t vs1,
+vuint64m8_t test_vzip_vv_u64m8_m(vbool8_t vm, vuint64m4_t vs2, vuint64m4_t vs1,
size_t vl) {
return __riscv_vzip(vm, vs2, vs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c
index b516b276ed9c1..7bf301ebbbe68 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c
@@ -505,1586 +505,3 @@ vuint64m4_t test_vunzipe_v_u64m4_tu(vuint64m4_t vd, vuint64m8_t vs, size_t vl) {
return __riscv_vunzipe_v_u64m4_tu(vd, vs, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vunzipe_v_f16mf4_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 2 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vunzipe.mask.nxv1f16.nxv2f16.i64(<vscale x 1 x half> [[VD]], <vscale x 2 x half> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
-//
-vfloat16mf4_t test_vunzipe_v_f16mf4_tum(vbool64_t vm, vfloat16mf4_t vd,
- vfloat16mf2_t vs, size_t vl) {
- return __riscv_vunzipe_v_f16mf4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vunzipe_v_f16mf2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 4 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vunzipe.mask.nxv2f16.nxv4f16.i64(<vscale x 2 x half> [[VD]], <vscale x 4 x half> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
-//
-vfloat16mf2_t test_vunzipe_v_f16mf2_tum(vbool32_t vm, vfloat16mf2_t vd,
- vfloat16m1_t vs, size_t vl) {
- return __riscv_vunzipe_v_f16mf2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vunzipe_v_f16m1_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 8 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vunzipe.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[VD]], <vscale x 8 x half> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
-//
-vfloat16m1_t test_vunzipe_v_f16m1_tum(vbool16_t vm, vfloat16m1_t vd,
- vfloat16m2_t vs, size_t vl) {
- return __riscv_vunzipe_v_f16m1_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vunzipe_v_f16m2_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 16 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vunzipe.mask.nxv8f16.nxv16f16.i64(<vscale x 8 x half> [[VD]], <vscale x 16 x half> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
-//
-vfloat16m2_t test_vunzipe_v_f16m2_tum(vbool8_t vm, vfloat16m2_t vd,
- vfloat16m4_t vs, size_t vl) {
- return __riscv_vunzipe_v_f16m2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vunzipe_v_f16m4_tum
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 32 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vunzipe.mask.nxv16f16.nxv32f16.i64(<vscale x 16 x half> [[VD]], <vscale x 32 x half> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
-//
-vfloat16m4_t test_vunzipe_v_f16m4_tum(vbool4_t vm, vfloat16m4_t vd,
- vfloat16m8_t vs, size_t vl) {
- return __riscv_vunzipe_v_f16m4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vunzipe_v_f32mf2_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 2 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vunzipe.mask.nxv1f32.nxv2f32.i64(<vscale x 1 x float> [[VD]], <vscale x 2 x float> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
-//
-vfloat32mf2_t test_vunzipe_v_f32mf2_tum(vbool64_t vm, vfloat32mf2_t vd,
- vfloat32m1_t vs, size_t vl) {
- return __riscv_vunzipe_v_f32mf2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vunzipe_v_f32m1_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 4 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vunzipe.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[VD]], <vscale x 4 x float> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
-//
-vfloat32m1_t test_vunzipe_v_f32m1_tum(vbool32_t vm, vfloat32m1_t vd,
- vfloat32m2_t vs, size_t vl) {
- return __riscv_vunzipe_v_f32m1_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vunzipe_v_f32m2_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 8 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vunzipe.mask.nxv4f32.nxv8f32.i64(<vscale x 4 x float> [[VD]], <vscale x 8 x float> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
-//
-vfloat32m2_t test_vunzipe_v_f32m2_tum(vbool16_t vm, vfloat32m2_t vd,
- vfloat32m4_t vs, size_t vl) {
- return __riscv_vunzipe_v_f32m2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vunzipe_v_f32m4_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 16 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vunzipe.mask.nxv8f32.nxv16f32.i64(<vscale x 8 x float> [[VD]], <vscale x 16 x float> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
-//
-vfloat32m4_t test_vunzipe_v_f32m4_tum(vbool8_t vm, vfloat32m4_t vd,
- vfloat32m8_t vs, size_t vl) {
- return __riscv_vunzipe_v_f32m4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vunzipe_v_f64m1_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 2 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vunzipe.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[VD]], <vscale x 2 x double> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
-//
-vfloat64m1_t test_vunzipe_v_f64m1_tum(vbool64_t vm, vfloat64m1_t vd,
- vfloat64m2_t vs, size_t vl) {
- return __riscv_vunzipe_v_f64m1_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vunzipe_v_f64m2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 4 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vunzipe.mask.nxv2f64.nxv4f64.i64(<vscale x 2 x double> [[VD]], <vscale x 4 x double> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
-//
-vfloat64m2_t test_vunzipe_v_f64m2_tum(vbool32_t vm, vfloat64m2_t vd,
- vfloat64m4_t vs, size_t vl) {
- return __riscv_vunzipe_v_f64m2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vunzipe_v_f64m4_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 8 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vunzipe.mask.nxv4f64.nxv8f64.i64(<vscale x 4 x double> [[VD]], <vscale x 8 x double> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
-//
-vfloat64m4_t test_vunzipe_v_f64m4_tum(vbool16_t vm, vfloat64m4_t vd,
- vfloat64m8_t vs, size_t vl) {
- return __riscv_vunzipe_v_f64m4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vunzipe_v_i8mf8_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vunzipe.mask.nxv1i8.nxv2i8.i64(<vscale x 1 x i8> [[VD]], <vscale x 2 x i8> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
-//
-vint8mf8_t test_vunzipe_v_i8mf8_tum(vbool64_t vm, vint8mf8_t vd, vint8mf4_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i8mf8_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vunzipe_v_i8mf4_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vunzipe.mask.nxv2i8.nxv4i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 4 x i8> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
-//
-vint8mf4_t test_vunzipe_v_i8mf4_tum(vbool32_t vm, vint8mf4_t vd, vint8mf2_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i8mf4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vunzipe_v_i8mf2_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vunzipe.mask.nxv4i8.nxv8i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 8 x i8> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
-//
-vint8mf2_t test_vunzipe_v_i8mf2_tum(vbool16_t vm, vint8mf2_t vd, vint8m1_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i8mf2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vunzipe_v_i8m1_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vunzipe.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 16 x i8> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
-//
-vint8m1_t test_vunzipe_v_i8m1_tum(vbool8_t vm, vint8m1_t vd, vint8m2_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i8m1_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vunzipe_v_i8m2_tum
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vunzipe.mask.nxv16i8.nxv32i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 32 x i8> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-vint8m2_t test_vunzipe_v_i8m2_tum(vbool4_t vm, vint8m2_t vd, vint8m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i8m2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vunzipe_v_i8m4_tum
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vunzipe.mask.nxv32i8.nxv64i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 64 x i8> [[VS]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
-//
-vint8m4_t test_vunzipe_v_i8m4_tum(vbool2_t vm, vint8m4_t vd, vint8m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i8m4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vunzipe_v_i16mf4_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vunzipe.mask.nxv1i16.nxv2i16.i64(<vscale x 1 x i16> [[VD]], <vscale x 2 x i16> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
-//
-vint16mf4_t test_vunzipe_v_i16mf4_tum(vbool64_t vm, vint16mf4_t vd,
- vint16mf2_t vs, size_t vl) {
- return __riscv_vunzipe_v_i16mf4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vunzipe_v_i16mf2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vunzipe.mask.nxv2i16.nxv4i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 4 x i16> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
-//
-vint16mf2_t test_vunzipe_v_i16mf2_tum(vbool32_t vm, vint16mf2_t vd,
- vint16m1_t vs, size_t vl) {
- return __riscv_vunzipe_v_i16mf2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vunzipe_v_i16m1_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vunzipe.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 8 x i16> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
-//
-vint16m1_t test_vunzipe_v_i16m1_tum(vbool16_t vm, vint16m1_t vd, vint16m2_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i16m1_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vunzipe_v_i16m2_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vunzipe.mask.nxv8i16.nxv16i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 16 x i16> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-vint16m2_t test_vunzipe_v_i16m2_tum(vbool8_t vm, vint16m2_t vd, vint16m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i16m2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vunzipe_v_i16m4_tum
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vunzipe.mask.nxv16i16.nxv32i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 32 x i16> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
-//
-vint16m4_t test_vunzipe_v_i16m4_tum(vbool4_t vm, vint16m4_t vd, vint16m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i16m4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vunzipe_v_i32mf2_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vunzipe.mask.nxv1i32.nxv2i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 2 x i32> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vunzipe_v_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
- vint32m1_t vs, size_t vl) {
- return __riscv_vunzipe_v_i32mf2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vunzipe_v_i32m1_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vunzipe.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 4 x i32> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vunzipe_v_i32m1_tum(vbool32_t vm, vint32m1_t vd, vint32m2_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i32m1_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vunzipe_v_i32m2_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vunzipe.mask.nxv4i32.nxv8i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i32> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vunzipe_v_i32m2_tum(vbool16_t vm, vint32m2_t vd, vint32m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i32m2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vunzipe_v_i32m4_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vunzipe.mask.nxv8i32.nxv16i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 16 x i32> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vunzipe_v_i32m4_tum(vbool8_t vm, vint32m4_t vd, vint32m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i32m4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vunzipe_v_i64m1_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vunzipe.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> [[VD]], <vscale x 2 x i64> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
-//
-vint64m1_t test_vunzipe_v_i64m1_tum(vbool64_t vm, vint64m1_t vd, vint64m2_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i64m1_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vunzipe_v_i64m2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vunzipe.mask.nxv2i64.nxv4i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 4 x i64> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-vint64m2_t test_vunzipe_v_i64m2_tum(vbool32_t vm, vint64m2_t vd, vint64m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i64m2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vunzipe_v_i64m4_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vunzipe.mask.nxv4i64.nxv8i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 8 x i64> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
-//
-vint64m4_t test_vunzipe_v_i64m4_tum(vbool16_t vm, vint64m4_t vd, vint64m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i64m4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vunzipe_v_u8mf8_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vunzipe.mask.nxv1i8.nxv2i8.i64(<vscale x 1 x i8> [[VD]], <vscale x 2 x i8> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
-//
-vuint8mf8_t test_vunzipe_v_u8mf8_tum(vbool64_t vm, vuint8mf8_t vd,
- vuint8mf4_t vs, size_t vl) {
- return __riscv_vunzipe_v_u8mf8_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vunzipe_v_u8mf4_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vunzipe.mask.nxv2i8.nxv4i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 4 x i8> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
-//
-vuint8mf4_t test_vunzipe_v_u8mf4_tum(vbool32_t vm, vuint8mf4_t vd,
- vuint8mf2_t vs, size_t vl) {
- return __riscv_vunzipe_v_u8mf4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vunzipe_v_u8mf2_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vunzipe.mask.nxv4i8.nxv8i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 8 x i8> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
-//
-vuint8mf2_t test_vunzipe_v_u8mf2_tum(vbool16_t vm, vuint8mf2_t vd,
- vuint8m1_t vs, size_t vl) {
- return __riscv_vunzipe_v_u8mf2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vunzipe_v_u8m1_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vunzipe.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 16 x i8> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
-//
-vuint8m1_t test_vunzipe_v_u8m1_tum(vbool8_t vm, vuint8m1_t vd, vuint8m2_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_u8m1_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vunzipe_v_u8m2_tum
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vunzipe.mask.nxv16i8.nxv32i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 32 x i8> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-vuint8m2_t test_vunzipe_v_u8m2_tum(vbool4_t vm, vuint8m2_t vd, vuint8m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_u8m2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vunzipe_v_u8m4_tum
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vunzipe.mask.nxv32i8.nxv64i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 64 x i8> [[VS]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
-//
-vuint8m4_t test_vunzipe_v_u8m4_tum(vbool2_t vm, vuint8m4_t vd, vuint8m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_u8m4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vunzipe_v_u16mf4_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vunzipe.mask.nxv1i16.nxv2i16.i64(<vscale x 1 x i16> [[VD]], <vscale x 2 x i16> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
-//
-vuint16mf4_t test_vunzipe_v_u16mf4_tum(vbool64_t vm, vuint16mf4_t vd,
- vuint16mf2_t vs, size_t vl) {
- return __riscv_vunzipe_v_u16mf4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vunzipe_v_u16mf2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vunzipe.mask.nxv2i16.nxv4i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 4 x i16> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
-//
-vuint16mf2_t test_vunzipe_v_u16mf2_tum(vbool32_t vm, vuint16mf2_t vd,
- vuint16m1_t vs, size_t vl) {
- return __riscv_vunzipe_v_u16mf2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vunzipe_v_u16m1_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vunzipe.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 8 x i16> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
-//
-vuint16m1_t test_vunzipe_v_u16m1_tum(vbool16_t vm, vuint16m1_t vd,
- vuint16m2_t vs, size_t vl) {
- return __riscv_vunzipe_v_u16m1_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vunzipe_v_u16m2_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vunzipe.mask.nxv8i16.nxv16i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 16 x i16> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-vuint16m2_t test_vunzipe_v_u16m2_tum(vbool8_t vm, vuint16m2_t vd,
- vuint16m4_t vs, size_t vl) {
- return __riscv_vunzipe_v_u16m2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vunzipe_v_u16m4_tum
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vunzipe.mask.nxv16i16.nxv32i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 32 x i16> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
-//
-vuint16m4_t test_vunzipe_v_u16m4_tum(vbool4_t vm, vuint16m4_t vd,
- vuint16m8_t vs, size_t vl) {
- return __riscv_vunzipe_v_u16m4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vunzipe_v_u32mf2_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vunzipe.mask.nxv1i32.nxv2i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 2 x i32> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vuint32mf2_t test_vunzipe_v_u32mf2_tum(vbool64_t vm, vuint32mf2_t vd,
- vuint32m1_t vs, size_t vl) {
- return __riscv_vunzipe_v_u32mf2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vunzipe_v_u32m1_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vunzipe.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 4 x i32> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vuint32m1_t test_vunzipe_v_u32m1_tum(vbool32_t vm, vuint32m1_t vd,
- vuint32m2_t vs, size_t vl) {
- return __riscv_vunzipe_v_u32m1_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vunzipe_v_u32m2_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vunzipe.mask.nxv4i32.nxv8i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i32> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vuint32m2_t test_vunzipe_v_u32m2_tum(vbool16_t vm, vuint32m2_t vd,
- vuint32m4_t vs, size_t vl) {
- return __riscv_vunzipe_v_u32m2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vunzipe_v_u32m4_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vunzipe.mask.nxv8i32.nxv16i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 16 x i32> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vuint32m4_t test_vunzipe_v_u32m4_tum(vbool8_t vm, vuint32m4_t vd,
- vuint32m8_t vs, size_t vl) {
- return __riscv_vunzipe_v_u32m4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vunzipe_v_u64m1_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vunzipe.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> [[VD]], <vscale x 2 x i64> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
-//
-vuint64m1_t test_vunzipe_v_u64m1_tum(vbool64_t vm, vuint64m1_t vd,
- vuint64m2_t vs, size_t vl) {
- return __riscv_vunzipe_v_u64m1_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vunzipe_v_u64m2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vunzipe.mask.nxv2i64.nxv4i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 4 x i64> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-vuint64m2_t test_vunzipe_v_u64m2_tum(vbool32_t vm, vuint64m2_t vd,
- vuint64m4_t vs, size_t vl) {
- return __riscv_vunzipe_v_u64m2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vunzipe_v_u64m4_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vunzipe.mask.nxv4i64.nxv8i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 8 x i64> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
-//
-vuint64m4_t test_vunzipe_v_u64m4_tum(vbool16_t vm, vuint64m4_t vd,
- vuint64m8_t vs, size_t vl) {
- return __riscv_vunzipe_v_u64m4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vunzipe_v_f16mf4_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 2 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vunzipe.mask.nxv1f16.nxv2f16.i64(<vscale x 1 x half> [[VD]], <vscale x 2 x half> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
-//
-vfloat16mf4_t test_vunzipe_v_f16mf4_tumu(vbool64_t vm, vfloat16mf4_t vd,
- vfloat16mf2_t vs, size_t vl) {
- return __riscv_vunzipe_v_f16mf4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vunzipe_v_f16mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 4 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vunzipe.mask.nxv2f16.nxv4f16.i64(<vscale x 2 x half> [[VD]], <vscale x 4 x half> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
-//
-vfloat16mf2_t test_vunzipe_v_f16mf2_tumu(vbool32_t vm, vfloat16mf2_t vd,
- vfloat16m1_t vs, size_t vl) {
- return __riscv_vunzipe_v_f16mf2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vunzipe_v_f16m1_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 8 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vunzipe.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[VD]], <vscale x 8 x half> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
-//
-vfloat16m1_t test_vunzipe_v_f16m1_tumu(vbool16_t vm, vfloat16m1_t vd,
- vfloat16m2_t vs, size_t vl) {
- return __riscv_vunzipe_v_f16m1_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vunzipe_v_f16m2_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 16 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vunzipe.mask.nxv8f16.nxv16f16.i64(<vscale x 8 x half> [[VD]], <vscale x 16 x half> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
-//
-vfloat16m2_t test_vunzipe_v_f16m2_tumu(vbool8_t vm, vfloat16m2_t vd,
- vfloat16m4_t vs, size_t vl) {
- return __riscv_vunzipe_v_f16m2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vunzipe_v_f16m4_tumu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 32 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vunzipe.mask.nxv16f16.nxv32f16.i64(<vscale x 16 x half> [[VD]], <vscale x 32 x half> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
-//
-vfloat16m4_t test_vunzipe_v_f16m4_tumu(vbool4_t vm, vfloat16m4_t vd,
- vfloat16m8_t vs, size_t vl) {
- return __riscv_vunzipe_v_f16m4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vunzipe_v_f32mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 2 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vunzipe.mask.nxv1f32.nxv2f32.i64(<vscale x 1 x float> [[VD]], <vscale x 2 x float> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
-//
-vfloat32mf2_t test_vunzipe_v_f32mf2_tumu(vbool64_t vm, vfloat32mf2_t vd,
- vfloat32m1_t vs, size_t vl) {
- return __riscv_vunzipe_v_f32mf2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vunzipe_v_f32m1_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 4 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vunzipe.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[VD]], <vscale x 4 x float> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
-//
-vfloat32m1_t test_vunzipe_v_f32m1_tumu(vbool32_t vm, vfloat32m1_t vd,
- vfloat32m2_t vs, size_t vl) {
- return __riscv_vunzipe_v_f32m1_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vunzipe_v_f32m2_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 8 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vunzipe.mask.nxv4f32.nxv8f32.i64(<vscale x 4 x float> [[VD]], <vscale x 8 x float> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
-//
-vfloat32m2_t test_vunzipe_v_f32m2_tumu(vbool16_t vm, vfloat32m2_t vd,
- vfloat32m4_t vs, size_t vl) {
- return __riscv_vunzipe_v_f32m2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vunzipe_v_f32m4_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 16 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vunzipe.mask.nxv8f32.nxv16f32.i64(<vscale x 8 x float> [[VD]], <vscale x 16 x float> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
-//
-vfloat32m4_t test_vunzipe_v_f32m4_tumu(vbool8_t vm, vfloat32m4_t vd,
- vfloat32m8_t vs, size_t vl) {
- return __riscv_vunzipe_v_f32m4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vunzipe_v_f64m1_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 2 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vunzipe.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[VD]], <vscale x 2 x double> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
-//
-vfloat64m1_t test_vunzipe_v_f64m1_tumu(vbool64_t vm, vfloat64m1_t vd,
- vfloat64m2_t vs, size_t vl) {
- return __riscv_vunzipe_v_f64m1_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vunzipe_v_f64m2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 4 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vunzipe.mask.nxv2f64.nxv4f64.i64(<vscale x 2 x double> [[VD]], <vscale x 4 x double> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
-//
-vfloat64m2_t test_vunzipe_v_f64m2_tumu(vbool32_t vm, vfloat64m2_t vd,
- vfloat64m4_t vs, size_t vl) {
- return __riscv_vunzipe_v_f64m2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vunzipe_v_f64m4_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 8 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vunzipe.mask.nxv4f64.nxv8f64.i64(<vscale x 4 x double> [[VD]], <vscale x 8 x double> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
-//
-vfloat64m4_t test_vunzipe_v_f64m4_tumu(vbool16_t vm, vfloat64m4_t vd,
- vfloat64m8_t vs, size_t vl) {
- return __riscv_vunzipe_v_f64m4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vunzipe_v_i8mf8_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vunzipe.mask.nxv1i8.nxv2i8.i64(<vscale x 1 x i8> [[VD]], <vscale x 2 x i8> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
-//
-vint8mf8_t test_vunzipe_v_i8mf8_tumu(vbool64_t vm, vint8mf8_t vd, vint8mf4_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i8mf8_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vunzipe_v_i8mf4_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vunzipe.mask.nxv2i8.nxv4i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 4 x i8> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
-//
-vint8mf4_t test_vunzipe_v_i8mf4_tumu(vbool32_t vm, vint8mf4_t vd, vint8mf2_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i8mf4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vunzipe_v_i8mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vunzipe.mask.nxv4i8.nxv8i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 8 x i8> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
-//
-vint8mf2_t test_vunzipe_v_i8mf2_tumu(vbool16_t vm, vint8mf2_t vd, vint8m1_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i8mf2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vunzipe_v_i8m1_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vunzipe.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 16 x i8> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
-//
-vint8m1_t test_vunzipe_v_i8m1_tumu(vbool8_t vm, vint8m1_t vd, vint8m2_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i8m1_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vunzipe_v_i8m2_tumu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vunzipe.mask.nxv16i8.nxv32i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 32 x i8> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-vint8m2_t test_vunzipe_v_i8m2_tumu(vbool4_t vm, vint8m2_t vd, vint8m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i8m2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vunzipe_v_i8m4_tumu
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vunzipe.mask.nxv32i8.nxv64i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 64 x i8> [[VS]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
-//
-vint8m4_t test_vunzipe_v_i8m4_tumu(vbool2_t vm, vint8m4_t vd, vint8m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i8m4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vunzipe_v_i16mf4_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vunzipe.mask.nxv1i16.nxv2i16.i64(<vscale x 1 x i16> [[VD]], <vscale x 2 x i16> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
-//
-vint16mf4_t test_vunzipe_v_i16mf4_tumu(vbool64_t vm, vint16mf4_t vd,
- vint16mf2_t vs, size_t vl) {
- return __riscv_vunzipe_v_i16mf4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vunzipe_v_i16mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vunzipe.mask.nxv2i16.nxv4i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 4 x i16> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
-//
-vint16mf2_t test_vunzipe_v_i16mf2_tumu(vbool32_t vm, vint16mf2_t vd,
- vint16m1_t vs, size_t vl) {
- return __riscv_vunzipe_v_i16mf2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vunzipe_v_i16m1_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vunzipe.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 8 x i16> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
-//
-vint16m1_t test_vunzipe_v_i16m1_tumu(vbool16_t vm, vint16m1_t vd, vint16m2_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i16m1_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vunzipe_v_i16m2_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vunzipe.mask.nxv8i16.nxv16i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 16 x i16> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-vint16m2_t test_vunzipe_v_i16m2_tumu(vbool8_t vm, vint16m2_t vd, vint16m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i16m2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vunzipe_v_i16m4_tumu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vunzipe.mask.nxv16i16.nxv32i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 32 x i16> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
-//
-vint16m4_t test_vunzipe_v_i16m4_tumu(vbool4_t vm, vint16m4_t vd, vint16m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i16m4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vunzipe_v_i32mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vunzipe.mask.nxv1i32.nxv2i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 2 x i32> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vunzipe_v_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
- vint32m1_t vs, size_t vl) {
- return __riscv_vunzipe_v_i32mf2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vunzipe_v_i32m1_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vunzipe.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 4 x i32> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vunzipe_v_i32m1_tumu(vbool32_t vm, vint32m1_t vd, vint32m2_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i32m1_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vunzipe_v_i32m2_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vunzipe.mask.nxv4i32.nxv8i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i32> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vunzipe_v_i32m2_tumu(vbool16_t vm, vint32m2_t vd, vint32m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i32m2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vunzipe_v_i32m4_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vunzipe.mask.nxv8i32.nxv16i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 16 x i32> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vunzipe_v_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vint32m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i32m4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vunzipe_v_i64m1_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vunzipe.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> [[VD]], <vscale x 2 x i64> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
-//
-vint64m1_t test_vunzipe_v_i64m1_tumu(vbool64_t vm, vint64m1_t vd, vint64m2_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i64m1_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vunzipe_v_i64m2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vunzipe.mask.nxv2i64.nxv4i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 4 x i64> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-vint64m2_t test_vunzipe_v_i64m2_tumu(vbool32_t vm, vint64m2_t vd, vint64m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i64m2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vunzipe_v_i64m4_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vunzipe.mask.nxv4i64.nxv8i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 8 x i64> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
-//
-vint64m4_t test_vunzipe_v_i64m4_tumu(vbool16_t vm, vint64m4_t vd, vint64m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i64m4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vunzipe_v_u8mf8_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vunzipe.mask.nxv1i8.nxv2i8.i64(<vscale x 1 x i8> [[VD]], <vscale x 2 x i8> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
-//
-vuint8mf8_t test_vunzipe_v_u8mf8_tumu(vbool64_t vm, vuint8mf8_t vd,
- vuint8mf4_t vs, size_t vl) {
- return __riscv_vunzipe_v_u8mf8_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vunzipe_v_u8mf4_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vunzipe.mask.nxv2i8.nxv4i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 4 x i8> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
-//
-vuint8mf4_t test_vunzipe_v_u8mf4_tumu(vbool32_t vm, vuint8mf4_t vd,
- vuint8mf2_t vs, size_t vl) {
- return __riscv_vunzipe_v_u8mf4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vunzipe_v_u8mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vunzipe.mask.nxv4i8.nxv8i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 8 x i8> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
-//
-vuint8mf2_t test_vunzipe_v_u8mf2_tumu(vbool16_t vm, vuint8mf2_t vd,
- vuint8m1_t vs, size_t vl) {
- return __riscv_vunzipe_v_u8mf2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vunzipe_v_u8m1_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vunzipe.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 16 x i8> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
-//
-vuint8m1_t test_vunzipe_v_u8m1_tumu(vbool8_t vm, vuint8m1_t vd, vuint8m2_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_u8m1_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vunzipe_v_u8m2_tumu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vunzipe.mask.nxv16i8.nxv32i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 32 x i8> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-vuint8m2_t test_vunzipe_v_u8m2_tumu(vbool4_t vm, vuint8m2_t vd, vuint8m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_u8m2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vunzipe_v_u8m4_tumu
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vunzipe.mask.nxv32i8.nxv64i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 64 x i8> [[VS]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
-//
-vuint8m4_t test_vunzipe_v_u8m4_tumu(vbool2_t vm, vuint8m4_t vd, vuint8m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_u8m4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vunzipe_v_u16mf4_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vunzipe.mask.nxv1i16.nxv2i16.i64(<vscale x 1 x i16> [[VD]], <vscale x 2 x i16> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
-//
-vuint16mf4_t test_vunzipe_v_u16mf4_tumu(vbool64_t vm, vuint16mf4_t vd,
- vuint16mf2_t vs, size_t vl) {
- return __riscv_vunzipe_v_u16mf4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vunzipe_v_u16mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vunzipe.mask.nxv2i16.nxv4i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 4 x i16> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
-//
-vuint16mf2_t test_vunzipe_v_u16mf2_tumu(vbool32_t vm, vuint16mf2_t vd,
- vuint16m1_t vs, size_t vl) {
- return __riscv_vunzipe_v_u16mf2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vunzipe_v_u16m1_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vunzipe.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 8 x i16> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
-//
-vuint16m1_t test_vunzipe_v_u16m1_tumu(vbool16_t vm, vuint16m1_t vd,
- vuint16m2_t vs, size_t vl) {
- return __riscv_vunzipe_v_u16m1_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vunzipe_v_u16m2_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vunzipe.mask.nxv8i16.nxv16i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 16 x i16> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-vuint16m2_t test_vunzipe_v_u16m2_tumu(vbool8_t vm, vuint16m2_t vd,
- vuint16m4_t vs, size_t vl) {
- return __riscv_vunzipe_v_u16m2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vunzipe_v_u16m4_tumu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vunzipe.mask.nxv16i16.nxv32i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 32 x i16> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
-//
-vuint16m4_t test_vunzipe_v_u16m4_tumu(vbool4_t vm, vuint16m4_t vd,
- vuint16m8_t vs, size_t vl) {
- return __riscv_vunzipe_v_u16m4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vunzipe_v_u32mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vunzipe.mask.nxv1i32.nxv2i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 2 x i32> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vuint32mf2_t test_vunzipe_v_u32mf2_tumu(vbool64_t vm, vuint32mf2_t vd,
- vuint32m1_t vs, size_t vl) {
- return __riscv_vunzipe_v_u32mf2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vunzipe_v_u32m1_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vunzipe.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 4 x i32> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vuint32m1_t test_vunzipe_v_u32m1_tumu(vbool32_t vm, vuint32m1_t vd,
- vuint32m2_t vs, size_t vl) {
- return __riscv_vunzipe_v_u32m1_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vunzipe_v_u32m2_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vunzipe.mask.nxv4i32.nxv8i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i32> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vuint32m2_t test_vunzipe_v_u32m2_tumu(vbool16_t vm, vuint32m2_t vd,
- vuint32m4_t vs, size_t vl) {
- return __riscv_vunzipe_v_u32m2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vunzipe_v_u32m4_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vunzipe.mask.nxv8i32.nxv16i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 16 x i32> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vuint32m4_t test_vunzipe_v_u32m4_tumu(vbool8_t vm, vuint32m4_t vd,
- vuint32m8_t vs, size_t vl) {
- return __riscv_vunzipe_v_u32m4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vunzipe_v_u64m1_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vunzipe.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> [[VD]], <vscale x 2 x i64> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
-//
-vuint64m1_t test_vunzipe_v_u64m1_tumu(vbool64_t vm, vuint64m1_t vd,
- vuint64m2_t vs, size_t vl) {
- return __riscv_vunzipe_v_u64m1_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vunzipe_v_u64m2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vunzipe.mask.nxv2i64.nxv4i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 4 x i64> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-vuint64m2_t test_vunzipe_v_u64m2_tumu(vbool32_t vm, vuint64m2_t vd,
- vuint64m4_t vs, size_t vl) {
- return __riscv_vunzipe_v_u64m2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vunzipe_v_u64m4_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vunzipe.mask.nxv4i64.nxv8i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 8 x i64> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
-//
-vuint64m4_t test_vunzipe_v_u64m4_tumu(vbool16_t vm, vuint64m4_t vd,
- vuint64m8_t vs, size_t vl) {
- return __riscv_vunzipe_v_u64m4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vunzipe_v_f16mf4_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 2 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vunzipe.mask.nxv1f16.nxv2f16.i64(<vscale x 1 x half> [[VD]], <vscale x 2 x half> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
-//
-vfloat16mf4_t test_vunzipe_v_f16mf4_mu(vbool64_t vm, vfloat16mf4_t vd,
- vfloat16mf2_t vs, size_t vl) {
- return __riscv_vunzipe_v_f16mf4_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vunzipe_v_f16mf2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 4 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vunzipe.mask.nxv2f16.nxv4f16.i64(<vscale x 2 x half> [[VD]], <vscale x 4 x half> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
-//
-vfloat16mf2_t test_vunzipe_v_f16mf2_mu(vbool32_t vm, vfloat16mf2_t vd,
- vfloat16m1_t vs, size_t vl) {
- return __riscv_vunzipe_v_f16mf2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vunzipe_v_f16m1_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 8 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vunzipe.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[VD]], <vscale x 8 x half> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
-//
-vfloat16m1_t test_vunzipe_v_f16m1_mu(vbool16_t vm, vfloat16m1_t vd,
- vfloat16m2_t vs, size_t vl) {
- return __riscv_vunzipe_v_f16m1_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vunzipe_v_f16m2_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 16 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vunzipe.mask.nxv8f16.nxv16f16.i64(<vscale x 8 x half> [[VD]], <vscale x 16 x half> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
-//
-vfloat16m2_t test_vunzipe_v_f16m2_mu(vbool8_t vm, vfloat16m2_t vd,
- vfloat16m4_t vs, size_t vl) {
- return __riscv_vunzipe_v_f16m2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vunzipe_v_f16m4_mu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 32 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vunzipe.mask.nxv16f16.nxv32f16.i64(<vscale x 16 x half> [[VD]], <vscale x 32 x half> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
-//
-vfloat16m4_t test_vunzipe_v_f16m4_mu(vbool4_t vm, vfloat16m4_t vd,
- vfloat16m8_t vs, size_t vl) {
- return __riscv_vunzipe_v_f16m4_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vunzipe_v_f32mf2_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 2 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vunzipe.mask.nxv1f32.nxv2f32.i64(<vscale x 1 x float> [[VD]], <vscale x 2 x float> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
-//
-vfloat32mf2_t test_vunzipe_v_f32mf2_mu(vbool64_t vm, vfloat32mf2_t vd,
- vfloat32m1_t vs, size_t vl) {
- return __riscv_vunzipe_v_f32mf2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vunzipe_v_f32m1_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 4 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vunzipe.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[VD]], <vscale x 4 x float> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
-//
-vfloat32m1_t test_vunzipe_v_f32m1_mu(vbool32_t vm, vfloat32m1_t vd,
- vfloat32m2_t vs, size_t vl) {
- return __riscv_vunzipe_v_f32m1_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vunzipe_v_f32m2_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 8 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vunzipe.mask.nxv4f32.nxv8f32.i64(<vscale x 4 x float> [[VD]], <vscale x 8 x float> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
-//
-vfloat32m2_t test_vunzipe_v_f32m2_mu(vbool16_t vm, vfloat32m2_t vd,
- vfloat32m4_t vs, size_t vl) {
- return __riscv_vunzipe_v_f32m2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vunzipe_v_f32m4_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 16 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vunzipe.mask.nxv8f32.nxv16f32.i64(<vscale x 8 x float> [[VD]], <vscale x 16 x float> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
-//
-vfloat32m4_t test_vunzipe_v_f32m4_mu(vbool8_t vm, vfloat32m4_t vd,
- vfloat32m8_t vs, size_t vl) {
- return __riscv_vunzipe_v_f32m4_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vunzipe_v_f64m1_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 2 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vunzipe.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[VD]], <vscale x 2 x double> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
-//
-vfloat64m1_t test_vunzipe_v_f64m1_mu(vbool64_t vm, vfloat64m1_t vd,
- vfloat64m2_t vs, size_t vl) {
- return __riscv_vunzipe_v_f64m1_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vunzipe_v_f64m2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 4 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vunzipe.mask.nxv2f64.nxv4f64.i64(<vscale x 2 x double> [[VD]], <vscale x 4 x double> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
-//
-vfloat64m2_t test_vunzipe_v_f64m2_mu(vbool32_t vm, vfloat64m2_t vd,
- vfloat64m4_t vs, size_t vl) {
- return __riscv_vunzipe_v_f64m2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vunzipe_v_f64m4_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 8 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vunzipe.mask.nxv4f64.nxv8f64.i64(<vscale x 4 x double> [[VD]], <vscale x 8 x double> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
-//
-vfloat64m4_t test_vunzipe_v_f64m4_mu(vbool16_t vm, vfloat64m4_t vd,
- vfloat64m8_t vs, size_t vl) {
- return __riscv_vunzipe_v_f64m4_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vunzipe_v_i8mf8_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vunzipe.mask.nxv1i8.nxv2i8.i64(<vscale x 1 x i8> [[VD]], <vscale x 2 x i8> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
-//
-vint8mf8_t test_vunzipe_v_i8mf8_mu(vbool64_t vm, vint8mf8_t vd, vint8mf4_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i8mf8_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vunzipe_v_i8mf4_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vunzipe.mask.nxv2i8.nxv4i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 4 x i8> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
-//
-vint8mf4_t test_vunzipe_v_i8mf4_mu(vbool32_t vm, vint8mf4_t vd, vint8mf2_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i8mf4_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vunzipe_v_i8mf2_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vunzipe.mask.nxv4i8.nxv8i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 8 x i8> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
-//
-vint8mf2_t test_vunzipe_v_i8mf2_mu(vbool16_t vm, vint8mf2_t vd, vint8m1_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i8mf2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vunzipe_v_i8m1_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vunzipe.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 16 x i8> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
-//
-vint8m1_t test_vunzipe_v_i8m1_mu(vbool8_t vm, vint8m1_t vd, vint8m2_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i8m1_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vunzipe_v_i8m2_mu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vunzipe.mask.nxv16i8.nxv32i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 32 x i8> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-vint8m2_t test_vunzipe_v_i8m2_mu(vbool4_t vm, vint8m2_t vd, vint8m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i8m2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vunzipe_v_i8m4_mu
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vunzipe.mask.nxv32i8.nxv64i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 64 x i8> [[VS]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
-//
-vint8m4_t test_vunzipe_v_i8m4_mu(vbool2_t vm, vint8m4_t vd, vint8m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i8m4_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vunzipe_v_i16mf4_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vunzipe.mask.nxv1i16.nxv2i16.i64(<vscale x 1 x i16> [[VD]], <vscale x 2 x i16> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
-//
-vint16mf4_t test_vunzipe_v_i16mf4_mu(vbool64_t vm, vint16mf4_t vd,
- vint16mf2_t vs, size_t vl) {
- return __riscv_vunzipe_v_i16mf4_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vunzipe_v_i16mf2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vunzipe.mask.nxv2i16.nxv4i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 4 x i16> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
-//
-vint16mf2_t test_vunzipe_v_i16mf2_mu(vbool32_t vm, vint16mf2_t vd,
- vint16m1_t vs, size_t vl) {
- return __riscv_vunzipe_v_i16mf2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vunzipe_v_i16m1_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vunzipe.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 8 x i16> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
-//
-vint16m1_t test_vunzipe_v_i16m1_mu(vbool16_t vm, vint16m1_t vd, vint16m2_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i16m1_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vunzipe_v_i16m2_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vunzipe.mask.nxv8i16.nxv16i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 16 x i16> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-vint16m2_t test_vunzipe_v_i16m2_mu(vbool8_t vm, vint16m2_t vd, vint16m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i16m2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vunzipe_v_i16m4_mu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vunzipe.mask.nxv16i16.nxv32i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 32 x i16> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
-//
-vint16m4_t test_vunzipe_v_i16m4_mu(vbool4_t vm, vint16m4_t vd, vint16m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i16m4_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vunzipe_v_i32mf2_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vunzipe.mask.nxv1i32.nxv2i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 2 x i32> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vunzipe_v_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
- vint32m1_t vs, size_t vl) {
- return __riscv_vunzipe_v_i32mf2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vunzipe_v_i32m1_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vunzipe.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 4 x i32> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vunzipe_v_i32m1_mu(vbool32_t vm, vint32m1_t vd, vint32m2_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i32m1_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vunzipe_v_i32m2_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vunzipe.mask.nxv4i32.nxv8i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i32> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vunzipe_v_i32m2_mu(vbool16_t vm, vint32m2_t vd, vint32m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i32m2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vunzipe_v_i32m4_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vunzipe.mask.nxv8i32.nxv16i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 16 x i32> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vunzipe_v_i32m4_mu(vbool8_t vm, vint32m4_t vd, vint32m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i32m4_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vunzipe_v_i64m1_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vunzipe.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> [[VD]], <vscale x 2 x i64> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
-//
-vint64m1_t test_vunzipe_v_i64m1_mu(vbool64_t vm, vint64m1_t vd, vint64m2_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i64m1_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vunzipe_v_i64m2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vunzipe.mask.nxv2i64.nxv4i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 4 x i64> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-vint64m2_t test_vunzipe_v_i64m2_mu(vbool32_t vm, vint64m2_t vd, vint64m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i64m2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vunzipe_v_i64m4_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vunzipe.mask.nxv4i64.nxv8i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 8 x i64> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
-//
-vint64m4_t test_vunzipe_v_i64m4_mu(vbool16_t vm, vint64m4_t vd, vint64m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_i64m4_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vunzipe_v_u8mf8_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vunzipe.mask.nxv1i8.nxv2i8.i64(<vscale x 1 x i8> [[VD]], <vscale x 2 x i8> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
-//
-vuint8mf8_t test_vunzipe_v_u8mf8_mu(vbool64_t vm, vuint8mf8_t vd,
- vuint8mf4_t vs, size_t vl) {
- return __riscv_vunzipe_v_u8mf8_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vunzipe_v_u8mf4_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vunzipe.mask.nxv2i8.nxv4i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 4 x i8> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
-//
-vuint8mf4_t test_vunzipe_v_u8mf4_mu(vbool32_t vm, vuint8mf4_t vd,
- vuint8mf2_t vs, size_t vl) {
- return __riscv_vunzipe_v_u8mf4_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vunzipe_v_u8mf2_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vunzipe.mask.nxv4i8.nxv8i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 8 x i8> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
-//
-vuint8mf2_t test_vunzipe_v_u8mf2_mu(vbool16_t vm, vuint8mf2_t vd, vuint8m1_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_u8mf2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vunzipe_v_u8m1_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vunzipe.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 16 x i8> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
-//
-vuint8m1_t test_vunzipe_v_u8m1_mu(vbool8_t vm, vuint8m1_t vd, vuint8m2_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_u8m1_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vunzipe_v_u8m2_mu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vunzipe.mask.nxv16i8.nxv32i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 32 x i8> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-vuint8m2_t test_vunzipe_v_u8m2_mu(vbool4_t vm, vuint8m2_t vd, vuint8m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_u8m2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vunzipe_v_u8m4_mu
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vunzipe.mask.nxv32i8.nxv64i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 64 x i8> [[VS]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
-//
-vuint8m4_t test_vunzipe_v_u8m4_mu(vbool2_t vm, vuint8m4_t vd, vuint8m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_u8m4_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vunzipe_v_u16mf4_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vunzipe.mask.nxv1i16.nxv2i16.i64(<vscale x 1 x i16> [[VD]], <vscale x 2 x i16> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
-//
-vuint16mf4_t test_vunzipe_v_u16mf4_mu(vbool64_t vm, vuint16mf4_t vd,
- vuint16mf2_t vs, size_t vl) {
- return __riscv_vunzipe_v_u16mf4_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vunzipe_v_u16mf2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vunzipe.mask.nxv2i16.nxv4i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 4 x i16> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
-//
-vuint16mf2_t test_vunzipe_v_u16mf2_mu(vbool32_t vm, vuint16mf2_t vd,
- vuint16m1_t vs, size_t vl) {
- return __riscv_vunzipe_v_u16mf2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vunzipe_v_u16m1_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vunzipe.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 8 x i16> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
-//
-vuint16m1_t test_vunzipe_v_u16m1_mu(vbool16_t vm, vuint16m1_t vd,
- vuint16m2_t vs, size_t vl) {
- return __riscv_vunzipe_v_u16m1_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vunzipe_v_u16m2_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vunzipe.mask.nxv8i16.nxv16i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 16 x i16> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-vuint16m2_t test_vunzipe_v_u16m2_mu(vbool8_t vm, vuint16m2_t vd, vuint16m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_u16m2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vunzipe_v_u16m4_mu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vunzipe.mask.nxv16i16.nxv32i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 32 x i16> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
-//
-vuint16m4_t test_vunzipe_v_u16m4_mu(vbool4_t vm, vuint16m4_t vd, vuint16m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_u16m4_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vunzipe_v_u32mf2_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vunzipe.mask.nxv1i32.nxv2i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 2 x i32> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vuint32mf2_t test_vunzipe_v_u32mf2_mu(vbool64_t vm, vuint32mf2_t vd,
- vuint32m1_t vs, size_t vl) {
- return __riscv_vunzipe_v_u32mf2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vunzipe_v_u32m1_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vunzipe.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 4 x i32> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vuint32m1_t test_vunzipe_v_u32m1_mu(vbool32_t vm, vuint32m1_t vd,
- vuint32m2_t vs, size_t vl) {
- return __riscv_vunzipe_v_u32m1_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vunzipe_v_u32m2_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vunzipe.mask.nxv4i32.nxv8i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i32> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vuint32m2_t test_vunzipe_v_u32m2_mu(vbool16_t vm, vuint32m2_t vd,
- vuint32m4_t vs, size_t vl) {
- return __riscv_vunzipe_v_u32m2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vunzipe_v_u32m4_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vunzipe.mask.nxv8i32.nxv16i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 16 x i32> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vuint32m4_t test_vunzipe_v_u32m4_mu(vbool8_t vm, vuint32m4_t vd, vuint32m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_u32m4_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vunzipe_v_u64m1_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vunzipe.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> [[VD]], <vscale x 2 x i64> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
-//
-vuint64m1_t test_vunzipe_v_u64m1_mu(vbool64_t vm, vuint64m1_t vd,
- vuint64m2_t vs, size_t vl) {
- return __riscv_vunzipe_v_u64m1_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vunzipe_v_u64m2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vunzipe.mask.nxv2i64.nxv4i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 4 x i64> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-vuint64m2_t test_vunzipe_v_u64m2_mu(vbool32_t vm, vuint64m2_t vd,
- vuint64m4_t vs, size_t vl) {
- return __riscv_vunzipe_v_u64m2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vunzipe_v_u64m4_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vunzipe.mask.nxv4i64.nxv8i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 8 x i64> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
-//
-vuint64m4_t test_vunzipe_v_u64m4_mu(vbool16_t vm, vuint64m4_t vd,
- vuint64m8_t vs, size_t vl) {
- return __riscv_vunzipe_v_u64m4_mu(vm, vd, vs, vl);
-}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c
index da073766c47d4..0de98b6d332fb 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c
@@ -505,1586 +505,3 @@ vuint64m4_t test_vunzipo_v_u64m4_tu(vuint64m4_t vd, vuint64m8_t vs, size_t vl) {
return __riscv_vunzipo_v_u64m4_tu(vd, vs, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vunzipo_v_f16mf4_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 2 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vunzipo.mask.nxv1f16.nxv2f16.i64(<vscale x 1 x half> [[VD]], <vscale x 2 x half> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
-//
-vfloat16mf4_t test_vunzipo_v_f16mf4_tum(vbool64_t vm, vfloat16mf4_t vd,
- vfloat16mf2_t vs, size_t vl) {
- return __riscv_vunzipo_v_f16mf4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vunzipo_v_f16mf2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 4 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vunzipo.mask.nxv2f16.nxv4f16.i64(<vscale x 2 x half> [[VD]], <vscale x 4 x half> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
-//
-vfloat16mf2_t test_vunzipo_v_f16mf2_tum(vbool32_t vm, vfloat16mf2_t vd,
- vfloat16m1_t vs, size_t vl) {
- return __riscv_vunzipo_v_f16mf2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vunzipo_v_f16m1_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 8 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vunzipo.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[VD]], <vscale x 8 x half> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
-//
-vfloat16m1_t test_vunzipo_v_f16m1_tum(vbool16_t vm, vfloat16m1_t vd,
- vfloat16m2_t vs, size_t vl) {
- return __riscv_vunzipo_v_f16m1_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vunzipo_v_f16m2_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 16 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vunzipo.mask.nxv8f16.nxv16f16.i64(<vscale x 8 x half> [[VD]], <vscale x 16 x half> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
-//
-vfloat16m2_t test_vunzipo_v_f16m2_tum(vbool8_t vm, vfloat16m2_t vd,
- vfloat16m4_t vs, size_t vl) {
- return __riscv_vunzipo_v_f16m2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vunzipo_v_f16m4_tum
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 32 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vunzipo.mask.nxv16f16.nxv32f16.i64(<vscale x 16 x half> [[VD]], <vscale x 32 x half> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
-//
-vfloat16m4_t test_vunzipo_v_f16m4_tum(vbool4_t vm, vfloat16m4_t vd,
- vfloat16m8_t vs, size_t vl) {
- return __riscv_vunzipo_v_f16m4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vunzipo_v_f32mf2_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 2 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vunzipo.mask.nxv1f32.nxv2f32.i64(<vscale x 1 x float> [[VD]], <vscale x 2 x float> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
-//
-vfloat32mf2_t test_vunzipo_v_f32mf2_tum(vbool64_t vm, vfloat32mf2_t vd,
- vfloat32m1_t vs, size_t vl) {
- return __riscv_vunzipo_v_f32mf2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vunzipo_v_f32m1_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 4 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vunzipo.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[VD]], <vscale x 4 x float> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
-//
-vfloat32m1_t test_vunzipo_v_f32m1_tum(vbool32_t vm, vfloat32m1_t vd,
- vfloat32m2_t vs, size_t vl) {
- return __riscv_vunzipo_v_f32m1_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vunzipo_v_f32m2_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 8 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vunzipo.mask.nxv4f32.nxv8f32.i64(<vscale x 4 x float> [[VD]], <vscale x 8 x float> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
-//
-vfloat32m2_t test_vunzipo_v_f32m2_tum(vbool16_t vm, vfloat32m2_t vd,
- vfloat32m4_t vs, size_t vl) {
- return __riscv_vunzipo_v_f32m2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vunzipo_v_f32m4_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 16 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vunzipo.mask.nxv8f32.nxv16f32.i64(<vscale x 8 x float> [[VD]], <vscale x 16 x float> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
-//
-vfloat32m4_t test_vunzipo_v_f32m4_tum(vbool8_t vm, vfloat32m4_t vd,
- vfloat32m8_t vs, size_t vl) {
- return __riscv_vunzipo_v_f32m4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vunzipo_v_f64m1_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 2 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vunzipo.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[VD]], <vscale x 2 x double> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
-//
-vfloat64m1_t test_vunzipo_v_f64m1_tum(vbool64_t vm, vfloat64m1_t vd,
- vfloat64m2_t vs, size_t vl) {
- return __riscv_vunzipo_v_f64m1_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vunzipo_v_f64m2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 4 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vunzipo.mask.nxv2f64.nxv4f64.i64(<vscale x 2 x double> [[VD]], <vscale x 4 x double> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
-//
-vfloat64m2_t test_vunzipo_v_f64m2_tum(vbool32_t vm, vfloat64m2_t vd,
- vfloat64m4_t vs, size_t vl) {
- return __riscv_vunzipo_v_f64m2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vunzipo_v_f64m4_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 8 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vunzipo.mask.nxv4f64.nxv8f64.i64(<vscale x 4 x double> [[VD]], <vscale x 8 x double> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
-//
-vfloat64m4_t test_vunzipo_v_f64m4_tum(vbool16_t vm, vfloat64m4_t vd,
- vfloat64m8_t vs, size_t vl) {
- return __riscv_vunzipo_v_f64m4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vunzipo_v_i8mf8_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vunzipo.mask.nxv1i8.nxv2i8.i64(<vscale x 1 x i8> [[VD]], <vscale x 2 x i8> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
-//
-vint8mf8_t test_vunzipo_v_i8mf8_tum(vbool64_t vm, vint8mf8_t vd, vint8mf4_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i8mf8_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vunzipo_v_i8mf4_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vunzipo.mask.nxv2i8.nxv4i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 4 x i8> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
-//
-vint8mf4_t test_vunzipo_v_i8mf4_tum(vbool32_t vm, vint8mf4_t vd, vint8mf2_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i8mf4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vunzipo_v_i8mf2_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vunzipo.mask.nxv4i8.nxv8i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 8 x i8> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
-//
-vint8mf2_t test_vunzipo_v_i8mf2_tum(vbool16_t vm, vint8mf2_t vd, vint8m1_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i8mf2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vunzipo_v_i8m1_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vunzipo.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 16 x i8> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
-//
-vint8m1_t test_vunzipo_v_i8m1_tum(vbool8_t vm, vint8m1_t vd, vint8m2_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i8m1_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vunzipo_v_i8m2_tum
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vunzipo.mask.nxv16i8.nxv32i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 32 x i8> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-vint8m2_t test_vunzipo_v_i8m2_tum(vbool4_t vm, vint8m2_t vd, vint8m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i8m2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vunzipo_v_i8m4_tum
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vunzipo.mask.nxv32i8.nxv64i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 64 x i8> [[VS]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
-//
-vint8m4_t test_vunzipo_v_i8m4_tum(vbool2_t vm, vint8m4_t vd, vint8m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i8m4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vunzipo_v_i16mf4_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vunzipo.mask.nxv1i16.nxv2i16.i64(<vscale x 1 x i16> [[VD]], <vscale x 2 x i16> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
-//
-vint16mf4_t test_vunzipo_v_i16mf4_tum(vbool64_t vm, vint16mf4_t vd,
- vint16mf2_t vs, size_t vl) {
- return __riscv_vunzipo_v_i16mf4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vunzipo_v_i16mf2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vunzipo.mask.nxv2i16.nxv4i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 4 x i16> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
-//
-vint16mf2_t test_vunzipo_v_i16mf2_tum(vbool32_t vm, vint16mf2_t vd,
- vint16m1_t vs, size_t vl) {
- return __riscv_vunzipo_v_i16mf2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vunzipo_v_i16m1_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vunzipo.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 8 x i16> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
-//
-vint16m1_t test_vunzipo_v_i16m1_tum(vbool16_t vm, vint16m1_t vd, vint16m2_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i16m1_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vunzipo_v_i16m2_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vunzipo.mask.nxv8i16.nxv16i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 16 x i16> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-vint16m2_t test_vunzipo_v_i16m2_tum(vbool8_t vm, vint16m2_t vd, vint16m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i16m2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vunzipo_v_i16m4_tum
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vunzipo.mask.nxv16i16.nxv32i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 32 x i16> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
-//
-vint16m4_t test_vunzipo_v_i16m4_tum(vbool4_t vm, vint16m4_t vd, vint16m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i16m4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vunzipo_v_i32mf2_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vunzipo.mask.nxv1i32.nxv2i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 2 x i32> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vunzipo_v_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
- vint32m1_t vs, size_t vl) {
- return __riscv_vunzipo_v_i32mf2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vunzipo_v_i32m1_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vunzipo.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 4 x i32> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vunzipo_v_i32m1_tum(vbool32_t vm, vint32m1_t vd, vint32m2_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i32m1_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vunzipo_v_i32m2_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vunzipo.mask.nxv4i32.nxv8i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i32> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vunzipo_v_i32m2_tum(vbool16_t vm, vint32m2_t vd, vint32m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i32m2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vunzipo_v_i32m4_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vunzipo.mask.nxv8i32.nxv16i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 16 x i32> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vunzipo_v_i32m4_tum(vbool8_t vm, vint32m4_t vd, vint32m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i32m4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vunzipo_v_i64m1_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vunzipo.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> [[VD]], <vscale x 2 x i64> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
-//
-vint64m1_t test_vunzipo_v_i64m1_tum(vbool64_t vm, vint64m1_t vd, vint64m2_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i64m1_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vunzipo_v_i64m2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vunzipo.mask.nxv2i64.nxv4i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 4 x i64> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-vint64m2_t test_vunzipo_v_i64m2_tum(vbool32_t vm, vint64m2_t vd, vint64m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i64m2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vunzipo_v_i64m4_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vunzipo.mask.nxv4i64.nxv8i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 8 x i64> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
-//
-vint64m4_t test_vunzipo_v_i64m4_tum(vbool16_t vm, vint64m4_t vd, vint64m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i64m4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vunzipo_v_u8mf8_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vunzipo.mask.nxv1i8.nxv2i8.i64(<vscale x 1 x i8> [[VD]], <vscale x 2 x i8> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
-//
-vuint8mf8_t test_vunzipo_v_u8mf8_tum(vbool64_t vm, vuint8mf8_t vd,
- vuint8mf4_t vs, size_t vl) {
- return __riscv_vunzipo_v_u8mf8_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vunzipo_v_u8mf4_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vunzipo.mask.nxv2i8.nxv4i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 4 x i8> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
-//
-vuint8mf4_t test_vunzipo_v_u8mf4_tum(vbool32_t vm, vuint8mf4_t vd,
- vuint8mf2_t vs, size_t vl) {
- return __riscv_vunzipo_v_u8mf4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vunzipo_v_u8mf2_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vunzipo.mask.nxv4i8.nxv8i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 8 x i8> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
-//
-vuint8mf2_t test_vunzipo_v_u8mf2_tum(vbool16_t vm, vuint8mf2_t vd,
- vuint8m1_t vs, size_t vl) {
- return __riscv_vunzipo_v_u8mf2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vunzipo_v_u8m1_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vunzipo.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 16 x i8> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
-//
-vuint8m1_t test_vunzipo_v_u8m1_tum(vbool8_t vm, vuint8m1_t vd, vuint8m2_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_u8m1_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vunzipo_v_u8m2_tum
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vunzipo.mask.nxv16i8.nxv32i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 32 x i8> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-vuint8m2_t test_vunzipo_v_u8m2_tum(vbool4_t vm, vuint8m2_t vd, vuint8m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_u8m2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vunzipo_v_u8m4_tum
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vunzipo.mask.nxv32i8.nxv64i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 64 x i8> [[VS]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
-//
-vuint8m4_t test_vunzipo_v_u8m4_tum(vbool2_t vm, vuint8m4_t vd, vuint8m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_u8m4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vunzipo_v_u16mf4_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vunzipo.mask.nxv1i16.nxv2i16.i64(<vscale x 1 x i16> [[VD]], <vscale x 2 x i16> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
-//
-vuint16mf4_t test_vunzipo_v_u16mf4_tum(vbool64_t vm, vuint16mf4_t vd,
- vuint16mf2_t vs, size_t vl) {
- return __riscv_vunzipo_v_u16mf4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vunzipo_v_u16mf2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vunzipo.mask.nxv2i16.nxv4i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 4 x i16> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
-//
-vuint16mf2_t test_vunzipo_v_u16mf2_tum(vbool32_t vm, vuint16mf2_t vd,
- vuint16m1_t vs, size_t vl) {
- return __riscv_vunzipo_v_u16mf2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vunzipo_v_u16m1_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vunzipo.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 8 x i16> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
-//
-vuint16m1_t test_vunzipo_v_u16m1_tum(vbool16_t vm, vuint16m1_t vd,
- vuint16m2_t vs, size_t vl) {
- return __riscv_vunzipo_v_u16m1_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vunzipo_v_u16m2_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vunzipo.mask.nxv8i16.nxv16i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 16 x i16> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-vuint16m2_t test_vunzipo_v_u16m2_tum(vbool8_t vm, vuint16m2_t vd,
- vuint16m4_t vs, size_t vl) {
- return __riscv_vunzipo_v_u16m2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vunzipo_v_u16m4_tum
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vunzipo.mask.nxv16i16.nxv32i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 32 x i16> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
-//
-vuint16m4_t test_vunzipo_v_u16m4_tum(vbool4_t vm, vuint16m4_t vd,
- vuint16m8_t vs, size_t vl) {
- return __riscv_vunzipo_v_u16m4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vunzipo_v_u32mf2_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vunzipo.mask.nxv1i32.nxv2i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 2 x i32> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vuint32mf2_t test_vunzipo_v_u32mf2_tum(vbool64_t vm, vuint32mf2_t vd,
- vuint32m1_t vs, size_t vl) {
- return __riscv_vunzipo_v_u32mf2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vunzipo_v_u32m1_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vunzipo.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 4 x i32> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vuint32m1_t test_vunzipo_v_u32m1_tum(vbool32_t vm, vuint32m1_t vd,
- vuint32m2_t vs, size_t vl) {
- return __riscv_vunzipo_v_u32m1_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vunzipo_v_u32m2_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vunzipo.mask.nxv4i32.nxv8i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i32> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vuint32m2_t test_vunzipo_v_u32m2_tum(vbool16_t vm, vuint32m2_t vd,
- vuint32m4_t vs, size_t vl) {
- return __riscv_vunzipo_v_u32m2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vunzipo_v_u32m4_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vunzipo.mask.nxv8i32.nxv16i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 16 x i32> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vuint32m4_t test_vunzipo_v_u32m4_tum(vbool8_t vm, vuint32m4_t vd,
- vuint32m8_t vs, size_t vl) {
- return __riscv_vunzipo_v_u32m4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vunzipo_v_u64m1_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vunzipo.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> [[VD]], <vscale x 2 x i64> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
-//
-vuint64m1_t test_vunzipo_v_u64m1_tum(vbool64_t vm, vuint64m1_t vd,
- vuint64m2_t vs, size_t vl) {
- return __riscv_vunzipo_v_u64m1_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vunzipo_v_u64m2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vunzipo.mask.nxv2i64.nxv4i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 4 x i64> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-vuint64m2_t test_vunzipo_v_u64m2_tum(vbool32_t vm, vuint64m2_t vd,
- vuint64m4_t vs, size_t vl) {
- return __riscv_vunzipo_v_u64m2_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vunzipo_v_u64m4_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vunzipo.mask.nxv4i64.nxv8i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 8 x i64> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
-//
-vuint64m4_t test_vunzipo_v_u64m4_tum(vbool16_t vm, vuint64m4_t vd,
- vuint64m8_t vs, size_t vl) {
- return __riscv_vunzipo_v_u64m4_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vunzipo_v_f16mf4_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 2 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vunzipo.mask.nxv1f16.nxv2f16.i64(<vscale x 1 x half> [[VD]], <vscale x 2 x half> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
-//
-vfloat16mf4_t test_vunzipo_v_f16mf4_tumu(vbool64_t vm, vfloat16mf4_t vd,
- vfloat16mf2_t vs, size_t vl) {
- return __riscv_vunzipo_v_f16mf4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vunzipo_v_f16mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 4 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vunzipo.mask.nxv2f16.nxv4f16.i64(<vscale x 2 x half> [[VD]], <vscale x 4 x half> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
-//
-vfloat16mf2_t test_vunzipo_v_f16mf2_tumu(vbool32_t vm, vfloat16mf2_t vd,
- vfloat16m1_t vs, size_t vl) {
- return __riscv_vunzipo_v_f16mf2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vunzipo_v_f16m1_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 8 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vunzipo.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[VD]], <vscale x 8 x half> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
-//
-vfloat16m1_t test_vunzipo_v_f16m1_tumu(vbool16_t vm, vfloat16m1_t vd,
- vfloat16m2_t vs, size_t vl) {
- return __riscv_vunzipo_v_f16m1_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vunzipo_v_f16m2_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 16 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vunzipo.mask.nxv8f16.nxv16f16.i64(<vscale x 8 x half> [[VD]], <vscale x 16 x half> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
-//
-vfloat16m2_t test_vunzipo_v_f16m2_tumu(vbool8_t vm, vfloat16m2_t vd,
- vfloat16m4_t vs, size_t vl) {
- return __riscv_vunzipo_v_f16m2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vunzipo_v_f16m4_tumu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 32 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vunzipo.mask.nxv16f16.nxv32f16.i64(<vscale x 16 x half> [[VD]], <vscale x 32 x half> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
-//
-vfloat16m4_t test_vunzipo_v_f16m4_tumu(vbool4_t vm, vfloat16m4_t vd,
- vfloat16m8_t vs, size_t vl) {
- return __riscv_vunzipo_v_f16m4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vunzipo_v_f32mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 2 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vunzipo.mask.nxv1f32.nxv2f32.i64(<vscale x 1 x float> [[VD]], <vscale x 2 x float> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
-//
-vfloat32mf2_t test_vunzipo_v_f32mf2_tumu(vbool64_t vm, vfloat32mf2_t vd,
- vfloat32m1_t vs, size_t vl) {
- return __riscv_vunzipo_v_f32mf2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vunzipo_v_f32m1_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 4 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vunzipo.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[VD]], <vscale x 4 x float> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
-//
-vfloat32m1_t test_vunzipo_v_f32m1_tumu(vbool32_t vm, vfloat32m1_t vd,
- vfloat32m2_t vs, size_t vl) {
- return __riscv_vunzipo_v_f32m1_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vunzipo_v_f32m2_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 8 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vunzipo.mask.nxv4f32.nxv8f32.i64(<vscale x 4 x float> [[VD]], <vscale x 8 x float> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
-//
-vfloat32m2_t test_vunzipo_v_f32m2_tumu(vbool16_t vm, vfloat32m2_t vd,
- vfloat32m4_t vs, size_t vl) {
- return __riscv_vunzipo_v_f32m2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vunzipo_v_f32m4_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 16 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vunzipo.mask.nxv8f32.nxv16f32.i64(<vscale x 8 x float> [[VD]], <vscale x 16 x float> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
-//
-vfloat32m4_t test_vunzipo_v_f32m4_tumu(vbool8_t vm, vfloat32m4_t vd,
- vfloat32m8_t vs, size_t vl) {
- return __riscv_vunzipo_v_f32m4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vunzipo_v_f64m1_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 2 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vunzipo.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[VD]], <vscale x 2 x double> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
-//
-vfloat64m1_t test_vunzipo_v_f64m1_tumu(vbool64_t vm, vfloat64m1_t vd,
- vfloat64m2_t vs, size_t vl) {
- return __riscv_vunzipo_v_f64m1_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vunzipo_v_f64m2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 4 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vunzipo.mask.nxv2f64.nxv4f64.i64(<vscale x 2 x double> [[VD]], <vscale x 4 x double> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
-//
-vfloat64m2_t test_vunzipo_v_f64m2_tumu(vbool32_t vm, vfloat64m2_t vd,
- vfloat64m4_t vs, size_t vl) {
- return __riscv_vunzipo_v_f64m2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vunzipo_v_f64m4_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 8 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vunzipo.mask.nxv4f64.nxv8f64.i64(<vscale x 4 x double> [[VD]], <vscale x 8 x double> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
-//
-vfloat64m4_t test_vunzipo_v_f64m4_tumu(vbool16_t vm, vfloat64m4_t vd,
- vfloat64m8_t vs, size_t vl) {
- return __riscv_vunzipo_v_f64m4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vunzipo_v_i8mf8_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vunzipo.mask.nxv1i8.nxv2i8.i64(<vscale x 1 x i8> [[VD]], <vscale x 2 x i8> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
-//
-vint8mf8_t test_vunzipo_v_i8mf8_tumu(vbool64_t vm, vint8mf8_t vd, vint8mf4_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i8mf8_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vunzipo_v_i8mf4_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vunzipo.mask.nxv2i8.nxv4i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 4 x i8> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
-//
-vint8mf4_t test_vunzipo_v_i8mf4_tumu(vbool32_t vm, vint8mf4_t vd, vint8mf2_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i8mf4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vunzipo_v_i8mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vunzipo.mask.nxv4i8.nxv8i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 8 x i8> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
-//
-vint8mf2_t test_vunzipo_v_i8mf2_tumu(vbool16_t vm, vint8mf2_t vd, vint8m1_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i8mf2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vunzipo_v_i8m1_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vunzipo.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 16 x i8> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
-//
-vint8m1_t test_vunzipo_v_i8m1_tumu(vbool8_t vm, vint8m1_t vd, vint8m2_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i8m1_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vunzipo_v_i8m2_tumu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vunzipo.mask.nxv16i8.nxv32i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 32 x i8> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-vint8m2_t test_vunzipo_v_i8m2_tumu(vbool4_t vm, vint8m2_t vd, vint8m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i8m2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vunzipo_v_i8m4_tumu
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vunzipo.mask.nxv32i8.nxv64i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 64 x i8> [[VS]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
-//
-vint8m4_t test_vunzipo_v_i8m4_tumu(vbool2_t vm, vint8m4_t vd, vint8m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i8m4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vunzipo_v_i16mf4_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vunzipo.mask.nxv1i16.nxv2i16.i64(<vscale x 1 x i16> [[VD]], <vscale x 2 x i16> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
-//
-vint16mf4_t test_vunzipo_v_i16mf4_tumu(vbool64_t vm, vint16mf4_t vd,
- vint16mf2_t vs, size_t vl) {
- return __riscv_vunzipo_v_i16mf4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vunzipo_v_i16mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vunzipo.mask.nxv2i16.nxv4i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 4 x i16> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
-//
-vint16mf2_t test_vunzipo_v_i16mf2_tumu(vbool32_t vm, vint16mf2_t vd,
- vint16m1_t vs, size_t vl) {
- return __riscv_vunzipo_v_i16mf2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vunzipo_v_i16m1_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vunzipo.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 8 x i16> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
-//
-vint16m1_t test_vunzipo_v_i16m1_tumu(vbool16_t vm, vint16m1_t vd, vint16m2_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i16m1_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vunzipo_v_i16m2_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vunzipo.mask.nxv8i16.nxv16i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 16 x i16> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-vint16m2_t test_vunzipo_v_i16m2_tumu(vbool8_t vm, vint16m2_t vd, vint16m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i16m2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vunzipo_v_i16m4_tumu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vunzipo.mask.nxv16i16.nxv32i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 32 x i16> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
-//
-vint16m4_t test_vunzipo_v_i16m4_tumu(vbool4_t vm, vint16m4_t vd, vint16m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i16m4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vunzipo_v_i32mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vunzipo.mask.nxv1i32.nxv2i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 2 x i32> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vunzipo_v_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
- vint32m1_t vs, size_t vl) {
- return __riscv_vunzipo_v_i32mf2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vunzipo_v_i32m1_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vunzipo.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 4 x i32> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vunzipo_v_i32m1_tumu(vbool32_t vm, vint32m1_t vd, vint32m2_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i32m1_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vunzipo_v_i32m2_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vunzipo.mask.nxv4i32.nxv8i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i32> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vunzipo_v_i32m2_tumu(vbool16_t vm, vint32m2_t vd, vint32m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i32m2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vunzipo_v_i32m4_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vunzipo.mask.nxv8i32.nxv16i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 16 x i32> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vunzipo_v_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vint32m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i32m4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vunzipo_v_i64m1_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vunzipo.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> [[VD]], <vscale x 2 x i64> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
-//
-vint64m1_t test_vunzipo_v_i64m1_tumu(vbool64_t vm, vint64m1_t vd, vint64m2_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i64m1_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vunzipo_v_i64m2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vunzipo.mask.nxv2i64.nxv4i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 4 x i64> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-vint64m2_t test_vunzipo_v_i64m2_tumu(vbool32_t vm, vint64m2_t vd, vint64m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i64m2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vunzipo_v_i64m4_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vunzipo.mask.nxv4i64.nxv8i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 8 x i64> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
-//
-vint64m4_t test_vunzipo_v_i64m4_tumu(vbool16_t vm, vint64m4_t vd, vint64m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i64m4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vunzipo_v_u8mf8_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vunzipo.mask.nxv1i8.nxv2i8.i64(<vscale x 1 x i8> [[VD]], <vscale x 2 x i8> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
-//
-vuint8mf8_t test_vunzipo_v_u8mf8_tumu(vbool64_t vm, vuint8mf8_t vd,
- vuint8mf4_t vs, size_t vl) {
- return __riscv_vunzipo_v_u8mf8_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vunzipo_v_u8mf4_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vunzipo.mask.nxv2i8.nxv4i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 4 x i8> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
-//
-vuint8mf4_t test_vunzipo_v_u8mf4_tumu(vbool32_t vm, vuint8mf4_t vd,
- vuint8mf2_t vs, size_t vl) {
- return __riscv_vunzipo_v_u8mf4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vunzipo_v_u8mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vunzipo.mask.nxv4i8.nxv8i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 8 x i8> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
-//
-vuint8mf2_t test_vunzipo_v_u8mf2_tumu(vbool16_t vm, vuint8mf2_t vd,
- vuint8m1_t vs, size_t vl) {
- return __riscv_vunzipo_v_u8mf2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vunzipo_v_u8m1_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vunzipo.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 16 x i8> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
-//
-vuint8m1_t test_vunzipo_v_u8m1_tumu(vbool8_t vm, vuint8m1_t vd, vuint8m2_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_u8m1_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vunzipo_v_u8m2_tumu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vunzipo.mask.nxv16i8.nxv32i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 32 x i8> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-vuint8m2_t test_vunzipo_v_u8m2_tumu(vbool4_t vm, vuint8m2_t vd, vuint8m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_u8m2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vunzipo_v_u8m4_tumu
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vunzipo.mask.nxv32i8.nxv64i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 64 x i8> [[VS]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
-//
-vuint8m4_t test_vunzipo_v_u8m4_tumu(vbool2_t vm, vuint8m4_t vd, vuint8m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_u8m4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vunzipo_v_u16mf4_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vunzipo.mask.nxv1i16.nxv2i16.i64(<vscale x 1 x i16> [[VD]], <vscale x 2 x i16> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
-//
-vuint16mf4_t test_vunzipo_v_u16mf4_tumu(vbool64_t vm, vuint16mf4_t vd,
- vuint16mf2_t vs, size_t vl) {
- return __riscv_vunzipo_v_u16mf4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vunzipo_v_u16mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vunzipo.mask.nxv2i16.nxv4i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 4 x i16> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
-//
-vuint16mf2_t test_vunzipo_v_u16mf2_tumu(vbool32_t vm, vuint16mf2_t vd,
- vuint16m1_t vs, size_t vl) {
- return __riscv_vunzipo_v_u16mf2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vunzipo_v_u16m1_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vunzipo.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 8 x i16> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
-//
-vuint16m1_t test_vunzipo_v_u16m1_tumu(vbool16_t vm, vuint16m1_t vd,
- vuint16m2_t vs, size_t vl) {
- return __riscv_vunzipo_v_u16m1_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vunzipo_v_u16m2_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vunzipo.mask.nxv8i16.nxv16i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 16 x i16> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-vuint16m2_t test_vunzipo_v_u16m2_tumu(vbool8_t vm, vuint16m2_t vd,
- vuint16m4_t vs, size_t vl) {
- return __riscv_vunzipo_v_u16m2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vunzipo_v_u16m4_tumu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vunzipo.mask.nxv16i16.nxv32i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 32 x i16> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
-//
-vuint16m4_t test_vunzipo_v_u16m4_tumu(vbool4_t vm, vuint16m4_t vd,
- vuint16m8_t vs, size_t vl) {
- return __riscv_vunzipo_v_u16m4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vunzipo_v_u32mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vunzipo.mask.nxv1i32.nxv2i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 2 x i32> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vuint32mf2_t test_vunzipo_v_u32mf2_tumu(vbool64_t vm, vuint32mf2_t vd,
- vuint32m1_t vs, size_t vl) {
- return __riscv_vunzipo_v_u32mf2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vunzipo_v_u32m1_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vunzipo.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 4 x i32> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vuint32m1_t test_vunzipo_v_u32m1_tumu(vbool32_t vm, vuint32m1_t vd,
- vuint32m2_t vs, size_t vl) {
- return __riscv_vunzipo_v_u32m1_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vunzipo_v_u32m2_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vunzipo.mask.nxv4i32.nxv8i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i32> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vuint32m2_t test_vunzipo_v_u32m2_tumu(vbool16_t vm, vuint32m2_t vd,
- vuint32m4_t vs, size_t vl) {
- return __riscv_vunzipo_v_u32m2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vunzipo_v_u32m4_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vunzipo.mask.nxv8i32.nxv16i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 16 x i32> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vuint32m4_t test_vunzipo_v_u32m4_tumu(vbool8_t vm, vuint32m4_t vd,
- vuint32m8_t vs, size_t vl) {
- return __riscv_vunzipo_v_u32m4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vunzipo_v_u64m1_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vunzipo.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> [[VD]], <vscale x 2 x i64> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
-//
-vuint64m1_t test_vunzipo_v_u64m1_tumu(vbool64_t vm, vuint64m1_t vd,
- vuint64m2_t vs, size_t vl) {
- return __riscv_vunzipo_v_u64m1_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vunzipo_v_u64m2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vunzipo.mask.nxv2i64.nxv4i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 4 x i64> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-vuint64m2_t test_vunzipo_v_u64m2_tumu(vbool32_t vm, vuint64m2_t vd,
- vuint64m4_t vs, size_t vl) {
- return __riscv_vunzipo_v_u64m2_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vunzipo_v_u64m4_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vunzipo.mask.nxv4i64.nxv8i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 8 x i64> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
-//
-vuint64m4_t test_vunzipo_v_u64m4_tumu(vbool16_t vm, vuint64m4_t vd,
- vuint64m8_t vs, size_t vl) {
- return __riscv_vunzipo_v_u64m4_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vunzipo_v_f16mf4_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 2 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vunzipo.mask.nxv1f16.nxv2f16.i64(<vscale x 1 x half> [[VD]], <vscale x 2 x half> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
-//
-vfloat16mf4_t test_vunzipo_v_f16mf4_mu(vbool64_t vm, vfloat16mf4_t vd,
- vfloat16mf2_t vs, size_t vl) {
- return __riscv_vunzipo_v_f16mf4_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vunzipo_v_f16mf2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 4 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vunzipo.mask.nxv2f16.nxv4f16.i64(<vscale x 2 x half> [[VD]], <vscale x 4 x half> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
-//
-vfloat16mf2_t test_vunzipo_v_f16mf2_mu(vbool32_t vm, vfloat16mf2_t vd,
- vfloat16m1_t vs, size_t vl) {
- return __riscv_vunzipo_v_f16mf2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vunzipo_v_f16m1_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 8 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vunzipo.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[VD]], <vscale x 8 x half> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
-//
-vfloat16m1_t test_vunzipo_v_f16m1_mu(vbool16_t vm, vfloat16m1_t vd,
- vfloat16m2_t vs, size_t vl) {
- return __riscv_vunzipo_v_f16m1_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vunzipo_v_f16m2_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 16 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vunzipo.mask.nxv8f16.nxv16f16.i64(<vscale x 8 x half> [[VD]], <vscale x 16 x half> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
-//
-vfloat16m2_t test_vunzipo_v_f16m2_mu(vbool8_t vm, vfloat16m2_t vd,
- vfloat16m4_t vs, size_t vl) {
- return __riscv_vunzipo_v_f16m2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vunzipo_v_f16m4_mu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 32 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vunzipo.mask.nxv16f16.nxv32f16.i64(<vscale x 16 x half> [[VD]], <vscale x 32 x half> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
-//
-vfloat16m4_t test_vunzipo_v_f16m4_mu(vbool4_t vm, vfloat16m4_t vd,
- vfloat16m8_t vs, size_t vl) {
- return __riscv_vunzipo_v_f16m4_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vunzipo_v_f32mf2_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 2 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vunzipo.mask.nxv1f32.nxv2f32.i64(<vscale x 1 x float> [[VD]], <vscale x 2 x float> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
-//
-vfloat32mf2_t test_vunzipo_v_f32mf2_mu(vbool64_t vm, vfloat32mf2_t vd,
- vfloat32m1_t vs, size_t vl) {
- return __riscv_vunzipo_v_f32mf2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vunzipo_v_f32m1_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 4 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vunzipo.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[VD]], <vscale x 4 x float> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
-//
-vfloat32m1_t test_vunzipo_v_f32m1_mu(vbool32_t vm, vfloat32m1_t vd,
- vfloat32m2_t vs, size_t vl) {
- return __riscv_vunzipo_v_f32m1_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vunzipo_v_f32m2_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 8 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vunzipo.mask.nxv4f32.nxv8f32.i64(<vscale x 4 x float> [[VD]], <vscale x 8 x float> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
-//
-vfloat32m2_t test_vunzipo_v_f32m2_mu(vbool16_t vm, vfloat32m2_t vd,
- vfloat32m4_t vs, size_t vl) {
- return __riscv_vunzipo_v_f32m2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vunzipo_v_f32m4_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 16 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vunzipo.mask.nxv8f32.nxv16f32.i64(<vscale x 8 x float> [[VD]], <vscale x 16 x float> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
-//
-vfloat32m4_t test_vunzipo_v_f32m4_mu(vbool8_t vm, vfloat32m4_t vd,
- vfloat32m8_t vs, size_t vl) {
- return __riscv_vunzipo_v_f32m4_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vunzipo_v_f64m1_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 2 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vunzipo.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[VD]], <vscale x 2 x double> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
-//
-vfloat64m1_t test_vunzipo_v_f64m1_mu(vbool64_t vm, vfloat64m1_t vd,
- vfloat64m2_t vs, size_t vl) {
- return __riscv_vunzipo_v_f64m1_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vunzipo_v_f64m2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 4 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vunzipo.mask.nxv2f64.nxv4f64.i64(<vscale x 2 x double> [[VD]], <vscale x 4 x double> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
-//
-vfloat64m2_t test_vunzipo_v_f64m2_mu(vbool32_t vm, vfloat64m2_t vd,
- vfloat64m4_t vs, size_t vl) {
- return __riscv_vunzipo_v_f64m2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vunzipo_v_f64m4_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 8 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vunzipo.mask.nxv4f64.nxv8f64.i64(<vscale x 4 x double> [[VD]], <vscale x 8 x double> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
-//
-vfloat64m4_t test_vunzipo_v_f64m4_mu(vbool16_t vm, vfloat64m4_t vd,
- vfloat64m8_t vs, size_t vl) {
- return __riscv_vunzipo_v_f64m4_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vunzipo_v_i8mf8_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vunzipo.mask.nxv1i8.nxv2i8.i64(<vscale x 1 x i8> [[VD]], <vscale x 2 x i8> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
-//
-vint8mf8_t test_vunzipo_v_i8mf8_mu(vbool64_t vm, vint8mf8_t vd, vint8mf4_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i8mf8_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vunzipo_v_i8mf4_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vunzipo.mask.nxv2i8.nxv4i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 4 x i8> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
-//
-vint8mf4_t test_vunzipo_v_i8mf4_mu(vbool32_t vm, vint8mf4_t vd, vint8mf2_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i8mf4_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vunzipo_v_i8mf2_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vunzipo.mask.nxv4i8.nxv8i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 8 x i8> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
-//
-vint8mf2_t test_vunzipo_v_i8mf2_mu(vbool16_t vm, vint8mf2_t vd, vint8m1_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i8mf2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vunzipo_v_i8m1_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vunzipo.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 16 x i8> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
-//
-vint8m1_t test_vunzipo_v_i8m1_mu(vbool8_t vm, vint8m1_t vd, vint8m2_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i8m1_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vunzipo_v_i8m2_mu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vunzipo.mask.nxv16i8.nxv32i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 32 x i8> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-vint8m2_t test_vunzipo_v_i8m2_mu(vbool4_t vm, vint8m2_t vd, vint8m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i8m2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vunzipo_v_i8m4_mu
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vunzipo.mask.nxv32i8.nxv64i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 64 x i8> [[VS]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
-//
-vint8m4_t test_vunzipo_v_i8m4_mu(vbool2_t vm, vint8m4_t vd, vint8m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i8m4_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vunzipo_v_i16mf4_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vunzipo.mask.nxv1i16.nxv2i16.i64(<vscale x 1 x i16> [[VD]], <vscale x 2 x i16> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
-//
-vint16mf4_t test_vunzipo_v_i16mf4_mu(vbool64_t vm, vint16mf4_t vd,
- vint16mf2_t vs, size_t vl) {
- return __riscv_vunzipo_v_i16mf4_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vunzipo_v_i16mf2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vunzipo.mask.nxv2i16.nxv4i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 4 x i16> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
-//
-vint16mf2_t test_vunzipo_v_i16mf2_mu(vbool32_t vm, vint16mf2_t vd,
- vint16m1_t vs, size_t vl) {
- return __riscv_vunzipo_v_i16mf2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vunzipo_v_i16m1_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vunzipo.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 8 x i16> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
-//
-vint16m1_t test_vunzipo_v_i16m1_mu(vbool16_t vm, vint16m1_t vd, vint16m2_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i16m1_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vunzipo_v_i16m2_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vunzipo.mask.nxv8i16.nxv16i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 16 x i16> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-vint16m2_t test_vunzipo_v_i16m2_mu(vbool8_t vm, vint16m2_t vd, vint16m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i16m2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vunzipo_v_i16m4_mu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vunzipo.mask.nxv16i16.nxv32i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 32 x i16> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
-//
-vint16m4_t test_vunzipo_v_i16m4_mu(vbool4_t vm, vint16m4_t vd, vint16m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i16m4_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vunzipo_v_i32mf2_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vunzipo.mask.nxv1i32.nxv2i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 2 x i32> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vunzipo_v_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
- vint32m1_t vs, size_t vl) {
- return __riscv_vunzipo_v_i32mf2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vunzipo_v_i32m1_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vunzipo.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 4 x i32> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vunzipo_v_i32m1_mu(vbool32_t vm, vint32m1_t vd, vint32m2_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i32m1_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vunzipo_v_i32m2_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vunzipo.mask.nxv4i32.nxv8i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i32> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vunzipo_v_i32m2_mu(vbool16_t vm, vint32m2_t vd, vint32m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i32m2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vunzipo_v_i32m4_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vunzipo.mask.nxv8i32.nxv16i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 16 x i32> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vunzipo_v_i32m4_mu(vbool8_t vm, vint32m4_t vd, vint32m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i32m4_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vunzipo_v_i64m1_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vunzipo.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> [[VD]], <vscale x 2 x i64> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
-//
-vint64m1_t test_vunzipo_v_i64m1_mu(vbool64_t vm, vint64m1_t vd, vint64m2_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i64m1_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vunzipo_v_i64m2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vunzipo.mask.nxv2i64.nxv4i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 4 x i64> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-vint64m2_t test_vunzipo_v_i64m2_mu(vbool32_t vm, vint64m2_t vd, vint64m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i64m2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vunzipo_v_i64m4_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vunzipo.mask.nxv4i64.nxv8i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 8 x i64> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
-//
-vint64m4_t test_vunzipo_v_i64m4_mu(vbool16_t vm, vint64m4_t vd, vint64m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_i64m4_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vunzipo_v_u8mf8_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vunzipo.mask.nxv1i8.nxv2i8.i64(<vscale x 1 x i8> [[VD]], <vscale x 2 x i8> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
-//
-vuint8mf8_t test_vunzipo_v_u8mf8_mu(vbool64_t vm, vuint8mf8_t vd,
- vuint8mf4_t vs, size_t vl) {
- return __riscv_vunzipo_v_u8mf8_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vunzipo_v_u8mf4_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vunzipo.mask.nxv2i8.nxv4i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 4 x i8> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
-//
-vuint8mf4_t test_vunzipo_v_u8mf4_mu(vbool32_t vm, vuint8mf4_t vd,
- vuint8mf2_t vs, size_t vl) {
- return __riscv_vunzipo_v_u8mf4_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vunzipo_v_u8mf2_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vunzipo.mask.nxv4i8.nxv8i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 8 x i8> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
-//
-vuint8mf2_t test_vunzipo_v_u8mf2_mu(vbool16_t vm, vuint8mf2_t vd, vuint8m1_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_u8mf2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vunzipo_v_u8m1_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vunzipo.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 16 x i8> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
-//
-vuint8m1_t test_vunzipo_v_u8m1_mu(vbool8_t vm, vuint8m1_t vd, vuint8m2_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_u8m1_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vunzipo_v_u8m2_mu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vunzipo.mask.nxv16i8.nxv32i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 32 x i8> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-vuint8m2_t test_vunzipo_v_u8m2_mu(vbool4_t vm, vuint8m2_t vd, vuint8m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_u8m2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vunzipo_v_u8m4_mu
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vunzipo.mask.nxv32i8.nxv64i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 64 x i8> [[VS]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
-//
-vuint8m4_t test_vunzipo_v_u8m4_mu(vbool2_t vm, vuint8m4_t vd, vuint8m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_u8m4_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vunzipo_v_u16mf4_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vunzipo.mask.nxv1i16.nxv2i16.i64(<vscale x 1 x i16> [[VD]], <vscale x 2 x i16> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
-//
-vuint16mf4_t test_vunzipo_v_u16mf4_mu(vbool64_t vm, vuint16mf4_t vd,
- vuint16mf2_t vs, size_t vl) {
- return __riscv_vunzipo_v_u16mf4_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vunzipo_v_u16mf2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vunzipo.mask.nxv2i16.nxv4i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 4 x i16> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
-//
-vuint16mf2_t test_vunzipo_v_u16mf2_mu(vbool32_t vm, vuint16mf2_t vd,
- vuint16m1_t vs, size_t vl) {
- return __riscv_vunzipo_v_u16mf2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vunzipo_v_u16m1_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vunzipo.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 8 x i16> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
-//
-vuint16m1_t test_vunzipo_v_u16m1_mu(vbool16_t vm, vuint16m1_t vd,
- vuint16m2_t vs, size_t vl) {
- return __riscv_vunzipo_v_u16m1_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vunzipo_v_u16m2_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vunzipo.mask.nxv8i16.nxv16i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 16 x i16> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-vuint16m2_t test_vunzipo_v_u16m2_mu(vbool8_t vm, vuint16m2_t vd, vuint16m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_u16m2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vunzipo_v_u16m4_mu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vunzipo.mask.nxv16i16.nxv32i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 32 x i16> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
-//
-vuint16m4_t test_vunzipo_v_u16m4_mu(vbool4_t vm, vuint16m4_t vd, vuint16m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_u16m4_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vunzipo_v_u32mf2_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vunzipo.mask.nxv1i32.nxv2i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 2 x i32> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vuint32mf2_t test_vunzipo_v_u32mf2_mu(vbool64_t vm, vuint32mf2_t vd,
- vuint32m1_t vs, size_t vl) {
- return __riscv_vunzipo_v_u32mf2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vunzipo_v_u32m1_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vunzipo.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 4 x i32> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vuint32m1_t test_vunzipo_v_u32m1_mu(vbool32_t vm, vuint32m1_t vd,
- vuint32m2_t vs, size_t vl) {
- return __riscv_vunzipo_v_u32m1_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vunzipo_v_u32m2_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vunzipo.mask.nxv4i32.nxv8i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i32> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vuint32m2_t test_vunzipo_v_u32m2_mu(vbool16_t vm, vuint32m2_t vd,
- vuint32m4_t vs, size_t vl) {
- return __riscv_vunzipo_v_u32m2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vunzipo_v_u32m4_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vunzipo.mask.nxv8i32.nxv16i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 16 x i32> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vuint32m4_t test_vunzipo_v_u32m4_mu(vbool8_t vm, vuint32m4_t vd, vuint32m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_u32m4_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vunzipo_v_u64m1_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vunzipo.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> [[VD]], <vscale x 2 x i64> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
-//
-vuint64m1_t test_vunzipo_v_u64m1_mu(vbool64_t vm, vuint64m1_t vd,
- vuint64m2_t vs, size_t vl) {
- return __riscv_vunzipo_v_u64m1_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vunzipo_v_u64m2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vunzipo.mask.nxv2i64.nxv4i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 4 x i64> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-vuint64m2_t test_vunzipo_v_u64m2_mu(vbool32_t vm, vuint64m2_t vd,
- vuint64m4_t vs, size_t vl) {
- return __riscv_vunzipo_v_u64m2_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vunzipo_v_u64m4_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vunzipo.mask.nxv4i64.nxv8i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 8 x i64> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
-//
-vuint64m4_t test_vunzipo_v_u64m4_mu(vbool16_t vm, vuint64m4_t vd,
- vuint64m8_t vs, size_t vl) {
- return __riscv_vunzipo_v_u64m4_mu(vm, vd, vs, vl);
-}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c
index 9e500270143f5..67fe5ea5d7b89 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c
@@ -538,1652 +538,1652 @@ vuint64m8_t test_vzip_vv_u64m8_tu(vuint64m8_t vd, vuint64m4_t vs2,
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vzip_vv_f16mf2_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vzip.mask.nxv2f16.nxv1f16.i64(<vscale x 2 x half> [[VD]], <vscale x 1 x half> [[VS2]], <vscale x 1 x half> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vzip.mask.nxv2f16.nxv1f16.i64(<vscale x 2 x half> [[VD]], <vscale x 1 x half> [[VS2]], <vscale x 1 x half> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
-vfloat16mf2_t test_vzip_vv_f16mf2_tum(vbool64_t vm, vfloat16mf2_t vd,
+vfloat16mf2_t test_vzip_vv_f16mf2_tum(vbool32_t vm, vfloat16mf2_t vd,
vfloat16mf4_t vs2, vfloat16mf4_t vs1,
size_t vl) {
return __riscv_vzip_vv_f16mf2_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vzip_vv_f16m1_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vzip.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[VD]], <vscale x 2 x half> [[VS2]], <vscale x 2 x half> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vzip.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[VD]], <vscale x 2 x half> [[VS2]], <vscale x 2 x half> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
-vfloat16m1_t test_vzip_vv_f16m1_tum(vbool32_t vm, vfloat16m1_t vd,
+vfloat16m1_t test_vzip_vv_f16m1_tum(vbool16_t vm, vfloat16m1_t vd,
vfloat16mf2_t vs2, vfloat16mf2_t vs1,
size_t vl) {
return __riscv_vzip_vv_f16m1_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vzip_vv_f16m2_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vzip.mask.nxv8f16.nxv4f16.i64(<vscale x 8 x half> [[VD]], <vscale x 4 x half> [[VS2]], <vscale x 4 x half> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vzip.mask.nxv8f16.nxv4f16.i64(<vscale x 8 x half> [[VD]], <vscale x 4 x half> [[VS2]], <vscale x 4 x half> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
-vfloat16m2_t test_vzip_vv_f16m2_tum(vbool16_t vm, vfloat16m2_t vd,
+vfloat16m2_t test_vzip_vv_f16m2_tum(vbool8_t vm, vfloat16m2_t vd,
vfloat16m1_t vs2, vfloat16m1_t vs1,
size_t vl) {
return __riscv_vzip_vv_f16m2_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vzip_vv_f16m4_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vzip.mask.nxv16f16.nxv8f16.i64(<vscale x 16 x half> [[VD]], <vscale x 8 x half> [[VS2]], <vscale x 8 x half> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vzip.mask.nxv16f16.nxv8f16.i64(<vscale x 16 x half> [[VD]], <vscale x 8 x half> [[VS2]], <vscale x 8 x half> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
-vfloat16m4_t test_vzip_vv_f16m4_tum(vbool8_t vm, vfloat16m4_t vd,
+vfloat16m4_t test_vzip_vv_f16m4_tum(vbool4_t vm, vfloat16m4_t vd,
vfloat16m2_t vs2, vfloat16m2_t vs1,
size_t vl) {
return __riscv_vzip_vv_f16m4_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vzip_vv_f16m8_tum
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vzip.mask.nxv32f16.nxv16f16.i64(<vscale x 32 x half> [[VD]], <vscale x 16 x half> [[VS2]], <vscale x 16 x half> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vzip.mask.nxv32f16.nxv16f16.i64(<vscale x 32 x half> [[VD]], <vscale x 16 x half> [[VS2]], <vscale x 16 x half> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
-vfloat16m8_t test_vzip_vv_f16m8_tum(vbool4_t vm, vfloat16m8_t vd,
+vfloat16m8_t test_vzip_vv_f16m8_tum(vbool2_t vm, vfloat16m8_t vd,
vfloat16m4_t vs2, vfloat16m4_t vs1,
size_t vl) {
return __riscv_vzip_vv_f16m8_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vzip_vv_f32m1_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 1 x float> [[VS2:%.*]], <vscale x 1 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 1 x float> [[VS2:%.*]], <vscale x 1 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vzip.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[VD]], <vscale x 1 x float> [[VS2]], <vscale x 1 x float> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vzip.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[VD]], <vscale x 1 x float> [[VS2]], <vscale x 1 x float> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
-vfloat32m1_t test_vzip_vv_f32m1_tum(vbool64_t vm, vfloat32m1_t vd,
+vfloat32m1_t test_vzip_vv_f32m1_tum(vbool32_t vm, vfloat32m1_t vd,
vfloat32mf2_t vs2, vfloat32mf2_t vs1,
size_t vl) {
return __riscv_vzip_vv_f32m1_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vzip_vv_f32m2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 2 x float> [[VS2:%.*]], <vscale x 2 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 2 x float> [[VS2:%.*]], <vscale x 2 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vzip.mask.nxv4f32.nxv2f32.i64(<vscale x 4 x float> [[VD]], <vscale x 2 x float> [[VS2]], <vscale x 2 x float> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vzip.mask.nxv4f32.nxv2f32.i64(<vscale x 4 x float> [[VD]], <vscale x 2 x float> [[VS2]], <vscale x 2 x float> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
-vfloat32m2_t test_vzip_vv_f32m2_tum(vbool32_t vm, vfloat32m2_t vd,
+vfloat32m2_t test_vzip_vv_f32m2_tum(vbool16_t vm, vfloat32m2_t vd,
vfloat32m1_t vs2, vfloat32m1_t vs1,
size_t vl) {
return __riscv_vzip_vv_f32m2_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vzip_vv_f32m4_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 4 x float> [[VS2:%.*]], <vscale x 4 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 4 x float> [[VS2:%.*]], <vscale x 4 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vzip.mask.nxv8f32.nxv4f32.i64(<vscale x 8 x float> [[VD]], <vscale x 4 x float> [[VS2]], <vscale x 4 x float> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vzip.mask.nxv8f32.nxv4f32.i64(<vscale x 8 x float> [[VD]], <vscale x 4 x float> [[VS2]], <vscale x 4 x float> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
-vfloat32m4_t test_vzip_vv_f32m4_tum(vbool16_t vm, vfloat32m4_t vd,
+vfloat32m4_t test_vzip_vv_f32m4_tum(vbool8_t vm, vfloat32m4_t vd,
vfloat32m2_t vs2, vfloat32m2_t vs1,
size_t vl) {
return __riscv_vzip_vv_f32m4_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vzip_vv_f32m8_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 8 x float> [[VS2:%.*]], <vscale x 8 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 8 x float> [[VS2:%.*]], <vscale x 8 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vzip.mask.nxv16f32.nxv8f32.i64(<vscale x 16 x float> [[VD]], <vscale x 8 x float> [[VS2]], <vscale x 8 x float> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vzip.mask.nxv16f32.nxv8f32.i64(<vscale x 16 x float> [[VD]], <vscale x 8 x float> [[VS2]], <vscale x 8 x float> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
-vfloat32m8_t test_vzip_vv_f32m8_tum(vbool8_t vm, vfloat32m8_t vd,
+vfloat32m8_t test_vzip_vv_f32m8_tum(vbool4_t vm, vfloat32m8_t vd,
vfloat32m4_t vs2, vfloat32m4_t vs1,
size_t vl) {
return __riscv_vzip_vv_f32m8_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vzip_vv_f64m2_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 1 x double> [[VS2:%.*]], <vscale x 1 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 1 x double> [[VS2:%.*]], <vscale x 1 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vzip.mask.nxv2f64.nxv1f64.i64(<vscale x 2 x double> [[VD]], <vscale x 1 x double> [[VS2]], <vscale x 1 x double> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vzip.mask.nxv2f64.nxv1f64.i64(<vscale x 2 x double> [[VD]], <vscale x 1 x double> [[VS2]], <vscale x 1 x double> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
-vfloat64m2_t test_vzip_vv_f64m2_tum(vbool64_t vm, vfloat64m2_t vd,
+vfloat64m2_t test_vzip_vv_f64m2_tum(vbool32_t vm, vfloat64m2_t vd,
vfloat64m1_t vs2, vfloat64m1_t vs1,
size_t vl) {
return __riscv_vzip_vv_f64m2_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vzip_vv_f64m4_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 2 x double> [[VS2:%.*]], <vscale x 2 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 2 x double> [[VS2:%.*]], <vscale x 2 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vzip.mask.nxv4f64.nxv2f64.i64(<vscale x 4 x double> [[VD]], <vscale x 2 x double> [[VS2]], <vscale x 2 x double> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vzip.mask.nxv4f64.nxv2f64.i64(<vscale x 4 x double> [[VD]], <vscale x 2 x double> [[VS2]], <vscale x 2 x double> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
-vfloat64m4_t test_vzip_vv_f64m4_tum(vbool32_t vm, vfloat64m4_t vd,
+vfloat64m4_t test_vzip_vv_f64m4_tum(vbool16_t vm, vfloat64m4_t vd,
vfloat64m2_t vs2, vfloat64m2_t vs1,
size_t vl) {
return __riscv_vzip_vv_f64m4_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vzip_vv_f64m8_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 4 x double> [[VS2:%.*]], <vscale x 4 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 4 x double> [[VS2:%.*]], <vscale x 4 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vzip.mask.nxv8f64.nxv4f64.i64(<vscale x 8 x double> [[VD]], <vscale x 4 x double> [[VS2]], <vscale x 4 x double> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vzip.mask.nxv8f64.nxv4f64.i64(<vscale x 8 x double> [[VD]], <vscale x 4 x double> [[VS2]], <vscale x 4 x double> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
-vfloat64m8_t test_vzip_vv_f64m8_tum(vbool16_t vm, vfloat64m8_t vd,
+vfloat64m8_t test_vzip_vv_f64m8_tum(vbool8_t vm, vfloat64m8_t vd,
vfloat64m4_t vs2, vfloat64m4_t vs1,
size_t vl) {
return __riscv_vzip_vv_f64m8_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vzip_vv_i8mf4_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
-vint8mf4_t test_vzip_vv_i8mf4_tum(vbool64_t vm, vint8mf4_t vd, vint8mf8_t vs2,
+vint8mf4_t test_vzip_vv_i8mf4_tum(vbool32_t vm, vint8mf4_t vd, vint8mf8_t vs2,
vint8mf8_t vs1, size_t vl) {
return __riscv_vzip_vv_i8mf4_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vzip_vv_i8mf2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
-vint8mf2_t test_vzip_vv_i8mf2_tum(vbool32_t vm, vint8mf2_t vd, vint8mf4_t vs2,
+vint8mf2_t test_vzip_vv_i8mf2_tum(vbool16_t vm, vint8mf2_t vd, vint8mf4_t vs2,
vint8mf4_t vs1, size_t vl) {
return __riscv_vzip_vv_i8mf2_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vzip_vv_i8m1_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
-vint8m1_t test_vzip_vv_i8m1_tum(vbool16_t vm, vint8m1_t vd, vint8mf2_t vs2,
+vint8m1_t test_vzip_vv_i8m1_tum(vbool8_t vm, vint8m1_t vd, vint8mf2_t vs2,
vint8mf2_t vs1, size_t vl) {
return __riscv_vzip_vv_i8m1_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vzip_vv_i8m2_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
-vint8m2_t test_vzip_vv_i8m2_tum(vbool8_t vm, vint8m2_t vd, vint8m1_t vs2,
+vint8m2_t test_vzip_vv_i8m2_tum(vbool4_t vm, vint8m2_t vd, vint8m1_t vs2,
vint8m1_t vs1, size_t vl) {
return __riscv_vzip_vv_i8m2_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vzip_vv_i8m4_tum
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
-vint8m4_t test_vzip_vv_i8m4_tum(vbool4_t vm, vint8m4_t vd, vint8m2_t vs2,
+vint8m4_t test_vzip_vv_i8m4_tum(vbool2_t vm, vint8m4_t vd, vint8m2_t vs2,
vint8m2_t vs1, size_t vl) {
return __riscv_vzip_vv_i8m4_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vzip_vv_i8m8_tum
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 64 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 64 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
-vint8m8_t test_vzip_vv_i8m8_tum(vbool2_t vm, vint8m8_t vd, vint8m4_t vs2,
+vint8m8_t test_vzip_vv_i8m8_tum(vbool1_t vm, vint8m8_t vd, vint8m4_t vs2,
vint8m4_t vs1, size_t vl) {
return __riscv_vzip_vv_i8m8_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vzip_vv_i16mf2_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
-vint16mf2_t test_vzip_vv_i16mf2_tum(vbool64_t vm, vint16mf2_t vd,
+vint16mf2_t test_vzip_vv_i16mf2_tum(vbool32_t vm, vint16mf2_t vd,
vint16mf4_t vs2, vint16mf4_t vs1,
size_t vl) {
return __riscv_vzip_vv_i16mf2_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vzip_vv_i16m1_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
-vint16m1_t test_vzip_vv_i16m1_tum(vbool32_t vm, vint16m1_t vd, vint16mf2_t vs2,
+vint16m1_t test_vzip_vv_i16m1_tum(vbool16_t vm, vint16m1_t vd, vint16mf2_t vs2,
vint16mf2_t vs1, size_t vl) {
return __riscv_vzip_vv_i16m1_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vzip_vv_i16m2_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
-vint16m2_t test_vzip_vv_i16m2_tum(vbool16_t vm, vint16m2_t vd, vint16m1_t vs2,
+vint16m2_t test_vzip_vv_i16m2_tum(vbool8_t vm, vint16m2_t vd, vint16m1_t vs2,
vint16m1_t vs1, size_t vl) {
return __riscv_vzip_vv_i16m2_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vzip_vv_i16m4_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
-vint16m4_t test_vzip_vv_i16m4_tum(vbool8_t vm, vint16m4_t vd, vint16m2_t vs2,
+vint16m4_t test_vzip_vv_i16m4_tum(vbool4_t vm, vint16m4_t vd, vint16m2_t vs2,
vint16m2_t vs1, size_t vl) {
return __riscv_vzip_vv_i16m4_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vzip_vv_i16m8_tum
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
-vint16m8_t test_vzip_vv_i16m8_tum(vbool4_t vm, vint16m8_t vd, vint16m4_t vs2,
+vint16m8_t test_vzip_vv_i16m8_tum(vbool2_t vm, vint16m8_t vd, vint16m4_t vs2,
vint16m4_t vs1, size_t vl) {
return __riscv_vzip_vv_i16m8_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vzip_vv_i32m1_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vzip_vv_i32m1_tum(vbool64_t vm, vint32m1_t vd, vint32mf2_t vs2,
+vint32m1_t test_vzip_vv_i32m1_tum(vbool32_t vm, vint32m1_t vd, vint32mf2_t vs2,
vint32mf2_t vs1, size_t vl) {
return __riscv_vzip_vv_i32m1_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vzip_vv_i32m2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vzip_vv_i32m2_tum(vbool32_t vm, vint32m2_t vd, vint32m1_t vs2,
+vint32m2_t test_vzip_vv_i32m2_tum(vbool16_t vm, vint32m2_t vd, vint32m1_t vs2,
vint32m1_t vs1, size_t vl) {
return __riscv_vzip_vv_i32m2_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vzip_vv_i32m4_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vzip_vv_i32m4_tum(vbool16_t vm, vint32m4_t vd, vint32m2_t vs2,
+vint32m4_t test_vzip_vv_i32m4_tum(vbool8_t vm, vint32m4_t vd, vint32m2_t vs2,
vint32m2_t vs1, size_t vl) {
return __riscv_vzip_vv_i32m4_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vzip_vv_i32m8_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vzip_vv_i32m8_tum(vbool8_t vm, vint32m8_t vd, vint32m4_t vs2,
+vint32m8_t test_vzip_vv_i32m8_tum(vbool4_t vm, vint32m8_t vd, vint32m4_t vs2,
vint32m4_t vs1, size_t vl) {
return __riscv_vzip_vv_i32m8_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vzip_vv_i64m2_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
-vint64m2_t test_vzip_vv_i64m2_tum(vbool64_t vm, vint64m2_t vd, vint64m1_t vs2,
+vint64m2_t test_vzip_vv_i64m2_tum(vbool32_t vm, vint64m2_t vd, vint64m1_t vs2,
vint64m1_t vs1, size_t vl) {
return __riscv_vzip_vv_i64m2_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vzip_vv_i64m4_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
-vint64m4_t test_vzip_vv_i64m4_tum(vbool32_t vm, vint64m4_t vd, vint64m2_t vs2,
+vint64m4_t test_vzip_vv_i64m4_tum(vbool16_t vm, vint64m4_t vd, vint64m2_t vs2,
vint64m2_t vs1, size_t vl) {
return __riscv_vzip_vv_i64m4_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vzip_vv_i64m8_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
-vint64m8_t test_vzip_vv_i64m8_tum(vbool16_t vm, vint64m8_t vd, vint64m4_t vs2,
+vint64m8_t test_vzip_vv_i64m8_tum(vbool8_t vm, vint64m8_t vd, vint64m4_t vs2,
vint64m4_t vs1, size_t vl) {
return __riscv_vzip_vv_i64m8_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vzip_vv_u8mf4_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
-vuint8mf4_t test_vzip_vv_u8mf4_tum(vbool64_t vm, vuint8mf4_t vd,
+vuint8mf4_t test_vzip_vv_u8mf4_tum(vbool32_t vm, vuint8mf4_t vd,
vuint8mf8_t vs2, vuint8mf8_t vs1,
size_t vl) {
return __riscv_vzip_vv_u8mf4_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vzip_vv_u8mf2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
-vuint8mf2_t test_vzip_vv_u8mf2_tum(vbool32_t vm, vuint8mf2_t vd,
+vuint8mf2_t test_vzip_vv_u8mf2_tum(vbool16_t vm, vuint8mf2_t vd,
vuint8mf4_t vs2, vuint8mf4_t vs1,
size_t vl) {
return __riscv_vzip_vv_u8mf2_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vzip_vv_u8m1_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
-vuint8m1_t test_vzip_vv_u8m1_tum(vbool16_t vm, vuint8m1_t vd, vuint8mf2_t vs2,
+vuint8m1_t test_vzip_vv_u8m1_tum(vbool8_t vm, vuint8m1_t vd, vuint8mf2_t vs2,
vuint8mf2_t vs1, size_t vl) {
return __riscv_vzip_vv_u8m1_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vzip_vv_u8m2_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
-vuint8m2_t test_vzip_vv_u8m2_tum(vbool8_t vm, vuint8m2_t vd, vuint8m1_t vs2,
+vuint8m2_t test_vzip_vv_u8m2_tum(vbool4_t vm, vuint8m2_t vd, vuint8m1_t vs2,
vuint8m1_t vs1, size_t vl) {
return __riscv_vzip_vv_u8m2_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vzip_vv_u8m4_tum
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
-vuint8m4_t test_vzip_vv_u8m4_tum(vbool4_t vm, vuint8m4_t vd, vuint8m2_t vs2,
+vuint8m4_t test_vzip_vv_u8m4_tum(vbool2_t vm, vuint8m4_t vd, vuint8m2_t vs2,
vuint8m2_t vs1, size_t vl) {
return __riscv_vzip_vv_u8m4_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vzip_vv_u8m8_tum
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 64 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 64 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
-vuint8m8_t test_vzip_vv_u8m8_tum(vbool2_t vm, vuint8m8_t vd, vuint8m4_t vs2,
+vuint8m8_t test_vzip_vv_u8m8_tum(vbool1_t vm, vuint8m8_t vd, vuint8m4_t vs2,
vuint8m4_t vs1, size_t vl) {
return __riscv_vzip_vv_u8m8_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vzip_vv_u16mf2_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
-vuint16mf2_t test_vzip_vv_u16mf2_tum(vbool64_t vm, vuint16mf2_t vd,
+vuint16mf2_t test_vzip_vv_u16mf2_tum(vbool32_t vm, vuint16mf2_t vd,
vuint16mf4_t vs2, vuint16mf4_t vs1,
size_t vl) {
return __riscv_vzip_vv_u16mf2_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vzip_vv_u16m1_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
-vuint16m1_t test_vzip_vv_u16m1_tum(vbool32_t vm, vuint16m1_t vd,
+vuint16m1_t test_vzip_vv_u16m1_tum(vbool16_t vm, vuint16m1_t vd,
vuint16mf2_t vs2, vuint16mf2_t vs1,
size_t vl) {
return __riscv_vzip_vv_u16m1_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vzip_vv_u16m2_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
-vuint16m2_t test_vzip_vv_u16m2_tum(vbool16_t vm, vuint16m2_t vd,
+vuint16m2_t test_vzip_vv_u16m2_tum(vbool8_t vm, vuint16m2_t vd,
vuint16m1_t vs2, vuint16m1_t vs1,
size_t vl) {
return __riscv_vzip_vv_u16m2_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vzip_vv_u16m4_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
-vuint16m4_t test_vzip_vv_u16m4_tum(vbool8_t vm, vuint16m4_t vd, vuint16m2_t vs2,
+vuint16m4_t test_vzip_vv_u16m4_tum(vbool4_t vm, vuint16m4_t vd, vuint16m2_t vs2,
vuint16m2_t vs1, size_t vl) {
return __riscv_vzip_vv_u16m4_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vzip_vv_u16m8_tum
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
-vuint16m8_t test_vzip_vv_u16m8_tum(vbool4_t vm, vuint16m8_t vd, vuint16m4_t vs2,
+vuint16m8_t test_vzip_vv_u16m8_tum(vbool2_t vm, vuint16m8_t vd, vuint16m4_t vs2,
vuint16m4_t vs1, size_t vl) {
return __riscv_vzip_vv_u16m8_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vzip_vv_u32m1_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vzip_vv_u32m1_tum(vbool64_t vm, vuint32m1_t vd,
+vuint32m1_t test_vzip_vv_u32m1_tum(vbool32_t vm, vuint32m1_t vd,
vuint32mf2_t vs2, vuint32mf2_t vs1,
size_t vl) {
return __riscv_vzip_vv_u32m1_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vzip_vv_u32m2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vzip_vv_u32m2_tum(vbool32_t vm, vuint32m2_t vd,
+vuint32m2_t test_vzip_vv_u32m2_tum(vbool16_t vm, vuint32m2_t vd,
vuint32m1_t vs2, vuint32m1_t vs1,
size_t vl) {
return __riscv_vzip_vv_u32m2_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vzip_vv_u32m4_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vzip_vv_u32m4_tum(vbool16_t vm, vuint32m4_t vd,
+vuint32m4_t test_vzip_vv_u32m4_tum(vbool8_t vm, vuint32m4_t vd,
vuint32m2_t vs2, vuint32m2_t vs1,
size_t vl) {
return __riscv_vzip_vv_u32m4_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vzip_vv_u32m8_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vzip_vv_u32m8_tum(vbool8_t vm, vuint32m8_t vd, vuint32m4_t vs2,
+vuint32m8_t test_vzip_vv_u32m8_tum(vbool4_t vm, vuint32m8_t vd, vuint32m4_t vs2,
vuint32m4_t vs1, size_t vl) {
return __riscv_vzip_vv_u32m8_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vzip_vv_u64m2_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
-vuint64m2_t test_vzip_vv_u64m2_tum(vbool64_t vm, vuint64m2_t vd,
+vuint64m2_t test_vzip_vv_u64m2_tum(vbool32_t vm, vuint64m2_t vd,
vuint64m1_t vs2, vuint64m1_t vs1,
size_t vl) {
return __riscv_vzip_vv_u64m2_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vzip_vv_u64m4_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
-vuint64m4_t test_vzip_vv_u64m4_tum(vbool32_t vm, vuint64m4_t vd,
+vuint64m4_t test_vzip_vv_u64m4_tum(vbool16_t vm, vuint64m4_t vd,
vuint64m2_t vs2, vuint64m2_t vs1,
size_t vl) {
return __riscv_vzip_vv_u64m4_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vzip_vv_u64m8_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
-vuint64m8_t test_vzip_vv_u64m8_tum(vbool16_t vm, vuint64m8_t vd,
+vuint64m8_t test_vzip_vv_u64m8_tum(vbool8_t vm, vuint64m8_t vd,
vuint64m4_t vs2, vuint64m4_t vs1,
size_t vl) {
return __riscv_vzip_vv_u64m8_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vzip_vv_f16mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vzip.mask.nxv2f16.nxv1f16.i64(<vscale x 2 x half> [[VD]], <vscale x 1 x half> [[VS2]], <vscale x 1 x half> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vzip.mask.nxv2f16.nxv1f16.i64(<vscale x 2 x half> [[VD]], <vscale x 1 x half> [[VS2]], <vscale x 1 x half> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
-vfloat16mf2_t test_vzip_vv_f16mf2_tumu(vbool64_t vm, vfloat16mf2_t vd,
+vfloat16mf2_t test_vzip_vv_f16mf2_tumu(vbool32_t vm, vfloat16mf2_t vd,
vfloat16mf4_t vs2, vfloat16mf4_t vs1,
size_t vl) {
return __riscv_vzip_vv_f16mf2_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vzip_vv_f16m1_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vzip.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[VD]], <vscale x 2 x half> [[VS2]], <vscale x 2 x half> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vzip.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[VD]], <vscale x 2 x half> [[VS2]], <vscale x 2 x half> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
-vfloat16m1_t test_vzip_vv_f16m1_tumu(vbool32_t vm, vfloat16m1_t vd,
+vfloat16m1_t test_vzip_vv_f16m1_tumu(vbool16_t vm, vfloat16m1_t vd,
vfloat16mf2_t vs2, vfloat16mf2_t vs1,
size_t vl) {
return __riscv_vzip_vv_f16m1_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vzip_vv_f16m2_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vzip.mask.nxv8f16.nxv4f16.i64(<vscale x 8 x half> [[VD]], <vscale x 4 x half> [[VS2]], <vscale x 4 x half> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vzip.mask.nxv8f16.nxv4f16.i64(<vscale x 8 x half> [[VD]], <vscale x 4 x half> [[VS2]], <vscale x 4 x half> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
-vfloat16m2_t test_vzip_vv_f16m2_tumu(vbool16_t vm, vfloat16m2_t vd,
+vfloat16m2_t test_vzip_vv_f16m2_tumu(vbool8_t vm, vfloat16m2_t vd,
vfloat16m1_t vs2, vfloat16m1_t vs1,
size_t vl) {
return __riscv_vzip_vv_f16m2_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vzip_vv_f16m4_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vzip.mask.nxv16f16.nxv8f16.i64(<vscale x 16 x half> [[VD]], <vscale x 8 x half> [[VS2]], <vscale x 8 x half> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vzip.mask.nxv16f16.nxv8f16.i64(<vscale x 16 x half> [[VD]], <vscale x 8 x half> [[VS2]], <vscale x 8 x half> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
-vfloat16m4_t test_vzip_vv_f16m4_tumu(vbool8_t vm, vfloat16m4_t vd,
+vfloat16m4_t test_vzip_vv_f16m4_tumu(vbool4_t vm, vfloat16m4_t vd,
vfloat16m2_t vs2, vfloat16m2_t vs1,
size_t vl) {
return __riscv_vzip_vv_f16m4_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vzip_vv_f16m8_tumu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vzip.mask.nxv32f16.nxv16f16.i64(<vscale x 32 x half> [[VD]], <vscale x 16 x half> [[VS2]], <vscale x 16 x half> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vzip.mask.nxv32f16.nxv16f16.i64(<vscale x 32 x half> [[VD]], <vscale x 16 x half> [[VS2]], <vscale x 16 x half> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
-vfloat16m8_t test_vzip_vv_f16m8_tumu(vbool4_t vm, vfloat16m8_t vd,
+vfloat16m8_t test_vzip_vv_f16m8_tumu(vbool2_t vm, vfloat16m8_t vd,
vfloat16m4_t vs2, vfloat16m4_t vs1,
size_t vl) {
return __riscv_vzip_vv_f16m8_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vzip_vv_f32m1_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 1 x float> [[VS2:%.*]], <vscale x 1 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 1 x float> [[VS2:%.*]], <vscale x 1 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vzip.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[VD]], <vscale x 1 x float> [[VS2]], <vscale x 1 x float> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vzip.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[VD]], <vscale x 1 x float> [[VS2]], <vscale x 1 x float> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
-vfloat32m1_t test_vzip_vv_f32m1_tumu(vbool64_t vm, vfloat32m1_t vd,
+vfloat32m1_t test_vzip_vv_f32m1_tumu(vbool32_t vm, vfloat32m1_t vd,
vfloat32mf2_t vs2, vfloat32mf2_t vs1,
size_t vl) {
return __riscv_vzip_vv_f32m1_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vzip_vv_f32m2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 2 x float> [[VS2:%.*]], <vscale x 2 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 2 x float> [[VS2:%.*]], <vscale x 2 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vzip.mask.nxv4f32.nxv2f32.i64(<vscale x 4 x float> [[VD]], <vscale x 2 x float> [[VS2]], <vscale x 2 x float> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vzip.mask.nxv4f32.nxv2f32.i64(<vscale x 4 x float> [[VD]], <vscale x 2 x float> [[VS2]], <vscale x 2 x float> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
-vfloat32m2_t test_vzip_vv_f32m2_tumu(vbool32_t vm, vfloat32m2_t vd,
+vfloat32m2_t test_vzip_vv_f32m2_tumu(vbool16_t vm, vfloat32m2_t vd,
vfloat32m1_t vs2, vfloat32m1_t vs1,
size_t vl) {
return __riscv_vzip_vv_f32m2_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vzip_vv_f32m4_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 4 x float> [[VS2:%.*]], <vscale x 4 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 4 x float> [[VS2:%.*]], <vscale x 4 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vzip.mask.nxv8f32.nxv4f32.i64(<vscale x 8 x float> [[VD]], <vscale x 4 x float> [[VS2]], <vscale x 4 x float> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vzip.mask.nxv8f32.nxv4f32.i64(<vscale x 8 x float> [[VD]], <vscale x 4 x float> [[VS2]], <vscale x 4 x float> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
-vfloat32m4_t test_vzip_vv_f32m4_tumu(vbool16_t vm, vfloat32m4_t vd,
+vfloat32m4_t test_vzip_vv_f32m4_tumu(vbool8_t vm, vfloat32m4_t vd,
vfloat32m2_t vs2, vfloat32m2_t vs1,
size_t vl) {
return __riscv_vzip_vv_f32m4_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vzip_vv_f32m8_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 8 x float> [[VS2:%.*]], <vscale x 8 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 8 x float> [[VS2:%.*]], <vscale x 8 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vzip.mask.nxv16f32.nxv8f32.i64(<vscale x 16 x float> [[VD]], <vscale x 8 x float> [[VS2]], <vscale x 8 x float> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vzip.mask.nxv16f32.nxv8f32.i64(<vscale x 16 x float> [[VD]], <vscale x 8 x float> [[VS2]], <vscale x 8 x float> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
-vfloat32m8_t test_vzip_vv_f32m8_tumu(vbool8_t vm, vfloat32m8_t vd,
+vfloat32m8_t test_vzip_vv_f32m8_tumu(vbool4_t vm, vfloat32m8_t vd,
vfloat32m4_t vs2, vfloat32m4_t vs1,
size_t vl) {
return __riscv_vzip_vv_f32m8_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vzip_vv_f64m2_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 1 x double> [[VS2:%.*]], <vscale x 1 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 1 x double> [[VS2:%.*]], <vscale x 1 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vzip.mask.nxv2f64.nxv1f64.i64(<vscale x 2 x double> [[VD]], <vscale x 1 x double> [[VS2]], <vscale x 1 x double> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vzip.mask.nxv2f64.nxv1f64.i64(<vscale x 2 x double> [[VD]], <vscale x 1 x double> [[VS2]], <vscale x 1 x double> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
-vfloat64m2_t test_vzip_vv_f64m2_tumu(vbool64_t vm, vfloat64m2_t vd,
+vfloat64m2_t test_vzip_vv_f64m2_tumu(vbool32_t vm, vfloat64m2_t vd,
vfloat64m1_t vs2, vfloat64m1_t vs1,
size_t vl) {
return __riscv_vzip_vv_f64m2_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vzip_vv_f64m4_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 2 x double> [[VS2:%.*]], <vscale x 2 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 2 x double> [[VS2:%.*]], <vscale x 2 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vzip.mask.nxv4f64.nxv2f64.i64(<vscale x 4 x double> [[VD]], <vscale x 2 x double> [[VS2]], <vscale x 2 x double> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vzip.mask.nxv4f64.nxv2f64.i64(<vscale x 4 x double> [[VD]], <vscale x 2 x double> [[VS2]], <vscale x 2 x double> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
-vfloat64m4_t test_vzip_vv_f64m4_tumu(vbool32_t vm, vfloat64m4_t vd,
+vfloat64m4_t test_vzip_vv_f64m4_tumu(vbool16_t vm, vfloat64m4_t vd,
vfloat64m2_t vs2, vfloat64m2_t vs1,
size_t vl) {
return __riscv_vzip_vv_f64m4_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vzip_vv_f64m8_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 4 x double> [[VS2:%.*]], <vscale x 4 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 4 x double> [[VS2:%.*]], <vscale x 4 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vzip.mask.nxv8f64.nxv4f64.i64(<vscale x 8 x double> [[VD]], <vscale x 4 x double> [[VS2]], <vscale x 4 x double> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vzip.mask.nxv8f64.nxv4f64.i64(<vscale x 8 x double> [[VD]], <vscale x 4 x double> [[VS2]], <vscale x 4 x double> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
-vfloat64m8_t test_vzip_vv_f64m8_tumu(vbool16_t vm, vfloat64m8_t vd,
+vfloat64m8_t test_vzip_vv_f64m8_tumu(vbool8_t vm, vfloat64m8_t vd,
vfloat64m4_t vs2, vfloat64m4_t vs1,
size_t vl) {
return __riscv_vzip_vv_f64m8_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vzip_vv_i8mf4_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
-vint8mf4_t test_vzip_vv_i8mf4_tumu(vbool64_t vm, vint8mf4_t vd, vint8mf8_t vs2,
+vint8mf4_t test_vzip_vv_i8mf4_tumu(vbool32_t vm, vint8mf4_t vd, vint8mf8_t vs2,
vint8mf8_t vs1, size_t vl) {
return __riscv_vzip_vv_i8mf4_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vzip_vv_i8mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
-vint8mf2_t test_vzip_vv_i8mf2_tumu(vbool32_t vm, vint8mf2_t vd, vint8mf4_t vs2,
+vint8mf2_t test_vzip_vv_i8mf2_tumu(vbool16_t vm, vint8mf2_t vd, vint8mf4_t vs2,
vint8mf4_t vs1, size_t vl) {
return __riscv_vzip_vv_i8mf2_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vzip_vv_i8m1_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
-vint8m1_t test_vzip_vv_i8m1_tumu(vbool16_t vm, vint8m1_t vd, vint8mf2_t vs2,
+vint8m1_t test_vzip_vv_i8m1_tumu(vbool8_t vm, vint8m1_t vd, vint8mf2_t vs2,
vint8mf2_t vs1, size_t vl) {
return __riscv_vzip_vv_i8m1_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vzip_vv_i8m2_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
-vint8m2_t test_vzip_vv_i8m2_tumu(vbool8_t vm, vint8m2_t vd, vint8m1_t vs2,
+vint8m2_t test_vzip_vv_i8m2_tumu(vbool4_t vm, vint8m2_t vd, vint8m1_t vs2,
vint8m1_t vs1, size_t vl) {
return __riscv_vzip_vv_i8m2_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vzip_vv_i8m4_tumu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
-vint8m4_t test_vzip_vv_i8m4_tumu(vbool4_t vm, vint8m4_t vd, vint8m2_t vs2,
+vint8m4_t test_vzip_vv_i8m4_tumu(vbool2_t vm, vint8m4_t vd, vint8m2_t vs2,
vint8m2_t vs1, size_t vl) {
return __riscv_vzip_vv_i8m4_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vzip_vv_i8m8_tumu
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 64 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 64 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
-vint8m8_t test_vzip_vv_i8m8_tumu(vbool2_t vm, vint8m8_t vd, vint8m4_t vs2,
+vint8m8_t test_vzip_vv_i8m8_tumu(vbool1_t vm, vint8m8_t vd, vint8m4_t vs2,
vint8m4_t vs1, size_t vl) {
return __riscv_vzip_vv_i8m8_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vzip_vv_i16mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
-vint16mf2_t test_vzip_vv_i16mf2_tumu(vbool64_t vm, vint16mf2_t vd,
+vint16mf2_t test_vzip_vv_i16mf2_tumu(vbool32_t vm, vint16mf2_t vd,
vint16mf4_t vs2, vint16mf4_t vs1,
size_t vl) {
return __riscv_vzip_vv_i16mf2_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vzip_vv_i16m1_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
-vint16m1_t test_vzip_vv_i16m1_tumu(vbool32_t vm, vint16m1_t vd, vint16mf2_t vs2,
+vint16m1_t test_vzip_vv_i16m1_tumu(vbool16_t vm, vint16m1_t vd, vint16mf2_t vs2,
vint16mf2_t vs1, size_t vl) {
return __riscv_vzip_vv_i16m1_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vzip_vv_i16m2_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
-vint16m2_t test_vzip_vv_i16m2_tumu(vbool16_t vm, vint16m2_t vd, vint16m1_t vs2,
+vint16m2_t test_vzip_vv_i16m2_tumu(vbool8_t vm, vint16m2_t vd, vint16m1_t vs2,
vint16m1_t vs1, size_t vl) {
return __riscv_vzip_vv_i16m2_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vzip_vv_i16m4_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
-vint16m4_t test_vzip_vv_i16m4_tumu(vbool8_t vm, vint16m4_t vd, vint16m2_t vs2,
+vint16m4_t test_vzip_vv_i16m4_tumu(vbool4_t vm, vint16m4_t vd, vint16m2_t vs2,
vint16m2_t vs1, size_t vl) {
return __riscv_vzip_vv_i16m4_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vzip_vv_i16m8_tumu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
-vint16m8_t test_vzip_vv_i16m8_tumu(vbool4_t vm, vint16m8_t vd, vint16m4_t vs2,
+vint16m8_t test_vzip_vv_i16m8_tumu(vbool2_t vm, vint16m8_t vd, vint16m4_t vs2,
vint16m4_t vs1, size_t vl) {
return __riscv_vzip_vv_i16m8_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vzip_vv_i32m1_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vzip_vv_i32m1_tumu(vbool64_t vm, vint32m1_t vd, vint32mf2_t vs2,
+vint32m1_t test_vzip_vv_i32m1_tumu(vbool32_t vm, vint32m1_t vd, vint32mf2_t vs2,
vint32mf2_t vs1, size_t vl) {
return __riscv_vzip_vv_i32m1_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vzip_vv_i32m2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vzip_vv_i32m2_tumu(vbool32_t vm, vint32m2_t vd, vint32m1_t vs2,
+vint32m2_t test_vzip_vv_i32m2_tumu(vbool16_t vm, vint32m2_t vd, vint32m1_t vs2,
vint32m1_t vs1, size_t vl) {
return __riscv_vzip_vv_i32m2_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vzip_vv_i32m4_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vzip_vv_i32m4_tumu(vbool16_t vm, vint32m4_t vd, vint32m2_t vs2,
+vint32m4_t test_vzip_vv_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vint32m2_t vs2,
vint32m2_t vs1, size_t vl) {
return __riscv_vzip_vv_i32m4_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vzip_vv_i32m8_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vzip_vv_i32m8_tumu(vbool8_t vm, vint32m8_t vd, vint32m4_t vs2,
+vint32m8_t test_vzip_vv_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vint32m4_t vs2,
vint32m4_t vs1, size_t vl) {
return __riscv_vzip_vv_i32m8_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vzip_vv_i64m2_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
-vint64m2_t test_vzip_vv_i64m2_tumu(vbool64_t vm, vint64m2_t vd, vint64m1_t vs2,
+vint64m2_t test_vzip_vv_i64m2_tumu(vbool32_t vm, vint64m2_t vd, vint64m1_t vs2,
vint64m1_t vs1, size_t vl) {
return __riscv_vzip_vv_i64m2_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vzip_vv_i64m4_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
-vint64m4_t test_vzip_vv_i64m4_tumu(vbool32_t vm, vint64m4_t vd, vint64m2_t vs2,
+vint64m4_t test_vzip_vv_i64m4_tumu(vbool16_t vm, vint64m4_t vd, vint64m2_t vs2,
vint64m2_t vs1, size_t vl) {
return __riscv_vzip_vv_i64m4_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vzip_vv_i64m8_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
-vint64m8_t test_vzip_vv_i64m8_tumu(vbool16_t vm, vint64m8_t vd, vint64m4_t vs2,
+vint64m8_t test_vzip_vv_i64m8_tumu(vbool8_t vm, vint64m8_t vd, vint64m4_t vs2,
vint64m4_t vs1, size_t vl) {
return __riscv_vzip_vv_i64m8_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vzip_vv_u8mf4_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
-vuint8mf4_t test_vzip_vv_u8mf4_tumu(vbool64_t vm, vuint8mf4_t vd,
+vuint8mf4_t test_vzip_vv_u8mf4_tumu(vbool32_t vm, vuint8mf4_t vd,
vuint8mf8_t vs2, vuint8mf8_t vs1,
size_t vl) {
return __riscv_vzip_vv_u8mf4_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vzip_vv_u8mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
-vuint8mf2_t test_vzip_vv_u8mf2_tumu(vbool32_t vm, vuint8mf2_t vd,
+vuint8mf2_t test_vzip_vv_u8mf2_tumu(vbool16_t vm, vuint8mf2_t vd,
vuint8mf4_t vs2, vuint8mf4_t vs1,
size_t vl) {
return __riscv_vzip_vv_u8mf2_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vzip_vv_u8m1_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
-vuint8m1_t test_vzip_vv_u8m1_tumu(vbool16_t vm, vuint8m1_t vd, vuint8mf2_t vs2,
+vuint8m1_t test_vzip_vv_u8m1_tumu(vbool8_t vm, vuint8m1_t vd, vuint8mf2_t vs2,
vuint8mf2_t vs1, size_t vl) {
return __riscv_vzip_vv_u8m1_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vzip_vv_u8m2_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
-vuint8m2_t test_vzip_vv_u8m2_tumu(vbool8_t vm, vuint8m2_t vd, vuint8m1_t vs2,
+vuint8m2_t test_vzip_vv_u8m2_tumu(vbool4_t vm, vuint8m2_t vd, vuint8m1_t vs2,
vuint8m1_t vs1, size_t vl) {
return __riscv_vzip_vv_u8m2_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vzip_vv_u8m4_tumu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
-vuint8m4_t test_vzip_vv_u8m4_tumu(vbool4_t vm, vuint8m4_t vd, vuint8m2_t vs2,
+vuint8m4_t test_vzip_vv_u8m4_tumu(vbool2_t vm, vuint8m4_t vd, vuint8m2_t vs2,
vuint8m2_t vs1, size_t vl) {
return __riscv_vzip_vv_u8m4_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vzip_vv_u8m8_tumu
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 64 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 64 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
-vuint8m8_t test_vzip_vv_u8m8_tumu(vbool2_t vm, vuint8m8_t vd, vuint8m4_t vs2,
+vuint8m8_t test_vzip_vv_u8m8_tumu(vbool1_t vm, vuint8m8_t vd, vuint8m4_t vs2,
vuint8m4_t vs1, size_t vl) {
return __riscv_vzip_vv_u8m8_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vzip_vv_u16mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
-vuint16mf2_t test_vzip_vv_u16mf2_tumu(vbool64_t vm, vuint16mf2_t vd,
+vuint16mf2_t test_vzip_vv_u16mf2_tumu(vbool32_t vm, vuint16mf2_t vd,
vuint16mf4_t vs2, vuint16mf4_t vs1,
size_t vl) {
return __riscv_vzip_vv_u16mf2_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vzip_vv_u16m1_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
-vuint16m1_t test_vzip_vv_u16m1_tumu(vbool32_t vm, vuint16m1_t vd,
+vuint16m1_t test_vzip_vv_u16m1_tumu(vbool16_t vm, vuint16m1_t vd,
vuint16mf2_t vs2, vuint16mf2_t vs1,
size_t vl) {
return __riscv_vzip_vv_u16m1_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vzip_vv_u16m2_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
-vuint16m2_t test_vzip_vv_u16m2_tumu(vbool16_t vm, vuint16m2_t vd,
+vuint16m2_t test_vzip_vv_u16m2_tumu(vbool8_t vm, vuint16m2_t vd,
vuint16m1_t vs2, vuint16m1_t vs1,
size_t vl) {
return __riscv_vzip_vv_u16m2_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vzip_vv_u16m4_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
-vuint16m4_t test_vzip_vv_u16m4_tumu(vbool8_t vm, vuint16m4_t vd,
+vuint16m4_t test_vzip_vv_u16m4_tumu(vbool4_t vm, vuint16m4_t vd,
vuint16m2_t vs2, vuint16m2_t vs1,
size_t vl) {
return __riscv_vzip_vv_u16m4_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vzip_vv_u16m8_tumu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
-vuint16m8_t test_vzip_vv_u16m8_tumu(vbool4_t vm, vuint16m8_t vd,
+vuint16m8_t test_vzip_vv_u16m8_tumu(vbool2_t vm, vuint16m8_t vd,
vuint16m4_t vs2, vuint16m4_t vs1,
size_t vl) {
return __riscv_vzip_vv_u16m8_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vzip_vv_u32m1_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vzip_vv_u32m1_tumu(vbool64_t vm, vuint32m1_t vd,
+vuint32m1_t test_vzip_vv_u32m1_tumu(vbool32_t vm, vuint32m1_t vd,
vuint32mf2_t vs2, vuint32mf2_t vs1,
size_t vl) {
return __riscv_vzip_vv_u32m1_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vzip_vv_u32m2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vzip_vv_u32m2_tumu(vbool32_t vm, vuint32m2_t vd,
+vuint32m2_t test_vzip_vv_u32m2_tumu(vbool16_t vm, vuint32m2_t vd,
vuint32m1_t vs2, vuint32m1_t vs1,
size_t vl) {
return __riscv_vzip_vv_u32m2_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vzip_vv_u32m4_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vzip_vv_u32m4_tumu(vbool16_t vm, vuint32m4_t vd,
+vuint32m4_t test_vzip_vv_u32m4_tumu(vbool8_t vm, vuint32m4_t vd,
vuint32m2_t vs2, vuint32m2_t vs1,
size_t vl) {
return __riscv_vzip_vv_u32m4_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vzip_vv_u32m8_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vzip_vv_u32m8_tumu(vbool8_t vm, vuint32m8_t vd,
+vuint32m8_t test_vzip_vv_u32m8_tumu(vbool4_t vm, vuint32m8_t vd,
vuint32m4_t vs2, vuint32m4_t vs1,
size_t vl) {
return __riscv_vzip_vv_u32m8_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vzip_vv_u64m2_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
-vuint64m2_t test_vzip_vv_u64m2_tumu(vbool64_t vm, vuint64m2_t vd,
+vuint64m2_t test_vzip_vv_u64m2_tumu(vbool32_t vm, vuint64m2_t vd,
vuint64m1_t vs2, vuint64m1_t vs1,
size_t vl) {
return __riscv_vzip_vv_u64m2_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vzip_vv_u64m4_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
-vuint64m4_t test_vzip_vv_u64m4_tumu(vbool32_t vm, vuint64m4_t vd,
+vuint64m4_t test_vzip_vv_u64m4_tumu(vbool16_t vm, vuint64m4_t vd,
vuint64m2_t vs2, vuint64m2_t vs1,
size_t vl) {
return __riscv_vzip_vv_u64m4_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vzip_vv_u64m8_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
-vuint64m8_t test_vzip_vv_u64m8_tumu(vbool16_t vm, vuint64m8_t vd,
+vuint64m8_t test_vzip_vv_u64m8_tumu(vbool8_t vm, vuint64m8_t vd,
vuint64m4_t vs2, vuint64m4_t vs1,
size_t vl) {
return __riscv_vzip_vv_u64m8_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vzip_vv_f16mf2_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vzip.mask.nxv2f16.nxv1f16.i64(<vscale x 2 x half> [[VD]], <vscale x 1 x half> [[VS2]], <vscale x 1 x half> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vzip.mask.nxv2f16.nxv1f16.i64(<vscale x 2 x half> [[VD]], <vscale x 1 x half> [[VS2]], <vscale x 1 x half> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
-vfloat16mf2_t test_vzip_vv_f16mf2_mu(vbool64_t vm, vfloat16mf2_t vd,
+vfloat16mf2_t test_vzip_vv_f16mf2_mu(vbool32_t vm, vfloat16mf2_t vd,
vfloat16mf4_t vs2, vfloat16mf4_t vs1,
size_t vl) {
return __riscv_vzip_vv_f16mf2_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vzip_vv_f16m1_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vzip.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[VD]], <vscale x 2 x half> [[VS2]], <vscale x 2 x half> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vzip.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[VD]], <vscale x 2 x half> [[VS2]], <vscale x 2 x half> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
-vfloat16m1_t test_vzip_vv_f16m1_mu(vbool32_t vm, vfloat16m1_t vd,
+vfloat16m1_t test_vzip_vv_f16m1_mu(vbool16_t vm, vfloat16m1_t vd,
vfloat16mf2_t vs2, vfloat16mf2_t vs1,
size_t vl) {
return __riscv_vzip_vv_f16m1_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vzip_vv_f16m2_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vzip.mask.nxv8f16.nxv4f16.i64(<vscale x 8 x half> [[VD]], <vscale x 4 x half> [[VS2]], <vscale x 4 x half> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vzip.mask.nxv8f16.nxv4f16.i64(<vscale x 8 x half> [[VD]], <vscale x 4 x half> [[VS2]], <vscale x 4 x half> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
-vfloat16m2_t test_vzip_vv_f16m2_mu(vbool16_t vm, vfloat16m2_t vd,
+vfloat16m2_t test_vzip_vv_f16m2_mu(vbool8_t vm, vfloat16m2_t vd,
vfloat16m1_t vs2, vfloat16m1_t vs1,
size_t vl) {
return __riscv_vzip_vv_f16m2_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vzip_vv_f16m4_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vzip.mask.nxv16f16.nxv8f16.i64(<vscale x 16 x half> [[VD]], <vscale x 8 x half> [[VS2]], <vscale x 8 x half> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vzip.mask.nxv16f16.nxv8f16.i64(<vscale x 16 x half> [[VD]], <vscale x 8 x half> [[VS2]], <vscale x 8 x half> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
-vfloat16m4_t test_vzip_vv_f16m4_mu(vbool8_t vm, vfloat16m4_t vd,
+vfloat16m4_t test_vzip_vv_f16m4_mu(vbool4_t vm, vfloat16m4_t vd,
vfloat16m2_t vs2, vfloat16m2_t vs1,
size_t vl) {
return __riscv_vzip_vv_f16m4_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vzip_vv_f16m8_mu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vzip.mask.nxv32f16.nxv16f16.i64(<vscale x 32 x half> [[VD]], <vscale x 16 x half> [[VS2]], <vscale x 16 x half> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vzip.mask.nxv32f16.nxv16f16.i64(<vscale x 32 x half> [[VD]], <vscale x 16 x half> [[VS2]], <vscale x 16 x half> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
-vfloat16m8_t test_vzip_vv_f16m8_mu(vbool4_t vm, vfloat16m8_t vd,
+vfloat16m8_t test_vzip_vv_f16m8_mu(vbool2_t vm, vfloat16m8_t vd,
vfloat16m4_t vs2, vfloat16m4_t vs1,
size_t vl) {
return __riscv_vzip_vv_f16m8_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vzip_vv_f32m1_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 1 x float> [[VS2:%.*]], <vscale x 1 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 1 x float> [[VS2:%.*]], <vscale x 1 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vzip.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[VD]], <vscale x 1 x float> [[VS2]], <vscale x 1 x float> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vzip.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[VD]], <vscale x 1 x float> [[VS2]], <vscale x 1 x float> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
-vfloat32m1_t test_vzip_vv_f32m1_mu(vbool64_t vm, vfloat32m1_t vd,
+vfloat32m1_t test_vzip_vv_f32m1_mu(vbool32_t vm, vfloat32m1_t vd,
vfloat32mf2_t vs2, vfloat32mf2_t vs1,
size_t vl) {
return __riscv_vzip_vv_f32m1_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vzip_vv_f32m2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 2 x float> [[VS2:%.*]], <vscale x 2 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 2 x float> [[VS2:%.*]], <vscale x 2 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vzip.mask.nxv4f32.nxv2f32.i64(<vscale x 4 x float> [[VD]], <vscale x 2 x float> [[VS2]], <vscale x 2 x float> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vzip.mask.nxv4f32.nxv2f32.i64(<vscale x 4 x float> [[VD]], <vscale x 2 x float> [[VS2]], <vscale x 2 x float> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
-vfloat32m2_t test_vzip_vv_f32m2_mu(vbool32_t vm, vfloat32m2_t vd,
+vfloat32m2_t test_vzip_vv_f32m2_mu(vbool16_t vm, vfloat32m2_t vd,
vfloat32m1_t vs2, vfloat32m1_t vs1,
size_t vl) {
return __riscv_vzip_vv_f32m2_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vzip_vv_f32m4_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 4 x float> [[VS2:%.*]], <vscale x 4 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 4 x float> [[VS2:%.*]], <vscale x 4 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vzip.mask.nxv8f32.nxv4f32.i64(<vscale x 8 x float> [[VD]], <vscale x 4 x float> [[VS2]], <vscale x 4 x float> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vzip.mask.nxv8f32.nxv4f32.i64(<vscale x 8 x float> [[VD]], <vscale x 4 x float> [[VS2]], <vscale x 4 x float> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
-vfloat32m4_t test_vzip_vv_f32m4_mu(vbool16_t vm, vfloat32m4_t vd,
+vfloat32m4_t test_vzip_vv_f32m4_mu(vbool8_t vm, vfloat32m4_t vd,
vfloat32m2_t vs2, vfloat32m2_t vs1,
size_t vl) {
return __riscv_vzip_vv_f32m4_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vzip_vv_f32m8_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 8 x float> [[VS2:%.*]], <vscale x 8 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 8 x float> [[VS2:%.*]], <vscale x 8 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vzip.mask.nxv16f32.nxv8f32.i64(<vscale x 16 x float> [[VD]], <vscale x 8 x float> [[VS2]], <vscale x 8 x float> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vzip.mask.nxv16f32.nxv8f32.i64(<vscale x 16 x float> [[VD]], <vscale x 8 x float> [[VS2]], <vscale x 8 x float> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
-vfloat32m8_t test_vzip_vv_f32m8_mu(vbool8_t vm, vfloat32m8_t vd,
+vfloat32m8_t test_vzip_vv_f32m8_mu(vbool4_t vm, vfloat32m8_t vd,
vfloat32m4_t vs2, vfloat32m4_t vs1,
size_t vl) {
return __riscv_vzip_vv_f32m8_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vzip_vv_f64m2_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 1 x double> [[VS2:%.*]], <vscale x 1 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 1 x double> [[VS2:%.*]], <vscale x 1 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vzip.mask.nxv2f64.nxv1f64.i64(<vscale x 2 x double> [[VD]], <vscale x 1 x double> [[VS2]], <vscale x 1 x double> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vzip.mask.nxv2f64.nxv1f64.i64(<vscale x 2 x double> [[VD]], <vscale x 1 x double> [[VS2]], <vscale x 1 x double> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
-vfloat64m2_t test_vzip_vv_f64m2_mu(vbool64_t vm, vfloat64m2_t vd,
+vfloat64m2_t test_vzip_vv_f64m2_mu(vbool32_t vm, vfloat64m2_t vd,
vfloat64m1_t vs2, vfloat64m1_t vs1,
size_t vl) {
return __riscv_vzip_vv_f64m2_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vzip_vv_f64m4_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 2 x double> [[VS2:%.*]], <vscale x 2 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 2 x double> [[VS2:%.*]], <vscale x 2 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vzip.mask.nxv4f64.nxv2f64.i64(<vscale x 4 x double> [[VD]], <vscale x 2 x double> [[VS2]], <vscale x 2 x double> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vzip.mask.nxv4f64.nxv2f64.i64(<vscale x 4 x double> [[VD]], <vscale x 2 x double> [[VS2]], <vscale x 2 x double> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
-vfloat64m4_t test_vzip_vv_f64m4_mu(vbool32_t vm, vfloat64m4_t vd,
+vfloat64m4_t test_vzip_vv_f64m4_mu(vbool16_t vm, vfloat64m4_t vd,
vfloat64m2_t vs2, vfloat64m2_t vs1,
size_t vl) {
return __riscv_vzip_vv_f64m4_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vzip_vv_f64m8_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 4 x double> [[VS2:%.*]], <vscale x 4 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 4 x double> [[VS2:%.*]], <vscale x 4 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vzip.mask.nxv8f64.nxv4f64.i64(<vscale x 8 x double> [[VD]], <vscale x 4 x double> [[VS2]], <vscale x 4 x double> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vzip.mask.nxv8f64.nxv4f64.i64(<vscale x 8 x double> [[VD]], <vscale x 4 x double> [[VS2]], <vscale x 4 x double> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
-vfloat64m8_t test_vzip_vv_f64m8_mu(vbool16_t vm, vfloat64m8_t vd,
+vfloat64m8_t test_vzip_vv_f64m8_mu(vbool8_t vm, vfloat64m8_t vd,
vfloat64m4_t vs2, vfloat64m4_t vs1,
size_t vl) {
return __riscv_vzip_vv_f64m8_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vzip_vv_i8mf4_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
-vint8mf4_t test_vzip_vv_i8mf4_mu(vbool64_t vm, vint8mf4_t vd, vint8mf8_t vs2,
+vint8mf4_t test_vzip_vv_i8mf4_mu(vbool32_t vm, vint8mf4_t vd, vint8mf8_t vs2,
vint8mf8_t vs1, size_t vl) {
return __riscv_vzip_vv_i8mf4_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vzip_vv_i8mf2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
-vint8mf2_t test_vzip_vv_i8mf2_mu(vbool32_t vm, vint8mf2_t vd, vint8mf4_t vs2,
+vint8mf2_t test_vzip_vv_i8mf2_mu(vbool16_t vm, vint8mf2_t vd, vint8mf4_t vs2,
vint8mf4_t vs1, size_t vl) {
return __riscv_vzip_vv_i8mf2_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vzip_vv_i8m1_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
-vint8m1_t test_vzip_vv_i8m1_mu(vbool16_t vm, vint8m1_t vd, vint8mf2_t vs2,
+vint8m1_t test_vzip_vv_i8m1_mu(vbool8_t vm, vint8m1_t vd, vint8mf2_t vs2,
vint8mf2_t vs1, size_t vl) {
return __riscv_vzip_vv_i8m1_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vzip_vv_i8m2_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
-vint8m2_t test_vzip_vv_i8m2_mu(vbool8_t vm, vint8m2_t vd, vint8m1_t vs2,
+vint8m2_t test_vzip_vv_i8m2_mu(vbool4_t vm, vint8m2_t vd, vint8m1_t vs2,
vint8m1_t vs1, size_t vl) {
return __riscv_vzip_vv_i8m2_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vzip_vv_i8m4_mu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
-vint8m4_t test_vzip_vv_i8m4_mu(vbool4_t vm, vint8m4_t vd, vint8m2_t vs2,
+vint8m4_t test_vzip_vv_i8m4_mu(vbool2_t vm, vint8m4_t vd, vint8m2_t vs2,
vint8m2_t vs1, size_t vl) {
return __riscv_vzip_vv_i8m4_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vzip_vv_i8m8_mu
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 64 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 64 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
-vint8m8_t test_vzip_vv_i8m8_mu(vbool2_t vm, vint8m8_t vd, vint8m4_t vs2,
+vint8m8_t test_vzip_vv_i8m8_mu(vbool1_t vm, vint8m8_t vd, vint8m4_t vs2,
vint8m4_t vs1, size_t vl) {
return __riscv_vzip_vv_i8m8_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vzip_vv_i16mf2_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
-vint16mf2_t test_vzip_vv_i16mf2_mu(vbool64_t vm, vint16mf2_t vd,
+vint16mf2_t test_vzip_vv_i16mf2_mu(vbool32_t vm, vint16mf2_t vd,
vint16mf4_t vs2, vint16mf4_t vs1,
size_t vl) {
return __riscv_vzip_vv_i16mf2_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vzip_vv_i16m1_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
-vint16m1_t test_vzip_vv_i16m1_mu(vbool32_t vm, vint16m1_t vd, vint16mf2_t vs2,
+vint16m1_t test_vzip_vv_i16m1_mu(vbool16_t vm, vint16m1_t vd, vint16mf2_t vs2,
vint16mf2_t vs1, size_t vl) {
return __riscv_vzip_vv_i16m1_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vzip_vv_i16m2_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
-vint16m2_t test_vzip_vv_i16m2_mu(vbool16_t vm, vint16m2_t vd, vint16m1_t vs2,
+vint16m2_t test_vzip_vv_i16m2_mu(vbool8_t vm, vint16m2_t vd, vint16m1_t vs2,
vint16m1_t vs1, size_t vl) {
return __riscv_vzip_vv_i16m2_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vzip_vv_i16m4_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
-vint16m4_t test_vzip_vv_i16m4_mu(vbool8_t vm, vint16m4_t vd, vint16m2_t vs2,
+vint16m4_t test_vzip_vv_i16m4_mu(vbool4_t vm, vint16m4_t vd, vint16m2_t vs2,
vint16m2_t vs1, size_t vl) {
return __riscv_vzip_vv_i16m4_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vzip_vv_i16m8_mu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
-vint16m8_t test_vzip_vv_i16m8_mu(vbool4_t vm, vint16m8_t vd, vint16m4_t vs2,
+vint16m8_t test_vzip_vv_i16m8_mu(vbool2_t vm, vint16m8_t vd, vint16m4_t vs2,
vint16m4_t vs1, size_t vl) {
return __riscv_vzip_vv_i16m8_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vzip_vv_i32m1_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vzip_vv_i32m1_mu(vbool64_t vm, vint32m1_t vd, vint32mf2_t vs2,
+vint32m1_t test_vzip_vv_i32m1_mu(vbool32_t vm, vint32m1_t vd, vint32mf2_t vs2,
vint32mf2_t vs1, size_t vl) {
return __riscv_vzip_vv_i32m1_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vzip_vv_i32m2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vzip_vv_i32m2_mu(vbool32_t vm, vint32m2_t vd, vint32m1_t vs2,
+vint32m2_t test_vzip_vv_i32m2_mu(vbool16_t vm, vint32m2_t vd, vint32m1_t vs2,
vint32m1_t vs1, size_t vl) {
return __riscv_vzip_vv_i32m2_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vzip_vv_i32m4_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vzip_vv_i32m4_mu(vbool16_t vm, vint32m4_t vd, vint32m2_t vs2,
+vint32m4_t test_vzip_vv_i32m4_mu(vbool8_t vm, vint32m4_t vd, vint32m2_t vs2,
vint32m2_t vs1, size_t vl) {
return __riscv_vzip_vv_i32m4_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vzip_vv_i32m8_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vzip_vv_i32m8_mu(vbool8_t vm, vint32m8_t vd, vint32m4_t vs2,
+vint32m8_t test_vzip_vv_i32m8_mu(vbool4_t vm, vint32m8_t vd, vint32m4_t vs2,
vint32m4_t vs1, size_t vl) {
return __riscv_vzip_vv_i32m8_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vzip_vv_i64m2_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
-vint64m2_t test_vzip_vv_i64m2_mu(vbool64_t vm, vint64m2_t vd, vint64m1_t vs2,
+vint64m2_t test_vzip_vv_i64m2_mu(vbool32_t vm, vint64m2_t vd, vint64m1_t vs2,
vint64m1_t vs1, size_t vl) {
return __riscv_vzip_vv_i64m2_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vzip_vv_i64m4_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
-vint64m4_t test_vzip_vv_i64m4_mu(vbool32_t vm, vint64m4_t vd, vint64m2_t vs2,
+vint64m4_t test_vzip_vv_i64m4_mu(vbool16_t vm, vint64m4_t vd, vint64m2_t vs2,
vint64m2_t vs1, size_t vl) {
return __riscv_vzip_vv_i64m4_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vzip_vv_i64m8_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
-vint64m8_t test_vzip_vv_i64m8_mu(vbool16_t vm, vint64m8_t vd, vint64m4_t vs2,
+vint64m8_t test_vzip_vv_i64m8_mu(vbool8_t vm, vint64m8_t vd, vint64m4_t vs2,
vint64m4_t vs1, size_t vl) {
return __riscv_vzip_vv_i64m8_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vzip_vv_u8mf4_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
-vuint8mf4_t test_vzip_vv_u8mf4_mu(vbool64_t vm, vuint8mf4_t vd, vuint8mf8_t vs2,
+vuint8mf4_t test_vzip_vv_u8mf4_mu(vbool32_t vm, vuint8mf4_t vd, vuint8mf8_t vs2,
vuint8mf8_t vs1, size_t vl) {
return __riscv_vzip_vv_u8mf4_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vzip_vv_u8mf2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
-vuint8mf2_t test_vzip_vv_u8mf2_mu(vbool32_t vm, vuint8mf2_t vd, vuint8mf4_t vs2,
+vuint8mf2_t test_vzip_vv_u8mf2_mu(vbool16_t vm, vuint8mf2_t vd, vuint8mf4_t vs2,
vuint8mf4_t vs1, size_t vl) {
return __riscv_vzip_vv_u8mf2_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vzip_vv_u8m1_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
-vuint8m1_t test_vzip_vv_u8m1_mu(vbool16_t vm, vuint8m1_t vd, vuint8mf2_t vs2,
+vuint8m1_t test_vzip_vv_u8m1_mu(vbool8_t vm, vuint8m1_t vd, vuint8mf2_t vs2,
vuint8mf2_t vs1, size_t vl) {
return __riscv_vzip_vv_u8m1_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vzip_vv_u8m2_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
-vuint8m2_t test_vzip_vv_u8m2_mu(vbool8_t vm, vuint8m2_t vd, vuint8m1_t vs2,
+vuint8m2_t test_vzip_vv_u8m2_mu(vbool4_t vm, vuint8m2_t vd, vuint8m1_t vs2,
vuint8m1_t vs1, size_t vl) {
return __riscv_vzip_vv_u8m2_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vzip_vv_u8m4_mu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
-vuint8m4_t test_vzip_vv_u8m4_mu(vbool4_t vm, vuint8m4_t vd, vuint8m2_t vs2,
+vuint8m4_t test_vzip_vv_u8m4_mu(vbool2_t vm, vuint8m4_t vd, vuint8m2_t vs2,
vuint8m2_t vs1, size_t vl) {
return __riscv_vzip_vv_u8m4_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vzip_vv_u8m8_mu
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 64 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 64 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
-vuint8m8_t test_vzip_vv_u8m8_mu(vbool2_t vm, vuint8m8_t vd, vuint8m4_t vs2,
+vuint8m8_t test_vzip_vv_u8m8_mu(vbool1_t vm, vuint8m8_t vd, vuint8m4_t vs2,
vuint8m4_t vs1, size_t vl) {
return __riscv_vzip_vv_u8m8_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vzip_vv_u16mf2_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
-vuint16mf2_t test_vzip_vv_u16mf2_mu(vbool64_t vm, vuint16mf2_t vd,
+vuint16mf2_t test_vzip_vv_u16mf2_mu(vbool32_t vm, vuint16mf2_t vd,
vuint16mf4_t vs2, vuint16mf4_t vs1,
size_t vl) {
return __riscv_vzip_vv_u16mf2_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vzip_vv_u16m1_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
-vuint16m1_t test_vzip_vv_u16m1_mu(vbool32_t vm, vuint16m1_t vd,
+vuint16m1_t test_vzip_vv_u16m1_mu(vbool16_t vm, vuint16m1_t vd,
vuint16mf2_t vs2, vuint16mf2_t vs1,
size_t vl) {
return __riscv_vzip_vv_u16m1_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vzip_vv_u16m2_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
-vuint16m2_t test_vzip_vv_u16m2_mu(vbool16_t vm, vuint16m2_t vd, vuint16m1_t vs2,
+vuint16m2_t test_vzip_vv_u16m2_mu(vbool8_t vm, vuint16m2_t vd, vuint16m1_t vs2,
vuint16m1_t vs1, size_t vl) {
return __riscv_vzip_vv_u16m2_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vzip_vv_u16m4_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
-vuint16m4_t test_vzip_vv_u16m4_mu(vbool8_t vm, vuint16m4_t vd, vuint16m2_t vs2,
+vuint16m4_t test_vzip_vv_u16m4_mu(vbool4_t vm, vuint16m4_t vd, vuint16m2_t vs2,
vuint16m2_t vs1, size_t vl) {
return __riscv_vzip_vv_u16m4_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vzip_vv_u16m8_mu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
-vuint16m8_t test_vzip_vv_u16m8_mu(vbool4_t vm, vuint16m8_t vd, vuint16m4_t vs2,
+vuint16m8_t test_vzip_vv_u16m8_mu(vbool2_t vm, vuint16m8_t vd, vuint16m4_t vs2,
vuint16m4_t vs1, size_t vl) {
return __riscv_vzip_vv_u16m8_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vzip_vv_u32m1_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vzip_vv_u32m1_mu(vbool64_t vm, vuint32m1_t vd,
+vuint32m1_t test_vzip_vv_u32m1_mu(vbool32_t vm, vuint32m1_t vd,
vuint32mf2_t vs2, vuint32mf2_t vs1,
size_t vl) {
return __riscv_vzip_vv_u32m1_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vzip_vv_u32m2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vzip_vv_u32m2_mu(vbool32_t vm, vuint32m2_t vd, vuint32m1_t vs2,
+vuint32m2_t test_vzip_vv_u32m2_mu(vbool16_t vm, vuint32m2_t vd, vuint32m1_t vs2,
vuint32m1_t vs1, size_t vl) {
return __riscv_vzip_vv_u32m2_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vzip_vv_u32m4_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vzip_vv_u32m4_mu(vbool16_t vm, vuint32m4_t vd, vuint32m2_t vs2,
+vuint32m4_t test_vzip_vv_u32m4_mu(vbool8_t vm, vuint32m4_t vd, vuint32m2_t vs2,
vuint32m2_t vs1, size_t vl) {
return __riscv_vzip_vv_u32m4_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vzip_vv_u32m8_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vzip_vv_u32m8_mu(vbool8_t vm, vuint32m8_t vd, vuint32m4_t vs2,
+vuint32m8_t test_vzip_vv_u32m8_mu(vbool4_t vm, vuint32m8_t vd, vuint32m4_t vs2,
vuint32m4_t vs1, size_t vl) {
return __riscv_vzip_vv_u32m8_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vzip_vv_u64m2_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
-vuint64m2_t test_vzip_vv_u64m2_mu(vbool64_t vm, vuint64m2_t vd, vuint64m1_t vs2,
+vuint64m2_t test_vzip_vv_u64m2_mu(vbool32_t vm, vuint64m2_t vd, vuint64m1_t vs2,
vuint64m1_t vs1, size_t vl) {
return __riscv_vzip_vv_u64m2_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vzip_vv_u64m4_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
-vuint64m4_t test_vzip_vv_u64m4_mu(vbool32_t vm, vuint64m4_t vd, vuint64m2_t vs2,
+vuint64m4_t test_vzip_vv_u64m4_mu(vbool16_t vm, vuint64m4_t vd, vuint64m2_t vs2,
vuint64m2_t vs1, size_t vl) {
return __riscv_vzip_vv_u64m4_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vzip_vv_u64m8_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
-vuint64m8_t test_vzip_vv_u64m8_mu(vbool16_t vm, vuint64m8_t vd, vuint64m4_t vs2,
+vuint64m8_t test_vzip_vv_u64m8_mu(vbool8_t vm, vuint64m8_t vd, vuint64m4_t vs2,
vuint64m4_t vs1, size_t vl) {
return __riscv_vzip_vv_u64m8_mu(vm, vd, vs2, vs1, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c
index 3b2b68028bd77..6a85dc5283089 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c
@@ -505,1586 +505,3 @@ vuint64m4_t test_vunzipe_v_u64m4_tu(vuint64m4_t vd, vuint64m8_t vs, size_t vl) {
return __riscv_vunzipe_tu(vd, vs, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vunzipe_v_f16mf4_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 2 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vunzipe.mask.nxv1f16.nxv2f16.i64(<vscale x 1 x half> [[VD]], <vscale x 2 x half> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
-//
-vfloat16mf4_t test_vunzipe_v_f16mf4_tum(vbool64_t vm, vfloat16mf4_t vd,
- vfloat16mf2_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vunzipe_v_f16mf2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 4 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vunzipe.mask.nxv2f16.nxv4f16.i64(<vscale x 2 x half> [[VD]], <vscale x 4 x half> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
-//
-vfloat16mf2_t test_vunzipe_v_f16mf2_tum(vbool32_t vm, vfloat16mf2_t vd,
- vfloat16m1_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vunzipe_v_f16m1_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 8 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vunzipe.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[VD]], <vscale x 8 x half> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
-//
-vfloat16m1_t test_vunzipe_v_f16m1_tum(vbool16_t vm, vfloat16m1_t vd,
- vfloat16m2_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vunzipe_v_f16m2_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 16 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vunzipe.mask.nxv8f16.nxv16f16.i64(<vscale x 8 x half> [[VD]], <vscale x 16 x half> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
-//
-vfloat16m2_t test_vunzipe_v_f16m2_tum(vbool8_t vm, vfloat16m2_t vd,
- vfloat16m4_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vunzipe_v_f16m4_tum
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 32 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vunzipe.mask.nxv16f16.nxv32f16.i64(<vscale x 16 x half> [[VD]], <vscale x 32 x half> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
-//
-vfloat16m4_t test_vunzipe_v_f16m4_tum(vbool4_t vm, vfloat16m4_t vd,
- vfloat16m8_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vunzipe_v_f32mf2_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 2 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vunzipe.mask.nxv1f32.nxv2f32.i64(<vscale x 1 x float> [[VD]], <vscale x 2 x float> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
-//
-vfloat32mf2_t test_vunzipe_v_f32mf2_tum(vbool64_t vm, vfloat32mf2_t vd,
- vfloat32m1_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vunzipe_v_f32m1_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 4 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vunzipe.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[VD]], <vscale x 4 x float> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
-//
-vfloat32m1_t test_vunzipe_v_f32m1_tum(vbool32_t vm, vfloat32m1_t vd,
- vfloat32m2_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vunzipe_v_f32m2_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 8 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vunzipe.mask.nxv4f32.nxv8f32.i64(<vscale x 4 x float> [[VD]], <vscale x 8 x float> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
-//
-vfloat32m2_t test_vunzipe_v_f32m2_tum(vbool16_t vm, vfloat32m2_t vd,
- vfloat32m4_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vunzipe_v_f32m4_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 16 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vunzipe.mask.nxv8f32.nxv16f32.i64(<vscale x 8 x float> [[VD]], <vscale x 16 x float> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
-//
-vfloat32m4_t test_vunzipe_v_f32m4_tum(vbool8_t vm, vfloat32m4_t vd,
- vfloat32m8_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vunzipe_v_f64m1_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 2 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vunzipe.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[VD]], <vscale x 2 x double> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
-//
-vfloat64m1_t test_vunzipe_v_f64m1_tum(vbool64_t vm, vfloat64m1_t vd,
- vfloat64m2_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vunzipe_v_f64m2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 4 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vunzipe.mask.nxv2f64.nxv4f64.i64(<vscale x 2 x double> [[VD]], <vscale x 4 x double> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
-//
-vfloat64m2_t test_vunzipe_v_f64m2_tum(vbool32_t vm, vfloat64m2_t vd,
- vfloat64m4_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vunzipe_v_f64m4_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 8 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vunzipe.mask.nxv4f64.nxv8f64.i64(<vscale x 4 x double> [[VD]], <vscale x 8 x double> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
-//
-vfloat64m4_t test_vunzipe_v_f64m4_tum(vbool16_t vm, vfloat64m4_t vd,
- vfloat64m8_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vunzipe_v_i8mf8_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vunzipe.mask.nxv1i8.nxv2i8.i64(<vscale x 1 x i8> [[VD]], <vscale x 2 x i8> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
-//
-vint8mf8_t test_vunzipe_v_i8mf8_tum(vbool64_t vm, vint8mf8_t vd, vint8mf4_t vs,
- size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vunzipe_v_i8mf4_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vunzipe.mask.nxv2i8.nxv4i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 4 x i8> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
-//
-vint8mf4_t test_vunzipe_v_i8mf4_tum(vbool32_t vm, vint8mf4_t vd, vint8mf2_t vs,
- size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vunzipe_v_i8mf2_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vunzipe.mask.nxv4i8.nxv8i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 8 x i8> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
-//
-vint8mf2_t test_vunzipe_v_i8mf2_tum(vbool16_t vm, vint8mf2_t vd, vint8m1_t vs,
- size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vunzipe_v_i8m1_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vunzipe.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 16 x i8> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
-//
-vint8m1_t test_vunzipe_v_i8m1_tum(vbool8_t vm, vint8m1_t vd, vint8m2_t vs,
- size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vunzipe_v_i8m2_tum
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vunzipe.mask.nxv16i8.nxv32i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 32 x i8> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-vint8m2_t test_vunzipe_v_i8m2_tum(vbool4_t vm, vint8m2_t vd, vint8m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vunzipe_v_i8m4_tum
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vunzipe.mask.nxv32i8.nxv64i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 64 x i8> [[VS]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
-//
-vint8m4_t test_vunzipe_v_i8m4_tum(vbool2_t vm, vint8m4_t vd, vint8m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vunzipe_v_i16mf4_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vunzipe.mask.nxv1i16.nxv2i16.i64(<vscale x 1 x i16> [[VD]], <vscale x 2 x i16> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
-//
-vint16mf4_t test_vunzipe_v_i16mf4_tum(vbool64_t vm, vint16mf4_t vd,
- vint16mf2_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vunzipe_v_i16mf2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vunzipe.mask.nxv2i16.nxv4i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 4 x i16> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
-//
-vint16mf2_t test_vunzipe_v_i16mf2_tum(vbool32_t vm, vint16mf2_t vd,
- vint16m1_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vunzipe_v_i16m1_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vunzipe.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 8 x i16> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
-//
-vint16m1_t test_vunzipe_v_i16m1_tum(vbool16_t vm, vint16m1_t vd, vint16m2_t vs,
- size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vunzipe_v_i16m2_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vunzipe.mask.nxv8i16.nxv16i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 16 x i16> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-vint16m2_t test_vunzipe_v_i16m2_tum(vbool8_t vm, vint16m2_t vd, vint16m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vunzipe_v_i16m4_tum
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vunzipe.mask.nxv16i16.nxv32i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 32 x i16> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
-//
-vint16m4_t test_vunzipe_v_i16m4_tum(vbool4_t vm, vint16m4_t vd, vint16m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vunzipe_v_i32mf2_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vunzipe.mask.nxv1i32.nxv2i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 2 x i32> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vunzipe_v_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
- vint32m1_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vunzipe_v_i32m1_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vunzipe.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 4 x i32> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vunzipe_v_i32m1_tum(vbool32_t vm, vint32m1_t vd, vint32m2_t vs,
- size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vunzipe_v_i32m2_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vunzipe.mask.nxv4i32.nxv8i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i32> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vunzipe_v_i32m2_tum(vbool16_t vm, vint32m2_t vd, vint32m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vunzipe_v_i32m4_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vunzipe.mask.nxv8i32.nxv16i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 16 x i32> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vunzipe_v_i32m4_tum(vbool8_t vm, vint32m4_t vd, vint32m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vunzipe_v_i64m1_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vunzipe.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> [[VD]], <vscale x 2 x i64> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
-//
-vint64m1_t test_vunzipe_v_i64m1_tum(vbool64_t vm, vint64m1_t vd, vint64m2_t vs,
- size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vunzipe_v_i64m2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vunzipe.mask.nxv2i64.nxv4i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 4 x i64> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-vint64m2_t test_vunzipe_v_i64m2_tum(vbool32_t vm, vint64m2_t vd, vint64m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vunzipe_v_i64m4_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vunzipe.mask.nxv4i64.nxv8i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 8 x i64> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
-//
-vint64m4_t test_vunzipe_v_i64m4_tum(vbool16_t vm, vint64m4_t vd, vint64m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vunzipe_v_u8mf8_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vunzipe.mask.nxv1i8.nxv2i8.i64(<vscale x 1 x i8> [[VD]], <vscale x 2 x i8> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
-//
-vuint8mf8_t test_vunzipe_v_u8mf8_tum(vbool64_t vm, vuint8mf8_t vd,
- vuint8mf4_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vunzipe_v_u8mf4_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vunzipe.mask.nxv2i8.nxv4i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 4 x i8> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
-//
-vuint8mf4_t test_vunzipe_v_u8mf4_tum(vbool32_t vm, vuint8mf4_t vd,
- vuint8mf2_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vunzipe_v_u8mf2_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vunzipe.mask.nxv4i8.nxv8i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 8 x i8> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
-//
-vuint8mf2_t test_vunzipe_v_u8mf2_tum(vbool16_t vm, vuint8mf2_t vd,
- vuint8m1_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vunzipe_v_u8m1_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vunzipe.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 16 x i8> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
-//
-vuint8m1_t test_vunzipe_v_u8m1_tum(vbool8_t vm, vuint8m1_t vd, vuint8m2_t vs,
- size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vunzipe_v_u8m2_tum
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vunzipe.mask.nxv16i8.nxv32i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 32 x i8> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-vuint8m2_t test_vunzipe_v_u8m2_tum(vbool4_t vm, vuint8m2_t vd, vuint8m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vunzipe_v_u8m4_tum
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vunzipe.mask.nxv32i8.nxv64i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 64 x i8> [[VS]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
-//
-vuint8m4_t test_vunzipe_v_u8m4_tum(vbool2_t vm, vuint8m4_t vd, vuint8m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vunzipe_v_u16mf4_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vunzipe.mask.nxv1i16.nxv2i16.i64(<vscale x 1 x i16> [[VD]], <vscale x 2 x i16> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
-//
-vuint16mf4_t test_vunzipe_v_u16mf4_tum(vbool64_t vm, vuint16mf4_t vd,
- vuint16mf2_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vunzipe_v_u16mf2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vunzipe.mask.nxv2i16.nxv4i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 4 x i16> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
-//
-vuint16mf2_t test_vunzipe_v_u16mf2_tum(vbool32_t vm, vuint16mf2_t vd,
- vuint16m1_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vunzipe_v_u16m1_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vunzipe.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 8 x i16> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
-//
-vuint16m1_t test_vunzipe_v_u16m1_tum(vbool16_t vm, vuint16m1_t vd,
- vuint16m2_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vunzipe_v_u16m2_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vunzipe.mask.nxv8i16.nxv16i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 16 x i16> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-vuint16m2_t test_vunzipe_v_u16m2_tum(vbool8_t vm, vuint16m2_t vd,
- vuint16m4_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vunzipe_v_u16m4_tum
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vunzipe.mask.nxv16i16.nxv32i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 32 x i16> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
-//
-vuint16m4_t test_vunzipe_v_u16m4_tum(vbool4_t vm, vuint16m4_t vd,
- vuint16m8_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vunzipe_v_u32mf2_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vunzipe.mask.nxv1i32.nxv2i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 2 x i32> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vuint32mf2_t test_vunzipe_v_u32mf2_tum(vbool64_t vm, vuint32mf2_t vd,
- vuint32m1_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vunzipe_v_u32m1_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vunzipe.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 4 x i32> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vuint32m1_t test_vunzipe_v_u32m1_tum(vbool32_t vm, vuint32m1_t vd,
- vuint32m2_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vunzipe_v_u32m2_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vunzipe.mask.nxv4i32.nxv8i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i32> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vuint32m2_t test_vunzipe_v_u32m2_tum(vbool16_t vm, vuint32m2_t vd,
- vuint32m4_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vunzipe_v_u32m4_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vunzipe.mask.nxv8i32.nxv16i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 16 x i32> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vuint32m4_t test_vunzipe_v_u32m4_tum(vbool8_t vm, vuint32m4_t vd,
- vuint32m8_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vunzipe_v_u64m1_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vunzipe.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> [[VD]], <vscale x 2 x i64> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
-//
-vuint64m1_t test_vunzipe_v_u64m1_tum(vbool64_t vm, vuint64m1_t vd,
- vuint64m2_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vunzipe_v_u64m2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vunzipe.mask.nxv2i64.nxv4i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 4 x i64> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-vuint64m2_t test_vunzipe_v_u64m2_tum(vbool32_t vm, vuint64m2_t vd,
- vuint64m4_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vunzipe_v_u64m4_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vunzipe.mask.nxv4i64.nxv8i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 8 x i64> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
-//
-vuint64m4_t test_vunzipe_v_u64m4_tum(vbool16_t vm, vuint64m4_t vd,
- vuint64m8_t vs, size_t vl) {
- return __riscv_vunzipe_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vunzipe_v_f16mf4_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 2 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vunzipe.mask.nxv1f16.nxv2f16.i64(<vscale x 1 x half> [[VD]], <vscale x 2 x half> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
-//
-vfloat16mf4_t test_vunzipe_v_f16mf4_tumu(vbool64_t vm, vfloat16mf4_t vd,
- vfloat16mf2_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vunzipe_v_f16mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 4 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vunzipe.mask.nxv2f16.nxv4f16.i64(<vscale x 2 x half> [[VD]], <vscale x 4 x half> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
-//
-vfloat16mf2_t test_vunzipe_v_f16mf2_tumu(vbool32_t vm, vfloat16mf2_t vd,
- vfloat16m1_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vunzipe_v_f16m1_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 8 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vunzipe.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[VD]], <vscale x 8 x half> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
-//
-vfloat16m1_t test_vunzipe_v_f16m1_tumu(vbool16_t vm, vfloat16m1_t vd,
- vfloat16m2_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vunzipe_v_f16m2_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 16 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vunzipe.mask.nxv8f16.nxv16f16.i64(<vscale x 8 x half> [[VD]], <vscale x 16 x half> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
-//
-vfloat16m2_t test_vunzipe_v_f16m2_tumu(vbool8_t vm, vfloat16m2_t vd,
- vfloat16m4_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vunzipe_v_f16m4_tumu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 32 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vunzipe.mask.nxv16f16.nxv32f16.i64(<vscale x 16 x half> [[VD]], <vscale x 32 x half> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
-//
-vfloat16m4_t test_vunzipe_v_f16m4_tumu(vbool4_t vm, vfloat16m4_t vd,
- vfloat16m8_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vunzipe_v_f32mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 2 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vunzipe.mask.nxv1f32.nxv2f32.i64(<vscale x 1 x float> [[VD]], <vscale x 2 x float> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
-//
-vfloat32mf2_t test_vunzipe_v_f32mf2_tumu(vbool64_t vm, vfloat32mf2_t vd,
- vfloat32m1_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vunzipe_v_f32m1_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 4 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vunzipe.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[VD]], <vscale x 4 x float> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
-//
-vfloat32m1_t test_vunzipe_v_f32m1_tumu(vbool32_t vm, vfloat32m1_t vd,
- vfloat32m2_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vunzipe_v_f32m2_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 8 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vunzipe.mask.nxv4f32.nxv8f32.i64(<vscale x 4 x float> [[VD]], <vscale x 8 x float> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
-//
-vfloat32m2_t test_vunzipe_v_f32m2_tumu(vbool16_t vm, vfloat32m2_t vd,
- vfloat32m4_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vunzipe_v_f32m4_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 16 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vunzipe.mask.nxv8f32.nxv16f32.i64(<vscale x 8 x float> [[VD]], <vscale x 16 x float> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
-//
-vfloat32m4_t test_vunzipe_v_f32m4_tumu(vbool8_t vm, vfloat32m4_t vd,
- vfloat32m8_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vunzipe_v_f64m1_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 2 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vunzipe.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[VD]], <vscale x 2 x double> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
-//
-vfloat64m1_t test_vunzipe_v_f64m1_tumu(vbool64_t vm, vfloat64m1_t vd,
- vfloat64m2_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vunzipe_v_f64m2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 4 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vunzipe.mask.nxv2f64.nxv4f64.i64(<vscale x 2 x double> [[VD]], <vscale x 4 x double> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
-//
-vfloat64m2_t test_vunzipe_v_f64m2_tumu(vbool32_t vm, vfloat64m2_t vd,
- vfloat64m4_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vunzipe_v_f64m4_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 8 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vunzipe.mask.nxv4f64.nxv8f64.i64(<vscale x 4 x double> [[VD]], <vscale x 8 x double> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
-//
-vfloat64m4_t test_vunzipe_v_f64m4_tumu(vbool16_t vm, vfloat64m4_t vd,
- vfloat64m8_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vunzipe_v_i8mf8_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vunzipe.mask.nxv1i8.nxv2i8.i64(<vscale x 1 x i8> [[VD]], <vscale x 2 x i8> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
-//
-vint8mf8_t test_vunzipe_v_i8mf8_tumu(vbool64_t vm, vint8mf8_t vd, vint8mf4_t vs,
- size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vunzipe_v_i8mf4_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vunzipe.mask.nxv2i8.nxv4i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 4 x i8> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
-//
-vint8mf4_t test_vunzipe_v_i8mf4_tumu(vbool32_t vm, vint8mf4_t vd, vint8mf2_t vs,
- size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vunzipe_v_i8mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vunzipe.mask.nxv4i8.nxv8i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 8 x i8> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
-//
-vint8mf2_t test_vunzipe_v_i8mf2_tumu(vbool16_t vm, vint8mf2_t vd, vint8m1_t vs,
- size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vunzipe_v_i8m1_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vunzipe.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 16 x i8> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
-//
-vint8m1_t test_vunzipe_v_i8m1_tumu(vbool8_t vm, vint8m1_t vd, vint8m2_t vs,
- size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vunzipe_v_i8m2_tumu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vunzipe.mask.nxv16i8.nxv32i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 32 x i8> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-vint8m2_t test_vunzipe_v_i8m2_tumu(vbool4_t vm, vint8m2_t vd, vint8m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vunzipe_v_i8m4_tumu
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vunzipe.mask.nxv32i8.nxv64i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 64 x i8> [[VS]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
-//
-vint8m4_t test_vunzipe_v_i8m4_tumu(vbool2_t vm, vint8m4_t vd, vint8m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vunzipe_v_i16mf4_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vunzipe.mask.nxv1i16.nxv2i16.i64(<vscale x 1 x i16> [[VD]], <vscale x 2 x i16> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
-//
-vint16mf4_t test_vunzipe_v_i16mf4_tumu(vbool64_t vm, vint16mf4_t vd,
- vint16mf2_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vunzipe_v_i16mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vunzipe.mask.nxv2i16.nxv4i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 4 x i16> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
-//
-vint16mf2_t test_vunzipe_v_i16mf2_tumu(vbool32_t vm, vint16mf2_t vd,
- vint16m1_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vunzipe_v_i16m1_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vunzipe.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 8 x i16> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
-//
-vint16m1_t test_vunzipe_v_i16m1_tumu(vbool16_t vm, vint16m1_t vd, vint16m2_t vs,
- size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vunzipe_v_i16m2_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vunzipe.mask.nxv8i16.nxv16i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 16 x i16> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-vint16m2_t test_vunzipe_v_i16m2_tumu(vbool8_t vm, vint16m2_t vd, vint16m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vunzipe_v_i16m4_tumu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vunzipe.mask.nxv16i16.nxv32i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 32 x i16> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
-//
-vint16m4_t test_vunzipe_v_i16m4_tumu(vbool4_t vm, vint16m4_t vd, vint16m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vunzipe_v_i32mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vunzipe.mask.nxv1i32.nxv2i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 2 x i32> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vunzipe_v_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
- vint32m1_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vunzipe_v_i32m1_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vunzipe.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 4 x i32> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vunzipe_v_i32m1_tumu(vbool32_t vm, vint32m1_t vd, vint32m2_t vs,
- size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vunzipe_v_i32m2_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vunzipe.mask.nxv4i32.nxv8i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i32> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vunzipe_v_i32m2_tumu(vbool16_t vm, vint32m2_t vd, vint32m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vunzipe_v_i32m4_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vunzipe.mask.nxv8i32.nxv16i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 16 x i32> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vunzipe_v_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vint32m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vunzipe_v_i64m1_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vunzipe.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> [[VD]], <vscale x 2 x i64> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
-//
-vint64m1_t test_vunzipe_v_i64m1_tumu(vbool64_t vm, vint64m1_t vd, vint64m2_t vs,
- size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vunzipe_v_i64m2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vunzipe.mask.nxv2i64.nxv4i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 4 x i64> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-vint64m2_t test_vunzipe_v_i64m2_tumu(vbool32_t vm, vint64m2_t vd, vint64m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vunzipe_v_i64m4_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vunzipe.mask.nxv4i64.nxv8i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 8 x i64> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
-//
-vint64m4_t test_vunzipe_v_i64m4_tumu(vbool16_t vm, vint64m4_t vd, vint64m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vunzipe_v_u8mf8_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vunzipe.mask.nxv1i8.nxv2i8.i64(<vscale x 1 x i8> [[VD]], <vscale x 2 x i8> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
-//
-vuint8mf8_t test_vunzipe_v_u8mf8_tumu(vbool64_t vm, vuint8mf8_t vd,
- vuint8mf4_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vunzipe_v_u8mf4_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vunzipe.mask.nxv2i8.nxv4i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 4 x i8> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
-//
-vuint8mf4_t test_vunzipe_v_u8mf4_tumu(vbool32_t vm, vuint8mf4_t vd,
- vuint8mf2_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vunzipe_v_u8mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vunzipe.mask.nxv4i8.nxv8i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 8 x i8> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
-//
-vuint8mf2_t test_vunzipe_v_u8mf2_tumu(vbool16_t vm, vuint8mf2_t vd,
- vuint8m1_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vunzipe_v_u8m1_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vunzipe.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 16 x i8> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
-//
-vuint8m1_t test_vunzipe_v_u8m1_tumu(vbool8_t vm, vuint8m1_t vd, vuint8m2_t vs,
- size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vunzipe_v_u8m2_tumu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vunzipe.mask.nxv16i8.nxv32i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 32 x i8> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-vuint8m2_t test_vunzipe_v_u8m2_tumu(vbool4_t vm, vuint8m2_t vd, vuint8m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vunzipe_v_u8m4_tumu
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vunzipe.mask.nxv32i8.nxv64i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 64 x i8> [[VS]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
-//
-vuint8m4_t test_vunzipe_v_u8m4_tumu(vbool2_t vm, vuint8m4_t vd, vuint8m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vunzipe_v_u16mf4_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vunzipe.mask.nxv1i16.nxv2i16.i64(<vscale x 1 x i16> [[VD]], <vscale x 2 x i16> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
-//
-vuint16mf4_t test_vunzipe_v_u16mf4_tumu(vbool64_t vm, vuint16mf4_t vd,
- vuint16mf2_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vunzipe_v_u16mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vunzipe.mask.nxv2i16.nxv4i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 4 x i16> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
-//
-vuint16mf2_t test_vunzipe_v_u16mf2_tumu(vbool32_t vm, vuint16mf2_t vd,
- vuint16m1_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vunzipe_v_u16m1_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vunzipe.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 8 x i16> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
-//
-vuint16m1_t test_vunzipe_v_u16m1_tumu(vbool16_t vm, vuint16m1_t vd,
- vuint16m2_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vunzipe_v_u16m2_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vunzipe.mask.nxv8i16.nxv16i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 16 x i16> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-vuint16m2_t test_vunzipe_v_u16m2_tumu(vbool8_t vm, vuint16m2_t vd,
- vuint16m4_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vunzipe_v_u16m4_tumu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vunzipe.mask.nxv16i16.nxv32i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 32 x i16> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
-//
-vuint16m4_t test_vunzipe_v_u16m4_tumu(vbool4_t vm, vuint16m4_t vd,
- vuint16m8_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vunzipe_v_u32mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vunzipe.mask.nxv1i32.nxv2i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 2 x i32> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vuint32mf2_t test_vunzipe_v_u32mf2_tumu(vbool64_t vm, vuint32mf2_t vd,
- vuint32m1_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vunzipe_v_u32m1_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vunzipe.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 4 x i32> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vuint32m1_t test_vunzipe_v_u32m1_tumu(vbool32_t vm, vuint32m1_t vd,
- vuint32m2_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vunzipe_v_u32m2_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vunzipe.mask.nxv4i32.nxv8i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i32> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vuint32m2_t test_vunzipe_v_u32m2_tumu(vbool16_t vm, vuint32m2_t vd,
- vuint32m4_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vunzipe_v_u32m4_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vunzipe.mask.nxv8i32.nxv16i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 16 x i32> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vuint32m4_t test_vunzipe_v_u32m4_tumu(vbool8_t vm, vuint32m4_t vd,
- vuint32m8_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vunzipe_v_u64m1_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vunzipe.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> [[VD]], <vscale x 2 x i64> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
-//
-vuint64m1_t test_vunzipe_v_u64m1_tumu(vbool64_t vm, vuint64m1_t vd,
- vuint64m2_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vunzipe_v_u64m2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vunzipe.mask.nxv2i64.nxv4i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 4 x i64> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-vuint64m2_t test_vunzipe_v_u64m2_tumu(vbool32_t vm, vuint64m2_t vd,
- vuint64m4_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vunzipe_v_u64m4_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vunzipe.mask.nxv4i64.nxv8i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 8 x i64> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
-//
-vuint64m4_t test_vunzipe_v_u64m4_tumu(vbool16_t vm, vuint64m4_t vd,
- vuint64m8_t vs, size_t vl) {
- return __riscv_vunzipe_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vunzipe_v_f16mf4_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 2 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vunzipe.mask.nxv1f16.nxv2f16.i64(<vscale x 1 x half> [[VD]], <vscale x 2 x half> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
-//
-vfloat16mf4_t test_vunzipe_v_f16mf4_mu(vbool64_t vm, vfloat16mf4_t vd,
- vfloat16mf2_t vs, size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vunzipe_v_f16mf2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 4 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vunzipe.mask.nxv2f16.nxv4f16.i64(<vscale x 2 x half> [[VD]], <vscale x 4 x half> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
-//
-vfloat16mf2_t test_vunzipe_v_f16mf2_mu(vbool32_t vm, vfloat16mf2_t vd,
- vfloat16m1_t vs, size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vunzipe_v_f16m1_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 8 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vunzipe.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[VD]], <vscale x 8 x half> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
-//
-vfloat16m1_t test_vunzipe_v_f16m1_mu(vbool16_t vm, vfloat16m1_t vd,
- vfloat16m2_t vs, size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vunzipe_v_f16m2_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 16 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vunzipe.mask.nxv8f16.nxv16f16.i64(<vscale x 8 x half> [[VD]], <vscale x 16 x half> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
-//
-vfloat16m2_t test_vunzipe_v_f16m2_mu(vbool8_t vm, vfloat16m2_t vd,
- vfloat16m4_t vs, size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vunzipe_v_f16m4_mu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 32 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vunzipe.mask.nxv16f16.nxv32f16.i64(<vscale x 16 x half> [[VD]], <vscale x 32 x half> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
-//
-vfloat16m4_t test_vunzipe_v_f16m4_mu(vbool4_t vm, vfloat16m4_t vd,
- vfloat16m8_t vs, size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vunzipe_v_f32mf2_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 2 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vunzipe.mask.nxv1f32.nxv2f32.i64(<vscale x 1 x float> [[VD]], <vscale x 2 x float> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
-//
-vfloat32mf2_t test_vunzipe_v_f32mf2_mu(vbool64_t vm, vfloat32mf2_t vd,
- vfloat32m1_t vs, size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vunzipe_v_f32m1_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 4 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vunzipe.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[VD]], <vscale x 4 x float> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
-//
-vfloat32m1_t test_vunzipe_v_f32m1_mu(vbool32_t vm, vfloat32m1_t vd,
- vfloat32m2_t vs, size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vunzipe_v_f32m2_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 8 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vunzipe.mask.nxv4f32.nxv8f32.i64(<vscale x 4 x float> [[VD]], <vscale x 8 x float> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
-//
-vfloat32m2_t test_vunzipe_v_f32m2_mu(vbool16_t vm, vfloat32m2_t vd,
- vfloat32m4_t vs, size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vunzipe_v_f32m4_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 16 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vunzipe.mask.nxv8f32.nxv16f32.i64(<vscale x 8 x float> [[VD]], <vscale x 16 x float> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
-//
-vfloat32m4_t test_vunzipe_v_f32m4_mu(vbool8_t vm, vfloat32m4_t vd,
- vfloat32m8_t vs, size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vunzipe_v_f64m1_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 2 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vunzipe.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[VD]], <vscale x 2 x double> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
-//
-vfloat64m1_t test_vunzipe_v_f64m1_mu(vbool64_t vm, vfloat64m1_t vd,
- vfloat64m2_t vs, size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vunzipe_v_f64m2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 4 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vunzipe.mask.nxv2f64.nxv4f64.i64(<vscale x 2 x double> [[VD]], <vscale x 4 x double> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
-//
-vfloat64m2_t test_vunzipe_v_f64m2_mu(vbool32_t vm, vfloat64m2_t vd,
- vfloat64m4_t vs, size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vunzipe_v_f64m4_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 8 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vunzipe.mask.nxv4f64.nxv8f64.i64(<vscale x 4 x double> [[VD]], <vscale x 8 x double> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
-//
-vfloat64m4_t test_vunzipe_v_f64m4_mu(vbool16_t vm, vfloat64m4_t vd,
- vfloat64m8_t vs, size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vunzipe_v_i8mf8_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vunzipe.mask.nxv1i8.nxv2i8.i64(<vscale x 1 x i8> [[VD]], <vscale x 2 x i8> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
-//
-vint8mf8_t test_vunzipe_v_i8mf8_mu(vbool64_t vm, vint8mf8_t vd, vint8mf4_t vs,
- size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vunzipe_v_i8mf4_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vunzipe.mask.nxv2i8.nxv4i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 4 x i8> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
-//
-vint8mf4_t test_vunzipe_v_i8mf4_mu(vbool32_t vm, vint8mf4_t vd, vint8mf2_t vs,
- size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vunzipe_v_i8mf2_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vunzipe.mask.nxv4i8.nxv8i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 8 x i8> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
-//
-vint8mf2_t test_vunzipe_v_i8mf2_mu(vbool16_t vm, vint8mf2_t vd, vint8m1_t vs,
- size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vunzipe_v_i8m1_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vunzipe.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 16 x i8> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
-//
-vint8m1_t test_vunzipe_v_i8m1_mu(vbool8_t vm, vint8m1_t vd, vint8m2_t vs,
- size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vunzipe_v_i8m2_mu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vunzipe.mask.nxv16i8.nxv32i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 32 x i8> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-vint8m2_t test_vunzipe_v_i8m2_mu(vbool4_t vm, vint8m2_t vd, vint8m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vunzipe_v_i8m4_mu
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vunzipe.mask.nxv32i8.nxv64i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 64 x i8> [[VS]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
-//
-vint8m4_t test_vunzipe_v_i8m4_mu(vbool2_t vm, vint8m4_t vd, vint8m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vunzipe_v_i16mf4_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vunzipe.mask.nxv1i16.nxv2i16.i64(<vscale x 1 x i16> [[VD]], <vscale x 2 x i16> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
-//
-vint16mf4_t test_vunzipe_v_i16mf4_mu(vbool64_t vm, vint16mf4_t vd,
- vint16mf2_t vs, size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vunzipe_v_i16mf2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vunzipe.mask.nxv2i16.nxv4i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 4 x i16> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
-//
-vint16mf2_t test_vunzipe_v_i16mf2_mu(vbool32_t vm, vint16mf2_t vd,
- vint16m1_t vs, size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vunzipe_v_i16m1_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vunzipe.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 8 x i16> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
-//
-vint16m1_t test_vunzipe_v_i16m1_mu(vbool16_t vm, vint16m1_t vd, vint16m2_t vs,
- size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vunzipe_v_i16m2_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vunzipe.mask.nxv8i16.nxv16i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 16 x i16> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-vint16m2_t test_vunzipe_v_i16m2_mu(vbool8_t vm, vint16m2_t vd, vint16m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vunzipe_v_i16m4_mu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vunzipe.mask.nxv16i16.nxv32i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 32 x i16> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
-//
-vint16m4_t test_vunzipe_v_i16m4_mu(vbool4_t vm, vint16m4_t vd, vint16m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vunzipe_v_i32mf2_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vunzipe.mask.nxv1i32.nxv2i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 2 x i32> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vunzipe_v_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
- vint32m1_t vs, size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vunzipe_v_i32m1_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vunzipe.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 4 x i32> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vunzipe_v_i32m1_mu(vbool32_t vm, vint32m1_t vd, vint32m2_t vs,
- size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vunzipe_v_i32m2_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vunzipe.mask.nxv4i32.nxv8i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i32> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vunzipe_v_i32m2_mu(vbool16_t vm, vint32m2_t vd, vint32m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vunzipe_v_i32m4_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vunzipe.mask.nxv8i32.nxv16i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 16 x i32> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vunzipe_v_i32m4_mu(vbool8_t vm, vint32m4_t vd, vint32m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vunzipe_v_i64m1_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vunzipe.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> [[VD]], <vscale x 2 x i64> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
-//
-vint64m1_t test_vunzipe_v_i64m1_mu(vbool64_t vm, vint64m1_t vd, vint64m2_t vs,
- size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vunzipe_v_i64m2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vunzipe.mask.nxv2i64.nxv4i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 4 x i64> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-vint64m2_t test_vunzipe_v_i64m2_mu(vbool32_t vm, vint64m2_t vd, vint64m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vunzipe_v_i64m4_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vunzipe.mask.nxv4i64.nxv8i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 8 x i64> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
-//
-vint64m4_t test_vunzipe_v_i64m4_mu(vbool16_t vm, vint64m4_t vd, vint64m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vunzipe_v_u8mf8_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vunzipe.mask.nxv1i8.nxv2i8.i64(<vscale x 1 x i8> [[VD]], <vscale x 2 x i8> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
-//
-vuint8mf8_t test_vunzipe_v_u8mf8_mu(vbool64_t vm, vuint8mf8_t vd,
- vuint8mf4_t vs, size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vunzipe_v_u8mf4_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vunzipe.mask.nxv2i8.nxv4i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 4 x i8> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
-//
-vuint8mf4_t test_vunzipe_v_u8mf4_mu(vbool32_t vm, vuint8mf4_t vd,
- vuint8mf2_t vs, size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vunzipe_v_u8mf2_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vunzipe.mask.nxv4i8.nxv8i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 8 x i8> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
-//
-vuint8mf2_t test_vunzipe_v_u8mf2_mu(vbool16_t vm, vuint8mf2_t vd, vuint8m1_t vs,
- size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vunzipe_v_u8m1_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vunzipe.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 16 x i8> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
-//
-vuint8m1_t test_vunzipe_v_u8m1_mu(vbool8_t vm, vuint8m1_t vd, vuint8m2_t vs,
- size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vunzipe_v_u8m2_mu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vunzipe.mask.nxv16i8.nxv32i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 32 x i8> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-vuint8m2_t test_vunzipe_v_u8m2_mu(vbool4_t vm, vuint8m2_t vd, vuint8m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vunzipe_v_u8m4_mu
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vunzipe.mask.nxv32i8.nxv64i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 64 x i8> [[VS]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
-//
-vuint8m4_t test_vunzipe_v_u8m4_mu(vbool2_t vm, vuint8m4_t vd, vuint8m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vunzipe_v_u16mf4_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vunzipe.mask.nxv1i16.nxv2i16.i64(<vscale x 1 x i16> [[VD]], <vscale x 2 x i16> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
-//
-vuint16mf4_t test_vunzipe_v_u16mf4_mu(vbool64_t vm, vuint16mf4_t vd,
- vuint16mf2_t vs, size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vunzipe_v_u16mf2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vunzipe.mask.nxv2i16.nxv4i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 4 x i16> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
-//
-vuint16mf2_t test_vunzipe_v_u16mf2_mu(vbool32_t vm, vuint16mf2_t vd,
- vuint16m1_t vs, size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vunzipe_v_u16m1_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vunzipe.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 8 x i16> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
-//
-vuint16m1_t test_vunzipe_v_u16m1_mu(vbool16_t vm, vuint16m1_t vd,
- vuint16m2_t vs, size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vunzipe_v_u16m2_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vunzipe.mask.nxv8i16.nxv16i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 16 x i16> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-vuint16m2_t test_vunzipe_v_u16m2_mu(vbool8_t vm, vuint16m2_t vd, vuint16m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vunzipe_v_u16m4_mu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vunzipe.mask.nxv16i16.nxv32i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 32 x i16> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
-//
-vuint16m4_t test_vunzipe_v_u16m4_mu(vbool4_t vm, vuint16m4_t vd, vuint16m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vunzipe_v_u32mf2_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vunzipe.mask.nxv1i32.nxv2i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 2 x i32> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vuint32mf2_t test_vunzipe_v_u32mf2_mu(vbool64_t vm, vuint32mf2_t vd,
- vuint32m1_t vs, size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vunzipe_v_u32m1_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vunzipe.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 4 x i32> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vuint32m1_t test_vunzipe_v_u32m1_mu(vbool32_t vm, vuint32m1_t vd,
- vuint32m2_t vs, size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vunzipe_v_u32m2_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vunzipe.mask.nxv4i32.nxv8i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i32> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vuint32m2_t test_vunzipe_v_u32m2_mu(vbool16_t vm, vuint32m2_t vd,
- vuint32m4_t vs, size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vunzipe_v_u32m4_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vunzipe.mask.nxv8i32.nxv16i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 16 x i32> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vuint32m4_t test_vunzipe_v_u32m4_mu(vbool8_t vm, vuint32m4_t vd, vuint32m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vunzipe_v_u64m1_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vunzipe.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> [[VD]], <vscale x 2 x i64> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
-//
-vuint64m1_t test_vunzipe_v_u64m1_mu(vbool64_t vm, vuint64m1_t vd,
- vuint64m2_t vs, size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vunzipe_v_u64m2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vunzipe.mask.nxv2i64.nxv4i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 4 x i64> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-vuint64m2_t test_vunzipe_v_u64m2_mu(vbool32_t vm, vuint64m2_t vd,
- vuint64m4_t vs, size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vunzipe_v_u64m4_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vunzipe.mask.nxv4i64.nxv8i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 8 x i64> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
-//
-vuint64m4_t test_vunzipe_v_u64m4_mu(vbool16_t vm, vuint64m4_t vd,
- vuint64m8_t vs, size_t vl) {
- return __riscv_vunzipe_mu(vm, vd, vs, vl);
-}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c
index 442bffaf27c64..904d3d948c681 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c
@@ -505,1586 +505,3 @@ vuint64m4_t test_vunzipo_v_u64m4_tu(vuint64m4_t vd, vuint64m8_t vs, size_t vl) {
return __riscv_vunzipo_tu(vd, vs, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vunzipo_v_f16mf4_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 2 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vunzipo.mask.nxv1f16.nxv2f16.i64(<vscale x 1 x half> [[VD]], <vscale x 2 x half> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
-//
-vfloat16mf4_t test_vunzipo_v_f16mf4_tum(vbool64_t vm, vfloat16mf4_t vd,
- vfloat16mf2_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vunzipo_v_f16mf2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 4 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vunzipo.mask.nxv2f16.nxv4f16.i64(<vscale x 2 x half> [[VD]], <vscale x 4 x half> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
-//
-vfloat16mf2_t test_vunzipo_v_f16mf2_tum(vbool32_t vm, vfloat16mf2_t vd,
- vfloat16m1_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vunzipo_v_f16m1_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 8 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vunzipo.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[VD]], <vscale x 8 x half> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
-//
-vfloat16m1_t test_vunzipo_v_f16m1_tum(vbool16_t vm, vfloat16m1_t vd,
- vfloat16m2_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vunzipo_v_f16m2_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 16 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vunzipo.mask.nxv8f16.nxv16f16.i64(<vscale x 8 x half> [[VD]], <vscale x 16 x half> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
-//
-vfloat16m2_t test_vunzipo_v_f16m2_tum(vbool8_t vm, vfloat16m2_t vd,
- vfloat16m4_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vunzipo_v_f16m4_tum
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 32 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vunzipo.mask.nxv16f16.nxv32f16.i64(<vscale x 16 x half> [[VD]], <vscale x 32 x half> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
-//
-vfloat16m4_t test_vunzipo_v_f16m4_tum(vbool4_t vm, vfloat16m4_t vd,
- vfloat16m8_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vunzipo_v_f32mf2_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 2 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vunzipo.mask.nxv1f32.nxv2f32.i64(<vscale x 1 x float> [[VD]], <vscale x 2 x float> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
-//
-vfloat32mf2_t test_vunzipo_v_f32mf2_tum(vbool64_t vm, vfloat32mf2_t vd,
- vfloat32m1_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vunzipo_v_f32m1_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 4 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vunzipo.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[VD]], <vscale x 4 x float> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
-//
-vfloat32m1_t test_vunzipo_v_f32m1_tum(vbool32_t vm, vfloat32m1_t vd,
- vfloat32m2_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vunzipo_v_f32m2_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 8 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vunzipo.mask.nxv4f32.nxv8f32.i64(<vscale x 4 x float> [[VD]], <vscale x 8 x float> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
-//
-vfloat32m2_t test_vunzipo_v_f32m2_tum(vbool16_t vm, vfloat32m2_t vd,
- vfloat32m4_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vunzipo_v_f32m4_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 16 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vunzipo.mask.nxv8f32.nxv16f32.i64(<vscale x 8 x float> [[VD]], <vscale x 16 x float> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
-//
-vfloat32m4_t test_vunzipo_v_f32m4_tum(vbool8_t vm, vfloat32m4_t vd,
- vfloat32m8_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vunzipo_v_f64m1_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 2 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vunzipo.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[VD]], <vscale x 2 x double> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
-//
-vfloat64m1_t test_vunzipo_v_f64m1_tum(vbool64_t vm, vfloat64m1_t vd,
- vfloat64m2_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vunzipo_v_f64m2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 4 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vunzipo.mask.nxv2f64.nxv4f64.i64(<vscale x 2 x double> [[VD]], <vscale x 4 x double> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
-//
-vfloat64m2_t test_vunzipo_v_f64m2_tum(vbool32_t vm, vfloat64m2_t vd,
- vfloat64m4_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vunzipo_v_f64m4_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 8 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vunzipo.mask.nxv4f64.nxv8f64.i64(<vscale x 4 x double> [[VD]], <vscale x 8 x double> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
-//
-vfloat64m4_t test_vunzipo_v_f64m4_tum(vbool16_t vm, vfloat64m4_t vd,
- vfloat64m8_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vunzipo_v_i8mf8_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vunzipo.mask.nxv1i8.nxv2i8.i64(<vscale x 1 x i8> [[VD]], <vscale x 2 x i8> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
-//
-vint8mf8_t test_vunzipo_v_i8mf8_tum(vbool64_t vm, vint8mf8_t vd, vint8mf4_t vs,
- size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vunzipo_v_i8mf4_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vunzipo.mask.nxv2i8.nxv4i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 4 x i8> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
-//
-vint8mf4_t test_vunzipo_v_i8mf4_tum(vbool32_t vm, vint8mf4_t vd, vint8mf2_t vs,
- size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vunzipo_v_i8mf2_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vunzipo.mask.nxv4i8.nxv8i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 8 x i8> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
-//
-vint8mf2_t test_vunzipo_v_i8mf2_tum(vbool16_t vm, vint8mf2_t vd, vint8m1_t vs,
- size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vunzipo_v_i8m1_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vunzipo.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 16 x i8> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
-//
-vint8m1_t test_vunzipo_v_i8m1_tum(vbool8_t vm, vint8m1_t vd, vint8m2_t vs,
- size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vunzipo_v_i8m2_tum
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vunzipo.mask.nxv16i8.nxv32i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 32 x i8> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-vint8m2_t test_vunzipo_v_i8m2_tum(vbool4_t vm, vint8m2_t vd, vint8m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vunzipo_v_i8m4_tum
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vunzipo.mask.nxv32i8.nxv64i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 64 x i8> [[VS]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
-//
-vint8m4_t test_vunzipo_v_i8m4_tum(vbool2_t vm, vint8m4_t vd, vint8m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vunzipo_v_i16mf4_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vunzipo.mask.nxv1i16.nxv2i16.i64(<vscale x 1 x i16> [[VD]], <vscale x 2 x i16> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
-//
-vint16mf4_t test_vunzipo_v_i16mf4_tum(vbool64_t vm, vint16mf4_t vd,
- vint16mf2_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vunzipo_v_i16mf2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vunzipo.mask.nxv2i16.nxv4i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 4 x i16> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
-//
-vint16mf2_t test_vunzipo_v_i16mf2_tum(vbool32_t vm, vint16mf2_t vd,
- vint16m1_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vunzipo_v_i16m1_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vunzipo.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 8 x i16> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
-//
-vint16m1_t test_vunzipo_v_i16m1_tum(vbool16_t vm, vint16m1_t vd, vint16m2_t vs,
- size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vunzipo_v_i16m2_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vunzipo.mask.nxv8i16.nxv16i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 16 x i16> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-vint16m2_t test_vunzipo_v_i16m2_tum(vbool8_t vm, vint16m2_t vd, vint16m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vunzipo_v_i16m4_tum
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vunzipo.mask.nxv16i16.nxv32i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 32 x i16> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
-//
-vint16m4_t test_vunzipo_v_i16m4_tum(vbool4_t vm, vint16m4_t vd, vint16m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vunzipo_v_i32mf2_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vunzipo.mask.nxv1i32.nxv2i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 2 x i32> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vunzipo_v_i32mf2_tum(vbool64_t vm, vint32mf2_t vd,
- vint32m1_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vunzipo_v_i32m1_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vunzipo.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 4 x i32> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vunzipo_v_i32m1_tum(vbool32_t vm, vint32m1_t vd, vint32m2_t vs,
- size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vunzipo_v_i32m2_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vunzipo.mask.nxv4i32.nxv8i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i32> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vunzipo_v_i32m2_tum(vbool16_t vm, vint32m2_t vd, vint32m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vunzipo_v_i32m4_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vunzipo.mask.nxv8i32.nxv16i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 16 x i32> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vunzipo_v_i32m4_tum(vbool8_t vm, vint32m4_t vd, vint32m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vunzipo_v_i64m1_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vunzipo.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> [[VD]], <vscale x 2 x i64> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
-//
-vint64m1_t test_vunzipo_v_i64m1_tum(vbool64_t vm, vint64m1_t vd, vint64m2_t vs,
- size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vunzipo_v_i64m2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vunzipo.mask.nxv2i64.nxv4i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 4 x i64> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-vint64m2_t test_vunzipo_v_i64m2_tum(vbool32_t vm, vint64m2_t vd, vint64m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vunzipo_v_i64m4_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vunzipo.mask.nxv4i64.nxv8i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 8 x i64> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
-//
-vint64m4_t test_vunzipo_v_i64m4_tum(vbool16_t vm, vint64m4_t vd, vint64m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vunzipo_v_u8mf8_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vunzipo.mask.nxv1i8.nxv2i8.i64(<vscale x 1 x i8> [[VD]], <vscale x 2 x i8> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
-//
-vuint8mf8_t test_vunzipo_v_u8mf8_tum(vbool64_t vm, vuint8mf8_t vd,
- vuint8mf4_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vunzipo_v_u8mf4_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vunzipo.mask.nxv2i8.nxv4i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 4 x i8> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
-//
-vuint8mf4_t test_vunzipo_v_u8mf4_tum(vbool32_t vm, vuint8mf4_t vd,
- vuint8mf2_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vunzipo_v_u8mf2_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vunzipo.mask.nxv4i8.nxv8i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 8 x i8> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
-//
-vuint8mf2_t test_vunzipo_v_u8mf2_tum(vbool16_t vm, vuint8mf2_t vd,
- vuint8m1_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vunzipo_v_u8m1_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vunzipo.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 16 x i8> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
-//
-vuint8m1_t test_vunzipo_v_u8m1_tum(vbool8_t vm, vuint8m1_t vd, vuint8m2_t vs,
- size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vunzipo_v_u8m2_tum
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vunzipo.mask.nxv16i8.nxv32i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 32 x i8> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-vuint8m2_t test_vunzipo_v_u8m2_tum(vbool4_t vm, vuint8m2_t vd, vuint8m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vunzipo_v_u8m4_tum
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vunzipo.mask.nxv32i8.nxv64i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 64 x i8> [[VS]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
-//
-vuint8m4_t test_vunzipo_v_u8m4_tum(vbool2_t vm, vuint8m4_t vd, vuint8m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vunzipo_v_u16mf4_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vunzipo.mask.nxv1i16.nxv2i16.i64(<vscale x 1 x i16> [[VD]], <vscale x 2 x i16> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
-//
-vuint16mf4_t test_vunzipo_v_u16mf4_tum(vbool64_t vm, vuint16mf4_t vd,
- vuint16mf2_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vunzipo_v_u16mf2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vunzipo.mask.nxv2i16.nxv4i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 4 x i16> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
-//
-vuint16mf2_t test_vunzipo_v_u16mf2_tum(vbool32_t vm, vuint16mf2_t vd,
- vuint16m1_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vunzipo_v_u16m1_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vunzipo.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 8 x i16> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
-//
-vuint16m1_t test_vunzipo_v_u16m1_tum(vbool16_t vm, vuint16m1_t vd,
- vuint16m2_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vunzipo_v_u16m2_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vunzipo.mask.nxv8i16.nxv16i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 16 x i16> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-vuint16m2_t test_vunzipo_v_u16m2_tum(vbool8_t vm, vuint16m2_t vd,
- vuint16m4_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vunzipo_v_u16m4_tum
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vunzipo.mask.nxv16i16.nxv32i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 32 x i16> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
-//
-vuint16m4_t test_vunzipo_v_u16m4_tum(vbool4_t vm, vuint16m4_t vd,
- vuint16m8_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vunzipo_v_u32mf2_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vunzipo.mask.nxv1i32.nxv2i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 2 x i32> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vuint32mf2_t test_vunzipo_v_u32mf2_tum(vbool64_t vm, vuint32mf2_t vd,
- vuint32m1_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vunzipo_v_u32m1_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vunzipo.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 4 x i32> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vuint32m1_t test_vunzipo_v_u32m1_tum(vbool32_t vm, vuint32m1_t vd,
- vuint32m2_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vunzipo_v_u32m2_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vunzipo.mask.nxv4i32.nxv8i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i32> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vuint32m2_t test_vunzipo_v_u32m2_tum(vbool16_t vm, vuint32m2_t vd,
- vuint32m4_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vunzipo_v_u32m4_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vunzipo.mask.nxv8i32.nxv16i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 16 x i32> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vuint32m4_t test_vunzipo_v_u32m4_tum(vbool8_t vm, vuint32m4_t vd,
- vuint32m8_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vunzipo_v_u64m1_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vunzipo.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> [[VD]], <vscale x 2 x i64> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
-//
-vuint64m1_t test_vunzipo_v_u64m1_tum(vbool64_t vm, vuint64m1_t vd,
- vuint64m2_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vunzipo_v_u64m2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vunzipo.mask.nxv2i64.nxv4i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 4 x i64> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-vuint64m2_t test_vunzipo_v_u64m2_tum(vbool32_t vm, vuint64m2_t vd,
- vuint64m4_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vunzipo_v_u64m4_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vunzipo.mask.nxv4i64.nxv8i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 8 x i64> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
-//
-vuint64m4_t test_vunzipo_v_u64m4_tum(vbool16_t vm, vuint64m4_t vd,
- vuint64m8_t vs, size_t vl) {
- return __riscv_vunzipo_tum(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vunzipo_v_f16mf4_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 2 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vunzipo.mask.nxv1f16.nxv2f16.i64(<vscale x 1 x half> [[VD]], <vscale x 2 x half> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
-//
-vfloat16mf4_t test_vunzipo_v_f16mf4_tumu(vbool64_t vm, vfloat16mf4_t vd,
- vfloat16mf2_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vunzipo_v_f16mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 4 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vunzipo.mask.nxv2f16.nxv4f16.i64(<vscale x 2 x half> [[VD]], <vscale x 4 x half> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
-//
-vfloat16mf2_t test_vunzipo_v_f16mf2_tumu(vbool32_t vm, vfloat16mf2_t vd,
- vfloat16m1_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vunzipo_v_f16m1_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 8 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vunzipo.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[VD]], <vscale x 8 x half> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
-//
-vfloat16m1_t test_vunzipo_v_f16m1_tumu(vbool16_t vm, vfloat16m1_t vd,
- vfloat16m2_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vunzipo_v_f16m2_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 16 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vunzipo.mask.nxv8f16.nxv16f16.i64(<vscale x 8 x half> [[VD]], <vscale x 16 x half> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
-//
-vfloat16m2_t test_vunzipo_v_f16m2_tumu(vbool8_t vm, vfloat16m2_t vd,
- vfloat16m4_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vunzipo_v_f16m4_tumu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 32 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vunzipo.mask.nxv16f16.nxv32f16.i64(<vscale x 16 x half> [[VD]], <vscale x 32 x half> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
-//
-vfloat16m4_t test_vunzipo_v_f16m4_tumu(vbool4_t vm, vfloat16m4_t vd,
- vfloat16m8_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vunzipo_v_f32mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 2 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vunzipo.mask.nxv1f32.nxv2f32.i64(<vscale x 1 x float> [[VD]], <vscale x 2 x float> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
-//
-vfloat32mf2_t test_vunzipo_v_f32mf2_tumu(vbool64_t vm, vfloat32mf2_t vd,
- vfloat32m1_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vunzipo_v_f32m1_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 4 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vunzipo.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[VD]], <vscale x 4 x float> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
-//
-vfloat32m1_t test_vunzipo_v_f32m1_tumu(vbool32_t vm, vfloat32m1_t vd,
- vfloat32m2_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vunzipo_v_f32m2_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 8 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vunzipo.mask.nxv4f32.nxv8f32.i64(<vscale x 4 x float> [[VD]], <vscale x 8 x float> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
-//
-vfloat32m2_t test_vunzipo_v_f32m2_tumu(vbool16_t vm, vfloat32m2_t vd,
- vfloat32m4_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vunzipo_v_f32m4_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 16 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vunzipo.mask.nxv8f32.nxv16f32.i64(<vscale x 8 x float> [[VD]], <vscale x 16 x float> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
-//
-vfloat32m4_t test_vunzipo_v_f32m4_tumu(vbool8_t vm, vfloat32m4_t vd,
- vfloat32m8_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vunzipo_v_f64m1_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 2 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vunzipo.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[VD]], <vscale x 2 x double> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
-//
-vfloat64m1_t test_vunzipo_v_f64m1_tumu(vbool64_t vm, vfloat64m1_t vd,
- vfloat64m2_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vunzipo_v_f64m2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 4 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vunzipo.mask.nxv2f64.nxv4f64.i64(<vscale x 2 x double> [[VD]], <vscale x 4 x double> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
-//
-vfloat64m2_t test_vunzipo_v_f64m2_tumu(vbool32_t vm, vfloat64m2_t vd,
- vfloat64m4_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vunzipo_v_f64m4_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 8 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vunzipo.mask.nxv4f64.nxv8f64.i64(<vscale x 4 x double> [[VD]], <vscale x 8 x double> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
-//
-vfloat64m4_t test_vunzipo_v_f64m4_tumu(vbool16_t vm, vfloat64m4_t vd,
- vfloat64m8_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vunzipo_v_i8mf8_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vunzipo.mask.nxv1i8.nxv2i8.i64(<vscale x 1 x i8> [[VD]], <vscale x 2 x i8> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
-//
-vint8mf8_t test_vunzipo_v_i8mf8_tumu(vbool64_t vm, vint8mf8_t vd, vint8mf4_t vs,
- size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vunzipo_v_i8mf4_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vunzipo.mask.nxv2i8.nxv4i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 4 x i8> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
-//
-vint8mf4_t test_vunzipo_v_i8mf4_tumu(vbool32_t vm, vint8mf4_t vd, vint8mf2_t vs,
- size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vunzipo_v_i8mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vunzipo.mask.nxv4i8.nxv8i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 8 x i8> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
-//
-vint8mf2_t test_vunzipo_v_i8mf2_tumu(vbool16_t vm, vint8mf2_t vd, vint8m1_t vs,
- size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vunzipo_v_i8m1_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vunzipo.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 16 x i8> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
-//
-vint8m1_t test_vunzipo_v_i8m1_tumu(vbool8_t vm, vint8m1_t vd, vint8m2_t vs,
- size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vunzipo_v_i8m2_tumu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vunzipo.mask.nxv16i8.nxv32i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 32 x i8> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-vint8m2_t test_vunzipo_v_i8m2_tumu(vbool4_t vm, vint8m2_t vd, vint8m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vunzipo_v_i8m4_tumu
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vunzipo.mask.nxv32i8.nxv64i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 64 x i8> [[VS]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
-//
-vint8m4_t test_vunzipo_v_i8m4_tumu(vbool2_t vm, vint8m4_t vd, vint8m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vunzipo_v_i16mf4_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vunzipo.mask.nxv1i16.nxv2i16.i64(<vscale x 1 x i16> [[VD]], <vscale x 2 x i16> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
-//
-vint16mf4_t test_vunzipo_v_i16mf4_tumu(vbool64_t vm, vint16mf4_t vd,
- vint16mf2_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vunzipo_v_i16mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vunzipo.mask.nxv2i16.nxv4i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 4 x i16> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
-//
-vint16mf2_t test_vunzipo_v_i16mf2_tumu(vbool32_t vm, vint16mf2_t vd,
- vint16m1_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vunzipo_v_i16m1_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vunzipo.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 8 x i16> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
-//
-vint16m1_t test_vunzipo_v_i16m1_tumu(vbool16_t vm, vint16m1_t vd, vint16m2_t vs,
- size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vunzipo_v_i16m2_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vunzipo.mask.nxv8i16.nxv16i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 16 x i16> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-vint16m2_t test_vunzipo_v_i16m2_tumu(vbool8_t vm, vint16m2_t vd, vint16m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vunzipo_v_i16m4_tumu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vunzipo.mask.nxv16i16.nxv32i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 32 x i16> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
-//
-vint16m4_t test_vunzipo_v_i16m4_tumu(vbool4_t vm, vint16m4_t vd, vint16m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vunzipo_v_i32mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vunzipo.mask.nxv1i32.nxv2i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 2 x i32> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vunzipo_v_i32mf2_tumu(vbool64_t vm, vint32mf2_t vd,
- vint32m1_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vunzipo_v_i32m1_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vunzipo.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 4 x i32> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vunzipo_v_i32m1_tumu(vbool32_t vm, vint32m1_t vd, vint32m2_t vs,
- size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vunzipo_v_i32m2_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vunzipo.mask.nxv4i32.nxv8i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i32> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vunzipo_v_i32m2_tumu(vbool16_t vm, vint32m2_t vd, vint32m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vunzipo_v_i32m4_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vunzipo.mask.nxv8i32.nxv16i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 16 x i32> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vunzipo_v_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vint32m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vunzipo_v_i64m1_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vunzipo.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> [[VD]], <vscale x 2 x i64> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
-//
-vint64m1_t test_vunzipo_v_i64m1_tumu(vbool64_t vm, vint64m1_t vd, vint64m2_t vs,
- size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vunzipo_v_i64m2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vunzipo.mask.nxv2i64.nxv4i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 4 x i64> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-vint64m2_t test_vunzipo_v_i64m2_tumu(vbool32_t vm, vint64m2_t vd, vint64m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vunzipo_v_i64m4_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vunzipo.mask.nxv4i64.nxv8i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 8 x i64> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
-//
-vint64m4_t test_vunzipo_v_i64m4_tumu(vbool16_t vm, vint64m4_t vd, vint64m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vunzipo_v_u8mf8_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vunzipo.mask.nxv1i8.nxv2i8.i64(<vscale x 1 x i8> [[VD]], <vscale x 2 x i8> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
-//
-vuint8mf8_t test_vunzipo_v_u8mf8_tumu(vbool64_t vm, vuint8mf8_t vd,
- vuint8mf4_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vunzipo_v_u8mf4_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vunzipo.mask.nxv2i8.nxv4i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 4 x i8> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
-//
-vuint8mf4_t test_vunzipo_v_u8mf4_tumu(vbool32_t vm, vuint8mf4_t vd,
- vuint8mf2_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vunzipo_v_u8mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vunzipo.mask.nxv4i8.nxv8i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 8 x i8> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
-//
-vuint8mf2_t test_vunzipo_v_u8mf2_tumu(vbool16_t vm, vuint8mf2_t vd,
- vuint8m1_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vunzipo_v_u8m1_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vunzipo.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 16 x i8> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
-//
-vuint8m1_t test_vunzipo_v_u8m1_tumu(vbool8_t vm, vuint8m1_t vd, vuint8m2_t vs,
- size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vunzipo_v_u8m2_tumu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vunzipo.mask.nxv16i8.nxv32i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 32 x i8> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-vuint8m2_t test_vunzipo_v_u8m2_tumu(vbool4_t vm, vuint8m2_t vd, vuint8m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vunzipo_v_u8m4_tumu
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vunzipo.mask.nxv32i8.nxv64i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 64 x i8> [[VS]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
-//
-vuint8m4_t test_vunzipo_v_u8m4_tumu(vbool2_t vm, vuint8m4_t vd, vuint8m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vunzipo_v_u16mf4_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vunzipo.mask.nxv1i16.nxv2i16.i64(<vscale x 1 x i16> [[VD]], <vscale x 2 x i16> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
-//
-vuint16mf4_t test_vunzipo_v_u16mf4_tumu(vbool64_t vm, vuint16mf4_t vd,
- vuint16mf2_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vunzipo_v_u16mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vunzipo.mask.nxv2i16.nxv4i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 4 x i16> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
-//
-vuint16mf2_t test_vunzipo_v_u16mf2_tumu(vbool32_t vm, vuint16mf2_t vd,
- vuint16m1_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vunzipo_v_u16m1_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vunzipo.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 8 x i16> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
-//
-vuint16m1_t test_vunzipo_v_u16m1_tumu(vbool16_t vm, vuint16m1_t vd,
- vuint16m2_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vunzipo_v_u16m2_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vunzipo.mask.nxv8i16.nxv16i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 16 x i16> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-vuint16m2_t test_vunzipo_v_u16m2_tumu(vbool8_t vm, vuint16m2_t vd,
- vuint16m4_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vunzipo_v_u16m4_tumu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vunzipo.mask.nxv16i16.nxv32i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 32 x i16> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
-//
-vuint16m4_t test_vunzipo_v_u16m4_tumu(vbool4_t vm, vuint16m4_t vd,
- vuint16m8_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vunzipo_v_u32mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vunzipo.mask.nxv1i32.nxv2i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 2 x i32> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vuint32mf2_t test_vunzipo_v_u32mf2_tumu(vbool64_t vm, vuint32mf2_t vd,
- vuint32m1_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vunzipo_v_u32m1_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vunzipo.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 4 x i32> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vuint32m1_t test_vunzipo_v_u32m1_tumu(vbool32_t vm, vuint32m1_t vd,
- vuint32m2_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vunzipo_v_u32m2_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vunzipo.mask.nxv4i32.nxv8i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i32> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vuint32m2_t test_vunzipo_v_u32m2_tumu(vbool16_t vm, vuint32m2_t vd,
- vuint32m4_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vunzipo_v_u32m4_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vunzipo.mask.nxv8i32.nxv16i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 16 x i32> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vuint32m4_t test_vunzipo_v_u32m4_tumu(vbool8_t vm, vuint32m4_t vd,
- vuint32m8_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vunzipo_v_u64m1_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vunzipo.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> [[VD]], <vscale x 2 x i64> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
-//
-vuint64m1_t test_vunzipo_v_u64m1_tumu(vbool64_t vm, vuint64m1_t vd,
- vuint64m2_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vunzipo_v_u64m2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vunzipo.mask.nxv2i64.nxv4i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 4 x i64> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-vuint64m2_t test_vunzipo_v_u64m2_tumu(vbool32_t vm, vuint64m2_t vd,
- vuint64m4_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vunzipo_v_u64m4_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vunzipo.mask.nxv4i64.nxv8i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 8 x i64> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
-//
-vuint64m4_t test_vunzipo_v_u64m4_tumu(vbool16_t vm, vuint64m4_t vd,
- vuint64m8_t vs, size_t vl) {
- return __riscv_vunzipo_tumu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vunzipo_v_f16mf4_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 2 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vunzipo.mask.nxv1f16.nxv2f16.i64(<vscale x 1 x half> [[VD]], <vscale x 2 x half> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
-//
-vfloat16mf4_t test_vunzipo_v_f16mf4_mu(vbool64_t vm, vfloat16mf4_t vd,
- vfloat16mf2_t vs, size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vunzipo_v_f16mf2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 4 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vunzipo.mask.nxv2f16.nxv4f16.i64(<vscale x 2 x half> [[VD]], <vscale x 4 x half> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
-//
-vfloat16mf2_t test_vunzipo_v_f16mf2_mu(vbool32_t vm, vfloat16mf2_t vd,
- vfloat16m1_t vs, size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vunzipo_v_f16m1_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 8 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vunzipo.mask.nxv4f16.nxv8f16.i64(<vscale x 4 x half> [[VD]], <vscale x 8 x half> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
-//
-vfloat16m1_t test_vunzipo_v_f16m1_mu(vbool16_t vm, vfloat16m1_t vd,
- vfloat16m2_t vs, size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vunzipo_v_f16m2_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 16 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vunzipo.mask.nxv8f16.nxv16f16.i64(<vscale x 8 x half> [[VD]], <vscale x 16 x half> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
-//
-vfloat16m2_t test_vunzipo_v_f16m2_mu(vbool8_t vm, vfloat16m2_t vd,
- vfloat16m4_t vs, size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vunzipo_v_f16m4_mu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 32 x half> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vunzipo.mask.nxv16f16.nxv32f16.i64(<vscale x 16 x half> [[VD]], <vscale x 32 x half> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
-//
-vfloat16m4_t test_vunzipo_v_f16m4_mu(vbool4_t vm, vfloat16m4_t vd,
- vfloat16m8_t vs, size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vunzipo_v_f32mf2_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 2 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vunzipo.mask.nxv1f32.nxv2f32.i64(<vscale x 1 x float> [[VD]], <vscale x 2 x float> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
-//
-vfloat32mf2_t test_vunzipo_v_f32mf2_mu(vbool64_t vm, vfloat32mf2_t vd,
- vfloat32m1_t vs, size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vunzipo_v_f32m1_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 4 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vunzipo.mask.nxv2f32.nxv4f32.i64(<vscale x 2 x float> [[VD]], <vscale x 4 x float> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
-//
-vfloat32m1_t test_vunzipo_v_f32m1_mu(vbool32_t vm, vfloat32m1_t vd,
- vfloat32m2_t vs, size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vunzipo_v_f32m2_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 8 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vunzipo.mask.nxv4f32.nxv8f32.i64(<vscale x 4 x float> [[VD]], <vscale x 8 x float> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
-//
-vfloat32m2_t test_vunzipo_v_f32m2_mu(vbool16_t vm, vfloat32m2_t vd,
- vfloat32m4_t vs, size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vunzipo_v_f32m4_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 16 x float> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vunzipo.mask.nxv8f32.nxv16f32.i64(<vscale x 8 x float> [[VD]], <vscale x 16 x float> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
-//
-vfloat32m4_t test_vunzipo_v_f32m4_mu(vbool8_t vm, vfloat32m4_t vd,
- vfloat32m8_t vs, size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vunzipo_v_f64m1_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 2 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vunzipo.mask.nxv1f64.nxv2f64.i64(<vscale x 1 x double> [[VD]], <vscale x 2 x double> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
-//
-vfloat64m1_t test_vunzipo_v_f64m1_mu(vbool64_t vm, vfloat64m1_t vd,
- vfloat64m2_t vs, size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vunzipo_v_f64m2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 4 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vunzipo.mask.nxv2f64.nxv4f64.i64(<vscale x 2 x double> [[VD]], <vscale x 4 x double> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
-//
-vfloat64m2_t test_vunzipo_v_f64m2_mu(vbool32_t vm, vfloat64m2_t vd,
- vfloat64m4_t vs, size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vunzipo_v_f64m4_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 8 x double> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vunzipo.mask.nxv4f64.nxv8f64.i64(<vscale x 4 x double> [[VD]], <vscale x 8 x double> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
-//
-vfloat64m4_t test_vunzipo_v_f64m4_mu(vbool16_t vm, vfloat64m4_t vd,
- vfloat64m8_t vs, size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vunzipo_v_i8mf8_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vunzipo.mask.nxv1i8.nxv2i8.i64(<vscale x 1 x i8> [[VD]], <vscale x 2 x i8> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
-//
-vint8mf8_t test_vunzipo_v_i8mf8_mu(vbool64_t vm, vint8mf8_t vd, vint8mf4_t vs,
- size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vunzipo_v_i8mf4_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vunzipo.mask.nxv2i8.nxv4i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 4 x i8> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
-//
-vint8mf4_t test_vunzipo_v_i8mf4_mu(vbool32_t vm, vint8mf4_t vd, vint8mf2_t vs,
- size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vunzipo_v_i8mf2_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vunzipo.mask.nxv4i8.nxv8i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 8 x i8> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
-//
-vint8mf2_t test_vunzipo_v_i8mf2_mu(vbool16_t vm, vint8mf2_t vd, vint8m1_t vs,
- size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vunzipo_v_i8m1_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vunzipo.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 16 x i8> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
-//
-vint8m1_t test_vunzipo_v_i8m1_mu(vbool8_t vm, vint8m1_t vd, vint8m2_t vs,
- size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vunzipo_v_i8m2_mu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vunzipo.mask.nxv16i8.nxv32i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 32 x i8> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-vint8m2_t test_vunzipo_v_i8m2_mu(vbool4_t vm, vint8m2_t vd, vint8m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vunzipo_v_i8m4_mu
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vunzipo.mask.nxv32i8.nxv64i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 64 x i8> [[VS]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
-//
-vint8m4_t test_vunzipo_v_i8m4_mu(vbool2_t vm, vint8m4_t vd, vint8m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vunzipo_v_i16mf4_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vunzipo.mask.nxv1i16.nxv2i16.i64(<vscale x 1 x i16> [[VD]], <vscale x 2 x i16> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
-//
-vint16mf4_t test_vunzipo_v_i16mf4_mu(vbool64_t vm, vint16mf4_t vd,
- vint16mf2_t vs, size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vunzipo_v_i16mf2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vunzipo.mask.nxv2i16.nxv4i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 4 x i16> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
-//
-vint16mf2_t test_vunzipo_v_i16mf2_mu(vbool32_t vm, vint16mf2_t vd,
- vint16m1_t vs, size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vunzipo_v_i16m1_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vunzipo.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 8 x i16> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
-//
-vint16m1_t test_vunzipo_v_i16m1_mu(vbool16_t vm, vint16m1_t vd, vint16m2_t vs,
- size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vunzipo_v_i16m2_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vunzipo.mask.nxv8i16.nxv16i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 16 x i16> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-vint16m2_t test_vunzipo_v_i16m2_mu(vbool8_t vm, vint16m2_t vd, vint16m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vunzipo_v_i16m4_mu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vunzipo.mask.nxv16i16.nxv32i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 32 x i16> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
-//
-vint16m4_t test_vunzipo_v_i16m4_mu(vbool4_t vm, vint16m4_t vd, vint16m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vunzipo_v_i32mf2_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vunzipo.mask.nxv1i32.nxv2i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 2 x i32> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vint32mf2_t test_vunzipo_v_i32mf2_mu(vbool64_t vm, vint32mf2_t vd,
- vint32m1_t vs, size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vunzipo_v_i32m1_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vunzipo.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 4 x i32> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vint32m1_t test_vunzipo_v_i32m1_mu(vbool32_t vm, vint32m1_t vd, vint32m2_t vs,
- size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vunzipo_v_i32m2_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vunzipo.mask.nxv4i32.nxv8i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i32> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vint32m2_t test_vunzipo_v_i32m2_mu(vbool16_t vm, vint32m2_t vd, vint32m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vunzipo_v_i32m4_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vunzipo.mask.nxv8i32.nxv16i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 16 x i32> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vint32m4_t test_vunzipo_v_i32m4_mu(vbool8_t vm, vint32m4_t vd, vint32m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vunzipo_v_i64m1_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vunzipo.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> [[VD]], <vscale x 2 x i64> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
-//
-vint64m1_t test_vunzipo_v_i64m1_mu(vbool64_t vm, vint64m1_t vd, vint64m2_t vs,
- size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vunzipo_v_i64m2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vunzipo.mask.nxv2i64.nxv4i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 4 x i64> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-vint64m2_t test_vunzipo_v_i64m2_mu(vbool32_t vm, vint64m2_t vd, vint64m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vunzipo_v_i64m4_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vunzipo.mask.nxv4i64.nxv8i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 8 x i64> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
-//
-vint64m4_t test_vunzipo_v_i64m4_mu(vbool16_t vm, vint64m4_t vd, vint64m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vunzipo_v_u8mf8_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vunzipo.mask.nxv1i8.nxv2i8.i64(<vscale x 1 x i8> [[VD]], <vscale x 2 x i8> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
-//
-vuint8mf8_t test_vunzipo_v_u8mf8_mu(vbool64_t vm, vuint8mf8_t vd,
- vuint8mf4_t vs, size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vunzipo_v_u8mf4_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vunzipo.mask.nxv2i8.nxv4i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 4 x i8> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
-//
-vuint8mf4_t test_vunzipo_v_u8mf4_mu(vbool32_t vm, vuint8mf4_t vd,
- vuint8mf2_t vs, size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vunzipo_v_u8mf2_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vunzipo.mask.nxv4i8.nxv8i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 8 x i8> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
-//
-vuint8mf2_t test_vunzipo_v_u8mf2_mu(vbool16_t vm, vuint8mf2_t vd, vuint8m1_t vs,
- size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vunzipo_v_u8m1_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vunzipo.mask.nxv8i8.nxv16i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 16 x i8> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
-//
-vuint8m1_t test_vunzipo_v_u8m1_mu(vbool8_t vm, vuint8m1_t vd, vuint8m2_t vs,
- size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vunzipo_v_u8m2_mu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vunzipo.mask.nxv16i8.nxv32i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 32 x i8> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-vuint8m2_t test_vunzipo_v_u8m2_mu(vbool4_t vm, vuint8m2_t vd, vuint8m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vunzipo_v_u8m4_mu
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 64 x i8> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vunzipo.mask.nxv32i8.nxv64i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 64 x i8> [[VS]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
-//
-vuint8m4_t test_vunzipo_v_u8m4_mu(vbool2_t vm, vuint8m4_t vd, vuint8m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vunzipo_v_u16mf4_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vunzipo.mask.nxv1i16.nxv2i16.i64(<vscale x 1 x i16> [[VD]], <vscale x 2 x i16> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
-//
-vuint16mf4_t test_vunzipo_v_u16mf4_mu(vbool64_t vm, vuint16mf4_t vd,
- vuint16mf2_t vs, size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vunzipo_v_u16mf2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vunzipo.mask.nxv2i16.nxv4i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 4 x i16> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
-//
-vuint16mf2_t test_vunzipo_v_u16mf2_mu(vbool32_t vm, vuint16mf2_t vd,
- vuint16m1_t vs, size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vunzipo_v_u16m1_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vunzipo.mask.nxv4i16.nxv8i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 8 x i16> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
-//
-vuint16m1_t test_vunzipo_v_u16m1_mu(vbool16_t vm, vuint16m1_t vd,
- vuint16m2_t vs, size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vunzipo_v_u16m2_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vunzipo.mask.nxv8i16.nxv16i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 16 x i16> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-vuint16m2_t test_vunzipo_v_u16m2_mu(vbool8_t vm, vuint16m2_t vd, vuint16m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vunzipo_v_u16m4_mu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 32 x i16> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vunzipo.mask.nxv16i16.nxv32i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 32 x i16> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
-//
-vuint16m4_t test_vunzipo_v_u16m4_mu(vbool4_t vm, vuint16m4_t vd, vuint16m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vunzipo_v_u32mf2_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vunzipo.mask.nxv1i32.nxv2i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 2 x i32> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
-//
-vuint32mf2_t test_vunzipo_v_u32mf2_mu(vbool64_t vm, vuint32mf2_t vd,
- vuint32m1_t vs, size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vunzipo_v_u32m1_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vunzipo.mask.nxv2i32.nxv4i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 4 x i32> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
-//
-vuint32m1_t test_vunzipo_v_u32m1_mu(vbool32_t vm, vuint32m1_t vd,
- vuint32m2_t vs, size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vunzipo_v_u32m2_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vunzipo.mask.nxv4i32.nxv8i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i32> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-vuint32m2_t test_vunzipo_v_u32m2_mu(vbool16_t vm, vuint32m2_t vd,
- vuint32m4_t vs, size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vunzipo_v_u32m4_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vunzipo.mask.nxv8i32.nxv16i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 16 x i32> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
-//
-vuint32m4_t test_vunzipo_v_u32m4_mu(vbool8_t vm, vuint32m4_t vd, vuint32m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vunzipo_v_u64m1_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vunzipo.mask.nxv1i64.nxv2i64.i64(<vscale x 1 x i64> [[VD]], <vscale x 2 x i64> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
-//
-vuint64m1_t test_vunzipo_v_u64m1_mu(vbool64_t vm, vuint64m1_t vd,
- vuint64m2_t vs, size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vunzipo_v_u64m2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vunzipo.mask.nxv2i64.nxv4i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 4 x i64> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-vuint64m2_t test_vunzipo_v_u64m2_mu(vbool32_t vm, vuint64m2_t vd,
- vuint64m4_t vs, size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vunzipo_v_u64m4_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vunzipo.mask.nxv4i64.nxv8i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 8 x i64> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
-// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
-//
-vuint64m4_t test_vunzipo_v_u64m4_mu(vbool16_t vm, vuint64m4_t vd,
- vuint64m8_t vs, size_t vl) {
- return __riscv_vunzipo_mu(vm, vd, vs, vl);
-}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c
index 312be0dc4055e..3b0b166c9ad99 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c
@@ -538,1652 +538,1652 @@ vuint64m8_t test_vzip_vv_u64m8_tu(vuint64m8_t vd, vuint64m4_t vs2,
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vzip_vv_f16mf2_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vzip.mask.nxv2f16.nxv1f16.i64(<vscale x 2 x half> [[VD]], <vscale x 1 x half> [[VS2]], <vscale x 1 x half> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vzip.mask.nxv2f16.nxv1f16.i64(<vscale x 2 x half> [[VD]], <vscale x 1 x half> [[VS2]], <vscale x 1 x half> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
-vfloat16mf2_t test_vzip_vv_f16mf2_tum(vbool64_t vm, vfloat16mf2_t vd,
+vfloat16mf2_t test_vzip_vv_f16mf2_tum(vbool32_t vm, vfloat16mf2_t vd,
vfloat16mf4_t vs2, vfloat16mf4_t vs1,
size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vzip_vv_f16m1_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vzip.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[VD]], <vscale x 2 x half> [[VS2]], <vscale x 2 x half> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vzip.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[VD]], <vscale x 2 x half> [[VS2]], <vscale x 2 x half> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
-vfloat16m1_t test_vzip_vv_f16m1_tum(vbool32_t vm, vfloat16m1_t vd,
+vfloat16m1_t test_vzip_vv_f16m1_tum(vbool16_t vm, vfloat16m1_t vd,
vfloat16mf2_t vs2, vfloat16mf2_t vs1,
size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vzip_vv_f16m2_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vzip.mask.nxv8f16.nxv4f16.i64(<vscale x 8 x half> [[VD]], <vscale x 4 x half> [[VS2]], <vscale x 4 x half> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vzip.mask.nxv8f16.nxv4f16.i64(<vscale x 8 x half> [[VD]], <vscale x 4 x half> [[VS2]], <vscale x 4 x half> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
-vfloat16m2_t test_vzip_vv_f16m2_tum(vbool16_t vm, vfloat16m2_t vd,
+vfloat16m2_t test_vzip_vv_f16m2_tum(vbool8_t vm, vfloat16m2_t vd,
vfloat16m1_t vs2, vfloat16m1_t vs1,
size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vzip_vv_f16m4_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vzip.mask.nxv16f16.nxv8f16.i64(<vscale x 16 x half> [[VD]], <vscale x 8 x half> [[VS2]], <vscale x 8 x half> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vzip.mask.nxv16f16.nxv8f16.i64(<vscale x 16 x half> [[VD]], <vscale x 8 x half> [[VS2]], <vscale x 8 x half> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
-vfloat16m4_t test_vzip_vv_f16m4_tum(vbool8_t vm, vfloat16m4_t vd,
+vfloat16m4_t test_vzip_vv_f16m4_tum(vbool4_t vm, vfloat16m4_t vd,
vfloat16m2_t vs2, vfloat16m2_t vs1,
size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vzip_vv_f16m8_tum
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vzip.mask.nxv32f16.nxv16f16.i64(<vscale x 32 x half> [[VD]], <vscale x 16 x half> [[VS2]], <vscale x 16 x half> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vzip.mask.nxv32f16.nxv16f16.i64(<vscale x 32 x half> [[VD]], <vscale x 16 x half> [[VS2]], <vscale x 16 x half> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
-vfloat16m8_t test_vzip_vv_f16m8_tum(vbool4_t vm, vfloat16m8_t vd,
+vfloat16m8_t test_vzip_vv_f16m8_tum(vbool2_t vm, vfloat16m8_t vd,
vfloat16m4_t vs2, vfloat16m4_t vs1,
size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vzip_vv_f32m1_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 1 x float> [[VS2:%.*]], <vscale x 1 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 1 x float> [[VS2:%.*]], <vscale x 1 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vzip.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[VD]], <vscale x 1 x float> [[VS2]], <vscale x 1 x float> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vzip.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[VD]], <vscale x 1 x float> [[VS2]], <vscale x 1 x float> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
-vfloat32m1_t test_vzip_vv_f32m1_tum(vbool64_t vm, vfloat32m1_t vd,
+vfloat32m1_t test_vzip_vv_f32m1_tum(vbool32_t vm, vfloat32m1_t vd,
vfloat32mf2_t vs2, vfloat32mf2_t vs1,
size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vzip_vv_f32m2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 2 x float> [[VS2:%.*]], <vscale x 2 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 2 x float> [[VS2:%.*]], <vscale x 2 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vzip.mask.nxv4f32.nxv2f32.i64(<vscale x 4 x float> [[VD]], <vscale x 2 x float> [[VS2]], <vscale x 2 x float> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vzip.mask.nxv4f32.nxv2f32.i64(<vscale x 4 x float> [[VD]], <vscale x 2 x float> [[VS2]], <vscale x 2 x float> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
-vfloat32m2_t test_vzip_vv_f32m2_tum(vbool32_t vm, vfloat32m2_t vd,
+vfloat32m2_t test_vzip_vv_f32m2_tum(vbool16_t vm, vfloat32m2_t vd,
vfloat32m1_t vs2, vfloat32m1_t vs1,
size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vzip_vv_f32m4_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 4 x float> [[VS2:%.*]], <vscale x 4 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 4 x float> [[VS2:%.*]], <vscale x 4 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vzip.mask.nxv8f32.nxv4f32.i64(<vscale x 8 x float> [[VD]], <vscale x 4 x float> [[VS2]], <vscale x 4 x float> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vzip.mask.nxv8f32.nxv4f32.i64(<vscale x 8 x float> [[VD]], <vscale x 4 x float> [[VS2]], <vscale x 4 x float> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
-vfloat32m4_t test_vzip_vv_f32m4_tum(vbool16_t vm, vfloat32m4_t vd,
+vfloat32m4_t test_vzip_vv_f32m4_tum(vbool8_t vm, vfloat32m4_t vd,
vfloat32m2_t vs2, vfloat32m2_t vs1,
size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vzip_vv_f32m8_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 8 x float> [[VS2:%.*]], <vscale x 8 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 8 x float> [[VS2:%.*]], <vscale x 8 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vzip.mask.nxv16f32.nxv8f32.i64(<vscale x 16 x float> [[VD]], <vscale x 8 x float> [[VS2]], <vscale x 8 x float> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vzip.mask.nxv16f32.nxv8f32.i64(<vscale x 16 x float> [[VD]], <vscale x 8 x float> [[VS2]], <vscale x 8 x float> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
-vfloat32m8_t test_vzip_vv_f32m8_tum(vbool8_t vm, vfloat32m8_t vd,
+vfloat32m8_t test_vzip_vv_f32m8_tum(vbool4_t vm, vfloat32m8_t vd,
vfloat32m4_t vs2, vfloat32m4_t vs1,
size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vzip_vv_f64m2_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 1 x double> [[VS2:%.*]], <vscale x 1 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 1 x double> [[VS2:%.*]], <vscale x 1 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vzip.mask.nxv2f64.nxv1f64.i64(<vscale x 2 x double> [[VD]], <vscale x 1 x double> [[VS2]], <vscale x 1 x double> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vzip.mask.nxv2f64.nxv1f64.i64(<vscale x 2 x double> [[VD]], <vscale x 1 x double> [[VS2]], <vscale x 1 x double> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
-vfloat64m2_t test_vzip_vv_f64m2_tum(vbool64_t vm, vfloat64m2_t vd,
+vfloat64m2_t test_vzip_vv_f64m2_tum(vbool32_t vm, vfloat64m2_t vd,
vfloat64m1_t vs2, vfloat64m1_t vs1,
size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vzip_vv_f64m4_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 2 x double> [[VS2:%.*]], <vscale x 2 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 2 x double> [[VS2:%.*]], <vscale x 2 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vzip.mask.nxv4f64.nxv2f64.i64(<vscale x 4 x double> [[VD]], <vscale x 2 x double> [[VS2]], <vscale x 2 x double> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vzip.mask.nxv4f64.nxv2f64.i64(<vscale x 4 x double> [[VD]], <vscale x 2 x double> [[VS2]], <vscale x 2 x double> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
-vfloat64m4_t test_vzip_vv_f64m4_tum(vbool32_t vm, vfloat64m4_t vd,
+vfloat64m4_t test_vzip_vv_f64m4_tum(vbool16_t vm, vfloat64m4_t vd,
vfloat64m2_t vs2, vfloat64m2_t vs1,
size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vzip_vv_f64m8_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 4 x double> [[VS2:%.*]], <vscale x 4 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 4 x double> [[VS2:%.*]], <vscale x 4 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vzip.mask.nxv8f64.nxv4f64.i64(<vscale x 8 x double> [[VD]], <vscale x 4 x double> [[VS2]], <vscale x 4 x double> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vzip.mask.nxv8f64.nxv4f64.i64(<vscale x 8 x double> [[VD]], <vscale x 4 x double> [[VS2]], <vscale x 4 x double> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
-vfloat64m8_t test_vzip_vv_f64m8_tum(vbool16_t vm, vfloat64m8_t vd,
+vfloat64m8_t test_vzip_vv_f64m8_tum(vbool8_t vm, vfloat64m8_t vd,
vfloat64m4_t vs2, vfloat64m4_t vs1,
size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vzip_vv_i8mf4_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
-vint8mf4_t test_vzip_vv_i8mf4_tum(vbool64_t vm, vint8mf4_t vd, vint8mf8_t vs2,
+vint8mf4_t test_vzip_vv_i8mf4_tum(vbool32_t vm, vint8mf4_t vd, vint8mf8_t vs2,
vint8mf8_t vs1, size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vzip_vv_i8mf2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
-vint8mf2_t test_vzip_vv_i8mf2_tum(vbool32_t vm, vint8mf2_t vd, vint8mf4_t vs2,
+vint8mf2_t test_vzip_vv_i8mf2_tum(vbool16_t vm, vint8mf2_t vd, vint8mf4_t vs2,
vint8mf4_t vs1, size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vzip_vv_i8m1_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
-vint8m1_t test_vzip_vv_i8m1_tum(vbool16_t vm, vint8m1_t vd, vint8mf2_t vs2,
+vint8m1_t test_vzip_vv_i8m1_tum(vbool8_t vm, vint8m1_t vd, vint8mf2_t vs2,
vint8mf2_t vs1, size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vzip_vv_i8m2_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
-vint8m2_t test_vzip_vv_i8m2_tum(vbool8_t vm, vint8m2_t vd, vint8m1_t vs2,
+vint8m2_t test_vzip_vv_i8m2_tum(vbool4_t vm, vint8m2_t vd, vint8m1_t vs2,
vint8m1_t vs1, size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vzip_vv_i8m4_tum
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
-vint8m4_t test_vzip_vv_i8m4_tum(vbool4_t vm, vint8m4_t vd, vint8m2_t vs2,
+vint8m4_t test_vzip_vv_i8m4_tum(vbool2_t vm, vint8m4_t vd, vint8m2_t vs2,
vint8m2_t vs1, size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vzip_vv_i8m8_tum
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 64 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 64 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
-vint8m8_t test_vzip_vv_i8m8_tum(vbool2_t vm, vint8m8_t vd, vint8m4_t vs2,
+vint8m8_t test_vzip_vv_i8m8_tum(vbool1_t vm, vint8m8_t vd, vint8m4_t vs2,
vint8m4_t vs1, size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vzip_vv_i16mf2_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
-vint16mf2_t test_vzip_vv_i16mf2_tum(vbool64_t vm, vint16mf2_t vd,
+vint16mf2_t test_vzip_vv_i16mf2_tum(vbool32_t vm, vint16mf2_t vd,
vint16mf4_t vs2, vint16mf4_t vs1,
size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vzip_vv_i16m1_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
-vint16m1_t test_vzip_vv_i16m1_tum(vbool32_t vm, vint16m1_t vd, vint16mf2_t vs2,
+vint16m1_t test_vzip_vv_i16m1_tum(vbool16_t vm, vint16m1_t vd, vint16mf2_t vs2,
vint16mf2_t vs1, size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vzip_vv_i16m2_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
-vint16m2_t test_vzip_vv_i16m2_tum(vbool16_t vm, vint16m2_t vd, vint16m1_t vs2,
+vint16m2_t test_vzip_vv_i16m2_tum(vbool8_t vm, vint16m2_t vd, vint16m1_t vs2,
vint16m1_t vs1, size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vzip_vv_i16m4_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
-vint16m4_t test_vzip_vv_i16m4_tum(vbool8_t vm, vint16m4_t vd, vint16m2_t vs2,
+vint16m4_t test_vzip_vv_i16m4_tum(vbool4_t vm, vint16m4_t vd, vint16m2_t vs2,
vint16m2_t vs1, size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vzip_vv_i16m8_tum
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
-vint16m8_t test_vzip_vv_i16m8_tum(vbool4_t vm, vint16m8_t vd, vint16m4_t vs2,
+vint16m8_t test_vzip_vv_i16m8_tum(vbool2_t vm, vint16m8_t vd, vint16m4_t vs2,
vint16m4_t vs1, size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vzip_vv_i32m1_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vzip_vv_i32m1_tum(vbool64_t vm, vint32m1_t vd, vint32mf2_t vs2,
+vint32m1_t test_vzip_vv_i32m1_tum(vbool32_t vm, vint32m1_t vd, vint32mf2_t vs2,
vint32mf2_t vs1, size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vzip_vv_i32m2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vzip_vv_i32m2_tum(vbool32_t vm, vint32m2_t vd, vint32m1_t vs2,
+vint32m2_t test_vzip_vv_i32m2_tum(vbool16_t vm, vint32m2_t vd, vint32m1_t vs2,
vint32m1_t vs1, size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vzip_vv_i32m4_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vzip_vv_i32m4_tum(vbool16_t vm, vint32m4_t vd, vint32m2_t vs2,
+vint32m4_t test_vzip_vv_i32m4_tum(vbool8_t vm, vint32m4_t vd, vint32m2_t vs2,
vint32m2_t vs1, size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vzip_vv_i32m8_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vzip_vv_i32m8_tum(vbool8_t vm, vint32m8_t vd, vint32m4_t vs2,
+vint32m8_t test_vzip_vv_i32m8_tum(vbool4_t vm, vint32m8_t vd, vint32m4_t vs2,
vint32m4_t vs1, size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vzip_vv_i64m2_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
-vint64m2_t test_vzip_vv_i64m2_tum(vbool64_t vm, vint64m2_t vd, vint64m1_t vs2,
+vint64m2_t test_vzip_vv_i64m2_tum(vbool32_t vm, vint64m2_t vd, vint64m1_t vs2,
vint64m1_t vs1, size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vzip_vv_i64m4_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
-vint64m4_t test_vzip_vv_i64m4_tum(vbool32_t vm, vint64m4_t vd, vint64m2_t vs2,
+vint64m4_t test_vzip_vv_i64m4_tum(vbool16_t vm, vint64m4_t vd, vint64m2_t vs2,
vint64m2_t vs1, size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vzip_vv_i64m8_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
-vint64m8_t test_vzip_vv_i64m8_tum(vbool16_t vm, vint64m8_t vd, vint64m4_t vs2,
+vint64m8_t test_vzip_vv_i64m8_tum(vbool8_t vm, vint64m8_t vd, vint64m4_t vs2,
vint64m4_t vs1, size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vzip_vv_u8mf4_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
-vuint8mf4_t test_vzip_vv_u8mf4_tum(vbool64_t vm, vuint8mf4_t vd,
+vuint8mf4_t test_vzip_vv_u8mf4_tum(vbool32_t vm, vuint8mf4_t vd,
vuint8mf8_t vs2, vuint8mf8_t vs1,
size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vzip_vv_u8mf2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
-vuint8mf2_t test_vzip_vv_u8mf2_tum(vbool32_t vm, vuint8mf2_t vd,
+vuint8mf2_t test_vzip_vv_u8mf2_tum(vbool16_t vm, vuint8mf2_t vd,
vuint8mf4_t vs2, vuint8mf4_t vs1,
size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vzip_vv_u8m1_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
-vuint8m1_t test_vzip_vv_u8m1_tum(vbool16_t vm, vuint8m1_t vd, vuint8mf2_t vs2,
+vuint8m1_t test_vzip_vv_u8m1_tum(vbool8_t vm, vuint8m1_t vd, vuint8mf2_t vs2,
vuint8mf2_t vs1, size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vzip_vv_u8m2_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
-vuint8m2_t test_vzip_vv_u8m2_tum(vbool8_t vm, vuint8m2_t vd, vuint8m1_t vs2,
+vuint8m2_t test_vzip_vv_u8m2_tum(vbool4_t vm, vuint8m2_t vd, vuint8m1_t vs2,
vuint8m1_t vs1, size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vzip_vv_u8m4_tum
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
-vuint8m4_t test_vzip_vv_u8m4_tum(vbool4_t vm, vuint8m4_t vd, vuint8m2_t vs2,
+vuint8m4_t test_vzip_vv_u8m4_tum(vbool2_t vm, vuint8m4_t vd, vuint8m2_t vs2,
vuint8m2_t vs1, size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vzip_vv_u8m8_tum
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 64 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 64 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
-vuint8m8_t test_vzip_vv_u8m8_tum(vbool2_t vm, vuint8m8_t vd, vuint8m4_t vs2,
+vuint8m8_t test_vzip_vv_u8m8_tum(vbool1_t vm, vuint8m8_t vd, vuint8m4_t vs2,
vuint8m4_t vs1, size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vzip_vv_u16mf2_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
-vuint16mf2_t test_vzip_vv_u16mf2_tum(vbool64_t vm, vuint16mf2_t vd,
+vuint16mf2_t test_vzip_vv_u16mf2_tum(vbool32_t vm, vuint16mf2_t vd,
vuint16mf4_t vs2, vuint16mf4_t vs1,
size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vzip_vv_u16m1_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
-vuint16m1_t test_vzip_vv_u16m1_tum(vbool32_t vm, vuint16m1_t vd,
+vuint16m1_t test_vzip_vv_u16m1_tum(vbool16_t vm, vuint16m1_t vd,
vuint16mf2_t vs2, vuint16mf2_t vs1,
size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vzip_vv_u16m2_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
-vuint16m2_t test_vzip_vv_u16m2_tum(vbool16_t vm, vuint16m2_t vd,
+vuint16m2_t test_vzip_vv_u16m2_tum(vbool8_t vm, vuint16m2_t vd,
vuint16m1_t vs2, vuint16m1_t vs1,
size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vzip_vv_u16m4_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
-vuint16m4_t test_vzip_vv_u16m4_tum(vbool8_t vm, vuint16m4_t vd, vuint16m2_t vs2,
+vuint16m4_t test_vzip_vv_u16m4_tum(vbool4_t vm, vuint16m4_t vd, vuint16m2_t vs2,
vuint16m2_t vs1, size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vzip_vv_u16m8_tum
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
-vuint16m8_t test_vzip_vv_u16m8_tum(vbool4_t vm, vuint16m8_t vd, vuint16m4_t vs2,
+vuint16m8_t test_vzip_vv_u16m8_tum(vbool2_t vm, vuint16m8_t vd, vuint16m4_t vs2,
vuint16m4_t vs1, size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vzip_vv_u32m1_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vzip_vv_u32m1_tum(vbool64_t vm, vuint32m1_t vd,
+vuint32m1_t test_vzip_vv_u32m1_tum(vbool32_t vm, vuint32m1_t vd,
vuint32mf2_t vs2, vuint32mf2_t vs1,
size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vzip_vv_u32m2_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vzip_vv_u32m2_tum(vbool32_t vm, vuint32m2_t vd,
+vuint32m2_t test_vzip_vv_u32m2_tum(vbool16_t vm, vuint32m2_t vd,
vuint32m1_t vs2, vuint32m1_t vs1,
size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vzip_vv_u32m4_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vzip_vv_u32m4_tum(vbool16_t vm, vuint32m4_t vd,
+vuint32m4_t test_vzip_vv_u32m4_tum(vbool8_t vm, vuint32m4_t vd,
vuint32m2_t vs2, vuint32m2_t vs1,
size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vzip_vv_u32m8_tum
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vzip_vv_u32m8_tum(vbool8_t vm, vuint32m8_t vd, vuint32m4_t vs2,
+vuint32m8_t test_vzip_vv_u32m8_tum(vbool4_t vm, vuint32m8_t vd, vuint32m4_t vs2,
vuint32m4_t vs1, size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vzip_vv_u64m2_tum
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
-vuint64m2_t test_vzip_vv_u64m2_tum(vbool64_t vm, vuint64m2_t vd,
+vuint64m2_t test_vzip_vv_u64m2_tum(vbool32_t vm, vuint64m2_t vd,
vuint64m1_t vs2, vuint64m1_t vs1,
size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vzip_vv_u64m4_tum
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
-vuint64m4_t test_vzip_vv_u64m4_tum(vbool32_t vm, vuint64m4_t vd,
+vuint64m4_t test_vzip_vv_u64m4_tum(vbool16_t vm, vuint64m4_t vd,
vuint64m2_t vs2, vuint64m2_t vs1,
size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vzip_vv_u64m8_tum
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
-vuint64m8_t test_vzip_vv_u64m8_tum(vbool16_t vm, vuint64m8_t vd,
+vuint64m8_t test_vzip_vv_u64m8_tum(vbool8_t vm, vuint64m8_t vd,
vuint64m4_t vs2, vuint64m4_t vs1,
size_t vl) {
return __riscv_vzip_tum(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vzip_vv_f16mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vzip.mask.nxv2f16.nxv1f16.i64(<vscale x 2 x half> [[VD]], <vscale x 1 x half> [[VS2]], <vscale x 1 x half> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vzip.mask.nxv2f16.nxv1f16.i64(<vscale x 2 x half> [[VD]], <vscale x 1 x half> [[VS2]], <vscale x 1 x half> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
-vfloat16mf2_t test_vzip_vv_f16mf2_tumu(vbool64_t vm, vfloat16mf2_t vd,
+vfloat16mf2_t test_vzip_vv_f16mf2_tumu(vbool32_t vm, vfloat16mf2_t vd,
vfloat16mf4_t vs2, vfloat16mf4_t vs1,
size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vzip_vv_f16m1_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vzip.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[VD]], <vscale x 2 x half> [[VS2]], <vscale x 2 x half> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vzip.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[VD]], <vscale x 2 x half> [[VS2]], <vscale x 2 x half> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
-vfloat16m1_t test_vzip_vv_f16m1_tumu(vbool32_t vm, vfloat16m1_t vd,
+vfloat16m1_t test_vzip_vv_f16m1_tumu(vbool16_t vm, vfloat16m1_t vd,
vfloat16mf2_t vs2, vfloat16mf2_t vs1,
size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vzip_vv_f16m2_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vzip.mask.nxv8f16.nxv4f16.i64(<vscale x 8 x half> [[VD]], <vscale x 4 x half> [[VS2]], <vscale x 4 x half> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vzip.mask.nxv8f16.nxv4f16.i64(<vscale x 8 x half> [[VD]], <vscale x 4 x half> [[VS2]], <vscale x 4 x half> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
-vfloat16m2_t test_vzip_vv_f16m2_tumu(vbool16_t vm, vfloat16m2_t vd,
+vfloat16m2_t test_vzip_vv_f16m2_tumu(vbool8_t vm, vfloat16m2_t vd,
vfloat16m1_t vs2, vfloat16m1_t vs1,
size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vzip_vv_f16m4_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vzip.mask.nxv16f16.nxv8f16.i64(<vscale x 16 x half> [[VD]], <vscale x 8 x half> [[VS2]], <vscale x 8 x half> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vzip.mask.nxv16f16.nxv8f16.i64(<vscale x 16 x half> [[VD]], <vscale x 8 x half> [[VS2]], <vscale x 8 x half> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
-vfloat16m4_t test_vzip_vv_f16m4_tumu(vbool8_t vm, vfloat16m4_t vd,
+vfloat16m4_t test_vzip_vv_f16m4_tumu(vbool4_t vm, vfloat16m4_t vd,
vfloat16m2_t vs2, vfloat16m2_t vs1,
size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vzip_vv_f16m8_tumu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vzip.mask.nxv32f16.nxv16f16.i64(<vscale x 32 x half> [[VD]], <vscale x 16 x half> [[VS2]], <vscale x 16 x half> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vzip.mask.nxv32f16.nxv16f16.i64(<vscale x 32 x half> [[VD]], <vscale x 16 x half> [[VS2]], <vscale x 16 x half> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
-vfloat16m8_t test_vzip_vv_f16m8_tumu(vbool4_t vm, vfloat16m8_t vd,
+vfloat16m8_t test_vzip_vv_f16m8_tumu(vbool2_t vm, vfloat16m8_t vd,
vfloat16m4_t vs2, vfloat16m4_t vs1,
size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vzip_vv_f32m1_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 1 x float> [[VS2:%.*]], <vscale x 1 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 1 x float> [[VS2:%.*]], <vscale x 1 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vzip.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[VD]], <vscale x 1 x float> [[VS2]], <vscale x 1 x float> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vzip.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[VD]], <vscale x 1 x float> [[VS2]], <vscale x 1 x float> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
-vfloat32m1_t test_vzip_vv_f32m1_tumu(vbool64_t vm, vfloat32m1_t vd,
+vfloat32m1_t test_vzip_vv_f32m1_tumu(vbool32_t vm, vfloat32m1_t vd,
vfloat32mf2_t vs2, vfloat32mf2_t vs1,
size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vzip_vv_f32m2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 2 x float> [[VS2:%.*]], <vscale x 2 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 2 x float> [[VS2:%.*]], <vscale x 2 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vzip.mask.nxv4f32.nxv2f32.i64(<vscale x 4 x float> [[VD]], <vscale x 2 x float> [[VS2]], <vscale x 2 x float> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vzip.mask.nxv4f32.nxv2f32.i64(<vscale x 4 x float> [[VD]], <vscale x 2 x float> [[VS2]], <vscale x 2 x float> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
-vfloat32m2_t test_vzip_vv_f32m2_tumu(vbool32_t vm, vfloat32m2_t vd,
+vfloat32m2_t test_vzip_vv_f32m2_tumu(vbool16_t vm, vfloat32m2_t vd,
vfloat32m1_t vs2, vfloat32m1_t vs1,
size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vzip_vv_f32m4_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 4 x float> [[VS2:%.*]], <vscale x 4 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 4 x float> [[VS2:%.*]], <vscale x 4 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vzip.mask.nxv8f32.nxv4f32.i64(<vscale x 8 x float> [[VD]], <vscale x 4 x float> [[VS2]], <vscale x 4 x float> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vzip.mask.nxv8f32.nxv4f32.i64(<vscale x 8 x float> [[VD]], <vscale x 4 x float> [[VS2]], <vscale x 4 x float> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
-vfloat32m4_t test_vzip_vv_f32m4_tumu(vbool16_t vm, vfloat32m4_t vd,
+vfloat32m4_t test_vzip_vv_f32m4_tumu(vbool8_t vm, vfloat32m4_t vd,
vfloat32m2_t vs2, vfloat32m2_t vs1,
size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vzip_vv_f32m8_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 8 x float> [[VS2:%.*]], <vscale x 8 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 8 x float> [[VS2:%.*]], <vscale x 8 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vzip.mask.nxv16f32.nxv8f32.i64(<vscale x 16 x float> [[VD]], <vscale x 8 x float> [[VS2]], <vscale x 8 x float> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vzip.mask.nxv16f32.nxv8f32.i64(<vscale x 16 x float> [[VD]], <vscale x 8 x float> [[VS2]], <vscale x 8 x float> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
-vfloat32m8_t test_vzip_vv_f32m8_tumu(vbool8_t vm, vfloat32m8_t vd,
+vfloat32m8_t test_vzip_vv_f32m8_tumu(vbool4_t vm, vfloat32m8_t vd,
vfloat32m4_t vs2, vfloat32m4_t vs1,
size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vzip_vv_f64m2_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 1 x double> [[VS2:%.*]], <vscale x 1 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 1 x double> [[VS2:%.*]], <vscale x 1 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vzip.mask.nxv2f64.nxv1f64.i64(<vscale x 2 x double> [[VD]], <vscale x 1 x double> [[VS2]], <vscale x 1 x double> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vzip.mask.nxv2f64.nxv1f64.i64(<vscale x 2 x double> [[VD]], <vscale x 1 x double> [[VS2]], <vscale x 1 x double> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
-vfloat64m2_t test_vzip_vv_f64m2_tumu(vbool64_t vm, vfloat64m2_t vd,
+vfloat64m2_t test_vzip_vv_f64m2_tumu(vbool32_t vm, vfloat64m2_t vd,
vfloat64m1_t vs2, vfloat64m1_t vs1,
size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vzip_vv_f64m4_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 2 x double> [[VS2:%.*]], <vscale x 2 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 2 x double> [[VS2:%.*]], <vscale x 2 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vzip.mask.nxv4f64.nxv2f64.i64(<vscale x 4 x double> [[VD]], <vscale x 2 x double> [[VS2]], <vscale x 2 x double> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vzip.mask.nxv4f64.nxv2f64.i64(<vscale x 4 x double> [[VD]], <vscale x 2 x double> [[VS2]], <vscale x 2 x double> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
-vfloat64m4_t test_vzip_vv_f64m4_tumu(vbool32_t vm, vfloat64m4_t vd,
+vfloat64m4_t test_vzip_vv_f64m4_tumu(vbool16_t vm, vfloat64m4_t vd,
vfloat64m2_t vs2, vfloat64m2_t vs1,
size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vzip_vv_f64m8_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 4 x double> [[VS2:%.*]], <vscale x 4 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 4 x double> [[VS2:%.*]], <vscale x 4 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vzip.mask.nxv8f64.nxv4f64.i64(<vscale x 8 x double> [[VD]], <vscale x 4 x double> [[VS2]], <vscale x 4 x double> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vzip.mask.nxv8f64.nxv4f64.i64(<vscale x 8 x double> [[VD]], <vscale x 4 x double> [[VS2]], <vscale x 4 x double> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
-vfloat64m8_t test_vzip_vv_f64m8_tumu(vbool16_t vm, vfloat64m8_t vd,
+vfloat64m8_t test_vzip_vv_f64m8_tumu(vbool8_t vm, vfloat64m8_t vd,
vfloat64m4_t vs2, vfloat64m4_t vs1,
size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vzip_vv_i8mf4_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
-vint8mf4_t test_vzip_vv_i8mf4_tumu(vbool64_t vm, vint8mf4_t vd, vint8mf8_t vs2,
+vint8mf4_t test_vzip_vv_i8mf4_tumu(vbool32_t vm, vint8mf4_t vd, vint8mf8_t vs2,
vint8mf8_t vs1, size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vzip_vv_i8mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
-vint8mf2_t test_vzip_vv_i8mf2_tumu(vbool32_t vm, vint8mf2_t vd, vint8mf4_t vs2,
+vint8mf2_t test_vzip_vv_i8mf2_tumu(vbool16_t vm, vint8mf2_t vd, vint8mf4_t vs2,
vint8mf4_t vs1, size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vzip_vv_i8m1_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
-vint8m1_t test_vzip_vv_i8m1_tumu(vbool16_t vm, vint8m1_t vd, vint8mf2_t vs2,
+vint8m1_t test_vzip_vv_i8m1_tumu(vbool8_t vm, vint8m1_t vd, vint8mf2_t vs2,
vint8mf2_t vs1, size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vzip_vv_i8m2_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
-vint8m2_t test_vzip_vv_i8m2_tumu(vbool8_t vm, vint8m2_t vd, vint8m1_t vs2,
+vint8m2_t test_vzip_vv_i8m2_tumu(vbool4_t vm, vint8m2_t vd, vint8m1_t vs2,
vint8m1_t vs1, size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vzip_vv_i8m4_tumu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
-vint8m4_t test_vzip_vv_i8m4_tumu(vbool4_t vm, vint8m4_t vd, vint8m2_t vs2,
+vint8m4_t test_vzip_vv_i8m4_tumu(vbool2_t vm, vint8m4_t vd, vint8m2_t vs2,
vint8m2_t vs1, size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vzip_vv_i8m8_tumu
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 64 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 64 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
-vint8m8_t test_vzip_vv_i8m8_tumu(vbool2_t vm, vint8m8_t vd, vint8m4_t vs2,
+vint8m8_t test_vzip_vv_i8m8_tumu(vbool1_t vm, vint8m8_t vd, vint8m4_t vs2,
vint8m4_t vs1, size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vzip_vv_i16mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
-vint16mf2_t test_vzip_vv_i16mf2_tumu(vbool64_t vm, vint16mf2_t vd,
+vint16mf2_t test_vzip_vv_i16mf2_tumu(vbool32_t vm, vint16mf2_t vd,
vint16mf4_t vs2, vint16mf4_t vs1,
size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vzip_vv_i16m1_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
-vint16m1_t test_vzip_vv_i16m1_tumu(vbool32_t vm, vint16m1_t vd, vint16mf2_t vs2,
+vint16m1_t test_vzip_vv_i16m1_tumu(vbool16_t vm, vint16m1_t vd, vint16mf2_t vs2,
vint16mf2_t vs1, size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vzip_vv_i16m2_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
-vint16m2_t test_vzip_vv_i16m2_tumu(vbool16_t vm, vint16m2_t vd, vint16m1_t vs2,
+vint16m2_t test_vzip_vv_i16m2_tumu(vbool8_t vm, vint16m2_t vd, vint16m1_t vs2,
vint16m1_t vs1, size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vzip_vv_i16m4_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
-vint16m4_t test_vzip_vv_i16m4_tumu(vbool8_t vm, vint16m4_t vd, vint16m2_t vs2,
+vint16m4_t test_vzip_vv_i16m4_tumu(vbool4_t vm, vint16m4_t vd, vint16m2_t vs2,
vint16m2_t vs1, size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vzip_vv_i16m8_tumu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
-vint16m8_t test_vzip_vv_i16m8_tumu(vbool4_t vm, vint16m8_t vd, vint16m4_t vs2,
+vint16m8_t test_vzip_vv_i16m8_tumu(vbool2_t vm, vint16m8_t vd, vint16m4_t vs2,
vint16m4_t vs1, size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vzip_vv_i32m1_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vzip_vv_i32m1_tumu(vbool64_t vm, vint32m1_t vd, vint32mf2_t vs2,
+vint32m1_t test_vzip_vv_i32m1_tumu(vbool32_t vm, vint32m1_t vd, vint32mf2_t vs2,
vint32mf2_t vs1, size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vzip_vv_i32m2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vzip_vv_i32m2_tumu(vbool32_t vm, vint32m2_t vd, vint32m1_t vs2,
+vint32m2_t test_vzip_vv_i32m2_tumu(vbool16_t vm, vint32m2_t vd, vint32m1_t vs2,
vint32m1_t vs1, size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vzip_vv_i32m4_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vzip_vv_i32m4_tumu(vbool16_t vm, vint32m4_t vd, vint32m2_t vs2,
+vint32m4_t test_vzip_vv_i32m4_tumu(vbool8_t vm, vint32m4_t vd, vint32m2_t vs2,
vint32m2_t vs1, size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vzip_vv_i32m8_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vzip_vv_i32m8_tumu(vbool8_t vm, vint32m8_t vd, vint32m4_t vs2,
+vint32m8_t test_vzip_vv_i32m8_tumu(vbool4_t vm, vint32m8_t vd, vint32m4_t vs2,
vint32m4_t vs1, size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vzip_vv_i64m2_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
-vint64m2_t test_vzip_vv_i64m2_tumu(vbool64_t vm, vint64m2_t vd, vint64m1_t vs2,
+vint64m2_t test_vzip_vv_i64m2_tumu(vbool32_t vm, vint64m2_t vd, vint64m1_t vs2,
vint64m1_t vs1, size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vzip_vv_i64m4_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
-vint64m4_t test_vzip_vv_i64m4_tumu(vbool32_t vm, vint64m4_t vd, vint64m2_t vs2,
+vint64m4_t test_vzip_vv_i64m4_tumu(vbool16_t vm, vint64m4_t vd, vint64m2_t vs2,
vint64m2_t vs1, size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vzip_vv_i64m8_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
-vint64m8_t test_vzip_vv_i64m8_tumu(vbool16_t vm, vint64m8_t vd, vint64m4_t vs2,
+vint64m8_t test_vzip_vv_i64m8_tumu(vbool8_t vm, vint64m8_t vd, vint64m4_t vs2,
vint64m4_t vs1, size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vzip_vv_u8mf4_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
-vuint8mf4_t test_vzip_vv_u8mf4_tumu(vbool64_t vm, vuint8mf4_t vd,
+vuint8mf4_t test_vzip_vv_u8mf4_tumu(vbool32_t vm, vuint8mf4_t vd,
vuint8mf8_t vs2, vuint8mf8_t vs1,
size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vzip_vv_u8mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
-vuint8mf2_t test_vzip_vv_u8mf2_tumu(vbool32_t vm, vuint8mf2_t vd,
+vuint8mf2_t test_vzip_vv_u8mf2_tumu(vbool16_t vm, vuint8mf2_t vd,
vuint8mf4_t vs2, vuint8mf4_t vs1,
size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vzip_vv_u8m1_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
-vuint8m1_t test_vzip_vv_u8m1_tumu(vbool16_t vm, vuint8m1_t vd, vuint8mf2_t vs2,
+vuint8m1_t test_vzip_vv_u8m1_tumu(vbool8_t vm, vuint8m1_t vd, vuint8mf2_t vs2,
vuint8mf2_t vs1, size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vzip_vv_u8m2_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
-vuint8m2_t test_vzip_vv_u8m2_tumu(vbool8_t vm, vuint8m2_t vd, vuint8m1_t vs2,
+vuint8m2_t test_vzip_vv_u8m2_tumu(vbool4_t vm, vuint8m2_t vd, vuint8m1_t vs2,
vuint8m1_t vs1, size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vzip_vv_u8m4_tumu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
-vuint8m4_t test_vzip_vv_u8m4_tumu(vbool4_t vm, vuint8m4_t vd, vuint8m2_t vs2,
+vuint8m4_t test_vzip_vv_u8m4_tumu(vbool2_t vm, vuint8m4_t vd, vuint8m2_t vs2,
vuint8m2_t vs1, size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vzip_vv_u8m8_tumu
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 64 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 64 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
-vuint8m8_t test_vzip_vv_u8m8_tumu(vbool2_t vm, vuint8m8_t vd, vuint8m4_t vs2,
+vuint8m8_t test_vzip_vv_u8m8_tumu(vbool1_t vm, vuint8m8_t vd, vuint8m4_t vs2,
vuint8m4_t vs1, size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vzip_vv_u16mf2_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
-vuint16mf2_t test_vzip_vv_u16mf2_tumu(vbool64_t vm, vuint16mf2_t vd,
+vuint16mf2_t test_vzip_vv_u16mf2_tumu(vbool32_t vm, vuint16mf2_t vd,
vuint16mf4_t vs2, vuint16mf4_t vs1,
size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vzip_vv_u16m1_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
-vuint16m1_t test_vzip_vv_u16m1_tumu(vbool32_t vm, vuint16m1_t vd,
+vuint16m1_t test_vzip_vv_u16m1_tumu(vbool16_t vm, vuint16m1_t vd,
vuint16mf2_t vs2, vuint16mf2_t vs1,
size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vzip_vv_u16m2_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
-vuint16m2_t test_vzip_vv_u16m2_tumu(vbool16_t vm, vuint16m2_t vd,
+vuint16m2_t test_vzip_vv_u16m2_tumu(vbool8_t vm, vuint16m2_t vd,
vuint16m1_t vs2, vuint16m1_t vs1,
size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vzip_vv_u16m4_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
-vuint16m4_t test_vzip_vv_u16m4_tumu(vbool8_t vm, vuint16m4_t vd,
+vuint16m4_t test_vzip_vv_u16m4_tumu(vbool4_t vm, vuint16m4_t vd,
vuint16m2_t vs2, vuint16m2_t vs1,
size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vzip_vv_u16m8_tumu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
-vuint16m8_t test_vzip_vv_u16m8_tumu(vbool4_t vm, vuint16m8_t vd,
+vuint16m8_t test_vzip_vv_u16m8_tumu(vbool2_t vm, vuint16m8_t vd,
vuint16m4_t vs2, vuint16m4_t vs1,
size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vzip_vv_u32m1_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vzip_vv_u32m1_tumu(vbool64_t vm, vuint32m1_t vd,
+vuint32m1_t test_vzip_vv_u32m1_tumu(vbool32_t vm, vuint32m1_t vd,
vuint32mf2_t vs2, vuint32mf2_t vs1,
size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vzip_vv_u32m2_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vzip_vv_u32m2_tumu(vbool32_t vm, vuint32m2_t vd,
+vuint32m2_t test_vzip_vv_u32m2_tumu(vbool16_t vm, vuint32m2_t vd,
vuint32m1_t vs2, vuint32m1_t vs1,
size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vzip_vv_u32m4_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vzip_vv_u32m4_tumu(vbool16_t vm, vuint32m4_t vd,
+vuint32m4_t test_vzip_vv_u32m4_tumu(vbool8_t vm, vuint32m4_t vd,
vuint32m2_t vs2, vuint32m2_t vs1,
size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vzip_vv_u32m8_tumu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vzip_vv_u32m8_tumu(vbool8_t vm, vuint32m8_t vd,
+vuint32m8_t test_vzip_vv_u32m8_tumu(vbool4_t vm, vuint32m8_t vd,
vuint32m4_t vs2, vuint32m4_t vs1,
size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vzip_vv_u64m2_tumu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
-vuint64m2_t test_vzip_vv_u64m2_tumu(vbool64_t vm, vuint64m2_t vd,
+vuint64m2_t test_vzip_vv_u64m2_tumu(vbool32_t vm, vuint64m2_t vd,
vuint64m1_t vs2, vuint64m1_t vs1,
size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vzip_vv_u64m4_tumu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
-vuint64m4_t test_vzip_vv_u64m4_tumu(vbool32_t vm, vuint64m4_t vd,
+vuint64m4_t test_vzip_vv_u64m4_tumu(vbool16_t vm, vuint64m4_t vd,
vuint64m2_t vs2, vuint64m2_t vs1,
size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vzip_vv_u64m8_tumu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
-vuint64m8_t test_vzip_vv_u64m8_tumu(vbool16_t vm, vuint64m8_t vd,
+vuint64m8_t test_vzip_vv_u64m8_tumu(vbool8_t vm, vuint64m8_t vd,
vuint64m4_t vs2, vuint64m4_t vs1,
size_t vl) {
return __riscv_vzip_tumu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vzip_vv_f16mf2_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 1 x half> [[VS2:%.*]], <vscale x 1 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vzip.mask.nxv2f16.nxv1f16.i64(<vscale x 2 x half> [[VD]], <vscale x 1 x half> [[VS2]], <vscale x 1 x half> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vzip.mask.nxv2f16.nxv1f16.i64(<vscale x 2 x half> [[VD]], <vscale x 1 x half> [[VS2]], <vscale x 1 x half> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
-vfloat16mf2_t test_vzip_vv_f16mf2_mu(vbool64_t vm, vfloat16mf2_t vd,
+vfloat16mf2_t test_vzip_vv_f16mf2_mu(vbool32_t vm, vfloat16mf2_t vd,
vfloat16mf4_t vs2, vfloat16mf4_t vs1,
size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vzip_vv_f16m1_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 2 x half> [[VS2:%.*]], <vscale x 2 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vzip.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[VD]], <vscale x 2 x half> [[VS2]], <vscale x 2 x half> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vzip.mask.nxv4f16.nxv2f16.i64(<vscale x 4 x half> [[VD]], <vscale x 2 x half> [[VS2]], <vscale x 2 x half> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
-vfloat16m1_t test_vzip_vv_f16m1_mu(vbool32_t vm, vfloat16m1_t vd,
+vfloat16m1_t test_vzip_vv_f16m1_mu(vbool16_t vm, vfloat16m1_t vd,
vfloat16mf2_t vs2, vfloat16mf2_t vs1,
size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vzip_vv_f16m2_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 4 x half> [[VS2:%.*]], <vscale x 4 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vzip.mask.nxv8f16.nxv4f16.i64(<vscale x 8 x half> [[VD]], <vscale x 4 x half> [[VS2]], <vscale x 4 x half> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vzip.mask.nxv8f16.nxv4f16.i64(<vscale x 8 x half> [[VD]], <vscale x 4 x half> [[VS2]], <vscale x 4 x half> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
-vfloat16m2_t test_vzip_vv_f16m2_mu(vbool16_t vm, vfloat16m2_t vd,
+vfloat16m2_t test_vzip_vv_f16m2_mu(vbool8_t vm, vfloat16m2_t vd,
vfloat16m1_t vs2, vfloat16m1_t vs1,
size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vzip_vv_f16m4_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 8 x half> [[VS2:%.*]], <vscale x 8 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vzip.mask.nxv16f16.nxv8f16.i64(<vscale x 16 x half> [[VD]], <vscale x 8 x half> [[VS2]], <vscale x 8 x half> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vzip.mask.nxv16f16.nxv8f16.i64(<vscale x 16 x half> [[VD]], <vscale x 8 x half> [[VS2]], <vscale x 8 x half> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
-vfloat16m4_t test_vzip_vv_f16m4_mu(vbool8_t vm, vfloat16m4_t vd,
+vfloat16m4_t test_vzip_vv_f16m4_mu(vbool4_t vm, vfloat16m4_t vd,
vfloat16m2_t vs2, vfloat16m2_t vs1,
size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vzip_vv_f16m8_mu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 16 x half> [[VS2:%.*]], <vscale x 16 x half> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vzip.mask.nxv32f16.nxv16f16.i64(<vscale x 32 x half> [[VD]], <vscale x 16 x half> [[VS2]], <vscale x 16 x half> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vzip.mask.nxv32f16.nxv16f16.i64(<vscale x 32 x half> [[VD]], <vscale x 16 x half> [[VS2]], <vscale x 16 x half> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
-vfloat16m8_t test_vzip_vv_f16m8_mu(vbool4_t vm, vfloat16m8_t vd,
+vfloat16m8_t test_vzip_vv_f16m8_mu(vbool2_t vm, vfloat16m8_t vd,
vfloat16m4_t vs2, vfloat16m4_t vs1,
size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vzip_vv_f32m1_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 1 x float> [[VS2:%.*]], <vscale x 1 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 1 x float> [[VS2:%.*]], <vscale x 1 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vzip.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[VD]], <vscale x 1 x float> [[VS2]], <vscale x 1 x float> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vzip.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[VD]], <vscale x 1 x float> [[VS2]], <vscale x 1 x float> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
-vfloat32m1_t test_vzip_vv_f32m1_mu(vbool64_t vm, vfloat32m1_t vd,
+vfloat32m1_t test_vzip_vv_f32m1_mu(vbool32_t vm, vfloat32m1_t vd,
vfloat32mf2_t vs2, vfloat32mf2_t vs1,
size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vzip_vv_f32m2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 2 x float> [[VS2:%.*]], <vscale x 2 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 2 x float> [[VS2:%.*]], <vscale x 2 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vzip.mask.nxv4f32.nxv2f32.i64(<vscale x 4 x float> [[VD]], <vscale x 2 x float> [[VS2]], <vscale x 2 x float> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vzip.mask.nxv4f32.nxv2f32.i64(<vscale x 4 x float> [[VD]], <vscale x 2 x float> [[VS2]], <vscale x 2 x float> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
-vfloat32m2_t test_vzip_vv_f32m2_mu(vbool32_t vm, vfloat32m2_t vd,
+vfloat32m2_t test_vzip_vv_f32m2_mu(vbool16_t vm, vfloat32m2_t vd,
vfloat32m1_t vs2, vfloat32m1_t vs1,
size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vzip_vv_f32m4_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 4 x float> [[VS2:%.*]], <vscale x 4 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 4 x float> [[VS2:%.*]], <vscale x 4 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vzip.mask.nxv8f32.nxv4f32.i64(<vscale x 8 x float> [[VD]], <vscale x 4 x float> [[VS2]], <vscale x 4 x float> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vzip.mask.nxv8f32.nxv4f32.i64(<vscale x 8 x float> [[VD]], <vscale x 4 x float> [[VS2]], <vscale x 4 x float> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
-vfloat32m4_t test_vzip_vv_f32m4_mu(vbool16_t vm, vfloat32m4_t vd,
+vfloat32m4_t test_vzip_vv_f32m4_mu(vbool8_t vm, vfloat32m4_t vd,
vfloat32m2_t vs2, vfloat32m2_t vs1,
size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vzip_vv_f32m8_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 8 x float> [[VS2:%.*]], <vscale x 8 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 8 x float> [[VS2:%.*]], <vscale x 8 x float> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vzip.mask.nxv16f32.nxv8f32.i64(<vscale x 16 x float> [[VD]], <vscale x 8 x float> [[VS2]], <vscale x 8 x float> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vzip.mask.nxv16f32.nxv8f32.i64(<vscale x 16 x float> [[VD]], <vscale x 8 x float> [[VS2]], <vscale x 8 x float> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
-vfloat32m8_t test_vzip_vv_f32m8_mu(vbool8_t vm, vfloat32m8_t vd,
+vfloat32m8_t test_vzip_vv_f32m8_mu(vbool4_t vm, vfloat32m8_t vd,
vfloat32m4_t vs2, vfloat32m4_t vs1,
size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vzip_vv_f64m2_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 1 x double> [[VS2:%.*]], <vscale x 1 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 1 x double> [[VS2:%.*]], <vscale x 1 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vzip.mask.nxv2f64.nxv1f64.i64(<vscale x 2 x double> [[VD]], <vscale x 1 x double> [[VS2]], <vscale x 1 x double> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vzip.mask.nxv2f64.nxv1f64.i64(<vscale x 2 x double> [[VD]], <vscale x 1 x double> [[VS2]], <vscale x 1 x double> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
-vfloat64m2_t test_vzip_vv_f64m2_mu(vbool64_t vm, vfloat64m2_t vd,
+vfloat64m2_t test_vzip_vv_f64m2_mu(vbool32_t vm, vfloat64m2_t vd,
vfloat64m1_t vs2, vfloat64m1_t vs1,
size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vzip_vv_f64m4_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 2 x double> [[VS2:%.*]], <vscale x 2 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 2 x double> [[VS2:%.*]], <vscale x 2 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vzip.mask.nxv4f64.nxv2f64.i64(<vscale x 4 x double> [[VD]], <vscale x 2 x double> [[VS2]], <vscale x 2 x double> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vzip.mask.nxv4f64.nxv2f64.i64(<vscale x 4 x double> [[VD]], <vscale x 2 x double> [[VS2]], <vscale x 2 x double> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
-vfloat64m4_t test_vzip_vv_f64m4_mu(vbool32_t vm, vfloat64m4_t vd,
+vfloat64m4_t test_vzip_vv_f64m4_mu(vbool16_t vm, vfloat64m4_t vd,
vfloat64m2_t vs2, vfloat64m2_t vs1,
size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vzip_vv_f64m8_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 4 x double> [[VS2:%.*]], <vscale x 4 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 4 x double> [[VS2:%.*]], <vscale x 4 x double> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vzip.mask.nxv8f64.nxv4f64.i64(<vscale x 8 x double> [[VD]], <vscale x 4 x double> [[VS2]], <vscale x 4 x double> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vzip.mask.nxv8f64.nxv4f64.i64(<vscale x 8 x double> [[VD]], <vscale x 4 x double> [[VS2]], <vscale x 4 x double> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
-vfloat64m8_t test_vzip_vv_f64m8_mu(vbool16_t vm, vfloat64m8_t vd,
+vfloat64m8_t test_vzip_vv_f64m8_mu(vbool8_t vm, vfloat64m8_t vd,
vfloat64m4_t vs2, vfloat64m4_t vs1,
size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vzip_vv_i8mf4_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
-vint8mf4_t test_vzip_vv_i8mf4_mu(vbool64_t vm, vint8mf4_t vd, vint8mf8_t vs2,
+vint8mf4_t test_vzip_vv_i8mf4_mu(vbool32_t vm, vint8mf4_t vd, vint8mf8_t vs2,
vint8mf8_t vs1, size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vzip_vv_i8mf2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
-vint8mf2_t test_vzip_vv_i8mf2_mu(vbool32_t vm, vint8mf2_t vd, vint8mf4_t vs2,
+vint8mf2_t test_vzip_vv_i8mf2_mu(vbool16_t vm, vint8mf2_t vd, vint8mf4_t vs2,
vint8mf4_t vs1, size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vzip_vv_i8m1_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
-vint8m1_t test_vzip_vv_i8m1_mu(vbool16_t vm, vint8m1_t vd, vint8mf2_t vs2,
+vint8m1_t test_vzip_vv_i8m1_mu(vbool8_t vm, vint8m1_t vd, vint8mf2_t vs2,
vint8mf2_t vs1, size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vzip_vv_i8m2_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
-vint8m2_t test_vzip_vv_i8m2_mu(vbool8_t vm, vint8m2_t vd, vint8m1_t vs2,
+vint8m2_t test_vzip_vv_i8m2_mu(vbool4_t vm, vint8m2_t vd, vint8m1_t vs2,
vint8m1_t vs1, size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vzip_vv_i8m4_mu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
-vint8m4_t test_vzip_vv_i8m4_mu(vbool4_t vm, vint8m4_t vd, vint8m2_t vs2,
+vint8m4_t test_vzip_vv_i8m4_mu(vbool2_t vm, vint8m4_t vd, vint8m2_t vs2,
vint8m2_t vs1, size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vzip_vv_i8m8_mu
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 64 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 64 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
-vint8m8_t test_vzip_vv_i8m8_mu(vbool2_t vm, vint8m8_t vd, vint8m4_t vs2,
+vint8m8_t test_vzip_vv_i8m8_mu(vbool1_t vm, vint8m8_t vd, vint8m4_t vs2,
vint8m4_t vs1, size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vzip_vv_i16mf2_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
-vint16mf2_t test_vzip_vv_i16mf2_mu(vbool64_t vm, vint16mf2_t vd,
+vint16mf2_t test_vzip_vv_i16mf2_mu(vbool32_t vm, vint16mf2_t vd,
vint16mf4_t vs2, vint16mf4_t vs1,
size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vzip_vv_i16m1_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
-vint16m1_t test_vzip_vv_i16m1_mu(vbool32_t vm, vint16m1_t vd, vint16mf2_t vs2,
+vint16m1_t test_vzip_vv_i16m1_mu(vbool16_t vm, vint16m1_t vd, vint16mf2_t vs2,
vint16mf2_t vs1, size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vzip_vv_i16m2_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
-vint16m2_t test_vzip_vv_i16m2_mu(vbool16_t vm, vint16m2_t vd, vint16m1_t vs2,
+vint16m2_t test_vzip_vv_i16m2_mu(vbool8_t vm, vint16m2_t vd, vint16m1_t vs2,
vint16m1_t vs1, size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vzip_vv_i16m4_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
-vint16m4_t test_vzip_vv_i16m4_mu(vbool8_t vm, vint16m4_t vd, vint16m2_t vs2,
+vint16m4_t test_vzip_vv_i16m4_mu(vbool4_t vm, vint16m4_t vd, vint16m2_t vs2,
vint16m2_t vs1, size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vzip_vv_i16m8_mu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
-vint16m8_t test_vzip_vv_i16m8_mu(vbool4_t vm, vint16m8_t vd, vint16m4_t vs2,
+vint16m8_t test_vzip_vv_i16m8_mu(vbool2_t vm, vint16m8_t vd, vint16m4_t vs2,
vint16m4_t vs1, size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vzip_vv_i32m1_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vint32m1_t test_vzip_vv_i32m1_mu(vbool64_t vm, vint32m1_t vd, vint32mf2_t vs2,
+vint32m1_t test_vzip_vv_i32m1_mu(vbool32_t vm, vint32m1_t vd, vint32mf2_t vs2,
vint32mf2_t vs1, size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vzip_vv_i32m2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vint32m2_t test_vzip_vv_i32m2_mu(vbool32_t vm, vint32m2_t vd, vint32m1_t vs2,
+vint32m2_t test_vzip_vv_i32m2_mu(vbool16_t vm, vint32m2_t vd, vint32m1_t vs2,
vint32m1_t vs1, size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vzip_vv_i32m4_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vint32m4_t test_vzip_vv_i32m4_mu(vbool16_t vm, vint32m4_t vd, vint32m2_t vs2,
+vint32m4_t test_vzip_vv_i32m4_mu(vbool8_t vm, vint32m4_t vd, vint32m2_t vs2,
vint32m2_t vs1, size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vzip_vv_i32m8_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vint32m8_t test_vzip_vv_i32m8_mu(vbool8_t vm, vint32m8_t vd, vint32m4_t vs2,
+vint32m8_t test_vzip_vv_i32m8_mu(vbool4_t vm, vint32m8_t vd, vint32m4_t vs2,
vint32m4_t vs1, size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vzip_vv_i64m2_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
-vint64m2_t test_vzip_vv_i64m2_mu(vbool64_t vm, vint64m2_t vd, vint64m1_t vs2,
+vint64m2_t test_vzip_vv_i64m2_mu(vbool32_t vm, vint64m2_t vd, vint64m1_t vs2,
vint64m1_t vs1, size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vzip_vv_i64m4_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
-vint64m4_t test_vzip_vv_i64m4_mu(vbool32_t vm, vint64m4_t vd, vint64m2_t vs2,
+vint64m4_t test_vzip_vv_i64m4_mu(vbool16_t vm, vint64m4_t vd, vint64m2_t vs2,
vint64m2_t vs1, size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vzip_vv_i64m8_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
-vint64m8_t test_vzip_vv_i64m8_mu(vbool16_t vm, vint64m8_t vd, vint64m4_t vs2,
+vint64m8_t test_vzip_vv_i64m8_mu(vbool8_t vm, vint64m8_t vd, vint64m4_t vs2,
vint64m4_t vs1, size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vzip_vv_u8mf4_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vzip.mask.nxv2i8.nxv1i8.i64(<vscale x 2 x i8> [[VD]], <vscale x 1 x i8> [[VS2]], <vscale x 1 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
-vuint8mf4_t test_vzip_vv_u8mf4_mu(vbool64_t vm, vuint8mf4_t vd, vuint8mf8_t vs2,
+vuint8mf4_t test_vzip_vv_u8mf4_mu(vbool32_t vm, vuint8mf4_t vd, vuint8mf8_t vs2,
vuint8mf8_t vs1, size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vzip_vv_u8mf2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i8> [[VD:%.*]], <vscale x 2 x i8> [[VS2:%.*]], <vscale x 2 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vzip.mask.nxv4i8.nxv2i8.i64(<vscale x 4 x i8> [[VD]], <vscale x 2 x i8> [[VS2]], <vscale x 2 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
-vuint8mf2_t test_vzip_vv_u8mf2_mu(vbool32_t vm, vuint8mf2_t vd, vuint8mf4_t vs2,
+vuint8mf2_t test_vzip_vv_u8mf2_mu(vbool16_t vm, vuint8mf2_t vd, vuint8mf4_t vs2,
vuint8mf4_t vs1, size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vzip_vv_u8m1_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i8> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vzip.mask.nxv8i8.nxv4i8.i64(<vscale x 8 x i8> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
-vuint8m1_t test_vzip_vv_u8m1_mu(vbool16_t vm, vuint8m1_t vd, vuint8mf2_t vs2,
+vuint8m1_t test_vzip_vv_u8m1_mu(vbool8_t vm, vuint8m1_t vd, vuint8mf2_t vs2,
vuint8mf2_t vs1, size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vzip_vv_u8m2_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i8> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vzip.mask.nxv16i8.nxv8i8.i64(<vscale x 16 x i8> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
-vuint8m2_t test_vzip_vv_u8m2_mu(vbool8_t vm, vuint8m2_t vd, vuint8m1_t vs2,
+vuint8m2_t test_vzip_vv_u8m2_mu(vbool4_t vm, vuint8m2_t vd, vuint8m1_t vs2,
vuint8m1_t vs1, size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vzip_vv_u8m4_mu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i8> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vzip.mask.nxv32i8.nxv16i8.i64(<vscale x 32 x i8> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
-vuint8m4_t test_vzip_vv_u8m4_mu(vbool4_t vm, vuint8m4_t vd, vuint8m2_t vs2,
+vuint8m4_t test_vzip_vv_u8m4_mu(vbool2_t vm, vuint8m4_t vd, vuint8m2_t vs2,
vuint8m2_t vs1, size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vzip_vv_u8m8_mu
-// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 64 x i1> [[VM:%.*]], <vscale x 64 x i8> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vzip.mask.nxv64i8.nxv32i8.i64(<vscale x 64 x i8> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 64 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
-vuint8m8_t test_vzip_vv_u8m8_mu(vbool2_t vm, vuint8m8_t vd, vuint8m4_t vs2,
+vuint8m8_t test_vzip_vv_u8m8_mu(vbool1_t vm, vuint8m8_t vd, vuint8m4_t vs2,
vuint8m4_t vs1, size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vzip_vv_u16mf2_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i16> [[VD:%.*]], <vscale x 1 x i16> [[VS2:%.*]], <vscale x 1 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzip.mask.nxv2i16.nxv1i16.i64(<vscale x 2 x i16> [[VD]], <vscale x 1 x i16> [[VS2]], <vscale x 1 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
-vuint16mf2_t test_vzip_vv_u16mf2_mu(vbool64_t vm, vuint16mf2_t vd,
+vuint16mf2_t test_vzip_vv_u16mf2_mu(vbool32_t vm, vuint16mf2_t vd,
vuint16mf4_t vs2, vuint16mf4_t vs1,
size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vzip_vv_u16m1_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i16> [[VD:%.*]], <vscale x 2 x i16> [[VS2:%.*]], <vscale x 2 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzip.mask.nxv4i16.nxv2i16.i64(<vscale x 4 x i16> [[VD]], <vscale x 2 x i16> [[VS2]], <vscale x 2 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
-vuint16m1_t test_vzip_vv_u16m1_mu(vbool32_t vm, vuint16m1_t vd,
+vuint16m1_t test_vzip_vv_u16m1_mu(vbool16_t vm, vuint16m1_t vd,
vuint16mf2_t vs2, vuint16mf2_t vs1,
size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vzip_vv_u16m2_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i16> [[VD:%.*]], <vscale x 4 x i16> [[VS2:%.*]], <vscale x 4 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzip.mask.nxv8i16.nxv4i16.i64(<vscale x 8 x i16> [[VD]], <vscale x 4 x i16> [[VS2]], <vscale x 4 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
-vuint16m2_t test_vzip_vv_u16m2_mu(vbool16_t vm, vuint16m2_t vd, vuint16m1_t vs2,
+vuint16m2_t test_vzip_vv_u16m2_mu(vbool8_t vm, vuint16m2_t vd, vuint16m1_t vs2,
vuint16m1_t vs1, size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vzip_vv_u16m4_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i16> [[VD:%.*]], <vscale x 8 x i16> [[VS2:%.*]], <vscale x 8 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzip.mask.nxv16i16.nxv8i16.i64(<vscale x 16 x i16> [[VD]], <vscale x 8 x i16> [[VS2]], <vscale x 8 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
-vuint16m4_t test_vzip_vv_u16m4_mu(vbool8_t vm, vuint16m4_t vd, vuint16m2_t vs2,
+vuint16m4_t test_vzip_vv_u16m4_mu(vbool4_t vm, vuint16m4_t vd, vuint16m2_t vs2,
vuint16m2_t vs1, size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vzip_vv_u16m8_mu
-// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[VM:%.*]], <vscale x 32 x i16> [[VD:%.*]], <vscale x 16 x i16> [[VS2:%.*]], <vscale x 16 x i16> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzip.mask.nxv32i16.nxv16i16.i64(<vscale x 32 x i16> [[VD]], <vscale x 16 x i16> [[VS2]], <vscale x 16 x i16> [[VS1]], <vscale x 32 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
-vuint16m8_t test_vzip_vv_u16m8_mu(vbool4_t vm, vuint16m8_t vd, vuint16m4_t vs2,
+vuint16m8_t test_vzip_vv_u16m8_mu(vbool2_t vm, vuint16m8_t vd, vuint16m4_t vs2,
vuint16m4_t vs1, size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vzip_vv_u32m1_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzip.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
-vuint32m1_t test_vzip_vv_u32m1_mu(vbool64_t vm, vuint32m1_t vd,
+vuint32m1_t test_vzip_vv_u32m1_mu(vbool32_t vm, vuint32m1_t vd,
vuint32mf2_t vs2, vuint32mf2_t vs1,
size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vzip_vv_u32m2_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzip.mask.nxv4i32.nxv2i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
-vuint32m2_t test_vzip_vv_u32m2_mu(vbool32_t vm, vuint32m2_t vd, vuint32m1_t vs2,
+vuint32m2_t test_vzip_vv_u32m2_mu(vbool16_t vm, vuint32m2_t vd, vuint32m1_t vs2,
vuint32m1_t vs1, size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vzip_vv_u32m4_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzip.mask.nxv8i32.nxv4i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
-vuint32m4_t test_vzip_vv_u32m4_mu(vbool16_t vm, vuint32m4_t vd, vuint32m2_t vs2,
+vuint32m4_t test_vzip_vv_u32m4_mu(vbool8_t vm, vuint32m4_t vd, vuint32m2_t vs2,
vuint32m2_t vs1, size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vzip_vv_u32m8_mu
-// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzip.mask.nxv16i32.nxv8i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
-vuint32m8_t test_vzip_vv_u32m8_mu(vbool8_t vm, vuint32m8_t vd, vuint32m4_t vs2,
+vuint32m8_t test_vzip_vv_u32m8_mu(vbool4_t vm, vuint32m8_t vd, vuint32m4_t vs2,
vuint32m4_t vs1, size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vzip_vv_u64m2_mu
-// CHECK-RV64-SAME: (<vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], <vscale x 1 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzip.mask.nxv2i64.nxv1i64.i64(<vscale x 2 x i64> [[VD]], <vscale x 1 x i64> [[VS2]], <vscale x 1 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
-vuint64m2_t test_vzip_vv_u64m2_mu(vbool64_t vm, vuint64m2_t vd, vuint64m1_t vs2,
+vuint64m2_t test_vzip_vv_u64m2_mu(vbool32_t vm, vuint64m2_t vd, vuint64m1_t vs2,
vuint64m1_t vs1, size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vzip_vv_u64m4_mu
-// CHECK-RV64-SAME: (<vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], <vscale x 2 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzip.mask.nxv4i64.nxv2i64.i64(<vscale x 4 x i64> [[VD]], <vscale x 2 x i64> [[VS2]], <vscale x 2 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
-vuint64m4_t test_vzip_vv_u64m4_mu(vbool32_t vm, vuint64m4_t vd, vuint64m2_t vs2,
+vuint64m4_t test_vzip_vv_u64m4_mu(vbool16_t vm, vuint64m4_t vd, vuint64m2_t vs2,
vuint64m2_t vs1, size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vzip_vv_u64m8_mu
-// CHECK-RV64-SAME: (<vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], <vscale x 4 x i64> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzip.mask.nxv8i64.nxv4i64.i64(<vscale x 8 x i64> [[VD]], <vscale x 4 x i64> [[VS2]], <vscale x 4 x i64> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
-vuint64m8_t test_vzip_vv_u64m8_mu(vbool16_t vm, vuint64m8_t vd, vuint64m4_t vs2,
+vuint64m8_t test_vzip_vv_u64m8_mu(vbool8_t vm, vuint64m8_t vd, vuint64m4_t vs2,
vuint64m4_t vs1, size_t vl) {
return __riscv_vzip_mu(vm, vd, vs2, vs1, vl);
}
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index a9af276367817..a4933b2c0eb54 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -268,7 +268,7 @@
// CHECK-NEXT: zvvmm 0.1 'Zvvmm' (Integer Matrix Multiply-Accumulate)
// CHECK-NEXT: zvvmtls 0.1 'Zvvmtls' (Matrix Tile Load/Store)
// CHECK-NEXT: zvvmttls 0.1 'Zvvmttls' (Transposing Matrix Tile Load/Store)
-// CHECK-NEXT: zvzip 0.1 'Zvzip' (Vector Reordering Structured Data)
+// CHECK-NEXT: zvzip 0.2 'Zvzip' (Vector Reordering Structured Data)
// CHECK-NEXT: smpmpmt 0.6 'Smpmpmt' (PMP-based Memory Types Extension)
// CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
// CHECK-NEXT: xqccmt 0.1 'Xqccmt' (Qualcomm 16-bit Table Jump)
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 28031814da16a..e7ea0318a676a 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -1733,12 +1733,12 @@
// CHECK-ZVFWDOTA16BF-EXT: __riscv_zvfwdota16bf 2000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve32x_zvzip0p1 -E -dM %s \
+// RUN: -march=rv32i_zve32x_zvzip0p2 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVZVIP-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve32x_zvzip0p1 -E -dM %s \
+// RUN: -march=rv64i_zve32x_zvzip0p2 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVZVIP-EXT %s
-// CHECK-ZVZVIP-EXT: __riscv_zvzip 1000{{$}}
+// CHECK-ZVZVIP-EXT: __riscv_zvzip 2000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
// RUN: -march=rv32izicfiss1p0 -E -dM %s \
diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp b/clang/utils/TableGen/RISCVVEmitter.cpp
index 95b7e71b060ab..071b2f0b846e9 100644
--- a/clang/utils/TableGen/RISCVVEmitter.cpp
+++ b/clang/utils/TableGen/RISCVVEmitter.cpp
@@ -65,6 +65,7 @@ struct SemaRecord {
bool HasTailPolicy : 1;
bool HasMaskPolicy : 1;
bool HasFRMRoundModeOp : 1;
+ bool MaskedPrototypeHasResultMask : 1;
bool AltFmt : 1;
bool IsTuple : 1;
LLVM_PREFERRED_TYPE(PolicyScheme)
@@ -668,6 +669,8 @@ void RVVEmitter::createRVVIntrinsics(
std::vector<int64_t> Log2LMULList = R->getValueAsListOfInts("Log2LMUL");
bool HasTailPolicy = R->getValueAsBit("HasTailPolicy");
bool HasMaskPolicy = R->getValueAsBit("HasMaskPolicy");
+ bool MaskedPrototypeHasResultMask =
+ R->getValueAsBit("MaskedPrototypeHasResultMask");
bool AltFmt = R->getValueAsBit("AltFmt");
bool SupportOverloading = R->getValueAsBit("SupportOverloading");
bool HasBuiltinAlias = R->getValueAsBit("HasBuiltinAlias");
@@ -709,6 +712,9 @@ void RVVEmitter::createRVVIntrinsics(
MaskedPrototype = RVVIntrinsic::computeBuiltinTypes(
BasicPrototype, /*IsMasked=*/true, HasMaskedOffOperand, HasVL, NF,
MaskedPolicyScheme, DefaultPolicy, IsTuple);
+ if (HasMasked && MaskedPrototypeHasResultMask)
+ MaskedPrototype[1] = PrototypeDescriptor(
+ BaseTypeModifier::Vector, VectorTypeModifier::DoubleLMULMaskVector);
// Create Intrinsics for each type and LMUL.
for (char I : TypeRange) {
@@ -765,6 +771,10 @@ void RVVEmitter::createRVVIntrinsics(
RVVIntrinsic::computeBuiltinTypes(
BasicPrototype, /*IsMasked=*/true, HasMaskedOffOperand, HasVL,
NF, MaskedPolicyScheme, P, IsTuple);
+ if (MaskedPrototypeHasResultMask)
+ PolicyPrototype[1] =
+ PrototypeDescriptor(BaseTypeModifier::Vector,
+ VectorTypeModifier::DoubleLMULMaskVector);
std::optional<RVVTypes> PolicyTypes =
TypeCache.computeTypes(BT, Log2LMUL, NF, PolicyPrototype);
Out.push_back(std::make_unique<RVVIntrinsic>(
@@ -810,6 +820,7 @@ void RVVEmitter::createRVVIntrinsics(
SR.HasMaskedOffOperand = HasMaskedOffOperand;
SR.HasTailPolicy = HasTailPolicy;
SR.HasMaskPolicy = HasMaskPolicy;
+ SR.MaskedPrototypeHasResultMask = MaskedPrototypeHasResultMask;
SR.AltFmt = AltFmt;
SR.UnMaskedPolicyScheme = static_cast<uint8_t>(UnMaskedPolicyScheme);
SR.MaskedPolicyScheme = static_cast<uint8_t>(MaskedPolicyScheme);
@@ -855,6 +866,7 @@ void RVVEmitter::createRVVIntrinsicRecords(std::vector<RVVIntrinsicRecord> &Out,
R.HasMaskedOffOperand = SR.HasMaskedOffOperand;
R.HasTailPolicy = SR.HasTailPolicy;
R.HasMaskPolicy = SR.HasMaskPolicy;
+ R.MaskedPrototypeHasResultMask = SR.MaskedPrototypeHasResultMask;
R.AltFmt = SR.AltFmt;
R.UnMaskedPolicyScheme = SR.UnMaskedPolicyScheme;
R.MaskedPolicyScheme = SR.MaskedPolicyScheme;
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 72428398fc465..864957d54a176 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -368,7 +368,7 @@ The primary goal of experimental support is to assist in the process of ratifica
LLVM implements the `0.7 draft specification <https://github.com/riscv/integer-vector-absolute-difference/releases/tag/v0.7>`__.
``experimental-zvzip``
- LLVM implements the `0.1 draft specification <https://github.com/ved-rivos/riscv-isa-manual/blob/zvzip/src/zvzip.adoc>`__.
+ LLVM implements the `0.2 draft specification <https://github.com/riscv/riscv-isa-manual/pull/3233>`__.
``experimental-zvvfmm``
LLVM implements the `0.1 draft specification <https://github.com/riscv/integrated-matrix-extension/releases/tag/riscv-isa-release-71c48b9-2026-05-17>`__.
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index fca28455f2117..ba88a3448d841 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -1958,7 +1958,7 @@ let TargetPrefix = "riscv" in {
DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_anyvector_ty,
LLVMMatchType<1>,
- LLVMScalarOrSameVectorWidth<1, llvm_i1_ty>,
+ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyint_ty, LLVMMatchType<2>],
[ImmArg<ArgIndex<5>>, IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 4;
@@ -1974,16 +1974,6 @@ let TargetPrefix = "riscv" in {
[IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 2;
}
-
- // Input: (maskedoff, vector_in, mask, vl, policy)
- def "int_riscv_" # NAME # "_mask" :
- DefaultAttrsIntrinsic<[llvm_anyvector_ty],
- [LLVMMatchType<0>, llvm_anyvector_ty,
- LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
- llvm_anyint_ty, LLVMMatchType<2>],
- [ImmArg<ArgIndex<4>>, IntrNoMem]>, RISCVVIntrinsic {
- let VLOperand = 3;
- }
}
defm vzip : RISCVZip;
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 03d28b8448ba4..e180b8430e849 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -917,7 +917,7 @@ def HasStdExtZvdot4a8i : Predicate<"Subtarget->hasStdExtZvdot4a8i()">,
// Vector Reordering Structured Data
def FeatureStdExtZvzip
- : RISCVExperimentalExtension<0, 1, "Vector Reordering Structured Data",
+ : RISCVExperimentalExtension<0, 2, "Vector Reordering Structured Data",
[FeatureStdExtZve32x]>;
def HasStdExtZvzip : Predicate<"Subtarget->hasStdExtZvzip()">,
AssemblerPredicate<(all_of FeatureStdExtZvzip),
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 8b3b555cb2656..b3863074df825 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -5327,7 +5327,8 @@ static SDValue getSingleShuffleSrc(MVT VT, SDValue V1, SDValue V2) {
return SDValue();
}
-static bool isLegalVTForZvzipOperand(MVT VT, const RISCVSubtarget &Subtarget) {
+static bool
+isLegalVTForZvzipDeinterleavedOperand(MVT VT, const RISCVSubtarget &Subtarget) {
MVT ContainerVT = VT;
if (VT.isFixedLengthVector())
ContainerVT = getContainerForFixedLengthVector(VT, Subtarget);
@@ -5335,6 +5336,14 @@ static bool isLegalVTForZvzipOperand(MVT VT, const RISCVSubtarget &Subtarget) {
return RISCVTargetLowering::getLMUL(ContainerVT) != RISCVVType::LMUL_8;
}
+static bool
+isLegalVTForZvzipInterleavedOperand(MVT VT, const RISCVSubtarget &Subtarget) {
+ MVT ContainerVT = VT;
+ if (VT.isFixedLengthVector())
+ ContainerVT = getContainerForFixedLengthVector(VT, Subtarget);
+ return RISCVTargetLowering::getLMUL(ContainerVT) != RISCVVType::LMUL_F8;
+}
+
/// Is this shuffle interleaving contiguous elements from one vector into the
/// even elements and contiguous elements from another vector into the odd
/// elements. \p EvenSrc will contain the element that should be in the first
@@ -5348,7 +5357,7 @@ static bool isInterleaveShuffle(ArrayRef<int> Mask, MVT VT, int &EvenSrc,
if (VT.getScalarSizeInBits() >= Subtarget.getELen()) {
if (!Subtarget.hasStdExtZvzip())
return false;
- if (!isLegalVTForZvzipOperand(VT, Subtarget))
+ if (!isLegalVTForZvzipInterleavedOperand(VT, Subtarget))
return false;
}
@@ -5847,7 +5856,8 @@ static SDValue lowerZvzipVZIP(SDValue Op0, SDValue Op1, const SDLoc &DL,
Op1 = convertToScalableVector(ContainerVT, Op1, DAG, Subtarget);
}
MVT ResVT = ContainerVT.getDoubleNumVectorElementsVT();
- auto [Mask, VL] = getDefaultVLOps(IntVT, ContainerVT, DL, DAG, Subtarget);
+ auto [Mask, VL] = getDefaultVLOps(IntVT.getDoubleNumVectorElementsVT(), ResVT,
+ DL, DAG, Subtarget);
SDValue Passthru = DAG.getUNDEF(ResVT);
SDValue Res =
DAG.getNode(RISCVISD::VZIP_VL, DL, ResVT, Op0, Op1, Passthru, Mask, VL);
@@ -5883,10 +5893,13 @@ static SDValue lowerZvzipVUNZIP(unsigned Opc, SDValue Op, const SDLoc &DL,
MVT ResVT = ContainerVT.getHalfNumVectorElementsVT();
MVT HalfVT = VT.getHalfNumVectorElementsVT();
MVT HalfIntVT = IntVT.getHalfNumVectorElementsVT();
- auto [Mask, VL] = getDefaultVLOps(ResVT, ResVT, DL, DAG, Subtarget);
- if (VT.isFixedLengthVector())
- VL = DAG.getConstant(VT.getVectorNumElements() / 2, DL,
+ SDValue VL;
+ if (IntVT.isFixedLengthVector())
+ VL = DAG.getConstant(IntVT.getVectorNumElements(), DL,
Subtarget.getXLenVT());
+ else
+ VL = DAG.getRegister(RISCV::X0, Subtarget.getXLenVT());
+ SDValue Mask = getAllOnesMask(ResVT, VL, DL, DAG);
SDValue Passthru = DAG.getUNDEF(ResVT);
SDValue Res = DAG.getNode(Opc, DL, ResVT, Op, Passthru, Mask, VL);
if (HalfIntVT.isFixedLengthVector())
@@ -6755,10 +6768,11 @@ SDValue RISCVTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
1 < count_if(Mask,
[&Mask](int Idx) { return Idx >= (int)Mask.size(); });
- if (isLegalVTForZvzipOperand(VT, Subtarget)) {
+ if (isLegalVTForZvzipDeinterleavedOperand(VT, Subtarget)) {
unsigned Opc = Index == 0 ? RISCVISD::VUNZIPE_VL : RISCVISD::VUNZIPO_VL;
MVT NewVT = VT.getDoubleNumVectorElementsVT();
- if (isTypeLegal(NewVT)) {
+ if (isTypeLegal(NewVT) &&
+ isLegalVTForZvzipInterleavedOperand(NewVT, Subtarget)) {
SDValue Op;
if (V2.isUndef()) {
Op = DAG.getNode(ISD::CONCAT_VECTORS, DL, NewVT, V1, V2);
@@ -6773,6 +6787,8 @@ SDValue RISCVTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
}
if (UsesBothSources &&
+ isLegalVTForZvzipInterleavedOperand(V1.getSimpleValueType(),
+ Subtarget) &&
V1.getSimpleValueType().getVectorMinNumElements() >= 2 &&
V2.getSimpleValueType().getVectorMinNumElements() >= 2) {
SDValue Lo = lowerZvzipVUNZIP(Opc, V1, DL, DAG, Subtarget);
@@ -6822,7 +6838,9 @@ SDValue RISCVTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
// Prefer vzip if available.
// TODO: Extend to matching vzip if EvenSrc and OddSrc allow.
- if (Subtarget.hasStdExtZvzip() && isLegalVTForZvzipOperand(VT, Subtarget))
+ if (Subtarget.hasStdExtZvzip() &&
+ isLegalVTForZvzipInterleavedOperand(VT, Subtarget) &&
+ isLegalVTForZvzipDeinterleavedOperand(HalfVT, Subtarget))
return lowerZvzipVZIP(EvenV, OddV, DL, DAG, Subtarget);
return getWideningInterleave(EvenV, OddV, DL, DAG, Subtarget);
}
@@ -13508,7 +13526,9 @@ SDValue RISCVTargetLowering::lowerVECTOR_DEINTERLEAVE(SDValue Op,
if (Subtarget.hasStdExtZvzip() && Factor == 2 && !IsFixedVector) {
MVT VT = Op->getSimpleValueType(0);
MVT NewVT = VT.getDoubleNumVectorElementsVT();
- if (isTypeLegal(NewVT) && isLegalVTForZvzipOperand(VT, Subtarget)) {
+ if (isTypeLegal(NewVT) &&
+ isLegalVTForZvzipDeinterleavedOperand(VT, Subtarget) &&
+ isLegalVTForZvzipInterleavedOperand(NewVT, Subtarget)) {
SDValue V1 = Op->getOperand(0);
SDValue V2 = Op->getOperand(1);
SDValue V = DAG.getNode(ISD::CONCAT_VECTORS, DL, NewVT, V1, V2);
@@ -13793,7 +13813,9 @@ SDValue RISCVTargetLowering::lowerVECTOR_INTERLEAVE(SDValue Op,
if (Subtarget.hasStdExtZvzip() && !Op.getOperand(0).isUndef() &&
!Op.getOperand(1).isUndef()) {
MVT VT = Op->getSimpleValueType(0);
- if (isLegalVTForZvzipOperand(VT, Subtarget)) {
+ if (isLegalVTForZvzipDeinterleavedOperand(VT, Subtarget) &&
+ isLegalVTForZvzipInterleavedOperand(VT.getDoubleNumVectorElementsVT(),
+ Subtarget)) {
// Freeze the sources so we can increase their use count.
SDValue V1 = DAG.getFreeze(Op->getOperand(0));
SDValue V2 = DAG.getFreeze(Op->getOperand(1));
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvzip.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvzip.td
index 6ed51a5da7478..903294cacb6f6 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvzip.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvzip.td
@@ -15,14 +15,23 @@
// Instructions
//===----------------------------------------------------------------------===//
+class VALUVs2NoVm<bits<6> funct6, bits<5> vs1, RISCVVFormat opv,
+ string opcodestr>
+ : RVInstVUnary<funct6, vs1, opv, (outs VR:$vd), (ins VR:$vs2), opcodestr,
+ "$vd, $vs2"> {
+ let vm = 1;
+ let VMConstraint = false;
+ let hasSideEffects = 0;
+ let mayLoad = 0;
+ let mayStore = 0;
+}
+
let Predicates = [HasStdExtZvzip], Constraints = "@earlyclobber $vd" in {
let VS1VS2Constraint = WidenV in
def VZIP_VV : VALUVV<0b111110, OPMVV, "vzip.vv">;
- let VS1VS2Constraint = VS2Constraint in {
- def VUNZIPE_V : VALUVs2<0b010010, 0b01011, OPMVV, "vunzipe.v">;
- def VUNZIPO_V : VALUVs2<0b010010, 0b01111, OPMVV, "vunzipo.v">;
- }
+ def VUNZIPE_V : VALUVs2NoVm<0b010010, 0b01011, OPMVV, "vunzipe.v">;
+ def VUNZIPO_V : VALUVs2NoVm<0b010010, 0b01111, OPMVV, "vunzipo.v">;
let VS1VS2Constraint = Vrgather in {
def VPAIRE_VV : VALUVV<0b001111, OPIVV, "vpaire.vv">;
@@ -80,23 +89,36 @@ defset list<VTypeInfoToWide> AllZvzipVectors = {
}
multiclass VPseudoVZIP {
- foreach m = MxListW in
- defm "" : VPseudoBinaryW_VV<m, Commutable=0>,
- SchedBinary<"WriteVIWALUV", "ReadVIWALUV", "ReadVIWALUV", m.MX,
- forcePassthruRead=true>;
+ foreach m = MxListW in {
+ defvar wideM = !cast<LMULInfo>("V_" # octuple_to_str<!shl(m.octuple, 1)>.ret);
+ let VLMul = wideM.value, isCommutable = 0 in {
+ def "_VV_" # m.MX : VPseudoBinaryNoMaskPolicy<m.wvrclass, m.vrclass,
+ m.vrclass,
+ "@earlyclobber $rd",
+ TargetConstraintType=3>,
+ SchedBinary<"WriteVIWALUV", "ReadVIWALUV",
+ "ReadVIWALUV", m.MX,
+ forcePassthruRead=true>;
+ def "_VV_" # m.MX # "_MASK" :
+ VPseudoBinaryMaskPolicy<m.wvrclass, m.vrclass, m.vrclass,
+ "@earlyclobber $rd",
+ TargetConstraintType=3>,
+ RISCVMaskedPseudo<MaskIdx=3>,
+ SchedBinary<"WriteVIWALUV", "ReadVIWALUV", "ReadVIWALUV", m.MX,
+ forcePassthruRead=true>;
+ }
+ }
}
multiclass VPseudoVUNZIP {
foreach m = MxListW in {
defvar mx = m.MX;
- let VLMul = m.value in {
- def "_V_" # mx : VPseudoUnaryNoMask<m.vrclass, m.wvrclass>,
+ defvar wideM = !cast<LMULInfo>("V_" # octuple_to_str<!shl(m.octuple, 1)>.ret);
+ let VLMul = wideM.value in {
+ def "_V_" # mx : VPseudoUnaryNoMask<m.vrclass, m.wvrclass,
+ TargetConstraintType=2>,
SchedUnary<"WriteVIALUV", "ReadVIALUV", mx,
forcePassthruRead=true>;
- def "_V_" # mx # "_MASK" :
- VPseudoUnaryMask<m.vrclass, m.wvrclass>,
- RISCVMaskedPseudo<MaskIdx=2>,
- SchedUnary<"WriteVIALUV", "ReadVIALUV", mx, forcePassthruRead=true>;
}
}
}
@@ -120,9 +142,26 @@ multiclass VPatVUnzipIntrinsic<string intrinsic_name,
def : VPatUnaryNoMask<intrinsic_name, instruction_name, "V",
vti.Vector, wti.Vector, vti.Log2SEW,
vti.LMul, vti.RegClass, wti.RegClass>;
- def : VPatUnaryMask<intrinsic_name, instruction_name, "V",
- vti.Vector, wti.Vector, vti.Mask, vti.Log2SEW,
- vti.LMul, vti.RegClass, wti.RegClass>;
+ }
+ }
+}
+
+multiclass VPatVZipIntrinsic<string intrinsic_name, string instruction_name> {
+ foreach VtiToWti = AllZvzipVectors in {
+ defvar vti = VtiToWti.Vti;
+ defvar wti = VtiToWti.Wti;
+ let Predicates = !listconcat(GetVTypeMinimalPredicates<wti>.Predicates,
+ [HasStdExtZvzip]) in {
+ def : VPatBinaryNoMaskTU<intrinsic_name,
+ instruction_name # "_VV_" # vti.LMul.MX,
+ wti.Vector, vti.Vector, vti.Vector,
+ vti.Log2SEW, wti.RegClass, vti.RegClass,
+ vti.RegClass>;
+ def : VPatBinaryMaskPolicy<intrinsic_name,
+ instruction_name # "_VV_" # vti.LMul.MX,
+ wti.Vector, vti.Vector, vti.Vector, wti.Mask,
+ vti.Log2SEW, wti.RegClass, vti.RegClass,
+ vti.RegClass>;
}
}
}
@@ -135,9 +174,7 @@ defm : VPatBinaryV_VV<"int_riscv_vpaire", "PseudoVPAIRE", AllVectors,
defm : VPatBinaryV_VV<"int_riscv_vpairo", "PseudoVPAIRO", AllVectors,
ExtraPreds = [HasStdExtZvzip],
requireMinimal = true>;
-defm : VPatBinaryW_VV<"int_riscv_vzip", "PseudoVZIP", AllZvzipVectors,
- ExtraPreds = [HasStdExtZvzip],
- requireMinimal = true>;
+defm : VPatVZipIntrinsic<"int_riscv_vzip", "PseudoVZIP">;
// (vd (op vs2, vs1, passthru, mask, vl))
def SDT_RISCVZip_VL : SDTypeProfile<1, 5, [SDTCisVec<0>, SDTCisVec<1>,
@@ -145,7 +182,7 @@ def SDT_RISCVZip_VL : SDTypeProfile<1, 5, [SDTCisVec<0>, SDTCisVec<1>,
SDTCisSameAs<1, 2>,
SDTCisSameAs<0, 3>,
SDTCVecEltisVT<4, i1>,
- SDTCisSameNumEltsAs<1, 4>,
+ SDTCisSameNumEltsAs<0, 4>,
SDTCisVT<5, XLenVT>]>;
// (vd (op vs2, passthru, mask, vl))
@@ -177,11 +214,16 @@ multiclass VPatVZIP<SDPatternOperator vop, string instruction_name> {
defvar vti = VtiToWti.Vti;
defvar wti = VtiToWti.Wti;
let Predicates = !listconcat([HasStdExtZvzip],
- GetVTypeMinimalPredicates<vti>.Predicates) in {
- def : VPatBinaryVL_V<vop, instruction_name, "VV",
- wti.Vector, vti.Vector, vti.Vector, vti.Mask,
- vti.Log2SEW, vti.LMul, wti.RegClass, vti.RegClass,
- vti.RegClass>;
+ GetVTypeMinimalPredicates<wti>.Predicates) in {
+ def : Pat<(wti.Vector (vop (vti.Vector vti.RegClass:$rs1),
+ (vti.Vector vti.RegClass:$rs2),
+ wti.RegClass:$passthru,
+ (wti.Mask VMV0:$vm), VLOpFrag)),
+ (!cast<Instruction>(instruction_name # "_VV_" # vti.LMul.MX #
+ "_MASK")
+ wti.RegClass:$passthru, vti.RegClass:$rs1,
+ vti.RegClass:$rs2, (wti.Mask VMV0:$vm), GPR:$vl,
+ vti.Log2SEW, TAIL_AGNOSTIC)>;
}
}
}
@@ -191,10 +233,13 @@ multiclass VPatVUNZIP<SDPatternOperator op, string instruction_name> {
defvar vti = VtiToWti.Vti;
defvar wti = VtiToWti.Wti;
let Predicates = !listconcat([HasStdExtZvzip],
- GetVTypeMinimalPredicates<vti>.Predicates) in {
- def : VPatUnaryVL_V<op, instruction_name, "V",
- vti.Vector, wti.Vector, vti.Mask, vti.Log2SEW,
- vti.LMul, vti.RegClass, wti.RegClass>;
+ GetVTypeMinimalPredicates<wti>.Predicates) in {
+ def : Pat<(vti.Vector (op (wti.Vector wti.RegClass:$rs2),
+ vti.RegClass:$passthru, (vti.Mask true_mask),
+ VLOpFrag)),
+ (!cast<Instruction>(instruction_name # "_V_" # vti.LMul.MX)
+ vti.RegClass:$passthru, wti.RegClass:$rs2, GPR:$vl,
+ vti.Log2SEW, TU_MU)>;
}
}
}
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 26ffd8bb4ec89..0a8289d36b231 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -452,7 +452,7 @@
; RV32ZVKSH: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksh1p0_zvl32b1p0"
; RV32ZVKT: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkt1p0_zvl32b1p0"
; RV32ZVDOT4A8I: .attribute 5, "rv32i2p1_zicsr2p0_zvdot4a8i0p1_zve32x1p0_zvl32b1p0"
-; RV32ZVZIP: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvzip0p1"
+; RV32ZVZIP: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvzip0p2"
; RV32ZVFH: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0"
; RV32ZVABD: .attribute 5, "rv32i2p1_zicsr2p0_zvabd0p7_zve32x1p0_zvl32b1p0"
; RV32ZICOND: .attribute 5, "rv32i2p1_zicond1p0"
@@ -617,7 +617,7 @@
; RV64ZVQWDOTA16I: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_zvqwdota16i0p2"
; RV64ZVFWDOTA16BF: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfwdota16bf0p2_zvl32b1p0"
; RV64ZVFQWDOTA8F: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfqwdota8f0p2_zvl32b1p0"
-; RV64ZVZIP: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvzip0p1"
+; RV64ZVZIP: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvzip0p2"
; RV64ZVFH: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0"
; RV64ZVABD: .attribute 5, "rv64i2p1_zicsr2p0_zvabd0p7_zve32x1p0_zvl32b1p0"
; RV64ZICOND: .attribute 5, "rv64i2p1_zicond1p0"
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
index 94429ac18dd3d..ff8ce7f3ca996 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
@@ -414,8 +414,9 @@ define void @vnsrl_0_i64(ptr %in, ptr %out) {
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
; ZVZIP-NEXT: vle64.v v8, (a0)
-; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; ZVZIP-NEXT: vunzipe.v v10, v8
+; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; ZVZIP-NEXT: vse64.v v10, (a1)
; ZVZIP-NEXT: ret
entry:
@@ -449,8 +450,9 @@ define void @vnsrl_64_i64(ptr %in, ptr %out) {
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
; ZVZIP-NEXT: vle64.v v8, (a0)
-; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; ZVZIP-NEXT: vunzipo.v v10, v8
+; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; ZVZIP-NEXT: vse64.v v10, (a1)
; ZVZIP-NEXT: ret
entry:
@@ -483,8 +485,9 @@ define void @vnsrl_0_double(ptr %in, ptr %out) {
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
; ZVZIP-NEXT: vle64.v v8, (a0)
-; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; ZVZIP-NEXT: vunzipe.v v10, v8
+; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; ZVZIP-NEXT: vse64.v v10, (a1)
; ZVZIP-NEXT: ret
entry:
@@ -518,8 +521,9 @@ define void @vnsrl_64_double(ptr %in, ptr %out) {
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
; ZVZIP-NEXT: vle64.v v8, (a0)
-; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; ZVZIP-NEXT: vunzipo.v v10, v8
+; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; ZVZIP-NEXT: vse64.v v10, (a1)
; ZVZIP-NEXT: ret
entry:
@@ -1525,7 +1529,7 @@ define <4 x i64> @unzip2a_dual_v4i64(<4 x i64> %a, <4 x i64> %b) {
;
; ZVZIP-LABEL: unzip2a_dual_v4i64:
; ZVZIP: # %bb.0: # %entry
-; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; ZVZIP-NEXT: vmv1r.v v10, v9
; ZVZIP-NEXT: vunzipe.v v12, v10
; ZVZIP-NEXT: vunzipe.v v10, v8
@@ -1661,10 +1665,9 @@ define <16 x i64> @unzip2a_dual_v16i64(<16 x i64> %a, <16 x i64> %b) {
;
; ZVZIP-LABEL: unzip2a_dual_v16i64:
; ZVZIP: # %bb.0: # %entry
-; ZVZIP-NEXT: vsetivli zero, 8, e64, m2, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 16, e64, m4, ta, ma
; ZVZIP-NEXT: vunzipe.v v16, v12
; ZVZIP-NEXT: vunzipe.v v12, v8
-; ZVZIP-NEXT: vsetivli zero, 16, e64, m4, ta, ma
; ZVZIP-NEXT: vslideup.vi v12, v16, 8
; ZVZIP-NEXT: vmv.v.v v8, v12
; ZVZIP-NEXT: ret
@@ -1712,9 +1715,9 @@ define <4 x i64> @unzip2a_dual_v4i64_exact(<4 x i64> %a, <4 x i64> %b) vscale_ra
;
; ZVZIP-LABEL: unzip2a_dual_v4i64_exact:
; ZVZIP: # %bb.0: # %entry
-; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 8, e64, m2, ta, ma
; ZVZIP-NEXT: vunzipe.v v10, v8
-; ZVZIP-NEXT: vmv.v.v v8, v10
+; ZVZIP-NEXT: vmv1r.v v8, v10
; ZVZIP-NEXT: ret
entry:
%c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
@@ -1760,7 +1763,7 @@ define <4 x i64> @unzip2a_dual_v4i64_exact_nf2(<4 x i64> %a, <4 x i64> %b) vscal
;
; ZVZIP-LABEL: unzip2a_dual_v4i64_exact_nf2:
; ZVZIP: # %bb.0: # %entry
-; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; ZVZIP-NEXT: vmv1r.v v10, v9
; ZVZIP-NEXT: vunzipe.v v12, v10
; ZVZIP-NEXT: vunzipe.v v10, v8
@@ -1891,9 +1894,9 @@ define <16 x i64> @unzip2a_dual_v16i64_exact(<16 x i64> %a, <16 x i64> %b) vscal
;
; ZVZIP-LABEL: unzip2a_dual_v16i64_exact:
; ZVZIP: # %bb.0: # %entry
-; ZVZIP-NEXT: vsetivli zero, 16, e64, m4, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; ZVZIP-NEXT: vunzipe.v v16, v8
-; ZVZIP-NEXT: vmv.v.v v8, v16
+; ZVZIP-NEXT: vmv4r.v v8, v16
; ZVZIP-NEXT: ret
entry:
%c = shufflevector <16 x i64> %a, <16 x i64> %b, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
@@ -1940,7 +1943,7 @@ define <4 x i64> @unzip2b_dual_v4i64(<4 x i64> %a, <4 x i64> %b) {
;
; ZVZIP-LABEL: unzip2b_dual_v4i64:
; ZVZIP: # %bb.0: # %entry
-; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; ZVZIP-NEXT: vmv1r.v v10, v9
; ZVZIP-NEXT: vunzipo.v v12, v10
; ZVZIP-NEXT: vunzipo.v v10, v8
@@ -1993,9 +1996,9 @@ define <4 x i64> @unzip2b_dual_v4i64_exact(<4 x i64> %a, <4 x i64> %b) vscale_ra
;
; ZVZIP-LABEL: unzip2b_dual_v4i64_exact:
; ZVZIP: # %bb.0: # %entry
-; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 8, e64, m2, ta, ma
; ZVZIP-NEXT: vunzipo.v v10, v8
-; ZVZIP-NEXT: vmv.v.v v8, v10
+; ZVZIP-NEXT: vmv1r.v v8, v10
; ZVZIP-NEXT: ret
entry:
%c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
index b4fdd5f9a9d37..9959c91faebcc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
@@ -20,7 +20,7 @@ define <4 x i8> @interleave_v2i8(<2 x i8> %x, <2 x i8> %y) {
;
; ZVZIP-LABEL: interleave_v2i8:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; ZVZIP-NEXT: vzip.vv v10, v8, v9
; ZVZIP-NEXT: vmv1r.v v8, v10
; ZVZIP-NEXT: ret
@@ -40,7 +40,7 @@ define <4 x i16> @interleave_v2i16(<2 x i16> %x, <2 x i16> %y) {
;
; ZVZIP-LABEL: interleave_v2i16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVZIP-NEXT: vzip.vv v10, v8, v9
; ZVZIP-NEXT: vmv1r.v v8, v10
; ZVZIP-NEXT: ret
@@ -61,9 +61,9 @@ define <4 x i32> @interleave_v2i32(<2 x i32> %x, <2 x i32> %y) {
;
; ZVZIP-LABEL: interleave_v2i32:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVZIP-NEXT: vzip.vv v10, v9, v8
-; ZVZIP-NEXT: vmv1r.v v8, v10
+; ZVZIP-NEXT: vmv.v.v v8, v10
; ZVZIP-NEXT: ret
%a = shufflevector <2 x i32> %x, <2 x i32> %y, <4 x i32> <i32 2, i32 0, i32 3, i32 1>
ret <4 x i32> %a
@@ -99,7 +99,7 @@ define <4 x i64> @interleave_v2i64(<2 x i64> %x, <2 x i64> %y) {
;
; ZVZIP-LABEL: interleave_v2i64:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; ZVZIP-NEXT: vmv1r.v v10, v9
; ZVZIP-NEXT: vmv1r.v v11, v8
; ZVZIP-NEXT: vzip.vv v8, v11, v10
@@ -130,7 +130,7 @@ define <8 x i8> @interleave_v4i8(<4 x i8> %x, <4 x i8> %y) {
;
; ZVZIP-LABEL: interleave_v4i8:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; ZVZIP-NEXT: vzip.vv v10, v9, v8
; ZVZIP-NEXT: vmv1r.v v8, v10
; ZVZIP-NEXT: ret
@@ -160,9 +160,9 @@ define <8 x i16> @interleave_v4i16(<4 x i16> %x, <4 x i16> %y) {
;
; ZVZIP-LABEL: interleave_v4i16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVZIP-NEXT: vzip.vv v10, v8, v9
-; ZVZIP-NEXT: vmv1r.v v8, v10
+; ZVZIP-NEXT: vmv.v.v v8, v10
; ZVZIP-NEXT: ret
%a = shufflevector <4 x i16> %x, <4 x i16> %y, <8 x i32> <i32 0, i32 4, i32 poison, i32 5, i32 2, i32 poison, i32 3, i32 7>
ret <8 x i16> %a
@@ -190,7 +190,7 @@ define <8 x i32> @interleave_v4i32(<4 x i32> %x, <4 x i32> %y) {
;
; ZVZIP-LABEL: interleave_v4i32:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVZIP-NEXT: vmv1r.v v10, v9
; ZVZIP-NEXT: vmv1r.v v11, v8
; ZVZIP-NEXT: vzip.vv v8, v11, v10
@@ -226,9 +226,9 @@ define <4 x i32> @interleave_v4i32_offset_2(<4 x i32> %x, <4 x i32> %y) {
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; ZVZIP-NEXT: vslidedown.vi v10, v9, 2
-; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVZIP-NEXT: vzip.vv v9, v8, v10
-; ZVZIP-NEXT: vmv1r.v v8, v9
+; ZVZIP-NEXT: vmv.v.v v8, v9
; ZVZIP-NEXT: ret
%a = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 6, i32 1, i32 7>
ret <4 x i32> %a
@@ -269,9 +269,7 @@ define <4 x i32> @interleave_v4i32_offset_1(<4 x i32> %x, <4 x i32> %y) {
; ZVZIP-NEXT: vmv1r.v v10, v9
; ZVZIP-NEXT: vslideup.vi v10, v9, 1, v0.t
; ZVZIP-NEXT: vmv.v.i v0, 10
-; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVZIP-NEXT: vzip.vv v11, v8, v9
-; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVZIP-NEXT: vmerge.vvm v8, v11, v10, v0
; ZVZIP-NEXT: ret
%a = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 5, i32 1, i32 6>
@@ -299,9 +297,9 @@ define <16 x i8> @interleave_v8i8(<8 x i8> %x, <8 x i8> %y) {
;
; ZVZIP-LABEL: interleave_v8i8:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; ZVZIP-NEXT: vzip.vv v10, v8, v9
-; ZVZIP-NEXT: vmv1r.v v8, v10
+; ZVZIP-NEXT: vmv.v.v v8, v10
; ZVZIP-NEXT: ret
%a = shufflevector <8 x i8> %x, <8 x i8> %y, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
ret <16 x i8> %a
@@ -330,7 +328,7 @@ define <16 x i16> @interleave_v8i16(<8 x i16> %x, <8 x i16> %y) {
;
; ZVZIP-LABEL: interleave_v8i16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVZIP-NEXT: vmv1r.v v10, v9
; ZVZIP-NEXT: vmv1r.v v11, v8
; ZVZIP-NEXT: vzip.vv v8, v10, v11
@@ -361,7 +359,7 @@ define <16 x i32> @interleave_v8i32(<8 x i32> %x, <8 x i32> %y) {
;
; ZVZIP-LABEL: interleave_v8i32:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVZIP-NEXT: vmv2r.v v12, v10
; ZVZIP-NEXT: vmv2r.v v14, v8
; ZVZIP-NEXT: vzip.vv v8, v14, v12
@@ -392,7 +390,8 @@ define <32 x i8> @interleave_v16i8(<16 x i8> %x, <16 x i8> %y) {
;
; ZVZIP-LABEL: interleave_v16i8:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; ZVZIP-NEXT: li a0, 32
+; ZVZIP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; ZVZIP-NEXT: vmv1r.v v10, v9
; ZVZIP-NEXT: vmv1r.v v11, v8
; ZVZIP-NEXT: vzip.vv v8, v11, v10
@@ -423,7 +422,8 @@ define <32 x i16> @interleave_v16i16(<16 x i16> %x, <16 x i16> %y) {
;
; ZVZIP-LABEL: interleave_v16i16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVZIP-NEXT: li a0, 32
+; ZVZIP-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; ZVZIP-NEXT: vmv2r.v v12, v10
; ZVZIP-NEXT: vmv2r.v v14, v8
; ZVZIP-NEXT: vzip.vv v8, v14, v12
@@ -455,12 +455,11 @@ define <32 x i32> @interleave_v16i32(<16 x i32> %x, <16 x i32> %y) {
;
; ZVZIP-LABEL: interleave_v16i32:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; ZVZIP-NEXT: li a0, 32
+; ZVZIP-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; ZVZIP-NEXT: vmv4r.v v16, v12
; ZVZIP-NEXT: vmv4r.v v20, v8
-; ZVZIP-NEXT: vwaddu.vv v8, v20, v16
-; ZVZIP-NEXT: li a0, -1
-; ZVZIP-NEXT: vwmaccu.vx v8, a0, v16
+; ZVZIP-NEXT: vzip.vv v8, v20, v16
; ZVZIP-NEXT: ret
%a = shufflevector <16 x i32> %x, <16 x i32> %y, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
ret <32 x i32> %a
@@ -490,8 +489,8 @@ define <64 x i8> @interleave_v32i8(<32 x i8> %x, <32 x i8> %y) {
;
; ZVZIP-LABEL: interleave_v32i8:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: li a0, 32
-; ZVZIP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; ZVZIP-NEXT: li a0, 64
+; ZVZIP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; ZVZIP-NEXT: vmv2r.v v12, v10
; ZVZIP-NEXT: vmv2r.v v14, v8
; ZVZIP-NEXT: vzip.vv v8, v14, v12
@@ -525,13 +524,11 @@ define <64 x i16> @interleave_v32i16(<32 x i16> %x, <32 x i16> %y) {
;
; ZVZIP-LABEL: interleave_v32i16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: li a0, 32
-; ZVZIP-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVZIP-NEXT: li a0, 64
+; ZVZIP-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; ZVZIP-NEXT: vmv4r.v v16, v12
; ZVZIP-NEXT: vmv4r.v v20, v8
-; ZVZIP-NEXT: vwaddu.vv v8, v20, v16
-; ZVZIP-NEXT: li a0, -1
-; ZVZIP-NEXT: vwmaccu.vx v8, a0, v16
+; ZVZIP-NEXT: vzip.vv v8, v20, v16
; ZVZIP-NEXT: ret
%a = shufflevector <32 x i16> %x, <32 x i16> %y, <64 x i32> <i32 0, i32 32, i32 1, i32 33, i32 2, i32 34, i32 3, i32 35, i32 4, i32 36, i32 5, i32 37, i32 6, i32 38, i32 7, i32 39, i32 8, i32 40, i32 9, i32 41, i32 10, i32 42, i32 11, i32 43, i32 12, i32 44, i32 13, i32 45, i32 14, i32 46, i32 15, i32 47, i32 16, i32 48, i32 17, i32 49, i32 18, i32 50, i32 19, i32 51, i32 20, i32 52, i32 21, i32 53, i32 22, i32 54, i32 23, i32 55, i32 24, i32 56, i32 25, i32 57, i32 26, i32 58, i32 27, i32 59, i32 28, i32 60, i32 29, i32 61, i32 30, i32 62, i32 31, i32 63>
ret <64 x i16> %a
@@ -594,35 +591,39 @@ define <64 x i32> @interleave_v32i32(<32 x i32> %x, <32 x i32> %y) {
; ZVZIP-NEXT: addi sp, sp, -16
; ZVZIP-NEXT: .cfi_def_cfa_offset 16
; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: slli a0, a0, 3
+; ZVZIP-NEXT: slli a0, a0, 4
; ZVZIP-NEXT: sub sp, sp, a0
-; ZVZIP-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; ZVZIP-NEXT: addi a0, sp, 16
-; ZVZIP-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; ZVZIP-NEXT: li a0, 32
+; ZVZIP-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 3
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 16
+; ZVZIP-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; ZVZIP-NEXT: vsetivli zero, 16, e32, m8, ta, ma
-; ZVZIP-NEXT: vslidedown.vi v24, v16, 16
-; ZVZIP-NEXT: vslidedown.vi v0, v8, 16
-; ZVZIP-NEXT: vmv4r.v v8, v24
-; ZVZIP-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; ZVZIP-NEXT: vzext.vf2 v24, v8
-; ZVZIP-NEXT: vsll.vx v24, v24, a0
-; ZVZIP-NEXT: vzext.vf2 v8, v0
-; ZVZIP-NEXT: lui a1, 699051
-; ZVZIP-NEXT: addi a1, a1, -1366
-; ZVZIP-NEXT: vmv.s.x v0, a1
+; ZVZIP-NEXT: vslidedown.vi v0, v16, 16
+; ZVZIP-NEXT: vslidedown.vi v24, v8, 16
+; ZVZIP-NEXT: li a0, 32
; ZVZIP-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZVZIP-NEXT: vmerge.vvm v24, v8, v24, v0
+; ZVZIP-NEXT: vzip.vv v16, v12, v0
; ZVZIP-NEXT: addi a0, sp, 16
-; ZVZIP-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVZIP-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; ZVZIP-NEXT: vwaddu.vv v0, v8, v16
-; ZVZIP-NEXT: li a0, -1
-; ZVZIP-NEXT: vwmaccu.vx v0, a0, v16
-; ZVZIP-NEXT: vmv8r.v v8, v0
-; ZVZIP-NEXT: vmv8r.v v16, v24
+; ZVZIP-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vzip.vv v16, v24, v12
+; ZVZIP-NEXT: lui a0, 699051
+; ZVZIP-NEXT: addi a0, a0, -1366
+; ZVZIP-NEXT: vmv.s.x v0, a0
+; ZVZIP-NEXT: addi a0, sp, 16
+; ZVZIP-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vmerge.vvm v24, v16, v24, v0
; ZVZIP-NEXT: csrr a0, vlenb
; ZVZIP-NEXT: slli a0, a0, 3
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 16
+; ZVZIP-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vzip.vv v0, v8, v16
+; ZVZIP-NEXT: vmv.v.v v8, v0
+; ZVZIP-NEXT: vmv.v.v v16, v24
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 4
; ZVZIP-NEXT: add sp, sp, a0
; ZVZIP-NEXT: .cfi_def_cfa sp, 16
; ZVZIP-NEXT: addi sp, sp, 16
@@ -658,7 +659,7 @@ define <4 x i8> @unary_interleave_v4i8(<4 x i8> %x) {
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; ZVZIP-NEXT: vslidedown.vi v10, v8, 2
-; ZVZIP-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; ZVZIP-NEXT: vzip.vv v9, v8, v10
; ZVZIP-NEXT: vmv1r.v v8, v9
; ZVZIP-NEXT: ret
@@ -730,7 +731,7 @@ define <4 x i16> @unary_interleave_v4i16(<4 x i16> %x) {
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; ZVZIP-NEXT: vslidedown.vi v10, v8, 2
-; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVZIP-NEXT: vzip.vv v9, v8, v10
; ZVZIP-NEXT: vmv1r.v v8, v9
; ZVZIP-NEXT: ret
@@ -764,9 +765,9 @@ define <4 x i32> @unary_interleave_v4i32(<4 x i32> %x) {
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; ZVZIP-NEXT: vslidedown.vi v10, v8, 2
-; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVZIP-NEXT: vzip.vv v9, v8, v10
-; ZVZIP-NEXT: vmv1r.v v8, v9
+; ZVZIP-NEXT: vmv.v.v v8, v9
; ZVZIP-NEXT: ret
%a = shufflevector <4 x i32> %x, <4 x i32> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
ret <4 x i32> %a
@@ -815,9 +816,9 @@ define <4 x i64> @unary_interleave_v4i64(<4 x i64> %x) {
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 2, e64, m2, ta, ma
; ZVZIP-NEXT: vslidedown.vi v12, v8, 2
-; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; ZVZIP-NEXT: vzip.vv v10, v8, v12
-; ZVZIP-NEXT: vmv2r.v v8, v10
+; ZVZIP-NEXT: vmv.v.v v8, v10
; ZVZIP-NEXT: ret
%a = shufflevector <4 x i64> %x, <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
ret <4 x i64> %a
@@ -849,7 +850,7 @@ define <8 x i8> @unary_interleave_v8i8(<8 x i8> %x) {
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; ZVZIP-NEXT: vslidedown.vi v10, v8, 4
-; ZVZIP-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; ZVZIP-NEXT: vzip.vv v9, v8, v10
; ZVZIP-NEXT: vmv1r.v v8, v9
; ZVZIP-NEXT: ret
@@ -883,9 +884,9 @@ define <8 x i16> @unary_interleave_v8i16(<8 x i16> %x) {
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 4, e16, m1, ta, ma
; ZVZIP-NEXT: vslidedown.vi v10, v8, 4
-; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVZIP-NEXT: vzip.vv v9, v10, v8
-; ZVZIP-NEXT: vmv1r.v v8, v9
+; ZVZIP-NEXT: vmv.v.v v8, v9
; ZVZIP-NEXT: ret
%a = shufflevector <8 x i16> %x, <8 x i16> poison, <8 x i32> <i32 4, i32 poison, i32 5, i32 1, i32 6, i32 2, i32 7, i32 3>
ret <8 x i16> %a
@@ -917,9 +918,9 @@ define <8 x i32> @unary_interleave_v8i32(<8 x i32> %x) {
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 4, e32, m2, ta, ma
; ZVZIP-NEXT: vslidedown.vi v12, v8, 4
-; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVZIP-NEXT: vzip.vv v10, v8, v12
-; ZVZIP-NEXT: vmv2r.v v8, v10
+; ZVZIP-NEXT: vmv.v.v v8, v10
; ZVZIP-NEXT: ret
%a = shufflevector <8 x i32> %x, <8 x i32> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
ret <8 x i32> %a
@@ -969,7 +970,7 @@ define <16 x i16> @interleave_slp(<8 x i16> %v0, <8 x i16> %v1) {
;
; ZVZIP-LABEL: interleave_slp:
; ZVZIP: # %bb.0: # %entry
-; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVZIP-NEXT: vmv1r.v v10, v9
; ZVZIP-NEXT: vmv1r.v v11, v8
; ZVZIP-NEXT: vzip.vv v8, v11, v10
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
index bce071e988f0e..e3e58af53d235 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
@@ -85,11 +85,11 @@ define {<2 x i64>, <2 x i64>} @vector_deinterleave_v2i64_v4i64(<4 x i64> %vec) {
;
; ZVZIP-LABEL: vector_deinterleave_v2i64_v4i64:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; ZVZIP-NEXT: vunzipe.v v10, v8
; ZVZIP-NEXT: vunzipo.v v11, v8
-; ZVZIP-NEXT: vmv.v.v v8, v10
-; ZVZIP-NEXT: vmv.v.v v9, v11
+; ZVZIP-NEXT: vmv1r.v v8, v10
+; ZVZIP-NEXT: vmv1r.v v9, v11
; ZVZIP-NEXT: ret
%retval = call {<2 x i64>, <2 x i64>} @llvm.vector.deinterleave2.v4i64(<4 x i64> %vec)
ret {<2 x i64>, <2 x i64>} %retval
@@ -131,11 +131,11 @@ define {<4 x i64>, <4 x i64>} @vector_deinterleave_v4i64_v8i64(<8 x i64> %vec) {
;
; ZVZIP-LABEL: vector_deinterleave_v4i64_v8i64:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; ZVZIP-NEXT: vunzipe.v v12, v8
; ZVZIP-NEXT: vunzipo.v v14, v8
-; ZVZIP-NEXT: vmv.v.v v8, v12
-; ZVZIP-NEXT: vmv.v.v v10, v14
+; ZVZIP-NEXT: vmv2r.v v8, v12
+; ZVZIP-NEXT: vmv2r.v v10, v14
; ZVZIP-NEXT: ret
%retval = call {<4 x i64>, <4 x i64>} @llvm.vector.deinterleave2.v8i64(<8 x i64> %vec)
ret {<4 x i64>, <4 x i64>} %retval
@@ -169,11 +169,11 @@ define {<8 x i64>, <8 x i64>} @vector_deinterleave_v8i64_v16i64(<16 x i64> %vec)
;
; ZVZIP-LABEL: vector_deinterleave_v8i64_v16i64:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; ZVZIP-NEXT: vunzipe.v v16, v8
; ZVZIP-NEXT: vunzipo.v v20, v8
-; ZVZIP-NEXT: vmv.v.v v8, v16
-; ZVZIP-NEXT: vmv.v.v v12, v20
+; ZVZIP-NEXT: vmv4r.v v8, v16
+; ZVZIP-NEXT: vmv4r.v v12, v20
; ZVZIP-NEXT: ret
%retval = call {<8 x i64>, <8 x i64>} @llvm.vector.deinterleave2.v16i64(<16 x i64> %vec)
ret {<8 x i64>, <8 x i64>} %retval
@@ -811,11 +811,11 @@ define {<2 x double>, <2 x double>} @vector_deinterleave_v2f64_v4f64(<4 x double
;
; ZVZIP-LABEL: vector_deinterleave_v2f64_v4f64:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; ZVZIP-NEXT: vunzipe.v v10, v8
; ZVZIP-NEXT: vunzipo.v v11, v8
-; ZVZIP-NEXT: vmv.v.v v8, v10
-; ZVZIP-NEXT: vmv.v.v v9, v11
+; ZVZIP-NEXT: vmv1r.v v8, v10
+; ZVZIP-NEXT: vmv1r.v v9, v11
; ZVZIP-NEXT: ret
%retval = call {<2 x double>, <2 x double>} @llvm.vector.deinterleave2.v4f64(<4 x double> %vec)
ret {<2 x double>, <2 x double>} %retval
@@ -857,11 +857,11 @@ define {<4 x double>, <4 x double>} @vector_deinterleave_v4f64_v8f64(<8 x double
;
; ZVZIP-LABEL: vector_deinterleave_v4f64_v8f64:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; ZVZIP-NEXT: vunzipe.v v12, v8
; ZVZIP-NEXT: vunzipo.v v14, v8
-; ZVZIP-NEXT: vmv.v.v v8, v12
-; ZVZIP-NEXT: vmv.v.v v10, v14
+; ZVZIP-NEXT: vmv2r.v v8, v12
+; ZVZIP-NEXT: vmv2r.v v10, v14
; ZVZIP-NEXT: ret
%retval = call {<4 x double>, <4 x double>} @llvm.vector.deinterleave2.v8f64(<8 x double> %vec)
ret {<4 x double>, <4 x double>} %retval
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
index e58ee62d1a90f..80536a4709ea9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
@@ -34,8 +34,10 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>} @vector_deinterleave_nxv16i1_nxv
; ZVZIP-NEXT: vslidedown.vx v0, v0, a0
; ZVZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; ZVZIP-NEXT: vmerge.vim v10, v10, 1, v0
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; ZVZIP-NEXT: vunzipe.v v12, v8
; ZVZIP-NEXT: vunzipo.v v14, v8
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; ZVZIP-NEXT: vmsne.vi v0, v12, 0
; ZVZIP-NEXT: vmsne.vi v8, v14, 0
; ZVZIP-NEXT: ret
@@ -55,11 +57,11 @@ define {<vscale x 16 x i8>, <vscale x 16 x i8>} @vector_deinterleave_nxv16i8_nxv
;
; ZVZIP-LABEL: vector_deinterleave_nxv16i8_nxv32i8:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; ZVZIP-NEXT: vunzipe.v v12, v8
; ZVZIP-NEXT: vunzipo.v v14, v8
-; ZVZIP-NEXT: vmv.v.v v8, v12
-; ZVZIP-NEXT: vmv.v.v v10, v14
+; ZVZIP-NEXT: vmv2r.v v8, v12
+; ZVZIP-NEXT: vmv2r.v v10, v14
; ZVZIP-NEXT: ret
%retval = call {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> %vec)
ret {<vscale x 16 x i8>, <vscale x 16 x i8>} %retval
@@ -77,11 +79,11 @@ define {<vscale x 8 x i16>, <vscale x 8 x i16>} @vector_deinterleave_nxv8i16_nxv
;
; ZVZIP-LABEL: vector_deinterleave_nxv8i16_nxv16i16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVZIP-NEXT: vunzipe.v v12, v8
; ZVZIP-NEXT: vunzipo.v v14, v8
-; ZVZIP-NEXT: vmv.v.v v8, v12
-; ZVZIP-NEXT: vmv.v.v v10, v14
+; ZVZIP-NEXT: vmv2r.v v8, v12
+; ZVZIP-NEXT: vmv2r.v v10, v14
; ZVZIP-NEXT: ret
%retval = call {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.vector.deinterleave2.nxv16i16(<vscale x 16 x i16> %vec)
ret {<vscale x 8 x i16>, <vscale x 8 x i16>} %retval
@@ -100,11 +102,11 @@ define {<vscale x 4 x i32>, <vscale x 4 x i32>} @vector_deinterleave_nxv4i32_nxv
;
; ZVZIP-LABEL: vector_deinterleave_nxv4i32_nxvv8i32:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; ZVZIP-NEXT: vunzipe.v v12, v8
; ZVZIP-NEXT: vunzipo.v v14, v8
-; ZVZIP-NEXT: vmv.v.v v8, v12
-; ZVZIP-NEXT: vmv.v.v v10, v14
+; ZVZIP-NEXT: vmv2r.v v8, v12
+; ZVZIP-NEXT: vmv2r.v v10, v14
; ZVZIP-NEXT: ret
%retval = call {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.vector.deinterleave2.nxv8i32(<vscale x 8 x i32> %vec)
ret {<vscale x 4 x i32>, <vscale x 4 x i32>} %retval
@@ -161,11 +163,11 @@ define {<vscale x 2 x i64>, <vscale x 2 x i64>} @vector_deinterleave_nxv2i64_nxv
;
; ZVZIP-LABEL: vector_deinterleave_nxv2i64_nxv4i64:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; ZVZIP-NEXT: vunzipe.v v12, v8
; ZVZIP-NEXT: vunzipo.v v14, v8
-; ZVZIP-NEXT: vmv.v.v v8, v12
-; ZVZIP-NEXT: vmv.v.v v10, v14
+; ZVZIP-NEXT: vmv2r.v v8, v12
+; ZVZIP-NEXT: vmv2r.v v10, v14
; ZVZIP-NEXT: ret
%retval = call {<vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.vector.deinterleave2.nxv4i64(<vscale x 4 x i64> %vec)
ret {<vscale x 2 x i64>, <vscale x 2 x i64>} %retval
@@ -190,11 +192,11 @@ define {<vscale x 4 x i64>, <vscale x 4 x i64>} @vector_deinterleave_nxv4i64_nxv
;
; ZVZIP-LABEL: vector_deinterleave_nxv4i64_nxv8i64:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; ZVZIP-NEXT: vunzipe.v v16, v8
; ZVZIP-NEXT: vunzipo.v v20, v8
-; ZVZIP-NEXT: vmv.v.v v8, v16
-; ZVZIP-NEXT: vmv.v.v v12, v20
+; ZVZIP-NEXT: vmv4r.v v8, v16
+; ZVZIP-NEXT: vmv4r.v v12, v20
; ZVZIP-NEXT: ret
%retval = call {<vscale x 4 x i64>, <vscale x 4 x i64>} @llvm.vector.deinterleave2.nxv8i64(<vscale x 8 x i64> %vec)
ret {<vscale x 4 x i64>, <vscale x 4 x i64>} %retval
@@ -246,15 +248,11 @@ define {<vscale x 64 x i1>, <vscale x 64 x i1>} @vector_deinterleave_nxv64i1_nxv
; ZVZIP-NEXT: vmerge.vim v16, v24, 1, v0
; ZVZIP-NEXT: vmv1r.v v0, v8
; ZVZIP-NEXT: vmerge.vim v8, v24, 1, v0
-; ZVZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; ZVZIP-NEXT: vunzipe.v v24, v16
; ZVZIP-NEXT: vunzipe.v v28, v8
-; ZVZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; ZVZIP-NEXT: vmsne.vi v0, v24, 0
-; ZVZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; ZVZIP-NEXT: vunzipo.v v24, v16
; ZVZIP-NEXT: vunzipo.v v28, v8
-; ZVZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; ZVZIP-NEXT: vmsne.vi v8, v24, 0
; ZVZIP-NEXT: ret
%retval = call {<vscale x 64 x i1>, <vscale x 64 x i1>} @llvm.vector.deinterleave2.nxv128i1(<vscale x 128 x i1> %vec)
@@ -275,7 +273,7 @@ define {<vscale x 64 x i8>, <vscale x 64 x i8>} @vector_deinterleave_nxv64i8_nxv
;
; ZVZIP-LABEL: vector_deinterleave_nxv64i8_nxv128i8:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; ZVZIP-NEXT: vmv8r.v v24, v8
; ZVZIP-NEXT: vunzipe.v v8, v24
; ZVZIP-NEXT: vunzipe.v v12, v16
@@ -301,7 +299,7 @@ define {<vscale x 32 x i16>, <vscale x 32 x i16>} @vector_deinterleave_nxv32i16_
;
; ZVZIP-LABEL: vector_deinterleave_nxv32i16_nxv64i16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; ZVZIP-NEXT: vmv8r.v v24, v8
; ZVZIP-NEXT: vunzipe.v v8, v24
; ZVZIP-NEXT: vunzipe.v v12, v16
@@ -328,7 +326,7 @@ define {<vscale x 16 x i32>, <vscale x 16 x i32>} @vector_deinterleave_nxv16i32_
;
; ZVZIP-LABEL: vector_deinterleave_nxv16i32_nxvv32i32:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; ZVZIP-NEXT: vmv8r.v v24, v8
; ZVZIP-NEXT: vunzipe.v v8, v24
; ZVZIP-NEXT: vunzipe.v v12, v16
@@ -389,7 +387,7 @@ define {<vscale x 8 x i64>, <vscale x 8 x i64>} @vector_deinterleave_nxv8i64_nxv
;
; ZVZIP-LABEL: vector_deinterleave_nxv8i64_nxv16i64:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; ZVZIP-NEXT: vmv8r.v v24, v8
; ZVZIP-NEXT: vunzipe.v v8, v24
; ZVZIP-NEXT: vunzipe.v v12, v16
@@ -1657,10 +1655,10 @@ define {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @vector_deinterleave_nxv2b
;
; ZVZIP-LABEL: vector_deinterleave_nxv2bf16_nxv4bf16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVZIP-NEXT: vunzipe.v v10, v8
; ZVZIP-NEXT: vunzipo.v v9, v8
-; ZVZIP-NEXT: vmv1r.v v8, v10
+; ZVZIP-NEXT: vmv.v.v v8, v10
; ZVZIP-NEXT: ret
%retval = call {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @llvm.vector.deinterleave2.nxv4bf16(<vscale x 4 x bfloat> %vec)
ret {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>} %retval
@@ -1677,10 +1675,10 @@ define {<vscale x 2 x half>, <vscale x 2 x half>} @vector_deinterleave_nxv2f16_n
;
; ZVZIP-LABEL: vector_deinterleave_nxv2f16_nxv4f16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVZIP-NEXT: vunzipe.v v10, v8
; ZVZIP-NEXT: vunzipo.v v9, v8
-; ZVZIP-NEXT: vmv1r.v v8, v10
+; ZVZIP-NEXT: vmv.v.v v8, v10
; ZVZIP-NEXT: ret
%retval = call {<vscale x 2 x half>, <vscale x 2 x half>} @llvm.vector.deinterleave2.nxv4f16(<vscale x 4 x half> %vec)
ret {<vscale x 2 x half>, <vscale x 2 x half>} %retval
@@ -1698,11 +1696,11 @@ define {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>} @vector_deinterleave_nxv4b
;
; ZVZIP-LABEL: vector_deinterleave_nxv4bf16_nxv8bf16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; ZVZIP-NEXT: vunzipe.v v10, v8
; ZVZIP-NEXT: vunzipo.v v11, v8
-; ZVZIP-NEXT: vmv.v.v v8, v10
-; ZVZIP-NEXT: vmv.v.v v9, v11
+; ZVZIP-NEXT: vmv1r.v v8, v10
+; ZVZIP-NEXT: vmv1r.v v9, v11
; ZVZIP-NEXT: ret
%retval = call {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>} @llvm.vector.deinterleave2.nxv8bf16(<vscale x 8 x bfloat> %vec)
ret {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>} %retval
@@ -1720,11 +1718,11 @@ define {<vscale x 4 x half>, <vscale x 4 x half>} @vector_deinterleave_nxv4f16_n
;
; ZVZIP-LABEL: vector_deinterleave_nxv4f16_nxv8f16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; ZVZIP-NEXT: vunzipe.v v10, v8
; ZVZIP-NEXT: vunzipo.v v11, v8
-; ZVZIP-NEXT: vmv.v.v v8, v10
-; ZVZIP-NEXT: vmv.v.v v9, v11
+; ZVZIP-NEXT: vmv1r.v v8, v10
+; ZVZIP-NEXT: vmv1r.v v9, v11
; ZVZIP-NEXT: ret
%retval = call {<vscale x 4 x half>, <vscale x 4 x half>} @llvm.vector.deinterleave2.nxv8f16(<vscale x 8 x half> %vec)
ret {<vscale x 4 x half>, <vscale x 4 x half>} %retval
@@ -1743,11 +1741,11 @@ define {<vscale x 2 x float>, <vscale x 2 x float>} @vector_deinterleave_nxv2f32
;
; ZVZIP-LABEL: vector_deinterleave_nxv2f32_nxv4f32:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; ZVZIP-NEXT: vunzipe.v v10, v8
; ZVZIP-NEXT: vunzipo.v v11, v8
-; ZVZIP-NEXT: vmv.v.v v8, v10
-; ZVZIP-NEXT: vmv.v.v v9, v11
+; ZVZIP-NEXT: vmv1r.v v8, v10
+; ZVZIP-NEXT: vmv1r.v v9, v11
; ZVZIP-NEXT: ret
%retval = call {<vscale x 2 x float>, <vscale x 2 x float>} @llvm.vector.deinterleave2.nxv4f32(<vscale x 4 x float> %vec)
ret {<vscale x 2 x float>, <vscale x 2 x float>} %retval
@@ -1765,11 +1763,11 @@ define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @vector_deinterleave_nxv8b
;
; ZVZIP-LABEL: vector_deinterleave_nxv8bf16_nxv16bf16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVZIP-NEXT: vunzipe.v v12, v8
; ZVZIP-NEXT: vunzipo.v v14, v8
-; ZVZIP-NEXT: vmv.v.v v8, v12
-; ZVZIP-NEXT: vmv.v.v v10, v14
+; ZVZIP-NEXT: vmv2r.v v8, v12
+; ZVZIP-NEXT: vmv2r.v v10, v14
; ZVZIP-NEXT: ret
%retval = call {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @llvm.vector.deinterleave2.nxv16bf16(<vscale x 16 x bfloat> %vec)
ret {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} %retval
@@ -1787,11 +1785,11 @@ define {<vscale x 8 x half>, <vscale x 8 x half>} @vector_deinterleave_nxv8f16_n
;
; ZVZIP-LABEL: vector_deinterleave_nxv8f16_nxv16f16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVZIP-NEXT: vunzipe.v v12, v8
; ZVZIP-NEXT: vunzipo.v v14, v8
-; ZVZIP-NEXT: vmv.v.v v8, v12
-; ZVZIP-NEXT: vmv.v.v v10, v14
+; ZVZIP-NEXT: vmv2r.v v8, v12
+; ZVZIP-NEXT: vmv2r.v v10, v14
; ZVZIP-NEXT: ret
%retval = call {<vscale x 8 x half>, <vscale x 8 x half>} @llvm.vector.deinterleave2.nxv16f16(<vscale x 16 x half> %vec)
ret {<vscale x 8 x half>, <vscale x 8 x half>} %retval
@@ -1810,11 +1808,11 @@ define {<vscale x 4 x float>, <vscale x 4 x float>} @vector_deinterleave_nxv4f32
;
; ZVZIP-LABEL: vector_deinterleave_nxv4f32_nxv8f32:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; ZVZIP-NEXT: vunzipe.v v12, v8
; ZVZIP-NEXT: vunzipo.v v14, v8
-; ZVZIP-NEXT: vmv.v.v v8, v12
-; ZVZIP-NEXT: vmv.v.v v10, v14
+; ZVZIP-NEXT: vmv2r.v v8, v12
+; ZVZIP-NEXT: vmv2r.v v10, v14
; ZVZIP-NEXT: ret
%retval = call {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.vector.deinterleave2.nxv8f32(<vscale x 8 x float> %vec)
ret {<vscale x 4 x float>, <vscale x 4 x float>} %retval
@@ -1839,11 +1837,11 @@ define {<vscale x 2 x double>, <vscale x 2 x double>} @vector_deinterleave_nxv2f
;
; ZVZIP-LABEL: vector_deinterleave_nxv2f64_nxv4f64:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; ZVZIP-NEXT: vunzipe.v v12, v8
; ZVZIP-NEXT: vunzipo.v v14, v8
-; ZVZIP-NEXT: vmv.v.v v8, v12
-; ZVZIP-NEXT: vmv.v.v v10, v14
+; ZVZIP-NEXT: vmv2r.v v8, v12
+; ZVZIP-NEXT: vmv2r.v v10, v14
; ZVZIP-NEXT: ret
%retval = call {<vscale x 2 x double>, <vscale x 2 x double>} @llvm.vector.deinterleave2.nxv4f64(<vscale x 4 x double> %vec)
ret {<vscale x 2 x double>, <vscale x 2 x double>} %retval
@@ -1864,7 +1862,7 @@ define {<vscale x 32 x bfloat>, <vscale x 32 x bfloat>} @vector_deinterleave_nxv
;
; ZVZIP-LABEL: vector_deinterleave_nxv32bf16_nxv64bf16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; ZVZIP-NEXT: vmv8r.v v24, v8
; ZVZIP-NEXT: vunzipe.v v8, v24
; ZVZIP-NEXT: vunzipe.v v12, v16
@@ -1890,7 +1888,7 @@ define {<vscale x 32 x half>, <vscale x 32 x half>} @vector_deinterleave_nxv32f1
;
; ZVZIP-LABEL: vector_deinterleave_nxv32f16_nxv64f16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; ZVZIP-NEXT: vmv8r.v v24, v8
; ZVZIP-NEXT: vunzipe.v v8, v24
; ZVZIP-NEXT: vunzipe.v v12, v16
@@ -1917,7 +1915,7 @@ define {<vscale x 16 x float>, <vscale x 16 x float>} @vector_deinterleave_nxv16
;
; ZVZIP-LABEL: vector_deinterleave_nxv16f32_nxv32f32:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; ZVZIP-NEXT: vmv8r.v v24, v8
; ZVZIP-NEXT: vunzipe.v v8, v24
; ZVZIP-NEXT: vunzipe.v v12, v16
@@ -1978,7 +1976,7 @@ define {<vscale x 8 x double>, <vscale x 8 x double>} @vector_deinterleave_nxv8f
;
; ZVZIP-LABEL: vector_deinterleave_nxv8f64_nxv16f64:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; ZVZIP-NEXT: vmv8r.v v24, v8
; ZVZIP-NEXT: vunzipe.v v8, v24
; ZVZIP-NEXT: vunzipe.v v12, v16
@@ -3766,9 +3764,9 @@ define <vscale x 16 x i8> @vector_deinterleave_nxv16i8_nxv32i8_oneactive(<vscale
;
; ZVZIP-LABEL: vector_deinterleave_nxv16i8_nxv32i8_oneactive:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; ZVZIP-NEXT: vunzipe.v v12, v8
-; ZVZIP-NEXT: vmv.v.v v8, v12
+; ZVZIP-NEXT: vmv2r.v v8, v12
; ZVZIP-NEXT: ret
%retval = call {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> %vec)
%ext = extractvalue {<vscale x 16 x i8>, <vscale x 16 x i8>} %retval, 0
@@ -3836,8 +3834,9 @@ define { <8 x float>, <8 x float> } @interleave_deinterleave2(<8 x float> %a, <8
; ZVZIP-LABEL: interleave_deinterleave2:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: li a0, 32
-; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVZIP-NEXT: vzip.vv v12, v8, v10
+; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVZIP-NEXT: vnsrl.wx v10, v12, a0
; ZVZIP-NEXT: vnsrl.wi v8, v12, 0
; ZVZIP-NEXT: ret
@@ -3865,6 +3864,7 @@ define <16 x float> @deinterleave_interleave2(<16 x float> %arg) {
; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVZIP-NEXT: vnsrl.wx v12, v8, a0
; ZVZIP-NEXT: vnsrl.wi v14, v8, 0
+; ZVZIP-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZVZIP-NEXT: vzip.vv v8, v14, v12
; ZVZIP-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
index a56bb463dd2c4..da06716f6c2cc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
@@ -54,9 +54,8 @@ define <32 x i1> @vector_interleave_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b) {
; ZVZIP-NEXT: vmerge.vim v8, v8, 1, v0
; ZVZIP-NEXT: vsetivli zero, 16, e8, m2, ta, ma
; ZVZIP-NEXT: vslidedown.vi v10, v8, 16
-; ZVZIP-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZVZIP-NEXT: vzip.vv v12, v8, v10
; ZVZIP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; ZVZIP-NEXT: vzip.vv v12, v8, v10
; ZVZIP-NEXT: vmsne.vi v0, v12, 0
; ZVZIP-NEXT: ret
%res = call <32 x i1> @llvm.vector.interleave2.v32i1(<16 x i1> %a, <16 x i1> %b)
@@ -85,7 +84,7 @@ define <16 x i16> @vector_interleave_v16i16_v8i16(<8 x i16> %a, <8 x i16> %b) {
;
; ZVZIP-LABEL: vector_interleave_v16i16_v8i16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVZIP-NEXT: vmv1r.v v10, v9
; ZVZIP-NEXT: vmv1r.v v11, v8
; ZVZIP-NEXT: vzip.vv v8, v11, v10
@@ -117,7 +116,7 @@ define <8 x i32> @vector_interleave_v8i32_v4i32(<4 x i32> %a, <4 x i32> %b) {
;
; ZVZIP-LABEL: vector_interleave_v8i32_v4i32:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVZIP-NEXT: vmv1r.v v10, v9
; ZVZIP-NEXT: vmv1r.v v11, v8
; ZVZIP-NEXT: vzip.vv v8, v11, v10
@@ -159,7 +158,7 @@ define <4 x i64> @vector_interleave_v4i64_v2i64(<2 x i64> %a, <2 x i64> %b) {
;
; ZVZIP-LABEL: vector_interleave_v4i64_v2i64:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; ZVZIP-NEXT: vmv1r.v v10, v9
; ZVZIP-NEXT: vmv1r.v v11, v8
; ZVZIP-NEXT: vzip.vv v8, v11, v10
@@ -868,7 +867,7 @@ define <4 x half> @vector_interleave_v4f16_v2f16(<2 x half> %a, <2 x half> %b) {
;
; ZVZIP-LABEL: vector_interleave_v4f16_v2f16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVZIP-NEXT: vzip.vv v10, v8, v9
; ZVZIP-NEXT: vmv1r.v v8, v10
; ZVZIP-NEXT: ret
@@ -896,7 +895,7 @@ define <4 x bfloat> @vector_interleave_v4bf16_v2bf16(<2 x bfloat> %a, <2 x bfloa
;
; ZVZIP-LABEL: vector_interleave_v4bf16_v2bf16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVZIP-NEXT: vzip.vv v10, v8, v9
; ZVZIP-NEXT: vmv1r.v v8, v10
; ZVZIP-NEXT: ret
@@ -924,9 +923,9 @@ define <8 x half> @vector_interleave_v8f16_v4f16(<4 x half> %a, <4 x half> %b) {
;
; ZVZIP-LABEL: vector_interleave_v8f16_v4f16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVZIP-NEXT: vzip.vv v10, v8, v9
-; ZVZIP-NEXT: vmv1r.v v8, v10
+; ZVZIP-NEXT: vmv.v.v v8, v10
; ZVZIP-NEXT: ret
%res = call <8 x half> @llvm.vector.interleave2.v8f16(<4 x half> %a, <4 x half> %b)
ret <8 x half> %res
@@ -952,9 +951,9 @@ define <8 x bfloat> @vector_interleave_v8bf16_v4bf16(<4 x bfloat> %a, <4 x bfloa
;
; ZVZIP-LABEL: vector_interleave_v8bf16_v4bf16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVZIP-NEXT: vzip.vv v10, v8, v9
-; ZVZIP-NEXT: vmv1r.v v8, v10
+; ZVZIP-NEXT: vmv.v.v v8, v10
; ZVZIP-NEXT: ret
%res = call <8 x bfloat> @llvm.vector.interleave2.v8bf16(<4 x bfloat> %a, <4 x bfloat> %b)
ret <8 x bfloat> %res
@@ -981,9 +980,9 @@ define <4 x float> @vector_interleave_v4f32_v2f32(<2 x float> %a, <2 x float> %b
;
; ZVZIP-LABEL: vector_interleave_v4f32_v2f32:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVZIP-NEXT: vzip.vv v10, v8, v9
-; ZVZIP-NEXT: vmv1r.v v8, v10
+; ZVZIP-NEXT: vmv.v.v v8, v10
; ZVZIP-NEXT: ret
%res = call <4 x float> @llvm.vector.interleave2.v4f32(<2 x float> %a, <2 x float> %b)
ret <4 x float> %res
@@ -1011,7 +1010,7 @@ define <16 x half> @vector_interleave_v16f16_v8f16(<8 x half> %a, <8 x half> %b)
;
; ZVZIP-LABEL: vector_interleave_v16f16_v8f16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVZIP-NEXT: vmv1r.v v10, v9
; ZVZIP-NEXT: vmv1r.v v11, v8
; ZVZIP-NEXT: vzip.vv v8, v11, v10
@@ -1042,7 +1041,7 @@ define <16 x bfloat> @vector_interleave_v16bf16_v8bf16(<8 x bfloat> %a, <8 x bfl
;
; ZVZIP-LABEL: vector_interleave_v16bf16_v8bf16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVZIP-NEXT: vmv1r.v v10, v9
; ZVZIP-NEXT: vmv1r.v v11, v8
; ZVZIP-NEXT: vzip.vv v8, v11, v10
@@ -1074,7 +1073,7 @@ define <8 x float> @vector_interleave_v8f32_v4f32(<4 x float> %a, <4 x float> %b
;
; ZVZIP-LABEL: vector_interleave_v8f32_v4f32:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVZIP-NEXT: vmv1r.v v10, v9
; ZVZIP-NEXT: vmv1r.v v11, v8
; ZVZIP-NEXT: vzip.vv v8, v11, v10
@@ -1116,7 +1115,7 @@ define <4 x double> @vector_interleave_v4f64_v2f64(<2 x double> %a, <2 x double>
;
; ZVZIP-LABEL: vector_interleave_v4f64_v2f64:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; ZVZIP-NEXT: vmv1r.v v10, v9
; ZVZIP-NEXT: vmv1r.v v11, v8
; ZVZIP-NEXT: vzip.vv v8, v11, v10
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
index b4053654e42f2..3114ee55c5070 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
@@ -58,7 +58,9 @@ define <vscale x 32 x i1> @vector_interleave_nxv32i1_nxv16i1(<vscale x 16 x i1>
; ZVZIP-NEXT: vmerge.vim v12, v10, 1, v0
; ZVZIP-NEXT: vmv1r.v v0, v9
; ZVZIP-NEXT: vmerge.vim v14, v10, 1, v0
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; ZVZIP-NEXT: vzip.vv v8, v14, v12
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; ZVZIP-NEXT: vmsne.vi v12, v10, 0
; ZVZIP-NEXT: vmsne.vi v0, v8, 0
; ZVZIP-NEXT: csrr a0, vlenb
@@ -92,7 +94,7 @@ define <vscale x 32 x i8> @vector_interleave_nxv32i8_nxv16i8(<vscale x 16 x i8>
;
; ZVZIP-LABEL: vector_interleave_nxv32i8_nxv16i8:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; ZVZIP-NEXT: vmv2r.v v12, v10
; ZVZIP-NEXT: vmv2r.v v14, v8
; ZVZIP-NEXT: vzip.vv v8, v14, v12
@@ -123,7 +125,7 @@ define <vscale x 16 x i16> @vector_interleave_nxv16i16_nxv8i16(<vscale x 8 x i16
;
; ZVZIP-LABEL: vector_interleave_nxv16i16_nxv8i16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVZIP-NEXT: vmv2r.v v12, v10
; ZVZIP-NEXT: vmv2r.v v14, v8
; ZVZIP-NEXT: vzip.vv v8, v14, v12
@@ -155,7 +157,7 @@ define <vscale x 8 x i32> @vector_interleave_nxv8i32_nxv4i32(<vscale x 4 x i32>
;
; ZVZIP-LABEL: vector_interleave_nxv8i32_nxv4i32:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; ZVZIP-NEXT: vmv2r.v v12, v10
; ZVZIP-NEXT: vmv2r.v v14, v8
; ZVZIP-NEXT: vzip.vv v8, v14, v12
@@ -197,7 +199,7 @@ define <vscale x 4 x i64> @vector_interleave_nxv4i64_nxv2i64(<vscale x 2 x i64>
;
; ZVZIP-LABEL: vector_interleave_nxv4i64_nxv2i64:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; ZVZIP-NEXT: vmv2r.v v12, v10
; ZVZIP-NEXT: vmv2r.v v14, v8
; ZVZIP-NEXT: vzip.vv v8, v14, v12
@@ -258,13 +260,9 @@ define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv64i1(<vscale x 64 x i1
; ZVZIP-NEXT: vmerge.vim v16, v24, 1, v0
; ZVZIP-NEXT: vmv1r.v v0, v9
; ZVZIP-NEXT: vmerge.vim v8, v24, 1, v0
-; ZVZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; ZVZIP-NEXT: vzip.vv v24, v8, v16
-; ZVZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; ZVZIP-NEXT: vmsne.vi v0, v24, 0
-; ZVZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; ZVZIP-NEXT: vzip.vv v24, v12, v20
-; ZVZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; ZVZIP-NEXT: vmsne.vi v8, v24, 0
; ZVZIP-NEXT: ret
%res = call <vscale x 128 x i1> @llvm.vector.interleave2.nxv128i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b)
@@ -297,11 +295,11 @@ define <vscale x 128 x i8> @vector_interleave_nxv128i8_nxv64i8(<vscale x 64 x i8
;
; ZVZIP-LABEL: vector_interleave_nxv128i8_nxv64i8:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; ZVZIP-NEXT: vzip.vv v24, v8, v16
; ZVZIP-NEXT: vzip.vv v0, v12, v20
-; ZVZIP-NEXT: vmv8r.v v8, v24
-; ZVZIP-NEXT: vmv8r.v v16, v0
+; ZVZIP-NEXT: vmv.v.v v8, v24
+; ZVZIP-NEXT: vmv.v.v v16, v0
; ZVZIP-NEXT: ret
%res = call <vscale x 128 x i8> @llvm.vector.interleave2.nxv128i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b)
ret <vscale x 128 x i8> %res
@@ -333,11 +331,11 @@ define <vscale x 64 x i16> @vector_interleave_nxv64i16_nxv32i16(<vscale x 32 x i
;
; ZVZIP-LABEL: vector_interleave_nxv64i16_nxv32i16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; ZVZIP-NEXT: vzip.vv v24, v8, v16
; ZVZIP-NEXT: vzip.vv v0, v12, v20
-; ZVZIP-NEXT: vmv8r.v v8, v24
-; ZVZIP-NEXT: vmv8r.v v16, v0
+; ZVZIP-NEXT: vmv.v.v v8, v24
+; ZVZIP-NEXT: vmv.v.v v16, v0
; ZVZIP-NEXT: ret
%res = call <vscale x 64 x i16> @llvm.vector.interleave2.nxv64i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b)
ret <vscale x 64 x i16> %res
@@ -370,11 +368,11 @@ define <vscale x 32 x i32> @vector_interleave_nxv32i32_nxv16i32(<vscale x 16 x i
;
; ZVZIP-LABEL: vector_interleave_nxv32i32_nxv16i32:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; ZVZIP-NEXT: vzip.vv v24, v8, v16
; ZVZIP-NEXT: vzip.vv v0, v12, v20
-; ZVZIP-NEXT: vmv8r.v v8, v24
-; ZVZIP-NEXT: vmv8r.v v16, v0
+; ZVZIP-NEXT: vmv.v.v v8, v24
+; ZVZIP-NEXT: vmv.v.v v16, v0
; ZVZIP-NEXT: ret
%res = call <vscale x 32 x i32> @llvm.vector.interleave2.nxv32i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b)
ret <vscale x 32 x i32> %res
@@ -425,11 +423,11 @@ define <vscale x 16 x i64> @vector_interleave_nxv16i64_nxv8i64(<vscale x 8 x i64
;
; ZVZIP-LABEL: vector_interleave_nxv16i64_nxv8i64:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; ZVZIP-NEXT: vzip.vv v24, v8, v16
; ZVZIP-NEXT: vzip.vv v0, v12, v20
-; ZVZIP-NEXT: vmv8r.v v8, v24
-; ZVZIP-NEXT: vmv8r.v v16, v0
+; ZVZIP-NEXT: vmv.v.v v8, v24
+; ZVZIP-NEXT: vmv.v.v v16, v0
; ZVZIP-NEXT: ret
%res = call <vscale x 16 x i64> @llvm.vector.interleave2.nxv16i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b)
ret <vscale x 16 x i64> %res
@@ -6235,11 +6233,10 @@ define <vscale x 4 x bfloat> @vector_interleave_nxv4bf16_nxv2bf16(<vscale x 2 x
;
; ZVZIP-LABEL: vector_interleave_nxv4bf16_nxv2bf16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVZIP-NEXT: vzip.vv v10, v8, v9
; ZVZIP-NEXT: csrr a0, vlenb
; ZVZIP-NEXT: srli a0, a0, 2
-; ZVZIP-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVZIP-NEXT: vslidedown.vx v8, v10, a0
; ZVZIP-NEXT: vslideup.vx v10, v8, a0
; ZVZIP-NEXT: vmv.v.v v8, v10
@@ -6270,7 +6267,7 @@ define <vscale x 8 x bfloat> @vector_interleave_nxv8bf16_nxv4bf16(<vscale x 4 x
;
; ZVZIP-LABEL: vector_interleave_nxv8bf16_nxv4bf16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; ZVZIP-NEXT: vmv1r.v v10, v9
; ZVZIP-NEXT: vmv1r.v v11, v8
; ZVZIP-NEXT: vzip.vv v8, v11, v10
@@ -6309,11 +6306,10 @@ define <vscale x 4 x half> @vector_interleave_nxv4f16_nxv2f16(<vscale x 2 x half
;
; ZVZIP-LABEL: vector_interleave_nxv4f16_nxv2f16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVZIP-NEXT: vzip.vv v10, v8, v9
; ZVZIP-NEXT: csrr a0, vlenb
; ZVZIP-NEXT: srli a0, a0, 2
-; ZVZIP-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVZIP-NEXT: vslidedown.vx v8, v10, a0
; ZVZIP-NEXT: vslideup.vx v10, v8, a0
; ZVZIP-NEXT: vmv.v.v v8, v10
@@ -6344,7 +6340,7 @@ define <vscale x 8 x half> @vector_interleave_nxv8f16_nxv4f16(<vscale x 4 x half
;
; ZVZIP-LABEL: vector_interleave_nxv8f16_nxv4f16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; ZVZIP-NEXT: vmv1r.v v10, v9
; ZVZIP-NEXT: vmv1r.v v11, v8
; ZVZIP-NEXT: vzip.vv v8, v11, v10
@@ -6376,7 +6372,7 @@ define <vscale x 4 x float> @vector_interleave_nxv4f32_nxv2f32(<vscale x 2 x flo
;
; ZVZIP-LABEL: vector_interleave_nxv4f32_nxv2f32:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; ZVZIP-NEXT: vmv1r.v v10, v9
; ZVZIP-NEXT: vmv1r.v v11, v8
; ZVZIP-NEXT: vzip.vv v8, v11, v10
@@ -6407,7 +6403,7 @@ define <vscale x 16 x bfloat> @vector_interleave_nxv16bf16_nxv8bf16(<vscale x 8
;
; ZVZIP-LABEL: vector_interleave_nxv16bf16_nxv8bf16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVZIP-NEXT: vmv2r.v v12, v10
; ZVZIP-NEXT: vmv2r.v v14, v8
; ZVZIP-NEXT: vzip.vv v8, v14, v12
@@ -6438,7 +6434,7 @@ define <vscale x 16 x half> @vector_interleave_nxv16f16_nxv8f16(<vscale x 8 x ha
;
; ZVZIP-LABEL: vector_interleave_nxv16f16_nxv8f16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVZIP-NEXT: vmv2r.v v12, v10
; ZVZIP-NEXT: vmv2r.v v14, v8
; ZVZIP-NEXT: vzip.vv v8, v14, v12
@@ -6470,7 +6466,7 @@ define <vscale x 8 x float> @vector_interleave_nxv8f32_nxv4f32(<vscale x 4 x flo
;
; ZVZIP-LABEL: vector_interleave_nxv8f32_nxv4f32:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; ZVZIP-NEXT: vmv2r.v v12, v10
; ZVZIP-NEXT: vmv2r.v v14, v8
; ZVZIP-NEXT: vzip.vv v8, v14, v12
@@ -6512,7 +6508,7 @@ define <vscale x 4 x double> @vector_interleave_nxv4f64_nxv2f64(<vscale x 2 x do
;
; ZVZIP-LABEL: vector_interleave_nxv4f64_nxv2f64:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; ZVZIP-NEXT: vmv2r.v v12, v10
; ZVZIP-NEXT: vmv2r.v v14, v8
; ZVZIP-NEXT: vzip.vv v8, v14, v12
@@ -6549,11 +6545,11 @@ define <vscale x 64 x bfloat> @vector_interleave_nxv64bf16_nxv32bf16(<vscale x 3
;
; ZVZIP-LABEL: vector_interleave_nxv64bf16_nxv32bf16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; ZVZIP-NEXT: vzip.vv v24, v8, v16
; ZVZIP-NEXT: vzip.vv v0, v12, v20
-; ZVZIP-NEXT: vmv8r.v v8, v24
-; ZVZIP-NEXT: vmv8r.v v16, v0
+; ZVZIP-NEXT: vmv.v.v v8, v24
+; ZVZIP-NEXT: vmv.v.v v16, v0
; ZVZIP-NEXT: ret
%res = call <vscale x 64 x bfloat> @llvm.vector.interleave2.nxv64bf16(<vscale x 32 x bfloat> %a, <vscale x 32 x bfloat> %b)
ret <vscale x 64 x bfloat> %res
@@ -6585,11 +6581,11 @@ define <vscale x 64 x half> @vector_interleave_nxv64f16_nxv32f16(<vscale x 32 x
;
; ZVZIP-LABEL: vector_interleave_nxv64f16_nxv32f16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; ZVZIP-NEXT: vzip.vv v24, v8, v16
; ZVZIP-NEXT: vzip.vv v0, v12, v20
-; ZVZIP-NEXT: vmv8r.v v8, v24
-; ZVZIP-NEXT: vmv8r.v v16, v0
+; ZVZIP-NEXT: vmv.v.v v8, v24
+; ZVZIP-NEXT: vmv.v.v v16, v0
; ZVZIP-NEXT: ret
%res = call <vscale x 64 x half> @llvm.vector.interleave2.nxv64f16(<vscale x 32 x half> %a, <vscale x 32 x half> %b)
ret <vscale x 64 x half> %res
@@ -6622,11 +6618,11 @@ define <vscale x 32 x float> @vector_interleave_nxv32f32_nxv16f32(<vscale x 16 x
;
; ZVZIP-LABEL: vector_interleave_nxv32f32_nxv16f32:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; ZVZIP-NEXT: vzip.vv v24, v8, v16
; ZVZIP-NEXT: vzip.vv v0, v12, v20
-; ZVZIP-NEXT: vmv8r.v v8, v24
-; ZVZIP-NEXT: vmv8r.v v16, v0
+; ZVZIP-NEXT: vmv.v.v v8, v24
+; ZVZIP-NEXT: vmv.v.v v16, v0
; ZVZIP-NEXT: ret
%res = call <vscale x 32 x float> @llvm.vector.interleave2.nxv32f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b)
ret <vscale x 32 x float> %res
@@ -6677,11 +6673,11 @@ define <vscale x 16 x double> @vector_interleave_nxv16f64_nxv8f64(<vscale x 8 x
;
; ZVZIP-LABEL: vector_interleave_nxv16f64_nxv8f64:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; ZVZIP-NEXT: vzip.vv v24, v8, v16
; ZVZIP-NEXT: vzip.vv v0, v12, v20
-; ZVZIP-NEXT: vmv8r.v v8, v24
-; ZVZIP-NEXT: vmv8r.v v16, v0
+; ZVZIP-NEXT: vmv.v.v v8, v24
+; ZVZIP-NEXT: vmv.v.v v16, v0
; ZVZIP-NEXT: ret
%res = call <vscale x 16 x double> @llvm.vector.interleave2.nxv16f64(<vscale x 8 x double> %a, <vscale x 8 x double> %b)
ret <vscale x 16 x double> %res
@@ -14872,10 +14868,10 @@ define <vscale x 4 x i16> @interleave2_diff_const_splat_nxv4i16() {
; ZVZIP-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; ZVZIP-NEXT: vmv.v.i v9, 4
; ZVZIP-NEXT: vmv.v.i v10, 3
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVZIP-NEXT: vzip.vv v8, v10, v9
; ZVZIP-NEXT: csrr a0, vlenb
; ZVZIP-NEXT: srli a0, a0, 2
-; ZVZIP-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVZIP-NEXT: vslidedown.vx v9, v8, a0
; ZVZIP-NEXT: vslideup.vx v8, v9, a0
; ZVZIP-NEXT: ret
@@ -14934,10 +14930,10 @@ define <vscale x 4 x i16> @interleave2_diff_nonconst_splat_nxv4i16(i16 %a, i16 %
; ZVZIP-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
; ZVZIP-NEXT: vmv.v.x v9, a0
; ZVZIP-NEXT: vmv.v.x v10, a1
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVZIP-NEXT: vzip.vv v8, v9, v10
; ZVZIP-NEXT: csrr a0, vlenb
; ZVZIP-NEXT: srli a0, a0, 2
-; ZVZIP-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZVZIP-NEXT: vslidedown.vx v9, v8, a0
; ZVZIP-NEXT: vslideup.vx v8, v9, a0
; ZVZIP-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/vunzipe.ll b/llvm/test/CodeGen/RISCV/rvv/vunzipe.ll
index 69083ea978de5..3741681d69623 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vunzipe.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vunzipe.ll
@@ -7,7 +7,7 @@
define <vscale x 1 x i8> @test_vunzipe_i8mf8(<vscale x 1 x i8> %passthru, <vscale x 2 x i8> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_i8mf8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, ma
; CHECK-NEXT: vunzipe.v v8, v9
; CHECK-NEXT: ret
%a = call <vscale x 1 x i8> @llvm.riscv.vunzipe(
@@ -17,24 +17,11 @@ define <vscale x 1 x i8> @test_vunzipe_i8mf8(<vscale x 1 x i8> %passthru, <vscal
ret <vscale x 1 x i8> %a
}
-define <vscale x 1 x i8> @test_vunzipe_mask_i8mf8(<vscale x 1 x i8> %passthru, <vscale x 2 x i8> %arg1, <vscale x 1 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_i8mf8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v9, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 1 x i8> @llvm.riscv.vunzipe.mask(
- <vscale x 1 x i8> %passthru,
- <vscale x 2 x i8> %arg1,
- <vscale x 1 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 1 x i8> %a
-}
define <vscale x 2 x i8> @test_vunzipe_i8mf4(<vscale x 2 x i8> %passthru, <vscale x 4 x i8> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_i8mf4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma
; CHECK-NEXT: vunzipe.v v8, v9
; CHECK-NEXT: ret
%a = call <vscale x 2 x i8> @llvm.riscv.vunzipe(
@@ -44,24 +31,11 @@ define <vscale x 2 x i8> @test_vunzipe_i8mf4(<vscale x 2 x i8> %passthru, <vscal
ret <vscale x 2 x i8> %a
}
-define <vscale x 2 x i8> @test_vunzipe_mask_i8mf4(<vscale x 2 x i8> %passthru, <vscale x 4 x i8> %arg1, <vscale x 2 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_i8mf4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v9, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 2 x i8> @llvm.riscv.vunzipe.mask(
- <vscale x 2 x i8> %passthru,
- <vscale x 4 x i8> %arg1,
- <vscale x 2 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 2 x i8> %a
-}
define <vscale x 4 x i8> @test_vunzipe_i8mf2(<vscale x 4 x i8> %passthru, <vscale x 8 x i8> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_i8mf2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
; CHECK-NEXT: vunzipe.v v8, v9
; CHECK-NEXT: ret
%a = call <vscale x 4 x i8> @llvm.riscv.vunzipe(
@@ -71,24 +45,11 @@ define <vscale x 4 x i8> @test_vunzipe_i8mf2(<vscale x 4 x i8> %passthru, <vscal
ret <vscale x 4 x i8> %a
}
-define <vscale x 4 x i8> @test_vunzipe_mask_i8mf2(<vscale x 4 x i8> %passthru, <vscale x 8 x i8> %arg1, <vscale x 4 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_i8mf2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v9, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 4 x i8> @llvm.riscv.vunzipe.mask(
- <vscale x 4 x i8> %passthru,
- <vscale x 8 x i8> %arg1,
- <vscale x 4 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 4 x i8> %a
-}
define <vscale x 8 x i8> @test_vunzipe_i8m1(<vscale x 8 x i8> %passthru, <vscale x 16 x i8> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_i8m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, ma
; CHECK-NEXT: vunzipe.v v8, v10
; CHECK-NEXT: ret
%a = call <vscale x 8 x i8> @llvm.riscv.vunzipe(
@@ -98,24 +59,11 @@ define <vscale x 8 x i8> @test_vunzipe_i8m1(<vscale x 8 x i8> %passthru, <vscale
ret <vscale x 8 x i8> %a
}
-define <vscale x 8 x i8> @test_vunzipe_mask_i8m1(<vscale x 8 x i8> %passthru, <vscale x 16 x i8> %arg1, <vscale x 8 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_i8m1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v10, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 8 x i8> @llvm.riscv.vunzipe.mask(
- <vscale x 8 x i8> %passthru,
- <vscale x 16 x i8> %arg1,
- <vscale x 8 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 8 x i8> %a
-}
define <vscale x 16 x i8> @test_vunzipe_i8m2(<vscale x 16 x i8> %passthru, <vscale x 32 x i8> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_i8m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, ma
; CHECK-NEXT: vunzipe.v v8, v12
; CHECK-NEXT: ret
%a = call <vscale x 16 x i8> @llvm.riscv.vunzipe(
@@ -125,24 +73,11 @@ define <vscale x 16 x i8> @test_vunzipe_i8m2(<vscale x 16 x i8> %passthru, <vsca
ret <vscale x 16 x i8> %a
}
-define <vscale x 16 x i8> @test_vunzipe_mask_i8m2(<vscale x 16 x i8> %passthru, <vscale x 32 x i8> %arg1, <vscale x 16 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_i8m2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v12, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 16 x i8> @llvm.riscv.vunzipe.mask(
- <vscale x 16 x i8> %passthru,
- <vscale x 32 x i8> %arg1,
- <vscale x 16 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 16 x i8> %a
-}
define <vscale x 32 x i8> @test_vunzipe_i8m4(<vscale x 32 x i8> %passthru, <vscale x 64 x i8> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_i8m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, ma
; CHECK-NEXT: vunzipe.v v8, v16
; CHECK-NEXT: ret
%a = call <vscale x 32 x i8> @llvm.riscv.vunzipe(
@@ -152,24 +87,11 @@ define <vscale x 32 x i8> @test_vunzipe_i8m4(<vscale x 32 x i8> %passthru, <vsca
ret <vscale x 32 x i8> %a
}
-define <vscale x 32 x i8> @test_vunzipe_mask_i8m4(<vscale x 32 x i8> %passthru, <vscale x 64 x i8> %arg1, <vscale x 32 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_i8m4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v16, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 32 x i8> @llvm.riscv.vunzipe.mask(
- <vscale x 32 x i8> %passthru,
- <vscale x 64 x i8> %arg1,
- <vscale x 32 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 32 x i8> %a
-}
define <vscale x 1 x i16> @test_vunzipe_i16mf4(<vscale x 1 x i16> %passthru, <vscale x 2 x i16> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_i16mf4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
; CHECK-NEXT: vunzipe.v v8, v9
; CHECK-NEXT: ret
%a = call <vscale x 1 x i16> @llvm.riscv.vunzipe(
@@ -179,24 +101,11 @@ define <vscale x 1 x i16> @test_vunzipe_i16mf4(<vscale x 1 x i16> %passthru, <vs
ret <vscale x 1 x i16> %a
}
-define <vscale x 1 x i16> @test_vunzipe_mask_i16mf4(<vscale x 1 x i16> %passthru, <vscale x 2 x i16> %arg1, <vscale x 1 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_i16mf4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v9, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 1 x i16> @llvm.riscv.vunzipe.mask(
- <vscale x 1 x i16> %passthru,
- <vscale x 2 x i16> %arg1,
- <vscale x 1 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 1 x i16> %a
-}
define <vscale x 2 x i16> @test_vunzipe_i16mf2(<vscale x 2 x i16> %passthru, <vscale x 4 x i16> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_i16mf2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: vunzipe.v v8, v9
; CHECK-NEXT: ret
%a = call <vscale x 2 x i16> @llvm.riscv.vunzipe(
@@ -206,24 +115,11 @@ define <vscale x 2 x i16> @test_vunzipe_i16mf2(<vscale x 2 x i16> %passthru, <vs
ret <vscale x 2 x i16> %a
}
-define <vscale x 2 x i16> @test_vunzipe_mask_i16mf2(<vscale x 2 x i16> %passthru, <vscale x 4 x i16> %arg1, <vscale x 2 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_i16mf2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v9, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 2 x i16> @llvm.riscv.vunzipe.mask(
- <vscale x 2 x i16> %passthru,
- <vscale x 4 x i16> %arg1,
- <vscale x 2 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 2 x i16> %a
-}
define <vscale x 4 x i16> @test_vunzipe_i16m1(<vscale x 4 x i16> %passthru, <vscale x 8 x i16> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_i16m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
; CHECK-NEXT: vunzipe.v v8, v10
; CHECK-NEXT: ret
%a = call <vscale x 4 x i16> @llvm.riscv.vunzipe(
@@ -233,24 +129,11 @@ define <vscale x 4 x i16> @test_vunzipe_i16m1(<vscale x 4 x i16> %passthru, <vsc
ret <vscale x 4 x i16> %a
}
-define <vscale x 4 x i16> @test_vunzipe_mask_i16m1(<vscale x 4 x i16> %passthru, <vscale x 8 x i16> %arg1, <vscale x 4 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_i16m1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v10, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 4 x i16> @llvm.riscv.vunzipe.mask(
- <vscale x 4 x i16> %passthru,
- <vscale x 8 x i16> %arg1,
- <vscale x 4 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 4 x i16> %a
-}
define <vscale x 8 x i16> @test_vunzipe_i16m2(<vscale x 8 x i16> %passthru, <vscale x 16 x i16> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_i16m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
; CHECK-NEXT: vunzipe.v v8, v12
; CHECK-NEXT: ret
%a = call <vscale x 8 x i16> @llvm.riscv.vunzipe(
@@ -260,24 +143,11 @@ define <vscale x 8 x i16> @test_vunzipe_i16m2(<vscale x 8 x i16> %passthru, <vsc
ret <vscale x 8 x i16> %a
}
-define <vscale x 8 x i16> @test_vunzipe_mask_i16m2(<vscale x 8 x i16> %passthru, <vscale x 16 x i16> %arg1, <vscale x 8 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_i16m2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v12, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 8 x i16> @llvm.riscv.vunzipe.mask(
- <vscale x 8 x i16> %passthru,
- <vscale x 16 x i16> %arg1,
- <vscale x 8 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 8 x i16> %a
-}
define <vscale x 16 x i16> @test_vunzipe_i16m4(<vscale x 16 x i16> %passthru, <vscale x 32 x i16> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_i16m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma
; CHECK-NEXT: vunzipe.v v8, v16
; CHECK-NEXT: ret
%a = call <vscale x 16 x i16> @llvm.riscv.vunzipe(
@@ -287,24 +157,11 @@ define <vscale x 16 x i16> @test_vunzipe_i16m4(<vscale x 16 x i16> %passthru, <v
ret <vscale x 16 x i16> %a
}
-define <vscale x 16 x i16> @test_vunzipe_mask_i16m4(<vscale x 16 x i16> %passthru, <vscale x 32 x i16> %arg1, <vscale x 16 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_i16m4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v16, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 16 x i16> @llvm.riscv.vunzipe.mask(
- <vscale x 16 x i16> %passthru,
- <vscale x 32 x i16> %arg1,
- <vscale x 16 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 16 x i16> %a
-}
define <vscale x 1 x i32> @test_vunzipe_i32mf2(<vscale x 1 x i32> %passthru, <vscale x 2 x i32> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_i32mf2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
; CHECK-NEXT: vunzipe.v v8, v9
; CHECK-NEXT: ret
%a = call <vscale x 1 x i32> @llvm.riscv.vunzipe(
@@ -314,24 +171,11 @@ define <vscale x 1 x i32> @test_vunzipe_i32mf2(<vscale x 1 x i32> %passthru, <vs
ret <vscale x 1 x i32> %a
}
-define <vscale x 1 x i32> @test_vunzipe_mask_i32mf2(<vscale x 1 x i32> %passthru, <vscale x 2 x i32> %arg1, <vscale x 1 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_i32mf2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v9, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 1 x i32> @llvm.riscv.vunzipe.mask(
- <vscale x 1 x i32> %passthru,
- <vscale x 2 x i32> %arg1,
- <vscale x 1 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 1 x i32> %a
-}
define <vscale x 2 x i32> @test_vunzipe_i32m1(<vscale x 2 x i32> %passthru, <vscale x 4 x i32> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_i32m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
; CHECK-NEXT: vunzipe.v v8, v10
; CHECK-NEXT: ret
%a = call <vscale x 2 x i32> @llvm.riscv.vunzipe(
@@ -341,24 +185,11 @@ define <vscale x 2 x i32> @test_vunzipe_i32m1(<vscale x 2 x i32> %passthru, <vsc
ret <vscale x 2 x i32> %a
}
-define <vscale x 2 x i32> @test_vunzipe_mask_i32m1(<vscale x 2 x i32> %passthru, <vscale x 4 x i32> %arg1, <vscale x 2 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_i32m1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v10, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 2 x i32> @llvm.riscv.vunzipe.mask(
- <vscale x 2 x i32> %passthru,
- <vscale x 4 x i32> %arg1,
- <vscale x 2 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 2 x i32> %a
-}
define <vscale x 4 x i32> @test_vunzipe_i32m2(<vscale x 4 x i32> %passthru, <vscale x 8 x i32> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_i32m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
; CHECK-NEXT: vunzipe.v v8, v12
; CHECK-NEXT: ret
%a = call <vscale x 4 x i32> @llvm.riscv.vunzipe(
@@ -368,24 +199,11 @@ define <vscale x 4 x i32> @test_vunzipe_i32m2(<vscale x 4 x i32> %passthru, <vsc
ret <vscale x 4 x i32> %a
}
-define <vscale x 4 x i32> @test_vunzipe_mask_i32m2(<vscale x 4 x i32> %passthru, <vscale x 8 x i32> %arg1, <vscale x 4 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_i32m2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v12, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 4 x i32> @llvm.riscv.vunzipe.mask(
- <vscale x 4 x i32> %passthru,
- <vscale x 8 x i32> %arg1,
- <vscale x 4 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 4 x i32> %a
-}
define <vscale x 8 x i32> @test_vunzipe_i32m4(<vscale x 8 x i32> %passthru, <vscale x 16 x i32> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_i32m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, ma
; CHECK-NEXT: vunzipe.v v8, v16
; CHECK-NEXT: ret
%a = call <vscale x 8 x i32> @llvm.riscv.vunzipe(
@@ -395,24 +213,11 @@ define <vscale x 8 x i32> @test_vunzipe_i32m4(<vscale x 8 x i32> %passthru, <vsc
ret <vscale x 8 x i32> %a
}
-define <vscale x 8 x i32> @test_vunzipe_mask_i32m4(<vscale x 8 x i32> %passthru, <vscale x 16 x i32> %arg1, <vscale x 8 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_i32m4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v16, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 8 x i32> @llvm.riscv.vunzipe.mask(
- <vscale x 8 x i32> %passthru,
- <vscale x 16 x i32> %arg1,
- <vscale x 8 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 8 x i32> %a
-}
define <vscale x 1 x i64> @test_vunzipe_i64m1(<vscale x 1 x i64> %passthru, <vscale x 2 x i64> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_i64m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma
; CHECK-NEXT: vunzipe.v v8, v10
; CHECK-NEXT: ret
%a = call <vscale x 1 x i64> @llvm.riscv.vunzipe(
@@ -422,24 +227,11 @@ define <vscale x 1 x i64> @test_vunzipe_i64m1(<vscale x 1 x i64> %passthru, <vsc
ret <vscale x 1 x i64> %a
}
-define <vscale x 1 x i64> @test_vunzipe_mask_i64m1(<vscale x 1 x i64> %passthru, <vscale x 2 x i64> %arg1, <vscale x 1 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_i64m1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v10, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 1 x i64> @llvm.riscv.vunzipe.mask(
- <vscale x 1 x i64> %passthru,
- <vscale x 2 x i64> %arg1,
- <vscale x 1 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 1 x i64> %a
-}
define <vscale x 2 x i64> @test_vunzipe_i64m2(<vscale x 2 x i64> %passthru, <vscale x 4 x i64> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_i64m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma
; CHECK-NEXT: vunzipe.v v8, v12
; CHECK-NEXT: ret
%a = call <vscale x 2 x i64> @llvm.riscv.vunzipe(
@@ -449,24 +241,11 @@ define <vscale x 2 x i64> @test_vunzipe_i64m2(<vscale x 2 x i64> %passthru, <vsc
ret <vscale x 2 x i64> %a
}
-define <vscale x 2 x i64> @test_vunzipe_mask_i64m2(<vscale x 2 x i64> %passthru, <vscale x 4 x i64> %arg1, <vscale x 2 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_i64m2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v12, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 2 x i64> @llvm.riscv.vunzipe.mask(
- <vscale x 2 x i64> %passthru,
- <vscale x 4 x i64> %arg1,
- <vscale x 2 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 2 x i64> %a
-}
define <vscale x 4 x i64> @test_vunzipe_i64m4(<vscale x 4 x i64> %passthru, <vscale x 8 x i64> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_i64m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, ma
; CHECK-NEXT: vunzipe.v v8, v16
; CHECK-NEXT: ret
%a = call <vscale x 4 x i64> @llvm.riscv.vunzipe(
@@ -476,19 +255,6 @@ define <vscale x 4 x i64> @test_vunzipe_i64m4(<vscale x 4 x i64> %passthru, <vsc
ret <vscale x 4 x i64> %a
}
-define <vscale x 4 x i64> @test_vunzipe_mask_i64m4(<vscale x 4 x i64> %passthru, <vscale x 8 x i64> %arg1, <vscale x 4 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_i64m4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v16, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 4 x i64> @llvm.riscv.vunzipe.mask(
- <vscale x 4 x i64> %passthru,
- <vscale x 8 x i64> %arg1,
- <vscale x 4 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 4 x i64> %a
-}
; Floating-point types
@@ -496,7 +262,7 @@ define <vscale x 4 x i64> @test_vunzipe_mask_i64m4(<vscale x 4 x i64> %passthru,
define <vscale x 1 x half> @test_vunzipe_f16mf4(<vscale x 1 x half> %passthru, <vscale x 2 x half> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_f16mf4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
; CHECK-NEXT: vunzipe.v v8, v9
; CHECK-NEXT: ret
%r = call <vscale x 1 x half> @llvm.riscv.vunzipe(
@@ -506,24 +272,11 @@ define <vscale x 1 x half> @test_vunzipe_f16mf4(<vscale x 1 x half> %passthru, <
ret <vscale x 1 x half> %r
}
-define <vscale x 1 x half> @test_vunzipe_mask_f16mf4(<vscale x 1 x half> %passthru, <vscale x 2 x half> %src, <vscale x 1 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_f16mf4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v9, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 1 x half> @llvm.riscv.vunzipe.mask(
- <vscale x 1 x half> %passthru,
- <vscale x 2 x half> %src,
- <vscale x 1 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 1 x half> %r
-}
define <vscale x 2 x half> @test_vunzipe_f16mf2(<vscale x 2 x half> %passthru, <vscale x 4 x half> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_f16mf2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: vunzipe.v v8, v9
; CHECK-NEXT: ret
%r = call <vscale x 2 x half> @llvm.riscv.vunzipe(
@@ -533,24 +286,11 @@ define <vscale x 2 x half> @test_vunzipe_f16mf2(<vscale x 2 x half> %passthru, <
ret <vscale x 2 x half> %r
}
-define <vscale x 2 x half> @test_vunzipe_mask_f16mf2(<vscale x 2 x half> %passthru, <vscale x 4 x half> %src, <vscale x 2 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_f16mf2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v9, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 2 x half> @llvm.riscv.vunzipe.mask(
- <vscale x 2 x half> %passthru,
- <vscale x 4 x half> %src,
- <vscale x 2 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 2 x half> %r
-}
define <vscale x 4 x half> @test_vunzipe_f16m1(<vscale x 4 x half> %passthru, <vscale x 8 x half> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_f16m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
; CHECK-NEXT: vunzipe.v v8, v10
; CHECK-NEXT: ret
%r = call <vscale x 4 x half> @llvm.riscv.vunzipe(
@@ -560,24 +300,11 @@ define <vscale x 4 x half> @test_vunzipe_f16m1(<vscale x 4 x half> %passthru, <v
ret <vscale x 4 x half> %r
}
-define <vscale x 4 x half> @test_vunzipe_mask_f16m1(<vscale x 4 x half> %passthru, <vscale x 8 x half> %src, <vscale x 4 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_f16m1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v10, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 4 x half> @llvm.riscv.vunzipe.mask(
- <vscale x 4 x half> %passthru,
- <vscale x 8 x half> %src,
- <vscale x 4 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 4 x half> %r
-}
define <vscale x 8 x half> @test_vunzipe_f16m2(<vscale x 8 x half> %passthru, <vscale x 16 x half> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_f16m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
; CHECK-NEXT: vunzipe.v v8, v12
; CHECK-NEXT: ret
%r = call <vscale x 8 x half> @llvm.riscv.vunzipe(
@@ -587,24 +314,11 @@ define <vscale x 8 x half> @test_vunzipe_f16m2(<vscale x 8 x half> %passthru, <v
ret <vscale x 8 x half> %r
}
-define <vscale x 8 x half> @test_vunzipe_mask_f16m2(<vscale x 8 x half> %passthru, <vscale x 16 x half> %src, <vscale x 8 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_f16m2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v12, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 8 x half> @llvm.riscv.vunzipe.mask(
- <vscale x 8 x half> %passthru,
- <vscale x 16 x half> %src,
- <vscale x 8 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 8 x half> %r
-}
define <vscale x 16 x half> @test_vunzipe_f16m4(<vscale x 16 x half> %passthru, <vscale x 32 x half> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_f16m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma
; CHECK-NEXT: vunzipe.v v8, v16
; CHECK-NEXT: ret
%r = call <vscale x 16 x half> @llvm.riscv.vunzipe(
@@ -614,25 +328,12 @@ define <vscale x 16 x half> @test_vunzipe_f16m4(<vscale x 16 x half> %passthru,
ret <vscale x 16 x half> %r
}
-define <vscale x 16 x half> @test_vunzipe_mask_f16m4(<vscale x 16 x half> %passthru, <vscale x 32 x half> %src, <vscale x 16 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_f16m4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v16, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 16 x half> @llvm.riscv.vunzipe.mask(
- <vscale x 16 x half> %passthru,
- <vscale x 32 x half> %src,
- <vscale x 16 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 16 x half> %r
-}
; bf16
define <vscale x 1 x bfloat> @test_vunzipe_bf16mf4(<vscale x 1 x bfloat> %passthru, <vscale x 2 x bfloat> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_bf16mf4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
; CHECK-NEXT: vunzipe.v v8, v9
; CHECK-NEXT: ret
%r = call <vscale x 1 x bfloat> @llvm.riscv.vunzipe(
@@ -642,24 +343,11 @@ define <vscale x 1 x bfloat> @test_vunzipe_bf16mf4(<vscale x 1 x bfloat> %passth
ret <vscale x 1 x bfloat> %r
}
-define <vscale x 1 x bfloat> @test_vunzipe_mask_bf16mf4(<vscale x 1 x bfloat> %passthru, <vscale x 2 x bfloat> %src, <vscale x 1 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_bf16mf4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v9, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 1 x bfloat> @llvm.riscv.vunzipe.mask(
- <vscale x 1 x bfloat> %passthru,
- <vscale x 2 x bfloat> %src,
- <vscale x 1 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 1 x bfloat> %r
-}
define <vscale x 2 x bfloat> @test_vunzipe_bf16mf2(<vscale x 2 x bfloat> %passthru, <vscale x 4 x bfloat> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_bf16mf2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: vunzipe.v v8, v9
; CHECK-NEXT: ret
%r = call <vscale x 2 x bfloat> @llvm.riscv.vunzipe(
@@ -669,24 +357,11 @@ define <vscale x 2 x bfloat> @test_vunzipe_bf16mf2(<vscale x 2 x bfloat> %passth
ret <vscale x 2 x bfloat> %r
}
-define <vscale x 2 x bfloat> @test_vunzipe_mask_bf16mf2(<vscale x 2 x bfloat> %passthru, <vscale x 4 x bfloat> %src, <vscale x 2 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_bf16mf2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v9, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 2 x bfloat> @llvm.riscv.vunzipe.mask(
- <vscale x 2 x bfloat> %passthru,
- <vscale x 4 x bfloat> %src,
- <vscale x 2 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 2 x bfloat> %r
-}
define <vscale x 4 x bfloat> @test_vunzipe_bf16m1(<vscale x 4 x bfloat> %passthru, <vscale x 8 x bfloat> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_bf16m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
; CHECK-NEXT: vunzipe.v v8, v10
; CHECK-NEXT: ret
%r = call <vscale x 4 x bfloat> @llvm.riscv.vunzipe(
@@ -696,24 +371,11 @@ define <vscale x 4 x bfloat> @test_vunzipe_bf16m1(<vscale x 4 x bfloat> %passthr
ret <vscale x 4 x bfloat> %r
}
-define <vscale x 4 x bfloat> @test_vunzipe_mask_bf16m1(<vscale x 4 x bfloat> %passthru, <vscale x 8 x bfloat> %src, <vscale x 4 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_bf16m1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v10, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 4 x bfloat> @llvm.riscv.vunzipe.mask(
- <vscale x 4 x bfloat> %passthru,
- <vscale x 8 x bfloat> %src,
- <vscale x 4 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 4 x bfloat> %r
-}
define <vscale x 8 x bfloat> @test_vunzipe_bf16m2(<vscale x 8 x bfloat> %passthru, <vscale x 16 x bfloat> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_bf16m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
; CHECK-NEXT: vunzipe.v v8, v12
; CHECK-NEXT: ret
%r = call <vscale x 8 x bfloat> @llvm.riscv.vunzipe(
@@ -723,24 +385,11 @@ define <vscale x 8 x bfloat> @test_vunzipe_bf16m2(<vscale x 8 x bfloat> %passthr
ret <vscale x 8 x bfloat> %r
}
-define <vscale x 8 x bfloat> @test_vunzipe_mask_bf16m2(<vscale x 8 x bfloat> %passthru, <vscale x 16 x bfloat> %src, <vscale x 8 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_bf16m2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v12, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 8 x bfloat> @llvm.riscv.vunzipe.mask(
- <vscale x 8 x bfloat> %passthru,
- <vscale x 16 x bfloat> %src,
- <vscale x 8 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 8 x bfloat> %r
-}
define <vscale x 16 x bfloat> @test_vunzipe_bf16m4(<vscale x 16 x bfloat> %passthru, <vscale x 32 x bfloat> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_bf16m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma
; CHECK-NEXT: vunzipe.v v8, v16
; CHECK-NEXT: ret
%r = call <vscale x 16 x bfloat> @llvm.riscv.vunzipe(
@@ -750,25 +399,12 @@ define <vscale x 16 x bfloat> @test_vunzipe_bf16m4(<vscale x 16 x bfloat> %passt
ret <vscale x 16 x bfloat> %r
}
-define <vscale x 16 x bfloat> @test_vunzipe_mask_bf16m4(<vscale x 16 x bfloat> %passthru, <vscale x 32 x bfloat> %src, <vscale x 16 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_bf16m4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v16, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 16 x bfloat> @llvm.riscv.vunzipe.mask(
- <vscale x 16 x bfloat> %passthru,
- <vscale x 32 x bfloat> %src,
- <vscale x 16 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 16 x bfloat> %r
-}
; f32
define <vscale x 1 x float> @test_vunzipe_f32mf2(<vscale x 1 x float> %passthru, <vscale x 2 x float> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_f32mf2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
; CHECK-NEXT: vunzipe.v v8, v9
; CHECK-NEXT: ret
%r = call <vscale x 1 x float> @llvm.riscv.vunzipe(
@@ -778,24 +414,11 @@ define <vscale x 1 x float> @test_vunzipe_f32mf2(<vscale x 1 x float> %passthru,
ret <vscale x 1 x float> %r
}
-define <vscale x 1 x float> @test_vunzipe_mask_f32mf2(<vscale x 1 x float> %passthru, <vscale x 2 x float> %src, <vscale x 1 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_f32mf2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v9, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 1 x float> @llvm.riscv.vunzipe.mask(
- <vscale x 1 x float> %passthru,
- <vscale x 2 x float> %src,
- <vscale x 1 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 1 x float> %r
-}
define <vscale x 2 x float> @test_vunzipe_f32m1(<vscale x 2 x float> %passthru, <vscale x 4 x float> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_f32m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
; CHECK-NEXT: vunzipe.v v8, v10
; CHECK-NEXT: ret
%r = call <vscale x 2 x float> @llvm.riscv.vunzipe(
@@ -805,24 +428,11 @@ define <vscale x 2 x float> @test_vunzipe_f32m1(<vscale x 2 x float> %passthru,
ret <vscale x 2 x float> %r
}
-define <vscale x 2 x float> @test_vunzipe_mask_f32m1(<vscale x 2 x float> %passthru, <vscale x 4 x float> %src, <vscale x 2 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_f32m1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v10, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 2 x float> @llvm.riscv.vunzipe.mask(
- <vscale x 2 x float> %passthru,
- <vscale x 4 x float> %src,
- <vscale x 2 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 2 x float> %r
-}
define <vscale x 4 x float> @test_vunzipe_f32m2(<vscale x 4 x float> %passthru, <vscale x 8 x float> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_f32m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
; CHECK-NEXT: vunzipe.v v8, v12
; CHECK-NEXT: ret
%r = call <vscale x 4 x float> @llvm.riscv.vunzipe(
@@ -832,24 +442,11 @@ define <vscale x 4 x float> @test_vunzipe_f32m2(<vscale x 4 x float> %passthru,
ret <vscale x 4 x float> %r
}
-define <vscale x 4 x float> @test_vunzipe_mask_f32m2(<vscale x 4 x float> %passthru, <vscale x 8 x float> %src, <vscale x 4 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_f32m2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v12, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 4 x float> @llvm.riscv.vunzipe.mask(
- <vscale x 4 x float> %passthru,
- <vscale x 8 x float> %src,
- <vscale x 4 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 4 x float> %r
-}
define <vscale x 8 x float> @test_vunzipe_f32m4(<vscale x 8 x float> %passthru, <vscale x 16 x float> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_f32m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, ma
; CHECK-NEXT: vunzipe.v v8, v16
; CHECK-NEXT: ret
%r = call <vscale x 8 x float> @llvm.riscv.vunzipe(
@@ -859,25 +456,12 @@ define <vscale x 8 x float> @test_vunzipe_f32m4(<vscale x 8 x float> %passthru,
ret <vscale x 8 x float> %r
}
-define <vscale x 8 x float> @test_vunzipe_mask_f32m4(<vscale x 8 x float> %passthru, <vscale x 16 x float> %src, <vscale x 8 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_f32m4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v16, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 8 x float> @llvm.riscv.vunzipe.mask(
- <vscale x 8 x float> %passthru,
- <vscale x 16 x float> %src,
- <vscale x 8 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 8 x float> %r
-}
; f64
define <vscale x 1 x double> @test_vunzipe_f64m1(<vscale x 1 x double> %passthru, <vscale x 2 x double> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_f64m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma
; CHECK-NEXT: vunzipe.v v8, v10
; CHECK-NEXT: ret
%r = call <vscale x 1 x double> @llvm.riscv.vunzipe(
@@ -887,24 +471,11 @@ define <vscale x 1 x double> @test_vunzipe_f64m1(<vscale x 1 x double> %passthru
ret <vscale x 1 x double> %r
}
-define <vscale x 1 x double> @test_vunzipe_mask_f64m1(<vscale x 1 x double> %passthru, <vscale x 2 x double> %src, <vscale x 1 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_f64m1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v10, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 1 x double> @llvm.riscv.vunzipe.mask(
- <vscale x 1 x double> %passthru,
- <vscale x 2 x double> %src,
- <vscale x 1 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 1 x double> %r
-}
define <vscale x 2 x double> @test_vunzipe_f64m2(<vscale x 2 x double> %passthru, <vscale x 4 x double> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_f64m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma
; CHECK-NEXT: vunzipe.v v8, v12
; CHECK-NEXT: ret
%r = call <vscale x 2 x double> @llvm.riscv.vunzipe(
@@ -914,24 +485,11 @@ define <vscale x 2 x double> @test_vunzipe_f64m2(<vscale x 2 x double> %passthru
ret <vscale x 2 x double> %r
}
-define <vscale x 2 x double> @test_vunzipe_mask_f64m2(<vscale x 2 x double> %passthru, <vscale x 4 x double> %src, <vscale x 2 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_f64m2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v12, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 2 x double> @llvm.riscv.vunzipe.mask(
- <vscale x 2 x double> %passthru,
- <vscale x 4 x double> %src,
- <vscale x 2 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 2 x double> %r
-}
define <vscale x 4 x double> @test_vunzipe_f64m4(<vscale x 4 x double> %passthru, <vscale x 8 x double> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipe_f64m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, ma
; CHECK-NEXT: vunzipe.v v8, v16
; CHECK-NEXT: ret
%r = call <vscale x 4 x double> @llvm.riscv.vunzipe(
@@ -941,19 +499,6 @@ define <vscale x 4 x double> @test_vunzipe_f64m4(<vscale x 4 x double> %passthru
ret <vscale x 4 x double> %r
}
-define <vscale x 4 x double> @test_vunzipe_mask_f64m4(<vscale x 4 x double> %passthru, <vscale x 8 x double> %src, <vscale x 4 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipe_mask_f64m4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vunzipe.v v8, v16, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 4 x double> @llvm.riscv.vunzipe.mask(
- <vscale x 4 x double> %passthru,
- <vscale x 8 x double> %src,
- <vscale x 4 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 4 x double> %r
-}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; RV32: {{.*}}
; RV64: {{.*}}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vunzipo.ll b/llvm/test/CodeGen/RISCV/rvv/vunzipo.ll
index 0e7303ce3e130..b52dff2421f11 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vunzipo.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vunzipo.ll
@@ -7,7 +7,7 @@
define <vscale x 1 x i8> @test_vunzipo_i8mf8(<vscale x 1 x i8> %passthru, <vscale x 2 x i8> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_i8mf8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, ma
; CHECK-NEXT: vunzipo.v v8, v9
; CHECK-NEXT: ret
%a = call <vscale x 1 x i8> @llvm.riscv.vunzipo(
@@ -17,24 +17,11 @@ define <vscale x 1 x i8> @test_vunzipo_i8mf8(<vscale x 1 x i8> %passthru, <vscal
ret <vscale x 1 x i8> %a
}
-define <vscale x 1 x i8> @test_vunzipo_mask_i8mf8(<vscale x 1 x i8> %passthru, <vscale x 2 x i8> %arg1, <vscale x 1 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_i8mf8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v9, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 1 x i8> @llvm.riscv.vunzipo.mask(
- <vscale x 1 x i8> %passthru,
- <vscale x 2 x i8> %arg1,
- <vscale x 1 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 1 x i8> %a
-}
define <vscale x 2 x i8> @test_vunzipo_i8mf4(<vscale x 2 x i8> %passthru, <vscale x 4 x i8> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_i8mf4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma
; CHECK-NEXT: vunzipo.v v8, v9
; CHECK-NEXT: ret
%a = call <vscale x 2 x i8> @llvm.riscv.vunzipo(
@@ -44,24 +31,11 @@ define <vscale x 2 x i8> @test_vunzipo_i8mf4(<vscale x 2 x i8> %passthru, <vscal
ret <vscale x 2 x i8> %a
}
-define <vscale x 2 x i8> @test_vunzipo_mask_i8mf4(<vscale x 2 x i8> %passthru, <vscale x 4 x i8> %arg1, <vscale x 2 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_i8mf4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v9, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 2 x i8> @llvm.riscv.vunzipo.mask(
- <vscale x 2 x i8> %passthru,
- <vscale x 4 x i8> %arg1,
- <vscale x 2 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 2 x i8> %a
-}
define <vscale x 4 x i8> @test_vunzipo_i8mf2(<vscale x 4 x i8> %passthru, <vscale x 8 x i8> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_i8mf2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
; CHECK-NEXT: vunzipo.v v8, v9
; CHECK-NEXT: ret
%a = call <vscale x 4 x i8> @llvm.riscv.vunzipo(
@@ -71,24 +45,11 @@ define <vscale x 4 x i8> @test_vunzipo_i8mf2(<vscale x 4 x i8> %passthru, <vscal
ret <vscale x 4 x i8> %a
}
-define <vscale x 4 x i8> @test_vunzipo_mask_i8mf2(<vscale x 4 x i8> %passthru, <vscale x 8 x i8> %arg1, <vscale x 4 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_i8mf2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v9, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 4 x i8> @llvm.riscv.vunzipo.mask(
- <vscale x 4 x i8> %passthru,
- <vscale x 8 x i8> %arg1,
- <vscale x 4 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 4 x i8> %a
-}
define <vscale x 8 x i8> @test_vunzipo_i8m1(<vscale x 8 x i8> %passthru, <vscale x 16 x i8> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_i8m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, ma
; CHECK-NEXT: vunzipo.v v8, v10
; CHECK-NEXT: ret
%a = call <vscale x 8 x i8> @llvm.riscv.vunzipo(
@@ -98,24 +59,11 @@ define <vscale x 8 x i8> @test_vunzipo_i8m1(<vscale x 8 x i8> %passthru, <vscale
ret <vscale x 8 x i8> %a
}
-define <vscale x 8 x i8> @test_vunzipo_mask_i8m1(<vscale x 8 x i8> %passthru, <vscale x 16 x i8> %arg1, <vscale x 8 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_i8m1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v10, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 8 x i8> @llvm.riscv.vunzipo.mask(
- <vscale x 8 x i8> %passthru,
- <vscale x 16 x i8> %arg1,
- <vscale x 8 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 8 x i8> %a
-}
define <vscale x 16 x i8> @test_vunzipo_i8m2(<vscale x 16 x i8> %passthru, <vscale x 32 x i8> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_i8m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, ma
; CHECK-NEXT: vunzipo.v v8, v12
; CHECK-NEXT: ret
%a = call <vscale x 16 x i8> @llvm.riscv.vunzipo(
@@ -125,24 +73,11 @@ define <vscale x 16 x i8> @test_vunzipo_i8m2(<vscale x 16 x i8> %passthru, <vsca
ret <vscale x 16 x i8> %a
}
-define <vscale x 16 x i8> @test_vunzipo_mask_i8m2(<vscale x 16 x i8> %passthru, <vscale x 32 x i8> %arg1, <vscale x 16 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_i8m2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v12, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 16 x i8> @llvm.riscv.vunzipo.mask(
- <vscale x 16 x i8> %passthru,
- <vscale x 32 x i8> %arg1,
- <vscale x 16 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 16 x i8> %a
-}
define <vscale x 32 x i8> @test_vunzipo_i8m4(<vscale x 32 x i8> %passthru, <vscale x 64 x i8> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_i8m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, ma
; CHECK-NEXT: vunzipo.v v8, v16
; CHECK-NEXT: ret
%a = call <vscale x 32 x i8> @llvm.riscv.vunzipo(
@@ -152,24 +87,11 @@ define <vscale x 32 x i8> @test_vunzipo_i8m4(<vscale x 32 x i8> %passthru, <vsca
ret <vscale x 32 x i8> %a
}
-define <vscale x 32 x i8> @test_vunzipo_mask_i8m4(<vscale x 32 x i8> %passthru, <vscale x 64 x i8> %arg1, <vscale x 32 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_i8m4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v16, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 32 x i8> @llvm.riscv.vunzipo.mask(
- <vscale x 32 x i8> %passthru,
- <vscale x 64 x i8> %arg1,
- <vscale x 32 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 32 x i8> %a
-}
define <vscale x 1 x i16> @test_vunzipo_i16mf4(<vscale x 1 x i16> %passthru, <vscale x 2 x i16> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_i16mf4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
; CHECK-NEXT: vunzipo.v v8, v9
; CHECK-NEXT: ret
%a = call <vscale x 1 x i16> @llvm.riscv.vunzipo(
@@ -179,24 +101,11 @@ define <vscale x 1 x i16> @test_vunzipo_i16mf4(<vscale x 1 x i16> %passthru, <vs
ret <vscale x 1 x i16> %a
}
-define <vscale x 1 x i16> @test_vunzipo_mask_i16mf4(<vscale x 1 x i16> %passthru, <vscale x 2 x i16> %arg1, <vscale x 1 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_i16mf4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v9, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 1 x i16> @llvm.riscv.vunzipo.mask(
- <vscale x 1 x i16> %passthru,
- <vscale x 2 x i16> %arg1,
- <vscale x 1 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 1 x i16> %a
-}
define <vscale x 2 x i16> @test_vunzipo_i16mf2(<vscale x 2 x i16> %passthru, <vscale x 4 x i16> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_i16mf2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: vunzipo.v v8, v9
; CHECK-NEXT: ret
%a = call <vscale x 2 x i16> @llvm.riscv.vunzipo(
@@ -206,24 +115,11 @@ define <vscale x 2 x i16> @test_vunzipo_i16mf2(<vscale x 2 x i16> %passthru, <vs
ret <vscale x 2 x i16> %a
}
-define <vscale x 2 x i16> @test_vunzipo_mask_i16mf2(<vscale x 2 x i16> %passthru, <vscale x 4 x i16> %arg1, <vscale x 2 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_i16mf2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v9, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 2 x i16> @llvm.riscv.vunzipo.mask(
- <vscale x 2 x i16> %passthru,
- <vscale x 4 x i16> %arg1,
- <vscale x 2 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 2 x i16> %a
-}
define <vscale x 4 x i16> @test_vunzipo_i16m1(<vscale x 4 x i16> %passthru, <vscale x 8 x i16> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_i16m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
; CHECK-NEXT: vunzipo.v v8, v10
; CHECK-NEXT: ret
%a = call <vscale x 4 x i16> @llvm.riscv.vunzipo(
@@ -233,24 +129,11 @@ define <vscale x 4 x i16> @test_vunzipo_i16m1(<vscale x 4 x i16> %passthru, <vsc
ret <vscale x 4 x i16> %a
}
-define <vscale x 4 x i16> @test_vunzipo_mask_i16m1(<vscale x 4 x i16> %passthru, <vscale x 8 x i16> %arg1, <vscale x 4 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_i16m1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v10, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 4 x i16> @llvm.riscv.vunzipo.mask(
- <vscale x 4 x i16> %passthru,
- <vscale x 8 x i16> %arg1,
- <vscale x 4 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 4 x i16> %a
-}
define <vscale x 8 x i16> @test_vunzipo_i16m2(<vscale x 8 x i16> %passthru, <vscale x 16 x i16> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_i16m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
; CHECK-NEXT: vunzipo.v v8, v12
; CHECK-NEXT: ret
%a = call <vscale x 8 x i16> @llvm.riscv.vunzipo(
@@ -260,24 +143,11 @@ define <vscale x 8 x i16> @test_vunzipo_i16m2(<vscale x 8 x i16> %passthru, <vsc
ret <vscale x 8 x i16> %a
}
-define <vscale x 8 x i16> @test_vunzipo_mask_i16m2(<vscale x 8 x i16> %passthru, <vscale x 16 x i16> %arg1, <vscale x 8 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_i16m2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v12, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 8 x i16> @llvm.riscv.vunzipo.mask(
- <vscale x 8 x i16> %passthru,
- <vscale x 16 x i16> %arg1,
- <vscale x 8 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 8 x i16> %a
-}
define <vscale x 16 x i16> @test_vunzipo_i16m4(<vscale x 16 x i16> %passthru, <vscale x 32 x i16> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_i16m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma
; CHECK-NEXT: vunzipo.v v8, v16
; CHECK-NEXT: ret
%a = call <vscale x 16 x i16> @llvm.riscv.vunzipo(
@@ -287,24 +157,11 @@ define <vscale x 16 x i16> @test_vunzipo_i16m4(<vscale x 16 x i16> %passthru, <v
ret <vscale x 16 x i16> %a
}
-define <vscale x 16 x i16> @test_vunzipo_mask_i16m4(<vscale x 16 x i16> %passthru, <vscale x 32 x i16> %arg1, <vscale x 16 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_i16m4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v16, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 16 x i16> @llvm.riscv.vunzipo.mask(
- <vscale x 16 x i16> %passthru,
- <vscale x 32 x i16> %arg1,
- <vscale x 16 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 16 x i16> %a
-}
define <vscale x 1 x i32> @test_vunzipo_i32mf2(<vscale x 1 x i32> %passthru, <vscale x 2 x i32> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_i32mf2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
; CHECK-NEXT: vunzipo.v v8, v9
; CHECK-NEXT: ret
%a = call <vscale x 1 x i32> @llvm.riscv.vunzipo(
@@ -314,24 +171,11 @@ define <vscale x 1 x i32> @test_vunzipo_i32mf2(<vscale x 1 x i32> %passthru, <vs
ret <vscale x 1 x i32> %a
}
-define <vscale x 1 x i32> @test_vunzipo_mask_i32mf2(<vscale x 1 x i32> %passthru, <vscale x 2 x i32> %arg1, <vscale x 1 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_i32mf2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v9, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 1 x i32> @llvm.riscv.vunzipo.mask(
- <vscale x 1 x i32> %passthru,
- <vscale x 2 x i32> %arg1,
- <vscale x 1 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 1 x i32> %a
-}
define <vscale x 2 x i32> @test_vunzipo_i32m1(<vscale x 2 x i32> %passthru, <vscale x 4 x i32> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_i32m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
; CHECK-NEXT: vunzipo.v v8, v10
; CHECK-NEXT: ret
%a = call <vscale x 2 x i32> @llvm.riscv.vunzipo(
@@ -341,24 +185,11 @@ define <vscale x 2 x i32> @test_vunzipo_i32m1(<vscale x 2 x i32> %passthru, <vsc
ret <vscale x 2 x i32> %a
}
-define <vscale x 2 x i32> @test_vunzipo_mask_i32m1(<vscale x 2 x i32> %passthru, <vscale x 4 x i32> %arg1, <vscale x 2 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_i32m1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v10, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 2 x i32> @llvm.riscv.vunzipo.mask(
- <vscale x 2 x i32> %passthru,
- <vscale x 4 x i32> %arg1,
- <vscale x 2 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 2 x i32> %a
-}
define <vscale x 4 x i32> @test_vunzipo_i32m2(<vscale x 4 x i32> %passthru, <vscale x 8 x i32> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_i32m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
; CHECK-NEXT: vunzipo.v v8, v12
; CHECK-NEXT: ret
%a = call <vscale x 4 x i32> @llvm.riscv.vunzipo(
@@ -368,24 +199,11 @@ define <vscale x 4 x i32> @test_vunzipo_i32m2(<vscale x 4 x i32> %passthru, <vsc
ret <vscale x 4 x i32> %a
}
-define <vscale x 4 x i32> @test_vunzipo_mask_i32m2(<vscale x 4 x i32> %passthru, <vscale x 8 x i32> %arg1, <vscale x 4 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_i32m2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v12, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 4 x i32> @llvm.riscv.vunzipo.mask(
- <vscale x 4 x i32> %passthru,
- <vscale x 8 x i32> %arg1,
- <vscale x 4 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 4 x i32> %a
-}
define <vscale x 8 x i32> @test_vunzipo_i32m4(<vscale x 8 x i32> %passthru, <vscale x 16 x i32> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_i32m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, ma
; CHECK-NEXT: vunzipo.v v8, v16
; CHECK-NEXT: ret
%a = call <vscale x 8 x i32> @llvm.riscv.vunzipo(
@@ -395,24 +213,11 @@ define <vscale x 8 x i32> @test_vunzipo_i32m4(<vscale x 8 x i32> %passthru, <vsc
ret <vscale x 8 x i32> %a
}
-define <vscale x 8 x i32> @test_vunzipo_mask_i32m4(<vscale x 8 x i32> %passthru, <vscale x 16 x i32> %arg1, <vscale x 8 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_i32m4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v16, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 8 x i32> @llvm.riscv.vunzipo.mask(
- <vscale x 8 x i32> %passthru,
- <vscale x 16 x i32> %arg1,
- <vscale x 8 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 8 x i32> %a
-}
define <vscale x 1 x i64> @test_vunzipo_i64m1(<vscale x 1 x i64> %passthru, <vscale x 2 x i64> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_i64m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma
; CHECK-NEXT: vunzipo.v v8, v10
; CHECK-NEXT: ret
%a = call <vscale x 1 x i64> @llvm.riscv.vunzipo(
@@ -422,24 +227,11 @@ define <vscale x 1 x i64> @test_vunzipo_i64m1(<vscale x 1 x i64> %passthru, <vsc
ret <vscale x 1 x i64> %a
}
-define <vscale x 1 x i64> @test_vunzipo_mask_i64m1(<vscale x 1 x i64> %passthru, <vscale x 2 x i64> %arg1, <vscale x 1 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_i64m1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v10, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 1 x i64> @llvm.riscv.vunzipo.mask(
- <vscale x 1 x i64> %passthru,
- <vscale x 2 x i64> %arg1,
- <vscale x 1 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 1 x i64> %a
-}
define <vscale x 2 x i64> @test_vunzipo_i64m2(<vscale x 2 x i64> %passthru, <vscale x 4 x i64> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_i64m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma
; CHECK-NEXT: vunzipo.v v8, v12
; CHECK-NEXT: ret
%a = call <vscale x 2 x i64> @llvm.riscv.vunzipo(
@@ -449,24 +241,11 @@ define <vscale x 2 x i64> @test_vunzipo_i64m2(<vscale x 2 x i64> %passthru, <vsc
ret <vscale x 2 x i64> %a
}
-define <vscale x 2 x i64> @test_vunzipo_mask_i64m2(<vscale x 2 x i64> %passthru, <vscale x 4 x i64> %arg1, <vscale x 2 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_i64m2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v12, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 2 x i64> @llvm.riscv.vunzipo.mask(
- <vscale x 2 x i64> %passthru,
- <vscale x 4 x i64> %arg1,
- <vscale x 2 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 2 x i64> %a
-}
define <vscale x 4 x i64> @test_vunzipo_i64m4(<vscale x 4 x i64> %passthru, <vscale x 8 x i64> %arg1, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_i64m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, ma
; CHECK-NEXT: vunzipo.v v8, v16
; CHECK-NEXT: ret
%a = call <vscale x 4 x i64> @llvm.riscv.vunzipo(
@@ -476,19 +255,6 @@ define <vscale x 4 x i64> @test_vunzipo_i64m4(<vscale x 4 x i64> %passthru, <vsc
ret <vscale x 4 x i64> %a
}
-define <vscale x 4 x i64> @test_vunzipo_mask_i64m4(<vscale x 4 x i64> %passthru, <vscale x 8 x i64> %arg1, <vscale x 4 x i1> %mask, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_i64m4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v16, v0.t
-; CHECK-NEXT: ret
- %a = call <vscale x 4 x i64> @llvm.riscv.vunzipo.mask(
- <vscale x 4 x i64> %passthru,
- <vscale x 8 x i64> %arg1,
- <vscale x 4 x i1> %mask,
- iXLen %vl, iXLen 1)
- ret <vscale x 4 x i64> %a
-}
; Floating-point types
@@ -496,7 +262,7 @@ define <vscale x 4 x i64> @test_vunzipo_mask_i64m4(<vscale x 4 x i64> %passthru,
define <vscale x 1 x half> @test_vunzipo_f16mf4(<vscale x 1 x half> %passthru, <vscale x 2 x half> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_f16mf4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
; CHECK-NEXT: vunzipo.v v8, v9
; CHECK-NEXT: ret
%r = call <vscale x 1 x half> @llvm.riscv.vunzipo(
@@ -506,24 +272,11 @@ define <vscale x 1 x half> @test_vunzipo_f16mf4(<vscale x 1 x half> %passthru, <
ret <vscale x 1 x half> %r
}
-define <vscale x 1 x half> @test_vunzipo_mask_f16mf4(<vscale x 1 x half> %passthru, <vscale x 2 x half> %src, <vscale x 1 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_f16mf4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v9, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 1 x half> @llvm.riscv.vunzipo.mask(
- <vscale x 1 x half> %passthru,
- <vscale x 2 x half> %src,
- <vscale x 1 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 1 x half> %r
-}
define <vscale x 2 x half> @test_vunzipo_f16mf2(<vscale x 2 x half> %passthru, <vscale x 4 x half> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_f16mf2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: vunzipo.v v8, v9
; CHECK-NEXT: ret
%r = call <vscale x 2 x half> @llvm.riscv.vunzipo(
@@ -533,24 +286,11 @@ define <vscale x 2 x half> @test_vunzipo_f16mf2(<vscale x 2 x half> %passthru, <
ret <vscale x 2 x half> %r
}
-define <vscale x 2 x half> @test_vunzipo_mask_f16mf2(<vscale x 2 x half> %passthru, <vscale x 4 x half> %src, <vscale x 2 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_f16mf2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v9, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 2 x half> @llvm.riscv.vunzipo.mask(
- <vscale x 2 x half> %passthru,
- <vscale x 4 x half> %src,
- <vscale x 2 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 2 x half> %r
-}
define <vscale x 4 x half> @test_vunzipo_f16m1(<vscale x 4 x half> %passthru, <vscale x 8 x half> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_f16m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
; CHECK-NEXT: vunzipo.v v8, v10
; CHECK-NEXT: ret
%r = call <vscale x 4 x half> @llvm.riscv.vunzipo(
@@ -560,24 +300,11 @@ define <vscale x 4 x half> @test_vunzipo_f16m1(<vscale x 4 x half> %passthru, <v
ret <vscale x 4 x half> %r
}
-define <vscale x 4 x half> @test_vunzipo_mask_f16m1(<vscale x 4 x half> %passthru, <vscale x 8 x half> %src, <vscale x 4 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_f16m1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v10, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 4 x half> @llvm.riscv.vunzipo.mask(
- <vscale x 4 x half> %passthru,
- <vscale x 8 x half> %src,
- <vscale x 4 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 4 x half> %r
-}
define <vscale x 8 x half> @test_vunzipo_f16m2(<vscale x 8 x half> %passthru, <vscale x 16 x half> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_f16m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
; CHECK-NEXT: vunzipo.v v8, v12
; CHECK-NEXT: ret
%r = call <vscale x 8 x half> @llvm.riscv.vunzipo(
@@ -587,24 +314,11 @@ define <vscale x 8 x half> @test_vunzipo_f16m2(<vscale x 8 x half> %passthru, <v
ret <vscale x 8 x half> %r
}
-define <vscale x 8 x half> @test_vunzipo_mask_f16m2(<vscale x 8 x half> %passthru, <vscale x 16 x half> %src, <vscale x 8 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_f16m2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v12, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 8 x half> @llvm.riscv.vunzipo.mask(
- <vscale x 8 x half> %passthru,
- <vscale x 16 x half> %src,
- <vscale x 8 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 8 x half> %r
-}
define <vscale x 16 x half> @test_vunzipo_f16m4(<vscale x 16 x half> %passthru, <vscale x 32 x half> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_f16m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma
; CHECK-NEXT: vunzipo.v v8, v16
; CHECK-NEXT: ret
%r = call <vscale x 16 x half> @llvm.riscv.vunzipo(
@@ -614,25 +328,12 @@ define <vscale x 16 x half> @test_vunzipo_f16m4(<vscale x 16 x half> %passthru,
ret <vscale x 16 x half> %r
}
-define <vscale x 16 x half> @test_vunzipo_mask_f16m4(<vscale x 16 x half> %passthru, <vscale x 32 x half> %src, <vscale x 16 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_f16m4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v16, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 16 x half> @llvm.riscv.vunzipo.mask(
- <vscale x 16 x half> %passthru,
- <vscale x 32 x half> %src,
- <vscale x 16 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 16 x half> %r
-}
; bf16
define <vscale x 1 x bfloat> @test_vunzipo_bf16mf4(<vscale x 1 x bfloat> %passthru, <vscale x 2 x bfloat> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_bf16mf4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
; CHECK-NEXT: vunzipo.v v8, v9
; CHECK-NEXT: ret
%r = call <vscale x 1 x bfloat> @llvm.riscv.vunzipo(
@@ -642,24 +343,11 @@ define <vscale x 1 x bfloat> @test_vunzipo_bf16mf4(<vscale x 1 x bfloat> %passth
ret <vscale x 1 x bfloat> %r
}
-define <vscale x 1 x bfloat> @test_vunzipo_mask_bf16mf4(<vscale x 1 x bfloat> %passthru, <vscale x 2 x bfloat> %src, <vscale x 1 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_bf16mf4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v9, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 1 x bfloat> @llvm.riscv.vunzipo.mask(
- <vscale x 1 x bfloat> %passthru,
- <vscale x 2 x bfloat> %src,
- <vscale x 1 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 1 x bfloat> %r
-}
define <vscale x 2 x bfloat> @test_vunzipo_bf16mf2(<vscale x 2 x bfloat> %passthru, <vscale x 4 x bfloat> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_bf16mf2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: vunzipo.v v8, v9
; CHECK-NEXT: ret
%r = call <vscale x 2 x bfloat> @llvm.riscv.vunzipo(
@@ -669,24 +357,11 @@ define <vscale x 2 x bfloat> @test_vunzipo_bf16mf2(<vscale x 2 x bfloat> %passth
ret <vscale x 2 x bfloat> %r
}
-define <vscale x 2 x bfloat> @test_vunzipo_mask_bf16mf2(<vscale x 2 x bfloat> %passthru, <vscale x 4 x bfloat> %src, <vscale x 2 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_bf16mf2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v9, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 2 x bfloat> @llvm.riscv.vunzipo.mask(
- <vscale x 2 x bfloat> %passthru,
- <vscale x 4 x bfloat> %src,
- <vscale x 2 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 2 x bfloat> %r
-}
define <vscale x 4 x bfloat> @test_vunzipo_bf16m1(<vscale x 4 x bfloat> %passthru, <vscale x 8 x bfloat> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_bf16m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
; CHECK-NEXT: vunzipo.v v8, v10
; CHECK-NEXT: ret
%r = call <vscale x 4 x bfloat> @llvm.riscv.vunzipo(
@@ -696,24 +371,11 @@ define <vscale x 4 x bfloat> @test_vunzipo_bf16m1(<vscale x 4 x bfloat> %passthr
ret <vscale x 4 x bfloat> %r
}
-define <vscale x 4 x bfloat> @test_vunzipo_mask_bf16m1(<vscale x 4 x bfloat> %passthru, <vscale x 8 x bfloat> %src, <vscale x 4 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_bf16m1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v10, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 4 x bfloat> @llvm.riscv.vunzipo.mask(
- <vscale x 4 x bfloat> %passthru,
- <vscale x 8 x bfloat> %src,
- <vscale x 4 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 4 x bfloat> %r
-}
define <vscale x 8 x bfloat> @test_vunzipo_bf16m2(<vscale x 8 x bfloat> %passthru, <vscale x 16 x bfloat> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_bf16m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
; CHECK-NEXT: vunzipo.v v8, v12
; CHECK-NEXT: ret
%r = call <vscale x 8 x bfloat> @llvm.riscv.vunzipo(
@@ -723,24 +385,11 @@ define <vscale x 8 x bfloat> @test_vunzipo_bf16m2(<vscale x 8 x bfloat> %passthr
ret <vscale x 8 x bfloat> %r
}
-define <vscale x 8 x bfloat> @test_vunzipo_mask_bf16m2(<vscale x 8 x bfloat> %passthru, <vscale x 16 x bfloat> %src, <vscale x 8 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_bf16m2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v12, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 8 x bfloat> @llvm.riscv.vunzipo.mask(
- <vscale x 8 x bfloat> %passthru,
- <vscale x 16 x bfloat> %src,
- <vscale x 8 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 8 x bfloat> %r
-}
define <vscale x 16 x bfloat> @test_vunzipo_bf16m4(<vscale x 16 x bfloat> %passthru, <vscale x 32 x bfloat> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_bf16m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma
; CHECK-NEXT: vunzipo.v v8, v16
; CHECK-NEXT: ret
%r = call <vscale x 16 x bfloat> @llvm.riscv.vunzipo(
@@ -750,25 +399,12 @@ define <vscale x 16 x bfloat> @test_vunzipo_bf16m4(<vscale x 16 x bfloat> %passt
ret <vscale x 16 x bfloat> %r
}
-define <vscale x 16 x bfloat> @test_vunzipo_mask_bf16m4(<vscale x 16 x bfloat> %passthru, <vscale x 32 x bfloat> %src, <vscale x 16 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_bf16m4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v16, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 16 x bfloat> @llvm.riscv.vunzipo.mask(
- <vscale x 16 x bfloat> %passthru,
- <vscale x 32 x bfloat> %src,
- <vscale x 16 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 16 x bfloat> %r
-}
; f32
define <vscale x 1 x float> @test_vunzipo_f32mf2(<vscale x 1 x float> %passthru, <vscale x 2 x float> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_f32mf2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
; CHECK-NEXT: vunzipo.v v8, v9
; CHECK-NEXT: ret
%r = call <vscale x 1 x float> @llvm.riscv.vunzipo(
@@ -778,24 +414,11 @@ define <vscale x 1 x float> @test_vunzipo_f32mf2(<vscale x 1 x float> %passthru,
ret <vscale x 1 x float> %r
}
-define <vscale x 1 x float> @test_vunzipo_mask_f32mf2(<vscale x 1 x float> %passthru, <vscale x 2 x float> %src, <vscale x 1 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_f32mf2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v9, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 1 x float> @llvm.riscv.vunzipo.mask(
- <vscale x 1 x float> %passthru,
- <vscale x 2 x float> %src,
- <vscale x 1 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 1 x float> %r
-}
define <vscale x 2 x float> @test_vunzipo_f32m1(<vscale x 2 x float> %passthru, <vscale x 4 x float> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_f32m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
; CHECK-NEXT: vunzipo.v v8, v10
; CHECK-NEXT: ret
%r = call <vscale x 2 x float> @llvm.riscv.vunzipo(
@@ -805,24 +428,11 @@ define <vscale x 2 x float> @test_vunzipo_f32m1(<vscale x 2 x float> %passthru,
ret <vscale x 2 x float> %r
}
-define <vscale x 2 x float> @test_vunzipo_mask_f32m1(<vscale x 2 x float> %passthru, <vscale x 4 x float> %src, <vscale x 2 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_f32m1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v10, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 2 x float> @llvm.riscv.vunzipo.mask(
- <vscale x 2 x float> %passthru,
- <vscale x 4 x float> %src,
- <vscale x 2 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 2 x float> %r
-}
define <vscale x 4 x float> @test_vunzipo_f32m2(<vscale x 4 x float> %passthru, <vscale x 8 x float> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_f32m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
; CHECK-NEXT: vunzipo.v v8, v12
; CHECK-NEXT: ret
%r = call <vscale x 4 x float> @llvm.riscv.vunzipo(
@@ -832,24 +442,11 @@ define <vscale x 4 x float> @test_vunzipo_f32m2(<vscale x 4 x float> %passthru,
ret <vscale x 4 x float> %r
}
-define <vscale x 4 x float> @test_vunzipo_mask_f32m2(<vscale x 4 x float> %passthru, <vscale x 8 x float> %src, <vscale x 4 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_f32m2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v12, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 4 x float> @llvm.riscv.vunzipo.mask(
- <vscale x 4 x float> %passthru,
- <vscale x 8 x float> %src,
- <vscale x 4 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 4 x float> %r
-}
define <vscale x 8 x float> @test_vunzipo_f32m4(<vscale x 8 x float> %passthru, <vscale x 16 x float> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_f32m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, ma
; CHECK-NEXT: vunzipo.v v8, v16
; CHECK-NEXT: ret
%r = call <vscale x 8 x float> @llvm.riscv.vunzipo(
@@ -859,25 +456,12 @@ define <vscale x 8 x float> @test_vunzipo_f32m4(<vscale x 8 x float> %passthru,
ret <vscale x 8 x float> %r
}
-define <vscale x 8 x float> @test_vunzipo_mask_f32m4(<vscale x 8 x float> %passthru, <vscale x 16 x float> %src, <vscale x 8 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_f32m4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v16, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 8 x float> @llvm.riscv.vunzipo.mask(
- <vscale x 8 x float> %passthru,
- <vscale x 16 x float> %src,
- <vscale x 8 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 8 x float> %r
-}
; f64
define <vscale x 1 x double> @test_vunzipo_f64m1(<vscale x 1 x double> %passthru, <vscale x 2 x double> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_f64m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma
; CHECK-NEXT: vunzipo.v v8, v10
; CHECK-NEXT: ret
%r = call <vscale x 1 x double> @llvm.riscv.vunzipo(
@@ -887,24 +471,11 @@ define <vscale x 1 x double> @test_vunzipo_f64m1(<vscale x 1 x double> %passthru
ret <vscale x 1 x double> %r
}
-define <vscale x 1 x double> @test_vunzipo_mask_f64m1(<vscale x 1 x double> %passthru, <vscale x 2 x double> %src, <vscale x 1 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_f64m1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v10, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 1 x double> @llvm.riscv.vunzipo.mask(
- <vscale x 1 x double> %passthru,
- <vscale x 2 x double> %src,
- <vscale x 1 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 1 x double> %r
-}
define <vscale x 2 x double> @test_vunzipo_f64m2(<vscale x 2 x double> %passthru, <vscale x 4 x double> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_f64m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma
; CHECK-NEXT: vunzipo.v v8, v12
; CHECK-NEXT: ret
%r = call <vscale x 2 x double> @llvm.riscv.vunzipo(
@@ -914,24 +485,11 @@ define <vscale x 2 x double> @test_vunzipo_f64m2(<vscale x 2 x double> %passthru
ret <vscale x 2 x double> %r
}
-define <vscale x 2 x double> @test_vunzipo_mask_f64m2(<vscale x 2 x double> %passthru, <vscale x 4 x double> %src, <vscale x 2 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_f64m2:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v12, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 2 x double> @llvm.riscv.vunzipo.mask(
- <vscale x 2 x double> %passthru,
- <vscale x 4 x double> %src,
- <vscale x 2 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 2 x double> %r
-}
define <vscale x 4 x double> @test_vunzipo_f64m4(<vscale x 4 x double> %passthru, <vscale x 8 x double> %src, iXLen %vl) nounwind {
; CHECK-LABEL: test_vunzipo_f64m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, ma
; CHECK-NEXT: vunzipo.v v8, v16
; CHECK-NEXT: ret
%r = call <vscale x 4 x double> @llvm.riscv.vunzipo(
@@ -941,19 +499,6 @@ define <vscale x 4 x double> @test_vunzipo_f64m4(<vscale x 4 x double> %passthru
ret <vscale x 4 x double> %r
}
-define <vscale x 4 x double> @test_vunzipo_mask_f64m4(<vscale x 4 x double> %passthru, <vscale x 8 x double> %src, <vscale x 4 x i1> %m, iXLen %vl) nounwind {
-; CHECK-LABEL: test_vunzipo_mask_f64m4:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vunzipo.v v8, v16, v0.t
-; CHECK-NEXT: ret
- %r = call <vscale x 4 x double> @llvm.riscv.vunzipo.mask(
- <vscale x 4 x double> %passthru,
- <vscale x 8 x double> %src,
- <vscale x 4 x i1> %m,
- iXLen %vl, iXLen 1)
- ret <vscale x 4 x double> %r
-}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; RV32: {{.*}}
; RV64: {{.*}}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vzip.ll b/llvm/test/CodeGen/RISCV/rvv/vzip.ll
index 36ea02f78065e..87e9f446fc28c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vzip.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vzip.ll
@@ -7,7 +7,7 @@
define <vscale x 2 x i8> @test_vzip_vv_i8mf4(<vscale x 2 x i8> %passthru, <vscale x 1 x i8> %arg1, <vscale x 1 x i8> %arg2, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_i8mf4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, ma
; CHECK-NEXT: vzip.vv v8, v9, v10
; CHECK-NEXT: ret
%a = call <vscale x 2 x i8> @llvm.riscv.vzip(
@@ -18,17 +18,17 @@ define <vscale x 2 x i8> @test_vzip_vv_i8mf4(<vscale x 2 x i8> %passthru, <vscal
ret <vscale x 2 x i8> %a
}
-define <vscale x 2 x i8> @test_vzip_vv_mask_i8mf4(<vscale x 2 x i8> %passthru, <vscale x 1 x i8> %arg1, <vscale x 1 x i8> %arg2, <vscale x 1 x i1> %mask, iXLen %vl) nounwind {
+define <vscale x 2 x i8> @test_vzip_vv_mask_i8mf4(<vscale x 2 x i8> %passthru, <vscale x 1 x i8> %arg1, <vscale x 1 x i8> %arg2, <vscale x 2 x i1> %mask, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_mask_i8mf4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vzip.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 2 x i8> @llvm.riscv.vzip.mask(
<vscale x 2 x i8> %passthru,
<vscale x 1 x i8> %arg1,
<vscale x 1 x i8> %arg2,
- <vscale x 1 x i1> %mask,
+ <vscale x 2 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 2 x i8> %a
}
@@ -36,7 +36,7 @@ define <vscale x 2 x i8> @test_vzip_vv_mask_i8mf4(<vscale x 2 x i8> %passthru, <
define <vscale x 4 x i8> @test_vzip_vv_i8mf2(<vscale x 4 x i8> %passthru, <vscale x 2 x i8> %arg1, <vscale x 2 x i8> %arg2, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_i8mf2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma
; CHECK-NEXT: vzip.vv v8, v9, v10
; CHECK-NEXT: ret
%a = call <vscale x 4 x i8> @llvm.riscv.vzip(
@@ -47,17 +47,17 @@ define <vscale x 4 x i8> @test_vzip_vv_i8mf2(<vscale x 4 x i8> %passthru, <vscal
ret <vscale x 4 x i8> %a
}
-define <vscale x 4 x i8> @test_vzip_vv_mask_i8mf2(<vscale x 4 x i8> %passthru, <vscale x 2 x i8> %arg1, <vscale x 2 x i8> %arg2, <vscale x 2 x i1> %mask, iXLen %vl) nounwind {
+define <vscale x 4 x i8> @test_vzip_vv_mask_i8mf2(<vscale x 4 x i8> %passthru, <vscale x 2 x i8> %arg1, <vscale x 2 x i8> %arg2, <vscale x 4 x i1> %mask, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_mask_i8mf2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vzip.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 4 x i8> @llvm.riscv.vzip.mask(
<vscale x 4 x i8> %passthru,
<vscale x 2 x i8> %arg1,
<vscale x 2 x i8> %arg2,
- <vscale x 2 x i1> %mask,
+ <vscale x 4 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 4 x i8> %a
}
@@ -65,7 +65,7 @@ define <vscale x 4 x i8> @test_vzip_vv_mask_i8mf2(<vscale x 4 x i8> %passthru, <
define <vscale x 8 x i8> @test_vzip_vv_i8m1(<vscale x 8 x i8> %passthru, <vscale x 4 x i8> %arg1, <vscale x 4 x i8> %arg2, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_i8m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
; CHECK-NEXT: vzip.vv v8, v9, v10
; CHECK-NEXT: ret
%a = call <vscale x 8 x i8> @llvm.riscv.vzip(
@@ -76,17 +76,17 @@ define <vscale x 8 x i8> @test_vzip_vv_i8m1(<vscale x 8 x i8> %passthru, <vscale
ret <vscale x 8 x i8> %a
}
-define <vscale x 8 x i8> @test_vzip_vv_mask_i8m1(<vscale x 8 x i8> %passthru, <vscale x 4 x i8> %arg1, <vscale x 4 x i8> %arg2, <vscale x 4 x i1> %mask, iXLen %vl) nounwind {
+define <vscale x 8 x i8> @test_vzip_vv_mask_i8m1(<vscale x 8 x i8> %passthru, <vscale x 4 x i8> %arg1, <vscale x 4 x i8> %arg2, <vscale x 8 x i1> %mask, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_mask_i8m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vzip.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 8 x i8> @llvm.riscv.vzip.mask(
<vscale x 8 x i8> %passthru,
<vscale x 4 x i8> %arg1,
<vscale x 4 x i8> %arg2,
- <vscale x 4 x i1> %mask,
+ <vscale x 8 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 8 x i8> %a
}
@@ -94,7 +94,7 @@ define <vscale x 8 x i8> @test_vzip_vv_mask_i8m1(<vscale x 8 x i8> %passthru, <v
define <vscale x 16 x i8> @test_vzip_vv_i8m2(<vscale x 16 x i8> %passthru, <vscale x 8 x i8> %arg1, <vscale x 8 x i8> %arg2, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_i8m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, ma
; CHECK-NEXT: vzip.vv v8, v10, v11
; CHECK-NEXT: ret
%a = call <vscale x 16 x i8> @llvm.riscv.vzip(
@@ -105,17 +105,17 @@ define <vscale x 16 x i8> @test_vzip_vv_i8m2(<vscale x 16 x i8> %passthru, <vsca
ret <vscale x 16 x i8> %a
}
-define <vscale x 16 x i8> @test_vzip_vv_mask_i8m2(<vscale x 16 x i8> %passthru, <vscale x 8 x i8> %arg1, <vscale x 8 x i8> %arg2, <vscale x 8 x i1> %mask, iXLen %vl) nounwind {
+define <vscale x 16 x i8> @test_vzip_vv_mask_i8m2(<vscale x 16 x i8> %passthru, <vscale x 8 x i8> %arg1, <vscale x 8 x i8> %arg2, <vscale x 16 x i1> %mask, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_mask_i8m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vzip.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 16 x i8> @llvm.riscv.vzip.mask(
<vscale x 16 x i8> %passthru,
<vscale x 8 x i8> %arg1,
<vscale x 8 x i8> %arg2,
- <vscale x 8 x i1> %mask,
+ <vscale x 16 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 16 x i8> %a
}
@@ -123,7 +123,7 @@ define <vscale x 16 x i8> @test_vzip_vv_mask_i8m2(<vscale x 16 x i8> %passthru,
define <vscale x 32 x i8> @test_vzip_vv_i8m4(<vscale x 32 x i8> %passthru, <vscale x 16 x i8> %arg1, <vscale x 16 x i8> %arg2, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_i8m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, ma
; CHECK-NEXT: vzip.vv v8, v12, v14
; CHECK-NEXT: ret
%a = call <vscale x 32 x i8> @llvm.riscv.vzip(
@@ -134,17 +134,17 @@ define <vscale x 32 x i8> @test_vzip_vv_i8m4(<vscale x 32 x i8> %passthru, <vsca
ret <vscale x 32 x i8> %a
}
-define <vscale x 32 x i8> @test_vzip_vv_mask_i8m4(<vscale x 32 x i8> %passthru, <vscale x 16 x i8> %arg1, <vscale x 16 x i8> %arg2, <vscale x 16 x i1> %mask, iXLen %vl) nounwind {
+define <vscale x 32 x i8> @test_vzip_vv_mask_i8m4(<vscale x 32 x i8> %passthru, <vscale x 16 x i8> %arg1, <vscale x 16 x i8> %arg2, <vscale x 32 x i1> %mask, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_mask_i8m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vzip.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 32 x i8> @llvm.riscv.vzip.mask(
<vscale x 32 x i8> %passthru,
<vscale x 16 x i8> %arg1,
<vscale x 16 x i8> %arg2,
- <vscale x 16 x i1> %mask,
+ <vscale x 32 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 32 x i8> %a
}
@@ -152,7 +152,7 @@ define <vscale x 32 x i8> @test_vzip_vv_mask_i8m4(<vscale x 32 x i8> %passthru,
define <vscale x 64 x i8> @test_vzip_vv_i8m8(<vscale x 64 x i8> %passthru, <vscale x 32 x i8> %arg1, <vscale x 32 x i8> %arg2, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_i8m8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, ma
; CHECK-NEXT: vzip.vv v8, v16, v20
; CHECK-NEXT: ret
%a = call <vscale x 64 x i8> @llvm.riscv.vzip(
@@ -163,17 +163,17 @@ define <vscale x 64 x i8> @test_vzip_vv_i8m8(<vscale x 64 x i8> %passthru, <vsca
ret <vscale x 64 x i8> %a
}
-define <vscale x 64 x i8> @test_vzip_vv_mask_i8m8(<vscale x 64 x i8> %passthru, <vscale x 32 x i8> %arg1, <vscale x 32 x i8> %arg2, <vscale x 32 x i1> %mask, iXLen %vl) nounwind {
+define <vscale x 64 x i8> @test_vzip_vv_mask_i8m8(<vscale x 64 x i8> %passthru, <vscale x 32 x i8> %arg1, <vscale x 32 x i8> %arg2, <vscale x 64 x i1> %mask, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_mask_i8m8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vzip.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 64 x i8> @llvm.riscv.vzip.mask(
<vscale x 64 x i8> %passthru,
<vscale x 32 x i8> %arg1,
<vscale x 32 x i8> %arg2,
- <vscale x 32 x i1> %mask,
+ <vscale x 64 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 64 x i8> %a
}
@@ -181,7 +181,7 @@ define <vscale x 64 x i8> @test_vzip_vv_mask_i8m8(<vscale x 64 x i8> %passthru,
define <vscale x 2 x i16> @test_vzip_vv_i16mf2(<vscale x 2 x i16> %passthru, <vscale x 1 x i16> %arg1, <vscale x 1 x i16> %arg2, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_i16mf2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
; CHECK-NEXT: vzip.vv v8, v9, v10
; CHECK-NEXT: ret
%a = call <vscale x 2 x i16> @llvm.riscv.vzip(
@@ -192,17 +192,17 @@ define <vscale x 2 x i16> @test_vzip_vv_i16mf2(<vscale x 2 x i16> %passthru, <vs
ret <vscale x 2 x i16> %a
}
-define <vscale x 2 x i16> @test_vzip_vv_mask_i16mf2(<vscale x 2 x i16> %passthru, <vscale x 1 x i16> %arg1, <vscale x 1 x i16> %arg2, <vscale x 1 x i1> %mask, iXLen %vl) nounwind {
+define <vscale x 2 x i16> @test_vzip_vv_mask_i16mf2(<vscale x 2 x i16> %passthru, <vscale x 1 x i16> %arg1, <vscale x 1 x i16> %arg2, <vscale x 2 x i1> %mask, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_mask_i16mf2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vzip.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 2 x i16> @llvm.riscv.vzip.mask(
<vscale x 2 x i16> %passthru,
<vscale x 1 x i16> %arg1,
<vscale x 1 x i16> %arg2,
- <vscale x 1 x i1> %mask,
+ <vscale x 2 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 2 x i16> %a
}
@@ -210,7 +210,7 @@ define <vscale x 2 x i16> @test_vzip_vv_mask_i16mf2(<vscale x 2 x i16> %passthru
define <vscale x 4 x i16> @test_vzip_vv_i16m1(<vscale x 4 x i16> %passthru, <vscale x 2 x i16> %arg1, <vscale x 2 x i16> %arg2, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_i16m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: vzip.vv v8, v9, v10
; CHECK-NEXT: ret
%a = call <vscale x 4 x i16> @llvm.riscv.vzip(
@@ -221,17 +221,17 @@ define <vscale x 4 x i16> @test_vzip_vv_i16m1(<vscale x 4 x i16> %passthru, <vsc
ret <vscale x 4 x i16> %a
}
-define <vscale x 4 x i16> @test_vzip_vv_mask_i16m1(<vscale x 4 x i16> %passthru, <vscale x 2 x i16> %arg1, <vscale x 2 x i16> %arg2, <vscale x 2 x i1> %mask, iXLen %vl) nounwind {
+define <vscale x 4 x i16> @test_vzip_vv_mask_i16m1(<vscale x 4 x i16> %passthru, <vscale x 2 x i16> %arg1, <vscale x 2 x i16> %arg2, <vscale x 4 x i1> %mask, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_mask_i16m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vzip.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 4 x i16> @llvm.riscv.vzip.mask(
<vscale x 4 x i16> %passthru,
<vscale x 2 x i16> %arg1,
<vscale x 2 x i16> %arg2,
- <vscale x 2 x i1> %mask,
+ <vscale x 4 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 4 x i16> %a
}
@@ -239,7 +239,7 @@ define <vscale x 4 x i16> @test_vzip_vv_mask_i16m1(<vscale x 4 x i16> %passthru,
define <vscale x 8 x i16> @test_vzip_vv_i16m2(<vscale x 8 x i16> %passthru, <vscale x 4 x i16> %arg1, <vscale x 4 x i16> %arg2, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_i16m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
; CHECK-NEXT: vzip.vv v8, v10, v11
; CHECK-NEXT: ret
%a = call <vscale x 8 x i16> @llvm.riscv.vzip(
@@ -250,17 +250,17 @@ define <vscale x 8 x i16> @test_vzip_vv_i16m2(<vscale x 8 x i16> %passthru, <vsc
ret <vscale x 8 x i16> %a
}
-define <vscale x 8 x i16> @test_vzip_vv_mask_i16m2(<vscale x 8 x i16> %passthru, <vscale x 4 x i16> %arg1, <vscale x 4 x i16> %arg2, <vscale x 4 x i1> %mask, iXLen %vl) nounwind {
+define <vscale x 8 x i16> @test_vzip_vv_mask_i16m2(<vscale x 8 x i16> %passthru, <vscale x 4 x i16> %arg1, <vscale x 4 x i16> %arg2, <vscale x 8 x i1> %mask, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_mask_i16m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vzip.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 8 x i16> @llvm.riscv.vzip.mask(
<vscale x 8 x i16> %passthru,
<vscale x 4 x i16> %arg1,
<vscale x 4 x i16> %arg2,
- <vscale x 4 x i1> %mask,
+ <vscale x 8 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 8 x i16> %a
}
@@ -268,7 +268,7 @@ define <vscale x 8 x i16> @test_vzip_vv_mask_i16m2(<vscale x 8 x i16> %passthru,
define <vscale x 16 x i16> @test_vzip_vv_i16m4(<vscale x 16 x i16> %passthru, <vscale x 8 x i16> %arg1, <vscale x 8 x i16> %arg2, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_i16m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
; CHECK-NEXT: vzip.vv v8, v12, v14
; CHECK-NEXT: ret
%a = call <vscale x 16 x i16> @llvm.riscv.vzip(
@@ -279,17 +279,17 @@ define <vscale x 16 x i16> @test_vzip_vv_i16m4(<vscale x 16 x i16> %passthru, <v
ret <vscale x 16 x i16> %a
}
-define <vscale x 16 x i16> @test_vzip_vv_mask_i16m4(<vscale x 16 x i16> %passthru, <vscale x 8 x i16> %arg1, <vscale x 8 x i16> %arg2, <vscale x 8 x i1> %mask, iXLen %vl) nounwind {
+define <vscale x 16 x i16> @test_vzip_vv_mask_i16m4(<vscale x 16 x i16> %passthru, <vscale x 8 x i16> %arg1, <vscale x 8 x i16> %arg2, <vscale x 16 x i1> %mask, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_mask_i16m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vzip.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 16 x i16> @llvm.riscv.vzip.mask(
<vscale x 16 x i16> %passthru,
<vscale x 8 x i16> %arg1,
<vscale x 8 x i16> %arg2,
- <vscale x 8 x i1> %mask,
+ <vscale x 16 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 16 x i16> %a
}
@@ -297,7 +297,7 @@ define <vscale x 16 x i16> @test_vzip_vv_mask_i16m4(<vscale x 16 x i16> %passthr
define <vscale x 32 x i16> @test_vzip_vv_i16m8(<vscale x 32 x i16> %passthru, <vscale x 16 x i16> %arg1, <vscale x 16 x i16> %arg2, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_i16m8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma
; CHECK-NEXT: vzip.vv v8, v16, v20
; CHECK-NEXT: ret
%a = call <vscale x 32 x i16> @llvm.riscv.vzip(
@@ -308,17 +308,17 @@ define <vscale x 32 x i16> @test_vzip_vv_i16m8(<vscale x 32 x i16> %passthru, <v
ret <vscale x 32 x i16> %a
}
-define <vscale x 32 x i16> @test_vzip_vv_mask_i16m8(<vscale x 32 x i16> %passthru, <vscale x 16 x i16> %arg1, <vscale x 16 x i16> %arg2, <vscale x 16 x i1> %mask, iXLen %vl) nounwind {
+define <vscale x 32 x i16> @test_vzip_vv_mask_i16m8(<vscale x 32 x i16> %passthru, <vscale x 16 x i16> %arg1, <vscale x 16 x i16> %arg2, <vscale x 32 x i1> %mask, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_mask_i16m8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vzip.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 32 x i16> @llvm.riscv.vzip.mask(
<vscale x 32 x i16> %passthru,
<vscale x 16 x i16> %arg1,
<vscale x 16 x i16> %arg2,
- <vscale x 16 x i1> %mask,
+ <vscale x 32 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 32 x i16> %a
}
@@ -326,7 +326,7 @@ define <vscale x 32 x i16> @test_vzip_vv_mask_i16m8(<vscale x 32 x i16> %passthr
define <vscale x 2 x i32> @test_vzip_vv_i32m1(<vscale x 2 x i32> %passthru, <vscale x 1 x i32> %arg1, <vscale x 1 x i32> %arg2, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_i32m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
; CHECK-NEXT: vzip.vv v8, v9, v10
; CHECK-NEXT: ret
%a = call <vscale x 2 x i32> @llvm.riscv.vzip(
@@ -337,17 +337,17 @@ define <vscale x 2 x i32> @test_vzip_vv_i32m1(<vscale x 2 x i32> %passthru, <vsc
ret <vscale x 2 x i32> %a
}
-define <vscale x 2 x i32> @test_vzip_vv_mask_i32m1(<vscale x 2 x i32> %passthru, <vscale x 1 x i32> %arg1, <vscale x 1 x i32> %arg2, <vscale x 1 x i1> %mask, iXLen %vl) nounwind {
+define <vscale x 2 x i32> @test_vzip_vv_mask_i32m1(<vscale x 2 x i32> %passthru, <vscale x 1 x i32> %arg1, <vscale x 1 x i32> %arg2, <vscale x 2 x i1> %mask, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_mask_i32m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vzip.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 2 x i32> @llvm.riscv.vzip.mask(
<vscale x 2 x i32> %passthru,
<vscale x 1 x i32> %arg1,
<vscale x 1 x i32> %arg2,
- <vscale x 1 x i1> %mask,
+ <vscale x 2 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 2 x i32> %a
}
@@ -355,7 +355,7 @@ define <vscale x 2 x i32> @test_vzip_vv_mask_i32m1(<vscale x 2 x i32> %passthru,
define <vscale x 4 x i32> @test_vzip_vv_i32m2(<vscale x 4 x i32> %passthru, <vscale x 2 x i32> %arg1, <vscale x 2 x i32> %arg2, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_i32m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
; CHECK-NEXT: vzip.vv v8, v10, v11
; CHECK-NEXT: ret
%a = call <vscale x 4 x i32> @llvm.riscv.vzip(
@@ -366,17 +366,17 @@ define <vscale x 4 x i32> @test_vzip_vv_i32m2(<vscale x 4 x i32> %passthru, <vsc
ret <vscale x 4 x i32> %a
}
-define <vscale x 4 x i32> @test_vzip_vv_mask_i32m2(<vscale x 4 x i32> %passthru, <vscale x 2 x i32> %arg1, <vscale x 2 x i32> %arg2, <vscale x 2 x i1> %mask, iXLen %vl) nounwind {
+define <vscale x 4 x i32> @test_vzip_vv_mask_i32m2(<vscale x 4 x i32> %passthru, <vscale x 2 x i32> %arg1, <vscale x 2 x i32> %arg2, <vscale x 4 x i1> %mask, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_mask_i32m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vzip.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 4 x i32> @llvm.riscv.vzip.mask(
<vscale x 4 x i32> %passthru,
<vscale x 2 x i32> %arg1,
<vscale x 2 x i32> %arg2,
- <vscale x 2 x i1> %mask,
+ <vscale x 4 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 4 x i32> %a
}
@@ -384,7 +384,7 @@ define <vscale x 4 x i32> @test_vzip_vv_mask_i32m2(<vscale x 4 x i32> %passthru,
define <vscale x 8 x i32> @test_vzip_vv_i32m4(<vscale x 8 x i32> %passthru, <vscale x 4 x i32> %arg1, <vscale x 4 x i32> %arg2, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_i32m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
; CHECK-NEXT: vzip.vv v8, v12, v14
; CHECK-NEXT: ret
%a = call <vscale x 8 x i32> @llvm.riscv.vzip(
@@ -395,17 +395,17 @@ define <vscale x 8 x i32> @test_vzip_vv_i32m4(<vscale x 8 x i32> %passthru, <vsc
ret <vscale x 8 x i32> %a
}
-define <vscale x 8 x i32> @test_vzip_vv_mask_i32m4(<vscale x 8 x i32> %passthru, <vscale x 4 x i32> %arg1, <vscale x 4 x i32> %arg2, <vscale x 4 x i1> %mask, iXLen %vl) nounwind {
+define <vscale x 8 x i32> @test_vzip_vv_mask_i32m4(<vscale x 8 x i32> %passthru, <vscale x 4 x i32> %arg1, <vscale x 4 x i32> %arg2, <vscale x 8 x i1> %mask, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_mask_i32m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vzip.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 8 x i32> @llvm.riscv.vzip.mask(
<vscale x 8 x i32> %passthru,
<vscale x 4 x i32> %arg1,
<vscale x 4 x i32> %arg2,
- <vscale x 4 x i1> %mask,
+ <vscale x 8 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 8 x i32> %a
}
@@ -413,7 +413,7 @@ define <vscale x 8 x i32> @test_vzip_vv_mask_i32m4(<vscale x 8 x i32> %passthru,
define <vscale x 16 x i32> @test_vzip_vv_i32m8(<vscale x 16 x i32> %passthru, <vscale x 8 x i32> %arg1, <vscale x 8 x i32> %arg2, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_i32m8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, ma
; CHECK-NEXT: vzip.vv v8, v16, v20
; CHECK-NEXT: ret
%a = call <vscale x 16 x i32> @llvm.riscv.vzip(
@@ -424,17 +424,17 @@ define <vscale x 16 x i32> @test_vzip_vv_i32m8(<vscale x 16 x i32> %passthru, <v
ret <vscale x 16 x i32> %a
}
-define <vscale x 16 x i32> @test_vzip_vv_mask_i32m8(<vscale x 16 x i32> %passthru, <vscale x 8 x i32> %arg1, <vscale x 8 x i32> %arg2, <vscale x 8 x i1> %mask, iXLen %vl) nounwind {
+define <vscale x 16 x i32> @test_vzip_vv_mask_i32m8(<vscale x 16 x i32> %passthru, <vscale x 8 x i32> %arg1, <vscale x 8 x i32> %arg2, <vscale x 16 x i1> %mask, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_mask_i32m8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vzip.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 16 x i32> @llvm.riscv.vzip.mask(
<vscale x 16 x i32> %passthru,
<vscale x 8 x i32> %arg1,
<vscale x 8 x i32> %arg2,
- <vscale x 8 x i1> %mask,
+ <vscale x 16 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 16 x i32> %a
}
@@ -442,7 +442,7 @@ define <vscale x 16 x i32> @test_vzip_vv_mask_i32m8(<vscale x 16 x i32> %passthr
define <vscale x 2 x i64> @test_vzip_vv_i64m2(<vscale x 2 x i64> %passthru, <vscale x 1 x i64> %arg1, <vscale x 1 x i64> %arg2, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_i64m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma
; CHECK-NEXT: vzip.vv v8, v10, v11
; CHECK-NEXT: ret
%a = call <vscale x 2 x i64> @llvm.riscv.vzip(
@@ -453,17 +453,17 @@ define <vscale x 2 x i64> @test_vzip_vv_i64m2(<vscale x 2 x i64> %passthru, <vsc
ret <vscale x 2 x i64> %a
}
-define <vscale x 2 x i64> @test_vzip_vv_mask_i64m2(<vscale x 2 x i64> %passthru, <vscale x 1 x i64> %arg1, <vscale x 1 x i64> %arg2, <vscale x 1 x i1> %mask, iXLen %vl) nounwind {
+define <vscale x 2 x i64> @test_vzip_vv_mask_i64m2(<vscale x 2 x i64> %passthru, <vscale x 1 x i64> %arg1, <vscale x 1 x i64> %arg2, <vscale x 2 x i1> %mask, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_mask_i64m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vzip.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 2 x i64> @llvm.riscv.vzip.mask(
<vscale x 2 x i64> %passthru,
<vscale x 1 x i64> %arg1,
<vscale x 1 x i64> %arg2,
- <vscale x 1 x i1> %mask,
+ <vscale x 2 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 2 x i64> %a
}
@@ -471,7 +471,7 @@ define <vscale x 2 x i64> @test_vzip_vv_mask_i64m2(<vscale x 2 x i64> %passthru,
define <vscale x 4 x i64> @test_vzip_vv_i64m4(<vscale x 4 x i64> %passthru, <vscale x 2 x i64> %arg1, <vscale x 2 x i64> %arg2, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_i64m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma
; CHECK-NEXT: vzip.vv v8, v12, v14
; CHECK-NEXT: ret
%a = call <vscale x 4 x i64> @llvm.riscv.vzip(
@@ -482,17 +482,17 @@ define <vscale x 4 x i64> @test_vzip_vv_i64m4(<vscale x 4 x i64> %passthru, <vsc
ret <vscale x 4 x i64> %a
}
-define <vscale x 4 x i64> @test_vzip_vv_mask_i64m4(<vscale x 4 x i64> %passthru, <vscale x 2 x i64> %arg1, <vscale x 2 x i64> %arg2, <vscale x 2 x i1> %mask, iXLen %vl) nounwind {
+define <vscale x 4 x i64> @test_vzip_vv_mask_i64m4(<vscale x 4 x i64> %passthru, <vscale x 2 x i64> %arg1, <vscale x 2 x i64> %arg2, <vscale x 4 x i1> %mask, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_mask_i64m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vzip.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 4 x i64> @llvm.riscv.vzip.mask(
<vscale x 4 x i64> %passthru,
<vscale x 2 x i64> %arg1,
<vscale x 2 x i64> %arg2,
- <vscale x 2 x i1> %mask,
+ <vscale x 4 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 4 x i64> %a
}
@@ -500,7 +500,7 @@ define <vscale x 4 x i64> @test_vzip_vv_mask_i64m4(<vscale x 4 x i64> %passthru,
define <vscale x 8 x i64> @test_vzip_vv_i64m8(<vscale x 8 x i64> %passthru, <vscale x 4 x i64> %arg1, <vscale x 4 x i64> %arg2, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_i64m8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, ma
; CHECK-NEXT: vzip.vv v8, v16, v20
; CHECK-NEXT: ret
%a = call <vscale x 8 x i64> @llvm.riscv.vzip(
@@ -511,17 +511,17 @@ define <vscale x 8 x i64> @test_vzip_vv_i64m8(<vscale x 8 x i64> %passthru, <vsc
ret <vscale x 8 x i64> %a
}
-define <vscale x 8 x i64> @test_vzip_vv_mask_i64m8(<vscale x 8 x i64> %passthru, <vscale x 4 x i64> %arg1, <vscale x 4 x i64> %arg2, <vscale x 4 x i1> %mask, iXLen %vl) nounwind {
+define <vscale x 8 x i64> @test_vzip_vv_mask_i64m8(<vscale x 8 x i64> %passthru, <vscale x 4 x i64> %arg1, <vscale x 4 x i64> %arg2, <vscale x 8 x i1> %mask, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_mask_i64m8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vzip.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 8 x i64> @llvm.riscv.vzip.mask(
<vscale x 8 x i64> %passthru,
<vscale x 4 x i64> %arg1,
<vscale x 4 x i64> %arg2,
- <vscale x 4 x i1> %mask,
+ <vscale x 8 x i1> %mask,
iXLen %vl, iXLen 1)
ret <vscale x 8 x i64> %a
}
@@ -532,7 +532,7 @@ define <vscale x 8 x i64> @test_vzip_vv_mask_i64m8(<vscale x 8 x i64> %passthru,
define <vscale x 2 x half> @test_vzip_vv_f16mf4(<vscale x 2 x half> %passthru, <vscale x 1 x half> %a, <vscale x 1 x half> %b, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_f16mf4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
; CHECK-NEXT: vzip.vv v8, v9, v10
; CHECK-NEXT: ret
%r = call <vscale x 2 x half> @llvm.riscv.vzip(
@@ -543,17 +543,17 @@ define <vscale x 2 x half> @test_vzip_vv_f16mf4(<vscale x 2 x half> %passthru, <
ret <vscale x 2 x half> %r
}
-define <vscale x 2 x half> @test_vzip_vv_mask_f16mf4(<vscale x 2 x half> %passthru, <vscale x 1 x half> %a, <vscale x 1 x half> %b, <vscale x 1 x i1> %m, iXLen %vl) nounwind {
+define <vscale x 2 x half> @test_vzip_vv_mask_f16mf4(<vscale x 2 x half> %passthru, <vscale x 1 x half> %a, <vscale x 1 x half> %b, <vscale x 2 x i1> %m, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_mask_f16mf4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vzip.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
%r = call <vscale x 2 x half> @llvm.riscv.vzip.mask(
<vscale x 2 x half> %passthru,
<vscale x 1 x half> %a,
<vscale x 1 x half> %b,
- <vscale x 1 x i1> %m,
+ <vscale x 2 x i1> %m,
iXLen %vl, iXLen 1)
ret <vscale x 2 x half> %r
}
@@ -561,7 +561,7 @@ define <vscale x 2 x half> @test_vzip_vv_mask_f16mf4(<vscale x 2 x half> %passth
define <vscale x 4 x half> @test_vzip_vv_f16mf2(<vscale x 4 x half> %passthru, <vscale x 2 x half> %a, <vscale x 2 x half> %b, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_f16mf2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: vzip.vv v8, v9, v10
; CHECK-NEXT: ret
%r = call <vscale x 4 x half> @llvm.riscv.vzip(
@@ -572,17 +572,17 @@ define <vscale x 4 x half> @test_vzip_vv_f16mf2(<vscale x 4 x half> %passthru, <
ret <vscale x 4 x half> %r
}
-define <vscale x 4 x half> @test_vzip_vv_mask_f16mf2(<vscale x 4 x half> %passthru, <vscale x 2 x half> %a, <vscale x 2 x half> %b, <vscale x 2 x i1> %m, iXLen %vl) nounwind {
+define <vscale x 4 x half> @test_vzip_vv_mask_f16mf2(<vscale x 4 x half> %passthru, <vscale x 2 x half> %a, <vscale x 2 x half> %b, <vscale x 4 x i1> %m, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_mask_f16mf2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vzip.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
%r = call <vscale x 4 x half> @llvm.riscv.vzip.mask(
<vscale x 4 x half> %passthru,
<vscale x 2 x half> %a,
<vscale x 2 x half> %b,
- <vscale x 2 x i1> %m,
+ <vscale x 4 x i1> %m,
iXLen %vl, iXLen 1)
ret <vscale x 4 x half> %r
}
@@ -590,7 +590,7 @@ define <vscale x 4 x half> @test_vzip_vv_mask_f16mf2(<vscale x 4 x half> %passth
define <vscale x 8 x half> @test_vzip_vv_f16m1(<vscale x 8 x half> %passthru, <vscale x 4 x half> %a, <vscale x 4 x half> %b, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_f16m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
; CHECK-NEXT: vzip.vv v8, v10, v11
; CHECK-NEXT: ret
%r = call <vscale x 8 x half> @llvm.riscv.vzip(
@@ -601,17 +601,17 @@ define <vscale x 8 x half> @test_vzip_vv_f16m1(<vscale x 8 x half> %passthru, <v
ret <vscale x 8 x half> %r
}
-define <vscale x 8 x half> @test_vzip_vv_mask_f16m1(<vscale x 8 x half> %passthru, <vscale x 4 x half> %a, <vscale x 4 x half> %b, <vscale x 4 x i1> %m, iXLen %vl) nounwind {
+define <vscale x 8 x half> @test_vzip_vv_mask_f16m1(<vscale x 8 x half> %passthru, <vscale x 4 x half> %a, <vscale x 4 x half> %b, <vscale x 8 x i1> %m, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_mask_f16m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vzip.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret
%r = call <vscale x 8 x half> @llvm.riscv.vzip.mask(
<vscale x 8 x half> %passthru,
<vscale x 4 x half> %a,
<vscale x 4 x half> %b,
- <vscale x 4 x i1> %m,
+ <vscale x 8 x i1> %m,
iXLen %vl, iXLen 1)
ret <vscale x 8 x half> %r
}
@@ -619,7 +619,7 @@ define <vscale x 8 x half> @test_vzip_vv_mask_f16m1(<vscale x 8 x half> %passthr
define <vscale x 16 x half> @test_vzip_vv_f16m2(<vscale x 16 x half> %passthru, <vscale x 8 x half> %a, <vscale x 8 x half> %b, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_f16m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
; CHECK-NEXT: vzip.vv v8, v12, v14
; CHECK-NEXT: ret
%r = call <vscale x 16 x half> @llvm.riscv.vzip(
@@ -630,17 +630,17 @@ define <vscale x 16 x half> @test_vzip_vv_f16m2(<vscale x 16 x half> %passthru,
ret <vscale x 16 x half> %r
}
-define <vscale x 16 x half> @test_vzip_vv_mask_f16m2(<vscale x 16 x half> %passthru, <vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x i1> %m, iXLen %vl) nounwind {
+define <vscale x 16 x half> @test_vzip_vv_mask_f16m2(<vscale x 16 x half> %passthru, <vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 16 x i1> %m, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_mask_f16m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vzip.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret
%r = call <vscale x 16 x half> @llvm.riscv.vzip.mask(
<vscale x 16 x half> %passthru,
<vscale x 8 x half> %a,
<vscale x 8 x half> %b,
- <vscale x 8 x i1> %m,
+ <vscale x 16 x i1> %m,
iXLen %vl, iXLen 1)
ret <vscale x 16 x half> %r
}
@@ -648,7 +648,7 @@ define <vscale x 16 x half> @test_vzip_vv_mask_f16m2(<vscale x 16 x half> %passt
define <vscale x 32 x half> @test_vzip_vv_f16m4(<vscale x 32 x half> %passthru, <vscale x 16 x half> %a, <vscale x 16 x half> %b, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_f16m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma
; CHECK-NEXT: vzip.vv v8, v16, v20
; CHECK-NEXT: ret
%r = call <vscale x 32 x half> @llvm.riscv.vzip(
@@ -659,17 +659,17 @@ define <vscale x 32 x half> @test_vzip_vv_f16m4(<vscale x 32 x half> %passthru,
ret <vscale x 32 x half> %r
}
-define <vscale x 32 x half> @test_vzip_vv_mask_f16m4(<vscale x 32 x half> %passthru, <vscale x 16 x half> %a, <vscale x 16 x half> %b, <vscale x 16 x i1> %m, iXLen %vl) nounwind {
+define <vscale x 32 x half> @test_vzip_vv_mask_f16m4(<vscale x 32 x half> %passthru, <vscale x 16 x half> %a, <vscale x 16 x half> %b, <vscale x 32 x i1> %m, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_mask_f16m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vzip.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret
%r = call <vscale x 32 x half> @llvm.riscv.vzip.mask(
<vscale x 32 x half> %passthru,
<vscale x 16 x half> %a,
<vscale x 16 x half> %b,
- <vscale x 16 x i1> %m,
+ <vscale x 32 x i1> %m,
iXLen %vl, iXLen 1)
ret <vscale x 32 x half> %r
}
@@ -678,7 +678,7 @@ define <vscale x 32 x half> @test_vzip_vv_mask_f16m4(<vscale x 32 x half> %passt
define <vscale x 2 x bfloat> @test_vzip_vv_bf16mf4(<vscale x 2 x bfloat> %passthru, <vscale x 1 x bfloat> %a, <vscale x 1 x bfloat> %b, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_bf16mf4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
; CHECK-NEXT: vzip.vv v8, v9, v10
; CHECK-NEXT: ret
%r = call <vscale x 2 x bfloat> @llvm.riscv.vzip(
@@ -689,17 +689,17 @@ define <vscale x 2 x bfloat> @test_vzip_vv_bf16mf4(<vscale x 2 x bfloat> %passth
ret <vscale x 2 x bfloat> %r
}
-define <vscale x 2 x bfloat> @test_vzip_vv_mask_bf16mf4(<vscale x 2 x bfloat> %passthru, <vscale x 1 x bfloat> %a, <vscale x 1 x bfloat> %b, <vscale x 1 x i1> %m, iXLen %vl) nounwind {
+define <vscale x 2 x bfloat> @test_vzip_vv_mask_bf16mf4(<vscale x 2 x bfloat> %passthru, <vscale x 1 x bfloat> %a, <vscale x 1 x bfloat> %b, <vscale x 2 x i1> %m, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_mask_bf16mf4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vzip.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
%r = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask(
<vscale x 2 x bfloat> %passthru,
<vscale x 1 x bfloat> %a,
<vscale x 1 x bfloat> %b,
- <vscale x 1 x i1> %m,
+ <vscale x 2 x i1> %m,
iXLen %vl, iXLen 1)
ret <vscale x 2 x bfloat> %r
}
@@ -707,7 +707,7 @@ define <vscale x 2 x bfloat> @test_vzip_vv_mask_bf16mf4(<vscale x 2 x bfloat> %p
define <vscale x 8 x bfloat> @test_vzip_vv_bf16m1(<vscale x 8 x bfloat> %passthru, <vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_bf16m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
; CHECK-NEXT: vzip.vv v8, v10, v11
; CHECK-NEXT: ret
%r = call <vscale x 8 x bfloat> @llvm.riscv.vzip(
@@ -718,17 +718,17 @@ define <vscale x 8 x bfloat> @test_vzip_vv_bf16m1(<vscale x 8 x bfloat> %passthr
ret <vscale x 8 x bfloat> %r
}
-define <vscale x 8 x bfloat> @test_vzip_vv_mask_bf16m1(<vscale x 8 x bfloat> %passthru, <vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b, <vscale x 4 x i1> %m, iXLen %vl) nounwind {
+define <vscale x 8 x bfloat> @test_vzip_vv_mask_bf16m1(<vscale x 8 x bfloat> %passthru, <vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b, <vscale x 8 x i1> %m, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_mask_bf16m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vzip.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret
%r = call <vscale x 8 x bfloat> @llvm.riscv.vzip.mask(
<vscale x 8 x bfloat> %passthru,
<vscale x 4 x bfloat> %a,
<vscale x 4 x bfloat> %b,
- <vscale x 4 x i1> %m,
+ <vscale x 8 x i1> %m,
iXLen %vl, iXLen 1)
ret <vscale x 8 x bfloat> %r
}
@@ -737,7 +737,7 @@ define <vscale x 8 x bfloat> @test_vzip_vv_mask_bf16m1(<vscale x 8 x bfloat> %pa
define <vscale x 2 x float> @test_vzip_vv_f32mf2(<vscale x 2 x float> %passthru, <vscale x 1 x float> %a, <vscale x 1 x float> %b, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_f32mf2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
; CHECK-NEXT: vzip.vv v8, v9, v10
; CHECK-NEXT: ret
%r = call <vscale x 2 x float> @llvm.riscv.vzip(
@@ -748,17 +748,17 @@ define <vscale x 2 x float> @test_vzip_vv_f32mf2(<vscale x 2 x float> %passthru,
ret <vscale x 2 x float> %r
}
-define <vscale x 2 x float> @test_vzip_vv_mask_f32mf2(<vscale x 2 x float> %passthru, <vscale x 1 x float> %a, <vscale x 1 x float> %b, <vscale x 1 x i1> %m, iXLen %vl) nounwind {
+define <vscale x 2 x float> @test_vzip_vv_mask_f32mf2(<vscale x 2 x float> %passthru, <vscale x 1 x float> %a, <vscale x 1 x float> %b, <vscale x 2 x i1> %m, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_mask_f32mf2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vzip.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
%r = call <vscale x 2 x float> @llvm.riscv.vzip.mask(
<vscale x 2 x float> %passthru,
<vscale x 1 x float> %a,
<vscale x 1 x float> %b,
- <vscale x 1 x i1> %m,
+ <vscale x 2 x i1> %m,
iXLen %vl, iXLen 1)
ret <vscale x 2 x float> %r
}
@@ -766,7 +766,7 @@ define <vscale x 2 x float> @test_vzip_vv_mask_f32mf2(<vscale x 2 x float> %pass
define <vscale x 4 x float> @test_vzip_vv_f32m1(<vscale x 4 x float> %passthru, <vscale x 2 x float> %a, <vscale x 2 x float> %b, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_f32m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
; CHECK-NEXT: vzip.vv v8, v10, v11
; CHECK-NEXT: ret
%r = call <vscale x 4 x float> @llvm.riscv.vzip(
@@ -777,17 +777,17 @@ define <vscale x 4 x float> @test_vzip_vv_f32m1(<vscale x 4 x float> %passthru,
ret <vscale x 4 x float> %r
}
-define <vscale x 4 x float> @test_vzip_vv_mask_f32m1(<vscale x 4 x float> %passthru, <vscale x 2 x float> %a, <vscale x 2 x float> %b, <vscale x 2 x i1> %m, iXLen %vl) nounwind {
+define <vscale x 4 x float> @test_vzip_vv_mask_f32m1(<vscale x 4 x float> %passthru, <vscale x 2 x float> %a, <vscale x 2 x float> %b, <vscale x 4 x i1> %m, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_mask_f32m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vzip.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret
%r = call <vscale x 4 x float> @llvm.riscv.vzip.mask(
<vscale x 4 x float> %passthru,
<vscale x 2 x float> %a,
<vscale x 2 x float> %b,
- <vscale x 2 x i1> %m,
+ <vscale x 4 x i1> %m,
iXLen %vl, iXLen 1)
ret <vscale x 4 x float> %r
}
@@ -795,7 +795,7 @@ define <vscale x 4 x float> @test_vzip_vv_mask_f32m1(<vscale x 4 x float> %passt
define <vscale x 8 x float> @test_vzip_vv_f32m2(<vscale x 8 x float> %passthru, <vscale x 4 x float> %a, <vscale x 4 x float> %b, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_f32m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
; CHECK-NEXT: vzip.vv v8, v12, v14
; CHECK-NEXT: ret
%r = call <vscale x 8 x float> @llvm.riscv.vzip(
@@ -806,17 +806,17 @@ define <vscale x 8 x float> @test_vzip_vv_f32m2(<vscale x 8 x float> %passthru,
ret <vscale x 8 x float> %r
}
-define <vscale x 8 x float> @test_vzip_vv_mask_f32m2(<vscale x 8 x float> %passthru, <vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x i1> %m, iXLen %vl) nounwind {
+define <vscale x 8 x float> @test_vzip_vv_mask_f32m2(<vscale x 8 x float> %passthru, <vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 8 x i1> %m, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_mask_f32m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vzip.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret
%r = call <vscale x 8 x float> @llvm.riscv.vzip.mask(
<vscale x 8 x float> %passthru,
<vscale x 4 x float> %a,
<vscale x 4 x float> %b,
- <vscale x 4 x i1> %m,
+ <vscale x 8 x i1> %m,
iXLen %vl, iXLen 1)
ret <vscale x 8 x float> %r
}
@@ -824,7 +824,7 @@ define <vscale x 8 x float> @test_vzip_vv_mask_f32m2(<vscale x 8 x float> %passt
define <vscale x 16 x float> @test_vzip_vv_f32m4(<vscale x 16 x float> %passthru, <vscale x 8 x float> %a, <vscale x 8 x float> %b, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_f32m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, ma
; CHECK-NEXT: vzip.vv v8, v16, v20
; CHECK-NEXT: ret
%r = call <vscale x 16 x float> @llvm.riscv.vzip(
@@ -835,17 +835,17 @@ define <vscale x 16 x float> @test_vzip_vv_f32m4(<vscale x 16 x float> %passthru
ret <vscale x 16 x float> %r
}
-define <vscale x 16 x float> @test_vzip_vv_mask_f32m4(<vscale x 16 x float> %passthru, <vscale x 8 x float> %a, <vscale x 8 x float> %b, <vscale x 8 x i1> %m, iXLen %vl) nounwind {
+define <vscale x 16 x float> @test_vzip_vv_mask_f32m4(<vscale x 16 x float> %passthru, <vscale x 8 x float> %a, <vscale x 8 x float> %b, <vscale x 16 x i1> %m, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_mask_f32m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vzip.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret
%r = call <vscale x 16 x float> @llvm.riscv.vzip.mask(
<vscale x 16 x float> %passthru,
<vscale x 8 x float> %a,
<vscale x 8 x float> %b,
- <vscale x 8 x i1> %m,
+ <vscale x 16 x i1> %m,
iXLen %vl, iXLen 1)
ret <vscale x 16 x float> %r
}
@@ -854,7 +854,7 @@ define <vscale x 16 x float> @test_vzip_vv_mask_f32m4(<vscale x 16 x float> %pas
define <vscale x 2 x double> @test_vzip_vv_f64m1(<vscale x 2 x double> %passthru, <vscale x 1 x double> %a, <vscale x 1 x double> %b, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_f64m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma
; CHECK-NEXT: vzip.vv v8, v10, v11
; CHECK-NEXT: ret
%r = call <vscale x 2 x double> @llvm.riscv.vzip(
@@ -865,17 +865,17 @@ define <vscale x 2 x double> @test_vzip_vv_f64m1(<vscale x 2 x double> %passthru
ret <vscale x 2 x double> %r
}
-define <vscale x 2 x double> @test_vzip_vv_mask_f64m1(<vscale x 2 x double> %passthru, <vscale x 1 x double> %a, <vscale x 1 x double> %b, <vscale x 1 x i1> %m, iXLen %vl) nounwind {
+define <vscale x 2 x double> @test_vzip_vv_mask_f64m1(<vscale x 2 x double> %passthru, <vscale x 1 x double> %a, <vscale x 1 x double> %b, <vscale x 2 x i1> %m, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_mask_f64m1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vzip.vv v8, v10, v11, v0.t
; CHECK-NEXT: ret
%r = call <vscale x 2 x double> @llvm.riscv.vzip.mask(
<vscale x 2 x double> %passthru,
<vscale x 1 x double> %a,
<vscale x 1 x double> %b,
- <vscale x 1 x i1> %m,
+ <vscale x 2 x i1> %m,
iXLen %vl, iXLen 1)
ret <vscale x 2 x double> %r
}
@@ -883,7 +883,7 @@ define <vscale x 2 x double> @test_vzip_vv_mask_f64m1(<vscale x 2 x double> %pas
define <vscale x 4 x double> @test_vzip_vv_f64m2(<vscale x 4 x double> %passthru, <vscale x 2 x double> %a, <vscale x 2 x double> %b, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_f64m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma
; CHECK-NEXT: vzip.vv v8, v12, v14
; CHECK-NEXT: ret
%r = call <vscale x 4 x double> @llvm.riscv.vzip(
@@ -894,17 +894,17 @@ define <vscale x 4 x double> @test_vzip_vv_f64m2(<vscale x 4 x double> %passthru
ret <vscale x 4 x double> %r
}
-define <vscale x 4 x double> @test_vzip_vv_mask_f64m2(<vscale x 4 x double> %passthru, <vscale x 2 x double> %a, <vscale x 2 x double> %b, <vscale x 2 x i1> %m, iXLen %vl) nounwind {
+define <vscale x 4 x double> @test_vzip_vv_mask_f64m2(<vscale x 4 x double> %passthru, <vscale x 2 x double> %a, <vscale x 2 x double> %b, <vscale x 4 x i1> %m, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_mask_f64m2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vzip.vv v8, v12, v14, v0.t
; CHECK-NEXT: ret
%r = call <vscale x 4 x double> @llvm.riscv.vzip.mask(
<vscale x 4 x double> %passthru,
<vscale x 2 x double> %a,
<vscale x 2 x double> %b,
- <vscale x 2 x i1> %m,
+ <vscale x 4 x i1> %m,
iXLen %vl, iXLen 1)
ret <vscale x 4 x double> %r
}
@@ -912,7 +912,7 @@ define <vscale x 4 x double> @test_vzip_vv_mask_f64m2(<vscale x 4 x double> %pas
define <vscale x 8 x double> @test_vzip_vv_f64m4(<vscale x 8 x double> %passthru, <vscale x 4 x double> %a, <vscale x 4 x double> %b, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_f64m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, ma
; CHECK-NEXT: vzip.vv v8, v16, v20
; CHECK-NEXT: ret
%r = call <vscale x 8 x double> @llvm.riscv.vzip(
@@ -923,17 +923,17 @@ define <vscale x 8 x double> @test_vzip_vv_f64m4(<vscale x 8 x double> %passthru
ret <vscale x 8 x double> %r
}
-define <vscale x 8 x double> @test_vzip_vv_mask_f64m4(<vscale x 8 x double> %passthru, <vscale x 4 x double> %a, <vscale x 4 x double> %b, <vscale x 4 x i1> %m, iXLen %vl) nounwind {
+define <vscale x 8 x double> @test_vzip_vv_mask_f64m4(<vscale x 8 x double> %passthru, <vscale x 4 x double> %a, <vscale x 4 x double> %b, <vscale x 8 x i1> %m, iXLen %vl) nounwind {
; CHECK-LABEL: test_vzip_vv_mask_f64m4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vzip.vv v8, v16, v20, v0.t
; CHECK-NEXT: ret
%r = call <vscale x 8 x double> @llvm.riscv.vzip.mask(
<vscale x 8 x double> %passthru,
<vscale x 4 x double> %a,
<vscale x 4 x double> %b,
- <vscale x 4 x i1> %m,
+ <vscale x 8 x i1> %m,
iXLen %vl, iXLen 1)
ret <vscale x 8 x double> %r
}
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 367ec6f04d953..3017f6bcfe7b3 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -183,8 +183,8 @@
.attribute arch, "rv32i_zvdot4a8i0p1"
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvdot4a8i0p1_zve32x1p0_zvl32b1p0"
-.attribute arch, "rv32i_zvzip0p1"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvzip0p1"
+.attribute arch, "rv32i_zvzip0p2"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvzip0p2"
.attribute arch, "rv32izbs1p0"
# CHECK: attribute 5, "rv32i2p1_zbs1p0"
diff --git a/llvm/test/MC/RISCV/rvv/zvzip-invalid.s b/llvm/test/MC/RISCV/rvv/zvzip-invalid.s
index 2bf68a05f1569..917984d31ddda 100644
--- a/llvm/test/MC/RISCV/rvv/zvzip-invalid.s
+++ b/llvm/test/MC/RISCV/rvv/zvzip-invalid.s
@@ -13,14 +13,6 @@ vpairo.vv v0, v0, v4
# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group
# CHECK-ERROR-LABEL: vpairo.vv v0, v0, v4
-vunzipe.v v0, v0
-# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group
-# CHECK-ERROR-LABEL: vunzipe.v v0, v0
-
-vunzipo.v v0, v0
-# CHECK-ERROR: the destination vector register group cannot overlap the source vector register group
-# CHECK-ERROR-LABEL: vunzipo.v v0, v0
-
vzip.vv v0, v2, v4, v0.t
# CHECK-ERROR: the destination vector register group cannot overlap the mask register
# CHECK-ERROR-LABEL: vzip.vv v0, v2, v4, v0.t
@@ -32,3 +24,11 @@ vpaire.vv v0, v2, v4, v0.t
vpairo.vv v0, v2, v4, v0.t
# CHECK-ERROR: the destination vector register group cannot overlap the mask register
# CHECK-ERROR-LABEL: vpairo.vv v0, v2, v4, v0.t
+
+vunzipe.v v1, v2, v0.t
+# CHECK-ERROR: invalid operand for instruction
+# CHECK-ERROR-LABEL: vunzipe.v v1, v2, v0.t
+
+vunzipo.v v1, v2, v0.t
+# CHECK-ERROR: invalid operand for instruction
+# CHECK-ERROR-LABEL: vunzipo.v v1, v2, v0.t
diff --git a/llvm/test/MC/RISCV/rvv/zvzip.s b/llvm/test/MC/RISCV/rvv/zvzip.s
index 842b939ec1376..ba9cd0f4068f7 100644
--- a/llvm/test/MC/RISCV/rvv/zvzip.s
+++ b/llvm/test/MC/RISCV/rvv/zvzip.s
@@ -37,14 +37,6 @@ vpairo.vv v1, v2, v3, v0.t
# CHECK-ASM: encoding: [0xd7,0xa0,0x25,0x4a]
vunzipe.v v1, v2
-# CHECK-ASM-AND-OBJ: vunzipe.v v1, v2, v0.t
-# CHECK-ASM: encoding: [0xd7,0xa0,0x25,0x48]
-vunzipe.v v1, v2, v0.t
-
# CHECK-ASM-AND-OBJ: vunzipo.v v1, v2
# CHECK-ASM: encoding: [0xd7,0xa0,0x27,0x4a]
vunzipo.v v1, v2
-
-# CHECK-ASM-AND-OBJ: vunzipe.v v1, v2, v0.t
-# CHECK-ASM: encoding: [0xd7,0xa0,0x25,0x48]
-vunzipe.v v1, v2, v0.t
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index cdc2fcea37fcb..ee5fd1f2a48e0 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1637,7 +1637,7 @@ Experimental extensions
zvvmm 0.1
zvvmtls 0.1
zvvmttls 0.1
- zvzip 0.1
+ zvzip 0.2
smpmpmt 0.6
svukte 0.3
xqccmt 0.1
>From 41c5991e04f1d43ac67ca4f7a7b6d2fdb75cf376 Mon Sep 17 00:00:00 2001
From: liumingliang <liumingliang.dev at bytedance.com>
Date: Fri, 17 Jul 2026 15:26:11 +0800
Subject: [PATCH 2/3] [RISCV] Update Zvzip v0.2 pseudo patterns
Remove @earlyclobber for vunzipe.v/vunzipo.v pseudos when the
source LMUL <= 1, matching the narrowing overlap rules.
Also clean up the related TableGen definitions.
---
clang/include/clang/Basic/riscv_vector.td | 24 ++--
.../clang/Support/RISCVVIntrinsicUtils.h | 3 +-
clang/lib/Sema/SemaRISCV.cpp | 23 ++-
clang/lib/Support/RISCVVIntrinsicUtils.cpp | 15 +-
.../test/Preprocessor/riscv-target-features.c | 6 +-
clang/utils/TableGen/RISCVVEmitter.cpp | 29 ++--
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 25 ++--
llvm/lib/Target/RISCV/RISCVInstrInfoV.td | 10 ++
.../Target/RISCV/RISCVInstrInfoVVLPatterns.td | 22 +++
llvm/lib/Target/RISCV/RISCVInstrInfoZvzip.td | 136 +++++++-----------
llvm/test/MC/RISCV/rvv/zvzip-invalid.s | 4 +-
llvm/test/MC/RISCV/rvv/zvzip.s | 16 +++
12 files changed, 161 insertions(+), 152 deletions(-)
diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
index 8bc68888edd52..e5f7f456d069d 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -2149,26 +2149,22 @@ let RequiredFeatures = ["zvdot4a8i"] in {
let UnMaskedPolicyScheme = HasPassthruOperand in {
let RequiredFeatures = ["zvzip"] in {
// Signed and floating type
- let MaskedPrototypeHasResultMask = true in
- defm vzip : RVVOutOp0BuiltinSet<"vzip", "csilxfdy",
- [["vv", "d", "dvv"]]>;
+ let MaskedPrototypeHasResultMask = true in {
+ defm vzip : RVVOutOp0BuiltinSet<"vzip", "csilxfdy", [["vv", "d", "dvv"]]>;
+ }
let HasMasked = false in {
- defm vunzipe : RVVOutOp0BuiltinSet<"vunzipe", "csilxfdy",
- [["v", "v", "vd"]]>;
- defm vunzipo : RVVOutOp0BuiltinSet<"vunzipo", "csilxfdy",
- [["v", "v", "vd"]]>;
+ defm vunzipe : RVVOutOp0BuiltinSet<"vunzipe", "csilxfdy", [["v", "v", "vd"]]>;
+ defm vunzipo : RVVOutOp0BuiltinSet<"vunzipo", "csilxfdy", [["v", "v", "vd"]]>;
}
defm vpaire : RVVOutBuiltinSet<"vpaire", "csilxfdy", [["vv", "v", "vvv"]]>;
defm vpairo : RVVOutBuiltinSet<"vpairo", "csilxfdy", [["vv", "v", "vvv"]]>;
// Unsigned
- let MaskedPrototypeHasResultMask = true in
- defm vzip : RVVOutOp0BuiltinSet<"vzip", "csil",
- [["vv", "Ud", "UdUvUv"]]>;
+ let MaskedPrototypeHasResultMask = true in {
+ defm vzip : RVVOutOp0BuiltinSet<"vzip", "csil", [["vv", "Ud", "UdUvUv"]]>;
+ }
let HasMasked = false in {
- defm vunzipe : RVVOutOp0BuiltinSet<"vunzipe", "csil",
- [["v", "Uv", "UvUd"]]>;
- defm vunzipo : RVVOutOp0BuiltinSet<"vunzipo", "csil",
- [["v", "Uv", "UvUd"]]>;
+ defm vunzipe : RVVOutOp0BuiltinSet<"vunzipe", "csil", [["v", "Uv", "UvUd"]]>;
+ defm vunzipo : RVVOutOp0BuiltinSet<"vunzipo", "csil", [["v", "Uv", "UvUd"]]>;
}
defm vpaire : RVVOutBuiltinSet<"vpaire", "csil", [["vv", "Uv", "UvUvUv"]]>;
defm vpairo : RVVOutBuiltinSet<"vpairo", "csil", [["vv", "Uv", "UvUvUv"]]>;
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
index d7c8a2de16b3b..bfcaec572aa95 100644
--- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -483,7 +483,8 @@ class RVVIntrinsic {
static llvm::SmallVector<PrototypeDescriptor>
computeBuiltinTypes(llvm::ArrayRef<PrototypeDescriptor> Prototype,
- bool IsMasked, bool HasMaskedOffOperand, bool HasVL,
+ bool IsMasked, bool HasMaskedOffOperand,
+ bool MaskedPrototypeHasResultMask, bool HasVL,
unsigned NF, PolicyScheme DefaultScheme,
Policy PolicyAttrs, bool IsTuple);
diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp
index e263d88bb914c..b9b986a44ee24 100644
--- a/clang/lib/Sema/SemaRISCV.cpp
+++ b/clang/lib/Sema/SemaRISCV.cpp
@@ -264,18 +264,16 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
llvm::SmallVector<PrototypeDescriptor> ProtoSeq =
RVVIntrinsic::computeBuiltinTypes(
BasicProtoSeq, /*IsMasked=*/false,
- /*HasMaskedOffOperand=*/false, Record.HasVL, Record.NF,
+ /*HasMaskedOffOperand=*/false,
+ /*MaskedPrototypeHasResultMask=*/false, Record.HasVL, Record.NF,
UnMaskedPolicyScheme, DefaultPolicy, Record.IsTuple);
llvm::SmallVector<PrototypeDescriptor> ProtoMaskSeq;
if (Record.HasMasked)
ProtoMaskSeq = RVVIntrinsic::computeBuiltinTypes(
BasicProtoSeq, /*IsMasked=*/true, Record.HasMaskedOffOperand,
- Record.HasVL, Record.NF, MaskedPolicyScheme, DefaultPolicy,
- Record.IsTuple);
- if (Record.HasMasked && Record.MaskedPrototypeHasResultMask)
- ProtoMaskSeq[1] = PrototypeDescriptor(
- BaseTypeModifier::Vector, VectorTypeModifier::DoubleLMULMaskVector);
+ Record.MaskedPrototypeHasResultMask, Record.HasVL, Record.NF,
+ MaskedPolicyScheme, DefaultPolicy, Record.IsTuple);
bool UnMaskedHasPolicy = UnMaskedPolicyScheme != PolicyScheme::SchemeNone;
bool MaskedHasPolicy = MaskedPolicyScheme != PolicyScheme::SchemeNone;
@@ -321,8 +319,9 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
llvm::SmallVector<PrototypeDescriptor> PolicyPrototype =
RVVIntrinsic::computeBuiltinTypes(
BasicProtoSeq, /*IsMasked=*/false,
- /*HasMaskedOffOperand=*/false, Record.HasVL, Record.NF,
- UnMaskedPolicyScheme, P, Record.IsTuple);
+ /*HasMaskedOffOperand=*/false,
+ /*MaskedPrototypeHasResultMask=*/false, Record.HasVL,
+ Record.NF, UnMaskedPolicyScheme, P, Record.IsTuple);
std::optional<RVVTypes> PolicyTypes = TypeCache.computeTypes(
BaseType, Log2LMUL, Record.NF, PolicyPrototype);
InitRVVIntrinsic(Record, SuffixStr, OverloadedSuffixStr,
@@ -344,12 +343,8 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
llvm::SmallVector<PrototypeDescriptor> PolicyPrototype =
RVVIntrinsic::computeBuiltinTypes(
BasicProtoSeq, /*IsMasked=*/true, Record.HasMaskedOffOperand,
- Record.HasVL, Record.NF, MaskedPolicyScheme, P,
- Record.IsTuple);
- if (Record.MaskedPrototypeHasResultMask)
- PolicyPrototype[1] =
- PrototypeDescriptor(BaseTypeModifier::Vector,
- VectorTypeModifier::DoubleLMULMaskVector);
+ Record.MaskedPrototypeHasResultMask, Record.HasVL, Record.NF,
+ MaskedPolicyScheme, P, Record.IsTuple);
std::optional<RVVTypes> PolicyTypes = TypeCache.computeTypes(
BaseType, Log2LMUL, Record.NF, PolicyPrototype);
InitRVVIntrinsic(Record, SuffixStr, OverloadedSuffixStr,
diff --git a/clang/lib/Support/RISCVVIntrinsicUtils.cpp b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
index a01a39a3b5f4c..77e2994258411 100644
--- a/clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -1104,8 +1104,8 @@ std::string RVVIntrinsic::getSuffixStr(
llvm::SmallVector<PrototypeDescriptor> RVVIntrinsic::computeBuiltinTypes(
llvm::ArrayRef<PrototypeDescriptor> Prototype, bool IsMasked,
- bool HasMaskedOffOperand, bool HasVL, unsigned NF,
- PolicyScheme DefaultScheme, Policy PolicyAttrs, bool IsTuple) {
+ bool HasMaskedOffOperand, bool MaskedPrototypeHasResultMask, bool HasVL,
+ unsigned NF, PolicyScheme DefaultScheme, Policy PolicyAttrs, bool IsTuple) {
SmallVector<PrototypeDescriptor> NewPrototype(Prototype);
bool HasPassthruOp = DefaultScheme == PolicyScheme::HasPassthruOperand;
if (IsMasked) {
@@ -1146,7 +1146,14 @@ llvm::SmallVector<PrototypeDescriptor> RVVIntrinsic::computeBuiltinTypes(
PrototypeDescriptor::Mask);
} else {
// If IsMasked, insert PrototypeDescriptor:Mask as first input operand.
- NewPrototype.insert(NewPrototype.begin() + 1, PrototypeDescriptor::Mask);
+ if (MaskedPrototypeHasResultMask)
+ NewPrototype.insert(
+ NewPrototype.begin() + 1,
+ PrototypeDescriptor(BaseTypeModifier::Vector,
+ VectorTypeModifier::DoubleLMULMaskVector));
+ else
+ NewPrototype.insert(NewPrototype.begin() + 1,
+ PrototypeDescriptor::Mask);
}
} else {
if (NF == 1) {
@@ -1170,7 +1177,7 @@ llvm::SmallVector<PrototypeDescriptor> RVVIntrinsic::computeBuiltinTypes(
NewPrototype.insert(NewPrototype.begin() + NF + 1, NF, MaskoffType);
}
}
- }
+ }
// If HasVL, append PrototypeDescriptor:VL to last operand
if (HasVL)
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index e7ea0318a676a..d2dcf9dab9d92 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -1734,11 +1734,11 @@
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32i_zve32x_zvzip0p2 -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-ZVZVIP-EXT %s
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVZIP-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
// RUN: -march=rv64i_zve32x_zvzip0p2 -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-ZVZVIP-EXT %s
-// CHECK-ZVZVIP-EXT: __riscv_zvzip 2000{{$}}
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVZIP-EXT %s
+// CHECK-ZVZIP-EXT: __riscv_zvzip 2000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
// RUN: -march=rv32izicfiss1p0 -E -dM %s \
diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp b/clang/utils/TableGen/RISCVVEmitter.cpp
index 071b2f0b846e9..81dda320019c9 100644
--- a/clang/utils/TableGen/RISCVVEmitter.cpp
+++ b/clang/utils/TableGen/RISCVVEmitter.cpp
@@ -59,9 +59,9 @@ struct SemaRecord {
// Number of field, large than 1 if it's segment load/store.
unsigned NF;
- bool HasMasked :1;
- bool HasVL :1;
- bool HasMaskedOffOperand :1;
+ bool HasMasked : 1;
+ bool HasVL : 1;
+ bool HasMaskedOffOperand : 1;
bool HasTailPolicy : 1;
bool HasMaskPolicy : 1;
bool HasFRMRoundModeOp : 1;
@@ -705,16 +705,15 @@ void RVVEmitter::createRVVIntrinsics(
// Compute Builtin types
auto Prototype = RVVIntrinsic::computeBuiltinTypes(
BasicPrototype, /*IsMasked=*/false,
- /*HasMaskedOffOperand=*/false, HasVL, NF, UnMaskedPolicyScheme,
+ /*HasMaskedOffOperand=*/false,
+ /*MaskedPrototypeHasResultMask=*/false, HasVL, NF, UnMaskedPolicyScheme,
DefaultPolicy, IsTuple);
SmallVector<PrototypeDescriptor> MaskedPrototype;
if (HasMasked)
MaskedPrototype = RVVIntrinsic::computeBuiltinTypes(
- BasicPrototype, /*IsMasked=*/true, HasMaskedOffOperand, HasVL, NF,
- MaskedPolicyScheme, DefaultPolicy, IsTuple);
- if (HasMasked && MaskedPrototypeHasResultMask)
- MaskedPrototype[1] = PrototypeDescriptor(
- BaseTypeModifier::Vector, VectorTypeModifier::DoubleLMULMaskVector);
+ BasicPrototype, /*IsMasked=*/true, HasMaskedOffOperand,
+ MaskedPrototypeHasResultMask, HasVL, NF, MaskedPolicyScheme,
+ DefaultPolicy, IsTuple);
// Create Intrinsics for each type and LMUL.
for (char I : TypeRange) {
@@ -742,7 +741,8 @@ void RVVEmitter::createRVVIntrinsics(
SmallVector<PrototypeDescriptor> PolicyPrototype =
RVVIntrinsic::computeBuiltinTypes(
BasicPrototype, /*IsMasked=*/false,
- /*HasMaskedOffOperand=*/false, HasVL, NF,
+ /*HasMaskedOffOperand=*/false,
+ /*MaskedPrototypeHasResultMask=*/false, HasVL, NF,
UnMaskedPolicyScheme, P, IsTuple);
std::optional<RVVTypes> PolicyTypes =
TypeCache.computeTypes(BT, Log2LMUL, NF, PolicyPrototype);
@@ -769,12 +769,9 @@ void RVVEmitter::createRVVIntrinsics(
for (auto P : SupportedMaskedPolicies) {
SmallVector<PrototypeDescriptor> PolicyPrototype =
RVVIntrinsic::computeBuiltinTypes(
- BasicPrototype, /*IsMasked=*/true, HasMaskedOffOperand, HasVL,
- NF, MaskedPolicyScheme, P, IsTuple);
- if (MaskedPrototypeHasResultMask)
- PolicyPrototype[1] =
- PrototypeDescriptor(BaseTypeModifier::Vector,
- VectorTypeModifier::DoubleLMULMaskVector);
+ BasicPrototype, /*IsMasked=*/true, HasMaskedOffOperand,
+ MaskedPrototypeHasResultMask, HasVL, NF, MaskedPolicyScheme,
+ P, IsTuple);
std::optional<RVVTypes> PolicyTypes =
TypeCache.computeTypes(BT, Log2LMUL, NF, PolicyPrototype);
Out.push_back(std::make_unique<RVVIntrinsic>(
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index b3863074df825..0498fb5c424b2 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -5856,8 +5856,8 @@ static SDValue lowerZvzipVZIP(SDValue Op0, SDValue Op1, const SDLoc &DL,
Op1 = convertToScalableVector(ContainerVT, Op1, DAG, Subtarget);
}
MVT ResVT = ContainerVT.getDoubleNumVectorElementsVT();
- auto [Mask, VL] = getDefaultVLOps(IntVT.getDoubleNumVectorElementsVT(), ResVT,
- DL, DAG, Subtarget);
+ MVT ResIntVT = IntVT.getDoubleNumVectorElementsVT();
+ auto [Mask, VL] = getDefaultVLOps(ResIntVT, ResVT, DL, DAG, Subtarget);
SDValue Passthru = DAG.getUNDEF(ResVT);
SDValue Res =
DAG.getNode(RISCVISD::VZIP_VL, DL, ResVT, Op0, Op1, Passthru, Mask, VL);
@@ -5893,15 +5893,9 @@ static SDValue lowerZvzipVUNZIP(unsigned Opc, SDValue Op, const SDLoc &DL,
MVT ResVT = ContainerVT.getHalfNumVectorElementsVT();
MVT HalfVT = VT.getHalfNumVectorElementsVT();
MVT HalfIntVT = IntVT.getHalfNumVectorElementsVT();
- SDValue VL;
- if (IntVT.isFixedLengthVector())
- VL = DAG.getConstant(IntVT.getVectorNumElements(), DL,
- Subtarget.getXLenVT());
- else
- VL = DAG.getRegister(RISCV::X0, Subtarget.getXLenVT());
- SDValue Mask = getAllOnesMask(ResVT, VL, DL, DAG);
+ auto [_, VL] = getDefaultVLOps(IntVT, ContainerVT, DL, DAG, Subtarget);
SDValue Passthru = DAG.getUNDEF(ResVT);
- SDValue Res = DAG.getNode(Opc, DL, ResVT, Op, Passthru, Mask, VL);
+ SDValue Res = DAG.getNode(Opc, DL, ResVT, Op, Passthru, VL);
if (HalfIntVT.isFixedLengthVector())
Res = convertFromScalableVector(HalfIntVT, Res, DAG, Subtarget);
Res = DAG.getBitcast(HalfVT, Res);
@@ -6787,8 +6781,9 @@ SDValue RISCVTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
}
if (UsesBothSources &&
- isLegalVTForZvzipInterleavedOperand(V1.getSimpleValueType(),
- Subtarget) &&
+ isLegalVTForZvzipInterleavedOperand(
+ V1.getSimpleValueType().getDoubleNumVectorElementsVT(),
+ Subtarget) &&
V1.getSimpleValueType().getVectorMinNumElements() >= 2 &&
V2.getSimpleValueType().getVectorMinNumElements() >= 2) {
SDValue Lo = lowerZvzipVUNZIP(Opc, V1, DL, DAG, Subtarget);
@@ -6839,8 +6834,7 @@ SDValue RISCVTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
// Prefer vzip if available.
// TODO: Extend to matching vzip if EvenSrc and OddSrc allow.
if (Subtarget.hasStdExtZvzip() &&
- isLegalVTForZvzipInterleavedOperand(VT, Subtarget) &&
- isLegalVTForZvzipDeinterleavedOperand(HalfVT, Subtarget))
+ isLegalVTForZvzipInterleavedOperand(VT, Subtarget))
return lowerZvzipVZIP(EvenV, OddV, DL, DAG, Subtarget);
return getWideningInterleave(EvenV, OddV, DL, DAG, Subtarget);
}
@@ -13527,8 +13521,7 @@ SDValue RISCVTargetLowering::lowerVECTOR_DEINTERLEAVE(SDValue Op,
MVT VT = Op->getSimpleValueType(0);
MVT NewVT = VT.getDoubleNumVectorElementsVT();
if (isTypeLegal(NewVT) &&
- isLegalVTForZvzipDeinterleavedOperand(VT, Subtarget) &&
- isLegalVTForZvzipInterleavedOperand(NewVT, Subtarget)) {
+ isLegalVTForZvzipDeinterleavedOperand(VT, Subtarget)) {
SDValue V1 = Op->getOperand(0);
SDValue V2 = Op->getOperand(1);
SDValue V = DAG.getNode(ISD::CONCAT_VECTORS, DL, NewVT, V1, V2);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index a60d11c8172b8..41332701ffcff 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -597,6 +597,16 @@ class VALUVs2<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr>
: RVInstVUnary<funct6, vs1, opv, (outs VR:$vd),
(ins VR:$vs2, VMaskOp:$vm),
opcodestr, "$vd, $vs2$vm">;
+
+// op vd, vs2 (always without mask, use vs1 as instruction encoding)
+class VALUVs2NoVm<bits<6> funct6, bits<5> vs1, RISCVVFormat opv,
+ string opcodestr>
+ : RVInstVUnary<funct6, vs1, opv, (outs VR:$vd), (ins VR:$vs2),
+ opcodestr, "$vd, $vs2"> {
+ let vm = 1;
+
+ let VMConstraint = false;
+}
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 0264295c247fe..d772535a2cffb 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -782,6 +782,28 @@ class VPatUnaryVL_V<SDPatternOperator vop,
op1_reg_class:$rs2,
(mask_type VMV0:$vm), GPR:$vl, log2sew, TAIL_AGNOSTIC)>;
+class VPatUnaryVLNoMask_V<SDPatternOperator vop,
+ string instruction_name,
+ string suffix,
+ ValueType result_type,
+ ValueType op1_type,
+ int log2sew,
+ LMULInfo vlmul,
+ VReg result_reg_class,
+ VReg op1_reg_class,
+ bit isSEWAware = 0>
+ : Pat<(result_type (vop
+ (op1_type op1_reg_class:$rs2),
+ (result_type result_reg_class:$passthru),
+ VLOpFrag)),
+ (!cast<Instruction>(
+ !if(isSEWAware,
+ instruction_name#"_"#suffix#"_"#vlmul.MX#"_E"#!shl(1, log2sew),
+ instruction_name#"_"#suffix#"_"#vlmul.MX))
+ result_reg_class:$passthru,
+ op1_reg_class:$rs2,
+ GPR:$vl, log2sew, TAIL_AGNOSTIC)>;
+
class VPatBinaryVL_V<SDPatternOperator vop,
string instruction_name,
string suffix,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvzip.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvzip.td
index 903294cacb6f6..b140689ebd037 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvzip.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvzip.td
@@ -15,27 +15,20 @@
// Instructions
//===----------------------------------------------------------------------===//
-class VALUVs2NoVm<bits<6> funct6, bits<5> vs1, RISCVVFormat opv,
- string opcodestr>
- : RVInstVUnary<funct6, vs1, opv, (outs VR:$vd), (ins VR:$vs2), opcodestr,
- "$vd, $vs2"> {
- let vm = 1;
- let VMConstraint = false;
- let hasSideEffects = 0;
- let mayLoad = 0;
- let mayStore = 0;
-}
-
-let Predicates = [HasStdExtZvzip], Constraints = "@earlyclobber $vd" in {
- let VS1VS2Constraint = WidenV in
- def VZIP_VV : VALUVV<0b111110, OPMVV, "vzip.vv">;
+let Predicates = [HasStdExtZvzip] in {
+ let Constraints = "@earlyclobber $vd" in {
+ let VS1VS2Constraint = WidenV in
+ def VZIP_VV : VALUVV<0b111110, OPMVV, "vzip.vv">;
+ }
def VUNZIPE_V : VALUVs2NoVm<0b010010, 0b01011, OPMVV, "vunzipe.v">;
def VUNZIPO_V : VALUVs2NoVm<0b010010, 0b01111, OPMVV, "vunzipo.v">;
- let VS1VS2Constraint = Vrgather in {
- def VPAIRE_VV : VALUVV<0b001111, OPIVV, "vpaire.vv">;
- def VPAIRO_VV : VALUVV<0b001111, OPMVV, "vpairo.vv">;
+ let Constraints = "@earlyclobber $vd" in {
+ let VS1VS2Constraint = Vrgather in {
+ def VPAIRE_VV : VALUVV<0b001111, OPIVV, "vpaire.vv">;
+ def VPAIRO_VV : VALUVV<0b001111, OPMVV, "vpairo.vv">;
+ }
}
} // Predicates = [HasStdExtZvzip]
@@ -90,46 +83,38 @@ defset list<VTypeInfoToWide> AllZvzipVectors = {
multiclass VPseudoVZIP {
foreach m = MxListW in {
- defvar wideM = !cast<LMULInfo>("V_" # octuple_to_str<!shl(m.octuple, 1)>.ret);
- let VLMul = wideM.value, isCommutable = 0 in {
- def "_VV_" # m.MX : VPseudoBinaryNoMaskPolicy<m.wvrclass, m.vrclass,
- m.vrclass,
- "@earlyclobber $rd",
- TargetConstraintType=3>,
- SchedBinary<"WriteVIWALUV", "ReadVIWALUV",
- "ReadVIWALUV", m.MX,
- forcePassthruRead=true>;
- def "_VV_" # m.MX # "_MASK" :
- VPseudoBinaryMaskPolicy<m.wvrclass, m.vrclass, m.vrclass,
- "@earlyclobber $rd",
- TargetConstraintType=3>,
- RISCVMaskedPseudo<MaskIdx=3>,
- SchedBinary<"WriteVIWALUV", "ReadVIWALUV", "ReadVIWALUV", m.MX,
- forcePassthruRead=true>;
- }
+ defvar wm = !cast<LMULInfo>("V_" # octuple_to_str<!shl(m.octuple, 1)>.ret);
+ defm "_VV" : VPseudoBinary<wm.vrclass, m.vrclass, m.vrclass, wm,
+ "@earlyclobber $rd", TargetConstraintType=3>,
+ SchedBinary<"WriteVIWALUV", "ReadVIWALUV", "ReadVIWALUV",
+ m.MX, forcePassthruRead=true>;
}
}
+// vunzipe.v/vunzipo.v is narrowing-like and don't need @earlyclobber
+// if the source has an LMUL <= 1. The destination register group
+// can overlap with the lowest-numbered part of the source register group.
multiclass VPseudoVUNZIP {
foreach m = MxListW in {
- defvar mx = m.MX;
- defvar wideM = !cast<LMULInfo>("V_" # octuple_to_str<!shl(m.octuple, 1)>.ret);
- let VLMul = wideM.value in {
- def "_V_" # mx : VPseudoUnaryNoMask<m.vrclass, m.wvrclass,
- TargetConstraintType=2>,
- SchedUnary<"WriteVIALUV", "ReadVIALUV", mx,
- forcePassthruRead=true>;
+ defvar wm = !cast<LMULInfo>("V_" # octuple_to_str<!shl(m.octuple, 1)>.ret);
+ let VLMul = wm.value in {
+ def "_V_" # wm.MX : VPseudoUnaryNoMask<m.vrclass, wm.vrclass,
+ !if(!ge(m.octuple, 8), "@earlyclobber $rd", ""),
+ TargetConstraintType=2>,
+ SchedUnary<"WriteVIALUV", "ReadVIALUV", m.MX,
+ forcePassthruRead=true>;
}
}
}
-let Predicates = [HasStdExtZvzip],
- Constraints = "@earlyclobber $rd, $rd = $passthru" in {
+let Predicates = [HasStdExtZvzip] in {
defm PseudoVZIP : VPseudoVZIP;
defm PseudoVUNZIPE : VPseudoVUNZIP;
defm PseudoVUNZIPO : VPseudoVUNZIP;
- defm PseudoVPAIRE : VPseudoVALU_VV;
- defm PseudoVPAIRO : VPseudoVALU_VV;
+ let Constraints = "@earlyclobber $rd, $rd = $passthru" in {
+ defm PseudoVPAIRE : VPseudoVALU_VV;
+ defm PseudoVPAIRO : VPseudoVALU_VV;
+ }
}
multiclass VPatVUnzipIntrinsic<string intrinsic_name,
@@ -137,31 +122,25 @@ multiclass VPatVUnzipIntrinsic<string intrinsic_name,
foreach VtiToWti = AllZvzipVectors in {
defvar vti = VtiToWti.Vti;
defvar wti = VtiToWti.Wti;
- let Predicates = !listconcat(GetVTypeMinimalPredicates<wti>.Predicates,
+ let Predicates = !listconcat(GetVTypeMinimalPredicates<vti>.Predicates,
[HasStdExtZvzip]) in {
def : VPatUnaryNoMask<intrinsic_name, instruction_name, "V",
vti.Vector, wti.Vector, vti.Log2SEW,
- vti.LMul, vti.RegClass, wti.RegClass>;
+ wti.LMul, vti.RegClass, wti.RegClass>;
}
}
}
-multiclass VPatVZipIntrinsic<string intrinsic_name, string instruction_name> {
+multiclass VPatVZipIntrinsic<string intrinsic_name,
+ string instruction_name> {
foreach VtiToWti = AllZvzipVectors in {
defvar vti = VtiToWti.Vti;
defvar wti = VtiToWti.Wti;
- let Predicates = !listconcat(GetVTypeMinimalPredicates<wti>.Predicates,
+ let Predicates = !listconcat(GetVTypeMinimalPredicates<vti>.Predicates,
[HasStdExtZvzip]) in {
- def : VPatBinaryNoMaskTU<intrinsic_name,
- instruction_name # "_VV_" # vti.LMul.MX,
- wti.Vector, vti.Vector, vti.Vector,
- vti.Log2SEW, wti.RegClass, vti.RegClass,
- vti.RegClass>;
- def : VPatBinaryMaskPolicy<intrinsic_name,
- instruction_name # "_VV_" # vti.LMul.MX,
- wti.Vector, vti.Vector, vti.Vector, wti.Mask,
- vti.Log2SEW, wti.RegClass, vti.RegClass,
- vti.RegClass>;
+ defm : VPatBinary<intrinsic_name, instruction_name # "_VV_" # wti.LMul.MX,
+ wti.Vector, vti.Vector, vti.Vector, wti.Mask,
+ vti.Log2SEW, wti.RegClass, vti.RegClass, vti.RegClass>;
}
}
}
@@ -185,13 +164,11 @@ def SDT_RISCVZip_VL : SDTypeProfile<1, 5, [SDTCisVec<0>, SDTCisVec<1>,
SDTCisSameNumEltsAs<0, 4>,
SDTCisVT<5, XLenVT>]>;
-// (vd (op vs2, passthru, mask, vl))
-def SDT_RISCVUnzip_VL : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisVec<1>,
+// (vd (op vs2, passthru, vl))
+def SDT_RISCVUnzip_VL : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
SDTCisSubVecOfVec<0, 1>,
SDTCisSameAs<0, 2>,
- SDTCVecEltisVT<3, i1>,
- SDTCisSameNumEltsAs<0, 3>,
- SDTCisVT<4, XLenVT>]>;
+ SDTCisVT<3, XLenVT>]>;
def SDT_RISCVVecBinOp_VL : SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>,
SDTCisSameAs<0, 2>,
@@ -205,25 +182,23 @@ let HasPassthruOp = true, HasMaskOp = true in {
def vpaire_vl : RVSDNode<"VPAIRE_VL", SDT_RISCVVecBinOp_VL>;
def vpairo_vl : RVSDNode<"VPAIRO_VL", SDT_RISCVVecBinOp_VL>;
def vzip_vl : RVSDNode<"VZIP_VL", SDT_RISCVZip_VL>;
+} // HasPassthruOp = true, HasMaskOp = true
+
+let HasPassthruOp = true in {
def vunzipe_vl : RVSDNode<"VUNZIPE_VL", SDT_RISCVUnzip_VL>;
def vunzipo_vl : RVSDNode<"VUNZIPO_VL", SDT_RISCVUnzip_VL>;
-} // HasPassthruOp = true, HasMaskOp = true
+} // HasPassthruOp = true
multiclass VPatVZIP<SDPatternOperator vop, string instruction_name> {
foreach VtiToWti = AllZvzipVectors in {
defvar vti = VtiToWti.Vti;
defvar wti = VtiToWti.Wti;
let Predicates = !listconcat([HasStdExtZvzip],
- GetVTypeMinimalPredicates<wti>.Predicates) in {
- def : Pat<(wti.Vector (vop (vti.Vector vti.RegClass:$rs1),
- (vti.Vector vti.RegClass:$rs2),
- wti.RegClass:$passthru,
- (wti.Mask VMV0:$vm), VLOpFrag)),
- (!cast<Instruction>(instruction_name # "_VV_" # vti.LMul.MX #
- "_MASK")
- wti.RegClass:$passthru, vti.RegClass:$rs1,
- vti.RegClass:$rs2, (wti.Mask VMV0:$vm), GPR:$vl,
- vti.Log2SEW, TAIL_AGNOSTIC)>;
+ GetVTypeMinimalPredicates<vti>.Predicates) in {
+ def : VPatBinaryVL_V<vop, instruction_name, "VV",
+ wti.Vector, vti.Vector, vti.Vector, wti.Mask,
+ vti.Log2SEW, wti.LMul, wti.RegClass, vti.RegClass,
+ vti.RegClass>;
}
}
}
@@ -233,13 +208,10 @@ multiclass VPatVUNZIP<SDPatternOperator op, string instruction_name> {
defvar vti = VtiToWti.Vti;
defvar wti = VtiToWti.Wti;
let Predicates = !listconcat([HasStdExtZvzip],
- GetVTypeMinimalPredicates<wti>.Predicates) in {
- def : Pat<(vti.Vector (op (wti.Vector wti.RegClass:$rs2),
- vti.RegClass:$passthru, (vti.Mask true_mask),
- VLOpFrag)),
- (!cast<Instruction>(instruction_name # "_V_" # vti.LMul.MX)
- vti.RegClass:$passthru, wti.RegClass:$rs2, GPR:$vl,
- vti.Log2SEW, TU_MU)>;
+ GetVTypeMinimalPredicates<vti>.Predicates) in {
+ def : VPatUnaryVLNoMask_V<op, instruction_name, "V",
+ vti.Vector, wti.Vector, vti.Log2SEW,
+ wti.LMul, vti.RegClass, wti.RegClass>;
}
}
}
diff --git a/llvm/test/MC/RISCV/rvv/zvzip-invalid.s b/llvm/test/MC/RISCV/rvv/zvzip-invalid.s
index 917984d31ddda..bfee29a6c27d7 100644
--- a/llvm/test/MC/RISCV/rvv/zvzip-invalid.s
+++ b/llvm/test/MC/RISCV/rvv/zvzip-invalid.s
@@ -26,9 +26,9 @@ vpairo.vv v0, v2, v4, v0.t
# CHECK-ERROR-LABEL: vpairo.vv v0, v2, v4, v0.t
vunzipe.v v1, v2, v0.t
-# CHECK-ERROR: invalid operand for instruction
+# CHECK-ERROR: unexpected extra operand for instruction
# CHECK-ERROR-LABEL: vunzipe.v v1, v2, v0.t
vunzipo.v v1, v2, v0.t
-# CHECK-ERROR: invalid operand for instruction
+# CHECK-ERROR: unexpected extra operand for instruction
# CHECK-ERROR-LABEL: vunzipo.v v1, v2, v0.t
diff --git a/llvm/test/MC/RISCV/rvv/zvzip.s b/llvm/test/MC/RISCV/rvv/zvzip.s
index ba9cd0f4068f7..77bfcf5f9a939 100644
--- a/llvm/test/MC/RISCV/rvv/zvzip.s
+++ b/llvm/test/MC/RISCV/rvv/zvzip.s
@@ -40,3 +40,19 @@ vunzipe.v v1, v2
# CHECK-ASM-AND-OBJ: vunzipo.v v1, v2
# CHECK-ASM: encoding: [0xd7,0xa0,0x27,0x4a]
vunzipo.v v1, v2
+
+# CHECK-ASM-AND-OBJ: vunzipe.v v4, v4
+# CHECK-ASM: encoding: [0x57,0xa2,0x45,0x4a]
+vunzipe.v v4, v4
+
+# CHECK-ASM-AND-OBJ: vunzipo.v v4, v4
+# CHECK-ASM: encoding: [0x57,0xa2,0x47,0x4a]
+vunzipo.v v4, v4
+
+# CHECK-ASM-AND-OBJ: vunzipe.v v0, v0
+# CHECK-ASM: encoding: [0x57,0xa0,0x05,0x4a]
+vunzipe.v v0, v0
+
+# CHECK-ASM-AND-OBJ: vunzipo.v v0, v0
+# CHECK-ASM: encoding: [0x57,0xa0,0x07,0x4a]
+vunzipo.v v0, v0
>From 9b9bd2d0062c9fe81de71c49fec6193095ca5a04 Mon Sep 17 00:00:00 2001
From: liumingliang <liumingliang.dev at bytedance.com>
Date: Tue, 21 Jul 2026 11:19:59 +0800
Subject: [PATCH 3/3] [RISCV] Fix the constraint of Zvzip 0.2
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 38 +-
llvm/lib/Target/RISCV/RISCVInstrInfoZvzip.td | 16 +-
.../fixed-vectors-shuffle-deinterleave2.ll | 61 +--
.../rvv/fixed-vectors-shuffle-zvzip-zve32x.ll | 422 ++++++++++++++++++
4 files changed, 488 insertions(+), 49 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zvzip-zve32x.ll
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 0498fb5c424b2..457ee1d523b7b 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -5327,13 +5327,29 @@ static SDValue getSingleShuffleSrc(MVT VT, SDValue V1, SDValue V2) {
return SDValue();
}
+static unsigned getLMULOctuple(MVT ContainerVT) {
+ assert(ContainerVT.isScalableVector() && "Expected scalable vector type");
+ unsigned MinSize = ContainerVT.getSizeInBits().getKnownMinValue();
+ if (ContainerVT.getVectorElementType() == MVT::i1)
+ MinSize *= 8;
+ assert(isPowerOf2_32(MinSize) && MinSize >= 8 && MinSize <= 512 &&
+ "Unexpected LMUL");
+ return MinSize / (RISCV::RVVBitsPerBlock / 8);
+}
+
static bool
isLegalVTForZvzipDeinterleavedOperand(MVT VT, const RISCVSubtarget &Subtarget) {
MVT ContainerVT = VT;
if (VT.isFixedLengthVector())
ContainerVT = getContainerForFixedLengthVector(VT, Subtarget);
// Determine LMUL of the container vector.
- return RISCVTargetLowering::getLMUL(ContainerVT) != RISCVVType::LMUL_8;
+ unsigned EltBits = VT.getScalarSizeInBits();
+ unsigned LMULOctuple = getLMULOctuple(ContainerVT);
+ // The interleaved operand is described by the vtype LMUL. Since VT is a
+ // deinterleaved operand, check the constraint against twice VT's LMUL.
+ return EltBits * 8 <= LMULOctuple * std::min(Subtarget.getELen(),
+ Subtarget.getRealMinVLen()) &&
+ RISCVTargetLowering::getLMUL(ContainerVT) != RISCVVType::LMUL_8;
}
static bool
@@ -5341,7 +5357,11 @@ isLegalVTForZvzipInterleavedOperand(MVT VT, const RISCVSubtarget &Subtarget) {
MVT ContainerVT = VT;
if (VT.isFixedLengthVector())
ContainerVT = getContainerForFixedLengthVector(VT, Subtarget);
- return RISCVTargetLowering::getLMUL(ContainerVT) != RISCVVType::LMUL_F8;
+ unsigned EltBits = VT.getScalarSizeInBits();
+ unsigned LMULOctuple = getLMULOctuple(ContainerVT);
+ // Perform 2 * SEW <= LMUL * min(ELEN, VLEN) check.
+ return EltBits * 16 <= LMULOctuple * std::min(Subtarget.getELen(),
+ Subtarget.getRealMinVLen());
}
/// Is this shuffle interleaving contiguous elements from one vector into the
@@ -5880,20 +5900,13 @@ static SDValue lowerZvzipVUNZIP(unsigned Opc, SDValue Op, const SDLoc &DL,
MVT ContainerVT = IntVT;
if (VT.isFixedLengthVector()) {
ContainerVT = getContainerForFixedLengthVector(IntVT, Subtarget);
- // For E64 with LMUL <= 1, we can't represent a smaller fractional LMUL for
- // the result (LMUL <= 1/2 is not valid for E64). We must widen the input
- // container to at least LMUL=2 so the result can be LMUL=1.
- if (ContainerVT.getVectorElementType() == MVT::i64 &&
- RISCVTargetLowering::getLMUL(ContainerVT) == RISCVVType::LMUL_1) {
- ContainerVT = MVT::getScalableVectorVT(MVT::i64, 2);
- }
Op = convertToScalableVector(ContainerVT, Op, DAG, Subtarget);
}
MVT ResVT = ContainerVT.getHalfNumVectorElementsVT();
MVT HalfVT = VT.getHalfNumVectorElementsVT();
MVT HalfIntVT = IntVT.getHalfNumVectorElementsVT();
- auto [_, VL] = getDefaultVLOps(IntVT, ContainerVT, DL, DAG, Subtarget);
+ SDValue VL = getDefaultVLOps(IntVT, ContainerVT, DL, DAG, Subtarget).second;
SDValue Passthru = DAG.getUNDEF(ResVT);
SDValue Res = DAG.getNode(Opc, DL, ResVT, Op, Passthru, VL);
if (HalfIntVT.isFixedLengthVector())
@@ -6781,9 +6794,8 @@ SDValue RISCVTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
}
if (UsesBothSources &&
- isLegalVTForZvzipInterleavedOperand(
- V1.getSimpleValueType().getDoubleNumVectorElementsVT(),
- Subtarget) &&
+ isLegalVTForZvzipInterleavedOperand(V1.getSimpleValueType(),
+ Subtarget) &&
V1.getSimpleValueType().getVectorMinNumElements() >= 2 &&
V2.getSimpleValueType().getVectorMinNumElements() >= 2) {
SDValue Lo = lowerZvzipVUNZIP(Opc, V1, DL, DAG, Subtarget);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvzip.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvzip.td
index b140689ebd037..24220e464a763 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvzip.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvzip.td
@@ -117,13 +117,13 @@ let Predicates = [HasStdExtZvzip] in {
}
}
+let Predicates = [HasStdExtZvzip] in {
multiclass VPatVUnzipIntrinsic<string intrinsic_name,
string instruction_name> {
foreach VtiToWti = AllZvzipVectors in {
defvar vti = VtiToWti.Vti;
defvar wti = VtiToWti.Wti;
- let Predicates = !listconcat(GetVTypeMinimalPredicates<vti>.Predicates,
- [HasStdExtZvzip]) in {
+ let append Predicates = GetVTypeMinimalPredicates<vti>.Predicates in {
def : VPatUnaryNoMask<intrinsic_name, instruction_name, "V",
vti.Vector, wti.Vector, vti.Log2SEW,
wti.LMul, vti.RegClass, wti.RegClass>;
@@ -136,14 +136,14 @@ multiclass VPatVZipIntrinsic<string intrinsic_name,
foreach VtiToWti = AllZvzipVectors in {
defvar vti = VtiToWti.Vti;
defvar wti = VtiToWti.Wti;
- let Predicates = !listconcat(GetVTypeMinimalPredicates<vti>.Predicates,
- [HasStdExtZvzip]) in {
+ let append Predicates = GetVTypeMinimalPredicates<vti>.Predicates in {
defm : VPatBinary<intrinsic_name, instruction_name # "_VV_" # wti.LMul.MX,
wti.Vector, vti.Vector, vti.Vector, wti.Mask,
vti.Log2SEW, wti.RegClass, vti.RegClass, vti.RegClass>;
}
}
}
+} // Predicates = [HasStdExtZvzip]
defm : VPatVUnzipIntrinsic<"int_riscv_vunzipe", "PseudoVUNZIPE">;
defm : VPatVUnzipIntrinsic<"int_riscv_vunzipo", "PseudoVUNZIPO">;
@@ -189,12 +189,12 @@ def vunzipe_vl : RVSDNode<"VUNZIPE_VL", SDT_RISCVUnzip_VL>;
def vunzipo_vl : RVSDNode<"VUNZIPO_VL", SDT_RISCVUnzip_VL>;
} // HasPassthruOp = true
+let Predicates = [HasStdExtZvzip] in {
multiclass VPatVZIP<SDPatternOperator vop, string instruction_name> {
foreach VtiToWti = AllZvzipVectors in {
defvar vti = VtiToWti.Vti;
defvar wti = VtiToWti.Wti;
- let Predicates = !listconcat([HasStdExtZvzip],
- GetVTypeMinimalPredicates<vti>.Predicates) in {
+ let append Predicates = GetVTypeMinimalPredicates<vti>.Predicates in {
def : VPatBinaryVL_V<vop, instruction_name, "VV",
wti.Vector, vti.Vector, vti.Vector, wti.Mask,
vti.Log2SEW, wti.LMul, wti.RegClass, vti.RegClass,
@@ -207,14 +207,14 @@ multiclass VPatVUNZIP<SDPatternOperator op, string instruction_name> {
foreach VtiToWti = AllZvzipVectors in {
defvar vti = VtiToWti.Vti;
defvar wti = VtiToWti.Wti;
- let Predicates = !listconcat([HasStdExtZvzip],
- GetVTypeMinimalPredicates<vti>.Predicates) in {
+ let append Predicates = GetVTypeMinimalPredicates<vti>.Predicates in {
def : VPatUnaryVLNoMask_V<op, instruction_name, "V",
vti.Vector, wti.Vector, vti.Log2SEW,
wti.LMul, vti.RegClass, wti.RegClass>;
}
}
}
+} // Predicates = [HasStdExtZvzip]
defm : VPatVZIP<vzip_vl, "PseudoVZIP">;
defm : VPatVUNZIP<vunzipe_vl, "PseudoVUNZIPE">;
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
index ff8ce7f3ca996..92b00d61e5477 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
@@ -414,10 +414,10 @@ define void @vnsrl_0_i64(ptr %in, ptr %out) {
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
; ZVZIP-NEXT: vle64.v v8, (a0)
-; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; ZVZIP-NEXT: vunzipe.v v10, v8
; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; ZVZIP-NEXT: vse64.v v10, (a1)
+; ZVZIP-NEXT: vslidedown.vi v9, v8, 2
+; ZVZIP-NEXT: vslideup.vi v8, v9, 1
+; ZVZIP-NEXT: vse64.v v8, (a1)
; ZVZIP-NEXT: ret
entry:
%0 = load <4 x i64>, ptr %in, align 8
@@ -450,9 +450,9 @@ define void @vnsrl_64_i64(ptr %in, ptr %out) {
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
; ZVZIP-NEXT: vle64.v v8, (a0)
-; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; ZVZIP-NEXT: vunzipo.v v10, v8
; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v9, v8, 2
+; ZVZIP-NEXT: vpairo.vv v10, v8, v9
; ZVZIP-NEXT: vse64.v v10, (a1)
; ZVZIP-NEXT: ret
entry:
@@ -485,10 +485,10 @@ define void @vnsrl_0_double(ptr %in, ptr %out) {
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
; ZVZIP-NEXT: vle64.v v8, (a0)
-; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; ZVZIP-NEXT: vunzipe.v v10, v8
; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; ZVZIP-NEXT: vse64.v v10, (a1)
+; ZVZIP-NEXT: vslidedown.vi v9, v8, 2
+; ZVZIP-NEXT: vslideup.vi v8, v9, 1
+; ZVZIP-NEXT: vse64.v v8, (a1)
; ZVZIP-NEXT: ret
entry:
%0 = load <4 x double>, ptr %in, align 8
@@ -521,9 +521,9 @@ define void @vnsrl_64_double(ptr %in, ptr %out) {
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
; ZVZIP-NEXT: vle64.v v8, (a0)
-; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; ZVZIP-NEXT: vunzipo.v v10, v8
; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v9, v8, 2
+; ZVZIP-NEXT: vpairo.vv v10, v8, v9
; ZVZIP-NEXT: vse64.v v10, (a1)
; ZVZIP-NEXT: ret
entry:
@@ -1529,13 +1529,15 @@ define <4 x i64> @unzip2a_dual_v4i64(<4 x i64> %a, <4 x i64> %b) {
;
; ZVZIP-LABEL: unzip2a_dual_v4i64:
; ZVZIP: # %bb.0: # %entry
-; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v9
-; ZVZIP-NEXT: vunzipe.v v12, v10
-; ZVZIP-NEXT: vunzipe.v v10, v8
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, mu
+; ZVZIP-NEXT: vmv.v.i v0, 8
+; ZVZIP-NEXT: vslideup.vi v10, v9, 2
+; ZVZIP-NEXT: vslideup.vi v10, v9, 1, v0.t
+; ZVZIP-NEXT: vmv.v.i v0, 12
+; ZVZIP-NEXT: vsetivli zero, 8, e64, m2, ta, ma
+; ZVZIP-NEXT: vunzipe.v v11, v8
; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
-; ZVZIP-NEXT: vslideup.vi v10, v12, 2
-; ZVZIP-NEXT: vmv.v.v v8, v10
+; ZVZIP-NEXT: vmerge.vvm v8, v11, v10, v0
; ZVZIP-NEXT: ret
entry:
%c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
@@ -1763,13 +1765,14 @@ define <4 x i64> @unzip2a_dual_v4i64_exact_nf2(<4 x i64> %a, <4 x i64> %b) vscal
;
; ZVZIP-LABEL: unzip2a_dual_v4i64_exact_nf2:
; ZVZIP: # %bb.0: # %entry
-; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; ZVZIP-NEXT: vmv1r.v v10, v9
-; ZVZIP-NEXT: vunzipe.v v12, v10
-; ZVZIP-NEXT: vunzipe.v v10, v8
-; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, tu, ma
-; ZVZIP-NEXT: vslideup.vi v10, v12, 2
-; ZVZIP-NEXT: vmv1r.v v8, v10
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, mu
+; ZVZIP-NEXT: vmv.v.i v0, 8
+; ZVZIP-NEXT: vslideup.vi v10, v9, 2
+; ZVZIP-NEXT: vslideup.vi v10, v9, 1, v0.t
+; ZVZIP-NEXT: vmv.v.i v0, 2
+; ZVZIP-NEXT: vslidedown.vi v8, v8, 1, v0.t
+; ZVZIP-NEXT: vmv.v.i v0, 12
+; ZVZIP-NEXT: vmerge.vvm v8, v8, v10, v0
; ZVZIP-NEXT: ret
entry:
%c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
@@ -1943,13 +1946,15 @@ define <4 x i64> @unzip2b_dual_v4i64(<4 x i64> %a, <4 x i64> %b) {
;
; ZVZIP-LABEL: unzip2b_dual_v4i64:
; ZVZIP: # %bb.0: # %entry
-; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, mu
+; ZVZIP-NEXT: vmv.v.i v0, 4
; ZVZIP-NEXT: vmv1r.v v10, v9
-; ZVZIP-NEXT: vunzipo.v v12, v10
-; ZVZIP-NEXT: vunzipo.v v10, v8
+; ZVZIP-NEXT: vslideup.vi v10, v9, 1, v0.t
+; ZVZIP-NEXT: vmv.v.i v0, 12
+; ZVZIP-NEXT: vsetivli zero, 8, e64, m2, ta, ma
+; ZVZIP-NEXT: vunzipo.v v11, v8
; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
-; ZVZIP-NEXT: vslideup.vi v10, v12, 2
-; ZVZIP-NEXT: vmv.v.v v8, v10
+; ZVZIP-NEXT: vmerge.vvm v8, v11, v10, v0
; ZVZIP-NEXT: ret
entry:
%c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zvzip-zve32x.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zvzip-zve32x.ll
new file mode 100644
index 0000000000000..000859fafc533
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zvzip-zve32x.ll
@@ -0,0 +1,422 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+f,+zve32x,+zve32f,+zvfh,+zvl64b,+experimental-zvzip \
+; RUN: -lower-interleaved-accesses=false -verify-machineinstrs \
+; RUN: | FileCheck %s --check-prefix=ZVL64B
+; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+f,+zve32x,+zve32f,+zvfh,+zvl128b,+experimental-zvzip \
+; RUN: -lower-interleaved-accesses=false -verify-machineinstrs \
+; RUN: | FileCheck %s --check-prefix=ZVL128B
+
+define void @deinterleave_v4i32_even(ptr %in, ptr %out) {
+; ZVL64B-LABEL: deinterleave_v4i32_even:
+; ZVL64B: # %bb.0: # %entry
+; ZVL64B-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; ZVL64B-NEXT: vle32.v v8, (a0)
+; ZVL64B-NEXT: vunzipe.v v10, v8
+; ZVL64B-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; ZVL64B-NEXT: vse32.v v10, (a1)
+; ZVL64B-NEXT: ret
+;
+; ZVL128B-LABEL: deinterleave_v4i32_even:
+; ZVL128B: # %bb.0: # %entry
+; ZVL128B-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVL128B-NEXT: vle32.v v8, (a0)
+; ZVL128B-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; ZVL128B-NEXT: vslidedown.vi v9, v8, 2
+; ZVL128B-NEXT: vslideup.vi v8, v9, 1
+; ZVL128B-NEXT: vse32.v v8, (a1)
+; ZVL128B-NEXT: ret
+entry:
+ %v = load <4 x i32>, ptr %in, align 4
+ %s = shufflevector <4 x i32> %v, <4 x i32> poison, <2 x i32> <i32 0, i32 2>
+ store <2 x i32> %s, ptr %out, align 4
+ ret void
+}
+
+define void @deinterleave_v4i32_odd(ptr %in, ptr %out) {
+; ZVL64B-LABEL: deinterleave_v4i32_odd:
+; ZVL64B: # %bb.0: # %entry
+; ZVL64B-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; ZVL64B-NEXT: vle32.v v8, (a0)
+; ZVL64B-NEXT: vunzipo.v v10, v8
+; ZVL64B-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; ZVL64B-NEXT: vse32.v v10, (a1)
+; ZVL64B-NEXT: ret
+;
+; ZVL128B-LABEL: deinterleave_v4i32_odd:
+; ZVL128B: # %bb.0: # %entry
+; ZVL128B-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVL128B-NEXT: vle32.v v8, (a0)
+; ZVL128B-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; ZVL128B-NEXT: vslidedown.vi v9, v8, 2
+; ZVL128B-NEXT: vpairo.vv v10, v8, v9
+; ZVL128B-NEXT: vse32.v v10, (a1)
+; ZVL128B-NEXT: ret
+entry:
+ %v = load <4 x i32>, ptr %in, align 4
+ %s = shufflevector <4 x i32> %v, <4 x i32> poison, <2 x i32> <i32 1, i32 3>
+ store <2 x i32> %s, ptr %out, align 4
+ ret void
+}
+
+define void @interleave_v2i32(ptr %pa, ptr %pb, ptr %out) {
+; ZVL64B-LABEL: interleave_v2i32:
+; ZVL64B: # %bb.0: # %entry
+; ZVL64B-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; ZVL64B-NEXT: vle32.v v10, (a0)
+; ZVL64B-NEXT: vle32.v v11, (a1)
+; ZVL64B-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; ZVL64B-NEXT: vzip.vv v8, v10, v11
+; ZVL64B-NEXT: vse32.v v8, (a2)
+; ZVL64B-NEXT: ret
+;
+; ZVL128B-LABEL: interleave_v2i32:
+; ZVL128B: # %bb.0: # %entry
+; ZVL128B-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; ZVL128B-NEXT: vle32.v v8, (a1)
+; ZVL128B-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVL128B-NEXT: vslideup.vi v9, v8, 1
+; ZVL128B-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; ZVL128B-NEXT: vle32.v v10, (a0)
+; ZVL128B-NEXT: vmv.v.i v0, 10
+; ZVL128B-NEXT: vmv.v.v v11, v10
+; ZVL128B-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVL128B-NEXT: vslideup.vi v9, v8, 2
+; ZVL128B-NEXT: vslideup.vi v11, v10, 1
+; ZVL128B-NEXT: vmerge.vvm v8, v11, v9, v0
+; ZVL128B-NEXT: vse32.v v8, (a2)
+; ZVL128B-NEXT: ret
+entry:
+ %a = load <2 x i32>, ptr %pa, align 4
+ %b = load <2 x i32>, ptr %pb, align 4
+ %s = shufflevector <2 x i32> %a, <2 x i32> %b, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
+ store <4 x i32> %s, ptr %out, align 4
+ ret void
+}
+
+define void @deinterleave_v4i16_even(ptr %in, ptr %out) {
+; ZVL64B-LABEL: deinterleave_v4i16_even:
+; ZVL64B: # %bb.0: # %entry
+; ZVL64B-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; ZVL64B-NEXT: vle16.v v8, (a0)
+; ZVL64B-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; ZVL64B-NEXT: vnsrl.wi v8, v8, 0
+; ZVL64B-NEXT: vse16.v v8, (a1)
+; ZVL64B-NEXT: ret
+;
+; ZVL128B-LABEL: deinterleave_v4i16_even:
+; ZVL128B: # %bb.0: # %entry
+; ZVL128B-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVL128B-NEXT: vle16.v v8, (a0)
+; ZVL128B-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; ZVL128B-NEXT: vnsrl.wi v8, v8, 0
+; ZVL128B-NEXT: vse16.v v8, (a1)
+; ZVL128B-NEXT: ret
+entry:
+ %v = load <4 x i16>, ptr %in, align 2
+ %s = shufflevector <4 x i16> %v, <4 x i16> poison, <2 x i32> <i32 0, i32 2>
+ store <2 x i16> %s, ptr %out, align 2
+ ret void
+}
+
+define void @deinterleave_v4i16_odd(ptr %in, ptr %out) {
+; ZVL64B-LABEL: deinterleave_v4i16_odd:
+; ZVL64B: # %bb.0: # %entry
+; ZVL64B-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; ZVL64B-NEXT: vle16.v v8, (a0)
+; ZVL64B-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; ZVL64B-NEXT: vnsrl.wi v8, v8, 16
+; ZVL64B-NEXT: vse16.v v8, (a1)
+; ZVL64B-NEXT: ret
+;
+; ZVL128B-LABEL: deinterleave_v4i16_odd:
+; ZVL128B: # %bb.0: # %entry
+; ZVL128B-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVL128B-NEXT: vle16.v v8, (a0)
+; ZVL128B-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; ZVL128B-NEXT: vnsrl.wi v8, v8, 16
+; ZVL128B-NEXT: vse16.v v8, (a1)
+; ZVL128B-NEXT: ret
+entry:
+ %v = load <4 x i16>, ptr %in, align 2
+ %s = shufflevector <4 x i16> %v, <4 x i16> poison, <2 x i32> <i32 1, i32 3>
+ store <2 x i16> %s, ptr %out, align 2
+ ret void
+}
+
+define void @interleave_v2i16(ptr %pa, ptr %pb, ptr %out) {
+; ZVL64B-LABEL: interleave_v2i16:
+; ZVL64B: # %bb.0: # %entry
+; ZVL64B-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; ZVL64B-NEXT: vle16.v v8, (a0)
+; ZVL64B-NEXT: vle16.v v9, (a1)
+; ZVL64B-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; ZVL64B-NEXT: vzip.vv v10, v8, v9
+; ZVL64B-NEXT: vse16.v v10, (a2)
+; ZVL64B-NEXT: ret
+;
+; ZVL128B-LABEL: interleave_v2i16:
+; ZVL128B: # %bb.0: # %entry
+; ZVL128B-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; ZVL128B-NEXT: vle16.v v8, (a0)
+; ZVL128B-NEXT: vle16.v v9, (a1)
+; ZVL128B-NEXT: vwaddu.vv v10, v8, v9
+; ZVL128B-NEXT: li a0, -1
+; ZVL128B-NEXT: vwmaccu.vx v10, a0, v9
+; ZVL128B-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVL128B-NEXT: vse16.v v10, (a2)
+; ZVL128B-NEXT: ret
+entry:
+ %a = load <2 x i16>, ptr %pa, align 2
+ %b = load <2 x i16>, ptr %pb, align 2
+ %s = shufflevector <2 x i16> %a, <2 x i16> %b, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
+ store <4 x i16> %s, ptr %out, align 2
+ ret void
+}
+
+define void @deinterleave_v4i8_even(ptr %in, ptr %out) {
+; ZVL64B-LABEL: deinterleave_v4i8_even:
+; ZVL64B: # %bb.0: # %entry
+; ZVL64B-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; ZVL64B-NEXT: vle8.v v8, (a0)
+; ZVL64B-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; ZVL64B-NEXT: vnsrl.wi v8, v8, 0
+; ZVL64B-NEXT: vse8.v v8, (a1)
+; ZVL64B-NEXT: ret
+;
+; ZVL128B-LABEL: deinterleave_v4i8_even:
+; ZVL128B: # %bb.0: # %entry
+; ZVL128B-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; ZVL128B-NEXT: vle8.v v8, (a0)
+; ZVL128B-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; ZVL128B-NEXT: vnsrl.wi v8, v8, 0
+; ZVL128B-NEXT: vse8.v v8, (a1)
+; ZVL128B-NEXT: ret
+entry:
+ %v = load <4 x i8>, ptr %in, align 1
+ %s = shufflevector <4 x i8> %v, <4 x i8> poison, <2 x i32> <i32 0, i32 2>
+ store <2 x i8> %s, ptr %out, align 1
+ ret void
+}
+
+define void @deinterleave_v4i8_odd(ptr %in, ptr %out) {
+; ZVL64B-LABEL: deinterleave_v4i8_odd:
+; ZVL64B: # %bb.0: # %entry
+; ZVL64B-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; ZVL64B-NEXT: vle8.v v8, (a0)
+; ZVL64B-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; ZVL64B-NEXT: vnsrl.wi v8, v8, 8
+; ZVL64B-NEXT: vse8.v v8, (a1)
+; ZVL64B-NEXT: ret
+;
+; ZVL128B-LABEL: deinterleave_v4i8_odd:
+; ZVL128B: # %bb.0: # %entry
+; ZVL128B-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; ZVL128B-NEXT: vle8.v v8, (a0)
+; ZVL128B-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; ZVL128B-NEXT: vnsrl.wi v8, v8, 8
+; ZVL128B-NEXT: vse8.v v8, (a1)
+; ZVL128B-NEXT: ret
+entry:
+ %v = load <4 x i8>, ptr %in, align 1
+ %s = shufflevector <4 x i8> %v, <4 x i8> poison, <2 x i32> <i32 1, i32 3>
+ store <2 x i8> %s, ptr %out, align 1
+ ret void
+}
+
+define void @interleave_v2i8(ptr %pa, ptr %pb, ptr %out) {
+; ZVL64B-LABEL: interleave_v2i8:
+; ZVL64B: # %bb.0: # %entry
+; ZVL64B-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; ZVL64B-NEXT: vle8.v v8, (a0)
+; ZVL64B-NEXT: vle8.v v9, (a1)
+; ZVL64B-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; ZVL64B-NEXT: vzip.vv v10, v8, v9
+; ZVL64B-NEXT: vse8.v v10, (a2)
+; ZVL64B-NEXT: ret
+;
+; ZVL128B-LABEL: interleave_v2i8:
+; ZVL128B: # %bb.0: # %entry
+; ZVL128B-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; ZVL128B-NEXT: vle8.v v8, (a0)
+; ZVL128B-NEXT: vle8.v v9, (a1)
+; ZVL128B-NEXT: vwaddu.vv v10, v8, v9
+; ZVL128B-NEXT: li a0, -1
+; ZVL128B-NEXT: vwmaccu.vx v10, a0, v9
+; ZVL128B-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; ZVL128B-NEXT: vse8.v v10, (a2)
+; ZVL128B-NEXT: ret
+entry:
+ %a = load <2 x i8>, ptr %pa, align 1
+ %b = load <2 x i8>, ptr %pb, align 1
+ %s = shufflevector <2 x i8> %a, <2 x i8> %b, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
+ store <4 x i8> %s, ptr %out, align 1
+ ret void
+}
+
+define void @deinterleave_v4f32_even(ptr %in, ptr %out) {
+; ZVL64B-LABEL: deinterleave_v4f32_even:
+; ZVL64B: # %bb.0: # %entry
+; ZVL64B-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; ZVL64B-NEXT: vle32.v v8, (a0)
+; ZVL64B-NEXT: vunzipe.v v10, v8
+; ZVL64B-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; ZVL64B-NEXT: vse32.v v10, (a1)
+; ZVL64B-NEXT: ret
+;
+; ZVL128B-LABEL: deinterleave_v4f32_even:
+; ZVL128B: # %bb.0: # %entry
+; ZVL128B-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVL128B-NEXT: vle32.v v8, (a0)
+; ZVL128B-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; ZVL128B-NEXT: vslidedown.vi v9, v8, 2
+; ZVL128B-NEXT: vslideup.vi v8, v9, 1
+; ZVL128B-NEXT: vse32.v v8, (a1)
+; ZVL128B-NEXT: ret
+entry:
+ %v = load <4 x float>, ptr %in, align 4
+ %s = shufflevector <4 x float> %v, <4 x float> poison, <2 x i32> <i32 0, i32 2>
+ store <2 x float> %s, ptr %out, align 4
+ ret void
+}
+
+define void @deinterleave_v4f32_odd(ptr %in, ptr %out) {
+; ZVL64B-LABEL: deinterleave_v4f32_odd:
+; ZVL64B: # %bb.0: # %entry
+; ZVL64B-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; ZVL64B-NEXT: vle32.v v8, (a0)
+; ZVL64B-NEXT: vunzipo.v v10, v8
+; ZVL64B-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; ZVL64B-NEXT: vse32.v v10, (a1)
+; ZVL64B-NEXT: ret
+;
+; ZVL128B-LABEL: deinterleave_v4f32_odd:
+; ZVL128B: # %bb.0: # %entry
+; ZVL128B-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVL128B-NEXT: vle32.v v8, (a0)
+; ZVL128B-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; ZVL128B-NEXT: vslidedown.vi v9, v8, 2
+; ZVL128B-NEXT: vpairo.vv v10, v8, v9
+; ZVL128B-NEXT: vse32.v v10, (a1)
+; ZVL128B-NEXT: ret
+entry:
+ %v = load <4 x float>, ptr %in, align 4
+ %s = shufflevector <4 x float> %v, <4 x float> poison, <2 x i32> <i32 1, i32 3>
+ store <2 x float> %s, ptr %out, align 4
+ ret void
+}
+
+define void @interleave_v2f32(ptr %pa, ptr %pb, ptr %out) {
+; ZVL64B-LABEL: interleave_v2f32:
+; ZVL64B: # %bb.0: # %entry
+; ZVL64B-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; ZVL64B-NEXT: vle32.v v10, (a0)
+; ZVL64B-NEXT: vle32.v v11, (a1)
+; ZVL64B-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; ZVL64B-NEXT: vzip.vv v8, v10, v11
+; ZVL64B-NEXT: vse32.v v8, (a2)
+; ZVL64B-NEXT: ret
+;
+; ZVL128B-LABEL: interleave_v2f32:
+; ZVL128B: # %bb.0: # %entry
+; ZVL128B-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; ZVL128B-NEXT: vle32.v v8, (a1)
+; ZVL128B-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVL128B-NEXT: vslideup.vi v9, v8, 1
+; ZVL128B-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; ZVL128B-NEXT: vle32.v v10, (a0)
+; ZVL128B-NEXT: vmv.v.i v0, 10
+; ZVL128B-NEXT: vmv.v.v v11, v10
+; ZVL128B-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVL128B-NEXT: vslideup.vi v9, v8, 2
+; ZVL128B-NEXT: vslideup.vi v11, v10, 1
+; ZVL128B-NEXT: vmerge.vvm v8, v11, v9, v0
+; ZVL128B-NEXT: vse32.v v8, (a2)
+; ZVL128B-NEXT: ret
+entry:
+ %a = load <2 x float>, ptr %pa, align 4
+ %b = load <2 x float>, ptr %pb, align 4
+ %s = shufflevector <2 x float> %a, <2 x float> %b, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
+ store <4 x float> %s, ptr %out, align 4
+ ret void
+}
+
+define void @deinterleave_v4f16_even(ptr %in, ptr %out) {
+; ZVL64B-LABEL: deinterleave_v4f16_even:
+; ZVL64B: # %bb.0: # %entry
+; ZVL64B-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; ZVL64B-NEXT: vle16.v v8, (a0)
+; ZVL64B-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; ZVL64B-NEXT: vnsrl.wi v8, v8, 0
+; ZVL64B-NEXT: vse16.v v8, (a1)
+; ZVL64B-NEXT: ret
+;
+; ZVL128B-LABEL: deinterleave_v4f16_even:
+; ZVL128B: # %bb.0: # %entry
+; ZVL128B-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVL128B-NEXT: vle16.v v8, (a0)
+; ZVL128B-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; ZVL128B-NEXT: vnsrl.wi v8, v8, 0
+; ZVL128B-NEXT: vse16.v v8, (a1)
+; ZVL128B-NEXT: ret
+entry:
+ %v = load <4 x half>, ptr %in, align 2
+ %s = shufflevector <4 x half> %v, <4 x half> poison, <2 x i32> <i32 0, i32 2>
+ store <2 x half> %s, ptr %out, align 2
+ ret void
+}
+
+define void @deinterleave_v4f16_odd(ptr %in, ptr %out) {
+; ZVL64B-LABEL: deinterleave_v4f16_odd:
+; ZVL64B: # %bb.0: # %entry
+; ZVL64B-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; ZVL64B-NEXT: vle16.v v8, (a0)
+; ZVL64B-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; ZVL64B-NEXT: vnsrl.wi v8, v8, 16
+; ZVL64B-NEXT: vse16.v v8, (a1)
+; ZVL64B-NEXT: ret
+;
+; ZVL128B-LABEL: deinterleave_v4f16_odd:
+; ZVL128B: # %bb.0: # %entry
+; ZVL128B-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVL128B-NEXT: vle16.v v8, (a0)
+; ZVL128B-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; ZVL128B-NEXT: vnsrl.wi v8, v8, 16
+; ZVL128B-NEXT: vse16.v v8, (a1)
+; ZVL128B-NEXT: ret
+entry:
+ %v = load <4 x half>, ptr %in, align 2
+ %s = shufflevector <4 x half> %v, <4 x half> poison, <2 x i32> <i32 1, i32 3>
+ store <2 x half> %s, ptr %out, align 2
+ ret void
+}
+
+define void @interleave_v2f16(ptr %pa, ptr %pb, ptr %out) {
+; ZVL64B-LABEL: interleave_v2f16:
+; ZVL64B: # %bb.0: # %entry
+; ZVL64B-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; ZVL64B-NEXT: vle16.v v8, (a0)
+; ZVL64B-NEXT: vle16.v v9, (a1)
+; ZVL64B-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; ZVL64B-NEXT: vzip.vv v10, v8, v9
+; ZVL64B-NEXT: vse16.v v10, (a2)
+; ZVL64B-NEXT: ret
+;
+; ZVL128B-LABEL: interleave_v2f16:
+; ZVL128B: # %bb.0: # %entry
+; ZVL128B-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; ZVL128B-NEXT: vle16.v v8, (a0)
+; ZVL128B-NEXT: vle16.v v9, (a1)
+; ZVL128B-NEXT: vwaddu.vv v10, v8, v9
+; ZVL128B-NEXT: li a0, -1
+; ZVL128B-NEXT: vwmaccu.vx v10, a0, v9
+; ZVL128B-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVL128B-NEXT: vse16.v v10, (a2)
+; ZVL128B-NEXT: ret
+entry:
+ %a = load <2 x half>, ptr %pa, align 2
+ %b = load <2 x half>, ptr %pb, align 2
+ %s = shufflevector <2 x half> %a, <2 x half> %b, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
+ store <4 x half> %s, ptr %out, align 2
+ ret void
+}
+
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