[clang] [llvm] [RISCV] Update Zvzip support to v0.2 (PR #210603)
via cfe-commits
cfe-commits at lists.llvm.org
Sun Jul 19 08:14:55 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-clang-driver
Author: renndong
<details>
<summary>Changes</summary>
This updates the experimental Zvzip implementation to match the v0.2 draft
specification from RISC-V ISA manual PR https://github.com/riscv/riscv-isa-manual/pull/3233.
In Zvzip v0.2, `vtype`/`vl` describe the interleaved operand. This changes the
type shape of `vzip` and `vunzip`:
* `vzip.vv` produces the current LMUL result from two half-LMUL sources.
* `vunzipe.v`/`vunzipo.v` consume the current LMUL source and produce
half-LMUL results.
* `vunzipe.v`/`vunzipo.v` no longer have masked forms, and the destination
register group can overlap with the lowest-numbered part of the source
register group.
* Masked `vzip.vv` uses a mask type derived from the result vector.
This PR is developed with @<!-- -->wangpc-pp and is based on his draft PR https://github.com/llvm/llvm-project/pull/207971.
---
Patch is 1.32 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/210603.diff
53 Files Affected:
- (modified) clang/include/clang/Basic/riscv_vector.td (+14-6)
- (modified) clang/include/clang/Basic/riscv_vector_common.td (+5)
- (modified) clang/include/clang/Support/RISCVVIntrinsicUtils.h (+4-1)
- (modified) clang/lib/Sema/SemaRISCV.cpp (+9-7)
- (modified) clang/lib/Support/RISCVVIntrinsicUtils.cpp (+19-4)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c (-54)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c (-54)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c (+15-15)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c (-54)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c (-54)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c (+15-15)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c (-164)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c (-164)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c (+45-45)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c (-164)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c (-164)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c (+45-45)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c (-482)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c (-482)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c (+144-144)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c (-482)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c (-482)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c (+144-144)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c (-1583)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c (-1583)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c (+432-432)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c (-1583)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c (-1583)
- (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c (+432-432)
- (modified) clang/test/Driver/print-supported-extensions-riscv.c (+1-1)
- (modified) clang/test/Preprocessor/riscv-target-features.c (+5-5)
- (modified) clang/utils/TableGen/RISCVVEmitter.cpp (+18-9)
- (modified) llvm/docs/RISCVUsage.rst (+1-1)
- (modified) llvm/include/llvm/IR/IntrinsicsRISCV.td (+1-11)
- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+1-1)
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+26-13)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoV.td (+10)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td (+22)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoZvzip.td (+64-47)
- (modified) llvm/test/CodeGen/RISCV/attributes.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll (+18-15)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll (+66-65)
- (modified) llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll (+15-15)
- (modified) llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll (+55-55)
- (modified) llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll (+16-17)
- (modified) llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll (+41-45)
- (modified) llvm/test/CodeGen/RISCV/rvv/vunzipe.ll (+35-490)
- (modified) llvm/test/CodeGen/RISCV/rvv/vunzipo.ll (+35-490)
- (modified) llvm/test/CodeGen/RISCV/rvv/vzip.ll (+128-128)
- (modified) llvm/test/MC/RISCV/attribute-arch.s (+2-2)
- (modified) llvm/test/MC/RISCV/rvv/zvzip-invalid.s (+8-8)
- (modified) llvm/test/MC/RISCV/rvv/zvzip.s (+15-7)
- (modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+1-1)
``````````diff
diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
index c5ce8b7ae8fc1..e5f7f456d069d 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -2149,15 +2149,23 @@ let RequiredFeatures = ["zvdot4a8i"] in {
let UnMaskedPolicyScheme = HasPassthruOperand in {
let RequiredFeatures = ["zvzip"] in {
// Signed and floating type
- defm vzip : RVVOutOp0BuiltinSet<"vzip", "csilxfdy", [["vv", "d", "dvv"]]>;
- defm vunzipe : RVVOutOp0BuiltinSet<"vunzipe", "csilxfdy", [["v", "v", "vd"]]>;
- defm vunzipo : RVVOutOp0BuiltinSet<"vunzipo", "csilxfdy", [["v", "v", "vd"]]>;
+ let MaskedPrototypeHasResultMask = true in {
+ defm vzip : RVVOutOp0BuiltinSet<"vzip", "csilxfdy", [["vv", "d", "dvv"]]>;
+ }
+ let HasMasked = false in {
+ defm vunzipe : RVVOutOp0BuiltinSet<"vunzipe", "csilxfdy", [["v", "v", "vd"]]>;
+ defm vunzipo : RVVOutOp0BuiltinSet<"vunzipo", "csilxfdy", [["v", "v", "vd"]]>;
+ }
defm vpaire : RVVOutBuiltinSet<"vpaire", "csilxfdy", [["vv", "v", "vvv"]]>;
defm vpairo : RVVOutBuiltinSet<"vpairo", "csilxfdy", [["vv", "v", "vvv"]]>;
// Unsigned
- defm vzip : RVVOutOp0BuiltinSet<"vzip", "csil", [["vv", "Ud", "UdUvUv"]]>;
- defm vunzipe : RVVOutOp0BuiltinSet<"vunzipe", "csil", [["v", "Uv", "UvUd"]]>;
- defm vunzipo : RVVOutOp0BuiltinSet<"vunzipo", "csil", [["v", "Uv", "UvUd"]]>;
+ let MaskedPrototypeHasResultMask = true in {
+ defm vzip : RVVOutOp0BuiltinSet<"vzip", "csil", [["vv", "Ud", "UdUvUv"]]>;
+ }
+ let HasMasked = false in {
+ defm vunzipe : RVVOutOp0BuiltinSet<"vunzipe", "csil", [["v", "Uv", "UvUd"]]>;
+ defm vunzipo : RVVOutOp0BuiltinSet<"vunzipo", "csil", [["v", "Uv", "UvUd"]]>;
+ }
defm vpaire : RVVOutBuiltinSet<"vpaire", "csil", [["vv", "Uv", "UvUvUv"]]>;
defm vpairo : RVVOutBuiltinSet<"vpairo", "csil", [["vv", "Uv", "UvUvUv"]]>;
}
diff --git a/clang/include/clang/Basic/riscv_vector_common.td b/clang/include/clang/Basic/riscv_vector_common.td
index 739bbdd6f66e6..bef07556634fa 100644
--- a/clang/include/clang/Basic/riscv_vector_common.td
+++ b/clang/include/clang/Basic/riscv_vector_common.td
@@ -186,6 +186,11 @@ class RVVBuiltin<string suffix, string prototype, string type_range,
// This builtin has a masked form.
bit HasMasked = true;
+ // The masked form's predicate operand normally has the same LMUL as the
+ // unmasked base type. Some mixed-LMUL instructions instead predicate the
+ // result elements.
+ bit MaskedPrototypeHasResultMask = false;
+
// This is used by intrinsics that need vtype.altfmt
bit AltFmt = false;
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
index 3ea5725057f05..bfcaec572aa95 100644
--- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -37,6 +37,7 @@ enum class VectorTypeModifier : uint8_t {
Widening8XVector,
DoubleLMULVector,
MaskVector,
+ DoubleLMULMaskVector,
Log2EEW3,
Log2EEW4,
Log2EEW5,
@@ -482,7 +483,8 @@ class RVVIntrinsic {
static llvm::SmallVector<PrototypeDescriptor>
computeBuiltinTypes(llvm::ArrayRef<PrototypeDescriptor> Prototype,
- bool IsMasked, bool HasMaskedOffOperand, bool HasVL,
+ bool IsMasked, bool HasMaskedOffOperand,
+ bool MaskedPrototypeHasResultMask, bool HasVL,
unsigned NF, PolicyScheme DefaultScheme,
Policy PolicyAttrs, bool IsTuple);
@@ -543,6 +545,7 @@ struct RVVIntrinsicRecord {
bool HasTailPolicy : 1;
bool HasMaskPolicy : 1;
bool HasFRMRoundModeOp : 1;
+ bool MaskedPrototypeHasResultMask : 1;
bool AltFmt : 1;
bool IsTuple : 1;
LLVM_PREFERRED_TYPE(PolicyScheme)
diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp
index 9647a7d913744..b9b986a44ee24 100644
--- a/clang/lib/Sema/SemaRISCV.cpp
+++ b/clang/lib/Sema/SemaRISCV.cpp
@@ -264,15 +264,16 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
llvm::SmallVector<PrototypeDescriptor> ProtoSeq =
RVVIntrinsic::computeBuiltinTypes(
BasicProtoSeq, /*IsMasked=*/false,
- /*HasMaskedOffOperand=*/false, Record.HasVL, Record.NF,
+ /*HasMaskedOffOperand=*/false,
+ /*MaskedPrototypeHasResultMask=*/false, Record.HasVL, Record.NF,
UnMaskedPolicyScheme, DefaultPolicy, Record.IsTuple);
llvm::SmallVector<PrototypeDescriptor> ProtoMaskSeq;
if (Record.HasMasked)
ProtoMaskSeq = RVVIntrinsic::computeBuiltinTypes(
BasicProtoSeq, /*IsMasked=*/true, Record.HasMaskedOffOperand,
- Record.HasVL, Record.NF, MaskedPolicyScheme, DefaultPolicy,
- Record.IsTuple);
+ Record.MaskedPrototypeHasResultMask, Record.HasVL, Record.NF,
+ MaskedPolicyScheme, DefaultPolicy, Record.IsTuple);
bool UnMaskedHasPolicy = UnMaskedPolicyScheme != PolicyScheme::SchemeNone;
bool MaskedHasPolicy = MaskedPolicyScheme != PolicyScheme::SchemeNone;
@@ -318,8 +319,9 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
llvm::SmallVector<PrototypeDescriptor> PolicyPrototype =
RVVIntrinsic::computeBuiltinTypes(
BasicProtoSeq, /*IsMasked=*/false,
- /*HasMaskedOffOperand=*/false, Record.HasVL, Record.NF,
- UnMaskedPolicyScheme, P, Record.IsTuple);
+ /*HasMaskedOffOperand=*/false,
+ /*MaskedPrototypeHasResultMask=*/false, Record.HasVL,
+ Record.NF, UnMaskedPolicyScheme, P, Record.IsTuple);
std::optional<RVVTypes> PolicyTypes = TypeCache.computeTypes(
BaseType, Log2LMUL, Record.NF, PolicyPrototype);
InitRVVIntrinsic(Record, SuffixStr, OverloadedSuffixStr,
@@ -341,8 +343,8 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
llvm::SmallVector<PrototypeDescriptor> PolicyPrototype =
RVVIntrinsic::computeBuiltinTypes(
BasicProtoSeq, /*IsMasked=*/true, Record.HasMaskedOffOperand,
- Record.HasVL, Record.NF, MaskedPolicyScheme, P,
- Record.IsTuple);
+ Record.MaskedPrototypeHasResultMask, Record.HasVL, Record.NF,
+ MaskedPolicyScheme, P, Record.IsTuple);
std::optional<RVVTypes> PolicyTypes = TypeCache.computeTypes(
BaseType, Log2LMUL, Record.NF, PolicyPrototype);
InitRVVIntrinsic(Record, SuffixStr, OverloadedSuffixStr,
diff --git a/clang/lib/Support/RISCVVIntrinsicUtils.cpp b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
index 5031bf5a1a8ff..77e2994258411 100644
--- a/clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -774,6 +774,12 @@ void RVVType::applyModifier(const PrototypeDescriptor &Transformer) {
Scale = LMUL.getScale(ElementBitwidth);
ElementBitwidth = 1;
break;
+ case VectorTypeModifier::DoubleLMULMaskVector:
+ ScalarType = ScalarTypeKind::Boolean;
+ LMUL.MulLog2LMUL(1);
+ Scale = LMUL.getScale(ElementBitwidth);
+ ElementBitwidth = 1;
+ break;
case VectorTypeModifier::Log2EEW3:
applyLog2EEW(3);
break;
@@ -1098,8 +1104,8 @@ std::string RVVIntrinsic::getSuffixStr(
llvm::SmallVector<PrototypeDescriptor> RVVIntrinsic::computeBuiltinTypes(
llvm::ArrayRef<PrototypeDescriptor> Prototype, bool IsMasked,
- bool HasMaskedOffOperand, bool HasVL, unsigned NF,
- PolicyScheme DefaultScheme, Policy PolicyAttrs, bool IsTuple) {
+ bool HasMaskedOffOperand, bool MaskedPrototypeHasResultMask, bool HasVL,
+ unsigned NF, PolicyScheme DefaultScheme, Policy PolicyAttrs, bool IsTuple) {
SmallVector<PrototypeDescriptor> NewPrototype(Prototype);
bool HasPassthruOp = DefaultScheme == PolicyScheme::HasPassthruOperand;
if (IsMasked) {
@@ -1140,7 +1146,14 @@ llvm::SmallVector<PrototypeDescriptor> RVVIntrinsic::computeBuiltinTypes(
PrototypeDescriptor::Mask);
} else {
// If IsMasked, insert PrototypeDescriptor:Mask as first input operand.
- NewPrototype.insert(NewPrototype.begin() + 1, PrototypeDescriptor::Mask);
+ if (MaskedPrototypeHasResultMask)
+ NewPrototype.insert(
+ NewPrototype.begin() + 1,
+ PrototypeDescriptor(BaseTypeModifier::Vector,
+ VectorTypeModifier::DoubleLMULMaskVector));
+ else
+ NewPrototype.insert(NewPrototype.begin() + 1,
+ PrototypeDescriptor::Mask);
}
} else {
if (NF == 1) {
@@ -1164,7 +1177,7 @@ llvm::SmallVector<PrototypeDescriptor> RVVIntrinsic::computeBuiltinTypes(
NewPrototype.insert(NewPrototype.begin() + NF + 1, NF, MaskoffType);
}
}
- }
+ }
// If HasVL, append PrototypeDescriptor:VL to last operand
if (HasVL)
@@ -1301,6 +1314,8 @@ raw_ostream &operator<<(raw_ostream &OS, const RVVIntrinsicRecord &Record) {
OS << "/*HasTailPolicy=*/" << (int)Record.HasTailPolicy << ", ";
OS << "/*HasMaskPolicy=*/" << (int)Record.HasMaskPolicy << ", ";
OS << "/*HasFRMRoundModeOp=*/" << (int)Record.HasFRMRoundModeOp << ", ";
+ OS << "/*MaskedPrototypeHasResultMask=*/"
+ << (int)Record.MaskedPrototypeHasResultMask << ", ";
OS << "/*AltFmt=*/" << (int)Record.AltFmt << ",";
OS << "/*IsTuple=*/" << (int)Record.IsTuple << ", ";
OS << "/*UnMaskedPolicyScheme=*/" << (PolicyScheme)Record.UnMaskedPolicyScheme
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c
index 27da4aab99204..e87a2ac6d7818 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c
@@ -59,57 +59,3 @@ vbfloat16m4_t test_vunzipe_v_bf16m4(vbfloat16m8_t vs, size_t vl) {
return __riscv_vunzipe_v_bf16m4(vs, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vunzipe_v_bf16mf4_m(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vunzipe.mask.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 2 x bfloat> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
-//
-vbfloat16mf4_t test_vunzipe_v_bf16mf4_m(vbool64_t vm, vbfloat16mf2_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_bf16mf4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vunzipe_v_bf16mf2_m(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vunzipe.mask.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 4 x bfloat> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
-//
-vbfloat16mf2_t test_vunzipe_v_bf16mf2_m(vbool32_t vm, vbfloat16m1_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_bf16mf2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vunzipe_v_bf16m1_m(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vunzipe.mask.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 8 x bfloat> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
-//
-vbfloat16m1_t test_vunzipe_v_bf16m1_m(vbool16_t vm, vbfloat16m2_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_bf16m1_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vunzipe_v_bf16m2_m(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vunzipe.mask.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 16 x bfloat> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
-//
-vbfloat16m2_t test_vunzipe_v_bf16m2_m(vbool8_t vm, vbfloat16m4_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_bf16m2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vunzipe_v_bf16m4_m(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vunzipe.mask.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 32 x bfloat> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
-//
-vbfloat16m4_t test_vunzipe_v_bf16m4_m(vbool4_t vm, vbfloat16m8_t vs,
- size_t vl) {
- return __riscv_vunzipe_v_bf16m4_m(vm, vs, vl);
-}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c
index d901e5cc6f8dc..cdd036aae8907 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c
@@ -59,57 +59,3 @@ vbfloat16m4_t test_vunzipo_v_bf16m4(vbfloat16m8_t vs, size_t vl) {
return __riscv_vunzipo_v_bf16m4(vs, vl);
}
-// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vunzipo_v_bf16mf4_m(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vunzipo.mask.nxv1bf16.nxv2bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 2 x bfloat> [[VS]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
-//
-vbfloat16mf4_t test_vunzipo_v_bf16mf4_m(vbool64_t vm, vbfloat16mf2_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_bf16mf4_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vunzipo_v_bf16mf2_m(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 4 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vunzipo.mask.nxv2bf16.nxv4bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 4 x bfloat> [[VS]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
-//
-vbfloat16mf2_t test_vunzipo_v_bf16mf2_m(vbool32_t vm, vbfloat16m1_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_bf16mf2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vunzipo_v_bf16m1_m(
-// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 8 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vunzipo.mask.nxv4bf16.nxv8bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 8 x bfloat> [[VS]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
-//
-vbfloat16m1_t test_vunzipo_v_bf16m1_m(vbool16_t vm, vbfloat16m2_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_bf16m1_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vunzipo_v_bf16m2_m(
-// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 16 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vunzipo.mask.nxv8bf16.nxv16bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 16 x bfloat> [[VS]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
-//
-vbfloat16m2_t test_vunzipo_v_bf16m2_m(vbool8_t vm, vbfloat16m4_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_bf16m2_m(vm, vs, vl);
-}
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vunzipo_v_bf16m4_m(
-// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 32 x bfloat> [[VS:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vunzipo.mask.nxv16bf16.nxv32bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 32 x bfloat> [[VS]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
-//
-vbfloat16m4_t test_vunzipo_v_bf16m4_m(vbool4_t vm, vbfloat16m8_t vs,
- size_t vl) {
- return __riscv_vunzipo_v_bf16m4_m(vm, vs, vl);
-}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c
index 6b36bc7347772..c6fe3cff4ee9b 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c
@@ -65,56 +65,56 @@ vbfloat16m8_t test_vzip_vv_bf16m8(vbfloat16m4_t vs2, vbfloat16m4_t vs1,
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vzip_vv_bf16mf2_m(
-// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], <vscale x 1 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 1 x bfloat> [[VS2:%.*]], <vscale x 1 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x bfloat> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 1 x bfloat> [[VS2]], <vscale x 1 x bfloat> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
//
-vbfloat16mf2_t test_vzip_vv_bf16mf2_m(vbool64_t vm, vbfloat16mf4_t vs2,
+vbfloat16mf2_t test_vzip_vv_bf16mf2_m(vbool32_t vm, vbfloat16mf4_t vs2,
vbfloat16mf4_t vs1, size_t vl) {
return __riscv_vzip_vv_bf16mf2_m(vm, vs2, vs1, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vzip_vv_bf16m1_m(
-// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], <vscale x 2 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 2 x bfloat> [[VS2:%.*]], <vscale x 2 x bfloat> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 2 x bfloat> [[VS2]], <vscale x 2 x bfloat> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%....
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/210603
More information about the cfe-commits
mailing list