[clang] [clang][clangIR]: X86 upstream avx psrldqi/pslldqi (PR #208025)

[Lucas Ribeiro Lima via cfe-commits]

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@@ -811,6 +811,60 @@ static mlir::Value emitX86MaskedLoad(CIRGenBuilderTy &builder,
   return builder.createMaskedLoad(loc, ty, ptr, alignment, maskVec, ops[1]);
 }
 
+static mlir::Value emitX86PackedByteShift(CIRGenBuilderTy &builder,
+                                          unsigned builtinID,
+                                          mlir::Location loc,
+                                          llvm::ArrayRef<mlir::Value> ops,
+                                          llvm::Boolean isLeftShift) {
+  auto byteVecType = cast<cir::VectorType>(ops[0].getType());
+  assert(!byteVecType.getIsScalable() &&
+         "This is only intended for fixed-width vectors");
+
+  unsigned shiftVal = CIRGenFunction::getZExtIntValueFromConstOp(ops[1]) & 0xFF;
+  mlir::Value zeroVector = builder.getZero(loc, byteVecType);
+
+  // If pslldq is shifting the vector more than 15 bytes, emit zero.
+  // This matches the hardware behavior where shifting by 16+ bytes
+  // clears the entire 128-bit lane.
+  if (shiftVal >= 16)
+    return zeroVector;
+
+  uint64_t numElts = byteVecType.getSize();
+  assert(numElts % 16 == 0 && "Expected a multiple of 16");
+
+  llvm::SmallVector<int64_t, 64> shuffleMask;
+
+  const unsigned laneSize = 16;
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lucaslive974 wrote:

LGTM!

https://github.com/llvm/llvm-project/pull/208025