[clang] [llvm] [RISCV][P-ext] Support Packed Narrowing Zip (PR #210040)
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Fri Jul 17 01:56:45 PDT 2026
https://github.com/TelGome updated https://github.com/llvm/llvm-project/pull/210040
>From 850655f3ed450d92146cbf7dece38c714125162a Mon Sep 17 00:00:00 2001
From: Dongyan Chen <chendongyan at isrc.iscas.ac.cn>
Date: Thu, 16 Jul 2026 19:55:15 +0800
Subject: [PATCH 1/2] [RISCV][P-ext] Support Packed Narrowing Zip
---
clang/lib/Headers/riscv_packed_simd.h | 43 +++
clang/test/CodeGen/RISCV/rvp-intrinsics.c | 266 ++++++++++++++++++
.../riscv_packed_simd.c | 80 ++++++
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 47 ++++
llvm/lib/Target/RISCV/RISCVInstrInfoP.td | 25 ++
llvm/test/CodeGen/RISCV/rvp-narrowing-zip.ll | 99 +++++++
6 files changed, 560 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/rvp-narrowing-zip.ll
diff --git a/clang/lib/Headers/riscv_packed_simd.h b/clang/lib/Headers/riscv_packed_simd.h
index c0596aefe529a..0b8b710459d1b 100644
--- a/clang/lib/Headers/riscv_packed_simd.h
+++ b/clang/lib/Headers/riscv_packed_simd.h
@@ -176,6 +176,29 @@ typedef uint32_t uint32x2_t __attribute__((__vector_size__(8)));
return __builtin_shufflevector(__rs1, __rs1, 1, 3, 5, 7); \
}
+#define __packed_nzip2(name, rty, ty) \
+ static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \
+ ty __rs2) { \
+ return __builtin_shufflevector((rty)__rs1, (rty)__rs2, 0, 4, 2, 6); \
+ }
+#define __packed_nzip4(name, rty, ty) \
+ static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \
+ ty __rs2) { \
+ return __builtin_shufflevector((rty)__rs1, (rty)__rs2, 0, 8, 2, 10, 4, 12, \
+ 6, 14); \
+ }
+#define __packed_nziph2(name, rty, ty) \
+ static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \
+ ty __rs2) { \
+ return __builtin_shufflevector((rty)__rs1, (rty)__rs2, 1, 5, 3, 7); \
+ }
+#define __packed_nziph4(name, rty, ty) \
+ static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \
+ ty __rs2) { \
+ return __builtin_shufflevector((rty)__rs1, (rty)__rs2, 1, 9, 3, 11, 5, 13, \
+ 7, 15); \
+ }
+
#define __packed_abdsum(name, rty, ty, builtin) \
static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \
ty __rs2) { \
@@ -515,6 +538,22 @@ __packed_unzipo2(punzipo_i16x2, int16x2_t, int16x4_t)
__packed_unzipe2(punzipe_u16x2, uint16x2_t, uint16x4_t)
__packed_unzipo2(punzipo_u16x2, uint16x2_t, uint16x4_t)
+/* Packed Narrowing Zip (32-bit) */
+__packed_nzip2(pnzip_i8x4, int8x4_t, int16x2_t)
+__packed_nzip2(pnzip_u8x4, uint8x4_t, uint16x2_t)
+__packed_nziph2(pnziph_i8x4, int8x4_t, int16x2_t)
+__packed_nziph2(pnziph_u8x4, uint8x4_t, uint16x2_t)
+
+/* Packed Narrowing Zip (64-bit) */
+__packed_nzip4(pnzip_i8x8, int8x8_t, int16x4_t)
+__packed_nzip4(pnzip_u8x8, uint8x8_t, uint16x4_t)
+__packed_nzip2(pnzip_i16x4, int16x4_t, int32x2_t)
+__packed_nzip2(pnzip_u16x4, uint16x4_t, uint32x2_t)
+__packed_nziph4(pnziph_i8x8, int8x8_t, int16x4_t)
+__packed_nziph4(pnziph_u8x8, uint8x8_t, uint16x4_t)
+__packed_nziph2(pnziph_i16x4, int16x4_t, int32x2_t)
+__packed_nziph2(pnziph_u16x4, uint16x4_t, uint32x2_t)
+
/* Packed Averaging Addition and Subtraction (32-bit) */
__packed_binary_builtin(paadd_i8x4, int8x4_t, __builtin_riscv_paadd_i8x4)
__packed_binary_builtin(paadd_i16x2, int16x2_t, __builtin_riscv_paadd_i16x2)
@@ -729,6 +768,10 @@ __packed_reinterpret(u32x2_i32x2, int32x2_t, uint32x2_t)
#undef __packed_unzipe4
#undef __packed_unzipo2
#undef __packed_unzipo4
+#undef __packed_nzip2
+#undef __packed_nzip4
+#undef __packed_nziph2
+#undef __packed_nziph4
#undef __packed_abdsum
#undef __packed_abdsum_acc
#undef __packed_reinterpret
diff --git a/clang/test/CodeGen/RISCV/rvp-intrinsics.c b/clang/test/CodeGen/RISCV/rvp-intrinsics.c
index a3eb670fe23c9..6f55039bd1e36 100644
--- a/clang/test/CodeGen/RISCV/rvp-intrinsics.c
+++ b/clang/test/CodeGen/RISCV/rvp-intrinsics.c
@@ -8267,3 +8267,269 @@ int32x2_t test_preinterpret_i16x4_i32x2(int16x4_t x) {
int32x2_t test_preinterpret_u32x2_i32x2(uint32x2_t x) {
return __riscv_preinterpret_u32x2_i32x2(x);
}
+
+/* Packed Narrowing Zip */
+
+// RV32-LABEL: define dso_local i32 @test_pnzip_i8x4(
+// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
+// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
+// RV32-NEXT: ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local i32 @test_pnzip_i8x4(
+// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
+// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
+// RV64-NEXT: ret i32 [[TMP2]]
+//
+int8x4_t test_pnzip_i8x4(int16x2_t rs1, int16x2_t rs2) {
+ return __riscv_pnzip_i8x4(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pnzip_u8x4(
+// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
+// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
+// RV32-NEXT: ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local i32 @test_pnzip_u8x4(
+// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
+// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
+// RV64-NEXT: ret i32 [[TMP2]]
+//
+uint8x4_t test_pnzip_u8x4(uint16x2_t rs1, uint16x2_t rs2) {
+ return __riscv_pnzip_u8x4(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pnziph_i8x4(
+// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
+// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
+// RV32-NEXT: ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local i32 @test_pnziph_i8x4(
+// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
+// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
+// RV64-NEXT: ret i32 [[TMP2]]
+//
+int8x4_t test_pnziph_i8x4(int16x2_t rs1, int16x2_t rs2) {
+ return __riscv_pnziph_i8x4(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pnziph_u8x4(
+// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
+// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
+// RV32-NEXT: ret i32 [[TMP2]]
+//
+// RV64-LABEL: define dso_local i32 @test_pnziph_u8x4(
+// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
+// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
+// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
+// RV64-NEXT: ret i32 [[TMP2]]
+//
+uint8x4_t test_pnziph_u8x4(uint16x2_t rs1, uint16x2_t rs2) {
+ return __riscv_pnziph_u8x4(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pnzip_i8x8(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
+// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
+// RV32-NEXT: ret i64 [[TMP2]]
+//
+// RV64-LABEL: define dso_local i64 @test_pnzip_i8x8(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
+// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
+// RV64-NEXT: ret i64 [[TMP2]]
+//
+int8x8_t test_pnzip_i8x8(int16x4_t rs1, int16x4_t rs2) {
+ return __riscv_pnzip_i8x8(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pnzip_u8x8(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
+// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
+// RV32-NEXT: ret i64 [[TMP2]]
+//
+// RV64-LABEL: define dso_local i64 @test_pnzip_u8x8(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
+// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
+// RV64-NEXT: ret i64 [[TMP2]]
+//
+uint8x8_t test_pnzip_u8x8(uint16x4_t rs1, uint16x4_t rs2) {
+ return __riscv_pnzip_u8x8(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pnzip_i16x4(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
+// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// RV32-NEXT: ret i64 [[TMP2]]
+//
+// RV64-LABEL: define dso_local i64 @test_pnzip_i16x4(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
+// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// RV64-NEXT: ret i64 [[TMP2]]
+//
+int16x4_t test_pnzip_i16x4(int32x2_t rs1, int32x2_t rs2) {
+ return __riscv_pnzip_i16x4(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pnzip_u16x4(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
+// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// RV32-NEXT: ret i64 [[TMP2]]
+//
+// RV64-LABEL: define dso_local i64 @test_pnzip_u16x4(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
+// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// RV64-NEXT: ret i64 [[TMP2]]
+//
+uint16x4_t test_pnzip_u16x4(uint32x2_t rs1, uint32x2_t rs2) {
+ return __riscv_pnzip_u16x4(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pnziph_i8x8(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
+// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
+// RV32-NEXT: ret i64 [[TMP2]]
+//
+// RV64-LABEL: define dso_local i64 @test_pnziph_i8x8(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
+// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
+// RV64-NEXT: ret i64 [[TMP2]]
+//
+int8x8_t test_pnziph_i8x8(int16x4_t rs1, int16x4_t rs2) {
+ return __riscv_pnziph_i8x8(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pnziph_u8x8(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
+// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
+// RV32-NEXT: ret i64 [[TMP2]]
+//
+// RV64-LABEL: define dso_local i64 @test_pnziph_u8x8(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
+// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
+// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
+// RV64-NEXT: ret i64 [[TMP2]]
+//
+uint8x8_t test_pnziph_u8x8(uint16x4_t rs1, uint16x4_t rs2) {
+ return __riscv_pnziph_u8x8(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pnziph_i16x4(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
+// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// RV32-NEXT: ret i64 [[TMP2]]
+//
+// RV64-LABEL: define dso_local i64 @test_pnziph_i16x4(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
+// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// RV64-NEXT: ret i64 [[TMP2]]
+//
+int16x4_t test_pnziph_i16x4(int32x2_t rs1, int32x2_t rs2) {
+ return __riscv_pnziph_i16x4(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pnziph_u16x4(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
+// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// RV32-NEXT: ret i64 [[TMP2]]
+//
+// RV64-LABEL: define dso_local i64 @test_pnziph_u16x4(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
+// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
+// RV64-NEXT: ret i64 [[TMP2]]
+//
+uint16x4_t test_pnziph_u16x4(uint32x2_t rs1, uint32x2_t rs2) {
+ return __riscv_pnziph_u16x4(rs1, rs2);
+}
diff --git a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
index a73c0376db9d1..c39c94014fd13 100644
--- a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+++ b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
@@ -2452,3 +2452,83 @@ int8x8_t test_psabs_i8x8(int8x8_t a) { return __riscv_psabs_i8x8(a); }
// RV32: psabs.dh
// RV64: psabs.h
int16x4_t test_psabs_i16x4(int16x4_t a) { return __riscv_psabs_i16x4(a); }
+
+// CHECK-LABEL: test_pnzip_i8x4:
+// CHECK: ppaire.b
+int8x4_t test_pnzip_i8x4(int16x2_t rs1, int16x2_t rs2) {
+ return __riscv_pnzip_i8x4(rs1, rs2);
+}
+
+// CHECK-LABEL: test_pnzip_u8x4:
+// CHECK: ppaire.b
+uint8x4_t test_pnzip_u8x4(uint16x2_t rs1, uint16x2_t rs2) {
+ return __riscv_pnzip_u8x4(rs1, rs2);
+}
+
+// CHECK-LABEL: test_pnziph_i8x4:
+// CHECK: ppairo.b
+int8x4_t test_pnziph_i8x4(int16x2_t rs1, int16x2_t rs2) {
+ return __riscv_pnziph_i8x4(rs1, rs2);
+}
+
+// CHECK-LABEL: test_pnziph_u8x4:
+// CHECK: ppairo.b
+uint8x4_t test_pnziph_u8x4(uint16x2_t rs1, uint16x2_t rs2) {
+ return __riscv_pnziph_u8x4(rs1, rs2);
+}
+
+// CHECK-LABEL: test_pnzip_i8x8:
+// RV32: ppaire.db
+// RV64: ppaire.b
+int8x8_t test_pnzip_i8x8(int16x4_t rs1, int16x4_t rs2) {
+ return __riscv_pnzip_i8x8(rs1, rs2);
+}
+
+// CHECK-LABEL: test_pnzip_u8x8:
+// RV32: ppaire.db
+// RV64: ppaire.b
+uint8x8_t test_pnzip_u8x8(uint16x4_t rs1, uint16x4_t rs2) {
+ return __riscv_pnzip_u8x8(rs1, rs2);
+}
+
+// CHECK-LABEL: test_pnzip_i16x4:
+// RV32: ppaire.dh
+// RV64: ppaire.h
+int16x4_t test_pnzip_i16x4(int32x2_t rs1, int32x2_t rs2) {
+ return __riscv_pnzip_i16x4(rs1, rs2);
+}
+
+// CHECK-LABEL: test_pnzip_u16x4:
+// RV32: ppaire.dh
+// RV64: ppaire.h
+uint16x4_t test_pnzip_u16x4(uint32x2_t rs1, uint32x2_t rs2) {
+ return __riscv_pnzip_u16x4(rs1, rs2);
+}
+
+// CHECK-LABEL: test_pnziph_i8x8:
+// RV32: ppairo.db
+// RV64: ppairo.b
+int8x8_t test_pnziph_i8x8(int16x4_t rs1, int16x4_t rs2) {
+ return __riscv_pnziph_i8x8(rs1, rs2);
+}
+
+// CHECK-LABEL: test_pnziph_u8x8:
+// RV32: ppairo.db
+// RV64: ppairo.b
+uint8x8_t test_pnziph_u8x8(uint16x4_t rs1, uint16x4_t rs2) {
+ return __riscv_pnziph_u8x8(rs1, rs2);
+}
+
+// CHECK-LABEL: test_pnziph_i16x4:
+// RV32: ppairo.dh
+// RV64: ppairo.h
+int16x4_t test_pnziph_i16x4(int32x2_t rs1, int32x2_t rs2) {
+ return __riscv_pnziph_i16x4(rs1, rs2);
+}
+
+// CHECK-LABEL: test_pnziph_u16x4:
+// RV32: ppairo.dh
+// RV64: ppairo.h
+uint16x4_t test_pnziph_u16x4(uint32x2_t rs1, uint32x2_t rs2) {
+ return __riscv_pnziph_u16x4(rs1, rs2);
+}
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 8b3b555cb2656..4dda5f5defce3 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -6512,6 +6512,51 @@ lowerVECTOR_SHUFFLEAsRV32PNarrowingShift(ShuffleVectorSDNode *SVN,
DAG.getConstant(Index * EltBits, DL, MVT::i32));
}
+// Match a strided-interleave shuffle that forms a P-extension packed
+// narrowing zip:
+// <a0, b0, a2, b2, ...> -> ppaire.*
+// <a1, b1, a3, b3, ...> -> ppairo.*
+static SDValue lowerVECTOR_SHUFFLEAsPNarrowingZip(ShuffleVectorSDNode *SVN,
+ SelectionDAG &DAG) {
+ MVT VT = SVN->getSimpleValueType(0);
+ if (VT != MVT::v4i8 && VT != MVT::v8i8 && VT != MVT::v4i16)
+ return SDValue();
+
+ SDValue V1 = SVN->getOperand(0);
+ SDValue V2 = SVN->getOperand(1);
+ SDLoc DL(SVN);
+ unsigned NumElts = VT.getVectorNumElements();
+ ArrayRef<int> Mask = SVN->getMask();
+ if (V2.isUndef())
+ return SDValue();
+
+ // Match <start, N+start, start+2, N+start+2, ...>: each widened element of
+ // V1/V2 contributes its low (start=0, ppaire) or high (start=1, ppairo) byte.
+ // Trailing lanes may be undef when a 4-byte source was widened to v8i8.
+ auto IsStrided = [&](unsigned Start) {
+ for (unsigned I = 0; I != NumElts / 2; ++I) {
+ int M0 = Mask[2 * I];
+ int M1 = Mask[2 * I + 1];
+ if (M0 < 0 && M1 < 0)
+ continue;
+ if (M0 != (int)(Start + 2 * I) || M1 != (int)(NumElts + Start + 2 * I))
+ return false;
+ }
+ return true;
+ };
+
+ bool IsOdd;
+ if (IsStrided(0))
+ IsOdd = false;
+ else if (IsStrided(1))
+ IsOdd = true;
+ else
+ return SDValue();
+
+ unsigned Opc = IsOdd ? RISCVISD::PPAIRO : RISCVISD::PPAIRE;
+ return DAG.getNode(Opc, DL, VT, V1, V2);
+}
+
SDValue RISCVTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
SelectionDAG &DAG) const {
SDValue V1 = Op.getOperand(0);
@@ -6560,6 +6605,8 @@ SDValue RISCVTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
if (SDValue V =
lowerVECTOR_SHUFFLEAsRV32PNarrowingShift(SVN, Subtarget, DAG))
return V;
+ if (SDValue V = lowerVECTOR_SHUFFLEAsPNarrowingZip(SVN, DAG))
+ return V;
return SDValue();
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index c9300fd803dea..d7ef43b57b122 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -1868,6 +1868,7 @@ def SDT_RISCVPPairEven : SDTypeProfile<1, 2, [SDTCisVec<0>,
SDTCisSameAs<0, 1>,
SDTCisSameAs<0, 2>]>;
def riscv_ppaire : RVSDNode<"PPAIRE", SDT_RISCVPPairEven>;
+def riscv_ppairo : RVSDNode<"PPAIRO", SDT_RISCVPPairEven>;
def SDT_RISCVPackedBinary : SDTypeProfile<1, 2, [SDTCisVec<0>,
SDTCisSameAs<0, 1>,
SDTCisSameAs<0, 2>]>;
@@ -2303,6 +2304,13 @@ let append Predicates = [IsRV32] in {
def : Pat<(v4i16 (riscv_pwzip (v2i16 GPR:$rs1), (v2i16 GPR:$rs2))),
(WZIP16P GPR:$rs1, GPR:$rs2)>;
+ // Packed narrowing zip (32-bit): single-register ppaire.b/ppairo.b on the
+ // low bytes of each 16-bit element of two v4i8 operands.
+ def : Pat<(v4i8 (riscv_ppaire (v4i8 GPR:$rs1), (v4i8 GPR:$rs2))),
+ (PPAIRE_B GPR:$rs1, GPR:$rs2)>;
+ def : Pat<(v4i8 (riscv_ppairo (v4i8 GPR:$rs1), (v4i8 GPR:$rs2))),
+ (PPAIRO_B GPR:$rs1, GPR:$rs2)>;
+
// Sign-extend patterns using pwadd with zero
def : Pat<(v4i16 (sext (v4i8 GPR:$rs))), (PWADD_B GPR:$rs, (v4i8 X0))>;
def : Pat<(v2i32 (sext (v2i16 GPR:$rs))), (PWADD_H GPR:$rs, (v2i16 X0))>;
@@ -2561,6 +2569,12 @@ let append Predicates = [IsRV32] in {
def : Pat<(v8i8 (riscv_ppaire GPRPair:$rs1, GPRPair:$rs2)),
(PPAIRE_DB GPRPair:$rs1, GPRPair:$rs2)>;
+ def : Pat<(v8i8 (riscv_ppairo GPRPair:$rs1, GPRPair:$rs2)),
+ (PPAIRO_DB GPRPair:$rs1, GPRPair:$rs2)>;
+ def : Pat<(v4i16 (riscv_ppaire GPRPair:$rs1, GPRPair:$rs2)),
+ (PPAIRE_DH GPRPair:$rs1, GPRPair:$rs2)>;
+ def : Pat<(v4i16 (riscv_ppairo GPRPair:$rs1, GPRPair:$rs2)),
+ (PPAIRO_DH GPRPair:$rs1, GPRPair:$rs2)>;
// Concat vector patterns
def : Pat<(v8i8 (concat_vectors (v4i8 GPR:$a), (v4i8 GPR:$b))),
@@ -2838,6 +2852,17 @@ let append Predicates = [IsRV64] in {
(ZIP8P GPR:$rs1, GPR:$rs2)>;
def : Pat<(v4i16 (riscv_pzip (v4i16 GPR:$rs1), (v4i16 GPR:$rs2))),
(ZIP16P GPR:$rs1, GPR:$rs2)>;
+
+ // Packed narrowing zip: pair the low (even) / high (odd) byte/halfword of
+ // each widened element of rs1 and rs2.
+ def : Pat<(v8i8 (riscv_ppaire (v8i8 GPR:$rs1), (v8i8 GPR:$rs2))),
+ (PPAIRE_B GPR:$rs1, GPR:$rs2)>;
+ def : Pat<(v8i8 (riscv_ppairo (v8i8 GPR:$rs1), (v8i8 GPR:$rs2))),
+ (PPAIRO_B GPR:$rs1, GPR:$rs2)>;
+ def : Pat<(v4i16 (riscv_ppaire (v4i16 GPR:$rs1), (v4i16 GPR:$rs2))),
+ (PPAIRE_H GPR:$rs1, GPR:$rs2)>;
+ def : Pat<(v4i16 (riscv_ppairo (v4i16 GPR:$rs1), (v4i16 GPR:$rs2))),
+ (PPAIRO_H GPR:$rs1, GPR:$rs2)>;
// Sign extend inreg patterns using psext. sext_invec is lowered to
// zext_invec+sext_inreg.
def : Pat<(v4i16 (sext_inreg GPR:$rs1, v4i8)), (PSEXT_H_B GPR:$rs1)>;
diff --git a/llvm/test/CodeGen/RISCV/rvp-narrowing-zip.ll b/llvm/test/CodeGen/RISCV/rvp-narrowing-zip.ll
new file mode 100644
index 0000000000000..c9b8e8f6a261a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvp-narrowing-zip.ll
@@ -0,0 +1,99 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; This file covers packed narrowing zip (ppaire.*/ppairo.*) codegen from the
+; generic interleave IR produced by the C intrinsic header.
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-p,+m,+zbb \
+; RUN: -verify-machineinstrs < %s | \
+; RUN: FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb \
+; RUN: -verify-machineinstrs < %s | \
+; RUN: FileCheck %s --check-prefixes=CHECK,RV64
+
+; 64-bit section: two <4 x i16> widened inputs reinterpreted to <8 x i8>.
+
+define <8 x i8> @test_pnzip_v8i8(<4 x i16> %a, <4 x i16> %b) {
+; RV32-LABEL: test_pnzip_v8i8:
+; RV32: # %bb.0:
+; RV32-NEXT: ppaire.db a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pnzip_v8i8:
+; RV64: # %bb.0:
+; RV64-NEXT: ppaire.b a0, a0, a1
+; RV64-NEXT: ret
+ %ca = bitcast <4 x i16> %a to <8 x i8>
+ %cb = bitcast <4 x i16> %b to <8 x i8>
+ %r = shufflevector <8 x i8> %ca, <8 x i8> %cb, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
+ ret <8 x i8> %r
+}
+
+define <8 x i8> @test_pnziph_v8i8(<4 x i16> %a, <4 x i16> %b) {
+; RV32-LABEL: test_pnziph_v8i8:
+; RV32: # %bb.0:
+; RV32-NEXT: ppairo.db a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pnziph_v8i8:
+; RV64: # %bb.0:
+; RV64-NEXT: ppairo.b a0, a0, a1
+; RV64-NEXT: ret
+ %ca = bitcast <4 x i16> %a to <8 x i8>
+ %cb = bitcast <4 x i16> %b to <8 x i8>
+ %r = shufflevector <8 x i8> %ca, <8 x i8> %cb, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
+ ret <8 x i8> %r
+}
+
+define <4 x i16> @test_pnzip_v4i16(<2 x i32> %a, <2 x i32> %b) {
+; RV32-LABEL: test_pnzip_v4i16:
+; RV32: # %bb.0:
+; RV32-NEXT: ppaire.dh a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pnzip_v4i16:
+; RV64: # %bb.0:
+; RV64-NEXT: ppaire.h a0, a0, a1
+; RV64-NEXT: ret
+ %ca = bitcast <2 x i32> %a to <4 x i16>
+ %cb = bitcast <2 x i32> %b to <4 x i16>
+ %r = shufflevector <4 x i16> %ca, <4 x i16> %cb, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
+ ret <4 x i16> %r
+}
+
+define <4 x i16> @test_pnziph_v4i16(<2 x i32> %a, <2 x i32> %b) {
+; RV32-LABEL: test_pnziph_v4i16:
+; RV32: # %bb.0:
+; RV32-NEXT: ppairo.dh a0, a0, a2
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test_pnziph_v4i16:
+; RV64: # %bb.0:
+; RV64-NEXT: ppairo.h a0, a0, a1
+; RV64-NEXT: ret
+ %ca = bitcast <2 x i32> %a to <4 x i16>
+ %cb = bitcast <2 x i32> %b to <4 x i16>
+ %r = shufflevector <4 x i16> %ca, <4 x i16> %cb, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
+ ret <4 x i16> %r
+}
+
+; 32-bit section: two <2 x i16> widened inputs reinterpreted to <4 x i8>.
+
+define <4 x i8> @test_pnzip_v4i8(<2 x i16> %a, <2 x i16> %b) {
+; CHECK-LABEL: test_pnzip_v4i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: ppaire.b a0, a0, a1
+; CHECK-NEXT: ret
+ %ca = bitcast <2 x i16> %a to <4 x i8>
+ %cb = bitcast <2 x i16> %b to <4 x i8>
+ %r = shufflevector <4 x i8> %ca, <4 x i8> %cb, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
+ ret <4 x i8> %r
+}
+
+define <4 x i8> @test_pnziph_v4i8(<2 x i16> %a, <2 x i16> %b) {
+; CHECK-LABEL: test_pnziph_v4i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: ppairo.b a0, a0, a1
+; CHECK-NEXT: ret
+ %ca = bitcast <2 x i16> %a to <4 x i8>
+ %cb = bitcast <2 x i16> %b to <4 x i8>
+ %r = shufflevector <4 x i8> %ca, <4 x i8> %cb, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
+ ret <4 x i8> %r
+}
>From bb226d01cd5a7b36b24102f0ec99f7d841183350 Mon Sep 17 00:00:00 2001
From: Dongyan Chen <chendongyan at isrc.iscas.ac.cn>
Date: Fri, 17 Jul 2026 14:08:12 +0800
Subject: [PATCH 2/2] resolve comment
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 9 ++++----
llvm/lib/Target/RISCV/RISCVInstrInfoP.td | 24 ++++++++++-----------
2 files changed, 15 insertions(+), 18 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 4dda5f5defce3..9aaee1e47eab3 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -6512,12 +6512,11 @@ lowerVECTOR_SHUFFLEAsRV32PNarrowingShift(ShuffleVectorSDNode *SVN,
DAG.getConstant(Index * EltBits, DL, MVT::i32));
}
-// Match a strided-interleave shuffle that forms a P-extension packed
-// narrowing zip:
+// Match a strided-interleave shuffle that forms a P-extension packed pair:
// <a0, b0, a2, b2, ...> -> ppaire.*
// <a1, b1, a3, b3, ...> -> ppairo.*
-static SDValue lowerVECTOR_SHUFFLEAsPNarrowingZip(ShuffleVectorSDNode *SVN,
- SelectionDAG &DAG) {
+static SDValue lowerVECTOR_SHUFFLEAsPPair(ShuffleVectorSDNode *SVN,
+ SelectionDAG &DAG) {
MVT VT = SVN->getSimpleValueType(0);
if (VT != MVT::v4i8 && VT != MVT::v8i8 && VT != MVT::v4i16)
return SDValue();
@@ -6605,7 +6604,7 @@ SDValue RISCVTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
if (SDValue V =
lowerVECTOR_SHUFFLEAsRV32PNarrowingShift(SVN, Subtarget, DAG))
return V;
- if (SDValue V = lowerVECTOR_SHUFFLEAsPNarrowingZip(SVN, DAG))
+ if (SDValue V = lowerVECTOR_SHUFFLEAsPPair(SVN, DAG))
return V;
return SDValue();
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index d7ef43b57b122..ea9692985180f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -2304,12 +2304,19 @@ let append Predicates = [IsRV32] in {
def : Pat<(v4i16 (riscv_pwzip (v2i16 GPR:$rs1), (v2i16 GPR:$rs2))),
(WZIP16P GPR:$rs1, GPR:$rs2)>;
- // Packed narrowing zip (32-bit): single-register ppaire.b/ppairo.b on the
- // low bytes of each 16-bit element of two v4i8 operands.
+ // Packed pair: pair the even/odd-position elements of rs1 and rs2.
def : Pat<(v4i8 (riscv_ppaire (v4i8 GPR:$rs1), (v4i8 GPR:$rs2))),
(PPAIRE_B GPR:$rs1, GPR:$rs2)>;
def : Pat<(v4i8 (riscv_ppairo (v4i8 GPR:$rs1), (v4i8 GPR:$rs2))),
(PPAIRO_B GPR:$rs1, GPR:$rs2)>;
+ def : Pat<(v8i8 (riscv_ppaire GPRPair:$rs1, GPRPair:$rs2)),
+ (PPAIRE_DB GPRPair:$rs1, GPRPair:$rs2)>;
+ def : Pat<(v8i8 (riscv_ppairo GPRPair:$rs1, GPRPair:$rs2)),
+ (PPAIRO_DB GPRPair:$rs1, GPRPair:$rs2)>;
+ def : Pat<(v4i16 (riscv_ppaire GPRPair:$rs1, GPRPair:$rs2)),
+ (PPAIRE_DH GPRPair:$rs1, GPRPair:$rs2)>;
+ def : Pat<(v4i16 (riscv_ppairo GPRPair:$rs1, GPRPair:$rs2)),
+ (PPAIRO_DH GPRPair:$rs1, GPRPair:$rs2)>;
// Sign-extend patterns using pwadd with zero
def : Pat<(v4i16 (sext (v4i8 GPR:$rs))), (PWADD_B GPR:$rs, (v4i8 X0))>;
@@ -2567,15 +2574,6 @@ let append Predicates = [IsRV32] in {
def : Pat<(v2i32 (build_vector (XLenVT GPR:$a), (XLenVT GPR:$b))),
(BuildGPRPair GPR:$a, GPR:$b)>;
- def : Pat<(v8i8 (riscv_ppaire GPRPair:$rs1, GPRPair:$rs2)),
- (PPAIRE_DB GPRPair:$rs1, GPRPair:$rs2)>;
- def : Pat<(v8i8 (riscv_ppairo GPRPair:$rs1, GPRPair:$rs2)),
- (PPAIRO_DB GPRPair:$rs1, GPRPair:$rs2)>;
- def : Pat<(v4i16 (riscv_ppaire GPRPair:$rs1, GPRPair:$rs2)),
- (PPAIRE_DH GPRPair:$rs1, GPRPair:$rs2)>;
- def : Pat<(v4i16 (riscv_ppairo GPRPair:$rs1, GPRPair:$rs2)),
- (PPAIRO_DH GPRPair:$rs1, GPRPair:$rs2)>;
-
// Concat vector patterns
def : Pat<(v8i8 (concat_vectors (v4i8 GPR:$a), (v4i8 GPR:$b))),
(BuildGPRPair GPR:$a, GPR:$b)>;
@@ -2853,8 +2851,7 @@ let append Predicates = [IsRV64] in {
def : Pat<(v4i16 (riscv_pzip (v4i16 GPR:$rs1), (v4i16 GPR:$rs2))),
(ZIP16P GPR:$rs1, GPR:$rs2)>;
- // Packed narrowing zip: pair the low (even) / high (odd) byte/halfword of
- // each widened element of rs1 and rs2.
+ // Packed pair: pair the even/odd-position elements of rs1 and rs2.
def : Pat<(v8i8 (riscv_ppaire (v8i8 GPR:$rs1), (v8i8 GPR:$rs2))),
(PPAIRE_B GPR:$rs1, GPR:$rs2)>;
def : Pat<(v8i8 (riscv_ppairo (v8i8 GPR:$rs1), (v8i8 GPR:$rs2))),
@@ -2863,6 +2860,7 @@ let append Predicates = [IsRV64] in {
(PPAIRE_H GPR:$rs1, GPR:$rs2)>;
def : Pat<(v4i16 (riscv_ppairo (v4i16 GPR:$rs1), (v4i16 GPR:$rs2))),
(PPAIRO_H GPR:$rs1, GPR:$rs2)>;
+
// Sign extend inreg patterns using psext. sext_invec is lowered to
// zext_invec+sext_inreg.
def : Pat<(v4i16 (sext_inreg GPR:$rs1, v4i8)), (PSEXT_H_B GPR:$rs1)>;
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