[clang] [llvm] [RegAlloc] [X86] Enable callee saved register optimization for x86 (PR #188609)

[Shreeyash Pandey via cfe-commits]

bojle wrote:

Hi @weiguozhi, @hstk30-hw, @williamweixiao,

I've been looking at a SPEC codegen gap on AArch64 and enabled this optimization for AArch64 via the target scale hook. Baseline is the same tree with the CSR change reverted; SPECint rate refrate, single iteration. I added remat-awareness to this patch (can be found here https://github.com/bojle/llvm-project/tree/x86-csr), following numbers are from this patch.

Net SPECint is essentially flat, and I'd treat the ~1% on most benchmarks as noise. The one signal I trust is perlbench: in a controlled A/B it's ~2.4% faster - reproducible.

Perf +% vs. baseline (single-iteration refrate)

```
Benchmark         scale=80   scale=30
500.perlbench_r    +1.62%     +0.50%
505.mcf_r          -0.82%     -0.03%
523.xalancbmk_r    -1.57%     +0.20%
525.x264_r         +0.05%     +0.20%
531.deepsjeng_r    -1.03%     -0.73%
541.leela_r        +1.17%     +1.23%
557.xz_r           -0.25%     -0.72%
```

I am in support of this patch landing, though curious how scale calculation can be made a little more scientific and data-driven.


https://github.com/llvm/llvm-project/pull/188609