[clang] [CIR][AArch64] Upstream store (vst1_*/vst1q_*) NEON builtins (PR #209347)
Vicky Nguyen via cfe-commits
cfe-commits at lists.llvm.org
Mon Jul 13 17:50:28 PDT 2026
https://github.com/iamvickynguyen updated https://github.com/llvm/llvm-project/pull/209347
>From 427a0fa5bfa730cc34af5be6daf1bcc7435089a8 Mon Sep 17 00:00:00 2001
From: Vicky Nguyen <vicky.trucviennguyen at gmail.com>
Date: Mon, 13 Jul 2026 15:26:54 -0700
Subject: [PATCH] [CIR][AArch64] Upstream store (vst1_*/vst1q_*) NEON builtins
---
.../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 51 +-
clang/test/CodeGen/AArch64/neon-intrinsics.c | 660 -------
clang/test/CodeGen/AArch64/neon-ldst-one.c | 381 ----
clang/test/CodeGen/AArch64/neon/store.c | 1642 +++++++++++++++++
clang/test/CodeGen/AArch64/poly64.c | 24 -
5 files changed, 1690 insertions(+), 1068 deletions(-)
create mode 100644 clang/test/CodeGen/AArch64/neon/store.c
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index 2608aaf780591..63e339b72f0dc 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -1065,7 +1065,17 @@ static mlir::Value emitCommonNeonBuiltinExpr(
case NEON::BI__builtin_neon_vst1_x3_v:
case NEON::BI__builtin_neon_vst1q_x3_v:
case NEON::BI__builtin_neon_vst1_x4_v:
- case NEON::BI__builtin_neon_vst1q_x4_v:
+ case NEON::BI__builtin_neon_vst1q_x4_v: {
+ // The builtin call has the pointer first, but the AArch64 st1x2/3/4
+ // intrinsics take the vector operands first and the pointer last.
+ std::rotate(ops.begin(), ops.begin() + 1, ops.end());
+ llvm::SmallVector<mlir::Type> argTypes(ops.size() - 1, ty);
+ argTypes.push_back(cgf.getBuilder().getVoidPtrTy());
+ llvm::StringRef llvmIntrName = getLLVMIntrNameNoPrefix(
+ static_cast<llvm::Intrinsic::ID>(llvmIntrinsic));
+ return emitNeonCall(cgf.getCIRGenModule(), cgf.getBuilder(), argTypes, ops,
+ llvmIntrName, cgf.cgm.voidTy, loc);
+ }
case NEON::BI__builtin_neon_vtrn_v:
case NEON::BI__builtin_neon_vtrnq_v:
case NEON::BI__builtin_neon_vtst_v:
@@ -2345,6 +2355,11 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
assert(error == ASTContext::GE_None && "Should not codegen an error");
llvm::SmallVector<mlir::Value> ops;
+ // Captures the pointer and its alignment for builtins that store/load
+ // directly through the first argument (set in the arg-gathering loop
+ // below, used later when lowering the store/load itself).
+ Address ptrOp0 = Address::invalid();
+
// Skip extra arguments used to discriminate vector types and that are
// intended for Sema checking.
bool hasExtraArg = hasExtraNeonArgument(builtinID);
@@ -2358,10 +2373,20 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
case NEON::BI__builtin_neon_vld1q_dup_v:
case NEON::BI__builtin_neon_vld1_lane_v:
case NEON::BI__builtin_neon_vld1q_lane_v:
+ cgm.errorNYI(
+ expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin argument handling ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ break;
case NEON::BI__builtin_neon_vst1_v:
case NEON::BI__builtin_neon_vst1q_v:
case NEON::BI__builtin_neon_vst1_lane_v:
case NEON::BI__builtin_neon_vst1q_lane_v:
+ // Get the alignment for the argument in addition to the value;
+ // we'll use it later.
+ ptrOp0 = emitPointerWithAlignment(expr->getArg(0));
+ ops.push_back(ptrOp0.getPointer());
+ continue;
case NEON::BI__builtin_neon_vldap1_lane_s64:
case NEON::BI__builtin_neon_vldap1q_lane_s64:
case NEON::BI__builtin_neon_vstl1_lane_s64:
@@ -2372,6 +2397,7 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
expr->getSourceRange(),
std::string("unimplemented AArch64 builtin argument handling ") +
getContext().BuiltinInfo.getName(builtinID));
+ break;
}
}
ops.push_back(
@@ -3197,16 +3223,35 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
}
case NEON::BI__builtin_neon_vld1_v:
case NEON::BI__builtin_neon_vld1q_v:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
case NEON::BI__builtin_neon_vst1_v:
- case NEON::BI__builtin_neon_vst1q_v:
+ case NEON::BI__builtin_neon_vst1q_v: {
+ ops[1] = builder.createBitcast(ops[1], ty);
+ builder.createStore(loc, ops[1], ptrOp0.withElementType(builder, ty));
+ return nullptr;
+ }
case NEON::BI__builtin_neon_vld1_lane_v:
case NEON::BI__builtin_neon_vld1q_lane_v:
case NEON::BI__builtin_neon_vldap1_lane_s64:
case NEON::BI__builtin_neon_vldap1q_lane_s64:
case NEON::BI__builtin_neon_vld1_dup_v:
case NEON::BI__builtin_neon_vld1q_dup_v:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
case NEON::BI__builtin_neon_vst1_lane_v:
- case NEON::BI__builtin_neon_vst1q_lane_v:
+ case NEON::BI__builtin_neon_vst1q_lane_v: {
+ ops[1] = builder.createBitcast(ops[1], ty);
+ mlir::Value scalar = builder.createExtractElement(
+ loc, ops[1], static_cast<uint64_t>(getIntValueFromConstOp(ops[2])));
+ builder.createStore(loc, scalar,
+ ptrOp0.withElementType(builder, scalar.getType()));
+ return nullptr;
+ }
case NEON::BI__builtin_neon_vstl1_lane_s64:
case NEON::BI__builtin_neon_vstl1q_lane_s64:
case NEON::BI__builtin_neon_vld2_v:
diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c
index 883897a18cbf6..fe3428c02ba9c 100644
--- a/clang/test/CodeGen/AArch64/neon-intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c
@@ -8020,333 +8020,6 @@ poly16x4x4_t test_vld4_p16(poly16_t const *a) {
return vld4_p16(a);
}
-// CHECK-LABEL: define dso_local void @test_vst1q_u8(
-// CHECK-SAME: ptr noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: store <16 x i8> [[B]], ptr [[A]], align 1
-// CHECK-NEXT: ret void
-//
-void test_vst1q_u8(uint8_t *a, uint8x16_t b) {
- vst1q_u8(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_u16(
-// CHECK-SAME: ptr noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: store <8 x i16> [[TMP1]], ptr [[A]], align 2
-// CHECK-NEXT: ret void
-//
-void test_vst1q_u16(uint16_t *a, uint16x8_t b) {
- vst1q_u16(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_u32(
-// CHECK-SAME: ptr noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
-// CHECK-NEXT: store <4 x i32> [[TMP1]], ptr [[A]], align 4
-// CHECK-NEXT: ret void
-//
-void test_vst1q_u32(uint32_t *a, uint32x4_t b) {
- vst1q_u32(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_u64(
-// CHECK-SAME: ptr noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: store <2 x i64> [[TMP1]], ptr [[A]], align 8
-// CHECK-NEXT: ret void
-//
-void test_vst1q_u64(uint64_t *a, uint64x2_t b) {
- vst1q_u64(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_s8(
-// CHECK-SAME: ptr noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: store <16 x i8> [[B]], ptr [[A]], align 1
-// CHECK-NEXT: ret void
-//
-void test_vst1q_s8(int8_t *a, int8x16_t b) {
- vst1q_s8(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_s16(
-// CHECK-SAME: ptr noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: store <8 x i16> [[TMP1]], ptr [[A]], align 2
-// CHECK-NEXT: ret void
-//
-void test_vst1q_s16(int16_t *a, int16x8_t b) {
- vst1q_s16(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_s32(
-// CHECK-SAME: ptr noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
-// CHECK-NEXT: store <4 x i32> [[TMP1]], ptr [[A]], align 4
-// CHECK-NEXT: ret void
-//
-void test_vst1q_s32(int32_t *a, int32x4_t b) {
- vst1q_s32(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_s64(
-// CHECK-SAME: ptr noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: store <2 x i64> [[TMP1]], ptr [[A]], align 8
-// CHECK-NEXT: ret void
-//
-void test_vst1q_s64(int64_t *a, int64x2_t b) {
- vst1q_s64(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_mf8(
-// CHECK-SAME: ptr noundef [[A:%.*]], <16 x i8> [[VAL:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: store <16 x i8> [[VAL]], ptr [[A]], align 1
-// CHECK-NEXT: ret void
-//
-void test_vst1q_mf8(mfloat8_t *a, mfloat8x16_t val) {
- vst1q_mf8(a, val);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_f16(
-// CHECK-SAME: ptr noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[B]] to <8 x i16>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>
-// CHECK-NEXT: store <8 x half> [[TMP2]], ptr [[A]], align 2
-// CHECK-NEXT: ret void
-//
-void test_vst1q_f16(float16_t *a, float16x8_t b) {
- vst1q_f16(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_f32(
-// CHECK-SAME: ptr noundef [[A:%.*]], <4 x float> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[B]] to <4 x i32>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
-// CHECK-NEXT: store <4 x float> [[TMP2]], ptr [[A]], align 4
-// CHECK-NEXT: ret void
-//
-void test_vst1q_f32(float32_t *a, float32x4_t b) {
- vst1q_f32(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_f64(
-// CHECK-SAME: ptr noundef [[A:%.*]], <2 x double> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[B]] to <2 x i64>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
-// CHECK-NEXT: store <2 x double> [[TMP2]], ptr [[A]], align 8
-// CHECK-NEXT: ret void
-//
-void test_vst1q_f64(float64_t *a, float64x2_t b) {
- vst1q_f64(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_p8(
-// CHECK-SAME: ptr noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: store <16 x i8> [[B]], ptr [[A]], align 1
-// CHECK-NEXT: ret void
-//
-void test_vst1q_p8(poly8_t *a, poly8x16_t b) {
- vst1q_p8(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_p16(
-// CHECK-SAME: ptr noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: store <8 x i16> [[TMP1]], ptr [[A]], align 2
-// CHECK-NEXT: ret void
-//
-void test_vst1q_p16(poly16_t *a, poly16x8_t b) {
- vst1q_p16(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_u8(
-// CHECK-SAME: ptr noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: store <8 x i8> [[B]], ptr [[A]], align 1
-// CHECK-NEXT: ret void
-//
-void test_vst1_u8(uint8_t *a, uint8x8_t b) {
- vst1_u8(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_u16(
-// CHECK-SAME: ptr noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: store <4 x i16> [[TMP1]], ptr [[A]], align 2
-// CHECK-NEXT: ret void
-//
-void test_vst1_u16(uint16_t *a, uint16x4_t b) {
- vst1_u16(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_u32(
-// CHECK-SAME: ptr noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
-// CHECK-NEXT: store <2 x i32> [[TMP1]], ptr [[A]], align 4
-// CHECK-NEXT: ret void
-//
-void test_vst1_u32(uint32_t *a, uint32x2_t b) {
- vst1_u32(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_u64(
-// CHECK-SAME: ptr noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: store <1 x i64> [[TMP1]], ptr [[A]], align 8
-// CHECK-NEXT: ret void
-//
-void test_vst1_u64(uint64_t *a, uint64x1_t b) {
- vst1_u64(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_s8(
-// CHECK-SAME: ptr noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: store <8 x i8> [[B]], ptr [[A]], align 1
-// CHECK-NEXT: ret void
-//
-void test_vst1_s8(int8_t *a, int8x8_t b) {
- vst1_s8(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_s16(
-// CHECK-SAME: ptr noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: store <4 x i16> [[TMP1]], ptr [[A]], align 2
-// CHECK-NEXT: ret void
-//
-void test_vst1_s16(int16_t *a, int16x4_t b) {
- vst1_s16(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_s32(
-// CHECK-SAME: ptr noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
-// CHECK-NEXT: store <2 x i32> [[TMP1]], ptr [[A]], align 4
-// CHECK-NEXT: ret void
-//
-void test_vst1_s32(int32_t *a, int32x2_t b) {
- vst1_s32(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_s64(
-// CHECK-SAME: ptr noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: store <1 x i64> [[TMP1]], ptr [[A]], align 8
-// CHECK-NEXT: ret void
-//
-void test_vst1_s64(int64_t *a, int64x1_t b) {
- vst1_s64(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_mf8(
-// CHECK-SAME: ptr noundef [[A:%.*]], <8 x i8> [[VAL:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: store <8 x i8> [[VAL]], ptr [[A]], align 1
-// CHECK-NEXT: ret void
-//
-void test_vst1_mf8(mfloat8_t *a, mfloat8x8_t val) {
- vst1_mf8(a, val);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_f16(
-// CHECK-SAME: ptr noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[B]] to <4 x i16>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half>
-// CHECK-NEXT: store <4 x half> [[TMP2]], ptr [[A]], align 2
-// CHECK-NEXT: ret void
-//
-void test_vst1_f16(float16_t *a, float16x4_t b) {
- vst1_f16(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_f32(
-// CHECK-SAME: ptr noundef [[A:%.*]], <2 x float> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[B]] to <2 x i32>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
-// CHECK-NEXT: store <2 x float> [[TMP2]], ptr [[A]], align 4
-// CHECK-NEXT: ret void
-//
-void test_vst1_f32(float32_t *a, float32x2_t b) {
- vst1_f32(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_f64(
-// CHECK-SAME: ptr noundef [[A:%.*]], <1 x double> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x double> [[B]] to i64
-// CHECK-NEXT: [[__S1_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[__S1_SROA_0_0_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double>
-// CHECK-NEXT: store <1 x double> [[TMP2]], ptr [[A]], align 8
-// CHECK-NEXT: ret void
-//
-void test_vst1_f64(float64_t *a, float64x1_t b) {
- vst1_f64(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_p8(
-// CHECK-SAME: ptr noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: store <8 x i8> [[B]], ptr [[A]], align 1
-// CHECK-NEXT: ret void
-//
-void test_vst1_p8(poly8_t *a, poly8x8_t b) {
- vst1_p8(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_p16(
-// CHECK-SAME: ptr noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: store <4 x i16> [[TMP1]], ptr [[A]], align 2
-// CHECK-NEXT: ret void
-//
-void test_vst1_p16(poly16_t *a, poly16x4_t b) {
- vst1_p16(a, b);
-}
-
// CHECK-LABEL: define dso_local void @test_vst2q_u8(
// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <16 x i8>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
@@ -10151,339 +9824,6 @@ poly64x1x4_t test_vld1_p64_x4(poly64_t const *a) {
return vld1_p64_x4(a);
}
-// CHECK-LABEL: define dso_local void @test_vst1q_mf8_x2(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <16 x i8>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <16 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <16 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: call void @llvm.aarch64.neon.st1x2.v16i8.p0(<16 x i8> [[B_COERCE_FCA_0_EXTRACT]], <16 x i8> [[B_COERCE_FCA_1_EXTRACT]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst1q_mf8_x2(mfloat8_t *a, mfloat8x16x2_t b) {
- vst1q_mf8_x2(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_f64_x2(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <2 x double>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <2 x double>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[B_COERCE_FCA_0_EXTRACT]] to <2 x i64>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <2 x double>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[B_COERCE_FCA_1_EXTRACT]] to <2 x i64>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP1]] to <16 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x double>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP3]] to <2 x double>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st1x2.v2f64.p0(<2 x double> [[TMP4]], <2 x double> [[TMP5]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst1q_f64_x2(float64_t *a, float64x2x2_t b) {
- vst1q_f64_x2(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_p64_x2(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <2 x i64>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <2 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <2 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st1x2.v2i64.p0(<2 x i64> [[TMP2]], <2 x i64> [[TMP3]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst1q_p64_x2(poly64_t *a, poly64x2x2_t b) {
- vst1q_p64_x2(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_mf8_x2(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <8 x i8>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <8 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <8 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: call void @llvm.aarch64.neon.st1x2.v8i8.p0(<8 x i8> [[B_COERCE_FCA_0_EXTRACT]], <8 x i8> [[B_COERCE_FCA_1_EXTRACT]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst1_mf8_x2(mfloat8_t *a, mfloat8x8x2_t b) {
- vst1_mf8_x2(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_f64_x2(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <1 x double>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <1 x double>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x double> [[B_COERCE_FCA_0_EXTRACT]] to i64
-// CHECK-NEXT: [[B_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <1 x double>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x double> [[B_COERCE_FCA_1_EXTRACT]] to i64
-// CHECK-NEXT: [[B_SROA_2_8_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP1]], i64 0
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <1 x i64> [[B_SROA_0_0_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[B_SROA_2_8_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x double>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP3]] to <1 x double>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st1x2.v1f64.p0(<1 x double> [[TMP4]], <1 x double> [[TMP5]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst1_f64_x2(float64_t *a, float64x1x2_t b) {
- vst1_f64_x2(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_p64_x2(
-// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <1 x i64>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [2 x <1 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [2 x <1 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st1x2.v1i64.p0(<1 x i64> [[TMP2]], <1 x i64> [[TMP3]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst1_p64_x2(poly64_t *a, poly64x1x2_t b) {
- vst1_p64_x2(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_mf8_x3(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <16 x i8>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <16 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <16 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <16 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: call void @llvm.aarch64.neon.st1x3.v16i8.p0(<16 x i8> [[B_COERCE_FCA_0_EXTRACT]], <16 x i8> [[B_COERCE_FCA_1_EXTRACT]], <16 x i8> [[B_COERCE_FCA_2_EXTRACT]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst1q_mf8_x3(mfloat8_t *a, mfloat8x16x3_t b) {
- vst1q_mf8_x3(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_f64_x3(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <2 x double>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <2 x double>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[B_COERCE_FCA_0_EXTRACT]] to <2 x i64>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <2 x double>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[B_COERCE_FCA_1_EXTRACT]] to <2 x i64>
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <2 x double>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x double> [[B_COERCE_FCA_2_EXTRACT]] to <2 x i64>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP1]] to <16 x i8>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP2]] to <16 x i8>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP3]] to <2 x double>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP4]] to <2 x double>
-// CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x double>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st1x3.v2f64.p0(<2 x double> [[TMP6]], <2 x double> [[TMP7]], <2 x double> [[TMP8]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst1q_f64_x3(float64_t *a, float64x2x3_t b) {
- vst1q_f64_x3(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_p64_x3(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <2 x i64>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <2 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <2 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <2 x i64>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st1x3.v2i64.p0(<2 x i64> [[TMP3]], <2 x i64> [[TMP4]], <2 x i64> [[TMP5]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst1q_p64_x3(poly64_t *a, poly64x2x3_t b) {
- vst1q_p64_x3(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_mf8_x3(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <8 x i8>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <8 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <8 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <8 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: call void @llvm.aarch64.neon.st1x3.v8i8.p0(<8 x i8> [[B_COERCE_FCA_0_EXTRACT]], <8 x i8> [[B_COERCE_FCA_1_EXTRACT]], <8 x i8> [[B_COERCE_FCA_2_EXTRACT]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst1_mf8_x3(mfloat8_t *a, mfloat8x8x3_t b) {
- vst1_mf8_x3(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_f64_x3(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <1 x double>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <1 x double>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x double> [[B_COERCE_FCA_0_EXTRACT]] to i64
-// CHECK-NEXT: [[B_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <1 x double>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x double> [[B_COERCE_FCA_1_EXTRACT]] to i64
-// CHECK-NEXT: [[B_SROA_2_8_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP1]], i64 0
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <1 x double>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <1 x double> [[B_COERCE_FCA_2_EXTRACT]] to i64
-// CHECK-NEXT: [[B_SROA_4_16_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i64 0
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[B_SROA_0_0_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i64> [[B_SROA_2_8_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[B_SROA_4_16_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP3]] to <1 x double>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP4]] to <1 x double>
-// CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP5]] to <1 x double>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st1x3.v1f64.p0(<1 x double> [[TMP6]], <1 x double> [[TMP7]], <1 x double> [[TMP8]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst1_f64_x3(float64_t *a, float64x1x3_t b) {
- vst1_f64_x3(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_p64_x3(
-// CHECK-SAME: ptr noundef [[A:%.*]], [3 x <1 x i64>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [3 x <1 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [3 x <1 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [3 x <1 x i64>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st1x3.v1i64.p0(<1 x i64> [[TMP3]], <1 x i64> [[TMP4]], <1 x i64> [[TMP5]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst1_p64_x3(poly64_t *a, poly64x1x3_t b) {
- vst1_p64_x3(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_mf8_x4(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <16 x i8>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <16 x i8>] [[B_COERCE]], 3
-// CHECK-NEXT: call void @llvm.aarch64.neon.st1x4.v16i8.p0(<16 x i8> [[B_COERCE_FCA_0_EXTRACT]], <16 x i8> [[B_COERCE_FCA_1_EXTRACT]], <16 x i8> [[B_COERCE_FCA_2_EXTRACT]], <16 x i8> [[B_COERCE_FCA_3_EXTRACT]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst1q_mf8_x4(mfloat8_t *a, mfloat8x16x4_t b) {
- vst1q_mf8_x4(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_f64_x4(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <2 x double>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <2 x double>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[B_COERCE_FCA_0_EXTRACT]] to <2 x i64>
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <2 x double>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[B_COERCE_FCA_1_EXTRACT]] to <2 x i64>
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <2 x double>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x double> [[B_COERCE_FCA_2_EXTRACT]] to <2 x i64>
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <2 x double>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x double> [[B_COERCE_FCA_3_EXTRACT]] to <2 x i64>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP1]] to <16 x i8>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i64> [[TMP2]] to <16 x i8>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP3]] to <16 x i8>
-// CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP4]] to <2 x double>
-// CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x double>
-// CHECK-NEXT: [[TMP10:%.*]] = bitcast <16 x i8> [[TMP6]] to <2 x double>
-// CHECK-NEXT: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP7]] to <2 x double>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st1x4.v2f64.p0(<2 x double> [[TMP8]], <2 x double> [[TMP9]], <2 x double> [[TMP10]], <2 x double> [[TMP11]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst1q_f64_x4(float64_t *a, float64x2x4_t b) {
- vst1q_f64_x4(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_p64_x4(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <2 x i64>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <2 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <2 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <2 x i64>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <2 x i64>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_2_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[B_COERCE_FCA_3_EXTRACT]] to <16 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP3]] to <2 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st1x4.v2i64.p0(<2 x i64> [[TMP4]], <2 x i64> [[TMP5]], <2 x i64> [[TMP6]], <2 x i64> [[TMP7]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst1q_p64_x4(poly64_t *a, poly64x2x4_t b) {
- vst1q_p64_x4(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_mf8_x4(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <8 x i8>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <8 x i8>] [[B_COERCE]], 3
-// CHECK-NEXT: call void @llvm.aarch64.neon.st1x4.v8i8.p0(<8 x i8> [[B_COERCE_FCA_0_EXTRACT]], <8 x i8> [[B_COERCE_FCA_1_EXTRACT]], <8 x i8> [[B_COERCE_FCA_2_EXTRACT]], <8 x i8> [[B_COERCE_FCA_3_EXTRACT]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst1_mf8_x4(mfloat8_t *a, mfloat8x8x4_t b) {
- vst1_mf8_x4(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_f64_x4(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <1 x double>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <1 x double>] [[B_COERCE]], 0
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x double> [[B_COERCE_FCA_0_EXTRACT]] to i64
-// CHECK-NEXT: [[B_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <1 x double>] [[B_COERCE]], 1
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x double> [[B_COERCE_FCA_1_EXTRACT]] to i64
-// CHECK-NEXT: [[B_SROA_2_8_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP1]], i64 0
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <1 x double>] [[B_COERCE]], 2
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <1 x double> [[B_COERCE_FCA_2_EXTRACT]] to i64
-// CHECK-NEXT: [[B_SROA_4_16_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i64 0
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <1 x double>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x double> [[B_COERCE_FCA_3_EXTRACT]] to i64
-// CHECK-NEXT: [[B_SROA_6_24_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP3]], i64 0
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i64> [[B_SROA_0_0_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[B_SROA_2_8_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <1 x i64> [[B_SROA_4_16_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <1 x i64> [[B_SROA_6_24_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP4]] to <1 x double>
-// CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP5]] to <1 x double>
-// CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x i8> [[TMP6]] to <1 x double>
-// CHECK-NEXT: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP7]] to <1 x double>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st1x4.v1f64.p0(<1 x double> [[TMP8]], <1 x double> [[TMP9]], <1 x double> [[TMP10]], <1 x double> [[TMP11]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst1_f64_x4(float64_t *a, float64x1x4_t b) {
- vst1_f64_x4(a, b);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_p64_x4(
-// CHECK-SAME: ptr noundef [[A:%.*]], [4 x <1 x i64>] alignstack(8) [[B_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[B_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x <1 x i64>] [[B_COERCE]], 0
-// CHECK-NEXT: [[B_COERCE_FCA_1_EXTRACT:%.*]] = extractvalue [4 x <1 x i64>] [[B_COERCE]], 1
-// CHECK-NEXT: [[B_COERCE_FCA_2_EXTRACT:%.*]] = extractvalue [4 x <1 x i64>] [[B_COERCE]], 2
-// CHECK-NEXT: [[B_COERCE_FCA_3_EXTRACT:%.*]] = extractvalue [4 x <1 x i64>] [[B_COERCE]], 3
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_0_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_1_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_2_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[B_COERCE_FCA_3_EXTRACT]] to <8 x i8>
-// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x i64>
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP3]] to <1 x i64>
-// CHECK-NEXT: call void @llvm.aarch64.neon.st1x4.v1i64.p0(<1 x i64> [[TMP4]], <1 x i64> [[TMP5]], <1 x i64> [[TMP6]], <1 x i64> [[TMP7]], ptr [[A]])
-// CHECK-NEXT: ret void
-//
-void test_vst1_p64_x4(poly64_t *a, poly64x1x4_t b) {
- vst1_p64_x4(a, b);
-}
-
// CHECK-LABEL: define dso_local i64 @test_vceqd_s64(
// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
diff --git a/clang/test/CodeGen/AArch64/neon-ldst-one.c b/clang/test/CodeGen/AArch64/neon-ldst-one.c
index 8f99c4bfcccd1..915788867a94c 100644
--- a/clang/test/CodeGen/AArch64/neon-ldst-one.c
+++ b/clang/test/CodeGen/AArch64/neon-ldst-one.c
@@ -3308,387 +3308,6 @@ poly64x1x4_t test_vld4_lane_p64(poly64_t *a, poly64x1x4_t b) {
return vld4_lane_p64(a, b, 0);
}
-// CHECK-LABEL: define dso_local void @test_vst1q_lane_u8(
-// CHECK-SAME: ptr noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = extractelement <16 x i8> [[B]], i32 15
-// CHECK-NEXT: store i8 [[TMP0]], ptr [[A]], align 1
-// CHECK-NEXT: ret void
-//
-void test_vst1q_lane_u8(uint8_t *a, uint8x16_t b) {
- vst1q_lane_u8(a, b, 15);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_lane_u16(
-// CHECK-SAME: ptr noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x i16> [[TMP1]], i32 7
-// CHECK-NEXT: store i16 [[TMP2]], ptr [[A]], align 2
-// CHECK-NEXT: ret void
-//
-void test_vst1q_lane_u16(uint16_t *a, uint16x8_t b) {
- vst1q_lane_u16(a, b, 7);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_lane_u32(
-// CHECK-SAME: ptr noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
-// CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3
-// CHECK-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK-NEXT: ret void
-//
-void test_vst1q_lane_u32(uint32_t *a, uint32x4_t b) {
- vst1q_lane_u32(a, b, 3);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_lane_u64(
-// CHECK-SAME: ptr noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[TMP1]], i32 1
-// CHECK-NEXT: store i64 [[TMP2]], ptr [[A]], align 8
-// CHECK-NEXT: ret void
-//
-void test_vst1q_lane_u64(uint64_t *a, uint64x2_t b) {
- vst1q_lane_u64(a, b, 1);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_lane_s8(
-// CHECK-SAME: ptr noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = extractelement <16 x i8> [[B]], i32 15
-// CHECK-NEXT: store i8 [[TMP0]], ptr [[A]], align 1
-// CHECK-NEXT: ret void
-//
-void test_vst1q_lane_s8(int8_t *a, int8x16_t b) {
- vst1q_lane_s8(a, b, 15);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_lane_s16(
-// CHECK-SAME: ptr noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x i16> [[TMP1]], i32 7
-// CHECK-NEXT: store i16 [[TMP2]], ptr [[A]], align 2
-// CHECK-NEXT: ret void
-//
-void test_vst1q_lane_s16(int16_t *a, int16x8_t b) {
- vst1q_lane_s16(a, b, 7);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_lane_s32(
-// CHECK-SAME: ptr noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
-// CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3
-// CHECK-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK-NEXT: ret void
-//
-void test_vst1q_lane_s32(int32_t *a, int32x4_t b) {
- vst1q_lane_s32(a, b, 3);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_lane_s64(
-// CHECK-SAME: ptr noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[TMP1]], i32 1
-// CHECK-NEXT: store i64 [[TMP2]], ptr [[A]], align 8
-// CHECK-NEXT: ret void
-//
-void test_vst1q_lane_s64(int64_t *a, int64x2_t b) {
- vst1q_lane_s64(a, b, 1);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_lane_mf8(
-// CHECK-SAME: ptr noundef [[A:%.*]], <16 x i8> [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = extractelement <16 x i8> [[B]], i32 15
-// CHECK-NEXT: store i8 [[TMP0]], ptr [[A]], align 1
-// CHECK-NEXT: ret void
-//
-void test_vst1q_lane_mf8(mfloat8_t *a, mfloat8x16_t b) {
- vst1q_lane_mf8(a, b, 15);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_lane_f16(
-// CHECK-SAME: ptr noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[B]] to <8 x i16>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>
-// CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x half> [[TMP2]], i32 7
-// CHECK-NEXT: store half [[TMP3]], ptr [[A]], align 2
-// CHECK-NEXT: ret void
-//
-void test_vst1q_lane_f16(float16_t *a, float16x8_t b) {
- vst1q_lane_f16(a, b, 7);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_lane_f32(
-// CHECK-SAME: ptr noundef [[A:%.*]], <4 x float> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[B]] to <4 x i32>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
-// CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x float> [[TMP2]], i32 3
-// CHECK-NEXT: store float [[TMP3]], ptr [[A]], align 4
-// CHECK-NEXT: ret void
-//
-void test_vst1q_lane_f32(float32_t *a, float32x4_t b) {
- vst1q_lane_f32(a, b, 3);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_lane_f64(
-// CHECK-SAME: ptr noundef [[A:%.*]], <2 x double> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[B]] to <2 x i64>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
-// CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x double> [[TMP2]], i32 1
-// CHECK-NEXT: store double [[TMP3]], ptr [[A]], align 8
-// CHECK-NEXT: ret void
-//
-void test_vst1q_lane_f64(float64_t *a, float64x2_t b) {
- vst1q_lane_f64(a, b, 1);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_lane_p8(
-// CHECK-SAME: ptr noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = extractelement <16 x i8> [[B]], i32 15
-// CHECK-NEXT: store i8 [[TMP0]], ptr [[A]], align 1
-// CHECK-NEXT: ret void
-//
-void test_vst1q_lane_p8(poly8_t *a, poly8x16_t b) {
- vst1q_lane_p8(a, b, 15);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_lane_p16(
-// CHECK-SAME: ptr noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x i16> [[TMP1]], i32 7
-// CHECK-NEXT: store i16 [[TMP2]], ptr [[A]], align 2
-// CHECK-NEXT: ret void
-//
-void test_vst1q_lane_p16(poly16_t *a, poly16x8_t b) {
- vst1q_lane_p16(a, b, 7);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_lane_p64(
-// CHECK-SAME: ptr noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[TMP1]], i32 1
-// CHECK-NEXT: store i64 [[TMP2]], ptr [[A]], align 8
-// CHECK-NEXT: ret void
-//
-void test_vst1q_lane_p64(poly64_t *a, poly64x2_t b) {
- vst1q_lane_p64(a, b, 1);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_lane_u8(
-// CHECK-SAME: ptr noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = extractelement <8 x i8> [[B]], i32 7
-// CHECK-NEXT: store i8 [[TMP0]], ptr [[A]], align 1
-// CHECK-NEXT: ret void
-//
-void test_vst1_lane_u8(uint8_t *a, uint8x8_t b) {
- vst1_lane_u8(a, b, 7);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_lane_u16(
-// CHECK-SAME: ptr noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i16> [[TMP1]], i32 3
-// CHECK-NEXT: store i16 [[TMP2]], ptr [[A]], align 2
-// CHECK-NEXT: ret void
-//
-void test_vst1_lane_u16(uint16_t *a, uint16x4_t b) {
- vst1_lane_u16(a, b, 3);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_lane_u32(
-// CHECK-SAME: ptr noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
-// CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
-// CHECK-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK-NEXT: ret void
-//
-void test_vst1_lane_u32(uint32_t *a, uint32x2_t b) {
- vst1_lane_u32(a, b, 1);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_lane_u64(
-// CHECK-SAME: ptr noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x i64> [[TMP1]], i32 0
-// CHECK-NEXT: store i64 [[TMP2]], ptr [[A]], align 8
-// CHECK-NEXT: ret void
-//
-void test_vst1_lane_u64(uint64_t *a, uint64x1_t b) {
- vst1_lane_u64(a, b, 0);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_lane_s8(
-// CHECK-SAME: ptr noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = extractelement <8 x i8> [[B]], i32 7
-// CHECK-NEXT: store i8 [[TMP0]], ptr [[A]], align 1
-// CHECK-NEXT: ret void
-//
-void test_vst1_lane_s8(int8_t *a, int8x8_t b) {
- vst1_lane_s8(a, b, 7);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_lane_s16(
-// CHECK-SAME: ptr noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i16> [[TMP1]], i32 3
-// CHECK-NEXT: store i16 [[TMP2]], ptr [[A]], align 2
-// CHECK-NEXT: ret void
-//
-void test_vst1_lane_s16(int16_t *a, int16x4_t b) {
- vst1_lane_s16(a, b, 3);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_lane_s32(
-// CHECK-SAME: ptr noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
-// CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
-// CHECK-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK-NEXT: ret void
-//
-void test_vst1_lane_s32(int32_t *a, int32x2_t b) {
- vst1_lane_s32(a, b, 1);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_lane_s64(
-// CHECK-SAME: ptr noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x i64> [[TMP1]], i32 0
-// CHECK-NEXT: store i64 [[TMP2]], ptr [[A]], align 8
-// CHECK-NEXT: ret void
-//
-void test_vst1_lane_s64(int64_t *a, int64x1_t b) {
- vst1_lane_s64(a, b, 0);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_lane_mf8(
-// CHECK-SAME: ptr noundef [[A:%.*]], <8 x i8> [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = extractelement <8 x i8> [[B]], i32 7
-// CHECK-NEXT: store i8 [[TMP0]], ptr [[A]], align 1
-// CHECK-NEXT: ret void
-//
-void test_vst1_lane_mf8(mfloat8_t *a, mfloat8x8_t b) {
- vst1_lane_mf8(a, b, 7);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_lane_f16(
-// CHECK-SAME: ptr noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[B]] to <4 x i16>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half>
-// CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x half> [[TMP2]], i32 3
-// CHECK-NEXT: store half [[TMP3]], ptr [[A]], align 2
-// CHECK-NEXT: ret void
-//
-void test_vst1_lane_f16(float16_t *a, float16x4_t b) {
- vst1_lane_f16(a, b, 3);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_lane_f32(
-// CHECK-SAME: ptr noundef [[A:%.*]], <2 x float> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[B]] to <2 x i32>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
-// CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i32 1
-// CHECK-NEXT: store float [[TMP3]], ptr [[A]], align 4
-// CHECK-NEXT: ret void
-//
-void test_vst1_lane_f32(float32_t *a, float32x2_t b) {
- vst1_lane_f32(a, b, 1);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_lane_f64(
-// CHECK-SAME: ptr noundef [[A:%.*]], <1 x double> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x double> [[B]] to i64
-// CHECK-NEXT: [[__S1_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[__S1_SROA_0_0_VEC_INSERT]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double>
-// CHECK-NEXT: [[TMP3:%.*]] = extractelement <1 x double> [[TMP2]], i32 0
-// CHECK-NEXT: store double [[TMP3]], ptr [[A]], align 8
-// CHECK-NEXT: ret void
-//
-void test_vst1_lane_f64(float64_t *a, float64x1_t b) {
- vst1_lane_f64(a, b, 0);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_lane_p8(
-// CHECK-SAME: ptr noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = extractelement <8 x i8> [[B]], i32 7
-// CHECK-NEXT: store i8 [[TMP0]], ptr [[A]], align 1
-// CHECK-NEXT: ret void
-//
-void test_vst1_lane_p8(poly8_t *a, poly8x8_t b) {
- vst1_lane_p8(a, b, 7);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_lane_p16(
-// CHECK-SAME: ptr noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i16> [[TMP1]], i32 3
-// CHECK-NEXT: store i16 [[TMP2]], ptr [[A]], align 2
-// CHECK-NEXT: ret void
-//
-void test_vst1_lane_p16(poly16_t *a, poly16x4_t b) {
- vst1_lane_p16(a, b, 3);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1_lane_p64(
-// CHECK-SAME: ptr noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x i64> [[TMP1]], i32 0
-// CHECK-NEXT: store i64 [[TMP2]], ptr [[A]], align 8
-// CHECK-NEXT: ret void
-//
-void test_vst1_lane_p64(poly64_t *a, poly64x1_t b) {
- vst1_lane_p64(a, b, 0);
-}
-
// CHECK-LABEL: define dso_local void @test_vst2q_lane_u8(
// CHECK-SAME: ptr noundef [[A:%.*]], [2 x <16 x i8>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
diff --git a/clang/test/CodeGen/AArch64/neon/store.c b/clang/test/CodeGen/AArch64/neon/store.c
new file mode 100644
index 0000000000000..1532b56c14995
--- /dev/null
+++ b/clang/test/CodeGen/AArch64/neon/store.c
@@ -0,0 +1,1642 @@
+// REQUIRES: aarch64-registered-target || arm-registered-target
+
+// RUN: %clang_cc1_cg_arm64_neon -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa,instcombine | FileCheck %s --check-prefix=LLVM
+// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon -fclangir -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa,instcombine,simplifycfg | FileCheck %s --check-prefix=LLVM %}
+// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon -fclangir -emit-cir %s -disable-O0-optnone | FileCheck %s --check-prefix=CIR %}
+
+#include <arm_neon.h>
+
+//===------------------------------------------------------===//
+// 2.14.3. Store
+// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#store
+//===------------------------------------------------------===//
+
+// LLVM-LABEL: @test_vst1_f16(
+// CIR-LABEL: @test_vst1_f16(
+void test_vst1_f16(float16_t *a, float16x4_t b) {
+// CIR: cir.store align(2) {{.*}}, {{.*}} : !cir.vector<4 x !cir.f16>, !cir.ptr<!cir.vector<4 x !cir.f16>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <4 x half> noundef {{.*}}[[B:%.*]])
+// LLVM: store <4 x half> [[B]], ptr [[A]], align 2
+// LLVM: ret void
+ vst1_f16(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_f32(
+// CIR-LABEL: @test_vst1_f32(
+void test_vst1_f32(float32_t *a, float32x2_t b) {
+// CIR: cir.store align(4) {{.*}}, {{.*}} : !cir.vector<2 x !cir.float>, !cir.ptr<!cir.vector<2 x !cir.float>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <2 x float> noundef {{.*}}[[B:%.*]])
+// LLVM: store <2 x float> [[B]], ptr [[A]], align 4
+// LLVM: ret void
+ vst1_f32(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_f64(
+// CIR-LABEL: @test_vst1_f64(
+void test_vst1_f64(float64_t *a, float64x1_t b) {
+// CIR: cir.store align(8) {{.*}}, {{.*}} : !cir.vector<1 x !cir.double>, !cir.ptr<!cir.vector<1 x !cir.double>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <1 x double> noundef {{.*}}[[B:%.*]])
+// LLVM: store <1 x double> [[B]], ptr [[A]], align 8
+// LLVM: ret void
+ vst1_f64(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_mf8(
+// CIR-LABEL: @test_vst1_mf8(
+void test_vst1_mf8(mfloat8_t *a, mfloat8x8_t val) {
+// CIR: cir.store align(1) {{.*}}, {{.*}} : !cir.vector<8 x !u8i>, !cir.ptr<!cir.vector<8 x !u8i>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <8 x i8> {{.*}}[[B:%.*]])
+// LLVM: store <8 x i8> [[B]], ptr [[A]], align 1
+// LLVM: ret void
+ vst1_mf8(a, val);
+}
+
+// LLVM-LABEL: @test_vst1_p16(
+// CIR-LABEL: @test_vst1_p16(
+void test_vst1_p16(poly16_t *a, poly16x4_t b) {
+// CIR: cir.store align(2) {{.*}}, {{.*}} : !cir.vector<4 x !s16i>, !cir.ptr<!cir.vector<4 x !s16i>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <4 x i16> noundef {{.*}}[[B:%.*]])
+// LLVM: store <4 x i16> [[B]], ptr [[A]], align 2
+// LLVM: ret void
+ vst1_p16(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_p64(
+// CIR-LABEL: @test_vst1_p64(
+void test_vst1_p64(poly64_t * ptr, poly64x1_t val) {
+// CIR: cir.store align(8) {{.*}}, {{.*}} : !cir.vector<1 x !s64i>, !cir.ptr<!cir.vector<1 x !s64i>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <1 x i64> noundef {{.*}}[[B:%.*]])
+// LLVM: store <1 x i64> [[B]], ptr [[A]], align 8
+// LLVM: ret void
+ return vst1_p64(ptr, val);
+}
+
+// LLVM-LABEL: @test_vst1_p8(
+// CIR-LABEL: @test_vst1_p8(
+void test_vst1_p8(poly8_t *a, poly8x8_t b) {
+// CIR: cir.store align(1) {{.*}}, {{.*}} : !cir.vector<8 x !s8i>, !cir.ptr<!cir.vector<8 x !s8i>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <8 x i8> noundef {{.*}}[[B:%.*]])
+// LLVM: store <8 x i8> [[B]], ptr [[A]], align 1
+// LLVM: ret void
+ vst1_p8(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_f16(
+// CIR-LABEL: @test_vst1q_f16(
+void test_vst1q_f16(float16_t *a, float16x8_t b) {
+// CIR: cir.store align(2) {{.*}}, {{.*}} : !cir.vector<8 x !cir.f16>, !cir.ptr<!cir.vector<8 x !cir.f16>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <8 x half> noundef {{.*}}[[B:%.*]])
+// LLVM: store <8 x half> [[B]], ptr [[A]], align 2
+// LLVM: ret void
+ vst1q_f16(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_f32(
+// CIR-LABEL: @test_vst1q_f32(
+void test_vst1q_f32(float32_t *a, float32x4_t b) {
+// CIR: cir.store align(4) {{.*}}, {{.*}} : !cir.vector<4 x !cir.float>, !cir.ptr<!cir.vector<4 x !cir.float>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <4 x float> noundef {{.*}}[[B:%.*]])
+// LLVM: store <4 x float> [[B]], ptr [[A]], align 4
+// LLVM: ret void
+ vst1q_f32(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_f64(
+// CIR-LABEL: @test_vst1q_f64(
+void test_vst1q_f64(float64_t *a, float64x2_t b) {
+// CIR: cir.store align(8) {{.*}}, {{.*}} : !cir.vector<2 x !cir.double>, !cir.ptr<!cir.vector<2 x !cir.double>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <2 x double> noundef {{.*}}[[B:%.*]])
+// LLVM: store <2 x double> [[B]], ptr [[A]], align 8
+// LLVM: ret void
+ vst1q_f64(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_mf8(
+// CIR-LABEL: @test_vst1q_mf8(
+void test_vst1q_mf8(mfloat8_t *a, mfloat8x16_t val) {
+// CIR: cir.store align(1) {{.*}}, {{.*}} : !cir.vector<16 x !u8i>, !cir.ptr<!cir.vector<16 x !u8i>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <16 x i8> {{.*}}[[B:%.*]])
+// LLVM: store <16 x i8> [[B]], ptr [[A]], align 1
+// LLVM: ret void
+ vst1q_mf8(a, val);
+}
+
+// LLVM-LABEL: @test_vst1q_p16(
+// CIR-LABEL: @test_vst1q_p16(
+void test_vst1q_p16(poly16_t *a, poly16x8_t b) {
+// CIR: cir.store align(2) {{.*}}, {{.*}} : !cir.vector<8 x !s16i>, !cir.ptr<!cir.vector<8 x !s16i>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <8 x i16> noundef {{.*}}[[B:%.*]])
+// LLVM: store <8 x i16> [[B]], ptr [[A]], align 2
+// LLVM: ret void
+ vst1q_p16(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_p64(
+// CIR-LABEL: @test_vst1q_p64(
+void test_vst1q_p64(poly64_t * ptr, poly64x2_t val) {
+// CIR: cir.store align(8) {{.*}}, {{.*}} : !cir.vector<2 x !s64i>, !cir.ptr<!cir.vector<2 x !s64i>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <2 x i64> noundef {{.*}}[[B:%.*]])
+// LLVM: store <2 x i64> [[B]], ptr [[A]], align 8
+// LLVM: ret void
+ return vst1q_p64(ptr, val);
+}
+
+// LLVM-LABEL: @test_vst1q_p8(
+// CIR-LABEL: @test_vst1q_p8(
+void test_vst1q_p8(poly8_t *a, poly8x16_t b) {
+// CIR: cir.store align(1) {{.*}}, {{.*}} : !cir.vector<16 x !s8i>, !cir.ptr<!cir.vector<16 x !s8i>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <16 x i8> noundef {{.*}}[[B:%.*]])
+// LLVM: store <16 x i8> [[B]], ptr [[A]], align 1
+// LLVM: ret void
+ vst1q_p8(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_s16(
+// CIR-LABEL: @test_vst1q_s16(
+void test_vst1q_s16(int16_t *a, int16x8_t b) {
+// CIR: cir.store align(2) {{.*}}, {{.*}} : !cir.vector<8 x !s16i>, !cir.ptr<!cir.vector<8 x !s16i>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <8 x i16> noundef {{.*}}[[B:%.*]])
+// LLVM: store <8 x i16> [[B]], ptr [[A]], align 2
+// LLVM: ret void
+ vst1q_s16(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_s32(
+// CIR-LABEL: @test_vst1q_s32(
+void test_vst1q_s32(int32_t *a, int32x4_t b) {
+// CIR: cir.store align(4) {{.*}}, {{.*}} : !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <4 x i32> noundef {{.*}}[[B:%.*]])
+// LLVM: store <4 x i32> [[B]], ptr [[A]], align 4
+// LLVM: ret void
+ vst1q_s32(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_s64(
+// CIR-LABEL: @test_vst1q_s64(
+void test_vst1q_s64(int64_t *a, int64x2_t b) {
+// CIR: cir.store align(8) {{.*}}, {{.*}} : !cir.vector<2 x !s64i>, !cir.ptr<!cir.vector<2 x !s64i>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <2 x i64> noundef {{.*}}[[B:%.*]])
+// LLVM: store <2 x i64> [[B]], ptr [[A]], align 8
+// LLVM: ret void
+ vst1q_s64(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_s8(
+// CIR-LABEL: @test_vst1q_s8(
+void test_vst1q_s8(int8_t *a, int8x16_t b) {
+// CIR: cir.store align(1) {{.*}}, {{.*}} : !cir.vector<16 x !s8i>, !cir.ptr<!cir.vector<16 x !s8i>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <16 x i8> noundef {{.*}}[[B:%.*]])
+// LLVM: store <16 x i8> [[B]], ptr [[A]], align 1
+// LLVM: ret void
+ vst1q_s8(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_u16(
+// CIR-LABEL: @test_vst1q_u16(
+void test_vst1q_u16(uint16_t *a, uint16x8_t b) {
+// CIR: cir.store align(2) {{.*}}, {{.*}} : !cir.vector<8 x !u16i>, !cir.ptr<!cir.vector<8 x !u16i>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <8 x i16> noundef {{.*}}[[B:%.*]])
+// LLVM: store <8 x i16> [[B]], ptr [[A]], align 2
+// LLVM: ret void
+ vst1q_u16(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_u32(
+// CIR-LABEL: @test_vst1q_u32(
+void test_vst1q_u32(uint32_t *a, uint32x4_t b) {
+// CIR: cir.store align(4) {{.*}}, {{.*}} : !cir.vector<4 x !u32i>, !cir.ptr<!cir.vector<4 x !u32i>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <4 x i32> noundef {{.*}}[[B:%.*]])
+// LLVM: store <4 x i32> [[B]], ptr [[A]], align 4
+// LLVM: ret void
+ vst1q_u32(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_u64(
+// CIR-LABEL: @test_vst1q_u64(
+void test_vst1q_u64(uint64_t *a, uint64x2_t b) {
+// CIR: cir.store align(8) {{.*}}, {{.*}} : !cir.vector<2 x !u64i>, !cir.ptr<!cir.vector<2 x !u64i>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <2 x i64> noundef {{.*}}[[B:%.*]])
+// LLVM: store <2 x i64> [[B]], ptr [[A]], align 8
+// LLVM: ret void
+ vst1q_u64(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_u8(
+// CIR-LABEL: @test_vst1q_u8(
+void test_vst1q_u8(uint8_t *a, uint8x16_t b) {
+// CIR: cir.store align(1) {{.*}}, {{.*}} : !cir.vector<16 x !u8i>, !cir.ptr<!cir.vector<16 x !u8i>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <16 x i8> noundef {{.*}}[[B:%.*]])
+// LLVM: store <16 x i8> [[B]], ptr [[A]], align 1
+// LLVM: ret void
+ vst1q_u8(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_s16(
+// CIR-LABEL: @test_vst1_s16(
+void test_vst1_s16(int16_t *a, int16x4_t b) {
+// CIR: cir.store align(2) {{.*}}, {{.*}} : !cir.vector<4 x !s16i>, !cir.ptr<!cir.vector<4 x !s16i>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <4 x i16> noundef {{.*}}[[B:%.*]])
+// LLVM: store <4 x i16> [[B]], ptr [[A]], align 2
+// LLVM: ret void
+ vst1_s16(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_s32(
+// CIR-LABEL: @test_vst1_s32(
+void test_vst1_s32(int32_t *a, int32x2_t b) {
+// CIR: cir.store align(4) {{.*}}, {{.*}} : !cir.vector<2 x !s32i>, !cir.ptr<!cir.vector<2 x !s32i>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <2 x i32> noundef {{.*}}[[B:%.*]])
+// LLVM: store <2 x i32> [[B]], ptr [[A]], align 4
+// LLVM: ret void
+ vst1_s32(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_s64(
+// CIR-LABEL: @test_vst1_s64(
+void test_vst1_s64(int64_t *a, int64x1_t b) {
+// CIR: cir.store align(8) {{.*}}, {{.*}} : !cir.vector<1 x !s64i>, !cir.ptr<!cir.vector<1 x !s64i>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <1 x i64> noundef {{.*}}[[B:%.*]])
+// LLVM: store <1 x i64> [[B]], ptr [[A]], align 8
+// LLVM: ret void
+ vst1_s64(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_s8(
+// CIR-LABEL: @test_vst1_s8(
+void test_vst1_s8(int8_t *a, int8x8_t b) {
+// CIR: cir.store align(1) {{.*}}, {{.*}} : !cir.vector<8 x !s8i>, !cir.ptr<!cir.vector<8 x !s8i>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <8 x i8> noundef {{.*}}[[B:%.*]])
+// LLVM: store <8 x i8> [[B]], ptr [[A]], align 1
+// LLVM: ret void
+ vst1_s8(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_u16(
+// CIR-LABEL: @test_vst1_u16(
+void test_vst1_u16(uint16_t *a, uint16x4_t b) {
+// CIR: cir.store align(2) {{.*}}, {{.*}} : !cir.vector<4 x !u16i>, !cir.ptr<!cir.vector<4 x !u16i>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <4 x i16> noundef {{.*}}[[B:%.*]])
+// LLVM: store <4 x i16> [[B]], ptr [[A]], align 2
+// LLVM: ret void
+ vst1_u16(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_u32(
+// CIR-LABEL: @test_vst1_u32(
+void test_vst1_u32(uint32_t *a, uint32x2_t b) {
+// CIR: cir.store align(4) {{.*}}, {{.*}} : !cir.vector<2 x !u32i>, !cir.ptr<!cir.vector<2 x !u32i>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <2 x i32> noundef {{.*}}[[B:%.*]])
+// LLVM: store <2 x i32> [[B]], ptr [[A]], align 4
+// LLVM: ret void
+ vst1_u32(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_u64(
+// CIR-LABEL: @test_vst1_u64(
+void test_vst1_u64(uint64_t *a, uint64x1_t b) {
+// CIR: cir.store align(8) {{.*}}, {{.*}} : !cir.vector<1 x !u64i>, !cir.ptr<!cir.vector<1 x !u64i>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <1 x i64> noundef {{.*}}[[B:%.*]])
+// LLVM: store <1 x i64> [[B]], ptr [[A]], align 8
+// LLVM: ret void
+ vst1_u64(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_u8(
+// CIR-LABEL: @test_vst1_u8(
+void test_vst1_u8(uint8_t *a, uint8x8_t b) {
+// CIR: cir.store align(1) {{.*}}, {{.*}} : !cir.vector<8 x !u8i>, !cir.ptr<!cir.vector<8 x !u8i>>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <8 x i8> noundef {{.*}}[[B:%.*]])
+// LLVM: store <8 x i8> [[B]], ptr [[A]], align 1
+// LLVM: ret void
+ vst1_u8(a, b);
+}
+
+//===------------------------------------------------------===//
+// Store single lane
+// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#store-single-lane
+//===------------------------------------------------------===//
+
+// LLVM-LABEL: @test_vst1_lane_f16(
+// CIR-LABEL: @test_vst1_lane_f16(
+void test_vst1_lane_f16(float16_t *a, float16x4_t b) {
+// CIR: {{.*}} = cir.vec.extract {{.*}}[{{.*}} : !u64i] : !cir.vector<4 x !cir.f16>
+// CIR: cir.store align(2) {{.*}}, {{.*}} : !cir.f16, !cir.ptr<!cir.f16>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <4 x half> noundef {{.*}}[[B:%.*]])
+// LLVM: [[TMP1:%.*]] = extractelement <4 x half> [[B]], i64 3
+// LLVM: store half [[TMP1]], ptr [[A]], align 2
+// LLVM: ret void
+ vst1_lane_f16(a, b, 3);
+}
+
+// LLVM-LABEL: @test_vst1_lane_f32(
+// CIR-LABEL: @test_vst1_lane_f32(
+void test_vst1_lane_f32(float32_t *a, float32x2_t b) {
+// CIR: {{.*}} = cir.vec.extract {{.*}}[{{.*}} : !u64i] : !cir.vector<2 x !cir.float>
+// CIR: cir.store align(4) {{.*}}, {{.*}} : !cir.float, !cir.ptr<!cir.float>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <2 x float> noundef {{.*}}[[B:%.*]])
+// LLVM: [[TMP1:%.*]] = extractelement <2 x float> [[B]], i64 1
+// LLVM: store float [[TMP1]], ptr [[A]], align 4
+// LLVM: ret void
+ vst1_lane_f32(a, b, 1);
+}
+
+// LLVM-LABEL: @test_vst1_lane_f64(
+// CIR-LABEL: @test_vst1_lane_f64(
+void test_vst1_lane_f64(float64_t *a, float64x1_t b) {
+// CIR: {{.*}} = cir.vec.extract {{.*}}[{{.*}} : !u64i] : !cir.vector<1 x !cir.double>
+// CIR: cir.store align(8) {{.*}}, {{.*}} : !cir.double, !cir.ptr<!cir.double>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <1 x double> noundef {{.*}}[[B:%.*]])
+// LLVM: [[TMP1:%.*]] = extractelement <1 x double> [[B]], i64 0
+// LLVM: store double [[TMP1]], ptr [[A]], align 8
+// LLVM: ret void
+ vst1_lane_f64(a, b, 0);
+}
+
+// LLVM-LABEL: @test_vst1_lane_mf8(
+// CIR-LABEL: @test_vst1_lane_mf8(
+void test_vst1_lane_mf8(mfloat8_t *a, mfloat8x8_t b) {
+// CIR: {{.*}} = cir.vec.extract {{.*}}[{{.*}} : !u64i] : !cir.vector<8 x !u8i>
+// CIR: cir.store align(1) {{.*}}, {{.*}} : !u8i, !cir.ptr<!u8i>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <8 x i8> {{.*}}[[B:%.*]])
+// LLVM: [[TMP1:%.*]] = extractelement <8 x i8> [[B]], i64 7
+// LLVM: store i8 [[TMP1]], ptr [[A]], align 1
+// LLVM: ret void
+ vst1_lane_mf8(a, b, 7);
+}
+
+// LLVM-LABEL: @test_vst1_lane_p16(
+// CIR-LABEL: @test_vst1_lane_p16(
+void test_vst1_lane_p16(poly16_t *a, poly16x4_t b) {
+// CIR: {{.*}} = cir.vec.extract {{.*}}[{{.*}} : !u64i] : !cir.vector<4 x !s16i>
+// CIR: cir.store align(2) {{.*}}, {{.*}} : !s16i, !cir.ptr<!s16i>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <4 x i16> noundef {{.*}}[[B:%.*]])
+// LLVM: [[TMP1:%.*]] = extractelement <4 x i16> [[B]], i64 3
+// LLVM: store i16 [[TMP1]], ptr [[A]], align 2
+// LLVM: ret void
+ vst1_lane_p16(a, b, 3);
+}
+
+// LLVM-LABEL: @test_vst1_lane_p64(
+// CIR-LABEL: @test_vst1_lane_p64(
+void test_vst1_lane_p64(poly64_t *a, poly64x1_t b) {
+// CIR: {{.*}} = cir.vec.extract {{.*}}[{{.*}} : !u64i] : !cir.vector<1 x !s64i>
+// CIR: cir.store align(8) {{.*}}, {{.*}} : !s64i, !cir.ptr<!s64i>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <1 x i64> noundef {{.*}}[[B:%.*]])
+// LLVM: [[TMP1:%.*]] = extractelement <1 x i64> [[B]], i64 0
+// LLVM: store i64 [[TMP1]], ptr [[A]], align 8
+// LLVM: ret void
+ vst1_lane_p64(a, b, 0);
+}
+
+// LLVM-LABEL: @test_vst1_lane_p8(
+// CIR-LABEL: @test_vst1_lane_p8(
+void test_vst1_lane_p8(poly8_t *a, poly8x8_t b) {
+// CIR: {{.*}} = cir.vec.extract {{.*}}[{{.*}} : !u64i] : !cir.vector<8 x !s8i>
+// CIR: cir.store align(1) {{.*}}, {{.*}} : !s8i, !cir.ptr<!s8i>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <8 x i8> noundef {{.*}}[[B:%.*]])
+// LLVM: [[TMP1:%.*]] = extractelement <8 x i8> [[B]], i64 7
+// LLVM: store i8 [[TMP1]], ptr [[A]], align 1
+// LLVM: ret void
+ vst1_lane_p8(a, b, 7);
+}
+
+// LLVM-LABEL: @test_vst1_lane_s16(
+// CIR-LABEL: @test_vst1_lane_s16(
+void test_vst1_lane_s16(int16_t *a, int16x4_t b) {
+// CIR: {{.*}} = cir.vec.extract {{.*}}[{{.*}} : !u64i] : !cir.vector<4 x !s16i>
+// CIR: cir.store align(2) {{.*}}, {{.*}} : !s16i, !cir.ptr<!s16i>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <4 x i16> noundef {{.*}}[[B:%.*]])
+// LLVM: [[TMP1:%.*]] = extractelement <4 x i16> [[B]], i64 3
+// LLVM: store i16 [[TMP1]], ptr [[A]], align 2
+// LLVM: ret void
+ vst1_lane_s16(a, b, 3);
+}
+
+// LLVM-LABEL: @test_vst1_lane_s32(
+// CIR-LABEL: @test_vst1_lane_s32(
+void test_vst1_lane_s32(int32_t *a, int32x2_t b) {
+// CIR: {{.*}} = cir.vec.extract {{.*}}[{{.*}} : !u64i] : !cir.vector<2 x !s32i>
+// CIR: cir.store align(4) {{.*}}, {{.*}} : !s32i, !cir.ptr<!s32i>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <2 x i32> noundef {{.*}}[[B:%.*]])
+// LLVM: [[TMP1:%.*]] = extractelement <2 x i32> [[B]], i64 1
+// LLVM: store i32 [[TMP1]], ptr [[A]], align 4
+// LLVM: ret void
+ vst1_lane_s32(a, b, 1);
+}
+
+// LLVM-LABEL: @test_vst1_lane_s64(
+// CIR-LABEL: @test_vst1_lane_s64(
+void test_vst1_lane_s64(int64_t *a, int64x1_t b) {
+// CIR: {{.*}} = cir.vec.extract {{.*}}[{{.*}} : !u64i] : !cir.vector<1 x !s64i>
+// CIR: cir.store align(8) {{.*}}, {{.*}} : !s64i, !cir.ptr<!s64i>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <1 x i64> noundef {{.*}}[[B:%.*]])
+// LLVM: [[TMP1:%.*]] = extractelement <1 x i64> [[B]], i64 0
+// LLVM: store i64 [[TMP1]], ptr [[A]], align 8
+// LLVM: ret void
+ vst1_lane_s64(a, b, 0);
+}
+
+// LLVM-LABEL: @test_vst1_lane_s8(
+// CIR-LABEL: @test_vst1_lane_s8(
+void test_vst1_lane_s8(int8_t *a, int8x8_t b) {
+// CIR: {{.*}} = cir.vec.extract {{.*}}[{{.*}} : !u64i] : !cir.vector<8 x !s8i>
+// CIR: cir.store align(1) {{.*}}, {{.*}} : !s8i, !cir.ptr<!s8i>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <8 x i8> noundef {{.*}}[[B:%.*]])
+// LLVM: [[TMP1:%.*]] = extractelement <8 x i8> [[B]], i64 7
+// LLVM: store i8 [[TMP1]], ptr [[A]], align 1
+// LLVM: ret void
+ vst1_lane_s8(a, b, 7);
+}
+
+// LLVM-LABEL: @test_vst1_lane_u16(
+// CIR-LABEL: @test_vst1_lane_u16(
+void test_vst1_lane_u16(uint16_t *a, uint16x4_t b) {
+// CIR: {{.*}} = cir.vec.extract {{.*}}[{{.*}} : !u64i] : !cir.vector<4 x !u16i>
+// CIR: cir.store align(2) {{.*}}, {{.*}} : !u16i, !cir.ptr<!u16i>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <4 x i16> noundef {{.*}}[[B:%.*]])
+// LLVM: [[TMP1:%.*]] = extractelement <4 x i16> [[B]], i64 3
+// LLVM: store i16 [[TMP1]], ptr [[A]], align 2
+// LLVM: ret void
+ vst1_lane_u16(a, b, 3);
+}
+
+// LLVM-LABEL: @test_vst1_lane_u32(
+// CIR-LABEL: @test_vst1_lane_u32(
+void test_vst1_lane_u32(uint32_t *a, uint32x2_t b) {
+// CIR: {{.*}} = cir.vec.extract {{.*}}[{{.*}} : !u64i] : !cir.vector<2 x !u32i>
+// CIR: cir.store align(4) {{.*}}, {{.*}} : !u32i, !cir.ptr<!u32i>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <2 x i32> noundef {{.*}}[[B:%.*]])
+// LLVM: [[TMP1:%.*]] = extractelement <2 x i32> [[B]], i64 1
+// LLVM: store i32 [[TMP1]], ptr [[A]], align 4
+// LLVM: ret void
+ vst1_lane_u32(a, b, 1);
+}
+
+// LLVM-LABEL: @test_vst1_lane_u64(
+// CIR-LABEL: @test_vst1_lane_u64(
+void test_vst1_lane_u64(uint64_t *a, uint64x1_t b) {
+// CIR: {{.*}} = cir.vec.extract {{.*}}[{{.*}} : !u64i] : !cir.vector<1 x !u64i>
+// CIR: cir.store align(8) {{.*}}, {{.*}} : !u64i, !cir.ptr<!u64i>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <1 x i64> noundef {{.*}}[[B:%.*]])
+// LLVM: [[TMP1:%.*]] = extractelement <1 x i64> [[B]], i64 0
+// LLVM: store i64 [[TMP1]], ptr [[A]], align 8
+// LLVM: ret void
+ vst1_lane_u64(a, b, 0);
+}
+
+// LLVM-LABEL: @test_vst1_lane_u8(
+// CIR-LABEL: @test_vst1_lane_u8(
+void test_vst1_lane_u8(uint8_t *a, uint8x8_t b) {
+// CIR: {{.*}} = cir.vec.extract {{.*}}[{{.*}} : !u64i] : !cir.vector<8 x !u8i>
+// CIR: cir.store align(1) {{.*}}, {{.*}} : !u8i, !cir.ptr<!u8i>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <8 x i8> noundef {{.*}}[[B:%.*]])
+// LLVM: [[TMP1:%.*]] = extractelement <8 x i8> [[B]], i64 7
+// LLVM: store i8 [[TMP1]], ptr [[A]], align 1
+// LLVM: ret void
+ vst1_lane_u8(a, b, 7);
+}
+
+// LLVM-LABEL: @test_vst1q_lane_f16(
+// CIR-LABEL: @test_vst1q_lane_f16(
+void test_vst1q_lane_f16(float16_t *a, float16x8_t b) {
+// CIR: {{.*}} = cir.vec.extract {{.*}}[{{.*}} : !u64i] : !cir.vector<8 x !cir.f16>
+// CIR: cir.store align(2) {{.*}}, {{.*}} : !cir.f16, !cir.ptr<!cir.f16>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <8 x half> noundef {{.*}}[[B:%.*]])
+// LLVM: [[TMP1:%.*]] = extractelement <8 x half> [[B]], i64 7
+// LLVM: store half [[TMP1]], ptr [[A]], align 2
+// LLVM: ret void
+ vst1q_lane_f16(a, b, 7);
+}
+
+// LLVM-LABEL: @test_vst1q_lane_f32(
+// CIR-LABEL: @test_vst1q_lane_f32(
+void test_vst1q_lane_f32(float32_t *a, float32x4_t b) {
+// CIR: {{.*}} = cir.vec.extract {{.*}}[{{.*}} : !u64i] : !cir.vector<4 x !cir.float>
+// CIR: cir.store align(4) {{.*}}, {{.*}} : !cir.float, !cir.ptr<!cir.float>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <4 x float> noundef {{.*}}[[B:%.*]])
+// LLVM: [[TMP1:%.*]] = extractelement <4 x float> [[B]], i64 3
+// LLVM: store float [[TMP1]], ptr [[A]], align 4
+// LLVM: ret void
+ vst1q_lane_f32(a, b, 3);
+}
+
+// LLVM-LABEL: @test_vst1q_lane_f64(
+// CIR-LABEL: @test_vst1q_lane_f64(
+void test_vst1q_lane_f64(float64_t *a, float64x2_t b) {
+// CIR: {{.*}} = cir.vec.extract {{.*}}[{{.*}} : !u64i] : !cir.vector<2 x !cir.double>
+// CIR: cir.store align(8) {{.*}}, {{.*}} : !cir.double, !cir.ptr<!cir.double>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <2 x double> noundef {{.*}}[[B:%.*]])
+// LLVM: [[TMP1:%.*]] = extractelement <2 x double> [[B]], i64 1
+// LLVM: store double [[TMP1]], ptr [[A]], align 8
+// LLVM: ret void
+ vst1q_lane_f64(a, b, 1);
+}
+
+// LLVM-LABEL: @test_vst1q_lane_mf8(
+// CIR-LABEL: @test_vst1q_lane_mf8(
+void test_vst1q_lane_mf8(mfloat8_t *a, mfloat8x16_t b) {
+// CIR: {{.*}} = cir.vec.extract {{.*}}[{{.*}} : !u64i] : !cir.vector<16 x !u8i>
+// CIR: cir.store align(1) {{.*}}, {{.*}} : !u8i, !cir.ptr<!u8i>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <16 x i8> {{.*}}[[B:%.*]])
+// LLVM: [[TMP1:%.*]] = extractelement <16 x i8> [[B]], i64 15
+// LLVM: store i8 [[TMP1]], ptr [[A]], align 1
+// LLVM: ret void
+ vst1q_lane_mf8(a, b, 15);
+}
+
+// LLVM-LABEL: @test_vst1q_lane_p16(
+// CIR-LABEL: @test_vst1q_lane_p16(
+void test_vst1q_lane_p16(poly16_t *a, poly16x8_t b) {
+// CIR: {{.*}} = cir.vec.extract {{.*}}[{{.*}} : !u64i] : !cir.vector<8 x !s16i>
+// CIR: cir.store align(2) {{.*}}, {{.*}} : !s16i, !cir.ptr<!s16i>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <8 x i16> noundef {{.*}}[[B:%.*]])
+// LLVM: [[TMP1:%.*]] = extractelement <8 x i16> [[B]], i64 7
+// LLVM: store i16 [[TMP1]], ptr [[A]], align 2
+// LLVM: ret void
+ vst1q_lane_p16(a, b, 7);
+}
+
+// LLVM-LABEL: @test_vst1q_lane_p64(
+// CIR-LABEL: @test_vst1q_lane_p64(
+void test_vst1q_lane_p64(poly64_t *a, poly64x2_t b) {
+// CIR: {{.*}} = cir.vec.extract {{.*}}[{{.*}} : !u64i] : !cir.vector<2 x !s64i>
+// CIR: cir.store align(8) {{.*}}, {{.*}} : !s64i, !cir.ptr<!s64i>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <2 x i64> noundef {{.*}}[[B:%.*]])
+// LLVM: [[TMP1:%.*]] = extractelement <2 x i64> [[B]], i64 1
+// LLVM: store i64 [[TMP1]], ptr [[A]], align 8
+// LLVM: ret void
+ vst1q_lane_p64(a, b, 1);
+}
+
+// LLVM-LABEL: @test_vst1q_lane_p8(
+// CIR-LABEL: @test_vst1q_lane_p8(
+void test_vst1q_lane_p8(poly8_t *a, poly8x16_t b) {
+// CIR: {{.*}} = cir.vec.extract {{.*}}[{{.*}} : !u64i] : !cir.vector<16 x !s8i>
+// CIR: cir.store align(1) {{.*}}, {{.*}} : !s8i, !cir.ptr<!s8i>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <16 x i8> noundef {{.*}}[[B:%.*]])
+// LLVM: [[TMP1:%.*]] = extractelement <16 x i8> [[B]], i64 15
+// LLVM: store i8 [[TMP1]], ptr [[A]], align 1
+// LLVM: ret void
+ vst1q_lane_p8(a, b, 15);
+}
+
+// LLVM-LABEL: @test_vst1q_lane_s16(
+// CIR-LABEL: @test_vst1q_lane_s16(
+void test_vst1q_lane_s16(int16_t *a, int16x8_t b) {
+// CIR: {{.*}} = cir.vec.extract {{.*}}[{{.*}} : !u64i] : !cir.vector<8 x !s16i>
+// CIR: cir.store align(2) {{.*}}, {{.*}} : !s16i, !cir.ptr<!s16i>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <8 x i16> noundef {{.*}}[[B:%.*]])
+// LLVM: [[TMP1:%.*]] = extractelement <8 x i16> [[B]], i64 7
+// LLVM: store i16 [[TMP1]], ptr [[A]], align 2
+// LLVM: ret void
+ vst1q_lane_s16(a, b, 7);
+}
+
+// LLVM-LABEL: @test_vst1q_lane_s32(
+// CIR-LABEL: @test_vst1q_lane_s32(
+void test_vst1q_lane_s32(int32_t *a, int32x4_t b) {
+// CIR: {{.*}} = cir.vec.extract {{.*}}[{{.*}} : !u64i] : !cir.vector<4 x !s32i>
+// CIR: cir.store align(4) {{.*}}, {{.*}} : !s32i, !cir.ptr<!s32i>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <4 x i32> noundef {{.*}}[[B:%.*]])
+// LLVM: [[TMP1:%.*]] = extractelement <4 x i32> [[B]], i64 3
+// LLVM: store i32 [[TMP1]], ptr [[A]], align 4
+// LLVM: ret void
+ vst1q_lane_s32(a, b, 3);
+}
+
+// LLVM-LABEL: @test_vst1q_lane_s64(
+// CIR-LABEL: @test_vst1q_lane_s64(
+void test_vst1q_lane_s64(int64_t *a, int64x2_t b) {
+// CIR: {{.*}} = cir.vec.extract {{.*}}[{{.*}} : !u64i] : !cir.vector<2 x !s64i>
+// CIR: cir.store align(8) {{.*}}, {{.*}} : !s64i, !cir.ptr<!s64i>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <2 x i64> noundef {{.*}}[[B:%.*]])
+// LLVM: [[TMP1:%.*]] = extractelement <2 x i64> [[B]], i64 1
+// LLVM: store i64 [[TMP1]], ptr [[A]], align 8
+// LLVM: ret void
+ vst1q_lane_s64(a, b, 1);
+}
+
+// LLVM-LABEL: @test_vst1q_lane_s8(
+// CIR-LABEL: @test_vst1q_lane_s8(
+void test_vst1q_lane_s8(int8_t *a, int8x16_t b) {
+// CIR: {{.*}} = cir.vec.extract {{.*}}[{{.*}} : !u64i] : !cir.vector<16 x !s8i>
+// CIR: cir.store align(1) {{.*}}, {{.*}} : !s8i, !cir.ptr<!s8i>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <16 x i8> noundef {{.*}}[[B:%.*]])
+// LLVM: [[TMP1:%.*]] = extractelement <16 x i8> [[B]], i64 15
+// LLVM: store i8 [[TMP1]], ptr [[A]], align 1
+// LLVM: ret void
+ vst1q_lane_s8(a, b, 15);
+}
+
+// LLVM-LABEL: @test_vst1q_lane_u16(
+// CIR-LABEL: @test_vst1q_lane_u16(
+void test_vst1q_lane_u16(uint16_t *a, uint16x8_t b) {
+// CIR: {{.*}} = cir.vec.extract {{.*}}[{{.*}} : !u64i] : !cir.vector<8 x !u16i>
+// CIR: cir.store align(2) {{.*}}, {{.*}} : !u16i, !cir.ptr<!u16i>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <8 x i16> noundef {{.*}}[[B:%.*]])
+// LLVM: [[TMP1:%.*]] = extractelement <8 x i16> [[B]], i64 7
+// LLVM: store i16 [[TMP1]], ptr [[A]], align 2
+// LLVM: ret void
+ vst1q_lane_u16(a, b, 7);
+}
+
+// LLVM-LABEL: @test_vst1q_lane_u32(
+// CIR-LABEL: @test_vst1q_lane_u32(
+void test_vst1q_lane_u32(uint32_t *a, uint32x4_t b) {
+// CIR: {{.*}} = cir.vec.extract {{.*}}[{{.*}} : !u64i] : !cir.vector<4 x !u32i>
+// CIR: cir.store align(4) {{.*}}, {{.*}} : !u32i, !cir.ptr<!u32i>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <4 x i32> noundef {{.*}}[[B:%.*]])
+// LLVM: [[TMP1:%.*]] = extractelement <4 x i32> [[B]], i64 3
+// LLVM: store i32 [[TMP1]], ptr [[A]], align 4
+// LLVM: ret void
+ vst1q_lane_u32(a, b, 3);
+}
+
+// LLVM-LABEL: @test_vst1q_lane_u64(
+// CIR-LABEL: @test_vst1q_lane_u64(
+void test_vst1q_lane_u64(uint64_t *a, uint64x2_t b) {
+// CIR: {{.*}} = cir.vec.extract {{.*}}[{{.*}} : !u64i] : !cir.vector<2 x !u64i>
+// CIR: cir.store align(8) {{.*}}, {{.*}} : !u64i, !cir.ptr<!u64i>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <2 x i64> noundef {{.*}}[[B:%.*]])
+// LLVM: [[TMP1:%.*]] = extractelement <2 x i64> [[B]], i64 1
+// LLVM: store i64 [[TMP1]], ptr [[A]], align 8
+// LLVM: ret void
+ vst1q_lane_u64(a, b, 1);
+}
+
+// LLVM-LABEL: @test_vst1q_lane_u8(
+// CIR-LABEL: @test_vst1q_lane_u8(
+void test_vst1q_lane_u8(uint8_t *a, uint8x16_t b) {
+// CIR: {{.*}} = cir.vec.extract {{.*}}[{{.*}} : !u64i] : !cir.vector<16 x !u8i>
+// CIR: cir.store align(1) {{.*}}, {{.*}} : !u8i, !cir.ptr<!u8i>
+
+// LLVM-SAME: ptr noundef {{.*}}[[A:%.*]], <16 x i8> noundef {{.*}}[[B:%.*]])
+// LLVM: [[TMP1:%.*]] = extractelement <16 x i8> [[B]], i64 15
+// LLVM: store i8 [[TMP1]], ptr [[A]], align 1
+// LLVM: ret void
+ vst1q_lane_u8(a, b, 15);
+}
+
+//===------------------------------------------------------===//
+// Store multiple single-element structures
+// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#store-multiple-single-element-structures
+//===------------------------------------------------------===//
+
+// LLVM-LABEL: @test_vst1_f16_x2(
+// CIR-LABEL: @test_vst1_f16_x2(
+void test_vst1_f16_x2(float16_t *a, float16x4x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x2" {{.*}} : (!cir.vector<4 x !cir.f16>, !cir.vector<4 x !cir.f16>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x2.v4f16.p0(<4 x half> {{.*}}, <4 x half> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_f16_x2(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_f16_x3(
+// CIR-LABEL: @test_vst1_f16_x3(
+void test_vst1_f16_x3(float16_t *a, float16x4x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x3" {{.*}} : (!cir.vector<4 x !cir.f16>, !cir.vector<4 x !cir.f16>, !cir.vector<4 x !cir.f16>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x3.v4f16.p0(<4 x half> {{.*}}, <4 x half> {{.*}}, <4 x half> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_f16_x3(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_f16_x4(
+// CIR-LABEL: @test_vst1_f16_x4(
+void test_vst1_f16_x4(float16_t *a, float16x4x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x4" {{.*}} : (!cir.vector<4 x !cir.f16>, !cir.vector<4 x !cir.f16>, !cir.vector<4 x !cir.f16>, !cir.vector<4 x !cir.f16>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x4.v4f16.p0(<4 x half> {{.*}}, <4 x half> {{.*}}, <4 x half> {{.*}}, <4 x half> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_f16_x4(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_f32_x2(
+// CIR-LABEL: @test_vst1_f32_x2(
+void test_vst1_f32_x2(float32_t *a, float32x2x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x2" {{.*}} : (!cir.vector<2 x !cir.float>, !cir.vector<2 x !cir.float>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x2.v2f32.p0(<2 x float> {{.*}}, <2 x float> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_f32_x2(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_f32_x3(
+// CIR-LABEL: @test_vst1_f32_x3(
+void test_vst1_f32_x3(float32_t *a, float32x2x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x3" {{.*}} : (!cir.vector<2 x !cir.float>, !cir.vector<2 x !cir.float>, !cir.vector<2 x !cir.float>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x3.v2f32.p0(<2 x float> {{.*}}, <2 x float> {{.*}}, <2 x float> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_f32_x3(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_f32_x4(
+// CIR-LABEL: @test_vst1_f32_x4(
+void test_vst1_f32_x4(float32_t *a, float32x2x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x4" {{.*}} : (!cir.vector<2 x !cir.float>, !cir.vector<2 x !cir.float>, !cir.vector<2 x !cir.float>, !cir.vector<2 x !cir.float>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x4.v2f32.p0(<2 x float> {{.*}}, <2 x float> {{.*}}, <2 x float> {{.*}}, <2 x float> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_f32_x4(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_f64_x2(
+// CIR-LABEL: @test_vst1_f64_x2(
+void test_vst1_f64_x2(float64_t *a, float64x1x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x2" {{.*}} : (!cir.vector<1 x !cir.double>, !cir.vector<1 x !cir.double>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x2.v1f64.p0(<1 x double> {{.*}}, <1 x double> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_f64_x2(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_f64_x3(
+// CIR-LABEL: @test_vst1_f64_x3(
+void test_vst1_f64_x3(float64_t *a, float64x1x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x3" {{.*}} : (!cir.vector<1 x !cir.double>, !cir.vector<1 x !cir.double>, !cir.vector<1 x !cir.double>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x3.v1f64.p0(<1 x double> {{.*}}, <1 x double> {{.*}}, <1 x double> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_f64_x3(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_f64_x4(
+// CIR-LABEL: @test_vst1_f64_x4(
+void test_vst1_f64_x4(float64_t *a, float64x1x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x4" {{.*}} : (!cir.vector<1 x !cir.double>, !cir.vector<1 x !cir.double>, !cir.vector<1 x !cir.double>, !cir.vector<1 x !cir.double>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x4.v1f64.p0(<1 x double> {{.*}}, <1 x double> {{.*}}, <1 x double> {{.*}}, <1 x double> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_f64_x4(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_mf8_x2(
+// CIR-LABEL: @test_vst1_mf8_x2(
+void test_vst1_mf8_x2(mfloat8_t *a, mfloat8x8x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x2" {{.*}} : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x2.v8i8.p0(<8 x i8> {{.*}}, <8 x i8> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_mf8_x2(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_mf8_x3(
+// CIR-LABEL: @test_vst1_mf8_x3(
+void test_vst1_mf8_x3(mfloat8_t *a, mfloat8x8x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x3" {{.*}} : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x3.v8i8.p0(<8 x i8> {{.*}}, <8 x i8> {{.*}}, <8 x i8> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_mf8_x3(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_mf8_x4(
+// CIR-LABEL: @test_vst1_mf8_x4(
+void test_vst1_mf8_x4(mfloat8_t *a, mfloat8x8x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x4" {{.*}} : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x4.v8i8.p0(<8 x i8> {{.*}}, <8 x i8> {{.*}}, <8 x i8> {{.*}}, <8 x i8> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_mf8_x4(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_p16_x2(
+// CIR-LABEL: @test_vst1_p16_x2(
+void test_vst1_p16_x2(poly16_t *a, poly16x4x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x2" {{.*}} : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x2.v4i16.p0(<4 x i16> {{.*}}, <4 x i16> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_p16_x2(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_p16_x3(
+// CIR-LABEL: @test_vst1_p16_x3(
+void test_vst1_p16_x3(poly16_t *a, poly16x4x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x3" {{.*}} : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x3.v4i16.p0(<4 x i16> {{.*}}, <4 x i16> {{.*}}, <4 x i16> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_p16_x3(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_p16_x4(
+// CIR-LABEL: @test_vst1_p16_x4(
+void test_vst1_p16_x4(poly16_t *a, poly16x4x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x4" {{.*}} : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x4.v4i16.p0(<4 x i16> {{.*}}, <4 x i16> {{.*}}, <4 x i16> {{.*}}, <4 x i16> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_p16_x4(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_p64_x2(
+// CIR-LABEL: @test_vst1_p64_x2(
+void test_vst1_p64_x2(poly64_t *a, poly64x1x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x2" {{.*}} : (!cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x2.v1i64.p0(<1 x i64> {{.*}}, <1 x i64> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_p64_x2(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_p64_x3(
+// CIR-LABEL: @test_vst1_p64_x3(
+void test_vst1_p64_x3(poly64_t *a, poly64x1x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x3" {{.*}} : (!cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x3.v1i64.p0(<1 x i64> {{.*}}, <1 x i64> {{.*}}, <1 x i64> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_p64_x3(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_p64_x4(
+// CIR-LABEL: @test_vst1_p64_x4(
+void test_vst1_p64_x4(poly64_t *a, poly64x1x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x4" {{.*}} : (!cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x4.v1i64.p0(<1 x i64> {{.*}}, <1 x i64> {{.*}}, <1 x i64> {{.*}}, <1 x i64> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_p64_x4(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_p8_x2(
+// CIR-LABEL: @test_vst1_p8_x2(
+void test_vst1_p8_x2(poly8_t *a, poly8x8x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x2" {{.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x2.v8i8.p0(<8 x i8> {{.*}}, <8 x i8> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_p8_x2(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_p8_x3(
+// CIR-LABEL: @test_vst1_p8_x3(
+void test_vst1_p8_x3(poly8_t *a, poly8x8x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x3" {{.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x3.v8i8.p0(<8 x i8> {{.*}}, <8 x i8> {{.*}}, <8 x i8> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_p8_x3(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_p8_x4(
+// CIR-LABEL: @test_vst1_p8_x4(
+void test_vst1_p8_x4(poly8_t *a, poly8x8x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x4" {{.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x4.v8i8.p0(<8 x i8> {{.*}}, <8 x i8> {{.*}}, <8 x i8> {{.*}}, <8 x i8> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_p8_x4(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_f16_x2(
+// CIR-LABEL: @test_vst1q_f16_x2(
+void test_vst1q_f16_x2(float16_t *a, float16x8x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x2" {{.*}} : (!cir.vector<8 x !cir.f16>, !cir.vector<8 x !cir.f16>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x2.v8f16.p0(<8 x half> {{.*}}, <8 x half> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_f16_x2(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_f16_x3(
+// CIR-LABEL: @test_vst1q_f16_x3(
+void test_vst1q_f16_x3(float16_t *a, float16x8x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x3" {{.*}} : (!cir.vector<8 x !cir.f16>, !cir.vector<8 x !cir.f16>, !cir.vector<8 x !cir.f16>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x3.v8f16.p0(<8 x half> {{.*}}, <8 x half> {{.*}}, <8 x half> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_f16_x3(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_f16_x4(
+// CIR-LABEL: @test_vst1q_f16_x4(
+void test_vst1q_f16_x4(float16_t *a, float16x8x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x4" {{.*}} : (!cir.vector<8 x !cir.f16>, !cir.vector<8 x !cir.f16>, !cir.vector<8 x !cir.f16>, !cir.vector<8 x !cir.f16>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x4.v8f16.p0(<8 x half> {{.*}}, <8 x half> {{.*}}, <8 x half> {{.*}}, <8 x half> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_f16_x4(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_f32_x2(
+// CIR-LABEL: @test_vst1q_f32_x2(
+void test_vst1q_f32_x2(float32_t *a, float32x4x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x2" {{.*}} : (!cir.vector<4 x !cir.float>, !cir.vector<4 x !cir.float>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x2.v4f32.p0(<4 x float> {{.*}}, <4 x float> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_f32_x2(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_f32_x3(
+// CIR-LABEL: @test_vst1q_f32_x3(
+void test_vst1q_f32_x3(float32_t *a, float32x4x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x3" {{.*}} : (!cir.vector<4 x !cir.float>, !cir.vector<4 x !cir.float>, !cir.vector<4 x !cir.float>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x3.v4f32.p0(<4 x float> {{.*}}, <4 x float> {{.*}}, <4 x float> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_f32_x3(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_f32_x4(
+// CIR-LABEL: @test_vst1q_f32_x4(
+void test_vst1q_f32_x4(float32_t *a, float32x4x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x4" {{.*}} : (!cir.vector<4 x !cir.float>, !cir.vector<4 x !cir.float>, !cir.vector<4 x !cir.float>, !cir.vector<4 x !cir.float>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x4.v4f32.p0(<4 x float> {{.*}}, <4 x float> {{.*}}, <4 x float> {{.*}}, <4 x float> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_f32_x4(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_f64_x2(
+// CIR-LABEL: @test_vst1q_f64_x2(
+void test_vst1q_f64_x2(float64_t *a, float64x2x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x2" {{.*}} : (!cir.vector<2 x !cir.double>, !cir.vector<2 x !cir.double>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x2.v2f64.p0(<2 x double> {{.*}}, <2 x double> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_f64_x2(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_f64_x3(
+// CIR-LABEL: @test_vst1q_f64_x3(
+void test_vst1q_f64_x3(float64_t *a, float64x2x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x3" {{.*}} : (!cir.vector<2 x !cir.double>, !cir.vector<2 x !cir.double>, !cir.vector<2 x !cir.double>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x3.v2f64.p0(<2 x double> {{.*}}, <2 x double> {{.*}}, <2 x double> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_f64_x3(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_f64_x4(
+// CIR-LABEL: @test_vst1q_f64_x4(
+void test_vst1q_f64_x4(float64_t *a, float64x2x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x4" {{.*}} : (!cir.vector<2 x !cir.double>, !cir.vector<2 x !cir.double>, !cir.vector<2 x !cir.double>, !cir.vector<2 x !cir.double>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x4.v2f64.p0(<2 x double> {{.*}}, <2 x double> {{.*}}, <2 x double> {{.*}}, <2 x double> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_f64_x4(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_mf8_x2(
+// CIR-LABEL: @test_vst1q_mf8_x2(
+void test_vst1q_mf8_x2(mfloat8_t *a, mfloat8x16x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x2" {{.*}} : (!cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x2.v16i8.p0(<16 x i8> {{.*}}, <16 x i8> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_mf8_x2(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_mf8_x3(
+// CIR-LABEL: @test_vst1q_mf8_x3(
+void test_vst1q_mf8_x3(mfloat8_t *a, mfloat8x16x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x3" {{.*}} : (!cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x3.v16i8.p0(<16 x i8> {{.*}}, <16 x i8> {{.*}}, <16 x i8> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_mf8_x3(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_mf8_x4(
+// CIR-LABEL: @test_vst1q_mf8_x4(
+void test_vst1q_mf8_x4(mfloat8_t *a, mfloat8x16x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x4" {{.*}} : (!cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x4.v16i8.p0(<16 x i8> {{.*}}, <16 x i8> {{.*}}, <16 x i8> {{.*}}, <16 x i8> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_mf8_x4(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_p16_x2(
+// CIR-LABEL: @test_vst1q_p16_x2(
+void test_vst1q_p16_x2(poly16_t *a, poly16x8x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x2" {{.*}} : (!cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x2.v8i16.p0(<8 x i16> {{.*}}, <8 x i16> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_p16_x2(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_p16_x3(
+// CIR-LABEL: @test_vst1q_p16_x3(
+void test_vst1q_p16_x3(poly16_t *a, poly16x8x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x3" {{.*}} : (!cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x3.v8i16.p0(<8 x i16> {{.*}}, <8 x i16> {{.*}}, <8 x i16> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_p16_x3(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_p16_x4(
+// CIR-LABEL: @test_vst1q_p16_x4(
+void test_vst1q_p16_x4(poly16_t *a, poly16x8x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x4" {{.*}} : (!cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x4.v8i16.p0(<8 x i16> {{.*}}, <8 x i16> {{.*}}, <8 x i16> {{.*}}, <8 x i16> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_p16_x4(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_p64_x2(
+// CIR-LABEL: @test_vst1q_p64_x2(
+void test_vst1q_p64_x2(poly64_t *a, poly64x2x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x2" {{.*}} : (!cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x2.v2i64.p0(<2 x i64> {{.*}}, <2 x i64> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_p64_x2(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_p64_x3(
+// CIR-LABEL: @test_vst1q_p64_x3(
+void test_vst1q_p64_x3(poly64_t *a, poly64x2x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x3" {{.*}} : (!cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x3.v2i64.p0(<2 x i64> {{.*}}, <2 x i64> {{.*}}, <2 x i64> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_p64_x3(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_p64_x4(
+// CIR-LABEL: @test_vst1q_p64_x4(
+void test_vst1q_p64_x4(poly64_t *a, poly64x2x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x4" {{.*}} : (!cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x4.v2i64.p0(<2 x i64> {{.*}}, <2 x i64> {{.*}}, <2 x i64> {{.*}}, <2 x i64> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_p64_x4(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_p8_x2(
+// CIR-LABEL: @test_vst1q_p8_x2(
+void test_vst1q_p8_x2(poly8_t *a, poly8x16x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x2" {{.*}} : (!cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x2.v16i8.p0(<16 x i8> {{.*}}, <16 x i8> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_p8_x2(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_p8_x3(
+// CIR-LABEL: @test_vst1q_p8_x3(
+void test_vst1q_p8_x3(poly8_t *a, poly8x16x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x3" {{.*}} : (!cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x3.v16i8.p0(<16 x i8> {{.*}}, <16 x i8> {{.*}}, <16 x i8> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_p8_x3(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_p8_x4(
+// CIR-LABEL: @test_vst1q_p8_x4(
+void test_vst1q_p8_x4(poly8_t *a, poly8x16x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x4" {{.*}} : (!cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x4.v16i8.p0(<16 x i8> {{.*}}, <16 x i8> {{.*}}, <16 x i8> {{.*}}, <16 x i8> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_p8_x4(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_s16_x2(
+// CIR-LABEL: @test_vst1q_s16_x2(
+void test_vst1q_s16_x2(int16_t *a, int16x8x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x2" {{.*}} : (!cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x2.v8i16.p0(<8 x i16> {{.*}}, <8 x i16> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_s16_x2(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_s16_x3(
+// CIR-LABEL: @test_vst1q_s16_x3(
+void test_vst1q_s16_x3(int16_t *a, int16x8x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x3" {{.*}} : (!cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x3.v8i16.p0(<8 x i16> {{.*}}, <8 x i16> {{.*}}, <8 x i16> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_s16_x3(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_s16_x4(
+// CIR-LABEL: @test_vst1q_s16_x4(
+void test_vst1q_s16_x4(int16_t *a, int16x8x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x4" {{.*}} : (!cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x4.v8i16.p0(<8 x i16> {{.*}}, <8 x i16> {{.*}}, <8 x i16> {{.*}}, <8 x i16> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_s16_x4(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_s32_x2(
+// CIR-LABEL: @test_vst1q_s32_x2(
+void test_vst1q_s32_x2(int32_t *a, int32x4x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x2" {{.*}} : (!cir.vector<4 x !s32i>, !cir.vector<4 x !s32i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x2.v4i32.p0(<4 x i32> {{.*}}, <4 x i32> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_s32_x2(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_s32_x3(
+// CIR-LABEL: @test_vst1q_s32_x3(
+void test_vst1q_s32_x3(int32_t *a, int32x4x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x3" {{.*}} : (!cir.vector<4 x !s32i>, !cir.vector<4 x !s32i>, !cir.vector<4 x !s32i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x3.v4i32.p0(<4 x i32> {{.*}}, <4 x i32> {{.*}}, <4 x i32> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_s32_x3(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_s32_x4(
+// CIR-LABEL: @test_vst1q_s32_x4(
+void test_vst1q_s32_x4(int32_t *a, int32x4x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x4" {{.*}} : (!cir.vector<4 x !s32i>, !cir.vector<4 x !s32i>, !cir.vector<4 x !s32i>, !cir.vector<4 x !s32i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x4.v4i32.p0(<4 x i32> {{.*}}, <4 x i32> {{.*}}, <4 x i32> {{.*}}, <4 x i32> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_s32_x4(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_s64_x2(
+// CIR-LABEL: @test_vst1q_s64_x2(
+void test_vst1q_s64_x2(int64_t *a, int64x2x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x2" {{.*}} : (!cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x2.v2i64.p0(<2 x i64> {{.*}}, <2 x i64> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_s64_x2(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_s64_x3(
+// CIR-LABEL: @test_vst1q_s64_x3(
+void test_vst1q_s64_x3(int64_t *a, int64x2x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x3" {{.*}} : (!cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x3.v2i64.p0(<2 x i64> {{.*}}, <2 x i64> {{.*}}, <2 x i64> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_s64_x3(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_s64_x4(
+// CIR-LABEL: @test_vst1q_s64_x4(
+void test_vst1q_s64_x4(int64_t *a, int64x2x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x4" {{.*}} : (!cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x4.v2i64.p0(<2 x i64> {{.*}}, <2 x i64> {{.*}}, <2 x i64> {{.*}}, <2 x i64> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_s64_x4(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_s8_x2(
+// CIR-LABEL: @test_vst1q_s8_x2(
+void test_vst1q_s8_x2(int8_t *a, int8x16x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x2" {{.*}} : (!cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x2.v16i8.p0(<16 x i8> {{.*}}, <16 x i8> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_s8_x2(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_s8_x3(
+// CIR-LABEL: @test_vst1q_s8_x3(
+void test_vst1q_s8_x3(int8_t *a, int8x16x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x3" {{.*}} : (!cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x3.v16i8.p0(<16 x i8> {{.*}}, <16 x i8> {{.*}}, <16 x i8> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_s8_x3(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_s8_x4(
+// CIR-LABEL: @test_vst1q_s8_x4(
+void test_vst1q_s8_x4(int8_t *a, int8x16x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x4" {{.*}} : (!cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x4.v16i8.p0(<16 x i8> {{.*}}, <16 x i8> {{.*}}, <16 x i8> {{.*}}, <16 x i8> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_s8_x4(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_u16_x2(
+// CIR-LABEL: @test_vst1q_u16_x2(
+void test_vst1q_u16_x2(uint16_t *a, uint16x8x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x2" {{.*}} : (!cir.vector<8 x !u16i>, !cir.vector<8 x !u16i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x2.v8i16.p0(<8 x i16> {{.*}}, <8 x i16> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_u16_x2(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_u16_x3(
+// CIR-LABEL: @test_vst1q_u16_x3(
+void test_vst1q_u16_x3(uint16_t *a, uint16x8x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x3" {{.*}} : (!cir.vector<8 x !u16i>, !cir.vector<8 x !u16i>, !cir.vector<8 x !u16i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x3.v8i16.p0(<8 x i16> {{.*}}, <8 x i16> {{.*}}, <8 x i16> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_u16_x3(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_u16_x4(
+// CIR-LABEL: @test_vst1q_u16_x4(
+void test_vst1q_u16_x4(uint16_t *a, uint16x8x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x4" {{.*}} : (!cir.vector<8 x !u16i>, !cir.vector<8 x !u16i>, !cir.vector<8 x !u16i>, !cir.vector<8 x !u16i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x4.v8i16.p0(<8 x i16> {{.*}}, <8 x i16> {{.*}}, <8 x i16> {{.*}}, <8 x i16> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_u16_x4(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_u32_x2(
+// CIR-LABEL: @test_vst1q_u32_x2(
+void test_vst1q_u32_x2(uint32_t *a, uint32x4x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x2" {{.*}} : (!cir.vector<4 x !u32i>, !cir.vector<4 x !u32i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x2.v4i32.p0(<4 x i32> {{.*}}, <4 x i32> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_u32_x2(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_u32_x3(
+// CIR-LABEL: @test_vst1q_u32_x3(
+void test_vst1q_u32_x3(uint32_t *a, uint32x4x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x3" {{.*}} : (!cir.vector<4 x !u32i>, !cir.vector<4 x !u32i>, !cir.vector<4 x !u32i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x3.v4i32.p0(<4 x i32> {{.*}}, <4 x i32> {{.*}}, <4 x i32> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_u32_x3(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_u32_x4(
+// CIR-LABEL: @test_vst1q_u32_x4(
+void test_vst1q_u32_x4(uint32_t *a, uint32x4x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x4" {{.*}} : (!cir.vector<4 x !u32i>, !cir.vector<4 x !u32i>, !cir.vector<4 x !u32i>, !cir.vector<4 x !u32i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x4.v4i32.p0(<4 x i32> {{.*}}, <4 x i32> {{.*}}, <4 x i32> {{.*}}, <4 x i32> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_u32_x4(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_u64_x2(
+// CIR-LABEL: @test_vst1q_u64_x2(
+void test_vst1q_u64_x2(uint64_t *a, uint64x2x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x2" {{.*}} : (!cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x2.v2i64.p0(<2 x i64> {{.*}}, <2 x i64> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_u64_x2(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_u64_x3(
+// CIR-LABEL: @test_vst1q_u64_x3(
+void test_vst1q_u64_x3(uint64_t *a, uint64x2x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x3" {{.*}} : (!cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x3.v2i64.p0(<2 x i64> {{.*}}, <2 x i64> {{.*}}, <2 x i64> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_u64_x3(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_u64_x4(
+// CIR-LABEL: @test_vst1q_u64_x4(
+void test_vst1q_u64_x4(uint64_t *a, uint64x2x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x4" {{.*}} : (!cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x4.v2i64.p0(<2 x i64> {{.*}}, <2 x i64> {{.*}}, <2 x i64> {{.*}}, <2 x i64> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_u64_x4(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_u8_x2(
+// CIR-LABEL: @test_vst1q_u8_x2(
+void test_vst1q_u8_x2(uint8_t *a, uint8x16x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x2" {{.*}} : (!cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x2.v16i8.p0(<16 x i8> {{.*}}, <16 x i8> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_u8_x2(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_u8_x3(
+// CIR-LABEL: @test_vst1q_u8_x3(
+void test_vst1q_u8_x3(uint8_t *a, uint8x16x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x3" {{.*}} : (!cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x3.v16i8.p0(<16 x i8> {{.*}}, <16 x i8> {{.*}}, <16 x i8> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_u8_x3(a, b);
+}
+
+// LLVM-LABEL: @test_vst1q_u8_x4(
+// CIR-LABEL: @test_vst1q_u8_x4(
+void test_vst1q_u8_x4(uint8_t *a, uint8x16x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x4" {{.*}} : (!cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x4.v16i8.p0(<16 x i8> {{.*}}, <16 x i8> {{.*}}, <16 x i8> {{.*}}, <16 x i8> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1q_u8_x4(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_s16_x2(
+// CIR-LABEL: @test_vst1_s16_x2(
+void test_vst1_s16_x2(int16_t *a, int16x4x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x2" {{.*}} : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x2.v4i16.p0(<4 x i16> {{.*}}, <4 x i16> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_s16_x2(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_s16_x3(
+// CIR-LABEL: @test_vst1_s16_x3(
+void test_vst1_s16_x3(int16_t *a, int16x4x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x3" {{.*}} : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x3.v4i16.p0(<4 x i16> {{.*}}, <4 x i16> {{.*}}, <4 x i16> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_s16_x3(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_s16_x4(
+// CIR-LABEL: @test_vst1_s16_x4(
+void test_vst1_s16_x4(int16_t *a, int16x4x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x4" {{.*}} : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x4.v4i16.p0(<4 x i16> {{.*}}, <4 x i16> {{.*}}, <4 x i16> {{.*}}, <4 x i16> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_s16_x4(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_s32_x2(
+// CIR-LABEL: @test_vst1_s32_x2(
+void test_vst1_s32_x2(int32_t *a, int32x2x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x2" {{.*}} : (!cir.vector<2 x !s32i>, !cir.vector<2 x !s32i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x2.v2i32.p0(<2 x i32> {{.*}}, <2 x i32> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_s32_x2(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_s32_x3(
+// CIR-LABEL: @test_vst1_s32_x3(
+void test_vst1_s32_x3(int32_t *a, int32x2x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x3" {{.*}} : (!cir.vector<2 x !s32i>, !cir.vector<2 x !s32i>, !cir.vector<2 x !s32i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x3.v2i32.p0(<2 x i32> {{.*}}, <2 x i32> {{.*}}, <2 x i32> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_s32_x3(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_s32_x4(
+// CIR-LABEL: @test_vst1_s32_x4(
+void test_vst1_s32_x4(int32_t *a, int32x2x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x4" {{.*}} : (!cir.vector<2 x !s32i>, !cir.vector<2 x !s32i>, !cir.vector<2 x !s32i>, !cir.vector<2 x !s32i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x4.v2i32.p0(<2 x i32> {{.*}}, <2 x i32> {{.*}}, <2 x i32> {{.*}}, <2 x i32> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_s32_x4(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_s64_x2(
+// CIR-LABEL: @test_vst1_s64_x2(
+void test_vst1_s64_x2(int64_t *a, int64x1x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x2" {{.*}} : (!cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x2.v1i64.p0(<1 x i64> {{.*}}, <1 x i64> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_s64_x2(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_s64_x3(
+// CIR-LABEL: @test_vst1_s64_x3(
+void test_vst1_s64_x3(int64_t *a, int64x1x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x3" {{.*}} : (!cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x3.v1i64.p0(<1 x i64> {{.*}}, <1 x i64> {{.*}}, <1 x i64> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_s64_x3(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_s64_x4(
+// CIR-LABEL: @test_vst1_s64_x4(
+void test_vst1_s64_x4(int64_t *a, int64x1x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x4" {{.*}} : (!cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x4.v1i64.p0(<1 x i64> {{.*}}, <1 x i64> {{.*}}, <1 x i64> {{.*}}, <1 x i64> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_s64_x4(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_s8_x2(
+// CIR-LABEL: @test_vst1_s8_x2(
+void test_vst1_s8_x2(int8_t *a, int8x8x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x2" {{.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x2.v8i8.p0(<8 x i8> {{.*}}, <8 x i8> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_s8_x2(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_s8_x3(
+// CIR-LABEL: @test_vst1_s8_x3(
+void test_vst1_s8_x3(int8_t *a, int8x8x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x3" {{.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x3.v8i8.p0(<8 x i8> {{.*}}, <8 x i8> {{.*}}, <8 x i8> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_s8_x3(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_s8_x4(
+// CIR-LABEL: @test_vst1_s8_x4(
+void test_vst1_s8_x4(int8_t *a, int8x8x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x4" {{.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x4.v8i8.p0(<8 x i8> {{.*}}, <8 x i8> {{.*}}, <8 x i8> {{.*}}, <8 x i8> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_s8_x4(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_u16_x2(
+// CIR-LABEL: @test_vst1_u16_x2(
+void test_vst1_u16_x2(uint16_t *a, uint16x4x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x2" {{.*}} : (!cir.vector<4 x !u16i>, !cir.vector<4 x !u16i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x2.v4i16.p0(<4 x i16> {{.*}}, <4 x i16> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_u16_x2(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_u16_x3(
+// CIR-LABEL: @test_vst1_u16_x3(
+void test_vst1_u16_x3(uint16_t *a, uint16x4x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x3" {{.*}} : (!cir.vector<4 x !u16i>, !cir.vector<4 x !u16i>, !cir.vector<4 x !u16i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x3.v4i16.p0(<4 x i16> {{.*}}, <4 x i16> {{.*}}, <4 x i16> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_u16_x3(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_u16_x4(
+// CIR-LABEL: @test_vst1_u16_x4(
+void test_vst1_u16_x4(uint16_t *a, uint16x4x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x4" {{.*}} : (!cir.vector<4 x !u16i>, !cir.vector<4 x !u16i>, !cir.vector<4 x !u16i>, !cir.vector<4 x !u16i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x4.v4i16.p0(<4 x i16> {{.*}}, <4 x i16> {{.*}}, <4 x i16> {{.*}}, <4 x i16> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_u16_x4(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_u32_x2(
+// CIR-LABEL: @test_vst1_u32_x2(
+void test_vst1_u32_x2(uint32_t *a, uint32x2x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x2" {{.*}} : (!cir.vector<2 x !u32i>, !cir.vector<2 x !u32i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x2.v2i32.p0(<2 x i32> {{.*}}, <2 x i32> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_u32_x2(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_u32_x3(
+// CIR-LABEL: @test_vst1_u32_x3(
+void test_vst1_u32_x3(uint32_t *a, uint32x2x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x3" {{.*}} : (!cir.vector<2 x !u32i>, !cir.vector<2 x !u32i>, !cir.vector<2 x !u32i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x3.v2i32.p0(<2 x i32> {{.*}}, <2 x i32> {{.*}}, <2 x i32> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_u32_x3(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_u32_x4(
+// CIR-LABEL: @test_vst1_u32_x4(
+void test_vst1_u32_x4(uint32_t *a, uint32x2x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x4" {{.*}} : (!cir.vector<2 x !u32i>, !cir.vector<2 x !u32i>, !cir.vector<2 x !u32i>, !cir.vector<2 x !u32i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x4.v2i32.p0(<2 x i32> {{.*}}, <2 x i32> {{.*}}, <2 x i32> {{.*}}, <2 x i32> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_u32_x4(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_u64_x2(
+// CIR-LABEL: @test_vst1_u64_x2(
+void test_vst1_u64_x2(uint64_t *a, uint64x1x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x2" {{.*}} : (!cir.vector<1 x !u64i>, !cir.vector<1 x !u64i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x2.v1i64.p0(<1 x i64> {{.*}}, <1 x i64> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_u64_x2(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_u64_x3(
+// CIR-LABEL: @test_vst1_u64_x3(
+void test_vst1_u64_x3(uint64_t *a, uint64x1x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x3" {{.*}} : (!cir.vector<1 x !u64i>, !cir.vector<1 x !u64i>, !cir.vector<1 x !u64i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x3.v1i64.p0(<1 x i64> {{.*}}, <1 x i64> {{.*}}, <1 x i64> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_u64_x3(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_u64_x4(
+// CIR-LABEL: @test_vst1_u64_x4(
+void test_vst1_u64_x4(uint64_t *a, uint64x1x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x4" {{.*}} : (!cir.vector<1 x !u64i>, !cir.vector<1 x !u64i>, !cir.vector<1 x !u64i>, !cir.vector<1 x !u64i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x4.v1i64.p0(<1 x i64> {{.*}}, <1 x i64> {{.*}}, <1 x i64> {{.*}}, <1 x i64> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_u64_x4(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_u8_x2(
+// CIR-LABEL: @test_vst1_u8_x2(
+void test_vst1_u8_x2(uint8_t *a, uint8x8x2_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x2" {{.*}} : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x2.v8i8.p0(<8 x i8> {{.*}}, <8 x i8> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_u8_x2(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_u8_x3(
+// CIR-LABEL: @test_vst1_u8_x3(
+void test_vst1_u8_x3(uint8_t *a, uint8x8x3_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x3" {{.*}} : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x3.v8i8.p0(<8 x i8> {{.*}}, <8 x i8> {{.*}}, <8 x i8> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_u8_x3(a, b);
+}
+
+// LLVM-LABEL: @test_vst1_u8_x4(
+// CIR-LABEL: @test_vst1_u8_x4(
+void test_vst1_u8_x4(uint8_t *a, uint8x8x4_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.st1x4" {{.*}} : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>, !cir.ptr<!void>) -> !void
+
+// LLVM: call void @llvm.aarch64.neon.st1x4.v8i8.p0(<8 x i8> {{.*}}, <8 x i8> {{.*}}, <8 x i8> {{.*}}, <8 x i8> {{.*}}, ptr {{.*}})
+// LLVM: ret void
+ vst1_u8_x4(a, b);
+}
diff --git a/clang/test/CodeGen/AArch64/poly64.c b/clang/test/CodeGen/AArch64/poly64.c
index 36409a97d32f1..f422a82f65138 100644
--- a/clang/test/CodeGen/AArch64/poly64.c
+++ b/clang/test/CodeGen/AArch64/poly64.c
@@ -232,30 +232,6 @@ poly64x2_t test_vld1q_p64(poly64_t const * ptr) {
return vld1q_p64(ptr);
}
-// CHECK-LABEL: define dso_local void @test_vst1_p64(
-// CHECK-SAME: ptr noundef [[PTR:%.*]], <1 x i64> noundef [[VAL:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[VAL]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: store <1 x i64> [[TMP1]], ptr [[PTR]], align 8
-// CHECK-NEXT: ret void
-//
-void test_vst1_p64(poly64_t * ptr, poly64x1_t val) {
- return vst1_p64(ptr, val);
-}
-
-// CHECK-LABEL: define dso_local void @test_vst1q_p64(
-// CHECK-SAME: ptr noundef [[PTR:%.*]], <2 x i64> noundef [[VAL:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[VAL]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: store <2 x i64> [[TMP1]], ptr [[PTR]], align 8
-// CHECK-NEXT: ret void
-//
-void test_vst1q_p64(poly64_t * ptr, poly64x2_t val) {
- return vst1q_p64(ptr, val);
-}
-
// CHECK-LABEL: define dso_local %struct.poly64x1x2_t @test_vld2_p64(
// CHECK-SAME: ptr noundef [[PTR:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
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