[clang] [llvm] [RISCV] Add support for vector registers with -fzero-call-used-regs (PR #206206)

[Luke Lau via cfe-commits]

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@@ -1511,9 +1513,42 @@ void RISCVFrameLowering::emitZeroCallUsedRegs(BitVector RegsToZero,
     } else if (TRI.isFPRegister(Reg)) {
       if (MCRegister MaybeReg = getLargestFPRegisterOrZero(STI, TRI, Reg))
         FinalRegsToZero.set(MaybeReg.id());
+    } else if (RISCVRegisterInfo::isRVVRegClass(
+                   TRI.getMinimalPhysRegClass(Reg))) {
+      if (!STI.hasVInstructions())
+        continue;
+      HasVRegister = true;
+
+      for (MCRegister SubReg : TRI.subregs_inclusive(Reg)) {
+        if (TRI.subregs(SubReg).empty())
+          FinalRegsToZero.set(SubReg.id());
+      }
     }
   }
 
+  if (HasVRegister) {
+    RISCVVType::VLMUL VLMUL = RISCVVType::encodeLMUL(1, /*Fractional=*/false);
+    unsigned VTypeImm = RISCVVType::encodeVTYPE(
+        VLMUL, /*SEW=*/32, /*TailAgnostic=*/false, /*MaskAgnostic=*/false);
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lukel97 wrote:

Might as well use ta,ma to give uarchs more freedom. You could also use EEW=64 on zve64x to operate on a lower VLEN. I don't think the latter matters much in practice.

https://github.com/llvm/llvm-project/pull/206206