[clang] [llvm] [RISCV] Add support for vector registers with -fzero-call-used-regs (PR #206206)

[Luke Lau via cfe-commits]

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@@ -0,0 +1,215 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv64-unknown-unknown -mattr="+i,+m,+v" | FileCheck %s  --check-prefixes=CHECK
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lukel97 wrote:

+i isn't an extension, +m isn't used. the quotes can be avoided too. You also don't need the full triple. FileCheck defaults to CHECK for the default prefix.

```suggestion
; RUN: llc < %s -verify-machineinstrs -mtriple=riscv64 -mattr=+v | FileCheck %s 
```

https://github.com/llvm/llvm-project/pull/206206