[clang] 670e0a0 - [IR] Use pretty printing for mask in is_fpclass (#207653)
via cfe-commits
cfe-commits at lists.llvm.org
Sat Jul 11 09:54:11 PDT 2026
Author: Serge Pavlov
Date: 2026-07-11T23:54:03+07:00
New Revision: 670e0a0c147aeade297b3235f5ade3786abd7d4c
URL: https://github.com/llvm/llvm-project/commit/670e0a0c147aeade297b3235f5ade3786abd7d4c
DIFF: https://github.com/llvm/llvm-project/commit/670e0a0c147aeade297b3235f5ade3786abd7d4c.diff
LOG: [IR] Use pretty printing for mask in is_fpclass (#207653)
The second argument of `llvm.is_fpclass` is a mask, where each bit
represents a floating-point class. Understanding the check that the call
makes in an IR dump requires additional effort. To simplify the
interpretation of IR dumps, a previously implemented pretty-printing
mechanism can be used:
https://github.com/llvm/llvm-project/commit/39e7712ac520ccfc43383b3e9d6ea8cf2958b8e3.
This commit implements this mechanism for printing the arguments of
`llvm.is_fpclass`.
This change also fixes the printing of argument names: if an argument
name is absent, it is simply not printed.
Added:
llvm/test/Assembler/print-formatted.ll
Modified:
clang/test/CodeGen/AArch64/strictfp-builtins.c
clang/test/CodeGen/X86/strictfp_builtins.c
clang/test/CodeGen/builtin_float.c
clang/test/CodeGen/builtin_float_strictfp.c
clang/test/CodeGen/builtins.c
clang/test/CodeGen/isfpclass.c
clang/test/CodeGen/strictfp_builtins.c
clang/test/Headers/amdgcn-openmp-device-math-complex.c
clang/test/Headers/amdgcn-openmp-device-math-complex.cpp
clang/test/Headers/hip-header.hip
clang/test/Headers/nvptx_device_math_complex.c
clang/test/Headers/nvptx_device_math_complex.cpp
clang/test/Headers/openmp_device_math_isnan.cpp
llvm/include/llvm/IR/Intrinsics.h
llvm/include/llvm/IR/Intrinsics.td
llvm/lib/IR/Intrinsics.cpp
llvm/test/Analysis/CostModel/AMDGPU/is_fpclass.ll
llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.f64.ll
llvm/test/Instrumentation/MemorySanitizer/is-fpclass.ll
llvm/test/Transforms/Attributor/nofpclass-select.ll
llvm/test/Transforms/Attributor/nofpclass.ll
llvm/test/Transforms/CodeGenPrepare/AArch64/fpclass-test.ll
llvm/test/Transforms/CodeGenPrepare/RISCV/fpclass-test.ll
llvm/test/Transforms/CodeGenPrepare/X86/fpclass-test.ll
llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
llvm/test/Transforms/InstCombine/combine-is.fpclass-and-fcmp.ll
llvm/test/Transforms/InstCombine/create-class-from-logic-fcmp.ll
llvm/test/Transforms/InstCombine/fabs.ll
llvm/test/Transforms/InstCombine/fadd.ll
llvm/test/Transforms/InstCombine/fpclass-check-idioms.ll
llvm/test/Transforms/InstCombine/fpclass-from-dom-cond.ll
llvm/test/Transforms/InstCombine/freeze-fp-ops.ll
llvm/test/Transforms/InstCombine/freeze-phi.ll
llvm/test/Transforms/InstCombine/is_fpclass.ll
llvm/test/Transforms/InstCombine/pr80941.ll
llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fdiv.ll
llvm/test/Transforms/InstSimplify/canonicalize.ll
llvm/test/Transforms/LoopVectorize/is_fpclass.ll
llvm/test/Transforms/SLPVectorizer/is_fpclass.ll
llvm/test/Transforms/Scalarizer/intrinsics.ll
llvm/test/Transforms/SpeculativeExecution/spec-calls.ll
llvm/test/Transforms/VectorCombine/AArch64/shuffle-of-intrinsics.ll
llvm/test/Transforms/VectorCombine/RISCV/shuffle-of-intrinsics.ll
llvm/test/Transforms/VectorCombine/X86/shuffle-of-intrinsics.ll
llvm/test/tools/llubi/intr_fp_is_fpclass.ll
llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp
Removed:
################################################################################
diff --git a/clang/test/CodeGen/AArch64/strictfp-builtins.c b/clang/test/CodeGen/AArch64/strictfp-builtins.c
index d762ae96965cb..a6d66c2a8d1eb 100644
--- a/clang/test/CodeGen/AArch64/strictfp-builtins.c
+++ b/clang/test/CodeGen/AArch64/strictfp-builtins.c
@@ -29,7 +29,7 @@ void p(char *str, int x) {
// CHECK-NEXT: [[LD_ADDR:%.*]] = alloca fp128, align 16
// CHECK-NEXT: store fp128 [[D:%.*]], ptr [[LD_ADDR]], align 16
// CHECK-NEXT: [[TMP0:%.*]] = load fp128, ptr [[LD_ADDR]], align 16
-// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[TMP0]], i32 516)
+// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[TMP0]], /* (inf) */ i32 516)
// CHECK-NEXT: [[RES:%.*]] = zext i1 [[TMP1]] to i32
// CHECK-NEXT: call void @p(ptr noundef @.str.[[#STRID:1]], i32 noundef [[RES]]) [[ATTR4]]
// CHECK-NEXT: ret void
@@ -45,7 +45,7 @@ void test_long_double_isinf(long double ld) {
// CHECK-NEXT: [[LD_ADDR:%.*]] = alloca fp128, align 16
// CHECK-NEXT: store fp128 [[D:%.*]], ptr [[LD_ADDR]], align 16
// CHECK-NEXT: [[TMP0:%.*]] = load fp128, ptr [[LD_ADDR]], align 16
-// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[TMP0]], i32 504)
+// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[TMP0]], /* (zero sub norm) */ i32 504)
// CHECK-NEXT: [[RES:%.*]] = zext i1 [[TMP1]] to i32
// CHECK-NEXT: call void @p(ptr noundef @.str.[[#STRID:STRID+1]], i32 noundef [[RES]]) [[ATTR4]]
// CHECK-NEXT: ret void
@@ -61,7 +61,7 @@ void test_long_double_isfinite(long double ld) {
// CHECK-NEXT: [[LD_ADDR:%.*]] = alloca fp128, align 16
// CHECK-NEXT: store fp128 [[D:%.*]], ptr [[LD_ADDR]], align 16
// CHECK-NEXT: [[TMP0:%.*]] = load fp128, ptr [[LD_ADDR]], align 16
-// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[TMP0]], i32 3)
+// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[TMP0]], /* (nan) */ i32 3)
// CHECK-NEXT: [[RES:%.*]] = zext i1 [[TMP1]] to i32
// CHECK-NEXT: call void @p(ptr noundef @.str.[[#STRID:STRID+1]], i32 noundef [[RES]])
// CHECK-NEXT: ret void
diff --git a/clang/test/CodeGen/X86/strictfp_builtins.c b/clang/test/CodeGen/X86/strictfp_builtins.c
index 43e4060bef259..ee9761a1c4d49 100644
--- a/clang/test/CodeGen/X86/strictfp_builtins.c
+++ b/clang/test/CodeGen/X86/strictfp_builtins.c
@@ -27,7 +27,7 @@ void p(char *str, int x) {
// CHECK-NEXT: [[LD_ADDR:%.*]] = alloca x86_fp80, align 16
// CHECK-NEXT: store x86_fp80 [[LD:%.*]], ptr [[LD_ADDR]], align 16
// CHECK-NEXT: [[TMP0:%.*]] = load x86_fp80, ptr [[LD_ADDR]], align 16
-// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f80(x86_fp80 [[TMP0]], i32 516) #[[ATTR3]]
+// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f80(x86_fp80 [[TMP0]], /* (inf) */ i32 516) #[[ATTR3]]
// CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP1]] to i32
// CHECK-NEXT: call void @p(ptr noundef @.str.1, i32 noundef [[TMP2]]) #[[ATTR3]]
// CHECK-NEXT: ret void
@@ -43,7 +43,7 @@ void test_long_double_isinf(long double ld) {
// CHECK-NEXT: [[LD_ADDR:%.*]] = alloca x86_fp80, align 16
// CHECK-NEXT: store x86_fp80 [[LD:%.*]], ptr [[LD_ADDR]], align 16
// CHECK-NEXT: [[TMP0:%.*]] = load x86_fp80, ptr [[LD_ADDR]], align 16
-// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f80(x86_fp80 [[TMP0]], i32 504) #[[ATTR3]]
+// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f80(x86_fp80 [[TMP0]], /* (zero sub norm) */ i32 504) #[[ATTR3]]
// CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP1]] to i32
// CHECK-NEXT: call void @p(ptr noundef @.str.2, i32 noundef [[TMP2]]) #[[ATTR3]]
// CHECK-NEXT: ret void
@@ -59,7 +59,7 @@ void test_long_double_isfinite(long double ld) {
// CHECK-NEXT: [[LD_ADDR:%.*]] = alloca x86_fp80, align 16
// CHECK-NEXT: store x86_fp80 [[LD:%.*]], ptr [[LD_ADDR]], align 16
// CHECK-NEXT: [[TMP0:%.*]] = load x86_fp80, ptr [[LD_ADDR]], align 16
-// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f80(x86_fp80 [[TMP0]], i32 3) #[[ATTR3]]
+// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f80(x86_fp80 [[TMP0]], /* (nan) */ i32 3) #[[ATTR3]]
// CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP1]] to i32
// CHECK-NEXT: call void @p(ptr noundef @.str.3, i32 noundef [[TMP2]]) #[[ATTR3]]
// CHECK-NEXT: ret void
diff --git a/clang/test/CodeGen/builtin_float.c b/clang/test/CodeGen/builtin_float.c
index 1c1ce6195b4be..7c6225c789e2b 100644
--- a/clang/test/CodeGen/builtin_float.c
+++ b/clang/test/CodeGen/builtin_float.c
@@ -49,7 +49,7 @@ void test_half(__fp16 *H, __fp16 *H2) {
// CHECK: fcmp ogt float
// CHECK-NEXT: zext i1
(void)__builtin_isinf(*H);
- // CHECK: call i1 @llvm.is.fpclass.f16(half %{{.*}}, i32 516)
+ // CHECK: call i1 @llvm.is.fpclass.f16(half %{{.*}}, /* (inf) */ i32 516)
}
void test_mixed(double d1, float f2) {
diff --git a/clang/test/CodeGen/builtin_float_strictfp.c b/clang/test/CodeGen/builtin_float_strictfp.c
index 7966110ddfcd1..6fd65de308688 100644
--- a/clang/test/CodeGen/builtin_float_strictfp.c
+++ b/clang/test/CodeGen/builtin_float_strictfp.c
@@ -20,11 +20,11 @@ void test_half(__fp16 *H, __fp16 *H2) {
// NOFP16-NEXT: [[IHALF:%.*]] = load i16, ptr [[LDADDR]], align 2
// NOFP16-NEXT: [[BITCAST:%.*]] = bitcast i16 [[IHALF]] to half
// NOFP16-NEXT: [[CONV:%.*]] = call float @llvm.experimental.constrained.fpext.f32.f16(half [[BITCAST]], metadata !"fpexcept.strict")
- // NOFP16-NEXT: [[RES1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[CONV]], i32 516)
+ // NOFP16-NEXT: [[RES1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[CONV]], /* (inf) */ i32 516)
// NOFP16-NEXT: zext i1 [[RES1]] to i32
// FP16: [[LDADDR:%.*]] = load ptr, ptr %{{.*}}, align 8
// FP16-NEXT: [[HALF:%.*]] = load half, ptr [[LDADDR]], align 2
- // FP16-NEXT: [[RES1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[HALF]], i32 516)
+ // FP16-NEXT: [[RES1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[HALF]], /* (inf) */ i32 516)
// FP16-NEXT: zext i1 [[RES1]] to i32
}
diff --git a/clang/test/CodeGen/builtins.c b/clang/test/CodeGen/builtins.c
index 44924062609c8..6603d255ff7fb 100644
--- a/clang/test/CodeGen/builtins.c
+++ b/clang/test/CodeGen/builtins.c
@@ -250,20 +250,20 @@ void test_conditional_bcopy(void) {
void test_float_builtins(__fp16 *H, float F, double D, long double LD) {
volatile int res;
res = __builtin_isinf(*H);
- // CHECK: [[TMP:%.*]] = call i1 @llvm.is.fpclass.f16(half {{.*}}, i32 516)
+ // CHECK: [[TMP:%.*]] = call i1 @llvm.is.fpclass.f16(half {{.*}}, /* (inf) */ i32 516)
// CHECK: zext i1 [[TMP]] to i32
res = __builtin_isinf(F);
- // CHECK: [[TMP:%.*]] = call i1 @llvm.is.fpclass.f32(float {{.*}}, i32 516)
+ // CHECK: [[TMP:%.*]] = call i1 @llvm.is.fpclass.f32(float {{.*}}, /* (inf) */ i32 516)
// CHECK: zext i1 [[TMP]] to i32
res = __builtin_isinf(D);
- // CHECK: [[TMP:%.*]] = call i1 @llvm.is.fpclass.f64(double {{.*}}, i32 516)
+ // CHECK: [[TMP:%.*]] = call i1 @llvm.is.fpclass.f64(double {{.*}}, /* (inf) */ i32 516)
// CHECK: zext i1 [[TMP]] to i32
res = __builtin_isinf(LD);
- // LD80: [[TMP:%.*]] = call i1 @llvm.is.fpclass.[[LDLLVMTY:f80]]([[LDTYPE]] {{.*}}, i32 516)
- // LD64: [[TMP:%.*]] = call i1 @llvm.is.fpclass.[[LDLLVMTY:f64]]([[LDTYPE]] {{.*}}, i32 516)
+ // LD80: [[TMP:%.*]] = call i1 @llvm.is.fpclass.[[LDLLVMTY:f80]]([[LDTYPE]] {{.*}}, /* (inf) */ i32 516)
+ // LD64: [[TMP:%.*]] = call i1 @llvm.is.fpclass.[[LDLLVMTY:f64]]([[LDTYPE]] {{.*}}, /* (inf) */ i32 516)
// CHECK: zext i1 [[TMP]] to i32
res = __builtin_isinf_sign(*H);
@@ -300,35 +300,35 @@ void test_float_builtins(__fp16 *H, float F, double D, long double LD) {
// CHECK: select i1 %[[ISINF]], i32 %[[SIGN]], i32 0
res = __builtin_isfinite(*H);
- // CHECK: [[TMP:%.*]] = call i1 @llvm.is.fpclass.f16(half {{.*}}, i32 504)
+ // CHECK: [[TMP:%.*]] = call i1 @llvm.is.fpclass.f16(half {{.*}}, /* (zero sub norm) */ i32 504)
// CHECK: zext i1 [[TMP]] to i32
res = __builtin_isfinite(F);
- // CHECK: [[TMP:%.*]] = call i1 @llvm.is.fpclass.f32(float {{.*}}, i32 504)
+ // CHECK: [[TMP:%.*]] = call i1 @llvm.is.fpclass.f32(float {{.*}}, /* (zero sub norm) */ i32 504)
// CHECK: zext i1 [[TMP]] to i32
res = finite(D);
- // CHECK: [[TMP:%.*]] = call i1 @llvm.is.fpclass.f64(double {{.*}}, i32 504)
+ // CHECK: [[TMP:%.*]] = call i1 @llvm.is.fpclass.f64(double {{.*}}, /* (zero sub norm) */ i32 504)
// CHECK: zext i1 [[TMP]] to i32
res = __builtin_isnormal(*H);
- // CHECK: [[TMP:%.*]] = call i1 @llvm.is.fpclass.f16(half {{.*}}, i32 264)
+ // CHECK: [[TMP:%.*]] = call i1 @llvm.is.fpclass.f16(half {{.*}}, /* (norm) */ i32 264)
// CHECK: zext i1 [[TMP]] to i32
res = __builtin_isnormal(F);
- // CHECK: [[TMP:%.*]] = call i1 @llvm.is.fpclass.f32(float {{.*}}, i32 264)
+ // CHECK: [[TMP:%.*]] = call i1 @llvm.is.fpclass.f32(float {{.*}}, /* (norm) */ i32 264)
// CHECK: zext i1 [[TMP]] to i32
res = __builtin_issubnormal(F);
- // CHECK: [[TMP:%.*]] = call i1 @llvm.is.fpclass.f32(float {{.*}}, i32 144)
+ // CHECK: [[TMP:%.*]] = call i1 @llvm.is.fpclass.f32(float {{.*}}, /* (sub) */ i32 144)
// CHECK: zext i1 [[TMP]] to i32
res = __builtin_iszero(F);
- // CHECK: [[TMP:%.*]] = call i1 @llvm.is.fpclass.f32(float {{.*}}, i32 96)
+ // CHECK: [[TMP:%.*]] = call i1 @llvm.is.fpclass.f32(float {{.*}}, /* (zero) */ i32 96)
// CHECK: zext i1 [[TMP]] to i32
res = __builtin_issignaling(F);
- // CHECK: [[TMP:%.*]] = call i1 @llvm.is.fpclass.f32(float {{.*}}, i32 1)
+ // CHECK: [[TMP:%.*]] = call i1 @llvm.is.fpclass.f32(float {{.*}}, /* (snan) */ i32 1)
// CHECK: zext i1 [[TMP]] to i32
res = __builtin_flt_rounds();
diff --git a/clang/test/CodeGen/isfpclass.c b/clang/test/CodeGen/isfpclass.c
index 67eb71e8f5f60..dad37d1da63af 100644
--- a/clang/test/CodeGen/isfpclass.c
+++ b/clang/test/CodeGen/isfpclass.c
@@ -15,7 +15,7 @@ _Bool check_isfpclass_finite(float x) {
// CHECK-LABEL: define dso_local noundef i1 @check_isfpclass_finite_strict(
// CHECK-SAME: float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR2:[0-9]+]] {
// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f32(float [[X]], i32 504) #[[ATTR5:[0-9]+]]
+// CHECK-NEXT: [[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f32(float [[X]], /* (zero sub norm) */ i32 504) #[[ATTR5:[0-9]+]]
// CHECK-NEXT: ret i1 [[TMP0]]
//
_Bool check_isfpclass_finite_strict(float x) {
@@ -36,7 +36,7 @@ _Bool check_isfpclass_nan_f32(float x) {
// CHECK-LABEL: define dso_local noundef i1 @check_isfpclass_nan_f32_strict(
// CHECK-SAME: float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR2]] {
// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f32(float [[X]], i32 3) #[[ATTR5]]
+// CHECK-NEXT: [[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f32(float [[X]], /* (nan) */ i32 3) #[[ATTR5]]
// CHECK-NEXT: ret i1 [[TMP0]]
//
_Bool check_isfpclass_nan_f32_strict(float x) {
@@ -47,7 +47,7 @@ _Bool check_isfpclass_nan_f32_strict(float x) {
// CHECK-LABEL: define dso_local noundef i1 @check_isfpclass_snan_f64(
// CHECK-SAME: double noundef [[X:%.*]]) local_unnamed_addr #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f64(double [[X]], i32 1)
+// CHECK-NEXT: [[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f64(double [[X]], /* (snan) */ i32 1)
// CHECK-NEXT: ret i1 [[TMP0]]
//
_Bool check_isfpclass_snan_f64(double x) {
@@ -57,7 +57,7 @@ _Bool check_isfpclass_snan_f64(double x) {
// CHECK-LABEL: define dso_local noundef i1 @check_isfpclass_snan_f64_strict(
// CHECK-SAME: double noundef [[X:%.*]]) local_unnamed_addr #[[ATTR2]] {
// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f64(double [[X]], i32 1) #[[ATTR5]]
+// CHECK-NEXT: [[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f64(double [[X]], /* (snan) */ i32 1) #[[ATTR5]]
// CHECK-NEXT: ret i1 [[TMP0]]
//
_Bool check_isfpclass_snan_f64_strict(double x) {
@@ -78,7 +78,7 @@ _Bool check_isfpclass_zero_f16(_Float16 x) {
// CHECK-LABEL: define dso_local noundef i1 @check_isfpclass_zero_f16_strict(
// CHECK-SAME: half noundef [[X:%.*]]) local_unnamed_addr #[[ATTR2]] {
// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f16(half [[X]], i32 96) #[[ATTR5]]
+// CHECK-NEXT: [[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f16(half [[X]], /* (zero) */ i32 96) #[[ATTR5]]
// CHECK-NEXT: ret i1 [[TMP0]]
//
_Bool check_isfpclass_zero_f16_strict(_Float16 x) {
@@ -89,7 +89,7 @@ _Bool check_isfpclass_zero_f16_strict(_Float16 x) {
// CHECK-LABEL: define dso_local noundef i1 @check_isnan(
// CHECK-SAME: float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR2]] {
// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f32(float [[X]], i32 3) #[[ATTR5]]
+// CHECK-NEXT: [[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f32(float [[X]], /* (nan) */ i32 3) #[[ATTR5]]
// CHECK-NEXT: ret i1 [[TMP0]]
//
_Bool check_isnan(float x) {
@@ -100,7 +100,7 @@ _Bool check_isnan(float x) {
// CHECK-LABEL: define dso_local noundef i1 @check_isinf(
// CHECK-SAME: float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR2]] {
// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f32(float [[X]], i32 516) #[[ATTR5]]
+// CHECK-NEXT: [[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f32(float [[X]], /* (inf) */ i32 516) #[[ATTR5]]
// CHECK-NEXT: ret i1 [[TMP0]]
//
_Bool check_isinf(float x) {
@@ -111,7 +111,7 @@ _Bool check_isinf(float x) {
// CHECK-LABEL: define dso_local noundef i1 @check_isfinite(
// CHECK-SAME: float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR2]] {
// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f32(float [[X]], i32 504) #[[ATTR5]]
+// CHECK-NEXT: [[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f32(float [[X]], /* (zero sub norm) */ i32 504) #[[ATTR5]]
// CHECK-NEXT: ret i1 [[TMP0]]
//
_Bool check_isfinite(float x) {
@@ -122,7 +122,7 @@ _Bool check_isfinite(float x) {
// CHECK-LABEL: define dso_local noundef i1 @check_isnormal(
// CHECK-SAME: float noundef [[X:%.*]]) local_unnamed_addr #[[ATTR2]] {
// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f32(float [[X]], i32 264) #[[ATTR5]]
+// CHECK-NEXT: [[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f32(float [[X]], /* (norm) */ i32 264) #[[ATTR5]]
// CHECK-NEXT: ret i1 [[TMP0]]
//
_Bool check_isnormal(float x) {
@@ -150,7 +150,7 @@ int4 check_isfpclass_nan_v4f32(float4 x) {
// CHECK-LABEL: define dso_local range(i32 0, 2) <4 x i32> @check_isfpclass_nan_strict_v4f32(
// CHECK-SAME: <4 x float> noundef [[X:%.*]]) local_unnamed_addr #[[ATTR2]] {
// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = tail call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> [[X]], i32 3) #[[ATTR5]]
+// CHECK-NEXT: [[TMP0:%.*]] = tail call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> [[X]], /* (nan) */ i32 3) #[[ATTR5]]
// CHECK-NEXT: [[TMP1:%.*]] = zext <4 x i1> [[TMP0]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP1]]
//
diff --git a/clang/test/CodeGen/strictfp_builtins.c b/clang/test/CodeGen/strictfp_builtins.c
index 8b6cdcc38c8af..494e8f737f2ab 100644
--- a/clang/test/CodeGen/strictfp_builtins.c
+++ b/clang/test/CodeGen/strictfp_builtins.c
@@ -60,7 +60,7 @@ void test_fpclassify(double d) {
// CHECK-NEXT: [[H_ADDR:%.*]] = alloca half, align 2
// CHECK-NEXT: store half [[H:%.*]], ptr [[H_ADDR]], align 2
// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[H_ADDR]], align 2
-// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[TMP0]], i32 516) #[[ATTR4]]
+// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[TMP0]], /* (inf) */ i32 516) #[[ATTR4]]
// CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP1]] to i32
// CHECK-NEXT: call void @p(ptr noundef @.str.2, i32 noundef [[TMP2]]) #[[ATTR4]]
// CHECK-NEXT: ret void
@@ -76,7 +76,7 @@ void test_fp16_isinf(_Float16 h) {
// CHECK-NEXT: [[F_ADDR:%.*]] = alloca float, align 4
// CHECK-NEXT: store float [[F:%.*]], ptr [[F_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[F_ADDR]], align 4
-// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[TMP0]], i32 516) #[[ATTR4]]
+// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[TMP0]], /* (inf) */ i32 516) #[[ATTR4]]
// CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP1]] to i32
// CHECK-NEXT: call void @p(ptr noundef @.str.3, i32 noundef [[TMP2]]) #[[ATTR4]]
// CHECK-NEXT: ret void
@@ -92,7 +92,7 @@ void test_float_isinf(float f) {
// CHECK-NEXT: [[D_ADDR:%.*]] = alloca double, align 8
// CHECK-NEXT: store double [[D:%.*]], ptr [[D_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load double, ptr [[D_ADDR]], align 8
-// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[TMP0]], i32 516) #[[ATTR4]]
+// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[TMP0]], /* (inf) */ i32 516) #[[ATTR4]]
// CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP1]] to i32
// CHECK-NEXT: call void @p(ptr noundef @.str.4, i32 noundef [[TMP2]]) #[[ATTR4]]
// CHECK-NEXT: ret void
@@ -108,7 +108,7 @@ void test_double_isinf(double d) {
// CHECK-NEXT: [[H_ADDR:%.*]] = alloca half, align 2
// CHECK-NEXT: store half [[H:%.*]], ptr [[H_ADDR]], align 2
// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[H_ADDR]], align 2
-// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[TMP0]], i32 504) #[[ATTR4]]
+// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[TMP0]], /* (zero sub norm) */ i32 504) #[[ATTR4]]
// CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP1]] to i32
// CHECK-NEXT: call void @p(ptr noundef @.str.5, i32 noundef [[TMP2]]) #[[ATTR4]]
// CHECK-NEXT: ret void
@@ -124,7 +124,7 @@ void test_fp16_isfinite(_Float16 h) {
// CHECK-NEXT: [[F_ADDR:%.*]] = alloca float, align 4
// CHECK-NEXT: store float [[F:%.*]], ptr [[F_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[F_ADDR]], align 4
-// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[TMP0]], i32 504) #[[ATTR4]]
+// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[TMP0]], /* (zero sub norm) */ i32 504) #[[ATTR4]]
// CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP1]] to i32
// CHECK-NEXT: call void @p(ptr noundef @.str.6, i32 noundef [[TMP2]]) #[[ATTR4]]
// CHECK-NEXT: ret void
@@ -140,7 +140,7 @@ void test_float_isfinite(float f) {
// CHECK-NEXT: [[D_ADDR:%.*]] = alloca double, align 8
// CHECK-NEXT: store double [[D:%.*]], ptr [[D_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load double, ptr [[D_ADDR]], align 8
-// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[TMP0]], i32 504) #[[ATTR4]]
+// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[TMP0]], /* (zero sub norm) */ i32 504) #[[ATTR4]]
// CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP1]] to i32
// CHECK-NEXT: call void @p(ptr noundef @.str.7, i32 noundef [[TMP2]]) #[[ATTR4]]
// CHECK-NEXT: ret void
@@ -176,7 +176,7 @@ void test_isinf_sign(double d) {
// CHECK-NEXT: [[H_ADDR:%.*]] = alloca half, align 2
// CHECK-NEXT: store half [[H:%.*]], ptr [[H_ADDR]], align 2
// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[H_ADDR]], align 2
-// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[TMP0]], i32 3) #[[ATTR4]]
+// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[TMP0]], /* (nan) */ i32 3) #[[ATTR4]]
// CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP1]] to i32
// CHECK-NEXT: call void @p(ptr noundef @.str.9, i32 noundef [[TMP2]]) #[[ATTR4]]
// CHECK-NEXT: ret void
@@ -192,7 +192,7 @@ void test_fp16_isnan(_Float16 h) {
// CHECK-NEXT: [[F_ADDR:%.*]] = alloca float, align 4
// CHECK-NEXT: store float [[F:%.*]], ptr [[F_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[F_ADDR]], align 4
-// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[TMP0]], i32 3) #[[ATTR4]]
+// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[TMP0]], /* (nan) */ i32 3) #[[ATTR4]]
// CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP1]] to i32
// CHECK-NEXT: call void @p(ptr noundef @.str.10, i32 noundef [[TMP2]]) #[[ATTR4]]
// CHECK-NEXT: ret void
@@ -208,7 +208,7 @@ void test_float_isnan(float f) {
// CHECK-NEXT: [[D_ADDR:%.*]] = alloca double, align 8
// CHECK-NEXT: store double [[D:%.*]], ptr [[D_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load double, ptr [[D_ADDR]], align 8
-// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[TMP0]], i32 3) #[[ATTR4]]
+// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[TMP0]], /* (nan) */ i32 3) #[[ATTR4]]
// CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP1]] to i32
// CHECK-NEXT: call void @p(ptr noundef @.str.11, i32 noundef [[TMP2]]) #[[ATTR4]]
// CHECK-NEXT: ret void
@@ -224,7 +224,7 @@ void test_double_isnan(double d) {
// CHECK-NEXT: [[D_ADDR:%.*]] = alloca double, align 8
// CHECK-NEXT: store double [[D:%.*]], ptr [[D_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load double, ptr [[D_ADDR]], align 8
-// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[TMP0]], i32 264) #[[ATTR4]]
+// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[TMP0]], /* (norm) */ i32 264) #[[ATTR4]]
// CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP1]] to i32
// CHECK-NEXT: call void @p(ptr noundef @.str.12, i32 noundef [[TMP2]]) #[[ATTR4]]
// CHECK-NEXT: ret void
diff --git a/clang/test/Headers/amdgcn-openmp-device-math-complex.c b/clang/test/Headers/amdgcn-openmp-device-math-complex.c
index b347cf4716df2..7b4dd9853a066 100644
--- a/clang/test/Headers/amdgcn-openmp-device-math-complex.c
+++ b/clang/test/Headers/amdgcn-openmp-device-math-complex.c
@@ -15,15 +15,15 @@ void test_complex_f64(double _Complex a) {
// CHECK: define weak {{.*}} @__divdc3
// CHECK-DAG: call double @llvm.fabs.f64(
-// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, i32 3)
-// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, i32 504)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, /* (nan) */ i32 3)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, /* (zero sub norm) */ i32 504)
// CHECK-DAG: call double @llvm.copysign.f64(
// CHECK-DAG: call double @llvm.ldexp.f64.i32(
// CHECK-DAG: call { double, i32 } @llvm.frexp.f64.i32
// CHECK: define weak {{.*}} @__muldc3
-// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, i32 3)
-// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, i32 516)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, /* (nan) */ i32 3)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, /* (inf) */ i32 516)
// CHECK-DAG: call double @llvm.copysign.f64(
void test_complex_f32(float _Complex a) {
@@ -38,13 +38,13 @@ void test_complex_f32(float _Complex a) {
// CHECK: define weak {{.*}} @__divsc3
// CHECK-DAG: call float @llvm.fabs.f32(
-// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, i32 3)
-// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, i32 516)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, /* (nan) */ i32 3)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, /* (inf) */ i32 516)
// CHECK-DAG: call float @llvm.copysign.f32(
// CHECK-DAG: call float @llvm.ldexp.f32.i32(
// CHECK-DAG: call { float, i32 } @llvm.frexp.f32.i32
// CHECK: define weak {{.*}} @__mulsc3
-// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, i32 3)
-// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, i32 516)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, /* (nan) */ i32 3)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, /* (inf) */ i32 516)
// CHECK-DAG: call float @llvm.copysign.f32(
diff --git a/clang/test/Headers/amdgcn-openmp-device-math-complex.cpp b/clang/test/Headers/amdgcn-openmp-device-math-complex.cpp
index bba1794001059..b2f83a3607956 100644
--- a/clang/test/Headers/amdgcn-openmp-device-math-complex.cpp
+++ b/clang/test/Headers/amdgcn-openmp-device-math-complex.cpp
@@ -6,27 +6,27 @@
#include <complex>
// CHECK: define weak {{.*}} @__muldc3
-// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, i32 3)
-// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, i32 516)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, /* (nan) */ i32 3)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, /* (inf) */ i32 516)
// CHECK: define weak {{.*}} @__mulsc3
-// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, i32 3)
-// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, i32 516)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, /* (nan) */ i32 3)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, /* (inf) */ i32 516)
// CHECK-DAG: call float @llvm.copysign.f32(
// CHECK: define weak {{.*}} @__divdc3
-// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, i32 3)
-// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, i32 504)
-// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, i32 516)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, /* (nan) */ i32 3)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, /* (zero sub norm) */ i32 504)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, /* (inf) */ i32 516)
// CHECK-DAG: call double @llvm.copysign.f64(
// CHECK-DAG: call double @llvm.ldexp.f64.i32(
// CHECK-DAG: call double @llvm.fabs.f64(
// CHECK-DAG: call { double, i32 } @llvm.frexp.f64.i32
// CHECK: define weak {{.*}} @__divsc3
-// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, i32 3)
-// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, i32 504)
-// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, i32 516)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, /* (nan) */ i32 3)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, /* (zero sub norm) */ i32 504)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, /* (inf) */ i32 516)
// CHECK-DAG: call float @llvm.copysign.f32(
// CHECK-DAG: call float @llvm.ldexp.f32.i32(
// CHECK-DAG: call float @llvm.fabs.f32(
diff --git a/clang/test/Headers/hip-header.hip b/clang/test/Headers/hip-header.hip
index b4bd32dc9e3b0..4b92ada52066f 100644
--- a/clang/test/Headers/hip-header.hip
+++ b/clang/test/Headers/hip-header.hip
@@ -149,12 +149,12 @@ __device__ double test_isnan() {
double d = 5.0;
float f = 5.0;
- // AMD_INT_RETURN: call noundef i1 @llvm.is.fpclass.f32(float {{.*}}, i32 3)
- // AMD_BOOL_RETURN: call noundef i1 @llvm.is.fpclass.f32(float {{.*}}, i32 3)
+ // AMD_INT_RETURN: call noundef i1 @llvm.is.fpclass.f32(float {{.*}}, /* (nan) */ i32 3)
+ // AMD_BOOL_RETURN: call noundef i1 @llvm.is.fpclass.f32(float {{.*}}, /* (nan) */ i32 3)
r += isnan(f);
- // AMD_INT_RETURN: call noundef i1 @llvm.is.fpclass.f64(double {{.*}}, i32 3)
- // AMD_BOOL_RETURN: call noundef i1 @llvm.is.fpclass.f64(double {{.*}}, i32 3)
+ // AMD_INT_RETURN: call noundef i1 @llvm.is.fpclass.f64(double {{.*}}, /* (nan) */ i32 3)
+ // AMD_BOOL_RETURN: call noundef i1 @llvm.is.fpclass.f64(double {{.*}}, /* (nan) */ i32 3)
r += isnan(d);
return r ;
diff --git a/clang/test/Headers/nvptx_device_math_complex.c b/clang/test/Headers/nvptx_device_math_complex.c
index b8bf07ed385e3..ab073ec8fff2c 100644
--- a/clang/test/Headers/nvptx_device_math_complex.c
+++ b/clang/test/Headers/nvptx_device_math_complex.c
@@ -12,9 +12,9 @@
#endif
// CHECK: define weak {{.*}} @__divsc3
-// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, i32 3)
-// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, i32 516)
-// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, i32 504)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, /* (nan) */ i32 3)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, /* (inf) */ i32 516)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, /* (zero sub norm) */ i32 504)
// CHECK-DAG: call float @llvm.copysign.f32(
// CHECK-DAG: call float @__nv_scalbnf(
// CHECK-DAG: call nsz float @llvm.fabs.f32(
@@ -23,14 +23,14 @@
// CHECK-DAG: call float @__nv_logbf(
// CHECK: define weak {{.*}} @__mulsc3
-// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, i32 3)
-// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, i32 516)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, /* (nan) */ i32 3)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, /* (inf) */ i32 516)
// CHECK-DAG: call float @llvm.copysign.f32(
// CHECK: define weak {{.*}} @__divdc3
-// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, i32 3)
-// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, i32 504)
-// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, i32 516)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, /* (nan) */ i32 3)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, /* (zero sub norm) */ i32 504)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, /* (inf) */ i32 516)
// CHECK-DAG: call double @llvm.copysign.f64(
// CHECK-DAG: call double @__nv_scalbn(
// CHECK-DAG: call nsz double @llvm.fabs.f64(
@@ -39,8 +39,8 @@
// CHECK-DAG: call double @__nv_logb(
// CHECK: define weak {{.*}} @__muldc3
-// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, i32 3)
-// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, i32 516)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, /* (nan) */ i32 3)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, /* (inf) */ i32 516)
// CHECK-DAG: call double @llvm.copysign.f64(
void test_scmplx(float _Complex a) {
diff --git a/clang/test/Headers/nvptx_device_math_complex.cpp b/clang/test/Headers/nvptx_device_math_complex.cpp
index c8a924997c2b8..7299b795a557f 100644
--- a/clang/test/Headers/nvptx_device_math_complex.cpp
+++ b/clang/test/Headers/nvptx_device_math_complex.cpp
@@ -7,19 +7,19 @@
#include <complex>
// CHECK: define weak {{.*}} @__muldc3
-// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, i32 3)
-// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, i32 516)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, /* (nan) */ i32 3)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, /* (inf) */ i32 516)
// CHECK-DAG: call double @llvm.copysign.f64(
// CHECK: define weak {{.*}} @__mulsc3
-// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, i32 3)
-// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, i32 516)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, /* (nan) */ i32 3)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, /* (inf) */ i32 516)
// CHECK-DAG: call float @llvm.copysign.f32(
// CHECK: define weak {{.*}} @__divdc3
-// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, i32 3)
-// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, i32 516)
-// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, i32 504)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, /* (nan) */ i32 3)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, /* (inf) */ i32 516)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f64(double %{{.+}}, /* (zero sub norm) */ i32 504)
// CHECK-DAG: call double @llvm.copysign.f64(
// CHECK-DAG: call double @__nv_scalbn(
// CHECK-DAG: call nsz double @llvm.fabs.f64(
@@ -28,9 +28,9 @@
// CHECK-DAG: call double @__nv_logb(
// CHECK: define weak {{.*}} @__divsc3
-// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, i32 3)
-// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, i32 516)
-// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, i32 504)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, /* (nan) */ i32 3)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, /* (inf) */ i32 516)
+// CHECK-DAG: call i1 @llvm.is.fpclass.f32(float %{{.+}}, /* (zero sub norm) */ i32 504)
// CHECK-DAG: call float @llvm.copysign.f32(
// CHECK-DAG: call float @__nv_scalbnf(
// CHECK-DAG: call nsz float @llvm.fabs.f32(
diff --git a/clang/test/Headers/openmp_device_math_isnan.cpp b/clang/test/Headers/openmp_device_math_isnan.cpp
index bc885982e84f5..abbe842a6b9ad 100644
--- a/clang/test/Headers/openmp_device_math_isnan.cpp
+++ b/clang/test/Headers/openmp_device_math_isnan.cpp
@@ -28,21 +28,21 @@
double math(float f, double d) {
double r = 0;
// INT_RETURN: call noundef i32 @__nv_isnanf(float
- // AMD_INT_RETURN_SAFE: call i1 @llvm.is.fpclass.f32(float{{.*}}, i32 3)
+ // AMD_INT_RETURN_SAFE: call i1 @llvm.is.fpclass.f32(float{{.*}}, /* (nan) */ i32 3)
// AMD_INT_RETURN_FAST: sitofp fast i32 {{.*}} to double
// SPIRV_INT_RETURN: call spir_func noundef i32 @_Z5isnanf(float
// BOOL_RETURN: call noundef i32 @__nv_isnanf(float
// SPIRV_BOOL_RETURN: call spir_func noundef zeroext i1 @_Z5isnanf(float
- // AMD_BOOL_RETURN_SAFE: call i1 @llvm.is.fpclass.f32(float{{.*}}, i32 3)
+ // AMD_BOOL_RETURN_SAFE: call i1 @llvm.is.fpclass.f32(float{{.*}}, /* (nan) */ i32 3)
// AMD_BOOL_RETURN_FAST: icmp ne i32 {{.*}}, 0
r += std::isnan(f);
// INT_RETURN: call noundef i32 @__nv_isnand(double
// SPIRV_INT_RETURN: call spir_func noundef i32 @_Z5isnand(double
- // AMD_INT_RETURN_SAFE: call i1 @llvm.is.fpclass.f64(double{{.*}}, i32 3)
+ // AMD_INT_RETURN_SAFE: call i1 @llvm.is.fpclass.f64(double{{.*}}, /* (nan) */ i32 3)
// AMD_INT_RETURN_FAST: sitofp fast i32 {{.*}} to double
// BOOL_RETURN: call noundef i32 @__nv_isnand(double
// SPIRV_BOOL_RETURN: call spir_func noundef zeroext i1 @_Z5isnand(double
- // AMD_BOOL_RETURN_SAFE: call i1 @llvm.is.fpclass.f64(double{{.*}}, i32 3)
+ // AMD_BOOL_RETURN_SAFE: call i1 @llvm.is.fpclass.f64(double{{.*}}, /* (nan) */ i32 3)
// AMD_BOOL_RETURN_FAST: icmp ne i32 {{.*}}, 0
r += std::isnan(d);
return r;
diff --git a/llvm/include/llvm/IR/Intrinsics.h b/llvm/include/llvm/IR/Intrinsics.h
index 2f9239aa7b77a..a4799751832bf 100644
--- a/llvm/include/llvm/IR/Intrinsics.h
+++ b/llvm/include/llvm/IR/Intrinsics.h
@@ -325,6 +325,8 @@ LLVM_ABI Intrinsic::ID getDeinterleaveIntrinsicID(unsigned Factor);
LLVM_ABI void printImmArg(ID IID, unsigned ArgIdx, raw_ostream &OS,
const Constant *ImmArgVal);
+LLVM_ABI void printFPClassMask(raw_ostream &OS, const Constant *ImmArgVal);
+
} // namespace Intrinsic
} // namespace llvm
diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td
index ec30fe833e44a..37c9c783465d6 100644
--- a/llvm/include/llvm/IR/Intrinsics.td
+++ b/llvm/include/llvm/IR/Intrinsics.td
@@ -1363,7 +1363,9 @@ def int_is_fpclass
: DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
[llvm_anyfloat_ty, llvm_i32_ty],
[IntrNoMem, IntrSpeculatable,
- IntrNoCreateUndefOrPoison, ImmArg<ArgIndex<1>>]>;
+ IntrNoCreateUndefOrPoison, ImmArg<ArgIndex<1>>,
+ ArgInfo<ArgIndex<1>,
+ [ImmArgPrinter<"printFPClassMask">]>]>;
//===--------------- Constrained Floating Point Intrinsics ----------------===//
//
diff --git a/llvm/lib/IR/Intrinsics.cpp b/llvm/lib/IR/Intrinsics.cpp
index 6ddfc18c56501..266af8e06a230 100644
--- a/llvm/lib/IR/Intrinsics.cpp
+++ b/llvm/lib/IR/Intrinsics.cpp
@@ -1472,6 +1472,12 @@ Intrinsic::ID Intrinsic::getDeinterleaveIntrinsicID(unsigned Factor) {
return InterleaveIntrinsics[Factor - 2].Deinterleave;
}
+LLVM_ABI void Intrinsic::printFPClassMask(raw_ostream &OS,
+ const Constant *ImmArgVal) {
+ uint64_t Val = cast<ConstantInt>(ImmArgVal)->getZExtValue();
+ OS << static_cast<FPClassTest>(Val);
+}
+
#define GET_INTRINSIC_PRETTY_PRINT_ARGUMENTS
#include "llvm/IR/IntrinsicImpl.inc"
diff --git a/llvm/test/Analysis/CostModel/AMDGPU/is_fpclass.ll b/llvm/test/Analysis/CostModel/AMDGPU/is_fpclass.ll
index 657ffe9e421c4..75dcae1f9cf3a 100644
--- a/llvm/test/Analysis/CostModel/AMDGPU/is_fpclass.ll
+++ b/llvm/test/Analysis/CostModel/AMDGPU/is_fpclass.ll
@@ -4,25 +4,25 @@
define void @is_fpclass_f16() {
; ALL-LABEL: 'is_fpclass_f16'
-; ALL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %f16 = call i1 @llvm.is.fpclass.f16(half undef, i32 0)
-; ALL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2f16 = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> undef, i32 0)
-; ALL-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3f16 = call <3 x i1> @llvm.is.fpclass.v3f16(<3 x half> undef, i32 0)
-; ALL-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4f16 = call <4 x i1> @llvm.is.fpclass.v4f16(<4 x half> undef, i32 0)
-; ALL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %v5f16 = call <5 x i1> @llvm.is.fpclass.v5f16(<5 x half> undef, i32 0)
-; ALL-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v8f16 = call <8 x i1> @llvm.is.fpclass.v8f16(<8 x half> undef, i32 0)
-; ALL-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v16f16 = call <16 x i1> @llvm.is.fpclass.v16f16(<16 x half> undef, i32 0)
-; ALL-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v17f16 = call <17 x i1> @llvm.is.fpclass.v17f16(<17 x half> undef, i32 0)
+; ALL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %f16 = call i1 @llvm.is.fpclass.f16(half undef, /* (none) */ i32 0)
+; ALL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2f16 = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> undef, /* (none) */ i32 0)
+; ALL-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3f16 = call <3 x i1> @llvm.is.fpclass.v3f16(<3 x half> undef, /* (none) */ i32 0)
+; ALL-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4f16 = call <4 x i1> @llvm.is.fpclass.v4f16(<4 x half> undef, /* (none) */ i32 0)
+; ALL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %v5f16 = call <5 x i1> @llvm.is.fpclass.v5f16(<5 x half> undef, /* (none) */ i32 0)
+; ALL-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v8f16 = call <8 x i1> @llvm.is.fpclass.v8f16(<8 x half> undef, /* (none) */ i32 0)
+; ALL-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v16f16 = call <16 x i1> @llvm.is.fpclass.v16f16(<16 x half> undef, /* (none) */ i32 0)
+; ALL-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v17f16 = call <17 x i1> @llvm.is.fpclass.v17f16(<17 x half> undef, /* (none) */ i32 0)
; ALL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
;
; ALL-SIZE-LABEL: 'is_fpclass_f16'
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %f16 = call i1 @llvm.is.fpclass.f16(half undef, i32 0)
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2f16 = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> undef, i32 0)
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3f16 = call <3 x i1> @llvm.is.fpclass.v3f16(<3 x half> undef, i32 0)
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4f16 = call <4 x i1> @llvm.is.fpclass.v4f16(<4 x half> undef, i32 0)
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %v5f16 = call <5 x i1> @llvm.is.fpclass.v5f16(<5 x half> undef, i32 0)
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v8f16 = call <8 x i1> @llvm.is.fpclass.v8f16(<8 x half> undef, i32 0)
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v16f16 = call <16 x i1> @llvm.is.fpclass.v16f16(<16 x half> undef, i32 0)
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v17f16 = call <17 x i1> @llvm.is.fpclass.v17f16(<17 x half> undef, i32 0)
+; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %f16 = call i1 @llvm.is.fpclass.f16(half undef, /* (none) */ i32 0)
+; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2f16 = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> undef, /* (none) */ i32 0)
+; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3f16 = call <3 x i1> @llvm.is.fpclass.v3f16(<3 x half> undef, /* (none) */ i32 0)
+; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4f16 = call <4 x i1> @llvm.is.fpclass.v4f16(<4 x half> undef, /* (none) */ i32 0)
+; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %v5f16 = call <5 x i1> @llvm.is.fpclass.v5f16(<5 x half> undef, /* (none) */ i32 0)
+; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v8f16 = call <8 x i1> @llvm.is.fpclass.v8f16(<8 x half> undef, /* (none) */ i32 0)
+; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v16f16 = call <16 x i1> @llvm.is.fpclass.v16f16(<16 x half> undef, /* (none) */ i32 0)
+; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v17f16 = call <17 x i1> @llvm.is.fpclass.v17f16(<17 x half> undef, /* (none) */ i32 0)
; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%f16 = call i1 @llvm.is.fpclass.f16(half undef, i32 0)
@@ -38,25 +38,25 @@ define void @is_fpclass_f16() {
define void @is_fpclass_bf16() {
; ALL-LABEL: 'is_fpclass_bf16'
-; ALL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bf16 = call i1 @llvm.is.fpclass.bf16(bfloat undef, i32 0)
-; ALL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2bf16 = call <2 x i1> @llvm.is.fpclass.v2bf16(<2 x bfloat> undef, i32 0)
-; ALL-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3bf16 = call <3 x i1> @llvm.is.fpclass.v3bf16(<3 x bfloat> undef, i32 0)
-; ALL-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4bf16 = call <4 x i1> @llvm.is.fpclass.v4bf16(<4 x bfloat> undef, i32 0)
-; ALL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %v5bf16 = call <5 x i1> @llvm.is.fpclass.v5bf16(<5 x bfloat> undef, i32 0)
-; ALL-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v8bf16 = call <8 x i1> @llvm.is.fpclass.v8bf16(<8 x bfloat> undef, i32 0)
-; ALL-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v16bf16 = call <16 x i1> @llvm.is.fpclass.v16bf16(<16 x bfloat> undef, i32 0)
-; ALL-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v17bf16 = call <17 x i1> @llvm.is.fpclass.v17bf16(<17 x bfloat> undef, i32 0)
+; ALL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bf16 = call i1 @llvm.is.fpclass.bf16(bfloat undef, /* (none) */ i32 0)
+; ALL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2bf16 = call <2 x i1> @llvm.is.fpclass.v2bf16(<2 x bfloat> undef, /* (none) */ i32 0)
+; ALL-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3bf16 = call <3 x i1> @llvm.is.fpclass.v3bf16(<3 x bfloat> undef, /* (none) */ i32 0)
+; ALL-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4bf16 = call <4 x i1> @llvm.is.fpclass.v4bf16(<4 x bfloat> undef, /* (none) */ i32 0)
+; ALL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %v5bf16 = call <5 x i1> @llvm.is.fpclass.v5bf16(<5 x bfloat> undef, /* (none) */ i32 0)
+; ALL-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v8bf16 = call <8 x i1> @llvm.is.fpclass.v8bf16(<8 x bfloat> undef, /* (none) */ i32 0)
+; ALL-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v16bf16 = call <16 x i1> @llvm.is.fpclass.v16bf16(<16 x bfloat> undef, /* (none) */ i32 0)
+; ALL-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v17bf16 = call <17 x i1> @llvm.is.fpclass.v17bf16(<17 x bfloat> undef, /* (none) */ i32 0)
; ALL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
;
; ALL-SIZE-LABEL: 'is_fpclass_bf16'
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bf16 = call i1 @llvm.is.fpclass.bf16(bfloat undef, i32 0)
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2bf16 = call <2 x i1> @llvm.is.fpclass.v2bf16(<2 x bfloat> undef, i32 0)
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3bf16 = call <3 x i1> @llvm.is.fpclass.v3bf16(<3 x bfloat> undef, i32 0)
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4bf16 = call <4 x i1> @llvm.is.fpclass.v4bf16(<4 x bfloat> undef, i32 0)
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %v5bf16 = call <5 x i1> @llvm.is.fpclass.v5bf16(<5 x bfloat> undef, i32 0)
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v8bf16 = call <8 x i1> @llvm.is.fpclass.v8bf16(<8 x bfloat> undef, i32 0)
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v16bf16 = call <16 x i1> @llvm.is.fpclass.v16bf16(<16 x bfloat> undef, i32 0)
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v17bf16 = call <17 x i1> @llvm.is.fpclass.v17bf16(<17 x bfloat> undef, i32 0)
+; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %bf16 = call i1 @llvm.is.fpclass.bf16(bfloat undef, /* (none) */ i32 0)
+; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2bf16 = call <2 x i1> @llvm.is.fpclass.v2bf16(<2 x bfloat> undef, /* (none) */ i32 0)
+; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3bf16 = call <3 x i1> @llvm.is.fpclass.v3bf16(<3 x bfloat> undef, /* (none) */ i32 0)
+; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4bf16 = call <4 x i1> @llvm.is.fpclass.v4bf16(<4 x bfloat> undef, /* (none) */ i32 0)
+; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %v5bf16 = call <5 x i1> @llvm.is.fpclass.v5bf16(<5 x bfloat> undef, /* (none) */ i32 0)
+; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v8bf16 = call <8 x i1> @llvm.is.fpclass.v8bf16(<8 x bfloat> undef, /* (none) */ i32 0)
+; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v16bf16 = call <16 x i1> @llvm.is.fpclass.v16bf16(<16 x bfloat> undef, /* (none) */ i32 0)
+; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v17bf16 = call <17 x i1> @llvm.is.fpclass.v17bf16(<17 x bfloat> undef, /* (none) */ i32 0)
; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%bf16 = call i1 @llvm.is.fpclass.bf16(bfloat undef, i32 0)
@@ -72,25 +72,25 @@ define void @is_fpclass_bf16() {
define void @is_fpclass_f32() {
; ALL-LABEL: 'is_fpclass_f32'
-; ALL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %f32 = call i1 @llvm.is.fpclass.f32(float undef, i32 0)
-; ALL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2f32 = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> undef, i32 0)
-; ALL-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3f32 = call <3 x i1> @llvm.is.fpclass.v3f32(<3 x float> undef, i32 0)
-; ALL-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4f32 = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> undef, i32 0)
-; ALL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %v5f32 = call <5 x i1> @llvm.is.fpclass.v5f32(<5 x float> undef, i32 0)
-; ALL-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v8f32 = call <8 x i1> @llvm.is.fpclass.v8f32(<8 x float> undef, i32 0)
-; ALL-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v16f32 = call <16 x i1> @llvm.is.fpclass.v16f32(<16 x float> undef, i32 0)
-; ALL-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v17f32 = call <17 x i1> @llvm.is.fpclass.v17f32(<17 x float> undef, i32 0)
+; ALL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %f32 = call i1 @llvm.is.fpclass.f32(float undef, /* (none) */ i32 0)
+; ALL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2f32 = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> undef, /* (none) */ i32 0)
+; ALL-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3f32 = call <3 x i1> @llvm.is.fpclass.v3f32(<3 x float> undef, /* (none) */ i32 0)
+; ALL-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4f32 = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> undef, /* (none) */ i32 0)
+; ALL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %v5f32 = call <5 x i1> @llvm.is.fpclass.v5f32(<5 x float> undef, /* (none) */ i32 0)
+; ALL-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v8f32 = call <8 x i1> @llvm.is.fpclass.v8f32(<8 x float> undef, /* (none) */ i32 0)
+; ALL-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v16f32 = call <16 x i1> @llvm.is.fpclass.v16f32(<16 x float> undef, /* (none) */ i32 0)
+; ALL-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v17f32 = call <17 x i1> @llvm.is.fpclass.v17f32(<17 x float> undef, /* (none) */ i32 0)
; ALL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
;
; ALL-SIZE-LABEL: 'is_fpclass_f32'
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %f32 = call i1 @llvm.is.fpclass.f32(float undef, i32 0)
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2f32 = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> undef, i32 0)
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3f32 = call <3 x i1> @llvm.is.fpclass.v3f32(<3 x float> undef, i32 0)
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4f32 = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> undef, i32 0)
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %v5f32 = call <5 x i1> @llvm.is.fpclass.v5f32(<5 x float> undef, i32 0)
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v8f32 = call <8 x i1> @llvm.is.fpclass.v8f32(<8 x float> undef, i32 0)
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v16f32 = call <16 x i1> @llvm.is.fpclass.v16f32(<16 x float> undef, i32 0)
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v17f32 = call <17 x i1> @llvm.is.fpclass.v17f32(<17 x float> undef, i32 0)
+; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %f32 = call i1 @llvm.is.fpclass.f32(float undef, /* (none) */ i32 0)
+; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2f32 = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> undef, /* (none) */ i32 0)
+; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3f32 = call <3 x i1> @llvm.is.fpclass.v3f32(<3 x float> undef, /* (none) */ i32 0)
+; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4f32 = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> undef, /* (none) */ i32 0)
+; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %v5f32 = call <5 x i1> @llvm.is.fpclass.v5f32(<5 x float> undef, /* (none) */ i32 0)
+; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v8f32 = call <8 x i1> @llvm.is.fpclass.v8f32(<8 x float> undef, /* (none) */ i32 0)
+; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v16f32 = call <16 x i1> @llvm.is.fpclass.v16f32(<16 x float> undef, /* (none) */ i32 0)
+; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v17f32 = call <17 x i1> @llvm.is.fpclass.v17f32(<17 x float> undef, /* (none) */ i32 0)
; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%f32 = call i1 @llvm.is.fpclass.f32(float undef, i32 0)
@@ -106,25 +106,25 @@ define void @is_fpclass_f32() {
define void @is_fpclass_f64() {
; ALL-LABEL: 'is_fpclass_f64'
-; ALL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %f64 = call i1 @llvm.is.fpclass.f64(double undef, i32 0)
-; ALL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2f64 = call <2 x i1> @llvm.is.fpclass.v2f64(<2 x double> undef, i32 0)
-; ALL-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3f64 = call <3 x i1> @llvm.is.fpclass.v3f64(<3 x double> undef, i32 0)
-; ALL-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4f64 = call <4 x i1> @llvm.is.fpclass.v4f64(<4 x double> undef, i32 0)
-; ALL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %v5f64 = call <5 x i1> @llvm.is.fpclass.v5f64(<5 x double> undef, i32 0)
-; ALL-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v8f64 = call <8 x i1> @llvm.is.fpclass.v8f64(<8 x double> undef, i32 0)
-; ALL-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v16f64 = call <16 x i1> @llvm.is.fpclass.v16f64(<16 x double> undef, i32 0)
-; ALL-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v17f64 = call <17 x i1> @llvm.is.fpclass.v17f64(<17 x double> undef, i32 0)
+; ALL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %f64 = call i1 @llvm.is.fpclass.f64(double undef, /* (none) */ i32 0)
+; ALL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2f64 = call <2 x i1> @llvm.is.fpclass.v2f64(<2 x double> undef, /* (none) */ i32 0)
+; ALL-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3f64 = call <3 x i1> @llvm.is.fpclass.v3f64(<3 x double> undef, /* (none) */ i32 0)
+; ALL-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4f64 = call <4 x i1> @llvm.is.fpclass.v4f64(<4 x double> undef, /* (none) */ i32 0)
+; ALL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %v5f64 = call <5 x i1> @llvm.is.fpclass.v5f64(<5 x double> undef, /* (none) */ i32 0)
+; ALL-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v8f64 = call <8 x i1> @llvm.is.fpclass.v8f64(<8 x double> undef, /* (none) */ i32 0)
+; ALL-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v16f64 = call <16 x i1> @llvm.is.fpclass.v16f64(<16 x double> undef, /* (none) */ i32 0)
+; ALL-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v17f64 = call <17 x i1> @llvm.is.fpclass.v17f64(<17 x double> undef, /* (none) */ i32 0)
; ALL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
;
; ALL-SIZE-LABEL: 'is_fpclass_f64'
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %f64 = call i1 @llvm.is.fpclass.f64(double undef, i32 0)
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2f64 = call <2 x i1> @llvm.is.fpclass.v2f64(<2 x double> undef, i32 0)
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3f64 = call <3 x i1> @llvm.is.fpclass.v3f64(<3 x double> undef, i32 0)
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4f64 = call <4 x i1> @llvm.is.fpclass.v4f64(<4 x double> undef, i32 0)
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %v5f64 = call <5 x i1> @llvm.is.fpclass.v5f64(<5 x double> undef, i32 0)
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v8f64 = call <8 x i1> @llvm.is.fpclass.v8f64(<8 x double> undef, i32 0)
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v16f64 = call <16 x i1> @llvm.is.fpclass.v16f64(<16 x double> undef, i32 0)
-; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v17f64 = call <17 x i1> @llvm.is.fpclass.v17f64(<17 x double> undef, i32 0)
+; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %f64 = call i1 @llvm.is.fpclass.f64(double undef, /* (none) */ i32 0)
+; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2f64 = call <2 x i1> @llvm.is.fpclass.v2f64(<2 x double> undef, /* (none) */ i32 0)
+; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v3f64 = call <3 x i1> @llvm.is.fpclass.v3f64(<3 x double> undef, /* (none) */ i32 0)
+; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4f64 = call <4 x i1> @llvm.is.fpclass.v4f64(<4 x double> undef, /* (none) */ i32 0)
+; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %v5f64 = call <5 x i1> @llvm.is.fpclass.v5f64(<5 x double> undef, /* (none) */ i32 0)
+; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v8f64 = call <8 x i1> @llvm.is.fpclass.v8f64(<8 x double> undef, /* (none) */ i32 0)
+; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v16f64 = call <16 x i1> @llvm.is.fpclass.v16f64(<16 x double> undef, /* (none) */ i32 0)
+; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v17f64 = call <17 x i1> @llvm.is.fpclass.v17f64(<17 x double> undef, /* (none) */ i32 0)
; ALL-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
;
%f64 = call i1 @llvm.is.fpclass.f64(double undef, i32 0)
diff --git a/llvm/test/Assembler/print-formatted.ll b/llvm/test/Assembler/print-formatted.ll
new file mode 100644
index 0000000000000..ec431a3b3961b
--- /dev/null
+++ b/llvm/test/Assembler/print-formatted.ll
@@ -0,0 +1,51 @@
+; RUN: llvm-as < %s | llvm-dis | FileCheck %s
+
+define i1 @print_is_fpclass(float %x) {
+ %1 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1)
+ %2 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 2)
+ %3 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 4)
+ %4 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 8)
+ %5 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 16)
+ %6 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 32)
+ %7 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 64)
+ %8 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 128)
+ %9 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 256)
+ %10 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 512)
+ %11 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 3)
+ %12 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 96)
+ %13 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 144)
+ %14 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 264)
+ %15 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 516)
+ %16 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 56)
+ %17 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 448)
+ %18 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 960)
+ %19 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 60)
+ %20 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 666)
+ %21 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 0)
+ %22 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1023)
+ ret i1 %20
+}
+
+; CHECK-LABEL: print_is_fpclass(float %x) {
+; CHECK: call i1 @llvm.is.fpclass.f32(float %x, /* (snan) */ i32 1)
+; CHECK: call i1 @llvm.is.fpclass.f32(float %x, /* (qnan) */ i32 2)
+; CHECK: call i1 @llvm.is.fpclass.f32(float %x, /* (ninf) */ i32 4)
+; CHECK: call i1 @llvm.is.fpclass.f32(float %x, /* (nnorm) */ i32 8)
+; CHECK: call i1 @llvm.is.fpclass.f32(float %x, /* (nsub) */ i32 16)
+; CHECK: call i1 @llvm.is.fpclass.f32(float %x, /* (nzero) */ i32 32)
+; CHECK: call i1 @llvm.is.fpclass.f32(float %x, /* (pzero) */ i32 64)
+; CHECK: call i1 @llvm.is.fpclass.f32(float %x, /* (psub) */ i32 128)
+; CHECK: call i1 @llvm.is.fpclass.f32(float %x, /* (pnorm) */ i32 256)
+; CHECK: call i1 @llvm.is.fpclass.f32(float %x, /* (pinf) */ i32 512)
+; CHECK: call i1 @llvm.is.fpclass.f32(float %x, /* (nan) */ i32 3)
+; CHECK: call i1 @llvm.is.fpclass.f32(float %x, /* (zero) */ i32 96)
+; CHECK: call i1 @llvm.is.fpclass.f32(float %x, /* (sub) */ i32 144)
+; CHECK: call i1 @llvm.is.fpclass.f32(float %x, /* (norm) */ i32 264)
+; CHECK: call i1 @llvm.is.fpclass.f32(float %x, /* (inf) */ i32 516)
+; CHECK: call i1 @llvm.is.fpclass.f32(float %x, /* (nzero nsub nnorm) */ i32 56)
+; CHECK: call i1 @llvm.is.fpclass.f32(float %x, /* (pzero psub pnorm) */ i32 448)
+; CHECK: call i1 @llvm.is.fpclass.f32(float %x, /* (pinf pzero psub pnorm) */ i32 960)
+; CHECK: call i1 @llvm.is.fpclass.f32(float %x, /* (ninf nzero nsub nnorm) */ i32 60)
+; CHECK: call i1 @llvm.is.fpclass.f32(float %x, /* (qnan pinf sub nnorm) */ i32 666)
+; CHECK: call i1 @llvm.is.fpclass.f32(float %x, /* (none) */ i32 0)
+; CHECK: call i1 @llvm.is.fpclass.f32(float %x, /* (all) */ i32 1023)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.f64.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.f64.ll
index b5a419f5969fe..de38916c22852 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.f64.ll
@@ -5,7 +5,7 @@ define double @rsq_f64(double %x) {
; CHECK-LABEL: define double @rsq_f64(
; CHECK-SAME: double [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call contract double @llvm.amdgcn.rsq.f64(double [[X]])
-; CHECK-NEXT: [[TMP2:%.*]] = call i1 @llvm.is.fpclass.f64(double [[X]], i32 608)
+; CHECK-NEXT: [[TMP2:%.*]] = call i1 @llvm.is.fpclass.f64(double [[X]], /* (pinf zero) */ i32 608)
; CHECK-NEXT: [[TMP3:%.*]] = select contract i1 [[TMP2]], double [[TMP1]], double [[X]]
; CHECK-NEXT: [[TMP4:%.*]] = fneg contract double [[TMP1]]
; CHECK-NEXT: [[TMP5:%.*]] = fmul contract double [[TMP3]], [[TMP4]]
@@ -24,7 +24,7 @@ define double @neg_rsq_f64(double %x) {
; CHECK-LABEL: define double @neg_rsq_f64(
; CHECK-SAME: double [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call contract double @llvm.amdgcn.rsq.f64(double [[X]])
-; CHECK-NEXT: [[TMP2:%.*]] = call i1 @llvm.is.fpclass.f64(double [[X]], i32 608)
+; CHECK-NEXT: [[TMP2:%.*]] = call i1 @llvm.is.fpclass.f64(double [[X]], /* (pinf zero) */ i32 608)
; CHECK-NEXT: [[TMP3:%.*]] = select contract i1 [[TMP2]], double [[TMP1]], double [[X]]
; CHECK-NEXT: [[TMP4:%.*]] = fneg contract double [[TMP1]]
; CHECK-NEXT: [[TMP5:%.*]] = fmul contract double [[TMP3]], [[TMP4]]
@@ -43,7 +43,7 @@ define double @rsq_f64_nnan(double %x) {
; CHECK-LABEL: define double @rsq_f64_nnan(
; CHECK-SAME: double [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call nnan contract double @llvm.amdgcn.rsq.f64(double [[X]])
-; CHECK-NEXT: [[TMP2:%.*]] = call i1 @llvm.is.fpclass.f64(double [[X]], i32 608)
+; CHECK-NEXT: [[TMP2:%.*]] = call i1 @llvm.is.fpclass.f64(double [[X]], /* (pinf zero) */ i32 608)
; CHECK-NEXT: [[TMP3:%.*]] = select nnan contract i1 [[TMP2]], double [[TMP1]], double [[X]]
; CHECK-NEXT: [[TMP4:%.*]] = fneg nnan contract double [[TMP1]]
; CHECK-NEXT: [[TMP5:%.*]] = fmul nnan contract double [[TMP3]], [[TMP4]]
@@ -62,7 +62,7 @@ define double @neg_rsq_f64_nnan(double %x) {
; CHECK-LABEL: define double @neg_rsq_f64_nnan(
; CHECK-SAME: double [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call nnan contract double @llvm.amdgcn.rsq.f64(double [[X]])
-; CHECK-NEXT: [[TMP2:%.*]] = call i1 @llvm.is.fpclass.f64(double [[X]], i32 608)
+; CHECK-NEXT: [[TMP2:%.*]] = call i1 @llvm.is.fpclass.f64(double [[X]], /* (pinf zero) */ i32 608)
; CHECK-NEXT: [[TMP3:%.*]] = select nnan contract i1 [[TMP2]], double [[TMP1]], double [[X]]
; CHECK-NEXT: [[TMP4:%.*]] = fneg nnan contract double [[TMP1]]
; CHECK-NEXT: [[TMP5:%.*]] = fmul nnan contract double [[TMP3]], [[TMP4]]
@@ -190,7 +190,7 @@ define <2 x double> @rsq_v2f64(<2 x double> %x) {
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x double> [[X]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[X]], i64 1
; CHECK-NEXT: [[TMP5:%.*]] = call contract double @llvm.amdgcn.rsq.f64(double [[TMP3]])
-; CHECK-NEXT: [[TMP6:%.*]] = call i1 @llvm.is.fpclass.f64(double [[TMP3]], i32 608)
+; CHECK-NEXT: [[TMP6:%.*]] = call i1 @llvm.is.fpclass.f64(double [[TMP3]], /* (pinf zero) */ i32 608)
; CHECK-NEXT: [[TMP7:%.*]] = select contract i1 [[TMP6]], double [[TMP5]], double [[TMP3]]
; CHECK-NEXT: [[TMP8:%.*]] = fneg contract double [[TMP5]]
; CHECK-NEXT: [[TMP9:%.*]] = fmul contract double [[TMP7]], [[TMP8]]
@@ -199,7 +199,7 @@ define <2 x double> @rsq_v2f64(<2 x double> %x) {
; CHECK-NEXT: [[TMP12:%.*]] = call contract double @llvm.fma.f64(double [[TMP10]], double 3.750000e-01, double 5.000000e-01)
; CHECK-NEXT: [[TMP13:%.*]] = call contract double @llvm.fma.f64(double [[TMP11]], double [[TMP12]], double [[TMP5]])
; CHECK-NEXT: [[TMP14:%.*]] = call contract double @llvm.amdgcn.rsq.f64(double [[TMP4]])
-; CHECK-NEXT: [[TMP15:%.*]] = call i1 @llvm.is.fpclass.f64(double [[TMP4]], i32 608)
+; CHECK-NEXT: [[TMP15:%.*]] = call i1 @llvm.is.fpclass.f64(double [[TMP4]], /* (pinf zero) */ i32 608)
; CHECK-NEXT: [[TMP16:%.*]] = select contract i1 [[TMP15]], double [[TMP14]], double [[TMP4]]
; CHECK-NEXT: [[TMP17:%.*]] = fneg contract double [[TMP14]]
; CHECK-NEXT: [[TMP18:%.*]] = fmul contract double [[TMP16]], [[TMP17]]
@@ -225,7 +225,7 @@ define <2 x double> @neg_rsq_v2f64(<2 x double> %x) {
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x double> [[X]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[X]], i64 1
; CHECK-NEXT: [[TMP5:%.*]] = call contract double @llvm.amdgcn.rsq.f64(double [[TMP3]])
-; CHECK-NEXT: [[TMP6:%.*]] = call i1 @llvm.is.fpclass.f64(double [[TMP3]], i32 608)
+; CHECK-NEXT: [[TMP6:%.*]] = call i1 @llvm.is.fpclass.f64(double [[TMP3]], /* (pinf zero) */ i32 608)
; CHECK-NEXT: [[TMP7:%.*]] = select contract i1 [[TMP6]], double [[TMP5]], double [[TMP3]]
; CHECK-NEXT: [[TMP8:%.*]] = fneg contract double [[TMP5]]
; CHECK-NEXT: [[TMP9:%.*]] = fmul contract double [[TMP7]], [[TMP8]]
@@ -234,7 +234,7 @@ define <2 x double> @neg_rsq_v2f64(<2 x double> %x) {
; CHECK-NEXT: [[TMP12:%.*]] = call contract double @llvm.fma.f64(double [[TMP10]], double 3.750000e-01, double 5.000000e-01)
; CHECK-NEXT: [[TMP13:%.*]] = call contract double @llvm.fma.f64(double [[TMP11]], double [[TMP12]], double [[TMP5]])
; CHECK-NEXT: [[TMP14:%.*]] = call contract double @llvm.amdgcn.rsq.f64(double [[TMP4]])
-; CHECK-NEXT: [[TMP15:%.*]] = call i1 @llvm.is.fpclass.f64(double [[TMP4]], i32 608)
+; CHECK-NEXT: [[TMP15:%.*]] = call i1 @llvm.is.fpclass.f64(double [[TMP4]], /* (pinf zero) */ i32 608)
; CHECK-NEXT: [[TMP16:%.*]] = select contract i1 [[TMP15]], double [[TMP14]], double [[TMP4]]
; CHECK-NEXT: [[TMP17:%.*]] = fneg contract double [[TMP14]]
; CHECK-NEXT: [[TMP18:%.*]] = fmul contract double [[TMP16]], [[TMP17]]
@@ -260,7 +260,7 @@ define <2 x double> @mixed_sign_rsq_v2f64(<2 x double> %x) {
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x double> [[X]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[X]], i64 1
; CHECK-NEXT: [[TMP5:%.*]] = call contract double @llvm.amdgcn.rsq.f64(double [[TMP3]])
-; CHECK-NEXT: [[TMP6:%.*]] = call i1 @llvm.is.fpclass.f64(double [[TMP3]], i32 608)
+; CHECK-NEXT: [[TMP6:%.*]] = call i1 @llvm.is.fpclass.f64(double [[TMP3]], /* (pinf zero) */ i32 608)
; CHECK-NEXT: [[TMP7:%.*]] = select contract i1 [[TMP6]], double [[TMP5]], double [[TMP3]]
; CHECK-NEXT: [[TMP8:%.*]] = fneg contract double [[TMP5]]
; CHECK-NEXT: [[TMP9:%.*]] = fmul contract double [[TMP7]], [[TMP8]]
@@ -269,7 +269,7 @@ define <2 x double> @mixed_sign_rsq_v2f64(<2 x double> %x) {
; CHECK-NEXT: [[TMP12:%.*]] = call contract double @llvm.fma.f64(double [[TMP10]], double 3.750000e-01, double 5.000000e-01)
; CHECK-NEXT: [[TMP13:%.*]] = call contract double @llvm.fma.f64(double [[TMP11]], double [[TMP12]], double [[TMP5]])
; CHECK-NEXT: [[TMP14:%.*]] = call contract double @llvm.amdgcn.rsq.f64(double [[TMP4]])
-; CHECK-NEXT: [[TMP15:%.*]] = call i1 @llvm.is.fpclass.f64(double [[TMP4]], i32 608)
+; CHECK-NEXT: [[TMP15:%.*]] = call i1 @llvm.is.fpclass.f64(double [[TMP4]], /* (pinf zero) */ i32 608)
; CHECK-NEXT: [[TMP16:%.*]] = select contract i1 [[TMP15]], double [[TMP14]], double [[TMP4]]
; CHECK-NEXT: [[TMP17:%.*]] = fneg contract double [[TMP14]]
; CHECK-NEXT: [[TMP18:%.*]] = fmul contract double [[TMP16]], [[TMP17]]
@@ -295,7 +295,7 @@ define <2 x double> @rsq_some_elements_v2f64(<2 x double> %x) {
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x double> [[X]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[X]], i64 1
; CHECK-NEXT: [[TMP5:%.*]] = call contract double @llvm.amdgcn.rsq.f64(double [[TMP3]])
-; CHECK-NEXT: [[TMP6:%.*]] = call i1 @llvm.is.fpclass.f64(double [[TMP3]], i32 608)
+; CHECK-NEXT: [[TMP6:%.*]] = call i1 @llvm.is.fpclass.f64(double [[TMP3]], /* (pinf zero) */ i32 608)
; CHECK-NEXT: [[TMP7:%.*]] = select contract i1 [[TMP6]], double [[TMP5]], double [[TMP3]]
; CHECK-NEXT: [[TMP8:%.*]] = fneg contract double [[TMP5]]
; CHECK-NEXT: [[TMP9:%.*]] = fmul contract double [[TMP7]], [[TMP8]]
@@ -638,7 +638,7 @@ define double @rsq_f64_nnan_sqrt(double %x) {
; CHECK-LABEL: define double @rsq_f64_nnan_sqrt(
; CHECK-SAME: double [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call nnan contract double @llvm.amdgcn.rsq.f64(double [[X]])
-; CHECK-NEXT: [[TMP2:%.*]] = call i1 @llvm.is.fpclass.f64(double [[X]], i32 608)
+; CHECK-NEXT: [[TMP2:%.*]] = call i1 @llvm.is.fpclass.f64(double [[X]], /* (pinf zero) */ i32 608)
; CHECK-NEXT: [[TMP3:%.*]] = select nnan contract i1 [[TMP2]], double [[TMP1]], double [[X]]
; CHECK-NEXT: [[TMP4:%.*]] = fneg nnan contract double [[TMP1]]
; CHECK-NEXT: [[TMP5:%.*]] = fmul nnan contract double [[TMP3]], [[TMP4]]
@@ -657,7 +657,7 @@ define double @rsq_f64_nnan_fdiv(double %x) {
; CHECK-LABEL: define double @rsq_f64_nnan_fdiv(
; CHECK-SAME: double [[X:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call nnan contract double @llvm.amdgcn.rsq.f64(double [[X]])
-; CHECK-NEXT: [[TMP2:%.*]] = call i1 @llvm.is.fpclass.f64(double [[X]], i32 608)
+; CHECK-NEXT: [[TMP2:%.*]] = call i1 @llvm.is.fpclass.f64(double [[X]], /* (pinf zero) */ i32 608)
; CHECK-NEXT: [[TMP3:%.*]] = select nnan contract i1 [[TMP2]], double [[TMP1]], double [[X]]
; CHECK-NEXT: [[TMP4:%.*]] = fneg nnan contract double [[TMP1]]
; CHECK-NEXT: [[TMP5:%.*]] = fmul nnan contract double [[TMP3]], [[TMP4]]
diff --git a/llvm/test/Instrumentation/MemorySanitizer/is-fpclass.ll b/llvm/test/Instrumentation/MemorySanitizer/is-fpclass.ll
index e3467d8da3011..9952664c2b3c3 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/is-fpclass.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/is-fpclass.ll
@@ -10,7 +10,7 @@ define i1 @not_isfinite_or_zero_f16(half %x) sanitize_memory {
; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 615)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (nan inf zero) */ i32 615)
; CHECK-NEXT: store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
; CHECK-NEXT: ret i1 [[CLASS]]
;
@@ -24,7 +24,7 @@ define <2 x i1> @not_isfinite_or_zero_v2f16_pos0_neg0_vec(<2 x half> %x) sanitiz
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr @__msan_param_tls, align 8
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i16> [[TMP1]], zeroinitializer
-; CHECK-NEXT: [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], i32 615)
+; CHECK-NEXT: [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], /* (nan inf zero) */ i32 615)
; CHECK-NEXT: store <2 x i1> [[TMP2]], ptr @__msan_retval_tls, align 8
; CHECK-NEXT: ret <2 x i1> [[CLASS]]
;
diff --git a/llvm/test/Transforms/Attributor/nofpclass-select.ll b/llvm/test/Transforms/Attributor/nofpclass-select.ll
index 59a006fd8431b..30fc03103b3ca 100644
--- a/llvm/test/Transforms/Attributor/nofpclass-select.ll
+++ b/llvm/test/Transforms/Attributor/nofpclass-select.ll
@@ -319,7 +319,7 @@ define float @clamp_zero_to_only_inf(float %arg) {
define float @clamp_is_class_subnormal_or_inf_to_nan(float %arg) {
; CHECK-LABEL: define float @clamp_is_class_subnormal_or_inf_to_nan
; CHECK-SAME: (float [[ARG:%.*]]) #[[ATTR1]] {
-; CHECK-NEXT: [[IS_SUBNORMAL_OR_INF:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG]], i32 noundef 660) #[[ATTR2]]
+; CHECK-NEXT: [[IS_SUBNORMAL_OR_INF:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG]], /* (inf sub) */ i32 noundef 660) #[[ATTR2]]
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_SUBNORMAL_OR_INF]], float +qnan, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -331,7 +331,7 @@ define float @clamp_is_class_subnormal_or_inf_to_nan(float %arg) {
define float @clamp_is_class_subnormal_or_inf_to_nan_swap(float %arg) {
; CHECK-LABEL: define float @clamp_is_class_subnormal_or_inf_to_nan_swap
; CHECK-SAME: (float [[ARG:%.*]]) #[[ATTR1]] {
-; CHECK-NEXT: [[NOT_IS_SUBNORMAL_OR_INF:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG]], i32 noundef 363) #[[ATTR2]]
+; CHECK-NEXT: [[NOT_IS_SUBNORMAL_OR_INF:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG]], /* (nan zero norm) */ i32 noundef 363) #[[ATTR2]]
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[NOT_IS_SUBNORMAL_OR_INF]], float [[ARG]], float +qnan
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -343,7 +343,7 @@ define float @clamp_is_class_subnormal_or_inf_to_nan_swap(float %arg) {
define float @ret_select_clamp_nan_to_zero_fpclass(float %arg) {
; CHECK-LABEL: define float @ret_select_clamp_nan_to_zero_fpclass
; CHECK-SAME: (float [[ARG:%.*]]) #[[ATTR1]] {
-; CHECK-NEXT: [[IS_NAN:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG]], i32 noundef 3) #[[ATTR2]]
+; CHECK-NEXT: [[IS_NAN:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG]], /* (nan) */ i32 noundef 3) #[[ATTR2]]
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_NAN]], float 0.000000e+00, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -355,7 +355,7 @@ define float @ret_select_clamp_nan_to_zero_fpclass(float %arg) {
define float @ret_select_clamp_snan_to_zero_fpclass(float %arg) {
; CHECK-LABEL: define float @ret_select_clamp_snan_to_zero_fpclass
; CHECK-SAME: (float [[ARG:%.*]]) #[[ATTR1]] {
-; CHECK-NEXT: [[IS_NAN:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG]], i32 noundef 1) #[[ATTR2]]
+; CHECK-NEXT: [[IS_NAN:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG]], /* (snan) */ i32 noundef 1) #[[ATTR2]]
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_NAN]], float 0.000000e+00, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -367,7 +367,7 @@ define float @ret_select_clamp_snan_to_zero_fpclass(float %arg) {
define float @ret_select_clamp_qnan_to_zero_fpclass(float %arg) {
; CHECK-LABEL: define float @ret_select_clamp_qnan_to_zero_fpclass
; CHECK-SAME: (float [[ARG:%.*]]) #[[ATTR1]] {
-; CHECK-NEXT: [[IS_NAN:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG]], i32 noundef 2) #[[ATTR2]]
+; CHECK-NEXT: [[IS_NAN:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG]], /* (qnan) */ i32 noundef 2) #[[ATTR2]]
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_NAN]], float 0.000000e+00, float [[ARG]]
; CHECK-NEXT: ret float [[SELECT]]
;
@@ -379,7 +379,7 @@ define float @ret_select_clamp_qnan_to_zero_fpclass(float %arg) {
define float @ret_select_clamp_nan_to_zero_fpclass_other_val(float %arg0, float %arg1) {
; CHECK-LABEL: define float @ret_select_clamp_nan_to_zero_fpclass_other_val
; CHECK-SAME: (float [[ARG0:%.*]], float [[ARG1:%.*]]) #[[ATTR1]] {
-; CHECK-NEXT: [[IS_NAN:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG0]], i32 noundef 3) #[[ATTR2]]
+; CHECK-NEXT: [[IS_NAN:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG0]], /* (nan) */ i32 noundef 3) #[[ATTR2]]
; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_NAN]], float 0.000000e+00, float [[ARG1]]
; CHECK-NEXT: ret float [[SELECT]]
;
diff --git a/llvm/test/Transforms/Attributor/nofpclass.ll b/llvm/test/Transforms/Attributor/nofpclass.ll
index 8652049226c75..719896870a479 100644
--- a/llvm/test/Transforms/Attributor/nofpclass.ll
+++ b/llvm/test/Transforms/Attributor/nofpclass.ll
@@ -573,7 +573,7 @@ define float @is_fpclass_assume_arg_return(float %arg) {
; CHECK-LABEL: define nofpclass(nan pinf pzero sub nnorm) float @is_fpclass_assume_arg_return
; CHECK-SAME: (float returned nofpclass(nan pinf pzero sub nnorm) [[ARG:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[CLASS_TEST:%.*]] = call i1 @llvm.is.fpclass.f32(float nofpclass(nan pinf pzero sub nnorm) [[ARG]], i32 noundef 292) #[[ATTR24]]
+; CHECK-NEXT: [[CLASS_TEST:%.*]] = call i1 @llvm.is.fpclass.f32(float nofpclass(nan pinf pzero sub nnorm) [[ARG]], /* (ninf nzero pnorm) */ i32 noundef 292) #[[ATTR24]]
; CHECK-NEXT: call void @llvm.assume(i1 noundef [[CLASS_TEST]]) #[[ATTR22]]
; CHECK-NEXT: call void @extern.use(float nofpclass(nan pinf pzero sub nnorm) [[ARG]])
; CHECK-NEXT: ret float [[ARG]]
@@ -1374,9 +1374,9 @@ define float @assume_intersection_class(float %arg) {
; CHECK-LABEL: define nofpclass(nan inf zero sub nnorm) float @assume_intersection_class
; CHECK-SAME: (float returned nofpclass(nan inf zero sub nnorm) [[ARG:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[POS_NORMAL_OR_POS_SUBNORMAL:%.*]] = call i1 @llvm.is.fpclass.f32(float nofpclass(nan inf zero sub nnorm) [[ARG]], i32 noundef 384) #[[ATTR24]]
+; CHECK-NEXT: [[POS_NORMAL_OR_POS_SUBNORMAL:%.*]] = call i1 @llvm.is.fpclass.f32(float nofpclass(nan inf zero sub nnorm) [[ARG]], /* (psub pnorm) */ i32 noundef 384) #[[ATTR24]]
; CHECK-NEXT: call void @llvm.assume(i1 noundef [[POS_NORMAL_OR_POS_SUBNORMAL]]) #[[ATTR22]]
-; CHECK-NEXT: [[IS_NORMAL:%.*]] = call i1 @llvm.is.fpclass.f32(float nofpclass(nan inf zero sub nnorm) [[ARG]], i32 noundef 264) #[[ATTR24]]
+; CHECK-NEXT: [[IS_NORMAL:%.*]] = call i1 @llvm.is.fpclass.f32(float nofpclass(nan inf zero sub nnorm) [[ARG]], /* (norm) */ i32 noundef 264) #[[ATTR24]]
; CHECK-NEXT: call void @llvm.assume(i1 noundef [[IS_NORMAL]]) #[[ATTR22]]
; CHECK-NEXT: call void @extern.use(float nofpclass(nan inf zero sub nnorm) [[ARG]])
; CHECK-NEXT: ret float [[ARG]]
@@ -1395,9 +1395,9 @@ define float @assume_intersection_none(float %arg) {
; CHECK-LABEL: define nofpclass(all) float @assume_intersection_none
; CHECK-SAME: (float returned nofpclass(all) [[ARG:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float nofpclass(all) [[ARG]], i32 noundef 682) #[[ATTR24]]
+; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float nofpclass(all) [[ARG]], /* (qnan pinf nzero psub nnorm) */ i32 noundef 682) #[[ATTR24]]
; CHECK-NEXT: call void @llvm.assume(i1 noundef [[CLASS1]]) #[[ATTR22]]
-; CHECK-NEXT: [[CLASS2:%.*]] = call i1 @llvm.is.fpclass.f32(float nofpclass(all) [[ARG]], i32 noundef 341) #[[ATTR24]]
+; CHECK-NEXT: [[CLASS2:%.*]] = call i1 @llvm.is.fpclass.f32(float nofpclass(all) [[ARG]], /* (snan ninf pzero nsub pnorm) */ i32 noundef 341) #[[ATTR24]]
; CHECK-NEXT: call void @llvm.assume(i1 noundef [[CLASS2]]) #[[ATTR22]]
; CHECK-NEXT: call void @extern.use(float nofpclass(all) [[ARG]])
; CHECK-NEXT: ret float [[ARG]]
diff --git a/llvm/test/Transforms/CodeGenPrepare/AArch64/fpclass-test.ll b/llvm/test/Transforms/CodeGenPrepare/AArch64/fpclass-test.ll
index 63ab22e96ad2a..92f905631d549 100644
--- a/llvm/test/Transforms/CodeGenPrepare/AArch64/fpclass-test.ll
+++ b/llvm/test/Transforms/CodeGenPrepare/AArch64/fpclass-test.ll
@@ -4,7 +4,7 @@
define i1 @test_is_inf_or_nan(double %arg) {
; CHECK-LABEL: define i1 @test_is_inf_or_nan(
; CHECK-SAME: double [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[ARG]], i32 519)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[ARG]], /* (nan inf) */ i32 519)
; CHECK-NEXT: ret i1 [[TMP1]]
;
%abs = tail call double @llvm.fabs.f64(double %arg)
@@ -15,7 +15,7 @@ define i1 @test_is_inf_or_nan(double %arg) {
define i1 @test_is_not_inf_or_nan(double %arg) {
; CHECK-LABEL: define i1 @test_is_not_inf_or_nan(
; CHECK-SAME: double [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[ARG]], i32 504)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[ARG]], /* (zero sub norm) */ i32 504)
; CHECK-NEXT: ret i1 [[TMP1]]
;
%abs = tail call double @llvm.fabs.f64(double %arg)
@@ -26,7 +26,7 @@ define i1 @test_is_not_inf_or_nan(double %arg) {
define i1 @test_is_inf(double %arg) {
; CHECK-LABEL: define i1 @test_is_inf(
; CHECK-SAME: double [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[ARG]], i32 516)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[ARG]], /* (inf) */ i32 516)
; CHECK-NEXT: ret i1 [[TMP1]]
;
%abs = tail call double @llvm.fabs.f64(double %arg)
@@ -37,7 +37,7 @@ define i1 @test_is_inf(double %arg) {
define i1 @test_is_not_inf(double %arg) {
; CHECK-LABEL: define i1 @test_is_not_inf(
; CHECK-SAME: double [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[ARG]], i32 507)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[ARG]], /* (nan zero sub norm) */ i32 507)
; CHECK-NEXT: ret i1 [[TMP1]]
;
%abs = tail call double @llvm.fabs.f64(double %arg)
@@ -48,7 +48,7 @@ define i1 @test_is_not_inf(double %arg) {
define <vscale x 2 x i1> @test_vec_is_inf_or_nan(<vscale x 2 x double> %arg) {
; CHECK-LABEL: define <vscale x 2 x i1> @test_vec_is_inf_or_nan(
; CHECK-SAME: <vscale x 2 x double> [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.is.fpclass.nxv2f64(<vscale x 2 x double> [[ARG]], i32 519)
+; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.is.fpclass.nxv2f64(<vscale x 2 x double> [[ARG]], /* (nan inf) */ i32 519)
; CHECK-NEXT: ret <vscale x 2 x i1> [[TMP1]]
;
%abs = tail call <vscale x 2 x double> @llvm.fabs.nxv2f64(<vscale x 2 x double> %arg)
@@ -59,7 +59,7 @@ define <vscale x 2 x i1> @test_vec_is_inf_or_nan(<vscale x 2 x double> %arg) {
define <vscale x 2 x i1> @test_vec_is_not_inf_or_nan(<vscale x 2 x double> %arg) {
; CHECK-LABEL: define <vscale x 2 x i1> @test_vec_is_not_inf_or_nan(
; CHECK-SAME: <vscale x 2 x double> [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.is.fpclass.nxv2f64(<vscale x 2 x double> [[ARG]], i32 504)
+; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.is.fpclass.nxv2f64(<vscale x 2 x double> [[ARG]], /* (zero sub norm) */ i32 504)
; CHECK-NEXT: ret <vscale x 2 x i1> [[TMP1]]
;
%abs = tail call <vscale x 2 x double> @llvm.fabs.nxv2f64(<vscale x 2 x double> %arg)
@@ -70,7 +70,7 @@ define <vscale x 2 x i1> @test_vec_is_not_inf_or_nan(<vscale x 2 x double> %arg)
define <vscale x 2 x i1> @test_vec_is_inf(<vscale x 2 x double> %arg) {
; CHECK-LABEL: define <vscale x 2 x i1> @test_vec_is_inf(
; CHECK-SAME: <vscale x 2 x double> [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.is.fpclass.nxv2f64(<vscale x 2 x double> [[ARG]], i32 516)
+; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.is.fpclass.nxv2f64(<vscale x 2 x double> [[ARG]], /* (inf) */ i32 516)
; CHECK-NEXT: ret <vscale x 2 x i1> [[TMP1]]
;
%abs = tail call <vscale x 2 x double> @llvm.fabs.nxv2f64(<vscale x 2 x double> %arg)
@@ -81,7 +81,7 @@ define <vscale x 2 x i1> @test_vec_is_inf(<vscale x 2 x double> %arg) {
define <vscale x 2 x i1> @test_vec_is_not_inf(<vscale x 2 x double> %arg) {
; CHECK-LABEL: define <vscale x 2 x i1> @test_vec_is_not_inf(
; CHECK-SAME: <vscale x 2 x double> [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.is.fpclass.nxv2f64(<vscale x 2 x double> [[ARG]], i32 507)
+; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.is.fpclass.nxv2f64(<vscale x 2 x double> [[ARG]], /* (nan zero sub norm) */ i32 507)
; CHECK-NEXT: ret <vscale x 2 x i1> [[TMP1]]
;
%abs = tail call <vscale x 2 x double> @llvm.fabs.nxv2f64(<vscale x 2 x double> %arg)
@@ -92,7 +92,7 @@ define <vscale x 2 x i1> @test_vec_is_not_inf(<vscale x 2 x double> %arg) {
define i1 @test_fp128_is_inf_or_nan(fp128 %arg) {
; CHECK-LABEL: define i1 @test_fp128_is_inf_or_nan(
; CHECK-SAME: fp128 [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[ARG]], i32 519)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[ARG]], /* (nan inf) */ i32 519)
; CHECK-NEXT: ret i1 [[TMP1]]
;
%abs = tail call fp128 @llvm.fabs.f128(fp128 %arg)
@@ -103,7 +103,7 @@ define i1 @test_fp128_is_inf_or_nan(fp128 %arg) {
define i1 @test_fp128_is_not_inf_or_nan(fp128 %arg) {
; CHECK-LABEL: define i1 @test_fp128_is_not_inf_or_nan(
; CHECK-SAME: fp128 [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[ARG]], i32 504)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[ARG]], /* (zero sub norm) */ i32 504)
; CHECK-NEXT: ret i1 [[TMP1]]
;
%abs = tail call fp128 @llvm.fabs.f128(fp128 %arg)
@@ -114,7 +114,7 @@ define i1 @test_fp128_is_not_inf_or_nan(fp128 %arg) {
define i1 @test_fp128_is_inf(fp128 %arg) {
; CHECK-LABEL: define i1 @test_fp128_is_inf(
; CHECK-SAME: fp128 [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[ARG]], i32 516)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[ARG]], /* (inf) */ i32 516)
; CHECK-NEXT: ret i1 [[TMP1]]
;
%abs = tail call fp128 @llvm.fabs.f128(fp128 %arg)
@@ -125,7 +125,7 @@ define i1 @test_fp128_is_inf(fp128 %arg) {
define i1 @test_fp128_is_not_inf(fp128 %arg) {
; CHECK-LABEL: define i1 @test_fp128_is_not_inf(
; CHECK-SAME: fp128 [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[ARG]], i32 507)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[ARG]], /* (nan zero sub norm) */ i32 507)
; CHECK-NEXT: ret i1 [[TMP1]]
;
%abs = tail call fp128 @llvm.fabs.f128(fp128 %arg)
diff --git a/llvm/test/Transforms/CodeGenPrepare/RISCV/fpclass-test.ll b/llvm/test/Transforms/CodeGenPrepare/RISCV/fpclass-test.ll
index 7c00218bdcce3..628427d03c3c7 100644
--- a/llvm/test/Transforms/CodeGenPrepare/RISCV/fpclass-test.ll
+++ b/llvm/test/Transforms/CodeGenPrepare/RISCV/fpclass-test.ll
@@ -4,7 +4,7 @@
define i1 @test_is_inf_or_nan(double %arg) {
; CHECK-LABEL: define i1 @test_is_inf_or_nan(
; CHECK-SAME: double [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[ARG]], i32 519)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[ARG]], /* (nan inf) */ i32 519)
; CHECK-NEXT: ret i1 [[TMP1]]
;
%abs = tail call double @llvm.fabs.f64(double %arg)
@@ -15,7 +15,7 @@ define i1 @test_is_inf_or_nan(double %arg) {
define i1 @test_is_not_inf_or_nan(double %arg) {
; CHECK-LABEL: define i1 @test_is_not_inf_or_nan(
; CHECK-SAME: double [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[ARG]], i32 504)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[ARG]], /* (zero sub norm) */ i32 504)
; CHECK-NEXT: ret i1 [[TMP1]]
;
%abs = tail call double @llvm.fabs.f64(double %arg)
@@ -26,7 +26,7 @@ define i1 @test_is_not_inf_or_nan(double %arg) {
define i1 @test_is_inf(double %arg) {
; CHECK-LABEL: define i1 @test_is_inf(
; CHECK-SAME: double [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[ARG]], i32 516)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[ARG]], /* (inf) */ i32 516)
; CHECK-NEXT: ret i1 [[TMP1]]
;
%abs = tail call double @llvm.fabs.f64(double %arg)
@@ -37,7 +37,7 @@ define i1 @test_is_inf(double %arg) {
define i1 @test_is_not_inf(double %arg) {
; CHECK-LABEL: define i1 @test_is_not_inf(
; CHECK-SAME: double [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[ARG]], i32 507)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[ARG]], /* (nan zero sub norm) */ i32 507)
; CHECK-NEXT: ret i1 [[TMP1]]
;
%abs = tail call double @llvm.fabs.f64(double %arg)
@@ -48,7 +48,7 @@ define i1 @test_is_not_inf(double %arg) {
define <vscale x 4 x i1> @test_vec_is_inf_or_nan(<vscale x 4 x double> %arg) {
; CHECK-LABEL: define <vscale x 4 x i1> @test_vec_is_inf_or_nan(
; CHECK-SAME: <vscale x 4 x double> [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f64(<vscale x 4 x double> [[ARG]], i32 519)
+; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f64(<vscale x 4 x double> [[ARG]], /* (nan inf) */ i32 519)
; CHECK-NEXT: ret <vscale x 4 x i1> [[TMP1]]
;
%abs = tail call <vscale x 4 x double> @llvm.fabs.nxv4f64(<vscale x 4 x double> %arg)
@@ -59,7 +59,7 @@ define <vscale x 4 x i1> @test_vec_is_inf_or_nan(<vscale x 4 x double> %arg) {
define <vscale x 4 x i1> @test_vec_is_not_inf_or_nan(<vscale x 4 x double> %arg) {
; CHECK-LABEL: define <vscale x 4 x i1> @test_vec_is_not_inf_or_nan(
; CHECK-SAME: <vscale x 4 x double> [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f64(<vscale x 4 x double> [[ARG]], i32 504)
+; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f64(<vscale x 4 x double> [[ARG]], /* (zero sub norm) */ i32 504)
; CHECK-NEXT: ret <vscale x 4 x i1> [[TMP1]]
;
%abs = tail call <vscale x 4 x double> @llvm.fabs.nxv4f64(<vscale x 4 x double> %arg)
@@ -70,7 +70,7 @@ define <vscale x 4 x i1> @test_vec_is_not_inf_or_nan(<vscale x 4 x double> %arg)
define <vscale x 4 x i1> @test_vec_is_inf(<vscale x 4 x double> %arg) {
; CHECK-LABEL: define <vscale x 4 x i1> @test_vec_is_inf(
; CHECK-SAME: <vscale x 4 x double> [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f64(<vscale x 4 x double> [[ARG]], i32 516)
+; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f64(<vscale x 4 x double> [[ARG]], /* (inf) */ i32 516)
; CHECK-NEXT: ret <vscale x 4 x i1> [[TMP1]]
;
%abs = tail call <vscale x 4 x double> @llvm.fabs.nxv4f64(<vscale x 4 x double> %arg)
@@ -81,7 +81,7 @@ define <vscale x 4 x i1> @test_vec_is_inf(<vscale x 4 x double> %arg) {
define <vscale x 4 x i1> @test_vec_is_not_inf(<vscale x 4 x double> %arg) {
; CHECK-LABEL: define <vscale x 4 x i1> @test_vec_is_not_inf(
; CHECK-SAME: <vscale x 4 x double> [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f64(<vscale x 4 x double> [[ARG]], i32 507)
+; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f64(<vscale x 4 x double> [[ARG]], /* (nan zero sub norm) */ i32 507)
; CHECK-NEXT: ret <vscale x 4 x i1> [[TMP1]]
;
%abs = tail call <vscale x 4 x double> @llvm.fabs.nxv4f64(<vscale x 4 x double> %arg)
@@ -92,7 +92,7 @@ define <vscale x 4 x i1> @test_vec_is_not_inf(<vscale x 4 x double> %arg) {
define i1 @test_fp128_is_inf_or_nan(fp128 %arg) {
; CHECK-LABEL: define i1 @test_fp128_is_inf_or_nan(
; CHECK-SAME: fp128 [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[ARG]], i32 519)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[ARG]], /* (nan inf) */ i32 519)
; CHECK-NEXT: ret i1 [[TMP1]]
;
%abs = tail call fp128 @llvm.fabs.f128(fp128 %arg)
@@ -103,7 +103,7 @@ define i1 @test_fp128_is_inf_or_nan(fp128 %arg) {
define i1 @test_fp128_is_not_inf_or_nan(fp128 %arg) {
; CHECK-LABEL: define i1 @test_fp128_is_not_inf_or_nan(
; CHECK-SAME: fp128 [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[ARG]], i32 504)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[ARG]], /* (zero sub norm) */ i32 504)
; CHECK-NEXT: ret i1 [[TMP1]]
;
%abs = tail call fp128 @llvm.fabs.f128(fp128 %arg)
@@ -114,7 +114,7 @@ define i1 @test_fp128_is_not_inf_or_nan(fp128 %arg) {
define i1 @test_fp128_is_inf(fp128 %arg) {
; CHECK-LABEL: define i1 @test_fp128_is_inf(
; CHECK-SAME: fp128 [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[ARG]], i32 516)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[ARG]], /* (inf) */ i32 516)
; CHECK-NEXT: ret i1 [[TMP1]]
;
%abs = tail call fp128 @llvm.fabs.f128(fp128 %arg)
@@ -125,7 +125,7 @@ define i1 @test_fp128_is_inf(fp128 %arg) {
define i1 @test_fp128_is_not_inf(fp128 %arg) {
; CHECK-LABEL: define i1 @test_fp128_is_not_inf(
; CHECK-SAME: fp128 [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[ARG]], i32 507)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[ARG]], /* (nan zero sub norm) */ i32 507)
; CHECK-NEXT: ret i1 [[TMP1]]
;
%abs = tail call fp128 @llvm.fabs.f128(fp128 %arg)
diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/fpclass-test.ll b/llvm/test/Transforms/CodeGenPrepare/X86/fpclass-test.ll
index 525caeb3e79a1..750851ab89d5a 100644
--- a/llvm/test/Transforms/CodeGenPrepare/X86/fpclass-test.ll
+++ b/llvm/test/Transforms/CodeGenPrepare/X86/fpclass-test.ll
@@ -4,7 +4,7 @@
define i1 @test_is_inf_or_nan(double %arg) {
; CHECK-LABEL: define i1 @test_is_inf_or_nan(
; CHECK-SAME: double [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[ARG]], i32 519)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[ARG]], /* (nan inf) */ i32 519)
; CHECK-NEXT: ret i1 [[TMP1]]
;
%abs = tail call double @llvm.fabs.f64(double %arg)
@@ -15,7 +15,7 @@ define i1 @test_is_inf_or_nan(double %arg) {
define i1 @test_is_not_inf_or_nan(double %arg) {
; CHECK-LABEL: define i1 @test_is_not_inf_or_nan(
; CHECK-SAME: double [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[ARG]], i32 504)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[ARG]], /* (zero sub norm) */ i32 504)
; CHECK-NEXT: ret i1 [[TMP1]]
;
%abs = tail call double @llvm.fabs.f64(double %arg)
@@ -26,7 +26,7 @@ define i1 @test_is_not_inf_or_nan(double %arg) {
define i1 @test_is_inf(double %arg) {
; CHECK-LABEL: define i1 @test_is_inf(
; CHECK-SAME: double [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[ARG]], i32 516)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[ARG]], /* (inf) */ i32 516)
; CHECK-NEXT: ret i1 [[TMP1]]
;
%abs = tail call double @llvm.fabs.f64(double %arg)
@@ -37,7 +37,7 @@ define i1 @test_is_inf(double %arg) {
define i1 @test_is_not_inf(double %arg) {
; CHECK-LABEL: define i1 @test_is_not_inf(
; CHECK-SAME: double [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[ARG]], i32 507)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[ARG]], /* (nan zero sub norm) */ i32 507)
; CHECK-NEXT: ret i1 [[TMP1]]
;
%abs = tail call double @llvm.fabs.f64(double %arg)
@@ -48,7 +48,7 @@ define i1 @test_is_not_inf(double %arg) {
define <4 x i1> @test_vec_is_inf_or_nan(<4 x double> %arg) {
; CHECK-LABEL: define <4 x i1> @test_vec_is_inf_or_nan(
; CHECK-SAME: <4 x double> [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.is.fpclass.v4f64(<4 x double> [[ARG]], i32 519)
+; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.is.fpclass.v4f64(<4 x double> [[ARG]], /* (nan inf) */ i32 519)
; CHECK-NEXT: ret <4 x i1> [[TMP1]]
;
%abs = tail call <4 x double> @llvm.fabs.v4f64(<4 x double> %arg)
@@ -59,7 +59,7 @@ define <4 x i1> @test_vec_is_inf_or_nan(<4 x double> %arg) {
define <4 x i1> @test_vec_is_not_inf_or_nan(<4 x double> %arg) {
; CHECK-LABEL: define <4 x i1> @test_vec_is_not_inf_or_nan(
; CHECK-SAME: <4 x double> [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.is.fpclass.v4f64(<4 x double> [[ARG]], i32 504)
+; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.is.fpclass.v4f64(<4 x double> [[ARG]], /* (zero sub norm) */ i32 504)
; CHECK-NEXT: ret <4 x i1> [[TMP1]]
;
%abs = tail call <4 x double> @llvm.fabs.v4f64(<4 x double> %arg)
@@ -70,7 +70,7 @@ define <4 x i1> @test_vec_is_not_inf_or_nan(<4 x double> %arg) {
define <4 x i1> @test_vec_is_inf(<4 x double> %arg) {
; CHECK-LABEL: define <4 x i1> @test_vec_is_inf(
; CHECK-SAME: <4 x double> [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.is.fpclass.v4f64(<4 x double> [[ARG]], i32 516)
+; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.is.fpclass.v4f64(<4 x double> [[ARG]], /* (inf) */ i32 516)
; CHECK-NEXT: ret <4 x i1> [[TMP1]]
;
%abs = tail call <4 x double> @llvm.fabs.v4f64(<4 x double> %arg)
@@ -81,7 +81,7 @@ define <4 x i1> @test_vec_is_inf(<4 x double> %arg) {
define <4 x i1> @test_vec_is_not_inf(<4 x double> %arg) {
; CHECK-LABEL: define <4 x i1> @test_vec_is_not_inf(
; CHECK-SAME: <4 x double> [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.is.fpclass.v4f64(<4 x double> [[ARG]], i32 507)
+; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.is.fpclass.v4f64(<4 x double> [[ARG]], /* (nan zero sub norm) */ i32 507)
; CHECK-NEXT: ret <4 x i1> [[TMP1]]
;
%abs = tail call <4 x double> @llvm.fabs.v4f64(<4 x double> %arg)
@@ -92,7 +92,7 @@ define <4 x i1> @test_vec_is_not_inf(<4 x double> %arg) {
define i1 @test_fp128_is_inf_or_nan(fp128 %arg) {
; CHECK-LABEL: define i1 @test_fp128_is_inf_or_nan(
; CHECK-SAME: fp128 [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[ARG]], i32 519)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[ARG]], /* (nan inf) */ i32 519)
; CHECK-NEXT: ret i1 [[TMP1]]
;
%abs = tail call fp128 @llvm.fabs.f128(fp128 %arg)
@@ -103,7 +103,7 @@ define i1 @test_fp128_is_inf_or_nan(fp128 %arg) {
define i1 @test_fp128_is_not_inf_or_nan(fp128 %arg) {
; CHECK-LABEL: define i1 @test_fp128_is_not_inf_or_nan(
; CHECK-SAME: fp128 [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[ARG]], i32 504)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[ARG]], /* (zero sub norm) */ i32 504)
; CHECK-NEXT: ret i1 [[TMP1]]
;
%abs = tail call fp128 @llvm.fabs.f128(fp128 %arg)
@@ -114,7 +114,7 @@ define i1 @test_fp128_is_not_inf_or_nan(fp128 %arg) {
define i1 @test_fp128_is_inf(fp128 %arg) {
; CHECK-LABEL: define i1 @test_fp128_is_inf(
; CHECK-SAME: fp128 [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[ARG]], i32 516)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[ARG]], /* (inf) */ i32 516)
; CHECK-NEXT: ret i1 [[TMP1]]
;
%abs = tail call fp128 @llvm.fabs.f128(fp128 %arg)
@@ -125,7 +125,7 @@ define i1 @test_fp128_is_inf(fp128 %arg) {
define i1 @test_fp128_is_not_inf(fp128 %arg) {
; CHECK-LABEL: define i1 @test_fp128_is_not_inf(
; CHECK-SAME: fp128 [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[ARG]], i32 507)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[ARG]], /* (nan zero sub norm) */ i32 507)
; CHECK-NEXT: ret i1 [[TMP1]]
;
%abs = tail call fp128 @llvm.fabs.f128(fp128 %arg)
@@ -136,7 +136,7 @@ define i1 @test_fp128_is_not_inf(fp128 %arg) {
define i1 @test_x86_fp80_is_inf_or_nan(x86_fp80 %arg) {
; CHECK-LABEL: define i1 @test_x86_fp80_is_inf_or_nan(
; CHECK-SAME: x86_fp80 [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f80(x86_fp80 [[ARG]], i32 519)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f80(x86_fp80 [[ARG]], /* (nan inf) */ i32 519)
; CHECK-NEXT: ret i1 [[TMP1]]
;
%abs = tail call x86_fp80 @llvm.fabs.f80(x86_fp80 %arg)
@@ -147,7 +147,7 @@ define i1 @test_x86_fp80_is_inf_or_nan(x86_fp80 %arg) {
define i1 @test_x86_fp80_is_not_inf_or_nan(x86_fp80 %arg) {
; CHECK-LABEL: define i1 @test_x86_fp80_is_not_inf_or_nan(
; CHECK-SAME: x86_fp80 [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f80(x86_fp80 [[ARG]], i32 504)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f80(x86_fp80 [[ARG]], /* (zero sub norm) */ i32 504)
; CHECK-NEXT: ret i1 [[TMP1]]
;
%abs = tail call x86_fp80 @llvm.fabs.f80(x86_fp80 %arg)
@@ -158,7 +158,7 @@ define i1 @test_x86_fp80_is_not_inf_or_nan(x86_fp80 %arg) {
define i1 @test_x86_fp80_is_inf(x86_fp80 %arg) {
; CHECK-LABEL: define i1 @test_x86_fp80_is_inf(
; CHECK-SAME: x86_fp80 [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f80(x86_fp80 [[ARG]], i32 516)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f80(x86_fp80 [[ARG]], /* (inf) */ i32 516)
; CHECK-NEXT: ret i1 [[TMP1]]
;
%abs = tail call x86_fp80 @llvm.fabs.f80(x86_fp80 %arg)
@@ -169,7 +169,7 @@ define i1 @test_x86_fp80_is_inf(x86_fp80 %arg) {
define i1 @test_x86_fp80_is_not_inf(x86_fp80 %arg) {
; CHECK-LABEL: define i1 @test_x86_fp80_is_not_inf(
; CHECK-SAME: x86_fp80 [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f80(x86_fp80 [[ARG]], i32 507)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f80(x86_fp80 [[ARG]], /* (nan zero sub norm) */ i32 507)
; CHECK-NEXT: ret i1 [[TMP1]]
;
%abs = tail call x86_fp80 @llvm.fabs.f80(x86_fp80 %arg)
diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll b/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
index f32b6a0c32b96..c3dd22d14806c 100644
--- a/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
+++ b/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
@@ -674,7 +674,7 @@ define i1 @test_class_poison_val_f32(i32 %arg) nounwind {
define i1 @test_class_over_max_mask_f32(float %x) nounwind {
; CHECK-LABEL: @test_class_over_max_mask_f32(
-; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 1)
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (snan) */ i32 1)
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.amdgcn.class.f32(float %x, i32 1025)
@@ -766,7 +766,7 @@ define i1 @test_class_isnan_f32(float %x) nounwind {
define i1 @test_class_isnan_f32_strict(float %x) nounwind strictfp {
; CHECK-LABEL: @test_class_isnan_f32_strict(
-; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 3) #[[ATTR20:[0-9]+]]
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (nan) */ i32 3) #[[ATTR20:[0-9]+]]
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.amdgcn.class.f32(float %x, i32 3) strictfp
@@ -784,7 +784,7 @@ define i1 @test_class_is_p0_n0_f32(float %x) nounwind {
define i1 @test_class_is_p0_n0_f32_strict(float %x) nounwind strictfp {
; CHECK-LABEL: @test_class_is_p0_n0_f32_strict(
-; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 96) #[[ATTR20]]
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (zero) */ i32 96) #[[ATTR20]]
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.amdgcn.class.f32(float %x, i32 96) strictfp
@@ -1005,7 +1005,7 @@ define i1 @test_class_is_nan_nnan_src(float %x) {
define i1 @test_class_is_nan_other_nnan_src(float %x) {
; CHECK-LABEL: @test_class_is_nan_other_nnan_src(
; CHECK-NEXT: [[NNAN:%.*]] = fadd nnan float [[X:%.*]], 1.000000e+00
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[NNAN]], i32 264)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[NNAN]], /* (norm) */ i32 264)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%nnan = fadd nnan float %x, 1.0
diff --git a/llvm/test/Transforms/InstCombine/combine-is.fpclass-and-fcmp.ll b/llvm/test/Transforms/InstCombine/combine-is.fpclass-and-fcmp.ll
index 5456b09513dd6..0134095a2cac9 100644
--- a/llvm/test/Transforms/InstCombine/combine-is.fpclass-and-fcmp.ll
+++ b/llvm/test/Transforms/InstCombine/combine-is.fpclass-and-fcmp.ll
@@ -3,7 +3,7 @@
define i1 @fcmp_oeq_inf_or_class_normal(half %x) {
; CHECK-LABEL: @fcmp_oeq_inf_or_class_normal(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 776)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (pinf norm) */ i32 776)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%oeq.inf = fcmp oeq half %x, 0xH7C00
@@ -14,7 +14,7 @@ define i1 @fcmp_oeq_inf_or_class_normal(half %x) {
define i1 @class_normal_or_fcmp_oeq_inf(half %x) {
; CHECK-LABEL: @class_normal_or_fcmp_oeq_inf(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 776)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (pinf norm) */ i32 776)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%oeq.inf = fcmp oeq half %x, 0xH7C00
@@ -25,7 +25,7 @@ define i1 @class_normal_or_fcmp_oeq_inf(half %x) {
define <2 x i1> @fcmp_oeq_inf_or_class_normal_vector(<2 x half> %x) {
; CHECK-LABEL: @fcmp_oeq_inf_or_class_normal_vector(
-; CHECK-NEXT: [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], i32 776)
+; CHECK-NEXT: [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], /* (pinf norm) */ i32 776)
; CHECK-NEXT: ret <2 x i1> [[CLASS]]
;
%oeq.inf = fcmp oeq <2 x half> %x, <half 0xH7C00, half 0xH7C00>
@@ -38,7 +38,7 @@ define i1 @fcmp_oeq_inf_multi_use_or_class_normal(half %x, ptr %ptr) {
; CHECK-LABEL: @fcmp_oeq_inf_multi_use_or_class_normal(
; CHECK-NEXT: [[OEQ_INF:%.*]] = fcmp oeq half [[X:%.*]], +inf
; CHECK-NEXT: store i1 [[OEQ_INF]], ptr [[PTR:%.*]], align 1
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 264)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], /* (norm) */ i32 264)
; CHECK-NEXT: [[OR:%.*]] = or i1 [[OEQ_INF]], [[CLASS]]
; CHECK-NEXT: ret i1 [[OR]]
;
@@ -52,7 +52,7 @@ define i1 @fcmp_oeq_inf_multi_use_or_class_normal(half %x, ptr %ptr) {
define i1 @fcmp_oeq_inf_or_class_normal_multi_use(half %x, ptr %ptr) {
; CHECK-LABEL: @fcmp_oeq_inf_or_class_normal_multi_use(
; CHECK-NEXT: [[OEQ_INF:%.*]] = fcmp oeq half [[X:%.*]], +inf
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 264)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], /* (norm) */ i32 264)
; CHECK-NEXT: store i1 [[CLASS]], ptr [[PTR:%.*]], align 1
; CHECK-NEXT: [[OR:%.*]] = or i1 [[OEQ_INF]], [[CLASS]]
; CHECK-NEXT: ret i1 [[OR]]
@@ -123,7 +123,7 @@ define i1 @fcmp_ord_and_class_isnan_commute(half %x) {
define i1 @fcmp_isfinite_and_class_subnormal(half %x) {
; CHECK-LABEL: @fcmp_isfinite_and_class_subnormal(
-; CHECK-NEXT: [[SUBNORMAL_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 144)
+; CHECK-NEXT: [[SUBNORMAL_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (sub) */ i32 144)
; CHECK-NEXT: ret i1 [[SUBNORMAL_CLASS]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -177,7 +177,7 @@ define i1 @class_finite_or_fcmp_issubnormal(half %x) {
; -> issubnormal
define i1 @fcmp_issubnormal_and_class_finite(half %x) {
; CHECK-LABEL: @fcmp_issubnormal_and_class_finite(
-; CHECK-NEXT: [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 240)
+; CHECK-NEXT: [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (zero sub) */ i32 240)
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -189,7 +189,7 @@ define i1 @fcmp_issubnormal_and_class_finite(half %x) {
define i1 @class_inf_or_fcmp_issubnormal(half %x) {
; CHECK-LABEL: @class_inf_or_fcmp_issubnormal(
-; CHECK-NEXT: [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 756)
+; CHECK-NEXT: [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (inf zero sub) */ i32 756)
; CHECK-NEXT: ret i1 [[OR]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -215,7 +215,7 @@ define <2 x i1> @class_finite_or_fcmp_issubnormal_vector(<2 x half> %x) {
define i1 @fcmp_oeq_zero_or_class_normal(half %x) {
; CHECK-LABEL: @fcmp_oeq_zero_or_class_normal(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 360)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (zero norm) */ i32 360)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%oeq.inf = fcmp oeq half %x, 0.0
@@ -227,7 +227,7 @@ define i1 @fcmp_oeq_zero_or_class_normal(half %x) {
define i1 @fcmp_oeq_zero_or_class_normal_daz(half %x) #1 {
; CHECK-LABEL: @fcmp_oeq_zero_or_class_normal_daz(
; CHECK-NEXT: [[OEQ_INF:%.*]] = fcmp oeq half [[X:%.*]], 0.000000e+00
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 264)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], /* (norm) */ i32 264)
; CHECK-NEXT: [[OR:%.*]] = or i1 [[OEQ_INF]], [[CLASS]]
; CHECK-NEXT: ret i1 [[OR]]
;
@@ -240,7 +240,7 @@ define i1 @fcmp_oeq_zero_or_class_normal_daz(half %x) #1 {
define <2 x i1> @fcmp_oeq_zero_or_class_normal_daz_v2f16(<2 x half> %x) #1 {
; CHECK-LABEL: @fcmp_oeq_zero_or_class_normal_daz_v2f16(
; CHECK-NEXT: [[OEQ_INF:%.*]] = fcmp oeq <2 x half> [[X:%.*]], zeroinitializer
-; CHECK-NEXT: [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X]], i32 264)
+; CHECK-NEXT: [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X]], /* (norm) */ i32 264)
; CHECK-NEXT: [[OR:%.*]] = or <2 x i1> [[OEQ_INF]], [[CLASS]]
; CHECK-NEXT: ret <2 x i1> [[OR]]
;
@@ -253,7 +253,7 @@ define <2 x i1> @fcmp_oeq_zero_or_class_normal_daz_v2f16(<2 x half> %x) #1 {
define i1 @fcmp_oeq_zero_or_class_normal_dynamic(half %x) #2 {
; CHECK-LABEL: @fcmp_oeq_zero_or_class_normal_dynamic(
; CHECK-NEXT: [[OEQ_INF:%.*]] = fcmp oeq half [[X:%.*]], 0.000000e+00
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 264)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], /* (norm) */ i32 264)
; CHECK-NEXT: [[OR:%.*]] = or i1 [[OEQ_INF]], [[CLASS]]
; CHECK-NEXT: ret i1 [[OR]]
;
@@ -266,7 +266,7 @@ define i1 @fcmp_oeq_zero_or_class_normal_dynamic(half %x) #2 {
define <2 x i1> @fcmp_oeq_zero_or_class_normal_dynamic_v2f16(<2 x half> %x) #2 {
; CHECK-LABEL: @fcmp_oeq_zero_or_class_normal_dynamic_v2f16(
; CHECK-NEXT: [[OEQ_INF:%.*]] = fcmp oeq <2 x half> [[X:%.*]], zeroinitializer
-; CHECK-NEXT: [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X]], i32 264)
+; CHECK-NEXT: [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X]], /* (norm) */ i32 264)
; CHECK-NEXT: [[OR:%.*]] = or <2 x i1> [[OEQ_INF]], [[CLASS]]
; CHECK-NEXT: ret <2 x i1> [[OR]]
;
@@ -278,7 +278,7 @@ define <2 x i1> @fcmp_oeq_zero_or_class_normal_dynamic_v2f16(<2 x half> %x) #2 {
define i1 @class_normal_or_fcmp_oeq_zero(half %x) {
; CHECK-LABEL: @class_normal_or_fcmp_oeq_zero(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 360)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (zero norm) */ i32 360)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%oeq.inf = fcmp oeq half %x, 0.0
@@ -289,7 +289,7 @@ define i1 @class_normal_or_fcmp_oeq_zero(half %x) {
define i1 @fcmp_ueq_zero_or_class_normal(half %x) {
; CHECK-LABEL: @fcmp_ueq_zero_or_class_normal(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 363)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (nan zero norm) */ i32 363)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%ueq.inf = fcmp ueq half %x, 0.0
@@ -300,7 +300,7 @@ define i1 @fcmp_ueq_zero_or_class_normal(half %x) {
define i1 @class_normal_or_fcmp_ueq_zero(half %x) {
; CHECK-LABEL: @class_normal_or_fcmp_ueq_zero(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 363)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (nan zero norm) */ i32 363)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%ueq.inf = fcmp ueq half %x, 0.0
@@ -323,7 +323,7 @@ define i1 @fcmp_one_zero_or_class_normal(half %x) {
define i1 @fcmp_one_zero_or_class_normal_daz(half %x) #1 {
; CHECK-LABEL: @fcmp_one_zero_or_class_normal_daz(
; CHECK-NEXT: [[ONE_INF:%.*]] = fcmp one half [[X:%.*]], 0.000000e+00
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 264)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], /* (norm) */ i32 264)
; CHECK-NEXT: [[OR:%.*]] = or i1 [[ONE_INF]], [[CLASS]]
; CHECK-NEXT: ret i1 [[OR]]
;
@@ -336,7 +336,7 @@ define i1 @fcmp_one_zero_or_class_normal_daz(half %x) #1 {
define i1 @fcmp_one_zero_or_class_normal_dynamic(half %x) #2 {
; CHECK-LABEL: @fcmp_one_zero_or_class_normal_dynamic(
; CHECK-NEXT: [[ONE_INF:%.*]] = fcmp one half [[X:%.*]], 0.000000e+00
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 264)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], /* (norm) */ i32 264)
; CHECK-NEXT: [[OR:%.*]] = or i1 [[ONE_INF]], [[CLASS]]
; CHECK-NEXT: ret i1 [[OR]]
;
@@ -382,7 +382,7 @@ define i1 @class_normal_or_fcmp_une_zero(half %x) {
define i1 @class_normal_or_fcmp_une_zero_daz(half %x) #1 {
; CHECK-LABEL: @class_normal_or_fcmp_une_zero_daz(
; CHECK-NEXT: [[UNE_INF:%.*]] = fcmp une half [[X:%.*]], 0.000000e+00
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 264)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], /* (norm) */ i32 264)
; CHECK-NEXT: [[OR:%.*]] = or i1 [[UNE_INF]], [[CLASS]]
; CHECK-NEXT: ret i1 [[OR]]
;
@@ -395,7 +395,7 @@ define i1 @class_normal_or_fcmp_une_zero_daz(half %x) #1 {
define i1 @class_normal_or_fcmp_une_zero_dynamic(half %x) #2 {
; CHECK-LABEL: @class_normal_or_fcmp_une_zero_dynamic(
; CHECK-NEXT: [[UNE_INF:%.*]] = fcmp une half [[X:%.*]], 0.000000e+00
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 264)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], /* (norm) */ i32 264)
; CHECK-NEXT: [[OR:%.*]] = or i1 [[UNE_INF]], [[CLASS]]
; CHECK-NEXT: ret i1 [[OR]]
;
@@ -407,7 +407,7 @@ define i1 @class_normal_or_fcmp_une_zero_dynamic(half %x) #2 {
define i1 @fcmp_oeq_inf_xor_class_normal(half %x) {
; CHECK-LABEL: @fcmp_oeq_inf_xor_class_normal(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 776)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (pinf norm) */ i32 776)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%oeq.inf = fcmp oeq half %x, 0xH7C00
@@ -418,7 +418,7 @@ define i1 @fcmp_oeq_inf_xor_class_normal(half %x) {
define i1 @class_normal_xor_fcmp_oeq_inf(half %x) {
; CHECK-LABEL: @class_normal_xor_fcmp_oeq_inf(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 776)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (pinf norm) */ i32 776)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%oeq.inf = fcmp oeq half %x, 0xH7C00
diff --git a/llvm/test/Transforms/InstCombine/create-class-from-logic-fcmp.ll b/llvm/test/Transforms/InstCombine/create-class-from-logic-fcmp.ll
index 5a956581ffd85..5986a56dd7b2f 100644
--- a/llvm/test/Transforms/InstCombine/create-class-from-logic-fcmp.ll
+++ b/llvm/test/Transforms/InstCombine/create-class-from-logic-fcmp.ll
@@ -10,7 +10,7 @@
; Base pattern !isfinite(x) || x == 0.0
define i1 @not_isfinite_or_zero_f16(half %x) {
; CHECK-LABEL: @not_isfinite_or_zero_f16(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 615)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (nan inf zero) */ i32 615)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -23,7 +23,7 @@ define i1 @not_isfinite_or_zero_f16(half %x) {
; Base pattern x == 0.0 || !isfinite(x)
define i1 @not_isfinite_or_zero_f16_commute_or(half %x) {
; CHECK-LABEL: @not_isfinite_or_zero_f16_commute_or(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 615)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (nan inf zero) */ i32 615)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -36,7 +36,7 @@ define i1 @not_isfinite_or_zero_f16_commute_or(half %x) {
; Base pattern !isfinite(x) || x == -0.0
define i1 @not_isfinite_or_zero_f16_negzero(half %x) {
; CHECK-LABEL: @not_isfinite_or_zero_f16_negzero(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 615)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (nan inf zero) */ i32 615)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -48,7 +48,7 @@ define i1 @not_isfinite_or_zero_f16_negzero(half %x) {
define i1 @not_isfinite_or_fabs_oeq_zero_f16(half %x) {
; CHECK-LABEL: @not_isfinite_or_fabs_oeq_zero_f16(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 615)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (nan inf zero) */ i32 615)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -61,7 +61,7 @@ define i1 @not_isfinite_or_fabs_oeq_zero_f16(half %x) {
; Base pattern !isfinite(x) || x == 0.0
define <2 x i1> @not_isfinite_or_zero_v2f16(<2 x half> %x) {
; CHECK-LABEL: @not_isfinite_or_zero_v2f16(
-; CHECK-NEXT: [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], i32 615)
+; CHECK-NEXT: [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], /* (nan inf zero) */ i32 615)
; CHECK-NEXT: ret <2 x i1> [[CLASS]]
;
%fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x)
@@ -74,7 +74,7 @@ define <2 x i1> @not_isfinite_or_zero_v2f16(<2 x half> %x) {
; Base pattern !isfinite(x) || x == <0.0, -0.0>
define <2 x i1> @not_isfinite_or_zero_v2f16_pos0_neg0_vec(<2 x half> %x) {
; CHECK-LABEL: @not_isfinite_or_zero_v2f16_pos0_neg0_vec(
-; CHECK-NEXT: [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], i32 615)
+; CHECK-NEXT: [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], /* (nan inf zero) */ i32 615)
; CHECK-NEXT: ret <2 x i1> [[CLASS]]
;
%fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x)
@@ -87,7 +87,7 @@ define <2 x i1> @not_isfinite_or_zero_v2f16_pos0_neg0_vec(<2 x half> %x) {
; Base pattern x == 0.0 || !isfinite(x)
define <2 x i1> @not_isfinite_or_zero_v2f16_commute_or(<2 x half> %x) {
; CHECK-LABEL: @not_isfinite_or_zero_v2f16_commute_or(
-; CHECK-NEXT: [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], i32 615)
+; CHECK-NEXT: [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], /* (nan inf zero) */ i32 615)
; CHECK-NEXT: ret <2 x i1> [[CLASS]]
;
%fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x)
@@ -100,7 +100,7 @@ define <2 x i1> @not_isfinite_or_zero_v2f16_commute_or(<2 x half> %x) {
; Positive test
define i1 @oeq_isinf_or_oeq_zero(half %x) {
; CHECK-LABEL: @oeq_isinf_or_oeq_zero(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 612)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (inf zero) */ i32 612)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -113,7 +113,7 @@ define i1 @oeq_isinf_or_oeq_zero(half %x) {
; Missing fabs for infinity check
define i1 @ueq_inf_or_oeq_zero(half %x) {
; CHECK-LABEL: @ueq_inf_or_oeq_zero(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 611)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (nan pinf zero) */ i32 611)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%cmpinf = fcmp ueq half %x, 0xH7C00
@@ -125,7 +125,7 @@ define i1 @ueq_inf_or_oeq_zero(half %x) {
; Extra fabs.
define i1 @oeq_isinf_or_fabs_oeq_zero(half %x) {
; CHECK-LABEL: @oeq_isinf_or_fabs_oeq_zero(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 612)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (inf zero) */ i32 612)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -138,7 +138,7 @@ define i1 @oeq_isinf_or_fabs_oeq_zero(half %x) {
; Positive test
define i1 @ueq_0_or_oeq_inf(half %x) {
; CHECK-LABEL: @ueq_0_or_oeq_inf(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 611)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (nan pinf zero) */ i32 611)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -163,7 +163,7 @@ define i1 @not_isfinite_or_zero_f16_not_inf(half %x) {
; Positive test
define i1 @ueq_inf_or_ueq_zero(half %x) {
; CHECK-LABEL: @ueq_inf_or_ueq_zero(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 615)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (nan inf zero) */ i32 615)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -237,7 +237,7 @@ define i1 @not_isfinite_or_zero_f16_neg_inf(half %x) {
; Negative test
define i1 @olt_0_or_fabs_ueq_inf(half %x) {
; CHECK-LABEL: @olt_0_or_fabs_ueq_inf(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 543)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (nan inf nsub nnorm) */ i32 543)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -316,7 +316,7 @@ define i1 @not_isfinite_or_zero_f16_not_fabs(half %x) {
; Negation of base pattern, isfinite(x) && !(x == 0.0)
define i1 @negated_isfinite_or_zero_f16(half %x) {
; CHECK-LABEL: @negated_isfinite_or_zero_f16(
-; CHECK-NEXT: [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 408)
+; CHECK-NEXT: [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (sub norm) */ i32 408)
; CHECK-NEXT: ret i1 [[NOT_CLASS]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -329,7 +329,7 @@ define i1 @negated_isfinite_or_zero_f16(half %x) {
; Commuted !(x == 0.0) && isfinite(x)
define i1 @negated_isfinite_or_zero_f16_commute_and(half %x) {
; CHECK-LABEL: @negated_isfinite_or_zero_f16_commute_and(
-; CHECK-NEXT: [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 408)
+; CHECK-NEXT: [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (sub norm) */ i32 408)
; CHECK-NEXT: ret i1 [[NOT_CLASS]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -342,7 +342,7 @@ define i1 @negated_isfinite_or_zero_f16_commute_and(half %x) {
; isfinite(x) && !(x == -0.0)
define i1 @negated_isfinite_or_zero_f16_negzero(half %x) {
; CHECK-LABEL: @negated_isfinite_or_zero_f16_negzero(
-; CHECK-NEXT: [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 408)
+; CHECK-NEXT: [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (sub norm) */ i32 408)
; CHECK-NEXT: ret i1 [[NOT_CLASS]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -355,7 +355,7 @@ define i1 @negated_isfinite_or_zero_f16_negzero(half %x) {
; Negated pattern
define <2 x i1> @negated_isfinite_or_zero_v2f16(<2 x half> %x) {
; CHECK-LABEL: @negated_isfinite_or_zero_v2f16(
-; CHECK-NEXT: [[NOT_CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], i32 408)
+; CHECK-NEXT: [[NOT_CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], /* (sub norm) */ i32 408)
; CHECK-NEXT: ret <2 x i1> [[NOT_CLASS]]
;
%fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x)
@@ -368,7 +368,7 @@ define <2 x i1> @negated_isfinite_or_zero_v2f16(<2 x half> %x) {
; Negated pattern, commuted vector and
define <2 x i1> @negated_isfinite_or_zero_v2f16_comumte(<2 x half> %x) {
; CHECK-LABEL: @negated_isfinite_or_zero_v2f16_comumte(
-; CHECK-NEXT: [[NOT_CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], i32 408)
+; CHECK-NEXT: [[NOT_CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], /* (sub norm) */ i32 408)
; CHECK-NEXT: ret <2 x i1> [[NOT_CLASS]]
;
%fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x)
@@ -381,7 +381,7 @@ define <2 x i1> @negated_isfinite_or_zero_v2f16_comumte(<2 x half> %x) {
; Positive test
define i1 @negated_isfinite_or_zero_f16_not_une_zero(half %x) {
; CHECK-LABEL: @negated_isfinite_or_zero_f16_not_une_zero(
-; CHECK-NEXT: [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 408)
+; CHECK-NEXT: [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (sub norm) */ i32 408)
; CHECK-NEXT: ret i1 [[NOT_CLASS]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -406,7 +406,7 @@ define i1 @negated_isfinite_and_zero_f16(half %x) {
; Negative test
define i1 @negated_isfinite_or_zero_f16_swapped_constants(half %x) {
; CHECK-LABEL: @negated_isfinite_or_zero_f16_swapped_constants(
-; CHECK-NEXT: [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 412)
+; CHECK-NEXT: [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (ninf sub norm) */ i32 412)
; CHECK-NEXT: ret i1 [[NOT_CLASS]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -455,7 +455,7 @@ define i1 @negated_isfinite_or_zero_f16_multi_use_cmp1(half %x, ptr %ptr) {
; Negative test
define i1 @negated_isfinite_or_zero_f16_multi_use_cmp0_not_one_inf(half %x) {
; CHECK-LABEL: @negated_isfinite_or_zero_f16_multi_use_cmp0_not_one_inf(
-; CHECK-NEXT: [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 411)
+; CHECK-NEXT: [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (nan sub norm) */ i32 411)
; CHECK-NEXT: ret i1 [[NOT_CLASS]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -497,7 +497,7 @@ define i1 @fcmp_une_0_or_fcmp_une_inf(half %x) {
define i1 @fcmp_one_0_and_fcmp_une_fabs_inf(half %x) {
; CHECK-LABEL: @fcmp_one_0_and_fcmp_une_fabs_inf(
-; CHECK-NEXT: [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 408)
+; CHECK-NEXT: [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (sub norm) */ i32 408)
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -509,7 +509,7 @@ define i1 @fcmp_one_0_and_fcmp_une_fabs_inf(half %x) {
define i1 @fcmp_une_0_and_fcmp_une_fabs_inf(half %x) {
; CHECK-LABEL: @fcmp_une_0_and_fcmp_une_fabs_inf(
-; CHECK-NEXT: [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 411)
+; CHECK-NEXT: [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (nan sub norm) */ i32 411)
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -531,7 +531,7 @@ define i1 @fcmp_une_0_and_fcmp_une_neginf(half %x) {
define i1 @issubnormal_or_inf(half %x) {
; CHECK-LABEL: @issubnormal_or_inf(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 756)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (inf zero sub) */ i32 756)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -543,7 +543,7 @@ define i1 @issubnormal_or_inf(half %x) {
define i1 @olt_smallest_normal_or_inf(half %x) {
; CHECK-LABEL: @olt_smallest_normal_or_inf(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 764)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (inf zero sub nnorm) */ i32 764)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -555,7 +555,7 @@ define i1 @olt_smallest_normal_or_inf(half %x) {
define i1 @not_issubnormal_or_inf(half %x) {
; CHECK-LABEL: @not_issubnormal_or_inf(
-; CHECK-NEXT: [[NOT:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 267)
+; CHECK-NEXT: [[NOT:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (nan norm) */ i32 267)
; CHECK-NEXT: ret i1 [[NOT]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -567,7 +567,7 @@ define i1 @not_issubnormal_or_inf(half %x) {
define i1 @issubnormal_uge_or_inf(half %x) {
; CHECK-LABEL: @issubnormal_uge_or_inf(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 783)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (nan inf norm) */ i32 783)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -638,7 +638,7 @@ define i1 @issubnormal_or_finite_olt(half %x) {
; inf | nan | zero | subnormal
define i1 @issubnormal_or_finite_uge(half %x) {
; CHECK-LABEL: @issubnormal_or_finite_uge(
-; CHECK-NEXT: [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 759)
+; CHECK-NEXT: [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (nan inf zero sub) */ i32 759)
; CHECK-NEXT: ret i1 [[OR]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -650,7 +650,7 @@ define i1 @issubnormal_or_finite_uge(half %x) {
define i1 @issubnormal_and_finite_olt(half %x) {
; CHECK-LABEL: @issubnormal_and_finite_olt(
-; CHECK-NEXT: [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 240)
+; CHECK-NEXT: [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (zero sub) */ i32 240)
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -674,7 +674,7 @@ define i1 @not_zero_and_subnormal(half %x) {
define i1 @fcmp_fabs_uge_inf_or_fabs_uge_smallest_norm(half %x) {
; CHECK-LABEL: @fcmp_fabs_uge_inf_or_fabs_uge_smallest_norm(
-; CHECK-NEXT: [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 783)
+; CHECK-NEXT: [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (nan inf norm) */ i32 783)
; CHECK-NEXT: ret i1 [[OR]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -793,7 +793,7 @@ define i1 @oeq_isinf_and_ord(half %x) {
define i1 @isnormal_or_zero(half %x) #0 {
; CHECK-LABEL: @isnormal_or_zero(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[AND1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 360)
+; CHECK-NEXT: [[AND1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (zero norm) */ i32 360)
; CHECK-NEXT: ret i1 [[AND1]]
;
entry:
@@ -811,7 +811,7 @@ entry:
define i1 @isnormal_uge_or_zero_oeq(half %x) #0 {
; CHECK-LABEL: @isnormal_uge_or_zero_oeq(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 879)
+; CHECK-NEXT: [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (nan inf zero norm) */ i32 879)
; CHECK-NEXT: ret i1 [[OR]]
;
entry:
@@ -868,7 +868,7 @@ define i1 @une_or_oge_smallest_normal(half %x) #0 {
; -> normal | inf
define i1 @isnormalinf_or_inf(half %x) #0 {
; CHECK-LABEL: @isnormalinf_or_inf(
-; CHECK-NEXT: [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 780)
+; CHECK-NEXT: [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (inf norm) */ i32 780)
; CHECK-NEXT: ret i1 [[OR]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -881,7 +881,7 @@ define i1 @isnormalinf_or_inf(half %x) #0 {
; -> pinf | pnormal
define i1 @posisnormalinf_or_posinf(half %x) #0 {
; CHECK-LABEL: @posisnormalinf_or_posinf(
-; CHECK-NEXT: [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 772)
+; CHECK-NEXT: [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (inf pnorm) */ i32 772)
; CHECK-NEXT: ret i1 [[OR]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -894,7 +894,7 @@ define i1 @posisnormalinf_or_posinf(half %x) #0 {
; -> normal | inf
define i1 @isnormalinf_or_posinf(half %x) #0 {
; CHECK-LABEL: @isnormalinf_or_posinf(
-; CHECK-NEXT: [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 780)
+; CHECK-NEXT: [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (inf norm) */ i32 780)
; CHECK-NEXT: ret i1 [[OR]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -963,7 +963,7 @@ define i1 @not_isnormalinf_or_ord(half %x) #0 {
; -> subnormal | zero
define i1 @not_isnormalinf_and_ord(half %x) #0 {
; CHECK-LABEL: @not_isnormalinf_and_ord(
-; CHECK-NEXT: [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 240)
+; CHECK-NEXT: [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (zero sub) */ i32 240)
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -1018,7 +1018,7 @@ define i1 @not_isnormalinf_or_uno_nofabs(half %x) #0 {
; -> ~pnormal
define i1 @not_negisnormalinf_or_inf(half %x) #0 {
; CHECK-LABEL: @not_negisnormalinf_or_inf(
-; CHECK-NEXT: [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 767)
+; CHECK-NEXT: [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (nan inf zero sub nnorm) */ i32 767)
; CHECK-NEXT: ret i1 [[OR]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -1031,7 +1031,7 @@ define i1 @not_negisnormalinf_or_inf(half %x) #0 {
; -> ~pnormal
define i1 @not_negisnormalinf_or_posinf(half %x) #0 {
; CHECK-LABEL: @not_negisnormalinf_or_posinf(
-; CHECK-NEXT: [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 767)
+; CHECK-NEXT: [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (nan inf zero sub nnorm) */ i32 767)
; CHECK-NEXT: ret i1 [[OR]]
;
%not.is.pos.normal.inf = fcmp ult half %x, 0xH0400
@@ -1043,7 +1043,7 @@ define i1 @not_negisnormalinf_or_posinf(half %x) #0 {
; -> ninf | nnormal
define i1 @not_isposnormalinf_and_isnormalinf(half %x) #0 {
; CHECK-LABEL: @not_isposnormalinf_and_isnormalinf(
-; CHECK-NEXT: [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 12)
+; CHECK-NEXT: [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (ninf nnorm) */ i32 12)
; CHECK-NEXT: ret i1 [[AND]]
;
%not.is.pos.normal.inf = fcmp ult half %x, 0xH0400
@@ -1068,7 +1068,7 @@ define i1 @olt_smallest_normal_or_ord(half %x) #0 {
; -> ~pinf
define i1 @olt_smallest_normal_or_uno(half %x) #0 {
; CHECK-LABEL: @olt_smallest_normal_or_uno(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 255)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (nan ninf zero sub nnorm) */ i32 255)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%uno = fcmp uno half %x, 0.0
@@ -1138,7 +1138,7 @@ define i1 @olt_infinity_or_finite(half %x) #0 {
; -> zero|subnormal|normal
define i1 @olt_infinity_and_finite(half %x) #0 { ; bustttedddd
; CHECK-LABEL: @olt_infinity_and_finite(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 252)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (ninf zero sub nnorm) */ i32 252)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%lt.infinity = fcmp olt half %x, 0xH7C00
@@ -1185,7 +1185,7 @@ define i1 @olt_infinity_or_subnormal(half %x) #0 {
define i1 @olt_infinity_and_subnormal(half %x) #0 {
; CHECK-LABEL: @olt_infinity_and_subnormal(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 240)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (zero sub) */ i32 240)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%lt.infinity = fcmp olt half %x, 0xH7C00
@@ -1197,7 +1197,7 @@ define i1 @olt_infinity_and_subnormal(half %x) #0 {
define i1 @olt_infinity_and_not_subnormal(half %x) #0 {
; CHECK-LABEL: @olt_infinity_and_not_subnormal(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 268)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (ninf norm) */ i32 268)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%lt.infinity = fcmp olt half %x, 0xH7C00
@@ -1235,7 +1235,7 @@ define i1 @olt_infinity_or_ueq_inf(half %x) #0 {
; -> pnormal
define i1 @olt_smallest_normal_or_ueq_inf(half %x) #0 {
; CHECK-LABEL: @olt_smallest_normal_or_ueq_inf(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 767)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (nan inf zero sub nnorm) */ i32 767)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%lt.normal = fcmp olt half %x, 0xH0400
@@ -1259,7 +1259,7 @@ define i1 @olt_smallest_normal_or_une_inf(half %x) #0 {
; -> ninf | nnormal | subnormal | zero
define i1 @olt_smallest_normal_and_une_inf(half %x) #0 {
; CHECK-LABEL: @olt_smallest_normal_and_une_inf(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 252)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (ninf zero sub nnorm) */ i32 252)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%lt.normal = fcmp olt half %x, 0xH0400
@@ -1270,7 +1270,7 @@ define i1 @olt_smallest_normal_and_une_inf(half %x) #0 {
define i1 @olt_smallest_normal_and_une_inf_or_oeq_smallest_normal(half %x) #0 {
; CHECK-LABEL: @olt_smallest_normal_and_une_inf_or_oeq_smallest_normal(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 252)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (ninf zero sub nnorm) */ i32 252)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%lt.normal = fcmp olt half %x, 0xH0400
@@ -1283,7 +1283,7 @@ define i1 @olt_smallest_normal_and_une_inf_or_oeq_smallest_normal(half %x) #0 {
define i1 @olt_smallest_normal_and_une_inf_or_one_smallest_normal(half %x) #0 {
; CHECK-LABEL: @olt_smallest_normal_and_une_inf_or_one_smallest_normal(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 252)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (ninf zero sub nnorm) */ i32 252)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%lt.normal = fcmp olt half %x, 0xH0400
@@ -1408,7 +1408,7 @@ define i1 @oeq_neginfinity_or_oeq_smallest_normal(half %x) #0 {
; -> ninf | fcZero | fcSubnormal
define i1 @oeq_neginfinity_or_olt_smallest_normal(half %x) #0 {
; CHECK-LABEL: @oeq_neginfinity_or_olt_smallest_normal(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 252)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (ninf zero sub nnorm) */ i32 252)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%oeq.neg.infinity = fcmp oeq half %x, 0xHFC00
@@ -1432,7 +1432,7 @@ define i1 @oeq_neginfinity_and_olt_smallest_normal(half %x) #0 {
; -> ninf | pnormal | pinf
define i1 @oeq_neginfinity_or_oge_smallest_normal(half %x) #0 {
; CHECK-LABEL: @oeq_neginfinity_or_oge_smallest_normal(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 772)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (inf pnorm) */ i32 772)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%oeq.neg.infinity = fcmp oeq half %x, 0xHFC00
@@ -1528,7 +1528,7 @@ define i1 @one_neginfinity_or_olt_smallest_normal(half %x) #0 {
; -> ~(nan|ninf)
define i1 @one_neginfinity_and_olt_smallest_normal(half %x) #0 {
; CHECK-LABEL: @one_neginfinity_and_olt_smallest_normal(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 248)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (zero sub nnorm) */ i32 248)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%one.neg.infinity = fcmp one half %x, 0xHFC00
@@ -1563,7 +1563,7 @@ define i1 @one_neginfinity_and_ord(half %x) #0 {
; -> pnormal|pinf
define i1 @one_neginfinity_and_uge_smallest_normal(half %x) #0 {
; CHECK-LABEL: @one_neginfinity_and_uge_smallest_normal(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 768)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (pinf pnorm) */ i32 768)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%one.neg.infinity = fcmp one half %x, 0xHFC00
@@ -1575,7 +1575,7 @@ define i1 @one_neginfinity_and_uge_smallest_normal(half %x) #0 {
; -> ~(pnormal|pinf)
define i1 @ueq_neginfinity_or_olt_smallest_normal(half %x) #0 {
; CHECK-LABEL: @ueq_neginfinity_or_olt_smallest_normal(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 255)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (nan ninf zero sub nnorm) */ i32 255)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%ueq.neg.infinity = fcmp ueq half %x, 0xHFC00
@@ -1722,7 +1722,7 @@ define i1 @fabs_ueq_neginfinity_and_olt_smallest_normal(half %x) #0 { ; WRONG
; -> pinf|pnormal
define i1 @fabs_one_neginfinity_and_uge_smallest_normal(half %x) #0 {
; CHECK-LABEL: @fabs_one_neginfinity_and_uge_smallest_normal(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 768)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (pinf pnorm) */ i32 768)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -1748,7 +1748,7 @@ define i1 @fabs_one_neginfinity_or_olt_smallest_normal(half %x) #0 {
; -> ~(zero|subnormal)
define i1 @fabs_ueq_neginfinity_or_fabs_uge_smallest_normal(half %x) #0 {
; CHECK-LABEL: @fabs_ueq_neginfinity_or_fabs_uge_smallest_normal(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 783)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (nan inf norm) */ i32 783)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -1854,7 +1854,7 @@ define i1 @not_zero_and_subnormal_dynamic(half %x) #2 {
; TODO: This could fold to just fcmp olt half %fabs, 0xH0400
define i1 @subnormal_or_zero_ieee(half %x) #0 {
; CHECK-LABEL: @subnormal_or_zero_ieee(
-; CHECK-NEXT: [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 240)
+; CHECK-NEXT: [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (zero sub) */ i32 240)
; CHECK-NEXT: ret i1 [[AND]]
;
%fabs = call half @llvm.fabs.f16(half %x)
@@ -1893,7 +1893,7 @@ define i1 @subnormal_or_zero_dynamic(half %x) #2 {
define i1 @issubnormal_or_inf_nnan_logical_select(half %x) {
; CHECK-LABEL: @issubnormal_or_inf_nnan_logical_select(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 756)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (inf zero sub) */ i32 756)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call nnan half @llvm.fabs.f16(half %x)
@@ -1905,7 +1905,7 @@ define i1 @issubnormal_or_inf_nnan_logical_select(half %x) {
define i1 @issubnormal_and_ninf_nnan_logical_select(half %x) {
; CHECK-LABEL: @issubnormal_and_ninf_nnan_logical_select(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 240)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (zero sub) */ i32 240)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call nnan half @llvm.fabs.f16(half %x)
@@ -1917,7 +1917,7 @@ define i1 @issubnormal_and_ninf_nnan_logical_select(half %x) {
define i1 @fcmp_ueq_neginf_or_oge_zero_f16(half %x) {
; CHECK-LABEL: @fcmp_ueq_neginf_or_oge_zero_f16(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 999)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (nan inf zero psub pnorm) */ i32 999)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%cmpinf = fcmp ueq half %x, 0xHFC00
@@ -1928,7 +1928,7 @@ define i1 @fcmp_ueq_neginf_or_oge_zero_f16(half %x) {
define i1 @fcmp_oeq_neginf_or_oge_zero_f16(half %x) {
; CHECK-LABEL: @fcmp_oeq_neginf_or_oge_zero_f16(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 996)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (inf zero psub pnorm) */ i32 996)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%cmpinf = fcmp oeq half %x, 0xHFC00
@@ -1965,7 +1965,7 @@ define i1 @fcmp_oeq_neginf_or_oge_zero_f16_daz(half %x) #1 {
define i1 @fcmp_oeq_neginf_or_ogt_zero_f16(half %x) {
; CHECK-LABEL: @fcmp_oeq_neginf_or_ogt_zero_f16(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 900)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (inf psub pnorm) */ i32 900)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%cmpinf = fcmp oeq half %x, 0xHFC00
@@ -1976,7 +1976,7 @@ define i1 @fcmp_oeq_neginf_or_ogt_zero_f16(half %x) {
define i1 @fcmp_ueq_neginf_or_ogt_zero_f16(half %x) {
; CHECK-LABEL: @fcmp_ueq_neginf_or_ogt_zero_f16(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 903)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (nan inf psub pnorm) */ i32 903)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%cmpinf = fcmp ueq half %x, 0xHFC00
@@ -2013,7 +2013,7 @@ define i1 @fcmp_oeq_neginf_or_ogt_zero_f16_daz(half %x) #1 {
define i1 @fcmp_oeq_neginf_or_ugt_zero_f16(half %x) {
; CHECK-LABEL: @fcmp_oeq_neginf_or_ugt_zero_f16(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 903)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (nan inf psub pnorm) */ i32 903)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%cmpinf = fcmp oeq half %x, 0xHFC00
@@ -2050,7 +2050,7 @@ define i1 @fcmp_oeq_neginf_or_ugt_zero_f16_daz(half %x) #1 {
define i1 @fcmp_ueq_posinf_or_ole_zero_f16(half %x) {
; CHECK-LABEL: @fcmp_ueq_posinf_or_ole_zero_f16(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 639)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (nan inf zero nsub nnorm) */ i32 639)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%cmpinf = fcmp ueq half %x, 0xH7C00
@@ -2061,7 +2061,7 @@ define i1 @fcmp_ueq_posinf_or_ole_zero_f16(half %x) {
define i1 @fcmp_oeq_posinf_or_ole_zero_f16(half %x) {
; CHECK-LABEL: @fcmp_oeq_posinf_or_ole_zero_f16(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 636)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (inf zero nsub nnorm) */ i32 636)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%cmpinf = fcmp oeq half %x, 0xH7C00
@@ -2098,7 +2098,7 @@ define i1 @fcmp_oeq_posinf_or_ole_zero_f16_daz(half %x) #1 {
define i1 @fcmp_oeq_posinf_or_olt_zero_f16(half %x) {
; CHECK-LABEL: @fcmp_oeq_posinf_or_olt_zero_f16(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 540)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (inf nsub nnorm) */ i32 540)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%cmpinf = fcmp oeq half %x, 0xH7C00
@@ -2122,7 +2122,7 @@ define i1 @fcmp_oeq_posinf_or_olt_zero_f16_daz(half %x) #1 {
define i1 @fcmp_ueq_posinf_or_ult_zero_f16(half %x) {
; CHECK-LABEL: @fcmp_ueq_posinf_or_ult_zero_f16(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 543)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (nan inf nsub nnorm) */ i32 543)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%cmpinf = fcmp ueq half %x, 0xH7C00
@@ -2133,7 +2133,7 @@ define i1 @fcmp_ueq_posinf_or_ult_zero_f16(half %x) {
define i1 @fcmp_oeq_posinf_or_ult_zero_f16(half %x) {
; CHECK-LABEL: @fcmp_oeq_posinf_or_ult_zero_f16(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 543)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (nan inf nsub nnorm) */ i32 543)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%cmpinf = fcmp oeq half %x, 0xH7C00
@@ -2170,7 +2170,7 @@ define i1 @fcmp_oeq_posinf_or_ult_zero_f16_daz(half %x) #1 {
define i1 @fcmp_ueq_posinf_or_ule_zero_f16(half %x) {
; CHECK-LABEL: @fcmp_ueq_posinf_or_ule_zero_f16(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 639)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (nan inf zero nsub nnorm) */ i32 639)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%cmpinf = fcmp ueq half %x, 0xH7C00
@@ -2207,7 +2207,7 @@ define i1 @fcmp_oeq_posinf_or_ule_zero_f16_daz(half %x) #1 {
define i1 @fcmp_ueq_posinf_or_olt_zero_f16(half %x) {
; CHECK-LABEL: @fcmp_ueq_posinf_or_olt_zero_f16(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 543)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], /* (nan inf nsub nnorm) */ i32 543)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%cmpinf = fcmp ueq half %x, 0xH7C00
diff --git a/llvm/test/Transforms/InstCombine/fabs.ll b/llvm/test/Transforms/InstCombine/fabs.ll
index 2425251207604..52a9ce7aab2bd 100644
--- a/llvm/test/Transforms/InstCombine/fabs.ll
+++ b/llvm/test/Transforms/InstCombine/fabs.ll
@@ -1476,7 +1476,7 @@ define float @test_fabs_nsz_used_by_maxnum(float %x, float %y) {
define i1 @test_fabs_used_is_fpclass_pnorm_or_nan(float %x) {
; CHECK-LABEL: @test_fabs_used_is_fpclass_pnorm_or_nan(
-; CHECK-NEXT: [[IS_FPCLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 267)
+; CHECK-NEXT: [[IS_FPCLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (nan norm) */ i32 267)
; CHECK-NEXT: ret i1 [[IS_FPCLASS]]
;
%cmp = fcmp oge float %x, 0.000000e+00
@@ -1488,7 +1488,7 @@ define i1 @test_fabs_used_is_fpclass_pnorm_or_nan(float %x) {
define i1 @test_fabs_used_is_fpclass_zero_or_pinf(float %x) {
; CHECK-LABEL: @test_fabs_used_is_fpclass_zero_or_pinf(
-; CHECK-NEXT: [[IS_FPCLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 612)
+; CHECK-NEXT: [[IS_FPCLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (inf zero) */ i32 612)
; CHECK-NEXT: ret i1 [[IS_FPCLASS]]
;
%cmp = fcmp oge float %x, 0.000000e+00
@@ -1817,7 +1817,7 @@ define i1 @test_fabs_used_is_fpclass_pzero(float %x) {
; CHECK-NEXT: [[CMP:%.*]] = fcmp oge float [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[NEG:%.*]] = fneg float [[X]]
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], float [[X]], float [[NEG]]
-; CHECK-NEXT: [[IS_FPCLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[SEL]], i32 64)
+; CHECK-NEXT: [[IS_FPCLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[SEL]], /* (pzero) */ i32 64)
; CHECK-NEXT: ret i1 [[IS_FPCLASS]]
;
%cmp = fcmp oge float %x, 0.000000e+00
diff --git a/llvm/test/Transforms/InstCombine/fadd.ll b/llvm/test/Transforms/InstCombine/fadd.ll
index 0291fdcdd17cd..2311685db410d 100644
--- a/llvm/test/Transforms/InstCombine/fadd.ll
+++ b/llvm/test/Transforms/InstCombine/fadd.ll
@@ -1194,7 +1194,7 @@ define <2 x i1> @fadd_vector_neg_normal_not_zero_or_subnormal(<2 x float> %a) {
define i1 @fadd_unknown_lhs_normal_rhs(float %a) {
; CHECK-LABEL: @fadd_unknown_lhs_normal_rhs(
; CHECK-NEXT: [[ADD:%.*]] = fadd float [[A:%.*]], 1.000000e+00
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ADD]], i32 208)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ADD]], /* (pzero sub) */ i32 208)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%add = fadd float %a, 1.0
@@ -1208,7 +1208,7 @@ define i1 @fadd_pos_lhs_negative_rhs(float %a) {
; CHECK-LABEL: @fadd_pos_lhs_negative_rhs(
; CHECK-NEXT: [[ABS:%.*]] = call float @llvm.fabs.f32(float [[A:%.*]])
; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ABS]], -1.000000e+00
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ADD]], i32 208)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ADD]], /* (pzero sub) */ i32 208)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%abs = call float @llvm.fabs.f32(float %a)
diff --git a/llvm/test/Transforms/InstCombine/fpclass-check-idioms.ll b/llvm/test/Transforms/InstCombine/fpclass-check-idioms.ll
index 0f714701b81e2..c6b025dcf6002 100644
--- a/llvm/test/Transforms/InstCombine/fpclass-check-idioms.ll
+++ b/llvm/test/Transforms/InstCombine/fpclass-check-idioms.ll
@@ -17,7 +17,7 @@ define i1 @f32_fcnan_fcinf(float %a) {
define i1 @f32_fcnan_fcinf_strictfp(float %a) strictfp {
; CHECK-LABEL: define i1 @f32_fcnan_fcinf_strictfp(
; CHECK-SAME: float [[A:%.*]]) #[[ATTR0:[0-9]+]] {
-; CHECK-NEXT: [[CMP:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 519)
+; CHECK-NEXT: [[CMP:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], /* (nan inf) */ i32 519)
; CHECK-NEXT: ret i1 [[CMP]]
;
%i32 = bitcast float %a to i32
@@ -42,7 +42,7 @@ define i1 @f32_not_fcnan_fcinf(float %a) {
define i1 @f32_not_fcnan_fcinf_strictfp(float %a) strictfp {
; CHECK-LABEL: define i1 @f32_not_fcnan_fcinf_strictfp(
; CHECK-SAME: float [[A:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CMP:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 504)
+; CHECK-NEXT: [[CMP:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], /* (zero sub norm) */ i32 504)
; CHECK-NEXT: ret i1 [[CMP]]
;
%i32 = bitcast float %a to i32
@@ -67,7 +67,7 @@ define i1 @f64_fcnan_fcinf(double %a) {
define i1 @f64_fcnan_fcinf_strictfp(double %a) strictfp {
; CHECK-LABEL: define i1 @f64_fcnan_fcinf_strictfp(
; CHECK-SAME: double [[A:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CMP:%.*]] = call i1 @llvm.is.fpclass.f64(double [[A]], i32 519)
+; CHECK-NEXT: [[CMP:%.*]] = call i1 @llvm.is.fpclass.f64(double [[A]], /* (nan inf) */ i32 519)
; CHECK-NEXT: ret i1 [[CMP]]
;
%i64 = bitcast double %a to i64
@@ -92,7 +92,7 @@ define i1 @f32_fcinf(float %a) {
define i1 @f32_fcinf_strictfp(float %a) strictfp {
; CHECK-LABEL: define i1 @f32_fcinf_strictfp(
; CHECK-SAME: float [[A:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CMP:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 516)
+; CHECK-NEXT: [[CMP:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], /* (inf) */ i32 516)
; CHECK-NEXT: ret i1 [[CMP]]
;
%i32 = bitcast float %a to i32
@@ -115,7 +115,7 @@ define i1 @f32_fcposinf(float %a) {
define i1 @f32_fcposinf_strictfp(float %a) strictfp {
; CHECK-LABEL: define i1 @f32_fcposinf_strictfp(
; CHECK-SAME: float [[A:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CMP:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 512)
+; CHECK-NEXT: [[CMP:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], /* (pinf) */ i32 512)
; CHECK-NEXT: ret i1 [[CMP]]
;
%i32 = bitcast float %a to i32
@@ -137,7 +137,7 @@ define i1 @f32_fcneginf(float %a) {
define i1 @f32_fcneginf_strictfp(float %a) strictfp {
; CHECK-LABEL: define i1 @f32_fcneginf_strictfp(
; CHECK-SAME: float [[A:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CMP:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 4)
+; CHECK-NEXT: [[CMP:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], /* (ninf) */ i32 4)
; CHECK-NEXT: ret i1 [[CMP]]
;
%i32 = bitcast float %a to i32
@@ -148,7 +148,7 @@ define i1 @f32_fcneginf_strictfp(float %a) strictfp {
define i1 @f32_fcposzero(float %a) {
; CHECK-LABEL: define i1 @f32_fcposzero(
; CHECK-SAME: float [[A:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 64)
+; CHECK-NEXT: [[CMP:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], /* (pzero) */ i32 64)
; CHECK-NEXT: ret i1 [[CMP]]
;
%i32 = bitcast float %a to i32
@@ -159,7 +159,7 @@ define i1 @f32_fcposzero(float %a) {
define i1 @f32_fcposzero_strictfp(float %a) strictfp {
; CHECK-LABEL: define i1 @f32_fcposzero_strictfp(
; CHECK-SAME: float [[A:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CMP:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 64)
+; CHECK-NEXT: [[CMP:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], /* (pzero) */ i32 64)
; CHECK-NEXT: ret i1 [[CMP]]
;
%i32 = bitcast float %a to i32
@@ -170,7 +170,7 @@ define i1 @f32_fcposzero_strictfp(float %a) strictfp {
define i1 @f32_fcnegzero(float %a) {
; CHECK-LABEL: define i1 @f32_fcnegzero(
; CHECK-SAME: float [[A:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 32)
+; CHECK-NEXT: [[CMP:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], /* (nzero) */ i32 32)
; CHECK-NEXT: ret i1 [[CMP]]
;
%i32 = bitcast float %a to i32
@@ -181,7 +181,7 @@ define i1 @f32_fcnegzero(float %a) {
define i1 @f32_fcnegzero_strictfp(float %a) strictfp {
; CHECK-LABEL: define i1 @f32_fcnegzero_strictfp(
; CHECK-SAME: float [[A:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CMP:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 32)
+; CHECK-NEXT: [[CMP:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], /* (nzero) */ i32 32)
; CHECK-NEXT: ret i1 [[CMP]]
;
%i32 = bitcast float %a to i32
@@ -204,7 +204,7 @@ define i1 @f32_fczero(float %a) {
define i1 @f32_fczero_strictfp(float %a) strictfp {
; CHECK-LABEL: define i1 @f32_fczero_strictfp(
; CHECK-SAME: float [[A:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CMP:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 96)
+; CHECK-NEXT: [[CMP:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], /* (zero) */ i32 96)
; CHECK-NEXT: ret i1 [[CMP]]
;
%i32 = bitcast float %a to i32
@@ -265,7 +265,7 @@ define <2 x i1> @f32_fcnan_fcinf_vec(<2 x float> %a) {
define <2 x i1> @f32_fcnan_fcinf_vec_strictfp(<2 x float> %a) strictfp {
; CHECK-LABEL: define <2 x i1> @f32_fcnan_fcinf_vec_strictfp(
; CHECK-SAME: <2 x float> [[A:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CMP:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[A]], i32 519)
+; CHECK-NEXT: [[CMP:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[A]], /* (nan inf) */ i32 519)
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;
%i32 = bitcast <2 x float> %a to <2 x i32>
@@ -290,7 +290,7 @@ define <2 x i1> @f32_fcinf_vec(<2 x float> %a) {
define <2 x i1> @f32_fcinf_vec_strictfp(<2 x float> %a) strictfp {
; CHECK-LABEL: define <2 x i1> @f32_fcinf_vec_strictfp(
; CHECK-SAME: <2 x float> [[A:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CMP:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[A]], i32 516)
+; CHECK-NEXT: [[CMP:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[A]], /* (inf) */ i32 516)
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;
%i32 = bitcast <2 x float> %a to <2 x i32>
@@ -401,7 +401,7 @@ define i1 @f32_fcnan_fcinf_wrong_pred(float %a) {
define i1 @f32_fcnan_fcinf_wrong_pred_strictfp(float %a) strictfp {
; CHECK-LABEL: define i1 @f32_fcnan_fcinf_wrong_pred_strictfp(
; CHECK-SAME: float [[A:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[CMP:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 504)
+; CHECK-NEXT: [[CMP:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], /* (zero sub norm) */ i32 504)
; CHECK-NEXT: ret i1 [[CMP]]
;
%i32 = bitcast float %a to i32
@@ -569,7 +569,7 @@ define i1 @f32_fcnan_fcinf_noimplicitfloat_strictfp(float %a) strictfp #0 {
define i1 @f32_fcsubnormal_fczero(float %a) {
; CHECK-LABEL: define i1 @f32_fcsubnormal_fczero(
; CHECK-SAME: float [[A:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 240)
+; CHECK-NEXT: [[CMP:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], /* (zero sub) */ i32 240)
; CHECK-NEXT: ret i1 [[CMP]]
;
%i32 = bitcast float %a to i32
@@ -581,7 +581,7 @@ define i1 @f32_fcsubnormal_fczero(float %a) {
define i1 @f32_not_fcsubnormal_fczero(float %a) {
; CHECK-LABEL: define i1 @f32_not_fcsubnormal_fczero(
; CHECK-SAME: float [[A:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 783)
+; CHECK-NEXT: [[CMP:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], /* (nan inf norm) */ i32 783)
; CHECK-NEXT: ret i1 [[CMP]]
;
%i32 = bitcast float %a to i32
@@ -593,7 +593,7 @@ define i1 @f32_not_fcsubnormal_fczero(float %a) {
define <2 x i1> @f64_fcsubnormal_fczero_vec(<2 x double> %a) {
; CHECK-LABEL: define <2 x i1> @f64_fcsubnormal_fczero_vec(
; CHECK-SAME: <2 x double> [[A:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f64(<2 x double> [[A]], i32 240)
+; CHECK-NEXT: [[CMP:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f64(<2 x double> [[A]], /* (zero sub) */ i32 240)
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;
%i64 = bitcast <2 x double> %a to <2 x i64>
@@ -605,7 +605,7 @@ define <2 x i1> @f64_fcsubnormal_fczero_vec(<2 x double> %a) {
define <2 x i1> @f64_no_fcsubnormal_fczero_vec(<2 x double> %a) {
; CHECK-LABEL: define <2 x i1> @f64_no_fcsubnormal_fczero_vec(
; CHECK-SAME: <2 x double> [[A:%.*]]) {
-; CHECK-NEXT: [[CMP:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f64(<2 x double> [[A]], i32 783)
+; CHECK-NEXT: [[CMP:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f64(<2 x double> [[A]], /* (nan inf norm) */ i32 783)
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;
%i64 = bitcast <2 x double> %a to <2 x i64>
@@ -1016,7 +1016,7 @@ define i1 @isnan_idiom_ppc_fp128(ppc_fp128 %x) {
define i1 @fpclass_test_normal(float %num) {
; CHECK-LABEL: define i1 @fpclass_test_normal(
; CHECK-SAME: float [[NUM:%.*]]) {
-; CHECK-NEXT: [[RES:%.*]] = call i1 @llvm.is.fpclass.f32(float [[NUM]], i32 264)
+; CHECK-NEXT: [[RES:%.*]] = call i1 @llvm.is.fpclass.f32(float [[NUM]], /* (norm) */ i32 264)
; CHECK-NEXT: ret i1 [[RES]]
;
%cast = bitcast float %num to i32
@@ -1030,7 +1030,7 @@ define i1 @fpclass_test_normal(float %num) {
define i1 @fpclass_test_normal_half(half %num) {
; CHECK-LABEL: define i1 @fpclass_test_normal_half(
; CHECK-SAME: half [[NUM:%.*]]) {
-; CHECK-NEXT: [[RES:%.*]] = call i1 @llvm.is.fpclass.f16(half [[NUM]], i32 264)
+; CHECK-NEXT: [[RES:%.*]] = call i1 @llvm.is.fpclass.f16(half [[NUM]], /* (norm) */ i32 264)
; CHECK-NEXT: ret i1 [[RES]]
;
%cast = bitcast half %num to i16
@@ -1044,7 +1044,7 @@ define i1 @fpclass_test_normal_half(half %num) {
define <2 x i1> @fpclass_test_normal_half_vec(<2 x half> %num) {
; CHECK-LABEL: define <2 x i1> @fpclass_test_normal_half_vec(
; CHECK-SAME: <2 x half> [[NUM:%.*]]) {
-; CHECK-NEXT: [[RES:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[NUM]], i32 264)
+; CHECK-NEXT: [[RES:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[NUM]], /* (norm) */ i32 264)
; CHECK-NEXT: ret <2 x i1> [[RES]]
;
%cast = bitcast <2 x half> %num to <2 x i16>
@@ -1058,7 +1058,7 @@ define <2 x i1> @fpclass_test_normal_half_vec(<2 x half> %num) {
define i1 @fpclass_test_not_normal(float %num) {
; CHECK-LABEL: define i1 @fpclass_test_not_normal(
; CHECK-SAME: float [[NUM:%.*]]) {
-; CHECK-NEXT: [[RES:%.*]] = call i1 @llvm.is.fpclass.f32(float [[NUM]], i32 759)
+; CHECK-NEXT: [[RES:%.*]] = call i1 @llvm.is.fpclass.f32(float [[NUM]], /* (nan inf zero sub) */ i32 759)
; CHECK-NEXT: ret i1 [[RES]]
;
%cast = bitcast float %num to i32
@@ -1072,7 +1072,7 @@ define i1 @fpclass_test_not_normal(float %num) {
define <2 x i1> @fpclass_test_not_normal_vec(<2 x float> %num) {
; CHECK-LABEL: define <2 x i1> @fpclass_test_not_normal_vec(
; CHECK-SAME: <2 x float> [[NUM:%.*]]) {
-; CHECK-NEXT: [[RES:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[NUM]], i32 759)
+; CHECK-NEXT: [[RES:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[NUM]], /* (nan inf zero sub) */ i32 759)
; CHECK-NEXT: ret <2 x i1> [[RES]]
;
%cast = bitcast <2 x float> %num to <2 x i32>
@@ -1086,7 +1086,7 @@ define <2 x i1> @fpclass_test_not_normal_vec(<2 x float> %num) {
define i1 @fpclass_test_normal_commuted(float %num) {
; CHECK-LABEL: define i1 @fpclass_test_normal_commuted(
; CHECK-SAME: float [[NUM:%.*]]) {
-; CHECK-NEXT: [[RES:%.*]] = call i1 @llvm.is.fpclass.f32(float [[NUM]], i32 264)
+; CHECK-NEXT: [[RES:%.*]] = call i1 @llvm.is.fpclass.f32(float [[NUM]], /* (norm) */ i32 264)
; CHECK-NEXT: ret i1 [[RES]]
;
%cast = bitcast float %num to i32
@@ -1120,7 +1120,7 @@ define i1 @fpclass_test_normal_fp128(ppc_fp128 %x) {
define i1 @fpclass_test_normal_mismatch_pred(float %num) {
; CHECK-LABEL: define i1 @fpclass_test_normal_mismatch_pred(
; CHECK-SAME: float [[NUM:%.*]]) {
-; CHECK-NEXT: [[TEST2:%.*]] = call i1 @llvm.is.fpclass.f32(float [[NUM]], i32 240)
+; CHECK-NEXT: [[TEST2:%.*]] = call i1 @llvm.is.fpclass.f32(float [[NUM]], /* (zero sub) */ i32 240)
; CHECK-NEXT: ret i1 [[TEST2]]
;
%cast = bitcast float %num to i32
diff --git a/llvm/test/Transforms/InstCombine/fpclass-from-dom-cond.ll b/llvm/test/Transforms/InstCombine/fpclass-from-dom-cond.ll
index 610092901f5e9..d4f4dde646e65 100644
--- a/llvm/test/Transforms/InstCombine/fpclass-from-dom-cond.ll
+++ b/llvm/test/Transforms/InstCombine/fpclass-from-dom-cond.ll
@@ -10,7 +10,7 @@ define i1 @test1(float %x) {
; CHECK: if.then:
; CHECK-NEXT: ret i1 false
; CHECK: if.else:
-; CHECK-NEXT: [[RET:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X]], i32 780)
+; CHECK-NEXT: [[RET:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X]], /* (inf norm) */ i32 780)
; CHECK-NEXT: ret i1 [[RET]]
;
entry:
@@ -131,7 +131,7 @@ define i1 @test5(double %x, i1 %cond) {
; CHECK: if.then:
; CHECK-NEXT: ret i1 false
; CHECK: if.end:
-; CHECK-NEXT: [[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f64(double [[X]], i32 408)
+; CHECK-NEXT: [[TMP0:%.*]] = tail call i1 @llvm.is.fpclass.f64(double [[X]], /* (sub norm) */ i32 408)
; CHECK-NEXT: br label [[EXIT]]
; CHECK: exit:
; CHECK-NEXT: [[RET:%.*]] = phi i1 [ true, [[ENTRY:%.*]] ], [ [[TMP0]], [[IF_END]] ]
@@ -183,13 +183,13 @@ land.end:
define i1 @test7(float %x) {
; CHECK-LABEL: define i1 @test7(
; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: [[COND:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X]], i32 345)
+; CHECK-NEXT: [[COND:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X]], /* (snan pzero nsub norm) */ i32 345)
; CHECK-NEXT: br i1 [[COND]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
; CHECK: if.then:
-; CHECK-NEXT: [[RET1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X]], i32 328)
+; CHECK-NEXT: [[RET1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X]], /* (pzero norm) */ i32 328)
; CHECK-NEXT: ret i1 [[RET1]]
; CHECK: if.else:
-; CHECK-NEXT: [[RET2:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X]], i32 128)
+; CHECK-NEXT: [[RET2:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X]], /* (psub) */ i32 128)
; CHECK-NEXT: ret i1 [[RET2]]
;
%cond = call i1 @llvm.is.fpclass.f32(float %x, i32 345)
@@ -212,7 +212,7 @@ define i1 @test8(float %x) {
; CHECK: if.then:
; CHECK-NEXT: ret i1 true
; CHECK: if.else:
-; CHECK-NEXT: [[RET2:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X]], i32 59)
+; CHECK-NEXT: [[RET2:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X]], /* (nan nzero nsub nnorm) */ i32 59)
; CHECK-NEXT: ret i1 [[RET2]]
;
%abs = call float @llvm.fabs.f32(float %x)
@@ -297,7 +297,7 @@ define i1 @test12_or(float %x, i1 %cond2) {
; CHECK: if.then:
; CHECK-NEXT: ret i1 false
; CHECK: if.else:
-; CHECK-NEXT: [[RET:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X]], i32 780)
+; CHECK-NEXT: [[RET:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X]], /* (inf norm) */ i32 780)
; CHECK-NEXT: ret i1 [[RET]]
;
entry:
@@ -324,7 +324,7 @@ define i1 @test1_no_dominating(float %x, i1 %c) {
; CHECK: if.then:
; CHECK-NEXT: ret i1 false
; CHECK: if.else:
-; CHECK-NEXT: [[RET:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X]], i32 783)
+; CHECK-NEXT: [[RET:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X]], /* (nan inf norm) */ i32 783)
; CHECK-NEXT: ret i1 [[RET]]
;
entry0:
@@ -492,7 +492,7 @@ define i1 @pr118257_is_fpclass(half %v0, half %v1) {
; CHECK-SAME: half [[V0:%.*]], half [[V1:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP1:%.*]] = fcmp une half [[V1]], 0.000000e+00
-; CHECK-NEXT: [[CMP2:%.*]] = call i1 @llvm.is.fpclass.f16(half [[V0]], i32 35)
+; CHECK-NEXT: [[CMP2:%.*]] = call i1 @llvm.is.fpclass.f16(half [[V0]], /* (nan nzero) */ i32 35)
; CHECK-NEXT: [[OR_COND:%.*]] = or i1 [[CMP1]], [[CMP2]]
; CHECK-NEXT: br i1 [[OR_COND]], label [[IF_END:%.*]], label [[IF_ELSE:%.*]]
; CHECK: if.else:
diff --git a/llvm/test/Transforms/InstCombine/freeze-fp-ops.ll b/llvm/test/Transforms/InstCombine/freeze-fp-ops.ll
index 1caf7ec87016e..1837c0376067a 100644
--- a/llvm/test/Transforms/InstCombine/freeze-fp-ops.ll
+++ b/llvm/test/Transforms/InstCombine/freeze-fp-ops.ll
@@ -580,7 +580,7 @@ define i1 @freeze_isfpclass(float %arg0) {
; CHECK-LABEL: define i1 @freeze_isfpclass(
; CHECK-SAME: float [[ARG0:%.*]]) {
; CHECK-NEXT: [[ARG0_FR:%.*]] = freeze float [[ARG0]]
-; CHECK-NEXT: [[OP:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG0_FR]], i32 27)
+; CHECK-NEXT: [[OP:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG0_FR]], /* (nan nsub nnorm) */ i32 27)
; CHECK-NEXT: ret i1 [[OP]]
;
%op = call i1 @llvm.is.fpclass.f32(float %arg0, i32 27)
diff --git a/llvm/test/Transforms/InstCombine/freeze-phi.ll b/llvm/test/Transforms/InstCombine/freeze-phi.ll
index 62bb9dc31b76b..7daff25747841 100644
--- a/llvm/test/Transforms/InstCombine/freeze-phi.ll
+++ b/llvm/test/Transforms/InstCombine/freeze-phi.ll
@@ -218,7 +218,7 @@ D:
define float @pr161524(float noundef %arg) {
; CHECK-LABEL: @pr161524(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[COND:%.*]] = tail call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 144)
+; CHECK-NEXT: [[COND:%.*]] = tail call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (sub) */ i32 144)
; CHECK-NEXT: br i1 [[COND]], label [[IF_THEN:%.*]], label [[IF_EXIT:%.*]]
; CHECK: if.then:
; CHECK-NEXT: [[FADD:%.*]] = fadd float [[ARG]], 1.000000e+00
diff --git a/llvm/test/Transforms/InstCombine/is_fpclass.ll b/llvm/test/Transforms/InstCombine/is_fpclass.ll
index 62b456a6e81a2..4f338f0df50e9 100644
--- a/llvm/test/Transforms/InstCombine/is_fpclass.ll
+++ b/llvm/test/Transforms/InstCombine/is_fpclass.ll
@@ -107,7 +107,7 @@ define <2 x i1> @test_class_isnan_v2f32(<2 x float> %x) {
define i1 @test_class_isnan_f32_strict(float %x) strictfp {
; CHECK-LABEL: @test_class_isnan_f32_strict(
-; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 3) #[[ATTR0:[0-9]+]]
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (nan) */ i32 3) #[[ATTR0:[0-9]+]]
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.is.fpclass.f32(float %x, i32 3) strictfp
@@ -134,7 +134,7 @@ define <2 x i1> @test_class_is_p0_n0_v2f32(<2 x float> %x) {
define <2 x i1> @test_class_is_p0_n0_v2f32_daz(<2 x float> %x) denormal_fpenv(float: ieee|preservesign) {
; CHECK-LABEL: @test_class_is_p0_n0_v2f32_daz(
-; CHECK-NEXT: [[VAL:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[X:%.*]], i32 96)
+; CHECK-NEXT: [[VAL:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[X:%.*]], /* (zero) */ i32 96)
; CHECK-NEXT: ret <2 x i1> [[VAL]]
;
%val = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, i32 96) ; fcZero
@@ -143,7 +143,7 @@ define <2 x i1> @test_class_is_p0_n0_v2f32_daz(<2 x float> %x) denormal_fpenv(fl
define <2 x i1> @test_class_is_p0_n0_v2f32_dynamic(<2 x float> %x) denormal_fpenv(float: ieee|dynamic) {
; CHECK-LABEL: @test_class_is_p0_n0_v2f32_dynamic(
-; CHECK-NEXT: [[VAL:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[X:%.*]], i32 96)
+; CHECK-NEXT: [[VAL:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[X:%.*]], /* (zero) */ i32 96)
; CHECK-NEXT: ret <2 x i1> [[VAL]]
;
%val = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, i32 96) ; fcZero
@@ -170,7 +170,7 @@ define <2 x i1> @test_class_is_p0_n0_or_nan_v2f32(<2 x float> %x) {
define i1 @test_class_is_p0_n0_or_nan_f32_daz(float %x) denormal_fpenv(float: ieee|preservesign) {
; CHECK-LABEL: @test_class_is_p0_n0_or_nan_f32_daz(
-; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 99)
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (nan zero) */ i32 99)
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.is.fpclass.f32(float %x, i32 99) ; fcZero|fcNan
@@ -179,7 +179,7 @@ define i1 @test_class_is_p0_n0_or_nan_f32_daz(float %x) denormal_fpenv(float: ie
define <2 x i1> @test_class_is_p0_n0_or_nan_v2f32_daz(<2 x float> %x) denormal_fpenv(float: ieee|preservesign) {
; CHECK-LABEL: @test_class_is_p0_n0_or_nan_v2f32_daz(
-; CHECK-NEXT: [[VAL:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[X:%.*]], i32 99)
+; CHECK-NEXT: [[VAL:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[X:%.*]], /* (nan zero) */ i32 99)
; CHECK-NEXT: ret <2 x i1> [[VAL]]
;
%val = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, i32 99) ; fcZero|fcNan
@@ -188,7 +188,7 @@ define <2 x i1> @test_class_is_p0_n0_or_nan_v2f32_daz(<2 x float> %x) denormal_f
define i1 @test_class_is_p0_n0_or_sub_or_nan_f32(float %x) {
; CHECK-LABEL: @test_class_is_p0_n0_or_sub_or_nan_f32(
-; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 243)
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (nan zero sub) */ i32 243)
; CHECK-NEXT: ret i1 [[VAL]]
;
;`
@@ -198,7 +198,7 @@ define i1 @test_class_is_p0_n0_or_sub_or_nan_f32(float %x) {
define <2 x i1> @test_class_is_p0_n0_or_sub_or_nan_v2f32(<2 x float> %x) {
; CHECK-LABEL: @test_class_is_p0_n0_or_sub_or_nan_v2f32(
-; CHECK-NEXT: [[VAL:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[X:%.*]], i32 243)
+; CHECK-NEXT: [[VAL:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[X:%.*]], /* (nan zero sub) */ i32 243)
; CHECK-NEXT: ret <2 x i1> [[VAL]]
;
%val = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, i32 243) ; fcZero|fcNan|fcSubnormal
@@ -225,7 +225,7 @@ define <2 x i1> @test_class_is_p0_n0_or_sub_or_nan_v2f32_daz(<2 x float> %x) den
define i1 @test_class_is_p0_n0_or_sub_or_snan_f32_daz(float %x) denormal_fpenv(float: ieee|preservesign) {
; CHECK-LABEL: @test_class_is_p0_n0_or_sub_or_snan_f32_daz(
-; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 241)
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (snan zero sub) */ i32 241)
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.is.fpclass.f32(float %x, i32 241) ; fcZero|fcSNan|fcSubnormal
@@ -234,7 +234,7 @@ define i1 @test_class_is_p0_n0_or_sub_or_snan_f32_daz(float %x) denormal_fpenv(f
define i1 @test_class_is_p0_n0_or_sub_or_qnan_f32_daz(float %x) denormal_fpenv(float: ieee|preservesign) {
; CHECK-LABEL: @test_class_is_p0_n0_or_sub_or_qnan_f32_daz(
-; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 242)
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (qnan zero sub) */ i32 242)
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.is.fpclass.f32(float %x, i32 242) ; fcZero|fcQNan|fcSubnormal
@@ -252,7 +252,7 @@ define i1 @test_class_is_not_p0_n0_or_nan_f32(float %x) {
define i1 @test_class_is_not_p0_n0_or_qnan_f32(float %x) {
; CHECK-LABEL: @test_class_is_not_p0_n0_or_qnan_f32(
-; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 926)
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (qnan inf sub norm) */ i32 926)
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.is.fpclass.f32(float %x, i32 926) ; ~fcZero & ~fcSNan & fcAllFlags
@@ -261,7 +261,7 @@ define i1 @test_class_is_not_p0_n0_or_qnan_f32(float %x) {
define i1 @test_class_is_not_p0_n0_or_snan_f32(float %x) {
; CHECK-LABEL: @test_class_is_not_p0_n0_or_snan_f32(
-; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 925)
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (snan inf sub norm) */ i32 925)
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.is.fpclass.f32(float %x, i32 925) ; ~fcZero & ~fcQNan & fcAllFlags
@@ -270,7 +270,7 @@ define i1 @test_class_is_not_p0_n0_or_snan_f32(float %x) {
define i1 @test_class_is_not_p0_n0_or_nan_f32_daz(float %x) denormal_fpenv(float: ieee|preservesign) {
; CHECK-LABEL: @test_class_is_not_p0_n0_or_nan_f32_daz(
-; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 924)
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (inf sub norm) */ i32 924)
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.is.fpclass.f32(float %x, i32 924) ; ~fcZero & ~fcNan & fcAllFlags
@@ -279,7 +279,7 @@ define i1 @test_class_is_not_p0_n0_or_nan_f32_daz(float %x) denormal_fpenv(float
define i1 @test_class_is_not_p0_n0_or_sub_or_nan_f32(float %x) {
; CHECK-LABEL: @test_class_is_not_p0_n0_or_sub_or_nan_f32(
-; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 783)
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (nan inf norm) */ i32 783)
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.is.fpclass.f32(float %x, i32 783) ; ~(fcZero|fcSubnormal) | fcNan
@@ -297,7 +297,7 @@ define i1 @test_class_is_not_p0_n0_or_sub_or_nan_f32_daz(float %x) denormal_fpen
define i1 @test_class_is_not_p0_n0_or_sub_and_not_nan_f32(float %x) {
; CHECK-LABEL: @test_class_is_not_p0_n0_or_sub_and_not_nan_f32(
-; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 780)
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (inf norm) */ i32 780)
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.is.fpclass.f32(float %x, i32 780) ; ~(fcZero|fcSubnormal) & ~fcNan & fcAllFlags
@@ -333,7 +333,7 @@ define <2 x i1> @test_class_is_not_p0_n0_v2f32(<2 x float> %x) {
define i1 @test_class_is_not_p0_n0_f32_strict(float %x) strictfp {
; CHECK-LABEL: @test_class_is_not_p0_n0_f32_strict(
-; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 927) #[[ATTR0]]
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (nan inf sub norm) */ i32 927) #[[ATTR0]]
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.is.fpclass.f32(float %x, i32 927) strictfp ; ~fcZero & fcAllFlags
@@ -342,7 +342,7 @@ define i1 @test_class_is_not_p0_n0_f32_strict(float %x) strictfp {
define i1 @test_class_is_not_p0_n0_f32_daz(float %x) denormal_fpenv(ieee|preservesign) {
; CHECK-LABEL: @test_class_is_not_p0_n0_f32_daz(
-; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 927)
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (nan inf sub norm) */ i32 927)
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.is.fpclass.f32(float %x, i32 927) ; ~fcZero & fcAllFlags
@@ -351,7 +351,7 @@ define i1 @test_class_is_not_p0_n0_f32_daz(float %x) denormal_fpenv(ieee|preserv
define i1 @test_class_is_not_p0_n0_f32_dynamic(float %x) denormal_fpenv(ieee|dynamic) {
; CHECK-LABEL: @test_class_is_not_p0_n0_f32_dynamic(
-; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 927)
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (nan inf sub norm) */ i32 927)
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.is.fpclass.f32(float %x, i32 927) ; ~fcZero & fcAllFlags
@@ -378,7 +378,7 @@ define i1 @test_class_is_not_p0_n0_psub_nsub_f32_dapz(float %x) denormal_fpenv(i
define i1 @test_class_is_not_p0_n0_psub_nsub_f32_dynamic(float %x) denormal_fpenv(ieee|dynamic) {
; CHECK-LABEL: @test_class_is_not_p0_n0_psub_nsub_f32_dynamic(
-; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 783)
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (nan inf norm) */ i32 783)
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.is.fpclass.f32(float %x, i32 783) ; ~(fcZero|fcSubnormal) & fcAllFlags
@@ -387,7 +387,7 @@ define i1 @test_class_is_not_p0_n0_psub_nsub_f32_dynamic(float %x) denormal_fpen
define i1 @test_class_is_p0_n0_f32_strict(float %x) strictfp {
; CHECK-LABEL: @test_class_is_p0_n0_f32_strict(
-; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 96) #[[ATTR0]]
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (zero) */ i32 96) #[[ATTR0]]
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.is.fpclass.f32(float %x, i32 96) strictfp
@@ -396,7 +396,7 @@ define i1 @test_class_is_p0_n0_f32_strict(float %x) strictfp {
define i1 @test_class_is_p0_n0_f32_daz(float %x) denormal_fpenv(ieee|preservesign) {
; CHECK-LABEL: @test_class_is_p0_n0_f32_daz(
-; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 96)
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (zero) */ i32 96)
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.is.fpclass.f32(float %x, i32 96) ; fcZero
@@ -405,7 +405,7 @@ define i1 @test_class_is_p0_n0_f32_daz(float %x) denormal_fpenv(ieee|preservesig
define i1 @test_class_is_p0_n0_f32_dapz(float %x) denormal_fpenv(ieee|positivezero) {
; CHECK-LABEL: @test_class_is_p0_n0_f32_dapz(
-; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 96)
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (zero) */ i32 96)
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.is.fpclass.f32(float %x, i32 96) ; fcZero
@@ -414,7 +414,7 @@ define i1 @test_class_is_p0_n0_f32_dapz(float %x) denormal_fpenv(ieee|positiveze
define i1 @test_class_is_p0_n0_psub_nsub_f32(float %x) {
; CHECK-LABEL: @test_class_is_p0_n0_psub_nsub_f32(
-; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 240)
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (zero sub) */ i32 240)
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.is.fpclass.f32(float %x, i32 240) ; fcZero | fcSubnormal
@@ -441,7 +441,7 @@ define i1 @test_class_is_p0_n0_psub_nsub_f32_dapz(float %x) denormal_fpenv(ieee|
define i1 @test_class_is_p0_n0_psub_nsub_f32_dynamic(float %x) denormal_fpenv(ieee|dynamic) {
; CHECK-LABEL: @test_class_is_p0_n0_psub_nsub_f32_dynamic(
-; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 240)
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (zero sub) */ i32 240)
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.is.fpclass.f32(float %x, i32 240) ; fcZero | fcSubnormal
@@ -450,7 +450,7 @@ define i1 @test_class_is_p0_n0_psub_nsub_f32_dynamic(float %x) denormal_fpenv(ie
define <2 x i1> @test_class_is_p0_n0_psub_nsub_v2f32(<2 x float> %x) {
; CHECK-LABEL: @test_class_is_p0_n0_psub_nsub_v2f32(
-; CHECK-NEXT: [[VAL:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[X:%.*]], i32 240)
+; CHECK-NEXT: [[VAL:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[X:%.*]], /* (zero sub) */ i32 240)
; CHECK-NEXT: ret <2 x i1> [[VAL]]
;
%val = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, i32 240) ; fcZero | fcSubnormal
@@ -477,7 +477,7 @@ define <2 x i1> @test_class_is_p0_n0_psub_nsub_v2f32_dapz(<2 x float> %x) denorm
define <2 x i1> @test_class_is_p0_n0_psub_nsub_v2f32_dynamic(<2 x float> %x) denormal_fpenv(ieee|dynamic) {
; CHECK-LABEL: @test_class_is_p0_n0_psub_nsub_v2f32_dynamic(
-; CHECK-NEXT: [[VAL:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[X:%.*]], i32 240)
+; CHECK-NEXT: [[VAL:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[X:%.*]], /* (zero sub) */ i32 240)
; CHECK-NEXT: ret <2 x i1> [[VAL]]
;
%val = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, i32 240) ; fcZero | fcSubnormal
@@ -570,7 +570,7 @@ define i1 @test_class_is_inf_or_nan_f32(float %x) {
define i1 @test_class_is_pinf_f32_strict(float %x) strictfp {
; CHECK-LABEL: @test_class_is_pinf_f32_strict(
-; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 512) #[[ATTR0]]
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (pinf) */ i32 512) #[[ATTR0]]
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.is.fpclass.f32(float %x, i32 512) strictfp ; fcPosInf
@@ -579,7 +579,7 @@ define i1 @test_class_is_pinf_f32_strict(float %x) strictfp {
define i1 @test_class_is_ninf_f32_strict(float %x) strictfp {
; CHECK-LABEL: @test_class_is_ninf_f32_strict(
-; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 4) #[[ATTR0]]
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (ninf) */ i32 4) #[[ATTR0]]
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.is.fpclass.f32(float %x, i32 4) strictfp ; fcNegInf
@@ -588,7 +588,7 @@ define i1 @test_class_is_ninf_f32_strict(float %x) strictfp {
define i1 @test_class_is_inf_f32_strict(float %x) strictfp {
; CHECK-LABEL: @test_class_is_inf_f32_strict(
-; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 516) #[[ATTR0]]
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (inf) */ i32 516) #[[ATTR0]]
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.is.fpclass.f32(float %x, i32 516) strictfp ; fcInf
@@ -597,7 +597,7 @@ define i1 @test_class_is_inf_f32_strict(float %x) strictfp {
define i1 @test_class_is_pinf_or_nan_f32_strict(float %x) strictfp {
; CHECK-LABEL: @test_class_is_pinf_or_nan_f32_strict(
-; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 515) #[[ATTR0]]
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (nan pinf) */ i32 515) #[[ATTR0]]
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.is.fpclass.f32(float %x, i32 515) strictfp ; fcPosInf|fcNan
@@ -606,7 +606,7 @@ define i1 @test_class_is_pinf_or_nan_f32_strict(float %x) strictfp {
define i1 @test_class_is_ninf_or_nan_f32_strict(float %x) strictfp {
; CHECK-LABEL: @test_class_is_ninf_or_nan_f32_strict(
-; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 7) #[[ATTR0]]
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (nan ninf) */ i32 7) #[[ATTR0]]
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.is.fpclass.f32(float %x, i32 7) strictfp ; fcNegInf|fcNan
@@ -615,7 +615,7 @@ define i1 @test_class_is_ninf_or_nan_f32_strict(float %x) strictfp {
define i1 @test_class_is_inf_or_nan_f32_strict(float %x) strictfp {
; CHECK-LABEL: @test_class_is_inf_or_nan_f32_strict(
-; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 519) #[[ATTR0]]
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (nan inf) */ i32 519) #[[ATTR0]]
; CHECK-NEXT: ret i1 [[VAL]]
;
%val = call i1 @llvm.is.fpclass.f32(float %x, i32 519) strictfp ; fcInf|fcNan
@@ -836,7 +836,7 @@ define i1 @test_class_is_nan_nnan_src(float %x) {
define i1 @test_class_is_nan_other_nnan_src(float %x) {
; CHECK-LABEL: @test_class_is_nan_other_nnan_src(
; CHECK-NEXT: [[NNAN:%.*]] = fadd nnan float [[X:%.*]], 1.000000e+00
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[NNAN]], i32 264)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[NNAN]], /* (norm) */ i32 264)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%nnan = fadd nnan float %x, 1.0
@@ -897,7 +897,7 @@ define i1 @test_class_is_pinf_ninf_src(float %x) {
define i1 @test_class_is_ninf_pinf_pnormal_ninf_src(float %x) {
; CHECK-LABEL: @test_class_is_ninf_pinf_pnormal_ninf_src(
; CHECK-NEXT: [[NINF:%.*]] = fadd ninf float [[X:%.*]], 1.000000e+00
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[NINF]], i32 256)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[NINF]], /* (pnorm) */ i32 256)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%ninf = fadd ninf float %x, 1.0
@@ -963,7 +963,7 @@ define i1 @test_class_not_is_inf_nan(float %x) {
define i1 @test_class_not_is_normal(float %x) {
; CHECK-LABEL: @test_class_not_is_normal(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 759)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (nan inf zero sub) */ i32 759)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %x, i32 264)
@@ -973,7 +973,7 @@ define i1 @test_class_not_is_normal(float %x) {
define i1 @test_class_xor_false(float %x) {
; CHECK-LABEL: @test_class_xor_false(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 33)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (snan nzero) */ i32 33)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %x, i32 33)
@@ -983,7 +983,7 @@ define i1 @test_class_xor_false(float %x) {
define <2 x i1> @test_class_not_vector(<2 x float> %x) {
; CHECK-LABEL: @test_class_not_vector(
-; CHECK-NEXT: [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[X:%.*]], i32 990)
+; CHECK-NEXT: [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[X:%.*]], /* (qnan inf pzero sub norm) */ i32 990)
; CHECK-NEXT: ret <2 x i1> [[CLASS]]
;
%class = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, i32 33)
@@ -993,7 +993,7 @@ define <2 x i1> @test_class_not_vector(<2 x float> %x) {
define <2 x i1> @test_class_xor_vector(<2 x float> %x) {
; CHECK-LABEL: @test_class_xor_vector(
-; CHECK-NEXT: [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[X:%.*]], i32 33)
+; CHECK-NEXT: [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[X:%.*]], /* (snan nzero) */ i32 33)
; CHECK-NEXT: [[NOT:%.*]] = xor <2 x i1> [[CLASS]], <i1 true, i1 false>
; CHECK-NEXT: ret <2 x i1> [[NOT]]
;
@@ -1058,7 +1058,7 @@ define i1 @test_fold_or_all_tests_class_f32_0(float %a) {
define i1 @test_fold_or_class_f32_1(float %a) {
; CHECK-LABEL: @test_fold_or_class_f32_1(
-; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A:%.*]], i32 12)
+; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A:%.*]], /* (ninf nnorm) */ i32 12)
; CHECK-NEXT: ret i1 [[CLASS1]]
;
%class0 = call i1 @llvm.is.fpclass.f32(float %a, i32 4)
@@ -1071,7 +1071,7 @@ define i1 @test_no_fold_or_class_f32_multi_use0(float %a, ptr %ptr) {
; CHECK-LABEL: @test_no_fold_or_class_f32_multi_use0(
; CHECK-NEXT: [[CLASS0:%.*]] = fcmp oeq float [[A:%.*]], -inf
; CHECK-NEXT: store i1 [[CLASS0]], ptr [[PTR:%.*]], align 1
-; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 8)
+; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], /* (nnorm) */ i32 8)
; CHECK-NEXT: [[OR:%.*]] = or i1 [[CLASS0]], [[CLASS1]]
; CHECK-NEXT: ret i1 [[OR]]
;
@@ -1085,7 +1085,7 @@ define i1 @test_no_fold_or_class_f32_multi_use0(float %a, ptr %ptr) {
define i1 @test_no_fold_or_class_f32_multi_use1(float %a, ptr %ptr) {
; CHECK-LABEL: @test_no_fold_or_class_f32_multi_use1(
; CHECK-NEXT: [[CLASS0:%.*]] = fcmp oeq float [[A:%.*]], -inf
-; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 8)
+; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], /* (nnorm) */ i32 8)
; CHECK-NEXT: store i1 [[CLASS1]], ptr [[PTR:%.*]], align 1
; CHECK-NEXT: [[OR:%.*]] = or i1 [[CLASS0]], [[CLASS1]]
; CHECK-NEXT: ret i1 [[OR]]
@@ -1111,7 +1111,7 @@ define i1 @test_fold_or_class_f32_2(float %a) {
define i1 @test_no_fold_or_class_f32_0(float %a, float %b) {
; CHECK-LABEL: @test_no_fold_or_class_f32_0(
; CHECK-NEXT: [[CLASS0:%.*]] = fcmp oeq float [[A:%.*]], -inf
-; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[B:%.*]], i32 8)
+; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[B:%.*]], /* (nnorm) */ i32 8)
; CHECK-NEXT: [[OR:%.*]] = or i1 [[CLASS0]], [[CLASS1]]
; CHECK-NEXT: ret i1 [[OR]]
;
@@ -1123,7 +1123,7 @@ define i1 @test_no_fold_or_class_f32_0(float %a, float %b) {
define <2 x i1> @test_fold_or_class_v2f32(<2 x float> %a) {
; CHECK-LABEL: @test_fold_or_class_v2f32(
-; CHECK-NEXT: [[CLASS1:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[A:%.*]], i32 12)
+; CHECK-NEXT: [[CLASS1:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[A:%.*]], /* (ninf nnorm) */ i32 12)
; CHECK-NEXT: ret <2 x i1> [[CLASS1]]
;
%class0 = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %a, i32 4)
@@ -1138,7 +1138,7 @@ define <2 x i1> @test_fold_or_class_v2f32(<2 x float> %a) {
define i1 @test_fold_and_class_f32_0(float %a) {
; CHECK-LABEL: @test_fold_and_class_f32_0(
-; CHECK-NEXT: [[CLASS0:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A:%.*]], i32 1)
+; CHECK-NEXT: [[CLASS0:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A:%.*]], /* (snan) */ i32 1)
; CHECK-NEXT: ret i1 [[CLASS0]]
;
%class0 = call i1 @llvm.is.fpclass.f32(float %a, i32 1)
@@ -1149,7 +1149,7 @@ define i1 @test_fold_and_class_f32_0(float %a) {
define i1 @test_fold_and3_class_f32_0(float %a) {
; CHECK-LABEL: @test_fold_and3_class_f32_0(
-; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A:%.*]], i32 2)
+; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A:%.*]], /* (qnan) */ i32 2)
; CHECK-NEXT: ret i1 [[CLASS1]]
;
%class0 = call i1 @llvm.is.fpclass.f32(float %a, i32 3)
@@ -1224,9 +1224,9 @@ define i1 @test_fold_and_class_f32_1(float %a) {
define i1 @test_no_fold_and_class_f32_multi_use0(float %a, ptr %ptr) {
; CHECK-LABEL: @test_no_fold_and_class_f32_multi_use0(
-; CHECK-NEXT: [[CLASS0:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A:%.*]], i32 15)
+; CHECK-NEXT: [[CLASS0:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A:%.*]], /* (nan ninf nnorm) */ i32 15)
; CHECK-NEXT: store i1 [[CLASS0]], ptr [[PTR:%.*]], align 1
-; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 8)
+; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], /* (nnorm) */ i32 8)
; CHECK-NEXT: [[AND:%.*]] = and i1 [[CLASS0]], [[CLASS1]]
; CHECK-NEXT: ret i1 [[AND]]
;
@@ -1239,8 +1239,8 @@ define i1 @test_no_fold_and_class_f32_multi_use0(float %a, ptr %ptr) {
define i1 @test_no_fold_and_class_f32_multi_use1(float %a, ptr %ptr) {
; CHECK-LABEL: @test_no_fold_and_class_f32_multi_use1(
-; CHECK-NEXT: [[CLASS0:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A:%.*]], i32 15)
-; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 8)
+; CHECK-NEXT: [[CLASS0:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A:%.*]], /* (nan ninf nnorm) */ i32 15)
+; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], /* (nnorm) */ i32 8)
; CHECK-NEXT: store i1 [[CLASS1]], ptr [[PTR:%.*]], align 1
; CHECK-NEXT: [[AND:%.*]] = and i1 [[CLASS0]], [[CLASS1]]
; CHECK-NEXT: ret i1 [[AND]]
@@ -1265,7 +1265,7 @@ define i1 @test_fold_and_class_f32_2(float %a) {
define i1 @test_fold_and_class_f32_3(float %a) {
; CHECK-LABEL: @test_fold_and_class_f32_3(
-; CHECK-NEXT: [[CLASS0:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A:%.*]], i32 1)
+; CHECK-NEXT: [[CLASS0:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A:%.*]], /* (snan) */ i32 1)
; CHECK-NEXT: ret i1 [[CLASS0]]
;
%class0 = call i1 @llvm.is.fpclass.f32(float %a, i32 37)
@@ -1276,7 +1276,7 @@ define i1 @test_fold_and_class_f32_3(float %a) {
define i1 @test_fold_and_class_f32_4(float %a) {
; CHECK-LABEL: @test_fold_and_class_f32_4(
-; CHECK-NEXT: [[CLASS0:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A:%.*]], i32 1)
+; CHECK-NEXT: [[CLASS0:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A:%.*]], /* (snan) */ i32 1)
; CHECK-NEXT: ret i1 [[CLASS0]]
;
%class0 = call i1 @llvm.is.fpclass.f32(float %a, i32 393)
@@ -1288,7 +1288,7 @@ define i1 @test_fold_and_class_f32_4(float %a) {
define i1 @test_no_fold_and_class_f32_0(float %a, float %b) {
; CHECK-LABEL: @test_no_fold_and_class_f32_0(
; CHECK-NEXT: [[CLASS0:%.*]] = fcmp ueq float [[A:%.*]], -inf
-; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[B:%.*]], i32 15)
+; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[B:%.*]], /* (nan ninf nnorm) */ i32 15)
; CHECK-NEXT: [[AND:%.*]] = and i1 [[CLASS0]], [[CLASS1]]
; CHECK-NEXT: ret i1 [[AND]]
;
@@ -1315,7 +1315,7 @@ define <2 x i1> @test_fold_and_class_v2f32(<2 x float> %a) {
define i1 @test_fold_xor_class_f32_0(float %a) {
; CHECK-LABEL: @test_fold_xor_class_f32_0(
-; CHECK-NEXT: [[CLASS0:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A:%.*]], i32 2)
+; CHECK-NEXT: [[CLASS0:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A:%.*]], /* (qnan) */ i32 2)
; CHECK-NEXT: ret i1 [[CLASS0]]
;
%class0 = call i1 @llvm.is.fpclass.f32(float %a, i32 1)
@@ -1365,7 +1365,7 @@ define i1 @test_fold_xor_all_tests_class_f32_0(float %a) {
define i1 @test_fold_xor_class_f32_1(float %a) {
; CHECK-LABEL: @test_fold_xor_class_f32_1(
-; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A:%.*]], i32 12)
+; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A:%.*]], /* (ninf nnorm) */ i32 12)
; CHECK-NEXT: ret i1 [[CLASS1]]
;
%class0 = call i1 @llvm.is.fpclass.f32(float %a, i32 4)
@@ -1378,7 +1378,7 @@ define i1 @test_no_fold_xor_class_f32_multi_use0(float %a, ptr %ptr) {
; CHECK-LABEL: @test_no_fold_xor_class_f32_multi_use0(
; CHECK-NEXT: [[CLASS0:%.*]] = fcmp oeq float [[A:%.*]], -inf
; CHECK-NEXT: store i1 [[CLASS0]], ptr [[PTR:%.*]], align 1
-; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 8)
+; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], /* (nnorm) */ i32 8)
; CHECK-NEXT: [[XOR:%.*]] = xor i1 [[CLASS0]], [[CLASS1]]
; CHECK-NEXT: ret i1 [[XOR]]
;
@@ -1392,7 +1392,7 @@ define i1 @test_no_fold_xor_class_f32_multi_use0(float %a, ptr %ptr) {
define i1 @test_no_fold_xor_class_f32_multi_use1(float %a, ptr %ptr) {
; CHECK-LABEL: @test_no_fold_xor_class_f32_multi_use1(
; CHECK-NEXT: [[CLASS0:%.*]] = fcmp oeq float [[A:%.*]], -inf
-; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 8)
+; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], /* (nnorm) */ i32 8)
; CHECK-NEXT: store i1 [[CLASS1]], ptr [[PTR:%.*]], align 1
; CHECK-NEXT: [[XOR:%.*]] = xor i1 [[CLASS0]], [[CLASS1]]
; CHECK-NEXT: ret i1 [[XOR]]
@@ -1417,7 +1417,7 @@ define i1 @test_fold_xor_class_f32_2(float %a) {
define i1 @test_no_fold_xor_class_f32_0(float %a, float %b) {
; CHECK-LABEL: @test_no_fold_xor_class_f32_0(
; CHECK-NEXT: [[CLASS0:%.*]] = fcmp oeq float [[A:%.*]], -inf
-; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[B:%.*]], i32 8)
+; CHECK-NEXT: [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[B:%.*]], /* (nnorm) */ i32 8)
; CHECK-NEXT: [[XOR:%.*]] = xor i1 [[CLASS0]], [[CLASS1]]
; CHECK-NEXT: ret i1 [[XOR]]
;
@@ -1429,7 +1429,7 @@ define i1 @test_no_fold_xor_class_f32_0(float %a, float %b) {
define <2 x i1> @test_fold_xor_class_v2f32(<2 x float> %a) {
; CHECK-LABEL: @test_fold_xor_class_v2f32(
-; CHECK-NEXT: [[CLASS1:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[A:%.*]], i32 9)
+; CHECK-NEXT: [[CLASS1:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[A:%.*]], /* (snan nnorm) */ i32 9)
; CHECK-NEXT: ret <2 x i1> [[CLASS1]]
;
%class0 = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %a, i32 4)
@@ -1465,7 +1465,7 @@ define i1 @test_class_fneg_all(float %arg) {
; -> snan
define i1 @test_class_fneg_snan(float %arg) {
; CHECK-LABEL: @test_class_fneg_snan(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 1)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan) */ i32 1)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fneg = fneg float %arg
@@ -1476,7 +1476,7 @@ define i1 @test_class_fneg_snan(float %arg) {
; -> qnan
define i1 @test_class_fneg_qnan(float %arg) {
; CHECK-LABEL: @test_class_fneg_qnan(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 2)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan) */ i32 2)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fneg = fneg float %arg
@@ -1498,7 +1498,7 @@ define i1 @test_class_fneg_neginf(float %arg) {
; -> posnormal
define i1 @test_class_fneg_negnormal(float %arg) {
; CHECK-LABEL: @test_class_fneg_negnormal(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 256)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (pnorm) */ i32 256)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fneg = fneg float %arg
@@ -1509,7 +1509,7 @@ define i1 @test_class_fneg_negnormal(float %arg) {
; -> possubnormal
define i1 @test_class_fneg_negsubnormal(float %arg) {
; CHECK-LABEL: @test_class_fneg_negsubnormal(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 128)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (psub) */ i32 128)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fneg = fneg float %arg
@@ -1520,7 +1520,7 @@ define i1 @test_class_fneg_negsubnormal(float %arg) {
; -> poszero
define i1 @test_class_fneg_negzero(float %arg) {
; CHECK-LABEL: @test_class_fneg_negzero(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 64)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (pzero) */ i32 64)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fneg = fneg float %arg
@@ -1531,7 +1531,7 @@ define i1 @test_class_fneg_negzero(float %arg) {
; -> negzero
define i1 @test_class_fneg_poszero(float %arg) {
; CHECK-LABEL: @test_class_fneg_poszero(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 32)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nzero) */ i32 32)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fneg = fneg float %arg
@@ -1542,7 +1542,7 @@ define i1 @test_class_fneg_poszero(float %arg) {
; -> negsubnormal
define i1 @test_class_fneg_possubnormal(float %arg) {
; CHECK-LABEL: @test_class_fneg_possubnormal(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 16)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nsub) */ i32 16)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fneg = fneg float %arg
@@ -1553,7 +1553,7 @@ define i1 @test_class_fneg_possubnormal(float %arg) {
; -> negnormal
define i1 @test_class_fneg_posnormal(float %arg) {
; CHECK-LABEL: @test_class_fneg_posnormal(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 8)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nnorm) */ i32 8)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fneg = fneg float %arg
@@ -1597,7 +1597,7 @@ define i1 @test_class_fneg_nnan(float %arg) {
; -> normal
define i1 @test_class_fneg_normal(float %arg) {
; CHECK-LABEL: @test_class_fneg_normal(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 264)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (norm) */ i32 264)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fneg = fneg float %arg
@@ -1621,7 +1621,7 @@ define i1 @test_class_fneg_zero(float %arg) {
define i1 @test_class_fneg_subnormal(float %arg) {
;
; CHECK-LABEL: @test_class_fneg_subnormal(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 144)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (sub) */ i32 144)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fneg = fneg float %arg
@@ -1632,7 +1632,7 @@ define i1 @test_class_fneg_subnormal(float %arg) {
; -> normal|pinf
define i1 @test_class_fneg_normal_neginf(float %arg) {
; CHECK-LABEL: @test_class_fneg_normal_neginf(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 776)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (pinf norm) */ i32 776)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fneg = fneg float %arg
@@ -1643,7 +1643,7 @@ define i1 @test_class_fneg_normal_neginf(float %arg) {
; -> normal|ninf
define i1 @test_class_fneg_normal_pinf(float %arg) {
; CHECK-LABEL: @test_class_fneg_normal_pinf(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 268)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (ninf norm) */ i32 268)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fneg = fneg float %arg
@@ -1654,7 +1654,7 @@ define i1 @test_class_fneg_normal_pinf(float %arg) {
; -> pinf|nnormal|pnormal|nzero
define i1 @test_class_fneg_neginf_posnormal_negsubnormal_poszero(float %arg) {
; CHECK-LABEL: @test_class_fneg_neginf_posnormal_negsubnormal_poszero(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 680)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (pinf nzero psub nnorm) */ i32 680)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fneg = fneg float %arg
@@ -1665,7 +1665,7 @@ define i1 @test_class_fneg_neginf_posnormal_negsubnormal_poszero(float %arg) {
; -> pinf|nnormal|psubnormal|negzero|snan
define i1 @test_class_fneg_neginf_posnormal_negsubnormal_poszero_snan(float %arg) {
; CHECK-LABEL: @test_class_fneg_neginf_posnormal_negsubnormal_poszero_snan(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 681)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan pinf nzero psub nnorm) */ i32 681)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fneg = fneg float %arg
@@ -1676,7 +1676,7 @@ define i1 @test_class_fneg_neginf_posnormal_negsubnormal_poszero_snan(float %arg
; pinf|negnormal|psubnormal|negzero|qnan
define i1 @test_class_fneg_neginf_posnormal_negsubnormal_poszero_qnan(float %arg) {
; CHECK-LABEL: @test_class_fneg_neginf_posnormal_negsubnormal_poszero_qnan(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 682)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan pinf nzero psub nnorm) */ i32 682)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fneg = fneg float %arg
@@ -1687,7 +1687,7 @@ define i1 @test_class_fneg_neginf_posnormal_negsubnormal_poszero_qnan(float %arg
; -> pinf | nnormal|psubnormal|nzero|nan
define i1 @test_class_fneg_neginf_posnormal_negsubnormal_poszero_nan(float %arg) {
; CHECK-LABEL: @test_class_fneg_neginf_posnormal_negsubnormal_poszero_nan(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 683)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan pinf nzero psub nnorm) */ i32 683)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fneg = fneg float %arg
@@ -1698,7 +1698,7 @@ define i1 @test_class_fneg_neginf_posnormal_negsubnormal_poszero_nan(float %arg)
; -> ninf|pnormal|negsubnormal|pzero
define i1 @test_class_fneg_posinf_negnormal_possubnormal_negzero(float %arg) {
; CHECK-LABEL: @test_class_fneg_posinf_negnormal_possubnormal_negzero(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 340)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (ninf pzero nsub pnorm) */ i32 340)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fneg = fneg float %arg
@@ -1709,7 +1709,7 @@ define i1 @test_class_fneg_posinf_negnormal_possubnormal_negzero(float %arg) {
; -> ninf|pnormal|negsubnormal|pzero|snan
define i1 @test_class_fneg_posinf_negnormal_possubnormal_negzero_snan(float %arg) {
; CHECK-LABEL: @test_class_fneg_posinf_negnormal_possubnormal_negzero_snan(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 341)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan ninf pzero nsub pnorm) */ i32 341)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fneg = fneg float %arg
@@ -1720,7 +1720,7 @@ define i1 @test_class_fneg_posinf_negnormal_possubnormal_negzero_snan(float %arg
; -> ninf|pnormal|negsubnormal|pzero|qnan
define i1 @test_class_fneg_posinf_negnormal_possubnormal_negzero_qnan(float %arg) {
; CHECK-LABEL: @test_class_fneg_posinf_negnormal_possubnormal_negzero_qnan(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 342)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan ninf pzero nsub pnorm) */ i32 342)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fneg = fneg float %arg
@@ -1731,7 +1731,7 @@ define i1 @test_class_fneg_posinf_negnormal_possubnormal_negzero_qnan(float %arg
; -> ninf|pnormal|negsubnormal|pzero
define i1 @test_class_fneg_posinf_negnormal_possubnormal_negzero_nan(float %arg) {
; CHECK-LABEL: @test_class_fneg_posinf_negnormal_possubnormal_negzero_nan(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 343)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan ninf pzero nsub pnorm) */ i32 343)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fneg = fneg float %arg
@@ -1743,7 +1743,7 @@ define i1 @test_class_fneg_posinf_negnormal_possubnormal_negzero_nan(float %arg)
; -> ninf|pnormal|negsubnormal|pzero|snan
define i1 @test_class_fneg_posinf_negnormal_possubnormal_negzero_snan_strictfp(float %arg) strictfp {
; CHECK-LABEL: @test_class_fneg_posinf_negnormal_possubnormal_negzero_snan_strictfp(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 341)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan ninf pzero nsub pnorm) */ i32 341)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fneg = fneg float %arg
@@ -1756,7 +1756,7 @@ define i1 @test_class_fneg_multiple_use_fneg(float %arg, ptr %ptr) {
; CHECK-LABEL: @test_class_fneg_multiple_use_fneg(
; CHECK-NEXT: [[FNEG:%.*]] = fneg float [[ARG:%.*]]
; CHECK-NEXT: store float [[FNEG]], ptr [[PTR:%.*]], align 4
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG]], i32 342)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG]], /* (qnan ninf pzero nsub pnorm) */ i32 342)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fneg = fneg float %arg
@@ -1767,7 +1767,7 @@ define i1 @test_class_fneg_multiple_use_fneg(float %arg, ptr %ptr) {
define <2 x i1> @test_class_fneg_posinf_negnormal_possubnormal_negzero_nan_vector(<2 x float> %arg) {
; CHECK-LABEL: @test_class_fneg_posinf_negnormal_possubnormal_negzero_nan_vector(
-; CHECK-NEXT: [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[ARG:%.*]], i32 343)
+; CHECK-NEXT: [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[ARG:%.*]], /* (nan ninf pzero nsub pnorm) */ i32 343)
; CHECK-NEXT: ret <2 x i1> [[CLASS]]
;
%fneg = fneg <2 x float> %arg
@@ -1802,7 +1802,7 @@ define i1 @test_class_fabs_all(float %arg) {
; -> snan
define i1 @test_class_fabs_snan(float %arg) {
; CHECK-LABEL: @test_class_fabs_snan(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 1)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan) */ i32 1)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -1813,7 +1813,7 @@ define i1 @test_class_fabs_snan(float %arg) {
; -> qnan
define i1 @test_class_fabs_qnan(float %arg) {
; CHECK-LABEL: @test_class_fabs_qnan(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 2)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan) */ i32 2)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -1875,7 +1875,7 @@ define i1 @test_class_fabs_poszero(float %arg) {
; -> possubnormal
define i1 @test_class_fabs_possubnormal(float %arg) {
; CHECK-LABEL: @test_class_fabs_possubnormal(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 144)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (sub) */ i32 144)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -1886,7 +1886,7 @@ define i1 @test_class_fabs_possubnormal(float %arg) {
; -> posnormal
define i1 @test_class_fabs_posnormal(float %arg) {
; CHECK-LABEL: @test_class_fabs_posnormal(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 264)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (norm) */ i32 264)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -1931,7 +1931,7 @@ define i1 @test_class_fabs_nnan(float %arg) {
; -> posnormal
define i1 @test_class_fabs_normal(float %arg) {
; CHECK-LABEL: @test_class_fabs_normal(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 264)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (norm) */ i32 264)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -1953,7 +1953,7 @@ define i1 @test_class_fabs_zero(float %arg) {
; -> possubnormal
define i1 @test_class_fabs_subnormal(float %arg) {
; CHECK-LABEL: @test_class_fabs_subnormal(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 144)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (sub) */ i32 144)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -1964,7 +1964,7 @@ define i1 @test_class_fabs_subnormal(float %arg) {
; -> posnormal
define i1 @test_class_fabs_normal_neginf(float %arg) {
; CHECK-LABEL: @test_class_fabs_normal_neginf(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 264)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (norm) */ i32 264)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -1975,7 +1975,7 @@ define i1 @test_class_fabs_normal_neginf(float %arg) {
; -> pnormal|pinf
define i1 @test_class_fabs_normal_pinf(float %arg) {
; CHECK-LABEL: @test_class_fabs_normal_pinf(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 780)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (inf norm) */ i32 780)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -1986,7 +1986,7 @@ define i1 @test_class_fabs_normal_pinf(float %arg) {
; -> pnormal|pzero
define i1 @test_class_fabs_neginf_posnormal_negsubnormal_poszero(float %arg) {
; CHECK-LABEL: @test_class_fabs_neginf_posnormal_negsubnormal_poszero(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 360)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (zero norm) */ i32 360)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -1997,7 +1997,7 @@ define i1 @test_class_fabs_neginf_posnormal_negsubnormal_poszero(float %arg) {
; -> pnormal|pzero|snan
define i1 @test_class_fabs_neginf_posnormal_negsubnormal_poszero_snan(float %arg) {
; CHECK-LABEL: @test_class_fabs_neginf_posnormal_negsubnormal_poszero_snan(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 361)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan zero norm) */ i32 361)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -2008,7 +2008,7 @@ define i1 @test_class_fabs_neginf_posnormal_negsubnormal_poszero_snan(float %arg
; -> negnormal|pzero|qnan
define i1 @test_class_fabs_neginf_posnormal_negsubnormal_poszero_qnan(float %arg) {
; CHECK-LABEL: @test_class_fabs_neginf_posnormal_negsubnormal_poszero_qnan(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 362)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan zero norm) */ i32 362)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -2019,7 +2019,7 @@ define i1 @test_class_fabs_neginf_posnormal_negsubnormal_poszero_qnan(float %arg
; -> pnormal|pzero|nan
define i1 @test_class_fabs_neginf_posnormal_negsubnormal_poszero_nan(float %arg) {
; CHECK-LABEL: @test_class_fabs_neginf_posnormal_negsubnormal_poszero_nan(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 363)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan zero norm) */ i32 363)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -2030,7 +2030,7 @@ define i1 @test_class_fabs_neginf_posnormal_negsubnormal_poszero_nan(float %arg)
; -> ninf|pnormal|negsubnormal|pzero
define i1 @test_class_fabs_posinf_negnormal_possubnormal_negzero(float %arg) {
; CHECK-LABEL: @test_class_fabs_posinf_negnormal_possubnormal_negzero(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 660)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (inf sub) */ i32 660)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -2041,7 +2041,7 @@ define i1 @test_class_fabs_posinf_negnormal_possubnormal_negzero(float %arg) {
; -> pinf|psubnormal|snan
define i1 @test_class_fabs_posinf_negnormal_possubnormal_negzero_snan(float %arg) {
; CHECK-LABEL: @test_class_fabs_posinf_negnormal_possubnormal_negzero_snan(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 661)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan inf sub) */ i32 661)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -2052,7 +2052,7 @@ define i1 @test_class_fabs_posinf_negnormal_possubnormal_negzero_snan(float %arg
; -> pinf|psubnormal|qnan
define i1 @test_class_fabs_posinf_negnormal_possubnormal_negzero_qnan(float %arg) {
; CHECK-LABEL: @test_class_fabs_posinf_negnormal_possubnormal_negzero_qnan(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 662)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan inf sub) */ i32 662)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -2063,7 +2063,7 @@ define i1 @test_class_fabs_posinf_negnormal_possubnormal_negzero_qnan(float %arg
; -> pinf|psubnormal|nan
define i1 @test_class_fabs_posinf_negnormal_possubnormal_negzero_nan(float %arg) {
; CHECK-LABEL: @test_class_fabs_posinf_negnormal_possubnormal_negzero_nan(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 663)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan inf sub) */ i32 663)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -2075,7 +2075,7 @@ define i1 @test_class_fabs_posinf_negnormal_possubnormal_negzero_nan(float %arg)
; -> pinf|psubnormal|snan
define i1 @test_class_fabs_posinf_negnormal_possubnormal_negzero_snan_strictfp(float %arg) strictfp {
; CHECK-LABEL: @test_class_fabs_posinf_negnormal_possubnormal_negzero_snan_strictfp(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 661)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan inf sub) */ i32 661)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg) strictfp
@@ -2088,7 +2088,7 @@ define i1 @test_class_fabs_multiple_use_fabs(float %arg, ptr %ptr) {
; CHECK-LABEL: @test_class_fabs_multiple_use_fabs(
; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[ARG:%.*]])
; CHECK-NEXT: store float [[FABS]], ptr [[PTR:%.*]], align 4
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG]], i32 662)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG]], /* (qnan inf sub) */ i32 662)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -2099,7 +2099,7 @@ define i1 @test_class_fabs_multiple_use_fabs(float %arg, ptr %ptr) {
define <2 x i1> @test_class_fabs_posinf_negnormal_possubnormal_negzero_nan_vector(<2 x float> %arg) {
; CHECK-LABEL: @test_class_fabs_posinf_negnormal_possubnormal_negzero_nan_vector(
-; CHECK-NEXT: [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[ARG:%.*]], i32 663)
+; CHECK-NEXT: [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[ARG:%.*]], /* (nan inf sub) */ i32 663)
; CHECK-NEXT: ret <2 x i1> [[CLASS]]
;
%fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %arg)
@@ -2133,7 +2133,7 @@ define i1 @test_class_fneg_fabs_all(float %arg) {
define i1 @test_class_fneg_fabs_snan(float %arg) {
; CHECK-LABEL: @test_class_fneg_fabs_snan(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 1)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan) */ i32 1)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -2144,7 +2144,7 @@ define i1 @test_class_fneg_fabs_snan(float %arg) {
define i1 @test_class_fneg_fabs_qnan(float %arg) {
; CHECK-LABEL: @test_class_fneg_fabs_qnan(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 2)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan) */ i32 2)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -2167,7 +2167,7 @@ define i1 @test_class_fneg_fabs_neginf(float %arg) {
define i1 @test_class_fneg_fabs_negnormal(float %arg) {
; CHECK-LABEL: @test_class_fneg_fabs_negnormal(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 264)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (norm) */ i32 264)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -2178,7 +2178,7 @@ define i1 @test_class_fneg_fabs_negnormal(float %arg) {
define i1 @test_class_fneg_fabs_negsubnormal(float %arg) {
; CHECK-LABEL: @test_class_fneg_fabs_negsubnormal(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 144)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (sub) */ i32 144)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -2262,7 +2262,7 @@ define i1 @test_class_fneg_fabs_nnan(float %arg) {
define i1 @test_class_fneg_fabs_normal(float %arg) {
; CHECK-LABEL: @test_class_fneg_fabs_normal(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 264)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (norm) */ i32 264)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -2284,7 +2284,7 @@ define i1 @test_class_fneg_fabs_zero(float %arg) {
define i1 @test_class_fneg_fabs_subnormal(float %arg) {
; CHECK-LABEL: @test_class_fneg_fabs_subnormal(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 144)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (sub) */ i32 144)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -2295,7 +2295,7 @@ define i1 @test_class_fneg_fabs_subnormal(float %arg) {
define i1 @test_class_fneg_fabs_normal_neginf(float %arg) {
; CHECK-LABEL: @test_class_fneg_fabs_normal_neginf(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 780)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (inf norm) */ i32 780)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -2306,7 +2306,7 @@ define i1 @test_class_fneg_fabs_normal_neginf(float %arg) {
define i1 @test_class_fneg_fabs_normal_pinf(float %arg) {
; CHECK-LABEL: @test_class_fneg_fabs_normal_pinf(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 264)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (norm) */ i32 264)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -2317,7 +2317,7 @@ define i1 @test_class_fneg_fabs_normal_pinf(float %arg) {
define i1 @test_class_fneg_fabs_neginf_posnormal_negsubnormal_poszero(float %arg) {
; CHECK-LABEL: @test_class_fneg_fabs_neginf_posnormal_negsubnormal_poszero(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 660)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (inf sub) */ i32 660)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -2328,7 +2328,7 @@ define i1 @test_class_fneg_fabs_neginf_posnormal_negsubnormal_poszero(float %arg
define i1 @test_class_fneg_fabs_neginf_posnormal_negsubnormal_poszero_snan(float %arg) {
; CHECK-LABEL: @test_class_fneg_fabs_neginf_posnormal_negsubnormal_poszero_snan(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 661)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan inf sub) */ i32 661)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -2339,7 +2339,7 @@ define i1 @test_class_fneg_fabs_neginf_posnormal_negsubnormal_poszero_snan(float
define i1 @test_class_fneg_fabs_neginf_posnormal_negsubnormal_poszero_qnan(float %arg) {
; CHECK-LABEL: @test_class_fneg_fabs_neginf_posnormal_negsubnormal_poszero_qnan(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 662)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan inf sub) */ i32 662)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -2350,7 +2350,7 @@ define i1 @test_class_fneg_fabs_neginf_posnormal_negsubnormal_poszero_qnan(float
define i1 @test_class_fneg_fabs_neginf_posnormal_negsubnormal_poszero_nan(float %arg) {
; CHECK-LABEL: @test_class_fneg_fabs_neginf_posnormal_negsubnormal_poszero_nan(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 663)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan inf sub) */ i32 663)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -2361,7 +2361,7 @@ define i1 @test_class_fneg_fabs_neginf_posnormal_negsubnormal_poszero_nan(float
define i1 @test_class_fneg_fabs_posinf_negnormal_possubnormal_negzero(float %arg) {
; CHECK-LABEL: @test_class_fneg_fabs_posinf_negnormal_possubnormal_negzero(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 360)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (zero norm) */ i32 360)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -2372,7 +2372,7 @@ define i1 @test_class_fneg_fabs_posinf_negnormal_possubnormal_negzero(float %arg
define i1 @test_class_fneg_fabs_posinf_negnormal_possubnormal_negzero_snan(float %arg) {
; CHECK-LABEL: @test_class_fneg_fabs_posinf_negnormal_possubnormal_negzero_snan(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 361)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan zero norm) */ i32 361)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -2383,7 +2383,7 @@ define i1 @test_class_fneg_fabs_posinf_negnormal_possubnormal_negzero_snan(float
define i1 @test_class_fneg_fabs_posinf_negnormal_possubnormal_negzero_qnan(float %arg) {
; CHECK-LABEL: @test_class_fneg_fabs_posinf_negnormal_possubnormal_negzero_qnan(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 362)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan zero norm) */ i32 362)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -2394,7 +2394,7 @@ define i1 @test_class_fneg_fabs_posinf_negnormal_possubnormal_negzero_qnan(float
define i1 @test_class_fneg_fabs_posinf_negnormal_possubnormal_negzero_nan(float %arg) {
; CHECK-LABEL: @test_class_fneg_fabs_posinf_negnormal_possubnormal_negzero_nan(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 363)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan zero norm) */ i32 363)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -2406,7 +2406,7 @@ define i1 @test_class_fneg_fabs_posinf_negnormal_possubnormal_negzero_nan(float
; strictfp doesn't matter
define i1 @test_class_fneg_fabs_posinf_negnormal_possubnormal_negzero_snan_strictfp(float %arg) strictfp {
; CHECK-LABEL: @test_class_fneg_fabs_posinf_negnormal_possubnormal_negzero_snan_strictfp(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 361)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan zero norm) */ i32 361)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg) strictfp
@@ -2421,7 +2421,7 @@ define i1 @test_class_fneg_fabs_multiple_use_fabs(float %arg, ptr %ptr) {
; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[ARG:%.*]])
; CHECK-NEXT: [[FNEG_FABS:%.*]] = fneg float [[FABS]]
; CHECK-NEXT: store float [[FNEG_FABS]], ptr [[PTR:%.*]], align 4
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG]], i32 362)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG]], /* (qnan zero norm) */ i32 362)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%fabs = call float @llvm.fabs.f32(float %arg)
@@ -2433,7 +2433,7 @@ define i1 @test_class_fneg_fabs_multiple_use_fabs(float %arg, ptr %ptr) {
define <2 x i1> @test_class_fneg_fabs_posinf_negnormal_possubnormal_negzero_nan_vector(<2 x float> %arg) {
; CHECK-LABEL: @test_class_fneg_fabs_posinf_negnormal_possubnormal_negzero_nan_vector(
-; CHECK-NEXT: [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[ARG:%.*]], i32 663)
+; CHECK-NEXT: [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[ARG:%.*]], /* (nan inf sub) */ i32 663)
; CHECK-NEXT: ret <2 x i1> [[CLASS]]
;
%fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %arg)
@@ -2486,7 +2486,7 @@ define i1 @test_class_is_pzero_nopzero_src(float nofpclass(pzero) %arg) {
define i1 @test_class_is_pzero_nonzero_src(float nofpclass(nzero) %arg) {
; CHECK-LABEL: @test_class_is_pzero_nonzero_src(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 64)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (pzero) */ i32 64)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 64)
@@ -2503,7 +2503,7 @@ define i1 @test_class_is_nzero_nozero_src(float nofpclass(zero) %arg) {
define i1 @test_class_is_nzero_nopzero_src(float nofpclass(pzero) %arg) {
; CHECK-LABEL: @test_class_is_nzero_nopzero_src(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 32)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nzero) */ i32 32)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 32)
@@ -2520,7 +2520,7 @@ define i1 @test_class_is_nzero_nonzero_src(float nofpclass(nzero) %arg) {
define i1 @test_class_is_normal_or_zero_nozero_src(float nofpclass(zero) %arg) {
; CHECK-LABEL: @test_class_is_normal_or_zero_nozero_src(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 264)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (norm) */ i32 264)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 360)
@@ -2559,7 +2559,7 @@ define i1 @test_class_is_inf_or_nan_nonan_src(float nofpclass(nan) %arg) {
define i1 @test_class_is_normal_or_subnormal_noinf_src(float nofpclass(inf) %arg) {
; CHECK-LABEL: @test_class_is_normal_or_subnormal_noinf_src(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 408)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (sub norm) */ i32 408)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 408)
@@ -2626,7 +2626,7 @@ define i1 @test_class_is_subnormal_nosub_src(float nofpclass(sub) %arg) {
define i1 @test_class_is_subnormal_nonsub_src(float nofpclass(nsub) %arg) {
; CHECK-LABEL: @test_class_is_subnormal_nonsub_src(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 128)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (psub) */ i32 128)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 144)
@@ -2692,7 +2692,7 @@ define i1 @test_class_is_nnormal_onlynorm_src(float nofpclass(nan inf zero sub)
; Make sure assume works
define i1 @test_class_is_normal_assume_normal(float %x) {
; CHECK-LABEL: @test_class_is_normal_assume_normal(
-; CHECK-NEXT: [[ASSUMED_IS_NORMAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 264)
+; CHECK-NEXT: [[ASSUMED_IS_NORMAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (norm) */ i32 264)
; CHECK-NEXT: call void @llvm.assume(i1 [[ASSUMED_IS_NORMAL]])
; CHECK-NEXT: ret i1 true
;
@@ -2704,7 +2704,7 @@ define i1 @test_class_is_normal_assume_normal(float %x) {
define i1 @test_class_is_normal_assume_not_normal(float %x) {
; CHECK-LABEL: @test_class_is_normal_assume_not_normal(
-; CHECK-NEXT: [[ASSUMED_IS_NORMAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 264)
+; CHECK-NEXT: [[ASSUMED_IS_NORMAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], /* (norm) */ i32 264)
; CHECK-NEXT: call void @llvm.assume(i1 [[ASSUMED_IS_NORMAL]])
; CHECK-NEXT: ret i1 false
;
@@ -2757,7 +2757,7 @@ define i1 @test_class_is_nan_assume_not_eq_pinf(float %x) {
define i1 @test_class_is_pzero_psub_pnorm_pinf__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_pzero_psub_pnorm_pinf__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 960)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (pinf pzero psub pnorm) */ i32 960)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 960)
@@ -2766,7 +2766,7 @@ define i1 @test_class_is_pzero_psub_pnorm_pinf__ieee(float %arg) #0 {
define i1 @test_class_is_pzero_psub_pnorm_pinf_snan__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_pzero_psub_pnorm_pinf_snan__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 961)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan pinf pzero psub pnorm) */ i32 961)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 961)
@@ -2775,7 +2775,7 @@ define i1 @test_class_is_pzero_psub_pnorm_pinf_snan__ieee(float %arg) #0 {
define i1 @test_class_is_pzero_psub_pnorm_pinf_qnan__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_pzero_psub_pnorm_pinf_qnan__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 962)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan pinf pzero psub pnorm) */ i32 962)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 962)
@@ -2784,7 +2784,7 @@ define i1 @test_class_is_pzero_psub_pnorm_pinf_qnan__ieee(float %arg) #0 {
define i1 @test_class_is_pzero_psub_pnorm_pinf_nan__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_pzero_psub_pnorm_pinf_nan__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 963)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan pinf pzero psub pnorm) */ i32 963)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 963)
@@ -2802,7 +2802,7 @@ define i1 @test_class_is_psub_pnorm_pinf__ieee(float %arg) #0 {
define i1 @test_class_is_psub_pnorm_pinf_snan__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_psub_pnorm_pinf_snan__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 897)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan pinf psub pnorm) */ i32 897)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 897)
@@ -2811,7 +2811,7 @@ define i1 @test_class_is_psub_pnorm_pinf_snan__ieee(float %arg) #0 {
define i1 @test_class_is_psub_pnorm_pinf_qnan__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_psub_pnorm_pinf_qnan__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 898)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan pinf psub pnorm) */ i32 898)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 898)
@@ -2829,7 +2829,7 @@ define i1 @test_class_is_psub_pnorm_pinf_nan__ieee(float %arg) #0 {
define i1 @test_class_is_pnorm_pinf__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_pnorm_pinf__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 768)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (pinf pnorm) */ i32 768)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 768)
@@ -2838,7 +2838,7 @@ define i1 @test_class_is_pnorm_pinf__ieee(float %arg) #0 {
define i1 @test_class_is_pzero_pnorm_pinf__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_pzero_pnorm_pinf__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 704)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (pinf pzero psub) */ i32 704)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 704)
@@ -2847,7 +2847,7 @@ define i1 @test_class_is_pzero_pnorm_pinf__ieee(float %arg) #0 {
define i1 @test_class_is_pzero_pnorm_pinf_nan__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_pzero_pnorm_pinf_nan__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 707)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan pinf pzero psub) */ i32 707)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 707)
@@ -2865,7 +2865,7 @@ define i1 @test_class_is_nzero_pzero_psub_pnorm_pinf__ieee(float %arg) #0 {
define i1 @test_class_is_nzero_pzero_psub_pnorm_pinf_snan__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_nzero_pzero_psub_pnorm_pinf_snan__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 993)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan pinf zero psub pnorm) */ i32 993)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 993)
@@ -2874,7 +2874,7 @@ define i1 @test_class_is_nzero_pzero_psub_pnorm_pinf_snan__ieee(float %arg) #0 {
define i1 @test_class_is_nzero_pzero_psub_pnorm_pinf_qnan__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_nzero_pzero_psub_pnorm_pinf_qnan__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 994)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan pinf zero psub pnorm) */ i32 994)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 994)
@@ -2892,7 +2892,7 @@ define i1 @test_class_is_nzero_pzero_psub_pnorm_pinf_nan__ieee(float %arg) #0 {
define i1 @test_class_is_nsub_nzero_pzero_psub_pnorm_pinf__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_nsub_nzero_pzero_psub_pnorm_pinf__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 1017)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan pinf zero sub norm) */ i32 1017)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 1017)
@@ -2901,7 +2901,7 @@ define i1 @test_class_is_nsub_nzero_pzero_psub_pnorm_pinf__ieee(float %arg) #0 {
define i1 @test_class_is_nsub_nzero_pzero_psub_pnorm_pinf_snan__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_nsub_nzero_pzero_psub_pnorm_pinf_snan__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 1009)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan pinf zero sub pnorm) */ i32 1009)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 1009)
@@ -2910,7 +2910,7 @@ define i1 @test_class_is_nsub_nzero_pzero_psub_pnorm_pinf_snan__ieee(float %arg)
define i1 @test_class_is_nsub_nzero_pzero_psub_pnorm_pinf_qnan__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_nsub_nzero_pzero_psub_pnorm_pinf_qnan__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 1010)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan pinf zero sub pnorm) */ i32 1010)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 1010)
@@ -2919,7 +2919,7 @@ define i1 @test_class_is_nsub_nzero_pzero_psub_pnorm_pinf_qnan__ieee(float %arg)
define i1 @test_class_is_nsub_nzero_pzero_psub_pnorm_pinf_nan__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_nsub_nzero_pzero_psub_pnorm_pinf_nan__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 1011)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan pinf zero sub pnorm) */ i32 1011)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 1011)
@@ -2928,7 +2928,7 @@ define i1 @test_class_is_nsub_nzero_pzero_psub_pnorm_pinf_nan__ieee(float %arg)
define i1 @test_class_is_nzero_psub_pnorm_pinf__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_nzero_psub_pnorm_pinf__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 928)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (pinf nzero psub pnorm) */ i32 928)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 928)
@@ -2937,7 +2937,7 @@ define i1 @test_class_is_nzero_psub_pnorm_pinf__ieee(float %arg) #0 {
define i1 @test_class_is_nzero_nsub_pnorm_pinf__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_nzero_nsub_pnorm_pinf__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 816)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (pinf nzero nsub pnorm) */ i32 816)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 816)
@@ -2947,7 +2947,7 @@ define i1 @test_class_is_nzero_nsub_pnorm_pinf__ieee(float %arg) #0 {
define i1 @test_class_is_not_pzero_psub_pnorm_pinf__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_not_pzero_psub_pnorm_pinf__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 63)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan ninf nzero nsub nnorm) */ i32 63)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 63)
@@ -2956,7 +2956,7 @@ define i1 @test_class_is_not_pzero_psub_pnorm_pinf__ieee(float %arg) #0 {
define i1 @test_class_is_not_pzero_psub_pnorm_pinf_snan__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_not_pzero_psub_pnorm_pinf_snan__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 62)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan ninf nzero nsub nnorm) */ i32 62)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 62)
@@ -2965,7 +2965,7 @@ define i1 @test_class_is_not_pzero_psub_pnorm_pinf_snan__ieee(float %arg) #0 {
define i1 @test_class_is_not_pzero_psub_pnorm_pinf_qnan__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_not_pzero_psub_pnorm_pinf_qnan__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 61)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan ninf nzero nsub nnorm) */ i32 61)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 61)
@@ -2974,7 +2974,7 @@ define i1 @test_class_is_not_pzero_psub_pnorm_pinf_qnan__ieee(float %arg) #0 {
define i1 @test_class_is_not_pzero_psub_pnorm_pinf_nan__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_not_pzero_psub_pnorm_pinf_nan__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 960)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (pinf pzero psub pnorm) */ i32 960)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 960)
@@ -2992,7 +2992,7 @@ define i1 @test_class_is_not_psub_pnorm_pinf__ieee(float %arg) #0 {
define i1 @test_class_is_not_psub_pnorm_pinf_snan__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_not_psub_pnorm_pinf_snan__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 126)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan ninf zero nsub nnorm) */ i32 126)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 126)
@@ -3001,7 +3001,7 @@ define i1 @test_class_is_not_psub_pnorm_pinf_snan__ieee(float %arg) #0 {
define i1 @test_class_is_not_psub_pnorm_pinf_qnan__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_not_psub_pnorm_pinf_qnan__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 125)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan ninf zero nsub nnorm) */ i32 125)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 125)
@@ -3019,7 +3019,7 @@ define i1 @test_class_is_not_psub_pnorm_pinf_nan__ieee(float %arg) #0 {
define i1 @test_class_is_not_pnorm_pinf__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_not_pnorm_pinf__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 255)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan ninf zero sub nnorm) */ i32 255)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 255)
@@ -3028,7 +3028,7 @@ define i1 @test_class_is_not_pnorm_pinf__ieee(float %arg) #0 {
define i1 @test_class_is_not_pzero_pnorm_pinf__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_not_pzero_pnorm_pinf__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 319)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan ninf nzero nsub norm) */ i32 319)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 319)
@@ -3037,7 +3037,7 @@ define i1 @test_class_is_not_pzero_pnorm_pinf__ieee(float %arg) #0 {
define i1 @test_class_is_not_pzero_pnorm_pinf_nan__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_not_pzero_pnorm_pinf_nan__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 316)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (ninf nzero nsub norm) */ i32 316)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 316)
@@ -3046,7 +3046,7 @@ define i1 @test_class_is_not_pzero_pnorm_pinf_nan__ieee(float %arg) #0 {
define i1 @test_class_is_not_nzero_pzero_psub_pnorm_pinf__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_not_nzero_pzero_psub_pnorm_pinf__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 22)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan ninf nsub) */ i32 22)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 22)
@@ -3055,7 +3055,7 @@ define i1 @test_class_is_not_nzero_pzero_psub_pnorm_pinf__ieee(float %arg) #0 {
define i1 @test_class_is_not_nzero_pzero_psub_pnorm_pinf_snan__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_not_nzero_pzero_psub_pnorm_pinf_snan__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 30)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan ninf nsub nnorm) */ i32 30)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 30)
@@ -3064,7 +3064,7 @@ define i1 @test_class_is_not_nzero_pzero_psub_pnorm_pinf_snan__ieee(float %arg)
define i1 @test_class_is_not_nzero_pzero_psub_pnorm_pinf_qnan__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_not_nzero_pzero_psub_pnorm_pinf_qnan__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 29)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan ninf nsub nnorm) */ i32 29)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 29)
@@ -3082,7 +3082,7 @@ define i1 @test_class_is_not_nzero_pzero_psub_pnorm_pinf_nan__ieee(float %arg) #
define i1 @test_class_is_not_nsub_nzero_pzero_psub_pnorm_pinf__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_not_nsub_nzero_pzero_psub_pnorm_pinf__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 6)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan ninf) */ i32 6)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 6)
@@ -3091,7 +3091,7 @@ define i1 @test_class_is_not_nsub_nzero_pzero_psub_pnorm_pinf__ieee(float %arg)
define i1 @test_class_is_not_nsub_nzero_pzero_psub_pnorm_pinf_snan__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_not_nsub_nzero_pzero_psub_pnorm_pinf_snan__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 14)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan ninf nnorm) */ i32 14)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 14)
@@ -3100,7 +3100,7 @@ define i1 @test_class_is_not_nsub_nzero_pzero_psub_pnorm_pinf_snan__ieee(float %
define i1 @test_class_is_not_nsub_nzero_pzero_psub_pnorm_pinf_qnan__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_not_nsub_nzero_pzero_psub_pnorm_pinf_qnan__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 13)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan ninf nnorm) */ i32 13)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 13)
@@ -3109,7 +3109,7 @@ define i1 @test_class_is_not_nsub_nzero_pzero_psub_pnorm_pinf_qnan__ieee(float %
define i1 @test_class_is_not_nsub_nzero_pzero_psub_pnorm_pinf_nan__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_not_nsub_nzero_pzero_psub_pnorm_pinf_nan__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 12)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (ninf nnorm) */ i32 12)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 12)
@@ -3118,7 +3118,7 @@ define i1 @test_class_is_not_nsub_nzero_pzero_psub_pnorm_pinf_nan__ieee(float %a
define i1 @test_class_is_not_nzero_psub_pnorm_pinf__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_not_nzero_psub_pnorm_pinf__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 95)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan ninf pzero nsub nnorm) */ i32 95)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 95)
@@ -3127,7 +3127,7 @@ define i1 @test_class_is_not_nzero_psub_pnorm_pinf__ieee(float %arg) #0 {
define i1 @test_class_is_not_nzero_nsub_pnorm_pinf__ieee(float %arg) #0 {
; CHECK-LABEL: @test_class_is_not_nzero_nsub_pnorm_pinf__ieee(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 207)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan ninf pzero psub nnorm) */ i32 207)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 207)
@@ -3140,7 +3140,7 @@ define i1 @test_class_is_not_nzero_nsub_pnorm_pinf__ieee(float %arg) #0 {
define i1 @test_class_is_pzero_psub_pnorm_pinf__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_pzero_psub_pnorm_pinf__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 960)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (pinf pzero psub pnorm) */ i32 960)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 960)
@@ -3149,7 +3149,7 @@ define i1 @test_class_is_pzero_psub_pnorm_pinf__daz(float %arg) #1 {
define i1 @test_class_is_pzero_psub_pnorm_pinf_snan__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_pzero_psub_pnorm_pinf_snan__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 961)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan pinf pzero psub pnorm) */ i32 961)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 961)
@@ -3158,7 +3158,7 @@ define i1 @test_class_is_pzero_psub_pnorm_pinf_snan__daz(float %arg) #1 {
define i1 @test_class_is_pzero_psub_pnorm_pinf_qnan__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_pzero_psub_pnorm_pinf_qnan__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 962)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan pinf pzero psub pnorm) */ i32 962)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 962)
@@ -3167,7 +3167,7 @@ define i1 @test_class_is_pzero_psub_pnorm_pinf_qnan__daz(float %arg) #1 {
define i1 @test_class_is_pzero_psub_pnorm_pinf_nan__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_pzero_psub_pnorm_pinf_nan__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 963)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan pinf pzero psub pnorm) */ i32 963)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 963)
@@ -3176,7 +3176,7 @@ define i1 @test_class_is_pzero_psub_pnorm_pinf_nan__daz(float %arg) #1 {
define i1 @test_class_is_psub_pnorm_pinf__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_psub_pnorm_pinf__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 896)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (pinf psub pnorm) */ i32 896)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 896)
@@ -3185,7 +3185,7 @@ define i1 @test_class_is_psub_pnorm_pinf__daz(float %arg) #1 {
define i1 @test_class_is_psub_pnorm_pinf_snan__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_psub_pnorm_pinf_snan__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 897)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan pinf psub pnorm) */ i32 897)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 897)
@@ -3194,7 +3194,7 @@ define i1 @test_class_is_psub_pnorm_pinf_snan__daz(float %arg) #1 {
define i1 @test_class_is_psub_pnorm_pinf_qnan__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_psub_pnorm_pinf_qnan__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 898)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan pinf psub pnorm) */ i32 898)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 898)
@@ -3203,7 +3203,7 @@ define i1 @test_class_is_psub_pnorm_pinf_qnan__daz(float %arg) #1 {
define i1 @test_class_is_psub_pnorm_pinf_nan__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_psub_pnorm_pinf_nan__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 899)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan pinf psub pnorm) */ i32 899)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 899)
@@ -3221,7 +3221,7 @@ define i1 @test_class_is_pnorm_pinf__daz(float %arg) #1 {
define i1 @test_class_is_pzero_pnorm_pinf__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_pzero_pnorm_pinf__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 704)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (pinf pzero psub) */ i32 704)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 704)
@@ -3230,7 +3230,7 @@ define i1 @test_class_is_pzero_pnorm_pinf__daz(float %arg) #1 {
define i1 @test_class_is_pzero_pnorm_pinf_nan__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_pzero_pnorm_pinf_nan__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 707)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan pinf pzero psub) */ i32 707)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 707)
@@ -3239,7 +3239,7 @@ define i1 @test_class_is_pzero_pnorm_pinf_nan__daz(float %arg) #1 {
define i1 @test_class_is_nzero_pzero_psub_pnorm_pinf__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_nzero_pzero_psub_pnorm_pinf__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 992)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (pinf zero psub pnorm) */ i32 992)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 992)
@@ -3248,7 +3248,7 @@ define i1 @test_class_is_nzero_pzero_psub_pnorm_pinf__daz(float %arg) #1 {
define i1 @test_class_is_nzero_pzero_psub_pnorm_pinf_snan__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_nzero_pzero_psub_pnorm_pinf_snan__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 993)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan pinf zero psub pnorm) */ i32 993)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 993)
@@ -3257,7 +3257,7 @@ define i1 @test_class_is_nzero_pzero_psub_pnorm_pinf_snan__daz(float %arg) #1 {
define i1 @test_class_is_nzero_pzero_psub_pnorm_pinf_qnan__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_nzero_pzero_psub_pnorm_pinf_qnan__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 994)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan pinf zero psub pnorm) */ i32 994)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 994)
@@ -3266,7 +3266,7 @@ define i1 @test_class_is_nzero_pzero_psub_pnorm_pinf_qnan__daz(float %arg) #1 {
define i1 @test_class_is_nzero_pzero_psub_pnorm_pinf_nan__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_nzero_pzero_psub_pnorm_pinf_nan__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 995)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan pinf zero psub pnorm) */ i32 995)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 995)
@@ -3275,7 +3275,7 @@ define i1 @test_class_is_nzero_pzero_psub_pnorm_pinf_nan__daz(float %arg) #1 {
define i1 @test_class_is_nsub_nzero_pzero_psub_pnorm_pinf__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_nsub_nzero_pzero_psub_pnorm_pinf__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 1017)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan pinf zero sub norm) */ i32 1017)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 1017)
@@ -3284,7 +3284,7 @@ define i1 @test_class_is_nsub_nzero_pzero_psub_pnorm_pinf__daz(float %arg) #1 {
define i1 @test_class_is_nsub_nzero_pzero_psub_pnorm_pinf_snan__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_nsub_nzero_pzero_psub_pnorm_pinf_snan__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 1009)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan pinf zero sub pnorm) */ i32 1009)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 1009)
@@ -3293,7 +3293,7 @@ define i1 @test_class_is_nsub_nzero_pzero_psub_pnorm_pinf_snan__daz(float %arg)
define i1 @test_class_is_nsub_nzero_pzero_psub_pnorm_pinf_qnan__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_nsub_nzero_pzero_psub_pnorm_pinf_qnan__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 1010)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan pinf zero sub pnorm) */ i32 1010)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 1010)
@@ -3311,7 +3311,7 @@ define i1 @test_class_is_nsub_nzero_pzero_psub_pnorm_pinf_nan__daz(float %arg) #
define i1 @test_class_is_nzero_psub_pnorm_pinf__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_nzero_psub_pnorm_pinf__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 928)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (pinf nzero psub pnorm) */ i32 928)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 928)
@@ -3320,7 +3320,7 @@ define i1 @test_class_is_nzero_psub_pnorm_pinf__daz(float %arg) #1 {
define i1 @test_class_is_nzero_nsub_pnorm_pinf__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_nzero_nsub_pnorm_pinf__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 816)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (pinf nzero nsub pnorm) */ i32 816)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 816)
@@ -3330,7 +3330,7 @@ define i1 @test_class_is_nzero_nsub_pnorm_pinf__daz(float %arg) #1 {
define i1 @test_class_is_not_pzero_psub_pnorm_pinf__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_not_pzero_psub_pnorm_pinf__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 63)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan ninf nzero nsub nnorm) */ i32 63)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 63)
@@ -3339,7 +3339,7 @@ define i1 @test_class_is_not_pzero_psub_pnorm_pinf__daz(float %arg) #1 {
define i1 @test_class_is_not_pzero_psub_pnorm_pinf_snan__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_not_pzero_psub_pnorm_pinf_snan__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 62)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan ninf nzero nsub nnorm) */ i32 62)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 62)
@@ -3348,7 +3348,7 @@ define i1 @test_class_is_not_pzero_psub_pnorm_pinf_snan__daz(float %arg) #1 {
define i1 @test_class_is_not_pzero_psub_pnorm_pinf_qnan__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_not_pzero_psub_pnorm_pinf_qnan__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 61)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan ninf nzero nsub nnorm) */ i32 61)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 61)
@@ -3357,7 +3357,7 @@ define i1 @test_class_is_not_pzero_psub_pnorm_pinf_qnan__daz(float %arg) #1 {
define i1 @test_class_is_not_pzero_psub_pnorm_pinf_nan__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_not_pzero_psub_pnorm_pinf_nan__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 960)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (pinf pzero psub pnorm) */ i32 960)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 960)
@@ -3366,7 +3366,7 @@ define i1 @test_class_is_not_pzero_psub_pnorm_pinf_nan__daz(float %arg) #1 {
define i1 @test_class_is_not_psub_pnorm_pinf__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_not_psub_pnorm_pinf__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 127)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan ninf zero nsub nnorm) */ i32 127)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 127)
@@ -3375,7 +3375,7 @@ define i1 @test_class_is_not_psub_pnorm_pinf__daz(float %arg) #1 {
define i1 @test_class_is_not_psub_pnorm_pinf_snan__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_not_psub_pnorm_pinf_snan__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 126)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan ninf zero nsub nnorm) */ i32 126)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 126)
@@ -3384,7 +3384,7 @@ define i1 @test_class_is_not_psub_pnorm_pinf_snan__daz(float %arg) #1 {
define i1 @test_class_is_not_psub_pnorm_pinf_qnan__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_not_psub_pnorm_pinf_qnan__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 125)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan ninf zero nsub nnorm) */ i32 125)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 125)
@@ -3393,7 +3393,7 @@ define i1 @test_class_is_not_psub_pnorm_pinf_qnan__daz(float %arg) #1 {
define i1 @test_class_is_not_psub_pnorm_pinf_nan__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_not_psub_pnorm_pinf_nan__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 124)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (ninf zero nsub nnorm) */ i32 124)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 124)
@@ -3411,7 +3411,7 @@ define i1 @test_class_is_not_pnorm_pinf__daz(float %arg) #1 {
define i1 @test_class_is_not_pzero_pnorm_pinf__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_not_pzero_pnorm_pinf__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 319)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan ninf nzero nsub norm) */ i32 319)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 319)
@@ -3420,7 +3420,7 @@ define i1 @test_class_is_not_pzero_pnorm_pinf__daz(float %arg) #1 {
define i1 @test_class_is_not_pzero_pnorm_pinf_nan__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_not_pzero_pnorm_pinf_nan__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 316)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (ninf nzero nsub norm) */ i32 316)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 316)
@@ -3429,7 +3429,7 @@ define i1 @test_class_is_not_pzero_pnorm_pinf_nan__daz(float %arg) #1 {
define i1 @test_class_is_not_nzero_pzero_psub_pnorm_pinf__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_not_nzero_pzero_psub_pnorm_pinf__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 22)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan ninf nsub) */ i32 22)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 22)
@@ -3438,7 +3438,7 @@ define i1 @test_class_is_not_nzero_pzero_psub_pnorm_pinf__daz(float %arg) #1 {
define i1 @test_class_is_not_nzero_pzero_psub_pnorm_pinf_snan__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_not_nzero_pzero_psub_pnorm_pinf_snan__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 30)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan ninf nsub nnorm) */ i32 30)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 30)
@@ -3447,7 +3447,7 @@ define i1 @test_class_is_not_nzero_pzero_psub_pnorm_pinf_snan__daz(float %arg) #
define i1 @test_class_is_not_nzero_pzero_psub_pnorm_pinf_qnan__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_not_nzero_pzero_psub_pnorm_pinf_qnan__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 29)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan ninf nsub nnorm) */ i32 29)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 29)
@@ -3456,7 +3456,7 @@ define i1 @test_class_is_not_nzero_pzero_psub_pnorm_pinf_qnan__daz(float %arg) #
define i1 @test_class_is_not_nzero_pzero_psub_pnorm_pinf_nan__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_not_nzero_pzero_psub_pnorm_pinf_nan__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 28)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (ninf nsub nnorm) */ i32 28)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 28)
@@ -3465,7 +3465,7 @@ define i1 @test_class_is_not_nzero_pzero_psub_pnorm_pinf_nan__daz(float %arg) #1
define i1 @test_class_is_not_nsub_nzero_pzero_psub_pnorm_pinf__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_not_nsub_nzero_pzero_psub_pnorm_pinf__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 6)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan ninf) */ i32 6)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 6)
@@ -3474,7 +3474,7 @@ define i1 @test_class_is_not_nsub_nzero_pzero_psub_pnorm_pinf__daz(float %arg) #
define i1 @test_class_is_not_nsub_nzero_pzero_psub_pnorm_pinf_snan__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_not_nsub_nzero_pzero_psub_pnorm_pinf_snan__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 14)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan ninf nnorm) */ i32 14)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 14)
@@ -3483,7 +3483,7 @@ define i1 @test_class_is_not_nsub_nzero_pzero_psub_pnorm_pinf_snan__daz(float %a
define i1 @test_class_is_not_nsub_nzero_pzero_psub_pnorm_pinf_qnan__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_not_nsub_nzero_pzero_psub_pnorm_pinf_qnan__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 13)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan ninf nnorm) */ i32 13)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 13)
@@ -3501,7 +3501,7 @@ define i1 @test_class_is_not_nsub_nzero_pzero_psub_pnorm_pinf_nan__daz(float %ar
define i1 @test_class_is_not_nzero_psub_pnorm_pinf__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_not_nzero_psub_pnorm_pinf__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 95)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan ninf pzero nsub nnorm) */ i32 95)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 95)
@@ -3510,7 +3510,7 @@ define i1 @test_class_is_not_nzero_psub_pnorm_pinf__daz(float %arg) #1 {
define i1 @test_class_is_not_nzero_nsub_pnorm_pinf__daz(float %arg) #1 {
; CHECK-LABEL: @test_class_is_not_nzero_nsub_pnorm_pinf__daz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 207)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan ninf pzero psub nnorm) */ i32 207)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 207)
@@ -3523,7 +3523,7 @@ define i1 @test_class_is_not_nzero_nsub_pnorm_pinf__daz(float %arg) #1 {
define i1 @test_class_is_pzero_psub_pnorm_pinf__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_pzero_psub_pnorm_pinf__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 960)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (pinf pzero psub pnorm) */ i32 960)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 960)
@@ -3532,7 +3532,7 @@ define i1 @test_class_is_pzero_psub_pnorm_pinf__dapz(float %arg) #2 {
define i1 @test_class_is_pzero_psub_pnorm_pinf_snan__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_pzero_psub_pnorm_pinf_snan__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 961)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan pinf pzero psub pnorm) */ i32 961)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 961)
@@ -3541,7 +3541,7 @@ define i1 @test_class_is_pzero_psub_pnorm_pinf_snan__dapz(float %arg) #2 {
define i1 @test_class_is_pzero_psub_pnorm_pinf_qnan__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_pzero_psub_pnorm_pinf_qnan__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 962)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan pinf pzero psub pnorm) */ i32 962)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 962)
@@ -3550,7 +3550,7 @@ define i1 @test_class_is_pzero_psub_pnorm_pinf_qnan__dapz(float %arg) #2 {
define i1 @test_class_is_pzero_psub_pnorm_pinf_nan__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_pzero_psub_pnorm_pinf_nan__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 963)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan pinf pzero psub pnorm) */ i32 963)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 963)
@@ -3559,7 +3559,7 @@ define i1 @test_class_is_pzero_psub_pnorm_pinf_nan__dapz(float %arg) #2 {
define i1 @test_class_is_psub_pnorm_pinf__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_psub_pnorm_pinf__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 896)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (pinf psub pnorm) */ i32 896)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 896)
@@ -3568,7 +3568,7 @@ define i1 @test_class_is_psub_pnorm_pinf__dapz(float %arg) #2 {
define i1 @test_class_is_psub_pnorm_pinf_snan__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_psub_pnorm_pinf_snan__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 897)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan pinf psub pnorm) */ i32 897)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 897)
@@ -3577,7 +3577,7 @@ define i1 @test_class_is_psub_pnorm_pinf_snan__dapz(float %arg) #2 {
define i1 @test_class_is_psub_pnorm_pinf_qnan__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_psub_pnorm_pinf_qnan__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 898)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan pinf psub pnorm) */ i32 898)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 898)
@@ -3586,7 +3586,7 @@ define i1 @test_class_is_psub_pnorm_pinf_qnan__dapz(float %arg) #2 {
define i1 @test_class_is_psub_pnorm_pinf_nan__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_psub_pnorm_pinf_nan__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 899)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan pinf psub pnorm) */ i32 899)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 899)
@@ -3604,7 +3604,7 @@ define i1 @test_class_is_pnorm_pinf__dapz(float %arg) #2 {
define i1 @test_class_is_pzero_pnorm_pinf__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_pzero_pnorm_pinf__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 704)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (pinf pzero psub) */ i32 704)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 704)
@@ -3613,7 +3613,7 @@ define i1 @test_class_is_pzero_pnorm_pinf__dapz(float %arg) #2 {
define i1 @test_class_is_pzero_pnorm_pinf_nan__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_pzero_pnorm_pinf_nan__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 707)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan pinf pzero psub) */ i32 707)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 707)
@@ -3622,7 +3622,7 @@ define i1 @test_class_is_pzero_pnorm_pinf_nan__dapz(float %arg) #2 {
define i1 @test_class_is_nzero_pzero_psub_pnorm_pinf__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_nzero_pzero_psub_pnorm_pinf__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 992)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (pinf zero psub pnorm) */ i32 992)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 992)
@@ -3631,7 +3631,7 @@ define i1 @test_class_is_nzero_pzero_psub_pnorm_pinf__dapz(float %arg) #2 {
define i1 @test_class_is_nzero_pzero_psub_pnorm_pinf_snan__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_nzero_pzero_psub_pnorm_pinf_snan__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 993)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan pinf zero psub pnorm) */ i32 993)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 993)
@@ -3640,7 +3640,7 @@ define i1 @test_class_is_nzero_pzero_psub_pnorm_pinf_snan__dapz(float %arg) #2 {
define i1 @test_class_is_nzero_pzero_psub_pnorm_pinf_qnan__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_nzero_pzero_psub_pnorm_pinf_qnan__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 994)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan pinf zero psub pnorm) */ i32 994)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 994)
@@ -3649,7 +3649,7 @@ define i1 @test_class_is_nzero_pzero_psub_pnorm_pinf_qnan__dapz(float %arg) #2 {
define i1 @test_class_is_nzero_pzero_psub_pnorm_pinf_nan__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_nzero_pzero_psub_pnorm_pinf_nan__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 995)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan pinf zero psub pnorm) */ i32 995)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 995)
@@ -3658,7 +3658,7 @@ define i1 @test_class_is_nzero_pzero_psub_pnorm_pinf_nan__dapz(float %arg) #2 {
define i1 @test_class_is_nsub_nzero_pzero_psub_pnorm_pinf__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_nsub_nzero_pzero_psub_pnorm_pinf__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 1017)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan pinf zero sub norm) */ i32 1017)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 1017)
@@ -3667,7 +3667,7 @@ define i1 @test_class_is_nsub_nzero_pzero_psub_pnorm_pinf__dapz(float %arg) #2 {
define i1 @test_class_is_nsub_nzero_pzero_psub_pnorm_pinf_snan__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_nsub_nzero_pzero_psub_pnorm_pinf_snan__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 1009)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan pinf zero sub pnorm) */ i32 1009)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 1009)
@@ -3676,7 +3676,7 @@ define i1 @test_class_is_nsub_nzero_pzero_psub_pnorm_pinf_snan__dapz(float %arg)
define i1 @test_class_is_nsub_nzero_pzero_psub_pnorm_pinf_qnan__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_nsub_nzero_pzero_psub_pnorm_pinf_qnan__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 1010)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan pinf zero sub pnorm) */ i32 1010)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 1010)
@@ -3694,7 +3694,7 @@ define i1 @test_class_is_nsub_nzero_pzero_psub_pnorm_pinf_nan__dapz(float %arg)
define i1 @test_class_is_nzero_psub_pnorm_pinf__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_nzero_psub_pnorm_pinf__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 928)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (pinf nzero psub pnorm) */ i32 928)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 928)
@@ -3703,7 +3703,7 @@ define i1 @test_class_is_nzero_psub_pnorm_pinf__dapz(float %arg) #2 {
define i1 @test_class_is_nzero_nsub_pnorm_pinf__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_nzero_nsub_pnorm_pinf__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 816)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (pinf nzero nsub pnorm) */ i32 816)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 816)
@@ -3713,7 +3713,7 @@ define i1 @test_class_is_nzero_nsub_pnorm_pinf__dapz(float %arg) #2 {
define i1 @test_class_is_not_pzero_psub_pnorm_pinf__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_not_pzero_psub_pnorm_pinf__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 63)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan ninf nzero nsub nnorm) */ i32 63)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 63)
@@ -3722,7 +3722,7 @@ define i1 @test_class_is_not_pzero_psub_pnorm_pinf__dapz(float %arg) #2 {
define i1 @test_class_is_not_pzero_psub_pnorm_pinf_snan__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_not_pzero_psub_pnorm_pinf_snan__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 62)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan ninf nzero nsub nnorm) */ i32 62)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 62)
@@ -3731,7 +3731,7 @@ define i1 @test_class_is_not_pzero_psub_pnorm_pinf_snan__dapz(float %arg) #2 {
define i1 @test_class_is_not_pzero_psub_pnorm_pinf_qnan__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_not_pzero_psub_pnorm_pinf_qnan__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 61)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan ninf nzero nsub nnorm) */ i32 61)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 61)
@@ -3740,7 +3740,7 @@ define i1 @test_class_is_not_pzero_psub_pnorm_pinf_qnan__dapz(float %arg) #2 {
define i1 @test_class_is_not_pzero_psub_pnorm_pinf_nan__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_not_pzero_psub_pnorm_pinf_nan__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 960)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (pinf pzero psub pnorm) */ i32 960)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 960)
@@ -3749,7 +3749,7 @@ define i1 @test_class_is_not_pzero_psub_pnorm_pinf_nan__dapz(float %arg) #2 {
define i1 @test_class_is_not_psub_pnorm_pinf__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_not_psub_pnorm_pinf__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 127)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan ninf zero nsub nnorm) */ i32 127)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 127)
@@ -3758,7 +3758,7 @@ define i1 @test_class_is_not_psub_pnorm_pinf__dapz(float %arg) #2 {
define i1 @test_class_is_not_psub_pnorm_pinf_snan__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_not_psub_pnorm_pinf_snan__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 126)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan ninf zero nsub nnorm) */ i32 126)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 126)
@@ -3767,7 +3767,7 @@ define i1 @test_class_is_not_psub_pnorm_pinf_snan__dapz(float %arg) #2 {
define i1 @test_class_is_not_psub_pnorm_pinf_qnan__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_not_psub_pnorm_pinf_qnan__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 125)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan ninf zero nsub nnorm) */ i32 125)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 125)
@@ -3776,7 +3776,7 @@ define i1 @test_class_is_not_psub_pnorm_pinf_qnan__dapz(float %arg) #2 {
define i1 @test_class_is_not_psub_pnorm_pinf_nan__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_not_psub_pnorm_pinf_nan__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 124)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (ninf zero nsub nnorm) */ i32 124)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 124)
@@ -3794,7 +3794,7 @@ define i1 @test_class_is_not_pnorm_pinf__dapz(float %arg) #2 {
define i1 @test_class_is_not_pzero_pnorm_pinf__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_not_pzero_pnorm_pinf__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 319)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan ninf nzero nsub norm) */ i32 319)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 319)
@@ -3803,7 +3803,7 @@ define i1 @test_class_is_not_pzero_pnorm_pinf__dapz(float %arg) #2 {
define i1 @test_class_is_not_pzero_pnorm_pinf_nan__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_not_pzero_pnorm_pinf_nan__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 316)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (ninf nzero nsub norm) */ i32 316)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 316)
@@ -3812,7 +3812,7 @@ define i1 @test_class_is_not_pzero_pnorm_pinf_nan__dapz(float %arg) #2 {
define i1 @test_class_is_not_nzero_pzero_psub_pnorm_pinf__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_not_nzero_pzero_psub_pnorm_pinf__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 22)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan ninf nsub) */ i32 22)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 22)
@@ -3821,7 +3821,7 @@ define i1 @test_class_is_not_nzero_pzero_psub_pnorm_pinf__dapz(float %arg) #2 {
define i1 @test_class_is_not_nzero_pzero_psub_pnorm_pinf_snan__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_not_nzero_pzero_psub_pnorm_pinf_snan__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 30)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan ninf nsub nnorm) */ i32 30)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 30)
@@ -3830,7 +3830,7 @@ define i1 @test_class_is_not_nzero_pzero_psub_pnorm_pinf_snan__dapz(float %arg)
define i1 @test_class_is_not_nzero_pzero_psub_pnorm_pinf_qnan__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_not_nzero_pzero_psub_pnorm_pinf_qnan__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 29)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan ninf nsub nnorm) */ i32 29)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 29)
@@ -3839,7 +3839,7 @@ define i1 @test_class_is_not_nzero_pzero_psub_pnorm_pinf_qnan__dapz(float %arg)
define i1 @test_class_is_not_nzero_pzero_psub_pnorm_pinf_nan__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_not_nzero_pzero_psub_pnorm_pinf_nan__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 28)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (ninf nsub nnorm) */ i32 28)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 28)
@@ -3848,7 +3848,7 @@ define i1 @test_class_is_not_nzero_pzero_psub_pnorm_pinf_nan__dapz(float %arg) #
define i1 @test_class_is_not_nsub_nzero_pzero_psub_pnorm_pinf__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_not_nsub_nzero_pzero_psub_pnorm_pinf__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 6)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan ninf) */ i32 6)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 6)
@@ -3857,7 +3857,7 @@ define i1 @test_class_is_not_nsub_nzero_pzero_psub_pnorm_pinf__dapz(float %arg)
define i1 @test_class_is_not_nsub_nzero_pzero_psub_pnorm_pinf_snan__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_not_nsub_nzero_pzero_psub_pnorm_pinf_snan__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 14)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (qnan ninf nnorm) */ i32 14)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 14)
@@ -3866,7 +3866,7 @@ define i1 @test_class_is_not_nsub_nzero_pzero_psub_pnorm_pinf_snan__dapz(float %
define i1 @test_class_is_not_nsub_nzero_pzero_psub_pnorm_pinf_qnan__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_not_nsub_nzero_pzero_psub_pnorm_pinf_qnan__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 13)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (snan ninf nnorm) */ i32 13)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 13)
@@ -3884,7 +3884,7 @@ define i1 @test_class_is_not_nsub_nzero_pzero_psub_pnorm_pinf_nan__dapz(float %a
define i1 @test_class_is_not_nzero_psub_pnorm_pinf__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_not_nzero_psub_pnorm_pinf__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 95)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan ninf pzero nsub nnorm) */ i32 95)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 95)
@@ -3893,7 +3893,7 @@ define i1 @test_class_is_not_nzero_psub_pnorm_pinf__dapz(float %arg) #2 {
define i1 @test_class_is_not_nzero_nsub_pnorm_pinf__dapz(float %arg) #2 {
; CHECK-LABEL: @test_class_is_not_nzero_nsub_pnorm_pinf__dapz(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 207)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan ninf pzero psub nnorm) */ i32 207)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 207)
@@ -3906,7 +3906,7 @@ define i1 @test_class_is_not_nzero_nsub_pnorm_pinf__dapz(float %arg) #2 {
define i1 @test_class_is_psub_pnorm_pinf__dynamic(float %arg) #3 {
; CHECK-LABEL: @test_class_is_psub_pnorm_pinf__dynamic(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 896)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (pinf psub pnorm) */ i32 896)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 896)
@@ -3915,7 +3915,7 @@ define i1 @test_class_is_psub_pnorm_pinf__dynamic(float %arg) #3 {
define i1 @test_class_is_not_psub_pnorm_pinf__dynamic(float %arg) #3 {
; CHECK-LABEL: @test_class_is_not_psub_pnorm_pinf__dynamic(
-; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], i32 127)
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[ARG:%.*]], /* (nan ninf zero nsub nnorm) */ i32 127)
; CHECK-NEXT: ret i1 [[CLASS]]
;
%class = call i1 @llvm.is.fpclass.f32(float %arg, i32 127)
@@ -3943,7 +3943,7 @@ define i1 @minnum_qnan_commuted(i32 %x, float nofpclass(nnorm nsub nzero ninf na
; CHECK-NEXT: [[QNAN_BITS:%.*]] = or i32 [[X:%.*]], -5938
; CHECK-NEXT: [[QNAN:%.*]] = bitcast i32 [[QNAN_BITS]] to float
; CHECK-NEXT: [[MIN:%.*]] = call float @llvm.minnum.f32(float [[Y:%.*]], float [[QNAN]])
-; CHECK-NEXT: [[TEST:%.*]] = call i1 @llvm.is.fpclass.f32(float [[MIN]], i32 64)
+; CHECK-NEXT: [[TEST:%.*]] = call i1 @llvm.is.fpclass.f32(float [[MIN]], /* (pzero) */ i32 64)
; CHECK-NEXT: ret i1 [[TEST]]
;
entry:
diff --git a/llvm/test/Transforms/InstCombine/pr80941.ll b/llvm/test/Transforms/InstCombine/pr80941.ll
index 95242b1d1407b..4e592cea2e76b 100644
--- a/llvm/test/Transforms/InstCombine/pr80941.ll
+++ b/llvm/test/Transforms/InstCombine/pr80941.ll
@@ -5,7 +5,7 @@ define float @pr80941(float %arg) {
; CHECK-LABEL: define float @pr80941(
; CHECK-SAME: float [[ARG:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[COND:%.*]] = tail call i1 @llvm.is.fpclass.f32(float [[ARG]], i32 144)
+; CHECK-NEXT: [[COND:%.*]] = tail call i1 @llvm.is.fpclass.f32(float [[ARG]], /* (sub) */ i32 144)
; CHECK-NEXT: br i1 [[COND]], label [[IF_THEN:%.*]], label [[IF_EXIT:%.*]]
; CHECK: if.then:
; CHECK-NEXT: [[FPEXT:%.*]] = fpext float [[ARG]] to double
diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fdiv.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fdiv.ll
index 343e453b9f88a..2a3487a1b9ca7 100644
--- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fdiv.ll
+++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fdiv.ll
@@ -247,7 +247,7 @@ define nofpclass(inf) half @ret_src_must_be_zero_or_nan_self_other_use_input1(ha
define nofpclass(snan) half @ret_src_nonan_self(half noundef nofpclass(nan) %x) !prof !0 {
; CHECK-LABEL: define nofpclass(snan) half @ret_src_nonan_self(
; CHECK-SAME: half noundef nofpclass(nan) [[X:%.*]]) !prof [[PROF0:![0-9]+]] {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 612)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], /* (inf zero) */ i32 612)
; CHECK-NEXT: [[DIV:%.*]] = select i1 [[TMP1]], half +qnan, half 1.000000e+00, !prof [[PROF1:![0-9]+]]
; CHECK-NEXT: ret half [[DIV]]
;
@@ -278,7 +278,7 @@ define nofpclass(snan) half @ret_src_noinf_self(half noundef nofpclass(inf) %x)
define nofpclass(inf) half @ret_noinf_self(half noundef %x) {
; CHECK-LABEL: define nofpclass(inf) half @ret_noinf_self(
; CHECK-SAME: half noundef [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 615)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], /* (nan inf zero) */ i32 615)
; CHECK-NEXT: [[DIV:%.*]] = select i1 [[TMP1]], half +qnan, half 1.000000e+00
; CHECK-NEXT: ret half [[DIV]]
;
@@ -361,7 +361,7 @@ define nofpclass(snan) half @ret_fdiv_nnan_self(half noundef %x) {
define nofpclass(snan) half @ret_fdiv_ninf_self(half noundef %x) {
; CHECK-LABEL: define nofpclass(snan) half @ret_fdiv_ninf_self(
; CHECK-SAME: half noundef [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 615)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], /* (nan inf zero) */ i32 615)
; CHECK-NEXT: [[DIV:%.*]] = select ninf i1 [[TMP1]], half +qnan, half 1.000000e+00
; CHECK-NEXT: ret half [[DIV]]
;
@@ -390,7 +390,7 @@ define nofpclass(pnorm) half @ret_nopnorm_self(half noundef %x) {
define nofpclass(ninf) half @ret_noninf_self(half noundef %x) {
; CHECK-LABEL: define nofpclass(ninf) half @ret_noninf_self(
; CHECK-SAME: half noundef [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 615)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], /* (nan inf zero) */ i32 615)
; CHECK-NEXT: [[DIV:%.*]] = select i1 [[TMP1]], half +qnan, half 1.000000e+00
; CHECK-NEXT: ret half [[DIV]]
;
@@ -401,7 +401,7 @@ define nofpclass(ninf) half @ret_noninf_self(half noundef %x) {
define nofpclass(pinf) half @ret_nopinf_self(half noundef %x) {
; CHECK-LABEL: define nofpclass(pinf) half @ret_nopinf_self(
; CHECK-SAME: half noundef [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 615)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], /* (nan inf zero) */ i32 615)
; CHECK-NEXT: [[DIV:%.*]] = select i1 [[TMP1]], half +qnan, half 1.000000e+00
; CHECK-NEXT: ret half [[DIV]]
;
@@ -412,7 +412,7 @@ define nofpclass(pinf) half @ret_nopinf_self(half noundef %x) {
define nofpclass(zero) half @ret_nozero_self(half noundef %x) {
; CHECK-LABEL: define nofpclass(zero) half @ret_nozero_self(
; CHECK-SAME: half noundef [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 615)
+; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], /* (nan inf zero) */ i32 615)
; CHECK-NEXT: [[DIV:%.*]] = select i1 [[TMP1]], half +qnan, half 1.000000e+00
; CHECK-NEXT: ret half [[DIV]]
;
@@ -2354,7 +2354,7 @@ define float @fdiv_replacement_insert_point_regression(i1 %cmp, float %x, float
; CHECK-LABEL: define float @fdiv_replacement_insert_point_regression(
; CHECK-SAME: i1 [[CMP:%.*]], float [[X:%.*]], float noundef [[Y:%.*]], float noundef [[Z:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = call i1 @llvm.is.fpclass.f32(float [[Y]], i32 615)
+; CHECK-NEXT: [[TMP0:%.*]] = call i1 @llvm.is.fpclass.f32(float [[Y]], /* (nan inf zero) */ i32 615)
; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[TMP0]], float +qnan, float 1.000000e+00
; CHECK-NEXT: [[SCALE_0:%.*]] = select i1 [[CMP]], float [[TMP1]], float [[Y]]
; CHECK-NEXT: [[MUL:%.*]] = fmul float [[SCALE_0]], [[X]]
diff --git a/llvm/test/Transforms/InstSimplify/canonicalize.ll b/llvm/test/Transforms/InstSimplify/canonicalize.ll
index e921e80dcafc2..985110a64dfcb 100644
--- a/llvm/test/Transforms/InstSimplify/canonicalize.ll
+++ b/llvm/test/Transforms/InstSimplify/canonicalize.ll
@@ -769,7 +769,7 @@ define ppc_fp128 @canonicalize_neg1.0_ppcf128() {
define i1 @is_poszero_daz_enabled_check_dynamic() denormal_fpenv(ieee|dynamic) {
; CHECK-LABEL: @is_poszero_daz_enabled_check_dynamic(
; CHECK-NEXT: [[CANONICAL:%.*]] = call float @llvm.canonicalize.f32(float 1.401300e-45)
-; CHECK-NEXT: [[IS_POS_ZERO:%.*]] = call i1 @llvm.is.fpclass.f32(float [[CANONICAL]], i32 64)
+; CHECK-NEXT: [[IS_POS_ZERO:%.*]] = call i1 @llvm.is.fpclass.f32(float [[CANONICAL]], /* (pzero) */ i32 64)
; CHECK-NEXT: ret i1 [[IS_POS_ZERO]]
;
%canonical = call float @llvm.canonicalize.f32(float bitcast (i32 1 to float))
@@ -780,7 +780,7 @@ define i1 @is_poszero_daz_enabled_check_dynamic() denormal_fpenv(ieee|dynamic) {
define i1 @is_preserve_sign_daz_enabled_check_dynamic() denormal_fpenv(ieee|dynamic) {
; CHECK-LABEL: @is_preserve_sign_daz_enabled_check_dynamic(
; CHECK-NEXT: [[CANONICAL:%.*]] = call float @llvm.canonicalize.f32(float -1.401300e-45)
-; CHECK-NEXT: [[IS_NEG_ZERO:%.*]] = call i1 @llvm.is.fpclass.f32(float [[CANONICAL]], i32 32)
+; CHECK-NEXT: [[IS_NEG_ZERO:%.*]] = call i1 @llvm.is.fpclass.f32(float [[CANONICAL]], /* (nzero) */ i32 32)
; CHECK-NEXT: ret i1 [[IS_NEG_ZERO]]
;
%canonical = call float @llvm.canonicalize.f32(float bitcast (i32 -2147483647 to float))
@@ -791,7 +791,7 @@ define i1 @is_preserve_sign_daz_enabled_check_dynamic() denormal_fpenv(ieee|dyna
define i1 @is_positive_zero_daz_enabled_check_dynamic() denormal_fpenv(ieee|dynamic) {
; CHECK-LABEL: @is_positive_zero_daz_enabled_check_dynamic(
; CHECK-NEXT: [[CANONICAL:%.*]] = call float @llvm.canonicalize.f32(float -1.401300e-45)
-; CHECK-NEXT: [[IS_POS_ZERO:%.*]] = call i1 @llvm.is.fpclass.f32(float [[CANONICAL]], i32 64)
+; CHECK-NEXT: [[IS_POS_ZERO:%.*]] = call i1 @llvm.is.fpclass.f32(float [[CANONICAL]], /* (pzero) */ i32 64)
; CHECK-NEXT: ret i1 [[IS_POS_ZERO]]
;
%canonical = call float @llvm.canonicalize.f32(float bitcast (i32 -2147483647 to float))
@@ -802,7 +802,7 @@ define i1 @is_positive_zero_daz_enabled_check_dynamic() denormal_fpenv(ieee|dyna
define i1 @is_any_daz_enabled_check_dynamic() denormal_fpenv(ieee|dynamic) {
; CHECK-LABEL: @is_any_daz_enabled_check_dynamic(
; CHECK-NEXT: [[CANONICAL:%.*]] = call float @llvm.canonicalize.f32(float -1.401300e-45)
-; CHECK-NEXT: [[IS_ANY_ZERO:%.*]] = call i1 @llvm.is.fpclass.f32(float [[CANONICAL]], i32 96)
+; CHECK-NEXT: [[IS_ANY_ZERO:%.*]] = call i1 @llvm.is.fpclass.f32(float [[CANONICAL]], /* (zero) */ i32 96)
; CHECK-NEXT: ret i1 [[IS_ANY_ZERO]]
;
%canonical = call float @llvm.canonicalize.f32(float bitcast (i32 -2147483647 to float))
@@ -813,7 +813,7 @@ define i1 @is_any_daz_enabled_check_dynamic() denormal_fpenv(ieee|dynamic) {
define i1 @is_not_daz_enabled_check_dynamic() denormal_fpenv(ieee|dynamic) {
; CHECK-LABEL: @is_not_daz_enabled_check_dynamic(
; CHECK-NEXT: [[CANONICAL:%.*]] = call float @llvm.canonicalize.f32(float 1.401300e-45)
-; CHECK-NEXT: [[IS_NOT_POS_ZERO:%.*]] = call i1 @llvm.is.fpclass.f32(float [[CANONICAL]], i32 959)
+; CHECK-NEXT: [[IS_NOT_POS_ZERO:%.*]] = call i1 @llvm.is.fpclass.f32(float [[CANONICAL]], /* (nan inf nzero sub norm) */ i32 959)
; CHECK-NEXT: ret i1 [[IS_NOT_POS_ZERO]]
;
%canonical = call float @llvm.canonicalize.f32(float bitcast (i32 1 to float))
diff --git a/llvm/test/Transforms/LoopVectorize/is_fpclass.ll b/llvm/test/Transforms/LoopVectorize/is_fpclass.ll
index 772bbb5ee45bf..ae199526d02d1 100644
--- a/llvm/test/Transforms/LoopVectorize/is_fpclass.ll
+++ b/llvm/test/Transforms/LoopVectorize/is_fpclass.ll
@@ -13,7 +13,7 @@ define void @d() {
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x float> poison, float [[TMP0]], i64 0
; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x float> [[BROADCAST_SPLATINSERT]], <2 x float> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr float, ptr @d, i64 [[INDEX]]
-; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[BROADCAST_SPLAT]], i32 0)
+; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[BROADCAST_SPLAT]], /* (none) */ i32 0)
; CHECK-NEXT: [[TMP3:%.*]] = select <2 x i1> [[TMP2]], <2 x float> zeroinitializer, <2 x float> splat (float 1.000000e+00)
; CHECK-NEXT: store <2 x float> [[TMP3]], ptr [[TMP1]], align 4
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
diff --git a/llvm/test/Transforms/SLPVectorizer/is_fpclass.ll b/llvm/test/Transforms/SLPVectorizer/is_fpclass.ll
index d76f9f5164f3e..2aa39ac86d590 100644
--- a/llvm/test/Transforms/SLPVectorizer/is_fpclass.ll
+++ b/llvm/test/Transforms/SLPVectorizer/is_fpclass.ll
@@ -4,7 +4,7 @@
define <2 x i1> @scalarize_is_fpclass(<2 x float> %x) {
; CHECK-LABEL: define <2 x i1> @scalarize_is_fpclass
; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[X]], i32 123)
+; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[X]], /* (nan zero nsub nnorm) */ i32 123)
; CHECK-NEXT: ret <2 x i1> [[TMP1]]
;
%x.i0 = extractelement <2 x float> %x, i32 0
diff --git a/llvm/test/Transforms/Scalarizer/intrinsics.ll b/llvm/test/Transforms/Scalarizer/intrinsics.ll
index 070c765294ba1..da16943ae075e 100644
--- a/llvm/test/Transforms/Scalarizer/intrinsics.ll
+++ b/llvm/test/Transforms/Scalarizer/intrinsics.ll
@@ -293,9 +293,9 @@ define <2 x i32> @scalarize_llround(<2 x float> %x) #0 {
define <2 x i1> @scalarize_is_fpclass(<2 x float> %x) #0 {
; CHECK-LABEL: @scalarize_is_fpclass(
; CHECK-NEXT: [[X_I0:%.*]] = extractelement <2 x float> [[X:%.*]], i64 0
-; CHECK-NEXT: [[ISFPCLASS_I0:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X_I0]], i32 123)
+; CHECK-NEXT: [[ISFPCLASS_I0:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X_I0]], /* (nan zero nsub nnorm) */ i32 123)
; CHECK-NEXT: [[X_I1:%.*]] = extractelement <2 x float> [[X]], i64 1
-; CHECK-NEXT: [[ISFPCLASS_I1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X_I1]], i32 123)
+; CHECK-NEXT: [[ISFPCLASS_I1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X_I1]], /* (nan zero nsub nnorm) */ i32 123)
; CHECK-NEXT: [[ISFPCLASS_UPTO0:%.*]] = insertelement <2 x i1> poison, i1 [[ISFPCLASS_I0]], i64 0
; CHECK-NEXT: [[ISFPCLASS:%.*]] = insertelement <2 x i1> [[ISFPCLASS_UPTO0]], i1 [[ISFPCLASS_I1]], i64 1
; CHECK-NEXT: ret <2 x i1> [[ISFPCLASS]]
diff --git a/llvm/test/Transforms/SpeculativeExecution/spec-calls.ll b/llvm/test/Transforms/SpeculativeExecution/spec-calls.ll
index f9033e790efe9..3a4ddf530a805 100644
--- a/llvm/test/Transforms/SpeculativeExecution/spec-calls.ll
+++ b/llvm/test/Transforms/SpeculativeExecution/spec-calls.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt < %s -S -passes=speculative-execution \
; RUN: -spec-exec-max-speculation-cost 4 -spec-exec-max-not-hoisted 3 \
; RUN: | FileCheck %s
@@ -8,10 +9,15 @@ declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone
declare float @unknown(float)
declare float @unknown_readnone(float) nounwind readnone
-; CHECK-LABEL: @ifThen_fabs(
-; CHECK: call float @llvm.fabs.f32(
-; CHECK: br i1 true
define void @ifThen_fabs() {
+; CHECK-LABEL: define void @ifThen_fabs() {
+; CHECK-NEXT: [[X:%.*]] = call float @llvm.fabs.f32(float 1.000000e+00)
+; CHECK-NEXT: br i1 true, label %[[A:.*]], label %[[B:.*]]
+; CHECK: [[A]]:
+; CHECK-NEXT: br label %[[B]]
+; CHECK: [[B]]:
+; CHECK-NEXT: ret void
+;
br i1 true, label %a, label %b
a:
@@ -22,10 +28,15 @@ b:
ret void
}
-; CHECK-LABEL: @ifThen_ctlz(
-; CHECK: call i32 @llvm.ctlz.i32(
-; CHECK: br i1 true
define void @ifThen_ctlz() {
+; CHECK-LABEL: define void @ifThen_ctlz() {
+; CHECK-NEXT: [[X:%.*]] = call i32 @llvm.ctlz.i32(i32 0, i1 true)
+; CHECK-NEXT: br i1 true, label %[[A:.*]], label %[[B:.*]]
+; CHECK: [[A]]:
+; CHECK-NEXT: br label %[[B]]
+; CHECK: [[B]]:
+; CHECK-NEXT: ret void
+;
br i1 true, label %a, label %b
a:
@@ -36,10 +47,15 @@ b:
ret void
}
-; CHECK-LABEL: @ifThen_call_sideeffects(
-; CHECK: br i1 true
-; CHECK: call float @unknown(
define void @ifThen_call_sideeffects() {
+; CHECK-LABEL: define void @ifThen_call_sideeffects() {
+; CHECK-NEXT: br i1 true, label %[[A:.*]], label %[[B:.*]]
+; CHECK: [[A]]:
+; CHECK-NEXT: [[X:%.*]] = call float @unknown(float 1.000000e+00)
+; CHECK-NEXT: br label %[[B]]
+; CHECK: [[B]]:
+; CHECK-NEXT: ret void
+;
br i1 true, label %a, label %b
a:
@@ -50,10 +66,15 @@ b:
ret void
}
-; CHECK-LABEL: @ifThen_call_readnone(
-; CHECK: br i1 true
-; CHECK: call float @unknown_readnone(
define void @ifThen_call_readnone() {
+; CHECK-LABEL: define void @ifThen_call_readnone() {
+; CHECK-NEXT: br i1 true, label %[[A:.*]], label %[[B:.*]]
+; CHECK: [[A]]:
+; CHECK-NEXT: [[X:%.*]] = call float @unknown_readnone(float 1.000000e+00)
+; CHECK-NEXT: br label %[[B]]
+; CHECK: [[B]]:
+; CHECK-NEXT: ret void
+;
br i1 true, label %a, label %b
a:
%x = call float @unknown_readnone(float 1.0)
@@ -63,10 +84,16 @@ b:
ret void
}
-; CHECK-LABEL: @ifThen_fpclass(
-; CHECK: %class = call i1 @llvm.is.fpclass.f32(float %x, i32 11)
-; CHECK-NEXT: br i1 true
define void @ifThen_fpclass(float %x) {
+; CHECK-LABEL: define void @ifThen_fpclass(
+; CHECK-SAME: float [[X:%.*]]) {
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X]], /* (nan nnorm) */ i32 11)
+; CHECK-NEXT: br i1 true, label %[[A:.*]], label %[[B:.*]]
+; CHECK: [[A]]:
+; CHECK-NEXT: br label %[[B]]
+; CHECK: [[B]]:
+; CHECK-NEXT: ret void
+;
br i1 true, label %a, label %b
a:
@@ -77,10 +104,16 @@ b:
ret void
}
-; CHECK-LABEL: @ifThen_arithmetic_fence(
-; CHECK: %fence = call float @llvm.arithmetic.fence.f32(float %x)
-; CHECK-NEXT: br i1 true
define void @ifThen_arithmetic_fence(float %x) {
+; CHECK-LABEL: define void @ifThen_arithmetic_fence(
+; CHECK-SAME: float [[X:%.*]]) {
+; CHECK-NEXT: [[FENCE:%.*]] = call float @llvm.arithmetic.fence.f32(float [[X]])
+; CHECK-NEXT: br i1 true, label %[[A:.*]], label %[[B:.*]]
+; CHECK: [[A]]:
+; CHECK-NEXT: br label %[[B]]
+; CHECK: [[B]]:
+; CHECK-NEXT: ret void
+;
br i1 true, label %a, label %b
a:
@@ -94,10 +127,16 @@ b:
declare i1 @llvm.is.fpclass.f32(float, i32)
declare float @llvm.arithmetic.fence.f32(float)
-; CHECK-LABEL: @ifThen_fptrunc_round(
-; CHECK: %round = call half @llvm.fptrunc.round.f16.f32(float %x, metadata !"round.downward")
-; CHECK-NEXT: br i1 true
define void @ifThen_fptrunc_round(float %x) {
+; CHECK-LABEL: define void @ifThen_fptrunc_round(
+; CHECK-SAME: float [[X:%.*]]) {
+; CHECK-NEXT: [[ROUND:%.*]] = call half @llvm.fptrunc.round.f16.f32(float [[X]], metadata !"round.downward")
+; CHECK-NEXT: br i1 true, label %[[A:.*]], label %[[B:.*]]
+; CHECK: [[A]]:
+; CHECK-NEXT: br label %[[B]]
+; CHECK: [[B]]:
+; CHECK-NEXT: ret void
+;
br i1 true, label %a, label %b
a:
@@ -110,10 +149,16 @@ b:
declare half @llvm.fptrunc.round.f16.f32(float, metadata)
-; CHECK-LABEL: @ifThen_vector_reduce_fadd(
-; CHECK: %reduce = call float @llvm.vector.reduce.fadd.v2f32(float %x, <2 x float> %y)
-; CHECK-NEXT: br i1 true
define void @ifThen_vector_reduce_fadd(float %x, <2 x float> %y) {
+; CHECK-LABEL: define void @ifThen_vector_reduce_fadd(
+; CHECK-SAME: float [[X:%.*]], <2 x float> [[Y:%.*]]) {
+; CHECK-NEXT: [[REDUCE:%.*]] = call float @llvm.vector.reduce.fadd.v2f32(float [[X]], <2 x float> [[Y]])
+; CHECK-NEXT: br i1 true, label %[[A:.*]], label %[[B:.*]]
+; CHECK: [[A]]:
+; CHECK-NEXT: br label %[[B]]
+; CHECK: [[B]]:
+; CHECK-NEXT: ret void
+;
br i1 true, label %a, label %b
a:
@@ -126,10 +171,16 @@ b:
declare float @llvm.vector.reduce.fadd.v2f32(float, <2 x float>)
-; CHECK-LABEL: @ifThen_vector_reduce_fmul(
-; CHECK: %reduce = call float @llvm.vector.reduce.fmul.v2f32(float %x, <2 x float> %y)
-; CHECK-NEXT: br i1 true
define void @ifThen_vector_reduce_fmul(float %x, <2 x float> %y) {
+; CHECK-LABEL: define void @ifThen_vector_reduce_fmul(
+; CHECK-SAME: float [[X:%.*]], <2 x float> [[Y:%.*]]) {
+; CHECK-NEXT: [[REDUCE:%.*]] = call float @llvm.vector.reduce.fmul.v2f32(float [[X]], <2 x float> [[Y]])
+; CHECK-NEXT: br i1 true, label %[[A:.*]], label %[[B:.*]]
+; CHECK: [[A]]:
+; CHECK-NEXT: br label %[[B]]
+; CHECK: [[B]]:
+; CHECK-NEXT: ret void
+;
br i1 true, label %a, label %b
a:
@@ -142,10 +193,16 @@ b:
declare float @llvm.vector.reduce.fmul.v2f32(float, <2 x float>)
-; CHECK-LABEL: @ifThen_vector_reduce_add(
-; CHECK: %reduce = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> %x)
-; CHECK-NEXT: br i1 true
define void @ifThen_vector_reduce_add(<2 x i32> %x) {
+; CHECK-LABEL: define void @ifThen_vector_reduce_add(
+; CHECK-SAME: <2 x i32> [[X:%.*]]) {
+; CHECK-NEXT: [[REDUCE:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[X]])
+; CHECK-NEXT: br i1 true, label %[[A:.*]], label %[[B:.*]]
+; CHECK: [[A]]:
+; CHECK-NEXT: br label %[[B]]
+; CHECK: [[B]]:
+; CHECK-NEXT: ret void
+;
br i1 true, label %a, label %b
a:
@@ -158,10 +215,16 @@ b:
declare i32 @llvm.vector.reduce.add.v2i32(<2 x i32>)
-; CHECK-LABEL: @ifThen_vector_reduce_mul(
-; CHECK: %reduce = call i32 @llvm.vector.reduce.mul.v2i32(<2 x i32> %x)
-; CHECK-NEXT: br i1 true
define void @ifThen_vector_reduce_mul(<2 x i32> %x) {
+; CHECK-LABEL: define void @ifThen_vector_reduce_mul(
+; CHECK-SAME: <2 x i32> [[X:%.*]]) {
+; CHECK-NEXT: [[REDUCE:%.*]] = call i32 @llvm.vector.reduce.mul.v2i32(<2 x i32> [[X]])
+; CHECK-NEXT: br i1 true, label %[[A:.*]], label %[[B:.*]]
+; CHECK: [[A]]:
+; CHECK-NEXT: br label %[[B]]
+; CHECK: [[B]]:
+; CHECK-NEXT: ret void
+;
br i1 true, label %a, label %b
a:
@@ -175,10 +238,16 @@ b:
declare i32 @llvm.vector.reduce.mul.v2i32(<2 x i32>)
-; CHECK-LABEL: @ifThen_vector_reduce_and(
-; CHECK: %reduce = call i32 @llvm.vector.reduce.and.v2i32(<2 x i32> %x)
-; CHECK-NEXT: br i1 true
define void @ifThen_vector_reduce_and(<2 x i32> %x) {
+; CHECK-LABEL: define void @ifThen_vector_reduce_and(
+; CHECK-SAME: <2 x i32> [[X:%.*]]) {
+; CHECK-NEXT: [[REDUCE:%.*]] = call i32 @llvm.vector.reduce.and.v2i32(<2 x i32> [[X]])
+; CHECK-NEXT: br i1 true, label %[[A:.*]], label %[[B:.*]]
+; CHECK: [[A]]:
+; CHECK-NEXT: br label %[[B]]
+; CHECK: [[B]]:
+; CHECK-NEXT: ret void
+;
br i1 true, label %a, label %b
a:
@@ -191,10 +260,16 @@ b:
declare i32 @llvm.vector.reduce.and.v2i32(<2 x i32>)
-; CHECK-LABEL: @ifThen_vector_reduce_or(
-; CHECK: %reduce = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> %x)
-; CHECK-NEXT: br i1 true
define void @ifThen_vector_reduce_or(<2 x i32> %x) {
+; CHECK-LABEL: define void @ifThen_vector_reduce_or(
+; CHECK-SAME: <2 x i32> [[X:%.*]]) {
+; CHECK-NEXT: [[REDUCE:%.*]] = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> [[X]])
+; CHECK-NEXT: br i1 true, label %[[A:.*]], label %[[B:.*]]
+; CHECK: [[A]]:
+; CHECK-NEXT: br label %[[B]]
+; CHECK: [[B]]:
+; CHECK-NEXT: ret void
+;
br i1 true, label %a, label %b
a:
@@ -207,10 +282,16 @@ b:
declare i32 @llvm.vector.reduce.or.v2i32(<2 x i32>)
-; CHECK-LABEL: @ifThen_vector_reduce_xor(
-; CHECK: %reduce = call i32 @llvm.vector.reduce.xor.v2i32(<2 x i32> %x)
-; CHECK-NEXT: br i1 true
define void @ifThen_vector_reduce_xor(<2 x i32> %x) {
+; CHECK-LABEL: define void @ifThen_vector_reduce_xor(
+; CHECK-SAME: <2 x i32> [[X:%.*]]) {
+; CHECK-NEXT: [[REDUCE:%.*]] = call i32 @llvm.vector.reduce.xor.v2i32(<2 x i32> [[X]])
+; CHECK-NEXT: br i1 true, label %[[A:.*]], label %[[B:.*]]
+; CHECK: [[A]]:
+; CHECK-NEXT: br label %[[B]]
+; CHECK: [[B]]:
+; CHECK-NEXT: ret void
+;
br i1 true, label %a, label %b
a:
@@ -223,10 +304,16 @@ b:
declare i32 @llvm.vector.reduce.xor.v2i32(<2 x i32>)
-; CHECK-LABEL: @ifThen_vector_reduce_smax(
-; CHECK: %reduce = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> %x)
-; CHECK-NEXT: br i1 true
define void @ifThen_vector_reduce_smax(<2 x i32> %x) {
+; CHECK-LABEL: define void @ifThen_vector_reduce_smax(
+; CHECK-SAME: <2 x i32> [[X:%.*]]) {
+; CHECK-NEXT: [[REDUCE:%.*]] = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> [[X]])
+; CHECK-NEXT: br i1 true, label %[[A:.*]], label %[[B:.*]]
+; CHECK: [[A]]:
+; CHECK-NEXT: br label %[[B]]
+; CHECK: [[B]]:
+; CHECK-NEXT: ret void
+;
br i1 true, label %a, label %b
a:
@@ -239,10 +326,16 @@ b:
declare i32 @llvm.vector.reduce.smax.v2i32(<2 x i32>)
-; CHECK-LABEL: @ifThen_vector_reduce_umax(
-; CHECK: %reduce = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> %x)
-; CHECK-NEXT: br i1 true
define void @ifThen_vector_reduce_umax(<2 x i32> %x) {
+; CHECK-LABEL: define void @ifThen_vector_reduce_umax(
+; CHECK-SAME: <2 x i32> [[X:%.*]]) {
+; CHECK-NEXT: [[REDUCE:%.*]] = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> [[X]])
+; CHECK-NEXT: br i1 true, label %[[A:.*]], label %[[B:.*]]
+; CHECK: [[A]]:
+; CHECK-NEXT: br label %[[B]]
+; CHECK: [[B]]:
+; CHECK-NEXT: ret void
+;
br i1 true, label %a, label %b
a:
@@ -255,10 +348,16 @@ b:
declare i32 @llvm.vector.reduce.umax.v2i32(<2 x i32>)
-; CHECK-LABEL: @ifThen_vector_reduce_umin(
-; CHECK: %reduce = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> %x)
-; CHECK-NEXT: br i1 true
define void @ifThen_vector_reduce_umin(<2 x i32> %x) {
+; CHECK-LABEL: define void @ifThen_vector_reduce_umin(
+; CHECK-SAME: <2 x i32> [[X:%.*]]) {
+; CHECK-NEXT: [[REDUCE:%.*]] = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> [[X]])
+; CHECK-NEXT: br i1 true, label %[[A:.*]], label %[[B:.*]]
+; CHECK: [[A]]:
+; CHECK-NEXT: br label %[[B]]
+; CHECK: [[B]]:
+; CHECK-NEXT: ret void
+;
br i1 true, label %a, label %b
a:
@@ -271,10 +370,16 @@ b:
declare i32 @llvm.vector.reduce.umin.v2i32(<2 x i32>)
-; CHECK-LABEL: @ifThen_vector_reduce_fmax(
-; CHECK: %reduce = call float @llvm.vector.reduce.fmax.v2f32(<2 x float> %x)
-; CHECK-NEXT: br i1 true
define void @ifThen_vector_reduce_fmax(<2 x float> %x) {
+; CHECK-LABEL: define void @ifThen_vector_reduce_fmax(
+; CHECK-SAME: <2 x float> [[X:%.*]]) {
+; CHECK-NEXT: [[REDUCE:%.*]] = call float @llvm.vector.reduce.fmax.v2f32(<2 x float> [[X]])
+; CHECK-NEXT: br i1 true, label %[[A:.*]], label %[[B:.*]]
+; CHECK: [[A]]:
+; CHECK-NEXT: br label %[[B]]
+; CHECK: [[B]]:
+; CHECK-NEXT: ret void
+;
br i1 true, label %a, label %b
a:
@@ -287,10 +392,16 @@ b:
declare float @llvm.vector.reduce.fmax.v2f32(<2 x float>)
-; CHECK-LABEL: @ifThen_vector_reduce_fmin(
-; CHECK: %reduce = call float @llvm.vector.reduce.fmin.v2f32(<2 x float> %x)
-; CHECK-NEXT: br i1 true
define void @ifThen_vector_reduce_fmin(<2 x float> %x) {
+; CHECK-LABEL: define void @ifThen_vector_reduce_fmin(
+; CHECK-SAME: <2 x float> [[X:%.*]]) {
+; CHECK-NEXT: [[REDUCE:%.*]] = call float @llvm.vector.reduce.fmin.v2f32(<2 x float> [[X]])
+; CHECK-NEXT: br i1 true, label %[[A:.*]], label %[[B:.*]]
+; CHECK: [[A]]:
+; CHECK-NEXT: br label %[[B]]
+; CHECK: [[B]]:
+; CHECK-NEXT: ret void
+;
br i1 true, label %a, label %b
a:
@@ -303,10 +414,16 @@ b:
declare float @llvm.vector.reduce.fmin.v2f32(<2 x float>)
-; CHECK-LABEL: @ifThen_ldexp(
-; CHECK: %ldexp = call float @llvm.ldexp.f32.i32(float %x, i32 %y)
-; CHECK-NEXT: br i1 true
define void @ifThen_ldexp(float %x, i32 %y) {
+; CHECK-LABEL: define void @ifThen_ldexp(
+; CHECK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) {
+; CHECK-NEXT: [[LDEXP:%.*]] = call float @llvm.ldexp.f32.i32(float [[X]], i32 [[Y]])
+; CHECK-NEXT: br i1 true, label %[[A:.*]], label %[[B:.*]]
+; CHECK: [[A]]:
+; CHECK-NEXT: br label %[[B]]
+; CHECK: [[B]]:
+; CHECK-NEXT: ret void
+;
br i1 true, label %a, label %b
a:
diff --git a/llvm/test/Transforms/VectorCombine/AArch64/shuffle-of-intrinsics.ll b/llvm/test/Transforms/VectorCombine/AArch64/shuffle-of-intrinsics.ll
index 78e9304ac81f2..144ebccfcda89 100644
--- a/llvm/test/Transforms/VectorCombine/AArch64/shuffle-of-intrinsics.ll
+++ b/llvm/test/Transforms/VectorCombine/AArch64/shuffle-of-intrinsics.ll
@@ -49,7 +49,7 @@ define <8 x i1> @test4(<4 x float> %0, <4 x float> %1) {
; CHECK-LABEL: @test4(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x float> [[TMP0:%.*]], <4 x float> [[TMP1:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
-; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i1> @llvm.is.fpclass.v8f32(<8 x float> [[TMP2]], i32 3)
+; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i1> @llvm.is.fpclass.v8f32(<8 x float> [[TMP2]], /* (nan) */ i32 3)
; CHECK-NEXT: ret <8 x i1> [[TMP3]]
;
entry:
@@ -63,7 +63,7 @@ define <2 x i1> @test4b(<4 x float> %0, <4 x float> %1) {
; CHECK-LABEL: @test4b(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x float> [[TMP0:%.*]], <4 x float> [[TMP1:%.*]], <2 x i32> <i32 0, i32 4>
-; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[TMP2]], i32 3)
+; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[TMP2]], /* (nan) */ i32 3)
; CHECK-NEXT: ret <2 x i1> [[TMP3]]
;
entry:
diff --git a/llvm/test/Transforms/VectorCombine/RISCV/shuffle-of-intrinsics.ll b/llvm/test/Transforms/VectorCombine/RISCV/shuffle-of-intrinsics.ll
index 9fb7ebd543fe5..baed7e4e09d91 100644
--- a/llvm/test/Transforms/VectorCombine/RISCV/shuffle-of-intrinsics.ll
+++ b/llvm/test/Transforms/VectorCombine/RISCV/shuffle-of-intrinsics.ll
@@ -49,7 +49,7 @@ define <8 x i1> @test4(<4 x float> %0, <4 x float> %1) {
; CHECK-LABEL: @test4(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x float> [[TMP0:%.*]], <4 x float> [[TMP1:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
-; CHECK-NEXT: [[TMP4:%.*]] = call <8 x i1> @llvm.is.fpclass.v8f32(<8 x float> [[TMP2]], i32 2)
+; CHECK-NEXT: [[TMP4:%.*]] = call <8 x i1> @llvm.is.fpclass.v8f32(<8 x float> [[TMP2]], /* (qnan) */ i32 2)
; CHECK-NEXT: ret <8 x i1> [[TMP4]]
;
entry:
diff --git a/llvm/test/Transforms/VectorCombine/X86/shuffle-of-intrinsics.ll b/llvm/test/Transforms/VectorCombine/X86/shuffle-of-intrinsics.ll
index 1f47db6370ac7..bebb95f6f5763 100644
--- a/llvm/test/Transforms/VectorCombine/X86/shuffle-of-intrinsics.ll
+++ b/llvm/test/Transforms/VectorCombine/X86/shuffle-of-intrinsics.ll
@@ -52,13 +52,13 @@ define <8 x i1> @test4(<4 x float> %0, <4 x float> %1) {
; SSE-LABEL: @test4(
; SSE-NEXT: entry:
; SSE-NEXT: [[TMP2:%.*]] = shufflevector <4 x float> [[TMP0:%.*]], <4 x float> [[TMP1:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
-; SSE-NEXT: [[TMP3:%.*]] = call <8 x i1> @llvm.is.fpclass.v8f32(<8 x float> [[TMP2]], i32 4)
+; SSE-NEXT: [[TMP3:%.*]] = call <8 x i1> @llvm.is.fpclass.v8f32(<8 x float> [[TMP2]], /* (ninf) */ i32 4)
; SSE-NEXT: ret <8 x i1> [[TMP3]]
;
; AVX-LABEL: @test4(
; AVX-NEXT: entry:
-; AVX-NEXT: [[TMP2:%.*]] = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> [[TMP0:%.*]], i32 4)
-; AVX-NEXT: [[TMP3:%.*]] = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> [[TMP1:%.*]], i32 4)
+; AVX-NEXT: [[TMP2:%.*]] = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> [[TMP0:%.*]], /* (ninf) */ i32 4)
+; AVX-NEXT: [[TMP3:%.*]] = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> [[TMP1:%.*]], /* (ninf) */ i32 4)
; AVX-NEXT: [[TMP4:%.*]] = shufflevector <4 x i1> [[TMP2]], <4 x i1> [[TMP3]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; AVX-NEXT: ret <8 x i1> [[TMP4]]
;
@@ -73,7 +73,7 @@ define <2 x i1> @test4b(<4 x float> %0, <4 x float> %1) {
; CHECK-LABEL: @test4b(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x float> [[TMP0:%.*]], <4 x float> [[TMP1:%.*]], <2 x i32> <i32 0, i32 4>
-; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[TMP2]], i32 4)
+; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[TMP2]], /* (ninf) */ i32 4)
; CHECK-NEXT: ret <2 x i1> [[TMP3]]
;
entry:
diff --git a/llvm/test/tools/llubi/intr_fp_is_fpclass.ll b/llvm/test/tools/llubi/intr_fp_is_fpclass.ll
index 32614a2bf65d8..5f56b9f74feaa 100644
--- a/llvm/test/tools/llubi/intr_fp_is_fpclass.ll
+++ b/llvm/test/tools/llubi/intr_fp_is_fpclass.ll
@@ -18,18 +18,18 @@ define void @main() {
ret void
}
; CHECK: Entering function: main
-; CHECK-NEXT: %is_snan = call i1 @llvm.is.fpclass.f32(float +snan(0x42), i32 1) => T
-; CHECK-NEXT: %is_qnan = call i1 @llvm.is.fpclass.f32(float +nan(0x42), i32 2) => T
-; CHECK-NEXT: %is_nan = call i1 @llvm.is.fpclass.f32(float -nan(0x42), i32 3) => T
-; CHECK-NEXT: %is_neg_inf = call i1 @llvm.is.fpclass.f32(float -inf, i32 4) => T
-; CHECK-NEXT: %is_neg_normal = call i1 @llvm.is.fpclass.f32(float -1.000000e+00, i32 8) => T
-; CHECK-NEXT: %is_neg_subnormal = call i1 @llvm.is.fpclass.f32(float -1.434930e-42, i32 16) => T
-; CHECK-NEXT: %is_neg_zero = call i1 @llvm.is.fpclass.f32(float -0.000000e+00, i32 32) => T
-; CHECK-NEXT: %is_pos_zero = call i1 @llvm.is.fpclass.f32(float 0.000000e+00, i32 64) => T
-; CHECK-NEXT: %is_pos_subnormal = call i1 @llvm.is.fpclass.f32(float 1.434930e-42, i32 128) => T
-; CHECK-NEXT: %is_pos_normal = call i1 @llvm.is.fpclass.f32(float 1.000000e+00, i32 256) => T
-; CHECK-NEXT: %is_pos_inf = call i1 @llvm.is.fpclass.f32(float +inf, i32 512) => T
-; CHECK-NEXT: %is_poison = call i1 @llvm.is.fpclass.f32(float poison, i32 256) => poison
-; CHECK-NEXT: %is_vec = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> <float +snan(0x42), float poison, float 1.000000e+00, float -0.000000e+00>, i32 291) => { T, poison, T, T }
+; CHECK-NEXT: %is_snan = call i1 @llvm.is.fpclass.f32(float +snan(0x42), /* (snan) */ i32 1) => T
+; CHECK-NEXT: %is_qnan = call i1 @llvm.is.fpclass.f32(float +nan(0x42), /* (qnan) */ i32 2) => T
+; CHECK-NEXT: %is_nan = call i1 @llvm.is.fpclass.f32(float -nan(0x42), /* (nan) */ i32 3) => T
+; CHECK-NEXT: %is_neg_inf = call i1 @llvm.is.fpclass.f32(float -inf, /* (ninf) */ i32 4) => T
+; CHECK-NEXT: %is_neg_normal = call i1 @llvm.is.fpclass.f32(float -1.000000e+00, /* (nnorm) */ i32 8) => T
+; CHECK-NEXT: %is_neg_subnormal = call i1 @llvm.is.fpclass.f32(float -1.434930e-42, /* (nsub) */ i32 16) => T
+; CHECK-NEXT: %is_neg_zero = call i1 @llvm.is.fpclass.f32(float -0.000000e+00, /* (nzero) */ i32 32) => T
+; CHECK-NEXT: %is_pos_zero = call i1 @llvm.is.fpclass.f32(float 0.000000e+00, /* (pzero) */ i32 64) => T
+; CHECK-NEXT: %is_pos_subnormal = call i1 @llvm.is.fpclass.f32(float 1.434930e-42, /* (psub) */ i32 128) => T
+; CHECK-NEXT: %is_pos_normal = call i1 @llvm.is.fpclass.f32(float 1.000000e+00, /* (pnorm) */ i32 256) => T
+; CHECK-NEXT: %is_pos_inf = call i1 @llvm.is.fpclass.f32(float +inf, /* (pinf) */ i32 512) => T
+; CHECK-NEXT: %is_poison = call i1 @llvm.is.fpclass.f32(float poison, /* (pnorm) */ i32 256) => poison
+; CHECK-NEXT: %is_vec = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> <float +snan(0x42), float poison, float 1.000000e+00, float -0.000000e+00>, /* (nan nzero pnorm) */ i32 291) => { T, poison, T, T }
; CHECK-NEXT: ret void
; CHECK-NEXT: Exiting function: main
diff --git a/llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp b/llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp
index 330de1063d666..23086c422ec1c 100644
--- a/llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp
+++ b/llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp
@@ -912,7 +912,8 @@ void Intrinsic::printImmArg(ID IID, unsigned ArgIdx, raw_ostream &OS, const Cons
OS << " switch (ArgIdx) {\n";
for (const auto [ArgIdx, ArgName, FuncName] : Int.PrettyPrintFunctions) {
OS << " case " << ArgIdx << ":\n";
- OS << " OS << \"" << ArgName << "=\";\n";
+ if (!ArgName.empty())
+ OS << " OS << \"" << ArgName << "=\";\n";
if (!FuncName.empty()) {
OS << " ";
if (!Int.TargetPrefix.empty())
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