[clang] [llvm] [RISCV] Add support for vector registers with -fzero-call-used-regs (PR #206206)

[Lucas Chollet via cfe-commits]

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@@ -0,0 +1,154 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv64-unknown-unknown -mattr="+i,+m,+v" | FileCheck %s  --check-prefixes=CHECK
+
+define void @all() "zero-call-used-regs"="all" {
+; CHECK-LABEL: all:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli t0, zero, e32, m1, tu, mu
+; CHECK-NEXT:    vmv.v.i v0, 0
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LucasChollet wrote:

I will try to give it a shot, but I prefer to do it in a follow-up.

https://github.com/llvm/llvm-project/pull/206206