[clang] [llvm] [AMDGPU] Remove icmp and fcmp intrinsics and builtins (PR #208183)
Jay Foad via cfe-commits
cfe-commits at lists.llvm.org
Fri Jul 10 05:49:19 PDT 2026
https://github.com/jayfoad updated https://github.com/llvm/llvm-project/pull/208183
>From 45020d29081297fc64a751392404dc9df7f156b4 Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Wed, 8 Jul 2026 10:06:21 +0100
Subject: [PATCH 1/2] [AMDGPU] Remove icmp and fcmp intrinsics and builtins
Remove these intrinsics in favour of llvm.amdgcn.ballot:
llvm.amdgcn.icmp
llvm.amdgcn.fcmp
Remove these builtins in favour of __builtin_amdgcn_ballot_w32 or
__builtin_amdgcn_ballot_w64:
__builtin_amdgcn_uicmp
__builtin_amdgcn_uicmpl
__builtin_amdgcn_sicmp
__builtin_amdgcn_sicmpl
__builtin_amdgcn_fcmp
__builtin_amdgcn_fcmpf
---
clang/include/clang/Basic/BuiltinsAMDGPU.td | 8 -
clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp | 16 -
clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp | 24 -
clang/test/CodeGenCUDA/builtins-amdgcn.cu | 28 -
.../test/CodeGenCUDA/builtins-spirv-amdgcn.cu | 49 -
clang/test/CodeGenOpenCL/builtins-amdgcn.cl | 42 -
.../test/SemaOpenCL/builtins-amdgcn-error.cl | 30 -
llvm/docs/ReleaseNotes.md | 10 +
llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 10 -
.../AMDGPU/AMDGPUInstCombineIntrinsic.cpp | 135 -
.../AMDGPU/AMDGPUInstructionSelector.cpp | 62 -
.../Target/AMDGPU/AMDGPUInstructionSelector.h | 1 -
.../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 25 -
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 20 -
.../Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 10 -
.../Target/AMDGPU/AMDGPUSearchableTables.td | 2 -
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 74 -
llvm/lib/Target/AMDGPU/SIInstructions.td | 12 -
.../AMDGPU/MIR/always-uniform-gmir.mir | 43 -
.../AMDGPU/always_uniform.ll | 16 -
.../AMDGPU/irreducible/irreducible-2.ll | 29 -
.../inst-select-amdgcn.fcmp.constants.w32.mir | 171 -
.../inst-select-amdgcn.fcmp.constants.w64.mir | 171 -
.../GlobalISel/regbankselect-amdgcn.fcmp.mir | 78 -
.../GlobalISel/regbankselect-amdgcn.icmp.mir | 78 -
.../CodeGen/AMDGPU/bitcast-vector-extract.ll | 21 -
llvm/test/CodeGen/AMDGPU/lds-relocs.ll | 4 -
.../CodeGen/AMDGPU/llvm.amdgcn.ballot.i32.ll | 126 -
.../CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.ll | 112 -
.../CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll | 2456 --------------
.../CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll | 2903 -----------------
.../CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll | 1717 ----------
.../CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll | 2072 ------------
llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll | 45 -
.../CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.ll | 89 +-
llvm/test/CodeGen/AMDGPU/wave32.ll | 780 +----
.../InstCombine/AMDGPU/amdgcn-intrinsics.ll | 756 -----
llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll | 19 -
38 files changed, 38 insertions(+), 12206 deletions(-)
delete mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w32.mir
delete mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w64.mir
delete mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir
delete mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir
delete mode 100644 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
delete mode 100644 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
delete mode 100644 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
delete mode 100644 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
diff --git a/clang/include/clang/Basic/BuiltinsAMDGPU.td b/clang/include/clang/Basic/BuiltinsAMDGPU.td
index 306af993fd869..6e364490dbe4c 100644
--- a/clang/include/clang/Basic/BuiltinsAMDGPU.td
+++ b/clang/include/clang/Basic/BuiltinsAMDGPU.td
@@ -313,14 +313,6 @@ def __builtin_amdgcn_ballot_w64 : AMDGPUBuiltin<"uint64_t(bool)", [Const]>;
def __builtin_amdgcn_inverse_ballot_w32 : AMDGPUBuiltin<"bool(uint32_t)", [Const], "wavefrontsize32">;
def __builtin_amdgcn_inverse_ballot_w64 : AMDGPUBuiltin<"bool(uint64_t)", [Const], "wavefrontsize64">;
-// Deprecated intrinsics in favor of __builtin_amdgn_ballot_{w32|w64}
-def __builtin_amdgcn_uicmp : AMDGPUBuiltin<"uint64_t(unsigned int, unsigned int, _Constant int)", [Const]>;
-def __builtin_amdgcn_uicmpl : AMDGPUBuiltin<"uint64_t(uint64_t, uint64_t, _Constant int)", [Const]>;
-def __builtin_amdgcn_sicmp : AMDGPUBuiltin<"uint64_t(int, int, _Constant int)", [Const]>;
-def __builtin_amdgcn_sicmpl : AMDGPUBuiltin<"uint64_t(int64_t, int64_t, _Constant int)", [Const]>;
-def __builtin_amdgcn_fcmp : AMDGPUBuiltin<"uint64_t(double, double, _Constant int)", [Const]>;
-def __builtin_amdgcn_fcmpf : AMDGPUBuiltin<"uint64_t(float, float, _Constant int)", [Const]>;
-
//===----------------------------------------------------------------------===//
// Flat addressing builtins.
//===----------------------------------------------------------------------===//
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
index 0a7ba0c194400..38a2797c6a1a4 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
@@ -391,22 +391,6 @@ CIRGenFunction::emitAMDGPUBuiltinExpr(unsigned builtinId,
getContext().BuiltinInfo.getName(builtinId));
return mlir::Value{};
}
- case AMDGPU::BI__builtin_amdgcn_uicmp:
- case AMDGPU::BI__builtin_amdgcn_uicmpl:
- case AMDGPU::BI__builtin_amdgcn_sicmp:
- case AMDGPU::BI__builtin_amdgcn_sicmpl: {
- cgm.errorNYI(expr->getSourceRange(),
- std::string("unimplemented AMDGPU builtin call: ") +
- getContext().BuiltinInfo.getName(builtinId));
- return mlir::Value{};
- }
- case AMDGPU::BI__builtin_amdgcn_fcmp:
- case AMDGPU::BI__builtin_amdgcn_fcmpf: {
- cgm.errorNYI(expr->getSourceRange(),
- std::string("unimplemented AMDGPU builtin call: ") +
- getContext().BuiltinInfo.getName(builtinId));
- return mlir::Value{};
- }
case AMDGPU::BI__builtin_amdgcn_class:
case AMDGPU::BI__builtin_amdgcn_classf:
case AMDGPU::BI__builtin_amdgcn_classh: {
diff --git a/clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp b/clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
index 6a17f4c55f80d..19f36ec55c616 100644
--- a/clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
@@ -772,30 +772,6 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID,
case AMDGPU::BI__builtin_amdgcn_tanh_bf16:
return emitBuiltinWithOneOverloadedType<1>(*this, E,
Intrinsic::amdgcn_tanh);
- case AMDGPU::BI__builtin_amdgcn_uicmp:
- case AMDGPU::BI__builtin_amdgcn_uicmpl:
- case AMDGPU::BI__builtin_amdgcn_sicmp:
- case AMDGPU::BI__builtin_amdgcn_sicmpl: {
- llvm::Value *Src0 = EmitScalarExpr(E->getArg(0));
- llvm::Value *Src1 = EmitScalarExpr(E->getArg(1));
- llvm::Value *Src2 = EmitScalarExpr(E->getArg(2));
-
- // FIXME-GFX10: How should 32 bit mask be handled?
- Function *F = CGM.getIntrinsic(Intrinsic::amdgcn_icmp,
- { Builder.getInt64Ty(), Src0->getType() });
- return Builder.CreateCall(F, { Src0, Src1, Src2 });
- }
- case AMDGPU::BI__builtin_amdgcn_fcmp:
- case AMDGPU::BI__builtin_amdgcn_fcmpf: {
- llvm::Value *Src0 = EmitScalarExpr(E->getArg(0));
- llvm::Value *Src1 = EmitScalarExpr(E->getArg(1));
- llvm::Value *Src2 = EmitScalarExpr(E->getArg(2));
-
- // FIXME-GFX10: How should 32 bit mask be handled?
- Function *F = CGM.getIntrinsic(Intrinsic::amdgcn_fcmp,
- { Builder.getInt64Ty(), Src0->getType() });
- return Builder.CreateCall(F, { Src0, Src1, Src2 });
- }
case AMDGPU::BI__builtin_amdgcn_class:
case AMDGPU::BI__builtin_amdgcn_classf:
case AMDGPU::BI__builtin_amdgcn_classh:
diff --git a/clang/test/CodeGenCUDA/builtins-amdgcn.cu b/clang/test/CodeGenCUDA/builtins-amdgcn.cu
index 35673773ec80c..9ad115d999b1c 100644
--- a/clang/test/CodeGenCUDA/builtins-amdgcn.cu
+++ b/clang/test/CodeGenCUDA/builtins-amdgcn.cu
@@ -164,34 +164,6 @@ __global__ void endpgm() {
__builtin_amdgcn_endpgm();
}
-// Check the 64 bit argument is correctly passed to the intrinsic without truncation or assertion.
-
-// CHECK-LABEL: @_Z14test_uicmp_i64Pyyy(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[OUT:%.*]] = alloca ptr, align 8, addrspace(5)
-// CHECK-NEXT: [[OUT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
-// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8, addrspace(5)
-// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8, addrspace(5)
-// CHECK-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT_ADDR]] to ptr
-// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr
-// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr
-// CHECK-NEXT: store ptr addrspace(1) [[OUT_COERCE:%.*]], ptr addrspace(5) [[OUT]], align 8
-// CHECK-NEXT: [[OUT1:%.*]] = load ptr, ptr addrspace(5) [[OUT]], align 8
-// CHECK-NEXT: store ptr [[OUT1]], ptr [[OUT_ADDR_ASCAST]], align 8
-// CHECK-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR_ASCAST]], align 8
-// CHECK-NEXT: store i64 [[B:%.*]], ptr [[B_ADDR_ASCAST]], align 8
-// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR_ASCAST]], align 8
-// CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[B_ADDR_ASCAST]], align 8
-// CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i64(i64 [[TMP0]], i64 [[TMP1]], i32 35)
-// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[OUT_ADDR_ASCAST]], align 8
-// CHECK-NEXT: store i64 [[TMP2]], ptr [[TMP3]], align 8
-// CHECK-NEXT: ret void
-//
-__global__ void test_uicmp_i64(unsigned long long *out, unsigned long long a, unsigned long long b)
-{
- *out = __builtin_amdgcn_uicmpl(a, b, 30+5);
-}
-
// Check the 64 bit return value is correctly returned without truncation or assertion.
// CHECK-LABEL: @_Z14test_s_memtimePy(
diff --git a/clang/test/CodeGenCUDA/builtins-spirv-amdgcn.cu b/clang/test/CodeGenCUDA/builtins-spirv-amdgcn.cu
index 94338f9027db1..1f6a8cda42c9d 100644
--- a/clang/test/CodeGenCUDA/builtins-spirv-amdgcn.cu
+++ b/clang/test/CodeGenCUDA/builtins-spirv-amdgcn.cu
@@ -257,55 +257,6 @@ __global__ void endpgm() {
__builtin_amdgcn_endpgm();
}
-// Check the 64 bit argument is correctly passed to the intrinsic without truncation or assertion.
-
-// CHECK-LABEL: @_Z14test_uicmp_i64Pyyy(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[OUT:%.*]] = alloca ptr addrspace(4), align 8
-// CHECK-NEXT: [[OUT_ADDR:%.*]] = alloca ptr addrspace(4), align 8
-// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
-// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
-// CHECK-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr [[OUT_ADDR]] to ptr addrspace(4)
-// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr [[A_ADDR]] to ptr addrspace(4)
-// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr [[B_ADDR]] to ptr addrspace(4)
-// CHECK-NEXT: store ptr addrspace(1) [[OUT_COERCE:%.*]], ptr [[OUT]], align 8
-// CHECK-NEXT: [[OUT1:%.*]] = load ptr addrspace(4), ptr [[OUT]], align 8
-// CHECK-NEXT: store ptr addrspace(4) [[OUT1]], ptr addrspace(4) [[OUT_ADDR_ASCAST]], align 8
-// CHECK-NEXT: store i64 [[A:%.*]], ptr addrspace(4) [[A_ADDR_ASCAST]], align 8
-// CHECK-NEXT: store i64 [[B:%.*]], ptr addrspace(4) [[B_ADDR_ASCAST]], align 8
-// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr addrspace(4) [[A_ADDR_ASCAST]], align 8
-// CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr addrspace(4) [[B_ADDR_ASCAST]], align 8
-// CHECK-NEXT: [[TMP2:%.*]] = call addrspace(4) i64 @llvm.amdgcn.icmp.i64.i64(i64 [[TMP0]], i64 [[TMP1]], i32 35)
-// CHECK-NEXT: [[TMP3:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[OUT_ADDR_ASCAST]], align 8
-// CHECK-NEXT: store i64 [[TMP2]], ptr addrspace(4) [[TMP3]], align 8
-// CHECK-NEXT: ret void
-//
-// AMDGCNSPIRV-LABEL: @_Z14test_uicmp_i64Pyyy(
-// AMDGCNSPIRV-NEXT: entry:
-// AMDGCNSPIRV-NEXT: [[OUT:%.*]] = alloca ptr addrspace(4), align 8
-// AMDGCNSPIRV-NEXT: [[OUT_ADDR:%.*]] = alloca ptr addrspace(4), align 8
-// AMDGCNSPIRV-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
-// AMDGCNSPIRV-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
-// AMDGCNSPIRV-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr [[OUT_ADDR]] to ptr addrspace(4)
-// AMDGCNSPIRV-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr [[A_ADDR]] to ptr addrspace(4)
-// AMDGCNSPIRV-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr [[B_ADDR]] to ptr addrspace(4)
-// AMDGCNSPIRV-NEXT: store ptr addrspace(1) [[OUT_COERCE:%.*]], ptr [[OUT]], align 8
-// AMDGCNSPIRV-NEXT: [[OUT1:%.*]] = load ptr addrspace(4), ptr [[OUT]], align 8
-// AMDGCNSPIRV-NEXT: store ptr addrspace(4) [[OUT1]], ptr addrspace(4) [[OUT_ADDR_ASCAST]], align 8
-// AMDGCNSPIRV-NEXT: store i64 [[A:%.*]], ptr addrspace(4) [[A_ADDR_ASCAST]], align 8
-// AMDGCNSPIRV-NEXT: store i64 [[B:%.*]], ptr addrspace(4) [[B_ADDR_ASCAST]], align 8
-// AMDGCNSPIRV-NEXT: [[TMP0:%.*]] = load i64, ptr addrspace(4) [[A_ADDR_ASCAST]], align 8
-// AMDGCNSPIRV-NEXT: [[TMP1:%.*]] = load i64, ptr addrspace(4) [[B_ADDR_ASCAST]], align 8
-// AMDGCNSPIRV-NEXT: [[TMP2:%.*]] = call addrspace(4) i64 @llvm.amdgcn.icmp.i64.i64(i64 [[TMP0]], i64 [[TMP1]], i32 35)
-// AMDGCNSPIRV-NEXT: [[TMP3:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[OUT_ADDR_ASCAST]], align 8
-// AMDGCNSPIRV-NEXT: store i64 [[TMP2]], ptr addrspace(4) [[TMP3]], align 8
-// AMDGCNSPIRV-NEXT: ret void
-//
-__global__ void test_uicmp_i64(unsigned long long *out, unsigned long long a, unsigned long long b)
-{
- *out = __builtin_amdgcn_uicmpl(a, b, 30+5);
-}
-
// Check the 64 bit return value is correctly returned without truncation or assertion.
// CHECK-LABEL: @_Z14test_s_memtimePy(
diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn.cl
index 11fbfdde92fa1..84ebc14f42766 100644
--- a/clang/test/CodeGenOpenCL/builtins-amdgcn.cl
+++ b/clang/test/CodeGenOpenCL/builtins-amdgcn.cl
@@ -251,34 +251,6 @@ void test_fract_f64(global int* out, double a)
*out = __builtin_amdgcn_fract(a);
}
-// CHECK-LABEL: @test_sicmp_i32
-// CHECK: {{.*}}call{{.*}} i64 @llvm.amdgcn.icmp.i64.i32(i32 %a, i32 %b, i32 32)
-void test_sicmp_i32(global ulong* out, int a, int b)
-{
- *out = __builtin_amdgcn_sicmp(a, b, 32);
-}
-
-// CHECK-LABEL: @test_uicmp_i32
-// CHECK: {{.*}}call{{.*}} i64 @llvm.amdgcn.icmp.i64.i32(i32 %a, i32 %b, i32 32)
-void test_uicmp_i32(global ulong* out, uint a, uint b)
-{
- *out = __builtin_amdgcn_uicmp(a, b, 32);
-}
-
-// CHECK-LABEL: @test_sicmp_i64
-// CHECK: {{.*}}call{{.*}} i64 @llvm.amdgcn.icmp.i64.i64(i64 %a, i64 %b, i32 38)
-void test_sicmp_i64(global ulong* out, long a, long b)
-{
- *out = __builtin_amdgcn_sicmpl(a, b, 39-1);
-}
-
-// CHECK-LABEL: @test_uicmp_i64
-// CHECK: {{.*}}call{{.*}} i64 @llvm.amdgcn.icmp.i64.i64(i64 %a, i64 %b, i32 35)
-void test_uicmp_i64(global ulong* out, ulong a, ulong b)
-{
- *out = __builtin_amdgcn_uicmpl(a, b, 30+5);
-}
-
// CHECK-LABEL: @test_ds_swizzle
// CHECK: {{.*}}call{{.*}} i32 @llvm.amdgcn.ds.swizzle(i32 %a, i32 32)
void test_ds_swizzle(global int* out, int a)
@@ -321,20 +293,6 @@ void test_wave_shuffle(global int* out, int a, int b)
*out = __builtin_amdgcn_wave_shuffle(a, b);
}
-// CHECK-LABEL: @test_fcmp_f32
-// CHECK: {{.*}}call{{.*}} i64 @llvm.amdgcn.fcmp.i64.f32(float %a, float %b, i32 5)
-void test_fcmp_f32(global ulong* out, float a, float b)
-{
- *out = __builtin_amdgcn_fcmpf(a, b, 5);
-}
-
-// CHECK-LABEL: @test_fcmp_f64
-// CHECK: {{.*}}call{{.*}} i64 @llvm.amdgcn.fcmp.i64.f64(double %a, double %b, i32 6)
-void test_fcmp_f64(global ulong* out, double a, double b)
-{
- *out = __builtin_amdgcn_fcmp(a, b, 3+3);
-}
-
// CHECK-LABEL: @test_class_f32
// CHECK: {{.*}}call{{.*}} i1 @llvm.amdgcn.class.f32
void test_class_f32(global float* out, float a, int b)
diff --git a/clang/test/SemaOpenCL/builtins-amdgcn-error.cl b/clang/test/SemaOpenCL/builtins-amdgcn-error.cl
index eb1a86bdcdeb0..a19d7ec85b1ee 100644
--- a/clang/test/SemaOpenCL/builtins-amdgcn-error.cl
+++ b/clang/test/SemaOpenCL/builtins-amdgcn-error.cl
@@ -77,36 +77,6 @@ void test_iglp_opt(int x)
__builtin_amdgcn_iglp_opt(x); // expected-error {{argument to '__builtin_amdgcn_iglp_opt' must be a constant integer}}
}
-void test_sicmp_i32(global ulong* out, int a, int b, uint c)
-{
- *out = __builtin_amdgcn_sicmp(a, b, c); // expected-error {{argument to '__builtin_amdgcn_sicmp' must be a constant integer}}
-}
-
-void test_uicmp_i32(global ulong* out, uint a, uint b, uint c)
-{
- *out = __builtin_amdgcn_uicmp(a, b, c); // expected-error {{argument to '__builtin_amdgcn_uicmp' must be a constant integer}}
-}
-
-void test_sicmp_i64(global ulong* out, long a, long b, uint c)
-{
- *out = __builtin_amdgcn_sicmpl(a, b, c); // expected-error {{argument to '__builtin_amdgcn_sicmpl' must be a constant integer}}
-}
-
-void test_uicmp_i64(global ulong* out, ulong a, ulong b, uint c)
-{
- *out = __builtin_amdgcn_uicmpl(a, b, c); // expected-error {{argument to '__builtin_amdgcn_uicmpl' must be a constant integer}}
-}
-
-void test_fcmp_f32(global ulong* out, float a, float b, uint c)
-{
- *out = __builtin_amdgcn_fcmpf(a, b, c); // expected-error {{argument to '__builtin_amdgcn_fcmpf' must be a constant integer}}
-}
-
-void test_fcmp_f64(global ulong* out, double a, double b, uint c)
-{
- *out = __builtin_amdgcn_fcmp(a, b, c); // expected-error {{argument to '__builtin_amdgcn_fcmp' must be a constant integer}}
-}
-
void test_ds_swizzle(global int* out, int a, int b)
{
*out = __builtin_amdgcn_ds_swizzle(a, b); // expected-error {{argument to '__builtin_amdgcn_ds_swizzle' must be a constant integer}}
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 3ca9f5166ad95..58f7062f89130 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -218,6 +218,16 @@ Makes programs 10x faster by doing Special New Thing.
previously relied on the subtarget feature to enable misaligned buffer merging
must now set the corresponding module flag to `1` (relaxed). An absent flag is
treated as strict by the backend.
+* These intrinsics have been removed in favour of `llvm.amdgcn.ballot`:
+ * `llvm.amdgcn.icmp`
+ * `llvm.amdgcn.fcmp`
+* The corresponding builtins have been removed in favour of
+ `__builtin_amdgcn_ballot_w32` or `__builtin_amdgcn_ballot_w64`:
+ * `__builtin_amdgcn_uicmp`
+ * `__builtin_amdgcn_uicmpl`
+ * `__builtin_amdgcn_sicmpl`
+ * `__builtin_amdgcn_fcmp`
+ * `__builtin_amdgcn_fcmpf`
### Changes to the ARM Backend
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index 21882e247c027..c02d485cc9273 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -2449,16 +2449,6 @@ def int_amdgcn_cvt_pk_u8_f32 :
ClangBuiltin<"__builtin_amdgcn_cvt_pk_u8_f32">,
PureIntrinsic<[llvm_i32_ty], [llvm_float_ty, llvm_i32_ty, llvm_i32_ty]>;
-def int_amdgcn_icmp :
- Intrinsic<[llvm_anyint_ty], [llvm_anyint_ty, LLVMMatchType<1>, llvm_i32_ty],
- [IntrNoMem, IntrConvergent,
- ImmArg<ArgIndex<2>>, IntrWillReturn, IntrNoCallback, IntrNoFree]>;
-
-def int_amdgcn_fcmp :
- Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, LLVMMatchType<1>, llvm_i32_ty],
- [IntrNoMem, IntrConvergent,
- ImmArg<ArgIndex<2>>, IntrWillReturn, IntrNoCallback, IntrNoFree]>;
-
// Returns a bitfield(i32 or i64) containing the result of its i1 argument
// in all active lanes, and zero in all inactive lanes.
def int_amdgcn_ballot :
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
index f5d8e43dce9db..eb4efac76fd11 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
@@ -1661,141 +1661,6 @@ GCNTTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const {
break;
}
- case Intrinsic::amdgcn_icmp:
- case Intrinsic::amdgcn_fcmp: {
- const ConstantInt *CC = cast<ConstantInt>(II.getArgOperand(2));
- // Guard against invalid arguments.
- int64_t CCVal = CC->getZExtValue();
- bool IsInteger = IID == Intrinsic::amdgcn_icmp;
- if ((IsInteger && (CCVal < CmpInst::FIRST_ICMP_PREDICATE ||
- CCVal > CmpInst::LAST_ICMP_PREDICATE)) ||
- (!IsInteger && (CCVal < CmpInst::FIRST_FCMP_PREDICATE ||
- CCVal > CmpInst::LAST_FCMP_PREDICATE)))
- break;
-
- Value *Src0 = II.getArgOperand(0);
- Value *Src1 = II.getArgOperand(1);
-
- if (auto *CSrc0 = dyn_cast<Constant>(Src0)) {
- if (auto *CSrc1 = dyn_cast<Constant>(Src1)) {
- Constant *CCmp = ConstantFoldCompareInstOperands(
- (ICmpInst::Predicate)CCVal, CSrc0, CSrc1, DL);
- if (CCmp && CCmp->isNullValue()) {
- return IC.replaceInstUsesWith(
- II, IC.Builder.CreateSExt(CCmp, II.getType()));
- }
-
- // The result of V_ICMP/V_FCMP assembly instructions (which this
- // intrinsic exposes) is one bit per thread, masked with the EXEC
- // register (which contains the bitmask of live threads). So a
- // comparison that always returns true is the same as a read of the
- // EXEC register. ballot(true) reads EXEC at the wave-size width, so
- // zext/trunc the result to the intrinsic's return type.
- Type *WaveTy = IC.Builder.getIntNTy(ST->getWavefrontSize());
- Value *Ballot = IC.Builder.CreateIntrinsic(
- Intrinsic::amdgcn_ballot, WaveTy, IC.Builder.getTrue());
- Value *Result = IC.Builder.CreateZExtOrTrunc(Ballot, II.getType());
- return IC.replaceInstUsesWith(II, Result);
- }
-
- // Canonicalize constants to RHS.
- CmpInst::Predicate SwapPred =
- CmpInst::getSwappedPredicate(static_cast<CmpInst::Predicate>(CCVal));
- II.setArgOperand(0, Src1);
- II.setArgOperand(1, Src0);
- II.setArgOperand(
- 2, ConstantInt::get(CC->getType(), static_cast<int>(SwapPred)));
- return &II;
- }
-
- if (CCVal != CmpInst::ICMP_EQ && CCVal != CmpInst::ICMP_NE)
- break;
-
- // Canonicalize compare eq with true value to compare != 0
- // llvm.amdgcn.icmp(zext (i1 x), 1, eq)
- // -> llvm.amdgcn.icmp(zext (i1 x), 0, ne)
- // llvm.amdgcn.icmp(sext (i1 x), -1, eq)
- // -> llvm.amdgcn.icmp(sext (i1 x), 0, ne)
- Value *ExtSrc;
- if (CCVal == CmpInst::ICMP_EQ &&
- ((match(Src1, PatternMatch::m_One()) &&
- match(Src0, m_ZExt(PatternMatch::m_Value(ExtSrc)))) ||
- (match(Src1, PatternMatch::m_AllOnes()) &&
- match(Src0, m_SExt(PatternMatch::m_Value(ExtSrc))))) &&
- ExtSrc->getType()->isIntegerTy(1)) {
- IC.replaceOperand(II, 1, ConstantInt::getNullValue(Src1->getType()));
- IC.replaceOperand(II, 2,
- ConstantInt::get(CC->getType(), CmpInst::ICMP_NE));
- return &II;
- }
-
- CmpPredicate SrcPred;
- Value *SrcLHS;
- Value *SrcRHS;
-
- // Fold compare eq/ne with 0 from a compare result as the predicate to the
- // intrinsic. The typical use is a wave vote function in the library, which
- // will be fed from a user code condition compared with 0. Fold in the
- // redundant compare.
-
- // llvm.amdgcn.icmp([sz]ext ([if]cmp pred a, b), 0, ne)
- // -> llvm.amdgcn.[if]cmp(a, b, pred)
- //
- // llvm.amdgcn.icmp([sz]ext ([if]cmp pred a, b), 0, eq)
- // -> llvm.amdgcn.[if]cmp(a, b, inv pred)
- if (match(Src1, PatternMatch::m_Zero()) &&
- match(Src0, PatternMatch::m_ZExtOrSExt(
- m_Cmp(SrcPred, PatternMatch::m_Value(SrcLHS),
- PatternMatch::m_Value(SrcRHS))))) {
- if (CCVal == CmpInst::ICMP_EQ)
- SrcPred = CmpInst::getInversePredicate(SrcPred);
-
- Intrinsic::ID NewIID = CmpInst::isFPPredicate(SrcPred)
- ? Intrinsic::amdgcn_fcmp
- : Intrinsic::amdgcn_icmp;
-
- Type *Ty = SrcLHS->getType();
- if (auto *CmpType = dyn_cast<IntegerType>(Ty)) {
- // Promote to next legal integer type.
- unsigned Width = CmpType->getBitWidth();
- unsigned NewWidth = Width;
-
- // Don't do anything for i1 comparisons.
- if (Width == 1)
- break;
-
- if (Width <= 16)
- NewWidth = 16;
- else if (Width <= 32)
- NewWidth = 32;
- else if (Width <= 64)
- NewWidth = 64;
- else
- break; // Can't handle this.
-
- if (Width != NewWidth) {
- IntegerType *CmpTy = IC.Builder.getIntNTy(NewWidth);
- if (CmpInst::isSigned(SrcPred)) {
- SrcLHS = IC.Builder.CreateSExt(SrcLHS, CmpTy);
- SrcRHS = IC.Builder.CreateSExt(SrcRHS, CmpTy);
- } else {
- SrcLHS = IC.Builder.CreateZExt(SrcLHS, CmpTy);
- SrcRHS = IC.Builder.CreateZExt(SrcRHS, CmpTy);
- }
- }
- } else if (!Ty->isFloatTy() && !Ty->isDoubleTy() && !Ty->isHalfTy())
- break;
-
- Value *Args[] = {SrcLHS, SrcRHS,
- ConstantInt::get(CC->getType(), SrcPred)};
- Value *NewCall = IC.Builder.CreateIntrinsic(
- NewIID, {II.getType(), SrcLHS->getType()}, Args);
- NewCall->takeName(&II);
- return IC.replaceInstUsesWith(II, NewCall);
- }
-
- break;
- }
case Intrinsic::amdgcn_mbcnt_hi:
// exec_hi is all 0, so this is just a copy.
if (ST->isWave32())
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index c85d7124f62bb..871c9af5d1161 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -1236,11 +1236,6 @@ bool AMDGPUInstructionSelector::selectG_INTRINSIC(MachineInstr &I) const {
return selectWritelane(I);
case Intrinsic::amdgcn_div_scale:
return selectDivScale(I);
- case Intrinsic::amdgcn_icmp:
- case Intrinsic::amdgcn_fcmp:
- if (selectImpl(I, *CoverageInfo))
- return true;
- return selectIntrinsicCmp(I);
case Intrinsic::amdgcn_ballot:
return selectBallot(I);
case Intrinsic::amdgcn_reloc_constant:
@@ -1619,63 +1614,6 @@ bool AMDGPUInstructionSelector::selectG_ICMP_or_FCMP(MachineInstr &I) const {
return true;
}
-bool AMDGPUInstructionSelector::selectIntrinsicCmp(MachineInstr &I) const {
- Register Dst = I.getOperand(0).getReg();
- if (isVCC(Dst, *MRI))
- return false;
-
- LLT DstTy = MRI->getType(Dst);
- if (DstTy.getSizeInBits() != STI.getWavefrontSize())
- return false;
-
- MachineBasicBlock *BB = I.getParent();
- const DebugLoc &DL = I.getDebugLoc();
- Register SrcReg = I.getOperand(2).getReg();
- unsigned Size = RBI.getSizeInBits(SrcReg, *MRI, TRI);
-
- // i1 inputs are not supported in GlobalISel.
- if (Size == 1)
- return false;
-
- auto Pred = static_cast<CmpInst::Predicate>(I.getOperand(4).getImm());
- if (!CmpInst::isIntPredicate(Pred) && !CmpInst::isFPPredicate(Pred)) {
- BuildMI(*BB, &I, DL, TII.get(AMDGPU::IMPLICIT_DEF), Dst);
- I.eraseFromParent();
- return RBI.constrainGenericRegister(Dst, *TRI.getBoolRC(), *MRI);
- }
-
- const int Opcode = getV_CMPOpcode(Pred, Size, *Subtarget);
- if (Opcode == -1)
- return false;
-
- MachineInstrBuilder SelectedMI;
- MachineOperand &LHS = I.getOperand(2);
- MachineOperand &RHS = I.getOperand(3);
- auto [Src0, Src0Mods] = selectVOP3ModsImpl(LHS.getReg());
- auto [Src1, Src1Mods] = selectVOP3ModsImpl(RHS.getReg());
- Register Src0Reg =
- copyToVGPRIfSrcFolded(Src0, Src0Mods, LHS, &I, /*ForceVGPR*/ true);
- Register Src1Reg =
- copyToVGPRIfSrcFolded(Src1, Src1Mods, RHS, &I, /*ForceVGPR*/ true);
- SelectedMI = BuildMI(*BB, &I, DL, TII.get(Opcode), Dst);
- if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src0_modifiers))
- SelectedMI.addImm(Src0Mods);
- SelectedMI.addReg(Src0Reg);
- if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src1_modifiers))
- SelectedMI.addImm(Src1Mods);
- SelectedMI.addReg(Src1Reg);
- if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::clamp))
- SelectedMI.addImm(0); // clamp
- if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::op_sel))
- SelectedMI.addImm(0); // op_sel
-
- RBI.constrainGenericRegister(Dst, *TRI.getBoolRC(), *MRI);
- constrainSelectedInstRegOperands(*SelectedMI, TII, TRI, RBI);
-
- I.eraseFromParent();
- return true;
-}
-
// Ballot has to zero bits in input lane-mask that are zero in current exec,
// Done as AND with exec. For inputs that are results of instruction that
// implicitly use same exec, for example compares in same basic block or SCC to
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
index 19028ef58a166..37d0138af28bc 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
@@ -112,7 +112,6 @@ class AMDGPUInstructionSelector final : public InstructionSelector {
bool selectInterpP1F16(MachineInstr &MI) const;
bool selectWritelane(MachineInstr &MI) const;
bool selectDivScale(MachineInstr &MI) const;
- bool selectIntrinsicCmp(MachineInstr &MI) const;
bool selectBallot(MachineInstr &I) const;
bool selectRelocConstant(MachineInstr &I) const;
bool selectGroupStaticSize(MachineInstr &I) const;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index c57ef9392a4ca..f65d4aa4c086b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -8106,31 +8106,6 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
// Replace the use G_BRCOND with the exec manipulate and branch pseudos.
auto IntrID = cast<GIntrinsic>(MI).getIntrinsicID();
switch (IntrID) {
- case Intrinsic::amdgcn_icmp: {
- // amdgcn.icmp(i1 src0, i1 0, NE) -> ballot(src0)
- // This is the only valid form of amdgcn.icmp with i1 inputs.
- Register Src0 = MI.getOperand(2).getReg();
- LLT SrcTy = MRI.getType(Src0);
- if (SrcTy != LLT::scalar(1))
- return true; // Not i1, leave for default handling.
-
- // Check that src1 is constant 0.
- Register Src1 = MI.getOperand(3).getReg();
- auto Src1Const = getIConstantVRegValWithLookThrough(Src1, MRI);
- if (!Src1Const || Src1Const->Value != 0)
- return false; // Invalid i1 icmp form.
-
- // Check that predicate is ICMP_NE.
- int64_t Pred = MI.getOperand(4).getImm();
- if (Pred != CmpInst::ICMP_NE)
- return false; // Invalid i1 icmp form.
-
- // Convert to ballot.
- Register Dst = MI.getOperand(0).getReg();
- B.buildIntrinsic(Intrinsic::amdgcn_ballot, Dst).addUse(Src0);
- MI.eraseFromParent();
- return true;
- }
case Intrinsic::sponentry:
if (B.getMF().getInfo<SIMachineFunctionInfo>()->isBottomOfStack()) {
// FIXME: The imported pattern checks for i32 instead of p5; if we fix
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 7f7225ad6d311..2a6f608486b58 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1762,26 +1762,6 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
addRulesForIOpcs({returnaddress}).Any({{UniP0}, {{SgprP0}, {}}});
- // Note: amdgcn.icmp with i1 inputs is legalized to ballot in the legalizer,
- // so no S1 rules are needed here.
- addRulesForIOpcs({amdgcn_icmp})
- .Any({{UniS64, _, S16}, {{Sgpr64}, {IntrId, Vgpr16, Vgpr16}}})
- .Any({{UniS64, _, S32}, {{Sgpr64}, {IntrId, Vgpr32, Vgpr32}}})
- .Any({{UniS64, _, S64}, {{Sgpr64}, {IntrId, Vgpr64, Vgpr64}}})
-
- .Any({{UniS32, _, S16}, {{Sgpr32}, {IntrId, Vgpr16, Vgpr16}}})
- .Any({{UniS32, _, S32}, {{Sgpr32}, {IntrId, Vgpr32, Vgpr32}}})
- .Any({{UniS32, _, S64}, {{Sgpr32}, {IntrId, Vgpr64, Vgpr64}}});
-
- addRulesForIOpcs({amdgcn_fcmp})
- .Any({{UniS64, _, S16}, {{Sgpr64}, {IntrId, Vgpr16, Vgpr16}}})
- .Any({{UniS64, _, S32}, {{Sgpr64}, {IntrId, Vgpr32, Vgpr32}}})
- .Any({{UniS64, _, S64}, {{Sgpr64}, {IntrId, Vgpr64, Vgpr64}}})
-
- .Any({{UniS32, _, S16}, {{Sgpr32}, {IntrId, Vgpr16, Vgpr16}}})
- .Any({{UniS32, _, S32}, {{Sgpr32}, {IntrId, Vgpr32, Vgpr32}}})
- .Any({{UniS32, _, S64}, {{Sgpr32}, {IntrId, Vgpr64, Vgpr64}}});
-
addRulesForIOpcs({amdgcn_s_getpc}).Any({{UniS64, _}, {{Sgpr64}, {}}});
addRulesForIOpcs({amdgcn_s_getreg}).Any({{}, {{Sgpr32}, {IntrId}}});
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 200234c23c886..8359cd9b02ae6 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -4965,16 +4965,6 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Src1Size);
break;
}
- case Intrinsic::amdgcn_icmp:
- case Intrinsic::amdgcn_fcmp: {
- unsigned DstSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
- // This is not VCCRegBank because this is not used in boolean contexts.
- OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, DstSize);
- unsigned OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
- OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, OpSize);
- OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, OpSize);
- break;
- }
case Intrinsic::amdgcn_readlane: {
// This must be an SGPR, but accept a VGPR.
Register IdxReg = MI.getOperand(3).getReg();
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td b/llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
index 2f7f72bd58f0e..81738d3fdc65a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
@@ -398,8 +398,6 @@ def UniformIntrinsics : GenericTable {
def : AlwaysUniform<int_amdgcn_readfirstlane>;
def : AlwaysUniform<int_amdgcn_readlane>;
-def : AlwaysUniform<int_amdgcn_icmp>;
-def : AlwaysUniform<int_amdgcn_fcmp>;
def : AlwaysUniform<int_amdgcn_ballot>;
def : AlwaysUniform<int_amdgcn_if_break>;
def : AlwaysUniform<int_amdgcn_cluster_workgroup_id_x>;
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index cb38d9081f16f..820c9642c36fb 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -7822,69 +7822,6 @@ SDValue SITargetLowering::lowerIntrinsicLoad(MemSDNode *M, bool IsFormat,
DL);
}
-static SDValue lowerICMPIntrinsic(const SITargetLowering &TLI, SDNode *N,
- SelectionDAG &DAG) {
- EVT VT = N->getValueType(0);
- unsigned CondCode = N->getConstantOperandVal(3);
- if (!ICmpInst::isIntPredicate(static_cast<ICmpInst::Predicate>(CondCode)))
- return DAG.getPOISON(VT);
-
- ICmpInst::Predicate IcInput = static_cast<ICmpInst::Predicate>(CondCode);
-
- SDValue LHS = N->getOperand(1);
- SDValue RHS = N->getOperand(2);
-
- SDLoc DL(N);
-
- EVT CmpVT = LHS.getValueType();
- if (CmpVT == MVT::i16 && !TLI.isTypeLegal(MVT::i16)) {
- unsigned PromoteOp =
- ICmpInst::isSigned(IcInput) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
- LHS = DAG.getNode(PromoteOp, DL, MVT::i32, LHS);
- RHS = DAG.getNode(PromoteOp, DL, MVT::i32, RHS);
- }
-
- ISD::CondCode CCOpcode = getICmpCondCode(IcInput);
-
- unsigned WavefrontSize = TLI.getSubtarget()->getWavefrontSize();
- EVT CCVT = EVT::getIntegerVT(*DAG.getContext(), WavefrontSize);
-
- SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, DL, CCVT, LHS, RHS,
- DAG.getCondCode(CCOpcode));
- if (VT.bitsEq(CCVT))
- return SetCC;
- return DAG.getZExtOrTrunc(SetCC, DL, VT);
-}
-
-static SDValue lowerFCMPIntrinsic(const SITargetLowering &TLI, SDNode *N,
- SelectionDAG &DAG) {
- EVT VT = N->getValueType(0);
-
- unsigned CondCode = N->getConstantOperandVal(3);
- if (!FCmpInst::isFPPredicate(static_cast<FCmpInst::Predicate>(CondCode)))
- return DAG.getPOISON(VT);
-
- SDValue Src0 = N->getOperand(1);
- SDValue Src1 = N->getOperand(2);
- EVT CmpVT = Src0.getValueType();
- SDLoc SL(N);
-
- if (CmpVT == MVT::f16 && !TLI.isTypeLegal(CmpVT)) {
- Src0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0);
- Src1 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src1);
- }
-
- FCmpInst::Predicate IcInput = static_cast<FCmpInst::Predicate>(CondCode);
- ISD::CondCode CCOpcode = getFCmpCondCode(IcInput);
- unsigned WavefrontSize = TLI.getSubtarget()->getWavefrontSize();
- EVT CCVT = EVT::getIntegerVT(*DAG.getContext(), WavefrontSize);
- SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, SL, CCVT, Src0, Src1,
- DAG.getCondCode(CCOpcode));
- if (VT.bitsEq(CCVT))
- return SetCC;
- return DAG.getZExtOrTrunc(SetCC, SL, VT);
-}
-
static SDValue lowerBALLOTIntrinsic(const SITargetLowering &TLI, SDNode *N,
SelectionDAG &DAG) {
EVT VT = N->getValueType(0);
@@ -11126,17 +11063,6 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
Denominator, Numerator);
}
- case Intrinsic::amdgcn_icmp: {
- // There is a Pat that handles this variant, so return it as-is.
- if (Op.getOperand(1).getValueType() == MVT::i1 &&
- Op.getConstantOperandVal(2) == 0 &&
- Op.getConstantOperandVal(3) == ICmpInst::Predicate::ICMP_NE)
- return Op;
- return lowerICMPIntrinsic(*this, Op.getNode(), DAG);
- }
- case Intrinsic::amdgcn_fcmp: {
- return lowerFCMPIntrinsic(*this, Op.getNode(), DAG);
- }
case Intrinsic::amdgcn_ballot:
return lowerBALLOTIntrinsic(*this, Op.getNode(), DAG);
case Intrinsic::amdgcn_fmed3:
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 49441b86d59eb..75f83ec69ed18 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -1431,18 +1431,6 @@ def : GCNPat <
(SI_DEMOTE_I1 SCSrc_i1:$src, -1)
>;
- // TODO: we could add more variants for other types of conditionals
-
-def : GCNPat <
- (i64 (int_amdgcn_icmp i1:$src, (i1 0), (i32 33))),
- (COPY $src) // Return the SGPRs representing i1 src
->;
-
-def : GCNPat <
- (i32 (int_amdgcn_icmp i1:$src, (i1 0), (i32 33))),
- (COPY $src) // Return the SGPRs representing i1 src
->;
-
//===----------------------------------------------------------------------===//
// VOP1 Patterns
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/always-uniform-gmir.mir b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/always-uniform-gmir.mir
index 8f44855b3caff..2fa704ef055cf 100644
--- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/always-uniform-gmir.mir
+++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/always-uniform-gmir.mir
@@ -16,49 +16,6 @@ body: |
S_ENDPGM 0
...
---
-name: icmp
-body: |
- bb.1:
- liveins: $sgpr4_sgpr5
- ; CHECK-LABEL: MachineUniformityInfo for function: @icmp
- ; CHECK: ALL VALUES UNIFORM
-
- %3:_(p4) = COPY $sgpr4_sgpr5
- %13:_(s32) = G_CONSTANT i32 0
- %7:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
- %8:_(s32) = G_LOAD %7(p4) :: (dereferenceable invariant load (s32), align 16, addrspace 4)
- %9:_(s64) = G_CONSTANT i64 8
- %10:_(p4) = G_PTR_ADD %7, %9(s64)
- %11:_(p1) = G_LOAD %10(p4) :: (dereferenceable invariant load (p1), addrspace 4)
- %12:_(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.icmp), %8(s32), %13(s32), 33
- G_STORE %12(s64), %11(p1) :: (volatile store (s64) , addrspace 1)
- S_ENDPGM 0
-
-...
----
-name: fcmp
-body: |
- bb.1:
- liveins: $sgpr4_sgpr5
- ; CHECK-LABEL: MachineUniformityInfo for function: @fcmp
- ; CHECK: ALL VALUES UNIFORM
-
- %3:_(p4) = COPY $sgpr4_sgpr5
- %10:_(s32) = G_CONSTANT i32 0
- %12:_(s32) = G_CONSTANT i32 1
- %16:_(p1) = G_IMPLICIT_DEF
- %7:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
- %8:_(<2 x s32>) = G_LOAD %7(p4) :: (dereferenceable invariant load (<2 x s32>) , align 16, addrspace 4)
- %9:_(s32) = G_EXTRACT_VECTOR_ELT %8(<2 x s32>), %10(s32)
- %11:_(s32) = G_EXTRACT_VECTOR_ELT %8(<2 x s32>), %12(s32)
- %13:_(s64) = G_CONSTANT i64 4
- %14:_(p4) = G_PTR_ADD %7, %13(s64)
- %15:_(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.fcmp), %9(s32), %11(s32), 33
- G_STORE %15(s64), %16(p1) :: (volatile store (s64) into `ptr addrspace(1) undef`, addrspace 1)
- S_ENDPGM 0
-
-...
----
name: ballot
body: |
bb.1:
diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/always_uniform.ll b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/always_uniform.ll
index 6e75d4ead8cdd..fe8caf14b2aaa 100644
--- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/always_uniform.ll
+++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/always_uniform.ll
@@ -9,20 +9,6 @@ define amdgpu_kernel void @readfirstlane() {
ret void
}
-; CHECK-LABEL: for function 'icmp':
-define amdgpu_kernel void @icmp(i32 inreg %x) {
-; CHECK-NOT: DIVERGENT: %icmp = call i64 @llvm.amdgcn.icmp.i32
- %icmp = call i64 @llvm.amdgcn.icmp.i32(i32 %x, i32 0, i32 33)
- ret void
-}
-
-; CHECK-LABEL: for function 'fcmp':
-define amdgpu_kernel void @fcmp(float inreg %x, float inreg %y) {
-; CHECK-NOT: DIVERGENT: %fcmp = call i64 @llvm.amdgcn.fcmp.i32
- %fcmp = call i64 @llvm.amdgcn.fcmp.i32(float %x, float %y, i32 33)
- ret void
-}
-
; CHECK-LABEL: for function 'ballot':
define amdgpu_kernel void @ballot(i1 inreg %x) {
; CHECK-NOT: DIVERGENT: %ballot = call i64 @llvm.amdgcn.ballot.i32
@@ -259,8 +245,6 @@ define void @s_memrealtime(ptr addrspace(1) inreg %out) {
declare i32 @llvm.amdgcn.workitem.id.x() #0
declare i32 @llvm.amdgcn.readfirstlane(i32) #0
-declare i64 @llvm.amdgcn.icmp.i32(i32, i32, i32) #1
-declare i64 @llvm.amdgcn.fcmp.i32(float, float, i32) #1
declare i64 @llvm.amdgcn.ballot.i32(i1) #1
declare i32 @llvm.amdgcn.workgroup.id.x() #0
declare i32 @llvm.amdgcn.workgroup.id.y() #0
diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/irreducible-2.ll b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/irreducible-2.ll
index 91b444647f8bf..316d43b1a7783 100644
--- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/irreducible-2.ll
+++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/irreducible-2.ll
@@ -569,37 +569,8 @@ X:
ret void
}
-define amdgpu_kernel void @always_uniform() {
-; CHECK-LABEL: UniformityInfo for function 'always_uniform':
-; CHECK: CYCLES ASSUMED DIVERGENT:
-; CHECK: depth=1: entries(bb2 bb3)
-
-bb:
- %inst = tail call i32 @llvm.amdgcn.mbcnt.hi(i32 0, i32 0)
- %inst1 = icmp ugt i32 %inst, 0
- br i1 %inst1, label %bb3, label %bb2
-; CHECK: DIVERGENT: %inst = tail call i32 @llvm.amdgcn.mbcnt.hi(i32 0, i32 0)
-; CHECK: DIVERGENT: %inst1 = icmp ugt i32 %inst, 0
-; CHECK: DIVERGENT: br i1 %inst1, label %bb3, label %bb2
-
-bb2: ; preds = %bb3, %bb
- br label %bb3
-
-bb3: ; preds = %bb2, %bb
- %inst4 = tail call i64 @llvm.amdgcn.icmp.i64.i16(i16 0, i16 0, i32 0)
- %inst5 = trunc i64 %inst4 to i32
- %inst6 = and i32 0, %inst5
- br label %bb2
-; CHECK-LABEL: BLOCK bb3
-; CHECK-NOT: DIVERGENT: {{.*}} call i64 @llvm.amdgcn.icmp.i64.i16
-; CHECK: DIVERGENT: %inst5 = trunc i64 %inst4 to i32
-; CHECK: DIVERGENT: %inst6 = and i32 0, %inst5
-}
-
declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32)
-declare i64 @llvm.amdgcn.icmp.i64.i16(i16, i16, i32 immarg)
-
declare i32 @llvm.amdgcn.workitem.id.x() #0
attributes #0 = { nounwind readnone }
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w32.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w32.mir
deleted file mode 100644
index 96953d51f26aa..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w32.mir
+++ /dev/null
@@ -1,171 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -mattr=+wavefrontsize32 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -mattr=+wavefrontsize32 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
-
----
-name: fcmp_false_f16
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-
-body: |
- bb.0:
- liveins: $vgpr0, $vgpr1
- ; GFX11-TRUE16-LABEL: name: fcmp_false_f16
- ; GFX11-TRUE16: liveins: $vgpr0, $vgpr1
- ; GFX11-TRUE16-NEXT: {{ $}}
- ; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
- ; GFX11-TRUE16-NEXT: [[V_CVT_F16_F32_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_CVT_F16_F32_t16_e64 0, [[COPY]], 0, 0, 0, implicit $mode, implicit $exec
- ; GFX11-TRUE16-NEXT: [[V_CVT_F16_F32_t16_e64_1:%[0-9]+]]:vgpr_16 = nofpexcept V_CVT_F16_F32_t16_e64 0, [[COPY1]], 0, 0, 0, implicit $mode, implicit $exec
- ; GFX11-TRUE16-NEXT: [[V_CMP_F_F16_t16_e64_:%[0-9]+]]:sreg_32 = V_CMP_F_F16_t16_e64 0, [[V_CVT_F16_F32_t16_e64_]], 0, [[V_CVT_F16_F32_t16_e64_1]], 0, 0, implicit $mode, implicit $exec
- ; GFX11-TRUE16-NEXT: S_ENDPGM 0, implicit [[V_CMP_F_F16_t16_e64_]]
- ;
- ; GFX11-FAKE16-LABEL: name: fcmp_false_f16
- ; GFX11-FAKE16: liveins: $vgpr0, $vgpr1
- ; GFX11-FAKE16-NEXT: {{ $}}
- ; GFX11-FAKE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX11-FAKE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
- ; GFX11-FAKE16-NEXT: [[V_CVT_F16_F32_fake16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_F16_F32_fake16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
- ; GFX11-FAKE16-NEXT: [[V_CVT_F16_F32_fake16_e64_1:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_F16_F32_fake16_e64 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
- ; GFX11-FAKE16-NEXT: [[V_CMP_F_F16_fake16_e64_:%[0-9]+]]:sreg_32 = V_CMP_F_F16_fake16_e64 0, [[V_CVT_F16_F32_fake16_e64_]], 0, [[V_CVT_F16_F32_fake16_e64_1]], 0, implicit $mode, implicit $exec
- ; GFX11-FAKE16-NEXT: S_ENDPGM 0, implicit [[V_CMP_F_F16_fake16_e64_]]
- %0:vgpr(s32) = COPY $vgpr0
- %1:vgpr(s32) = COPY $vgpr1
- %2:vgpr(s16) = G_FPTRUNC %0
- %3:vgpr(s16) = G_FPTRUNC %1
- %4:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.fcmp), %2, %3, 0
- S_ENDPGM 0, implicit %4
-...
-
----
-name: fcmp_true_f16
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-
-body: |
- bb.0:
- liveins: $vgpr0, $vgpr1
- ; GFX11-TRUE16-LABEL: name: fcmp_true_f16
- ; GFX11-TRUE16: liveins: $vgpr0, $vgpr1
- ; GFX11-TRUE16-NEXT: {{ $}}
- ; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
- ; GFX11-TRUE16-NEXT: [[V_CVT_F16_F32_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_CVT_F16_F32_t16_e64 0, [[COPY]], 0, 0, 0, implicit $mode, implicit $exec
- ; GFX11-TRUE16-NEXT: [[V_CVT_F16_F32_t16_e64_1:%[0-9]+]]:vgpr_16 = nofpexcept V_CVT_F16_F32_t16_e64 0, [[COPY1]], 0, 0, 0, implicit $mode, implicit $exec
- ; GFX11-TRUE16-NEXT: [[V_CMP_TRU_F16_t16_e64_:%[0-9]+]]:sreg_32 = V_CMP_TRU_F16_t16_e64 0, [[V_CVT_F16_F32_t16_e64_]], 0, [[V_CVT_F16_F32_t16_e64_1]], 0, 0, implicit $mode, implicit $exec
- ; GFX11-TRUE16-NEXT: S_ENDPGM 0, implicit [[V_CMP_TRU_F16_t16_e64_]]
- ;
- ; GFX11-FAKE16-LABEL: name: fcmp_true_f16
- ; GFX11-FAKE16: liveins: $vgpr0, $vgpr1
- ; GFX11-FAKE16-NEXT: {{ $}}
- ; GFX11-FAKE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX11-FAKE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
- ; GFX11-FAKE16-NEXT: [[V_CVT_F16_F32_fake16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_F16_F32_fake16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
- ; GFX11-FAKE16-NEXT: [[V_CVT_F16_F32_fake16_e64_1:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_F16_F32_fake16_e64 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
- ; GFX11-FAKE16-NEXT: [[V_CMP_TRU_F16_fake16_e64_:%[0-9]+]]:sreg_32 = V_CMP_TRU_F16_fake16_e64 0, [[V_CVT_F16_F32_fake16_e64_]], 0, [[V_CVT_F16_F32_fake16_e64_1]], 0, implicit $mode, implicit $exec
- ; GFX11-FAKE16-NEXT: S_ENDPGM 0, implicit [[V_CMP_TRU_F16_fake16_e64_]]
- %0:vgpr(s32) = COPY $vgpr0
- %1:vgpr(s32) = COPY $vgpr1
- %2:vgpr(s16) = G_FPTRUNC %0
- %3:vgpr(s16) = G_FPTRUNC %1
- %4:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.fcmp), %2, %3, 15
- S_ENDPGM 0, implicit %4
-...
-
----
-name: fcmp_false_f32
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-
-body: |
- bb.0:
- liveins: $vgpr0, $vgpr1
- ; GFX11-LABEL: name: fcmp_false_f32
- ; GFX11: liveins: $vgpr0, $vgpr1
- ; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
- ; GFX11-NEXT: [[V_CMP_F_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_F_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
- ; GFX11-NEXT: S_ENDPGM 0, implicit [[V_CMP_F_F32_e64_]]
- %0:vgpr(s32) = COPY $vgpr0
- %1:vgpr(s32) = COPY $vgpr1
- %4:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.fcmp), %0, %1, 0
- S_ENDPGM 0, implicit %4
-...
-
----
-name: fcmp_true_f32
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-
-body: |
- bb.0:
- liveins: $vgpr0, $vgpr1
- ; GFX11-LABEL: name: fcmp_true_f32
- ; GFX11: liveins: $vgpr0, $vgpr1
- ; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
- ; GFX11-NEXT: [[V_CMP_TRU_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_TRU_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
- ; GFX11-NEXT: S_ENDPGM 0, implicit [[V_CMP_TRU_F32_e64_]]
- %0:vgpr(s32) = COPY $vgpr0
- %1:vgpr(s32) = COPY $vgpr1
- %4:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.fcmp), %0, %1, 15
- S_ENDPGM 0, implicit %4
-...
-
----
-name: fcmp_false_f64
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-
-body: |
- bb.0:
- liveins: $vgpr0, $vgpr1
- ; GFX11-LABEL: name: fcmp_false_f64
- ; GFX11: liveins: $vgpr0, $vgpr1
- ; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
- ; GFX11-NEXT: [[V_CVT_F64_F32_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_CVT_F64_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
- ; GFX11-NEXT: [[V_CVT_F64_F32_e64_1:%[0-9]+]]:vreg_64 = nofpexcept V_CVT_F64_F32_e64 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
- ; GFX11-NEXT: [[V_CMP_F_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_F_F64_e64 0, [[V_CVT_F64_F32_e64_]], 0, [[V_CVT_F64_F32_e64_1]], 0, implicit $mode, implicit $exec
- ; GFX11-NEXT: S_ENDPGM 0, implicit [[V_CMP_F_F64_e64_]]
- %0:vgpr(s32) = COPY $vgpr0
- %1:vgpr(s32) = COPY $vgpr1
- %2:vgpr(s64) = G_FPEXT %0
- %3:vgpr(s64) = G_FPEXT %1
- %4:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.fcmp), %2, %3, 0
- S_ENDPGM 0, implicit %4
-...
-
----
-name: fcmp_true_f64
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-
-body: |
- bb.0:
- liveins: $vgpr0, $vgpr1
- ; GFX11-LABEL: name: fcmp_true_f64
- ; GFX11: liveins: $vgpr0, $vgpr1
- ; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
- ; GFX11-NEXT: [[V_CVT_F64_F32_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_CVT_F64_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
- ; GFX11-NEXT: [[V_CVT_F64_F32_e64_1:%[0-9]+]]:vreg_64 = nofpexcept V_CVT_F64_F32_e64 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
- ; GFX11-NEXT: [[V_CMP_TRU_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_TRU_F64_e64 0, [[V_CVT_F64_F32_e64_]], 0, [[V_CVT_F64_F32_e64_1]], 0, implicit $mode, implicit $exec
- ; GFX11-NEXT: S_ENDPGM 0, implicit [[V_CMP_TRU_F64_e64_]]
- %0:vgpr(s32) = COPY $vgpr0
- %1:vgpr(s32) = COPY $vgpr1
- %2:vgpr(s64) = G_FPEXT %0
- %3:vgpr(s64) = G_FPEXT %1
- %4:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.fcmp), %2, %3, 15
- S_ENDPGM 0, implicit %4
-...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w64.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w64.mir
deleted file mode 100644
index 4cada33b80126..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w64.mir
+++ /dev/null
@@ -1,171 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -mattr="+wavefrontsize64" -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -mattr="+wavefrontsize64" -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
-
----
-name: fcmp_false_f16
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-
-body: |
- bb.0:
- liveins: $vgpr0, $vgpr1
- ; GFX11-TRUE16-LABEL: name: fcmp_false_f16
- ; GFX11-TRUE16: liveins: $vgpr0, $vgpr1
- ; GFX11-TRUE16-NEXT: {{ $}}
- ; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
- ; GFX11-TRUE16-NEXT: [[V_CVT_F16_F32_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_CVT_F16_F32_t16_e64 0, [[COPY]], 0, 0, 0, implicit $mode, implicit $exec
- ; GFX11-TRUE16-NEXT: [[V_CVT_F16_F32_t16_e64_1:%[0-9]+]]:vgpr_16 = nofpexcept V_CVT_F16_F32_t16_e64 0, [[COPY1]], 0, 0, 0, implicit $mode, implicit $exec
- ; GFX11-TRUE16-NEXT: [[V_CMP_F_F16_t16_e64_:%[0-9]+]]:sreg_64 = V_CMP_F_F16_t16_e64 0, [[V_CVT_F16_F32_t16_e64_]], 0, [[V_CVT_F16_F32_t16_e64_1]], 0, 0, implicit $mode, implicit $exec
- ; GFX11-TRUE16-NEXT: S_ENDPGM 0, implicit [[V_CMP_F_F16_t16_e64_]]
- ;
- ; GFX11-FAKE16-LABEL: name: fcmp_false_f16
- ; GFX11-FAKE16: liveins: $vgpr0, $vgpr1
- ; GFX11-FAKE16-NEXT: {{ $}}
- ; GFX11-FAKE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX11-FAKE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
- ; GFX11-FAKE16-NEXT: [[V_CVT_F16_F32_fake16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_F16_F32_fake16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
- ; GFX11-FAKE16-NEXT: [[V_CVT_F16_F32_fake16_e64_1:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_F16_F32_fake16_e64 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
- ; GFX11-FAKE16-NEXT: [[V_CMP_F_F16_fake16_e64_:%[0-9]+]]:sreg_64 = V_CMP_F_F16_fake16_e64 0, [[V_CVT_F16_F32_fake16_e64_]], 0, [[V_CVT_F16_F32_fake16_e64_1]], 0, implicit $mode, implicit $exec
- ; GFX11-FAKE16-NEXT: S_ENDPGM 0, implicit [[V_CMP_F_F16_fake16_e64_]]
- %0:vgpr(s32) = COPY $vgpr0
- %1:vgpr(s32) = COPY $vgpr1
- %2:vgpr(s16) = G_FPTRUNC %0
- %3:vgpr(s16) = G_FPTRUNC %1
- %4:sgpr(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.fcmp), %2, %3, 0
- S_ENDPGM 0, implicit %4
-...
-
----
-name: fcmp_true_f16
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-
-body: |
- bb.0:
- liveins: $vgpr0, $vgpr1
- ; GFX11-TRUE16-LABEL: name: fcmp_true_f16
- ; GFX11-TRUE16: liveins: $vgpr0, $vgpr1
- ; GFX11-TRUE16-NEXT: {{ $}}
- ; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
- ; GFX11-TRUE16-NEXT: [[V_CVT_F16_F32_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_CVT_F16_F32_t16_e64 0, [[COPY]], 0, 0, 0, implicit $mode, implicit $exec
- ; GFX11-TRUE16-NEXT: [[V_CVT_F16_F32_t16_e64_1:%[0-9]+]]:vgpr_16 = nofpexcept V_CVT_F16_F32_t16_e64 0, [[COPY1]], 0, 0, 0, implicit $mode, implicit $exec
- ; GFX11-TRUE16-NEXT: [[V_CMP_TRU_F16_t16_e64_:%[0-9]+]]:sreg_64 = V_CMP_TRU_F16_t16_e64 0, [[V_CVT_F16_F32_t16_e64_]], 0, [[V_CVT_F16_F32_t16_e64_1]], 0, 0, implicit $mode, implicit $exec
- ; GFX11-TRUE16-NEXT: S_ENDPGM 0, implicit [[V_CMP_TRU_F16_t16_e64_]]
- ;
- ; GFX11-FAKE16-LABEL: name: fcmp_true_f16
- ; GFX11-FAKE16: liveins: $vgpr0, $vgpr1
- ; GFX11-FAKE16-NEXT: {{ $}}
- ; GFX11-FAKE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX11-FAKE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
- ; GFX11-FAKE16-NEXT: [[V_CVT_F16_F32_fake16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_F16_F32_fake16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
- ; GFX11-FAKE16-NEXT: [[V_CVT_F16_F32_fake16_e64_1:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_F16_F32_fake16_e64 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
- ; GFX11-FAKE16-NEXT: [[V_CMP_TRU_F16_fake16_e64_:%[0-9]+]]:sreg_64 = V_CMP_TRU_F16_fake16_e64 0, [[V_CVT_F16_F32_fake16_e64_]], 0, [[V_CVT_F16_F32_fake16_e64_1]], 0, implicit $mode, implicit $exec
- ; GFX11-FAKE16-NEXT: S_ENDPGM 0, implicit [[V_CMP_TRU_F16_fake16_e64_]]
- %0:vgpr(s32) = COPY $vgpr0
- %1:vgpr(s32) = COPY $vgpr1
- %2:vgpr(s16) = G_FPTRUNC %0
- %3:vgpr(s16) = G_FPTRUNC %1
- %4:sgpr(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.fcmp), %2, %3, 15
- S_ENDPGM 0, implicit %4
-...
-
----
-name: fcmp_false_f32
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-
-body: |
- bb.0:
- liveins: $vgpr0, $vgpr1
- ; GFX11-LABEL: name: fcmp_false_f32
- ; GFX11: liveins: $vgpr0, $vgpr1
- ; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
- ; GFX11-NEXT: [[V_CMP_F_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_F_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
- ; GFX11-NEXT: S_ENDPGM 0, implicit [[V_CMP_F_F32_e64_]]
- %0:vgpr(s32) = COPY $vgpr0
- %1:vgpr(s32) = COPY $vgpr1
- %4:sgpr(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.fcmp), %0, %1, 0
- S_ENDPGM 0, implicit %4
-...
-
----
-name: fcmp_true_f32
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-
-body: |
- bb.0:
- liveins: $vgpr0, $vgpr1
- ; GFX11-LABEL: name: fcmp_true_f32
- ; GFX11: liveins: $vgpr0, $vgpr1
- ; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
- ; GFX11-NEXT: [[V_CMP_TRU_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_TRU_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
- ; GFX11-NEXT: S_ENDPGM 0, implicit [[V_CMP_TRU_F32_e64_]]
- %0:vgpr(s32) = COPY $vgpr0
- %1:vgpr(s32) = COPY $vgpr1
- %4:sgpr(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.fcmp), %0, %1, 15
- S_ENDPGM 0, implicit %4
-...
-
----
-name: fcmp_false_f64
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-
-body: |
- bb.0:
- liveins: $vgpr0, $vgpr1
- ; GFX11-LABEL: name: fcmp_false_f64
- ; GFX11: liveins: $vgpr0, $vgpr1
- ; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
- ; GFX11-NEXT: [[V_CVT_F64_F32_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_CVT_F64_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
- ; GFX11-NEXT: [[V_CVT_F64_F32_e64_1:%[0-9]+]]:vreg_64 = nofpexcept V_CVT_F64_F32_e64 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
- ; GFX11-NEXT: [[V_CMP_F_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_F_F64_e64 0, [[V_CVT_F64_F32_e64_]], 0, [[V_CVT_F64_F32_e64_1]], 0, implicit $mode, implicit $exec
- ; GFX11-NEXT: S_ENDPGM 0, implicit [[V_CMP_F_F64_e64_]]
- %0:vgpr(s32) = COPY $vgpr0
- %1:vgpr(s32) = COPY $vgpr1
- %2:vgpr(s64) = G_FPEXT %0
- %3:vgpr(s64) = G_FPEXT %1
- %4:sgpr(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.fcmp), %2, %3, 0
- S_ENDPGM 0, implicit %4
-...
-
----
-name: fcmp_true_f64
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-
-body: |
- bb.0:
- liveins: $vgpr0, $vgpr1
- ; GFX11-LABEL: name: fcmp_true_f64
- ; GFX11: liveins: $vgpr0, $vgpr1
- ; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
- ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
- ; GFX11-NEXT: [[V_CVT_F64_F32_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_CVT_F64_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
- ; GFX11-NEXT: [[V_CVT_F64_F32_e64_1:%[0-9]+]]:vreg_64 = nofpexcept V_CVT_F64_F32_e64 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
- ; GFX11-NEXT: [[V_CMP_TRU_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_TRU_F64_e64 0, [[V_CVT_F64_F32_e64_]], 0, [[V_CVT_F64_F32_e64_1]], 0, implicit $mode, implicit $exec
- ; GFX11-NEXT: S_ENDPGM 0, implicit [[V_CMP_TRU_F64_e64_]]
- %0:vgpr(s32) = COPY $vgpr0
- %1:vgpr(s32) = COPY $vgpr1
- %2:vgpr(s64) = G_FPEXT %0
- %3:vgpr(s64) = G_FPEXT %1
- %4:sgpr(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.fcmp), %2, %3, 15
- S_ENDPGM 0, implicit %4
-...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir
deleted file mode 100644
index 685a712bbcd18..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir
+++ /dev/null
@@ -1,78 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -verify-machineinstrs -o - %s | FileCheck %s
-
----
-name: fcmp_ss
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0, $sgpr1
- ; CHECK-LABEL: name: fcmp_ss
- ; CHECK: liveins: $sgpr0, $sgpr1
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.fcmp), [[COPY2]](s32), [[COPY3]](s32), 1
- %0:_(s32) = COPY $sgpr0
- %1:_(s32) = COPY $sgpr1
- %2:_(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.fcmp), %0, %1, 1
-...
-
----
-name: fcmp_sv
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0, $vgpr0
- ; CHECK-LABEL: name: fcmp_sv
- ; CHECK: liveins: $sgpr0, $vgpr0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.fcmp), [[COPY2]](s32), [[COPY1]](s32), 1
- %0:_(s32) = COPY $sgpr0
- %1:_(s32) = COPY $vgpr0
- %2:_(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.fcmp), %0, %1, 1
-...
-
----
-name: fcmp_vs
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0, $vgpr0
- ; CHECK-LABEL: name: fcmp_vs
- ; CHECK: liveins: $sgpr0, $vgpr0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.fcmp), [[COPY]](s32), [[COPY2]](s32), 1
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $sgpr0
- %2:_(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.fcmp), %0, %1, 1
-...
-
----
-name: fcmp_vv
-legalized: true
-
-body: |
- bb.0:
- liveins: $vgpr0, $vgpr1
- ; CHECK-LABEL: name: fcmp_vv
- ; CHECK: liveins: $vgpr0, $vgpr1
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
- ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.fcmp), [[COPY]](s32), [[COPY1]](s32), 1
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.fcmp), %0, %1, 1
-...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir
deleted file mode 100644
index 5c181562954d7..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir
+++ /dev/null
@@ -1,78 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -verify-machineinstrs -o - %s | FileCheck %s
-
----
-name: icmp_ss
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0, $sgpr1
- ; CHECK-LABEL: name: icmp_ss
- ; CHECK: liveins: $sgpr0, $sgpr1
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.icmp), [[COPY2]](s32), [[COPY3]](s32), 32
- %0:_(s32) = COPY $sgpr0
- %1:_(s32) = COPY $sgpr1
- %2:_(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.icmp), %0, %1, 32
-...
-
----
-name: icmp_sv
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0, $vgpr0
- ; CHECK-LABEL: name: icmp_sv
- ; CHECK: liveins: $sgpr0, $vgpr0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.icmp), [[COPY2]](s32), [[COPY1]](s32), 32
- %0:_(s32) = COPY $sgpr0
- %1:_(s32) = COPY $vgpr0
- %2:_(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.icmp), %0, %1, 32
-...
-
----
-name: icmp_vs
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0, $vgpr0
- ; CHECK-LABEL: name: icmp_vs
- ; CHECK: liveins: $sgpr0, $vgpr0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
- ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.icmp), [[COPY]](s32), [[COPY2]](s32), 32
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $sgpr0
- %2:_(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.icmp), %0, %1, 32
-...
-
----
-name: icmp_vv
-legalized: true
-
-body: |
- bb.0:
- liveins: $vgpr0, $vgpr1
- ; CHECK-LABEL: name: icmp_vv
- ; CHECK: liveins: $vgpr0, $vgpr1
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
- ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.icmp), [[COPY]](s32), [[COPY1]](s32), 32
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $vgpr1
- %2:_(s64) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.icmp), %0, %1, 32
-...
diff --git a/llvm/test/CodeGen/AMDGPU/bitcast-vector-extract.ll b/llvm/test/CodeGen/AMDGPU/bitcast-vector-extract.ll
index 913dc3cfa6309..fb4985a6ae617 100644
--- a/llvm/test/CodeGen/AMDGPU/bitcast-vector-extract.ll
+++ b/llvm/test/CodeGen/AMDGPU/bitcast-vector-extract.ll
@@ -68,26 +68,5 @@ define amdgpu_kernel void @store_bitcast_constant_v8i32_to_v16i16(ptr addrspace(
ret void
}
-; GCN-LABEL: {{^}}store_value_lowered_to_undef_bitcast_source:
-; GCN-NOT: store_dword
-define amdgpu_kernel void @store_value_lowered_to_undef_bitcast_source(ptr addrspace(1) %out, i64 %a, i64 %b) #0 {
- %undef = call i64 @llvm.amdgcn.icmp.i64(i64 %a, i64 %b, i32 999) #1
- %bc = bitcast i64 %undef to <2 x i32>
- store <2 x i32> %bc, ptr addrspace(1) %out
- ret void
-}
-
-; GCN-LABEL: {{^}}store_value_lowered_to_undef_bitcast_source_extractelt:
-; GCN-NOT: store_dword
-define amdgpu_kernel void @store_value_lowered_to_undef_bitcast_source_extractelt(ptr addrspace(1) %out, i64 %a, i64 %b) #0 {
- %undef = call i64 @llvm.amdgcn.icmp.i64(i64 %a, i64 %b, i32 9999) #1
- %bc = bitcast i64 %undef to <2 x i32>
- %elt1 = extractelement <2 x i32> %bc, i32 1
- store i32 %elt1, ptr addrspace(1) %out
- ret void
-}
-
-declare i64 @llvm.amdgcn.icmp.i64(i64, i64, i32) #1
-
attributes #0 = { nounwind }
attributes #1 = { nounwind readnone convergent }
diff --git a/llvm/test/CodeGen/AMDGPU/lds-relocs.ll b/llvm/test/CodeGen/AMDGPU/lds-relocs.ll
index 91489d76b18f6..371944f43a0b5 100644
--- a/llvm/test/CodeGen/AMDGPU/lds-relocs.ll
+++ b/llvm/test/CodeGen/AMDGPU/lds-relocs.ll
@@ -54,8 +54,4 @@ main_body:
ret float %r
}
-; Function Attrs: convergent nounwind readnone
-declare i64 @llvm.amdgcn.icmp.i64.i32(i32, i32, i32) #4
-
attributes #0 = { "no-signed-zeros-fp-math"="true" }
-attributes #4 = { convergent nounwind readnone }
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i32.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i32.ll
index 9bcf8c7db29a0..40c6c645ead08 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i32.ll
@@ -397,132 +397,6 @@ false:
ret i32 33
}
-declare i32 @llvm.amdgcn.icmp.i32(i1, i1, i32)
-
-define amdgpu_cs i32 @branch_divergent_simulated_negated_ballot_ne_zero_and(i32 %v1, i32 %v2) {
-; CHECK-LABEL: branch_divergent_simulated_negated_ballot_ne_zero_and:
-; CHECK: ; %bb.0:
-; CHECK-NEXT: v_cmp_gt_u32_e32 vcc_lo, 12, v0
-; CHECK-NEXT: v_cmp_lt_u32_e64 s0, 34, v1
-; CHECK-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; CHECK-NEXT: s_cbranch_vccnz .LBB20_2
-; CHECK-NEXT: ; %bb.1: ; %true
-; CHECK-NEXT: s_mov_b32 s0, 42
-; CHECK-NEXT: s_branch .LBB20_3
-; CHECK-NEXT: .LBB20_2: ; %false
-; CHECK-NEXT: s_mov_b32 s0, 33
-; CHECK-NEXT: s_branch .LBB20_3
-; CHECK-NEXT: .LBB20_3:
- %v1c = icmp ult i32 %v1, 12
- %v2c = icmp ugt i32 %v2, 34
- %c = and i1 %v1c, %v2c
- %ballot = call i32 @llvm.amdgcn.icmp.i32(i1 %c, i1 0, i32 32) ; ICMP_EQ == 32
- %ballot_ne_zero = icmp ne i32 %ballot, 0
- br i1 %ballot_ne_zero, label %true, label %false
-true:
- ret i32 42
-false:
- ret i32 33
-}
-
-define amdgpu_cs i32 @branch_uniform_simulated_negated_ballot_ne_zero_and(i32 inreg %v1, i32 inreg %v2) {
-; TODO:
-; s_cmp_lt_u32 s0, 12
-; s_cselect_b32 s0, -1, 0
-; s_cmp_gt_u32 s1, 34
-; s_cselect_b32 s1, -1, 0
-; s_and_b32 s0, s0, s1
-; s_and_b32 s0, s0, exec_lo
-; could be improved to:
-; s_cmp_lt_u32 s0, 12
-; s_cselect_b32 s0, -1, 0
-; s_cmp_gt_u32 s1, 34
-; s_cselect_b32 s0, s0, 0
-; s_and_b32 s0, s0, exec_lo
-; By selecting into vcc(_lo) instead, we could even avoid the AND-with-exec.
-; CHECK-LABEL: branch_uniform_simulated_negated_ballot_ne_zero_and:
-; CHECK: ; %bb.0:
-; CHECK-NEXT: s_cmp_lt_u32 s0, 12
-; CHECK-NEXT: s_cselect_b32 s0, -1, 0
-; CHECK-NEXT: s_cmp_gt_u32 s1, 34
-; CHECK-NEXT: s_cselect_b32 s1, -1, 0
-; CHECK-NEXT: s_and_b32 s0, s0, s1
-; CHECK-NEXT: s_and_b32 s0, s0, exec_lo
-; CHECK-NEXT: s_cbranch_scc1 .LBB21_2
-; CHECK-NEXT: ; %bb.1: ; %true
-; CHECK-NEXT: s_mov_b32 s0, 42
-; CHECK-NEXT: s_branch .LBB21_3
-; CHECK-NEXT: .LBB21_2: ; %false
-; CHECK-NEXT: s_mov_b32 s0, 33
-; CHECK-NEXT: s_branch .LBB21_3
-; CHECK-NEXT: .LBB21_3:
- %v1c = icmp ult i32 %v1, 12
- %v2c = icmp ugt i32 %v2, 34
- %c = and i1 %v1c, %v2c
- %ballot = call i32 @llvm.amdgcn.icmp.i32(i1 %c, i1 0, i32 32) ; ICMP_EQ == 32
- %ballot_ne_zero = icmp ne i32 %ballot, 0
- br i1 %ballot_ne_zero, label %true, label %false
-true:
- ret i32 42
-false:
- ret i32 33
-}
-
-define amdgpu_cs i32 @branch_divergent_simulated_negated_ballot_eq_zero_and(i32 %v1, i32 %v2) {
-; CHECK-LABEL: branch_divergent_simulated_negated_ballot_eq_zero_and:
-; CHECK: ; %bb.0:
-; CHECK-NEXT: v_cmp_gt_u32_e32 vcc_lo, 12, v0
-; CHECK-NEXT: v_cmp_lt_u32_e64 s0, 34, v1
-; CHECK-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
-; CHECK-NEXT: s_cbranch_vccnz .LBB22_2
-; CHECK-NEXT: ; %bb.1: ; %false
-; CHECK-NEXT: s_mov_b32 s0, 33
-; CHECK-NEXT: s_branch .LBB22_3
-; CHECK-NEXT: .LBB22_2: ; %true
-; CHECK-NEXT: s_mov_b32 s0, 42
-; CHECK-NEXT: s_branch .LBB22_3
-; CHECK-NEXT: .LBB22_3:
- %v1c = icmp ult i32 %v1, 12
- %v2c = icmp ugt i32 %v2, 34
- %c = and i1 %v1c, %v2c
- %ballot = call i32 @llvm.amdgcn.icmp.i32(i1 %c, i1 0, i32 32) ; ICMP_EQ == 32
- %ballot_eq_zero = icmp eq i32 %ballot, 0
- br i1 %ballot_eq_zero, label %true, label %false
-true:
- ret i32 42
-false:
- ret i32 33
-}
-
-define amdgpu_cs i32 @branch_uniform_simulated_negated_ballot_eq_zero_and(i32 inreg %v1, i32 inreg %v2) {
-; CHECK-LABEL: branch_uniform_simulated_negated_ballot_eq_zero_and:
-; CHECK: ; %bb.0:
-; CHECK-NEXT: s_cmp_lt_u32 s0, 12
-; CHECK-NEXT: s_cselect_b32 s0, -1, 0
-; CHECK-NEXT: s_cmp_gt_u32 s1, 34
-; CHECK-NEXT: s_cselect_b32 s1, -1, 0
-; CHECK-NEXT: s_and_b32 s0, s0, s1
-; CHECK-NEXT: s_and_b32 s0, s0, exec_lo
-; CHECK-NEXT: s_cbranch_scc1 .LBB23_2
-; CHECK-NEXT: ; %bb.1: ; %false
-; CHECK-NEXT: s_mov_b32 s0, 33
-; CHECK-NEXT: s_branch .LBB23_3
-; CHECK-NEXT: .LBB23_2: ; %true
-; CHECK-NEXT: s_mov_b32 s0, 42
-; CHECK-NEXT: s_branch .LBB23_3
-; CHECK-NEXT: .LBB23_3:
- %v1c = icmp ult i32 %v1, 12
- %v2c = icmp ugt i32 %v2, 34
- %c = and i1 %v1c, %v2c
- %ballot = call i32 @llvm.amdgcn.icmp.i32(i1 %c, i1 0, i32 32) ; ICMP_EQ == 32
- %ballot_eq_zero = icmp eq i32 %ballot, 0
- br i1 %ballot_eq_zero, label %true, label %false
-true:
- ret i32 42
-false:
- ret i32 33
-}
-
; Input that is not constant or direct result of a compare.
; Tests setting 0 to inactive lanes.
define amdgpu_ps void @non_cst_non_compare_input(ptr addrspace(1) %out, i32 %tid, i32 %cond) {
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.ll
index 827a01ff33d02..aabf050a62134 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ballot.i64.ll
@@ -400,118 +400,6 @@ false:
ret i32 33
}
-declare i64 @llvm.amdgcn.icmp.i64(i1, i1, i32)
-
-define amdgpu_cs i32 @branch_divergent_simulated_negated_ballot_ne_zero_and(i32 %v1, i32 %v2) {
-; CHECK-LABEL: branch_divergent_simulated_negated_ballot_ne_zero_and:
-; CHECK: ; %bb.0:
-; CHECK-NEXT: v_cmp_gt_u32_e32 vcc, 12, v0
-; CHECK-NEXT: v_cmp_lt_u32_e64 s[0:1], 34, v1
-; CHECK-NEXT: s_and_b64 vcc, vcc, s[0:1]
-; CHECK-NEXT: s_cbranch_vccnz .LBB20_2
-; CHECK-NEXT: ; %bb.1: ; %true
-; CHECK-NEXT: s_mov_b32 s0, 42
-; CHECK-NEXT: s_branch .LBB20_3
-; CHECK-NEXT: .LBB20_2: ; %false
-; CHECK-NEXT: s_mov_b32 s0, 33
-; CHECK-NEXT: s_branch .LBB20_3
-; CHECK-NEXT: .LBB20_3:
- %v1c = icmp ult i32 %v1, 12
- %v2c = icmp ugt i32 %v2, 34
- %c = and i1 %v1c, %v2c
- %ballot = call i64 @llvm.amdgcn.icmp.i64(i1 %c, i1 0, i32 32) ; ICMP_EQ == 32
- %ballot_ne_zero = icmp ne i64 %ballot, 0
- br i1 %ballot_ne_zero, label %true, label %false
-true:
- ret i32 42
-false:
- ret i32 33
-}
-
-define amdgpu_cs i32 @branch_uniform_simulated_negated_ballot_ne_zero_and(i32 inreg %v1, i32 inreg %v2) {
-; CHECK-LABEL: branch_uniform_simulated_negated_ballot_ne_zero_and:
-; CHECK: ; %bb.0:
-; CHECK-NEXT: s_cmp_lt_u32 s0, 12
-; CHECK-NEXT: s_cselect_b64 s[2:3], -1, 0
-; CHECK-NEXT: s_cmp_gt_u32 s1, 34
-; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0
-; CHECK-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]
-; CHECK-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; CHECK-NEXT: s_cbranch_scc1 .LBB21_2
-; CHECK-NEXT: ; %bb.1: ; %true
-; CHECK-NEXT: s_mov_b32 s0, 42
-; CHECK-NEXT: s_branch .LBB21_3
-; CHECK-NEXT: .LBB21_2: ; %false
-; CHECK-NEXT: s_mov_b32 s0, 33
-; CHECK-NEXT: s_branch .LBB21_3
-; CHECK-NEXT: .LBB21_3:
- %v1c = icmp ult i32 %v1, 12
- %v2c = icmp ugt i32 %v2, 34
- %c = and i1 %v1c, %v2c
- %ballot = call i64 @llvm.amdgcn.icmp.i64(i1 %c, i1 0, i32 32) ; ICMP_EQ == 32
- %ballot_ne_zero = icmp ne i64 %ballot, 0
- br i1 %ballot_ne_zero, label %true, label %false
-true:
- ret i32 42
-false:
- ret i32 33
-}
-
-define amdgpu_cs i32 @branch_divergent_simulated_negated_ballot_eq_zero_and(i32 %v1, i32 %v2) {
-; CHECK-LABEL: branch_divergent_simulated_negated_ballot_eq_zero_and:
-; CHECK: ; %bb.0:
-; CHECK-NEXT: v_cmp_gt_u32_e32 vcc, 12, v0
-; CHECK-NEXT: v_cmp_lt_u32_e64 s[0:1], 34, v1
-; CHECK-NEXT: s_and_b64 vcc, vcc, s[0:1]
-; CHECK-NEXT: s_cbranch_vccnz .LBB22_2
-; CHECK-NEXT: ; %bb.1: ; %false
-; CHECK-NEXT: s_mov_b32 s0, 33
-; CHECK-NEXT: s_branch .LBB22_3
-; CHECK-NEXT: .LBB22_2: ; %true
-; CHECK-NEXT: s_mov_b32 s0, 42
-; CHECK-NEXT: s_branch .LBB22_3
-; CHECK-NEXT: .LBB22_3:
- %v1c = icmp ult i32 %v1, 12
- %v2c = icmp ugt i32 %v2, 34
- %c = and i1 %v1c, %v2c
- %ballot = call i64 @llvm.amdgcn.icmp.i64(i1 %c, i1 0, i32 32) ; ICMP_EQ == 32
- %ballot_eq_zero = icmp eq i64 %ballot, 0
- br i1 %ballot_eq_zero, label %true, label %false
-true:
- ret i32 42
-false:
- ret i32 33
-}
-
-define amdgpu_cs i32 @branch_uniform_simulated_negated_ballot_eq_zero_and(i32 inreg %v1, i32 inreg %v2) {
-; CHECK-LABEL: branch_uniform_simulated_negated_ballot_eq_zero_and:
-; CHECK: ; %bb.0:
-; CHECK-NEXT: s_cmp_lt_u32 s0, 12
-; CHECK-NEXT: s_cselect_b64 s[2:3], -1, 0
-; CHECK-NEXT: s_cmp_gt_u32 s1, 34
-; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0
-; CHECK-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]
-; CHECK-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; CHECK-NEXT: s_cbranch_scc1 .LBB23_2
-; CHECK-NEXT: ; %bb.1: ; %false
-; CHECK-NEXT: s_mov_b32 s0, 33
-; CHECK-NEXT: s_branch .LBB23_3
-; CHECK-NEXT: .LBB23_2: ; %true
-; CHECK-NEXT: s_mov_b32 s0, 42
-; CHECK-NEXT: s_branch .LBB23_3
-; CHECK-NEXT: .LBB23_3:
- %v1c = icmp ult i32 %v1, 12
- %v2c = icmp ugt i32 %v2, 34
- %c = and i1 %v1c, %v2c
- %ballot = call i64 @llvm.amdgcn.icmp.i64(i1 %c, i1 0, i32 32) ; ICMP_EQ == 32
- %ballot_eq_zero = icmp eq i64 %ballot, 0
- br i1 %ballot_eq_zero, label %true, label %false
-true:
- ret i32 42
-false:
- ret i32 33
-}
-
; Input that is not constant or direct result of a compare.
; Tests setting 0 to inactive lanes.
define amdgpu_ps void @non_cst_non_compare_input(ptr addrspace(1) %out, i32 %tid, i32 %cond) {
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
deleted file mode 100644
index 5352c7a79700b..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
+++ /dev/null
@@ -1,2456 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr="+wavefrontsize32" < %s | FileCheck -check-prefixes=SDAG-GFX11 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr="+wavefrontsize32" < %s | FileCheck -check-prefixes=SDAG-GFX10 %s
-
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr="+wavefrontsize32" < %s | FileCheck -check-prefixes=GISEL-GFX11 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 -mattr="+wavefrontsize32" < %s | FileCheck -check-prefixes=GISEL-GFX10 %s
-
-declare i32 @llvm.amdgcn.fcmp.f32(float, float, i32) #0
-declare i32 @llvm.amdgcn.fcmp.f64(double, double, i32) #0
-declare float @llvm.fabs.f32(float) #0
-
-declare i32 @llvm.amdgcn.fcmp.f16(half, half, i32) #0
-declare half @llvm.fabs.f16(half) #0
-
-define amdgpu_kernel void @v_fcmp_f32_oeq_with_fabs(ptr addrspace(1) %out, float %src, float %a) {
-; SDAG-GFX11-LABEL: v_fcmp_f32_oeq_with_fabs:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_eq_f32_e64 s2, s2, |s3|
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f32_oeq_with_fabs:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_eq_f32_e64 s2, s2, |s3|
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f32_oeq_with_fabs:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_eq_f32_e64 s2, s2, |s3|
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f32_oeq_with_fabs:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_eq_f32_e64 s2, s2, |s3|
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %temp = call float @llvm.fabs.f32(float %a)
- %result = call i32 @llvm.amdgcn.fcmp.f32(float %src, float %temp, i32 1)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f32_oeq_both_operands_with_fabs(ptr addrspace(1) %out, float %src, float %a) {
-; SDAG-GFX11-LABEL: v_fcmp_f32_oeq_both_operands_with_fabs:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_eq_f32_e64 s2, |s2|, |s3|
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f32_oeq_both_operands_with_fabs:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_eq_f32_e64 s2, |s2|, |s3|
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f32_oeq_both_operands_with_fabs:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_eq_f32_e64 s2, |s2|, |s3|
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f32_oeq_both_operands_with_fabs:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_eq_f32_e64 s2, |s2|, |s3|
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %temp = call float @llvm.fabs.f32(float %a)
- %src_input = call float @llvm.fabs.f32(float %src)
- %result = call i32 @llvm.amdgcn.fcmp.f32(float %src_input, float %temp, i32 1)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f32(ptr addrspace(1) %out, float %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f32:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f32:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f32:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: global_store_b32 v0, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f32:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: global_store_dword v0, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 -1)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f32_oeq(ptr addrspace(1) %out, float %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f32_oeq:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_eq_f32_e64 s2, 0x42c80000, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f32_oeq:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_eq_f32_e64 s2, 0x42c80000, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f32_oeq:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_eq_f32_e64 s2, 0x42c80000, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f32_oeq:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_eq_f32_e64 s2, 0x42c80000, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 1)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f32_one(ptr addrspace(1) %out, float %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f32_one:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_neq_f32_e64 s2, 0x42c80000, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f32_one:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_neq_f32_e64 s2, 0x42c80000, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f32_one:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_neq_f32_e64 s2, 0x42c80000, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f32_one:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_neq_f32_e64 s2, 0x42c80000, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 6)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f32_ogt(ptr addrspace(1) %out, float %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f32_ogt:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_lt_f32_e64 s2, 0x42c80000, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f32_ogt:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_lt_f32_e64 s2, 0x42c80000, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f32_ogt:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_lt_f32_e64 s2, 0x42c80000, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f32_ogt:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_lt_f32_e64 s2, 0x42c80000, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 2)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f32_oge(ptr addrspace(1) %out, float %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f32_oge:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_le_f32_e64 s2, 0x42c80000, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f32_oge:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_le_f32_e64 s2, 0x42c80000, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f32_oge:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_le_f32_e64 s2, 0x42c80000, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f32_oge:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_le_f32_e64 s2, 0x42c80000, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 3)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f32_olt(ptr addrspace(1) %out, float %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f32_olt:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_gt_f32_e64 s2, 0x42c80000, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f32_olt:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_gt_f32_e64 s2, 0x42c80000, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f32_olt:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_gt_f32_e64 s2, 0x42c80000, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f32_olt:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_gt_f32_e64 s2, 0x42c80000, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 4)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f32_ole(ptr addrspace(1) %out, float %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f32_ole:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_ge_f32_e64 s2, 0x42c80000, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f32_ole:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_ge_f32_e64 s2, 0x42c80000, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f32_ole:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_ge_f32_e64 s2, 0x42c80000, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f32_ole:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_ge_f32_e64 s2, 0x42c80000, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 5)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f32_o(ptr addrspace(1) %out, float %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f32_o:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_o_f32_e64 s2, 0x42c80000, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f32_o:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_o_f32_e64 s2, 0x42c80000, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f32_o:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_o_f32_e64 s2, 0x42c80000, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f32_o:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_o_f32_e64 s2, 0x42c80000, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 7)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f32_uo(ptr addrspace(1) %out, float %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f32_uo:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_u_f32_e64 s2, 0x42c80000, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f32_uo:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_u_f32_e64 s2, 0x42c80000, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f32_uo:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_u_f32_e64 s2, 0x42c80000, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f32_uo:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_u_f32_e64 s2, 0x42c80000, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 8)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f32_ueq(ptr addrspace(1) %out, float %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f32_ueq:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_nlg_f32_e64 s2, 0x42c80000, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f32_ueq:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_nlg_f32_e64 s2, 0x42c80000, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f32_ueq:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_nlg_f32_e64 s2, 0x42c80000, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f32_ueq:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_nlg_f32_e64 s2, 0x42c80000, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 9)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f32_une(ptr addrspace(1) %out, float %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f32_une:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_neq_f32_e64 s2, 0x42c80000, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f32_une:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_neq_f32_e64 s2, 0x42c80000, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f32_une:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_neq_f32_e64 s2, 0x42c80000, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f32_une:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_neq_f32_e64 s2, 0x42c80000, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 14)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f32_ugt(ptr addrspace(1) %out, float %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f32_ugt:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_nge_f32_e64 s2, 0x42c80000, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f32_ugt:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_nge_f32_e64 s2, 0x42c80000, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f32_ugt:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_nge_f32_e64 s2, 0x42c80000, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f32_ugt:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_nge_f32_e64 s2, 0x42c80000, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 10)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f32_uge(ptr addrspace(1) %out, float %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f32_uge:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_ngt_f32_e64 s2, 0x42c80000, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f32_uge:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_ngt_f32_e64 s2, 0x42c80000, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f32_uge:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_ngt_f32_e64 s2, 0x42c80000, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f32_uge:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_ngt_f32_e64 s2, 0x42c80000, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 11)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f32_ult(ptr addrspace(1) %out, float %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f32_ult:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_nle_f32_e64 s2, 0x42c80000, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f32_ult:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_nle_f32_e64 s2, 0x42c80000, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f32_ult:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_nle_f32_e64 s2, 0x42c80000, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f32_ult:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_nle_f32_e64 s2, 0x42c80000, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 12)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f32_ule(ptr addrspace(1) %out, float %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f32_ule:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_nlt_f32_e64 s2, 0x42c80000, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f32_ule:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_nlt_f32_e64 s2, 0x42c80000, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f32_ule:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_nlt_f32_e64 s2, 0x42c80000, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f32_ule:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_nlt_f32_e64 s2, 0x42c80000, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 13)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f64_oeq(ptr addrspace(1) %out, double %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f64_oeq:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_eq_f64_e64 s2, 0x40590000, s[2:3]
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f64_oeq:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_eq_f64_e64 s2, 0x40590000, s[2:3]
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f64_oeq:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_eq_f64_e64 s2, 0x40590000, s[2:3]
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f64_oeq:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_eq_f64_e64 s2, 0x40590000, s[2:3]
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 1)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f64_one(ptr addrspace(1) %out, double %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f64_one:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_neq_f64_e64 s2, 0x40590000, s[2:3]
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f64_one:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_neq_f64_e64 s2, 0x40590000, s[2:3]
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f64_one:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_neq_f64_e64 s2, 0x40590000, s[2:3]
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f64_one:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_neq_f64_e64 s2, 0x40590000, s[2:3]
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 6)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f64_ogt(ptr addrspace(1) %out, double %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f64_ogt:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_lt_f64_e64 s2, 0x40590000, s[2:3]
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f64_ogt:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_lt_f64_e64 s2, 0x40590000, s[2:3]
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f64_ogt:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_lt_f64_e64 s2, 0x40590000, s[2:3]
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f64_ogt:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_lt_f64_e64 s2, 0x40590000, s[2:3]
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 2)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f64_oge(ptr addrspace(1) %out, double %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f64_oge:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_le_f64_e64 s2, 0x40590000, s[2:3]
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f64_oge:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_le_f64_e64 s2, 0x40590000, s[2:3]
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f64_oge:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_le_f64_e64 s2, 0x40590000, s[2:3]
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f64_oge:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_le_f64_e64 s2, 0x40590000, s[2:3]
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 3)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f64_olt(ptr addrspace(1) %out, double %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f64_olt:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_gt_f64_e64 s2, 0x40590000, s[2:3]
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f64_olt:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_gt_f64_e64 s2, 0x40590000, s[2:3]
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f64_olt:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_gt_f64_e64 s2, 0x40590000, s[2:3]
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f64_olt:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_gt_f64_e64 s2, 0x40590000, s[2:3]
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 4)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f64_ole(ptr addrspace(1) %out, double %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f64_ole:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_ge_f64_e64 s2, 0x40590000, s[2:3]
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f64_ole:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_ge_f64_e64 s2, 0x40590000, s[2:3]
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f64_ole:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_ge_f64_e64 s2, 0x40590000, s[2:3]
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f64_ole:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_ge_f64_e64 s2, 0x40590000, s[2:3]
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 5)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f64_ueq(ptr addrspace(1) %out, double %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f64_ueq:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_nlg_f64_e64 s2, 0x40590000, s[2:3]
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f64_ueq:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_nlg_f64_e64 s2, 0x40590000, s[2:3]
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f64_ueq:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_nlg_f64_e64 s2, 0x40590000, s[2:3]
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f64_ueq:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_nlg_f64_e64 s2, 0x40590000, s[2:3]
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 9)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f64_o(ptr addrspace(1) %out, double %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f64_o:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_o_f64_e64 s2, 0x40590000, s[2:3]
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f64_o:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_o_f64_e64 s2, 0x40590000, s[2:3]
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f64_o:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_o_f64_e64 s2, 0x40590000, s[2:3]
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f64_o:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_o_f64_e64 s2, 0x40590000, s[2:3]
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 7)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f64_uo(ptr addrspace(1) %out, double %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f64_uo:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_u_f64_e64 s2, 0x40590000, s[2:3]
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f64_uo:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_u_f64_e64 s2, 0x40590000, s[2:3]
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f64_uo:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_u_f64_e64 s2, 0x40590000, s[2:3]
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f64_uo:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_u_f64_e64 s2, 0x40590000, s[2:3]
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 8)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f64_une(ptr addrspace(1) %out, double %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f64_une:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_neq_f64_e64 s2, 0x40590000, s[2:3]
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f64_une:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_neq_f64_e64 s2, 0x40590000, s[2:3]
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f64_une:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_neq_f64_e64 s2, 0x40590000, s[2:3]
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f64_une:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_neq_f64_e64 s2, 0x40590000, s[2:3]
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 14)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f64_ugt(ptr addrspace(1) %out, double %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f64_ugt:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_nge_f64_e64 s2, 0x40590000, s[2:3]
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f64_ugt:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_nge_f64_e64 s2, 0x40590000, s[2:3]
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f64_ugt:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_nge_f64_e64 s2, 0x40590000, s[2:3]
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f64_ugt:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_nge_f64_e64 s2, 0x40590000, s[2:3]
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 10)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f64_uge(ptr addrspace(1) %out, double %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f64_uge:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_ngt_f64_e64 s2, 0x40590000, s[2:3]
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f64_uge:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_ngt_f64_e64 s2, 0x40590000, s[2:3]
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f64_uge:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_ngt_f64_e64 s2, 0x40590000, s[2:3]
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f64_uge:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_ngt_f64_e64 s2, 0x40590000, s[2:3]
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 11)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f64_ult(ptr addrspace(1) %out, double %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f64_ult:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_nle_f64_e64 s2, 0x40590000, s[2:3]
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f64_ult:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_nle_f64_e64 s2, 0x40590000, s[2:3]
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f64_ult:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_nle_f64_e64 s2, 0x40590000, s[2:3]
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f64_ult:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_nle_f64_e64 s2, 0x40590000, s[2:3]
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 12)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f64_ule(ptr addrspace(1) %out, double %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f64_ule:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_nlt_f64_e64 s2, 0x40590000, s[2:3]
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f64_ule:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_nlt_f64_e64 s2, 0x40590000, s[2:3]
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f64_ule:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_nlt_f64_e64 s2, 0x40590000, s[2:3]
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f64_ule:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_nlt_f64_e64 s2, 0x40590000, s[2:3]
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 13)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-
-define amdgpu_kernel void @v_fcmp_f16_oeq_with_fabs(ptr addrspace(1) %out, half %src, half %a) {
-; SDAG-GFX11-LABEL: v_fcmp_f16_oeq_with_fabs:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: s_lshr_b32 s3, s2, 16
-; SDAG-GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_cmp_eq_f16_e64 s2, s2, |s3|
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f16_oeq_with_fabs:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: s_lshr_b32 s3, s2, 16
-; SDAG-GFX10-NEXT: v_cmp_eq_f16_e64 s2, s2, |s3|
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f16_oeq_with_fabs:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: s_lshr_b32 s3, s2, 16
-; GISEL-GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_cmp_eq_f16_e64 s2, s2, |s3|
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f16_oeq_with_fabs:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: s_lshr_b32 s3, s2, 16
-; GISEL-GFX10-NEXT: v_cmp_eq_f16_e64 s2, s2, |s3|
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %temp = call half @llvm.fabs.f16(half %a)
- %result = call i32 @llvm.amdgcn.fcmp.f16(half %src, half %temp, i32 1)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-
-define amdgpu_kernel void @v_fcmp_f16_oeq_both_operands_with_fabs(ptr addrspace(1) %out, half %src, half %a) {
-; SDAG-GFX11-LABEL: v_fcmp_f16_oeq_both_operands_with_fabs:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: s_lshr_b32 s3, s2, 16
-; SDAG-GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_cmp_eq_f16_e64 s2, |s2|, |s3|
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f16_oeq_both_operands_with_fabs:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: s_lshr_b32 s3, s2, 16
-; SDAG-GFX10-NEXT: v_cmp_eq_f16_e64 s2, |s2|, |s3|
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f16_oeq_both_operands_with_fabs:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: s_lshr_b32 s3, s2, 16
-; GISEL-GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_cmp_eq_f16_e64 s2, |s2|, |s3|
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f16_oeq_both_operands_with_fabs:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: s_lshr_b32 s3, s2, 16
-; GISEL-GFX10-NEXT: v_cmp_eq_f16_e64 s2, |s2|, |s3|
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %temp = call half @llvm.fabs.f16(half %a)
- %src_input = call half @llvm.fabs.f16(half %src)
- %result = call i32 @llvm.amdgcn.fcmp.f16(half %src_input, half %temp, i32 1)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f16(ptr addrspace(1) %out, half %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f16:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f16:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f16:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: global_store_b32 v0, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f16:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: global_store_dword v0, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 -1)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-
-define amdgpu_kernel void @v_fcmp_f16_oeq(ptr addrspace(1) %out, half %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f16_oeq:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_eq_f16_e64 s2, 0x5640, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f16_oeq:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_eq_f16_e64 s2, 0x5640, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f16_oeq:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_eq_f16_e64 s2, 0x5640, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f16_oeq:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_eq_f16_e64 s2, 0x5640, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 1)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-
-define amdgpu_kernel void @v_fcmp_f16_one(ptr addrspace(1) %out, half %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f16_one:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_neq_f16_e64 s2, 0x5640, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f16_one:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_neq_f16_e64 s2, 0x5640, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f16_one:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_neq_f16_e64 s2, 0x5640, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f16_one:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_neq_f16_e64 s2, 0x5640, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 6)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-
-define amdgpu_kernel void @v_fcmp_f16_ogt(ptr addrspace(1) %out, half %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f16_ogt:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_lt_f16_e64 s2, 0x5640, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f16_ogt:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_lt_f16_e64 s2, 0x5640, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f16_ogt:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_lt_f16_e64 s2, 0x5640, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f16_ogt:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_lt_f16_e64 s2, 0x5640, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 2)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-
-define amdgpu_kernel void @v_fcmp_f16_oge(ptr addrspace(1) %out, half %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f16_oge:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_le_f16_e64 s2, 0x5640, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f16_oge:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_le_f16_e64 s2, 0x5640, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f16_oge:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_le_f16_e64 s2, 0x5640, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f16_oge:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_le_f16_e64 s2, 0x5640, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 3)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-
-define amdgpu_kernel void @v_fcmp_f16_olt(ptr addrspace(1) %out, half %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f16_olt:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_gt_f16_e64 s2, 0x5640, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f16_olt:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_gt_f16_e64 s2, 0x5640, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f16_olt:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_gt_f16_e64 s2, 0x5640, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f16_olt:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_gt_f16_e64 s2, 0x5640, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 4)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-
-define amdgpu_kernel void @v_fcmp_f16_ole(ptr addrspace(1) %out, half %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f16_ole:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_ge_f16_e64 s2, 0x5640, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f16_ole:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_ge_f16_e64 s2, 0x5640, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f16_ole:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_ge_f16_e64 s2, 0x5640, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f16_ole:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_ge_f16_e64 s2, 0x5640, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 5)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-
-define amdgpu_kernel void @v_fcmp_f16_ueq(ptr addrspace(1) %out, half %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f16_ueq:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_nlg_f16_e64 s2, 0x5640, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f16_ueq:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_nlg_f16_e64 s2, 0x5640, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f16_ueq:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_nlg_f16_e64 s2, 0x5640, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f16_ueq:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_nlg_f16_e64 s2, 0x5640, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 9)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-
-define amdgpu_kernel void @v_fcmp_f16_une(ptr addrspace(1) %out, half %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f16_une:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_neq_f16_e64 s2, 0x5640, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f16_une:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_neq_f16_e64 s2, 0x5640, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f16_une:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_neq_f16_e64 s2, 0x5640, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f16_une:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_neq_f16_e64 s2, 0x5640, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 14)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-
-define amdgpu_kernel void @v_fcmp_f16_ugt(ptr addrspace(1) %out, half %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f16_ugt:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_nge_f16_e64 s2, 0x5640, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f16_ugt:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_nge_f16_e64 s2, 0x5640, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f16_ugt:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_nge_f16_e64 s2, 0x5640, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f16_ugt:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_nge_f16_e64 s2, 0x5640, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 10)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-
-define amdgpu_kernel void @v_fcmp_f16_uge(ptr addrspace(1) %out, half %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f16_uge:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_ngt_f16_e64 s2, 0x5640, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f16_uge:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_ngt_f16_e64 s2, 0x5640, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f16_uge:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_ngt_f16_e64 s2, 0x5640, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f16_uge:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_ngt_f16_e64 s2, 0x5640, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 11)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-
-define amdgpu_kernel void @v_fcmp_f16_ult(ptr addrspace(1) %out, half %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f16_ult:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_nle_f16_e64 s2, 0x5640, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f16_ult:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_nle_f16_e64 s2, 0x5640, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f16_ult:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_nle_f16_e64 s2, 0x5640, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f16_ult:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_nle_f16_e64 s2, 0x5640, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 12)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f16_o(ptr addrspace(1) %out, half %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f16_o:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_o_f16_e64 s2, 0x5640, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f16_o:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_o_f16_e64 s2, 0x5640, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f16_o:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_o_f16_e64 s2, 0x5640, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f16_o:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_o_f16_e64 s2, 0x5640, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 7)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f16_uo(ptr addrspace(1) %out, half %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f16_uo:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_u_f16_e64 s2, 0x5640, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f16_uo:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_u_f16_e64 s2, 0x5640, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f16_uo:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_u_f16_e64 s2, 0x5640, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f16_uo:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_u_f16_e64 s2, 0x5640, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 8)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f16_ule(ptr addrspace(1) %out, half %src) {
-; SDAG-GFX11-LABEL: v_fcmp_f16_ule:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_nlt_f16_e64 s2, 0x5640, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_fcmp_f16_ule:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_nlt_f16_e64 s2, 0x5640, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_fcmp_f16_ule:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_nlt_f16_e64 s2, 0x5640, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_fcmp_f16_ule:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_nlt_f16_e64 s2, 0x5640, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 13)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-attributes #0 = { nounwind readnone convergent }
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
deleted file mode 100644
index 102a9617e038f..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
+++ /dev/null
@@ -1,2903 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr="+wavefrontsize64" < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr="+wavefrontsize64" < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=VI-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=VI-GISEL %s
-
-declare i64 @llvm.amdgcn.fcmp.f32(float, float, i32) #0
-declare i64 @llvm.amdgcn.fcmp.f64(double, double, i32) #0
-declare float @llvm.fabs.f32(float) #0
-
-declare i64 @llvm.amdgcn.fcmp.f16(half, half, i32) #0
-declare half @llvm.fabs.f16(half) #0
-
-define amdgpu_kernel void @v_fcmp_f32_oeq_with_fabs(ptr addrspace(1) %out, float %src, float %a) {
-; GFX11-LABEL: v_fcmp_f32_oeq_with_fabs:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_eq_f32_e64 s[2:3], s2, |s3|
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-SDAG-LABEL: v_fcmp_f32_oeq_with_fabs:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s3
-; GFX9-SDAG-NEXT: v_cmp_eq_f32_e64 s[2:3], s2, |v0|
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-SDAG-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-SDAG-NEXT: s_endpgm
-;
-; GFX9-GISEL-LABEL: v_fcmp_f32_oeq_with_fabs:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-GISEL-NEXT: v_cmp_eq_f32_e64 s[2:3], v0, |s3|
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-GISEL-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f32_oeq_with_fabs:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s3
-; VI-SDAG-NEXT: v_cmp_eq_f32_e64 s[2:3], s2, |v0|
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f32_oeq_with_fabs:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_cmp_eq_f32_e64 s[2:3], v0, |s3|
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %temp = call float @llvm.fabs.f32(float %a)
- %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float %temp, i32 1)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f32_oeq_both_operands_with_fabs(ptr addrspace(1) %out, float %src, float %a) {
-; GFX11-LABEL: v_fcmp_f32_oeq_both_operands_with_fabs:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_eq_f32_e64 s[2:3], |s2|, |s3|
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-SDAG-LABEL: v_fcmp_f32_oeq_both_operands_with_fabs:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s3
-; GFX9-SDAG-NEXT: v_cmp_eq_f32_e64 s[2:3], |s2|, |v0|
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-SDAG-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-SDAG-NEXT: s_endpgm
-;
-; GFX9-GISEL-LABEL: v_fcmp_f32_oeq_both_operands_with_fabs:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-GISEL-NEXT: v_cmp_eq_f32_e64 s[2:3], |v0|, |s3|
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-GISEL-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f32_oeq_both_operands_with_fabs:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s3
-; VI-SDAG-NEXT: v_cmp_eq_f32_e64 s[2:3], |s2|, |v0|
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f32_oeq_both_operands_with_fabs:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_cmp_eq_f32_e64 s[2:3], |v0|, |s3|
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %temp = call float @llvm.fabs.f32(float %a)
- %src_input = call float @llvm.fabs.f32(float %src)
- %result = call i64 @llvm.amdgcn.fcmp.f32(float %src_input, float %temp, i32 1)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f32(ptr addrspace(1) %out, float %src) {
-; GFX11-SDAG-LABEL: v_fcmp_f32:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: v_fcmp_f32:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 0
-; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-NEXT: global_store_b64 v0, v[0:1], s[0:1]
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX9-SDAG-LABEL: v_fcmp_f32:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_endpgm
-;
-; GFX9-GISEL-LABEL: v_fcmp_f32:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-GISEL-NEXT: global_store_dwordx2 v0, v[0:1], s[0:1]
-; GFX9-GISEL-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f32:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f32:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
-; VI-GISEL-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 -1)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f32_oeq(ptr addrspace(1) %out, float %src) {
-; GFX11-LABEL: v_fcmp_f32_oeq:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_eq_f32_e64 s[2:3], 0x42c80000, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f32_oeq:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_eq_f32_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f32_oeq:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_eq_f32_e64 s[2:3], s2, v0
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f32_oeq:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_eq_f32_e64 s[2:3], s2, v0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 1)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f32_one(ptr addrspace(1) %out, float %src) {
-; GFX11-LABEL: v_fcmp_f32_one:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_neq_f32_e64 s[2:3], 0x42c80000, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f32_one:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_neq_f32_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f32_one:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_neq_f32_e64 s[2:3], s2, v0
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f32_one:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_neq_f32_e64 s[2:3], s2, v0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 6)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f32_ogt(ptr addrspace(1) %out, float %src) {
-; GFX11-LABEL: v_fcmp_f32_ogt:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_lt_f32_e64 s[2:3], 0x42c80000, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f32_ogt:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_gt_f32_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f32_ogt:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_gt_f32_e64 s[2:3], s2, v0
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f32_ogt:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_gt_f32_e64 s[2:3], s2, v0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 2)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f32_oge(ptr addrspace(1) %out, float %src) {
-; GFX11-LABEL: v_fcmp_f32_oge:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_le_f32_e64 s[2:3], 0x42c80000, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f32_oge:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ge_f32_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f32_oge:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_ge_f32_e64 s[2:3], s2, v0
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f32_oge:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_ge_f32_e64 s[2:3], s2, v0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 3)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f32_olt(ptr addrspace(1) %out, float %src) {
-; GFX11-LABEL: v_fcmp_f32_olt:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_gt_f32_e64 s[2:3], 0x42c80000, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f32_olt:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_lt_f32_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f32_olt:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_lt_f32_e64 s[2:3], s2, v0
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f32_olt:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], s2, v0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 4)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f32_ole(ptr addrspace(1) %out, float %src) {
-; GFX11-LABEL: v_fcmp_f32_ole:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_ge_f32_e64 s[2:3], 0x42c80000, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f32_ole:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_le_f32_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f32_ole:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_le_f32_e64 s[2:3], s2, v0
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f32_ole:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_le_f32_e64 s[2:3], s2, v0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 5)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f32_o(ptr addrspace(1) %out, float %src) {
-; GFX11-LABEL: v_fcmp_f32_o:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_o_f32_e64 s[2:3], 0x42c80000, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f32_o:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_o_f32_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f32_o:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_o_f32_e64 s[2:3], s2, v0
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f32_o:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_o_f32_e64 s[2:3], s2, v0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 7)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f32_uo(ptr addrspace(1) %out, float %src) {
-; GFX11-LABEL: v_fcmp_f32_uo:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_u_f32_e64 s[2:3], 0x42c80000, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f32_uo:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_u_f32_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f32_uo:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_u_f32_e64 s[2:3], s2, v0
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f32_uo:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_u_f32_e64 s[2:3], s2, v0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 8)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f32_ueq(ptr addrspace(1) %out, float %src) {
-; GFX11-LABEL: v_fcmp_f32_ueq:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_nlg_f32_e64 s[2:3], 0x42c80000, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f32_ueq:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_nlg_f32_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f32_ueq:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_nlg_f32_e64 s[2:3], s2, v0
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f32_ueq:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_nlg_f32_e64 s[2:3], s2, v0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 9)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f32_une(ptr addrspace(1) %out, float %src) {
-; GFX11-LABEL: v_fcmp_f32_une:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_neq_f32_e64 s[2:3], 0x42c80000, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f32_une:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_neq_f32_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f32_une:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_neq_f32_e64 s[2:3], s2, v0
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f32_une:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_neq_f32_e64 s[2:3], s2, v0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 14)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f32_ugt(ptr addrspace(1) %out, float %src) {
-; GFX11-LABEL: v_fcmp_f32_ugt:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_nge_f32_e64 s[2:3], 0x42c80000, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f32_ugt:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_nle_f32_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f32_ugt:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_nle_f32_e64 s[2:3], s2, v0
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f32_ugt:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_nle_f32_e64 s[2:3], s2, v0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 10)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f32_uge(ptr addrspace(1) %out, float %src) {
-; GFX11-LABEL: v_fcmp_f32_uge:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_ngt_f32_e64 s[2:3], 0x42c80000, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f32_uge:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_nlt_f32_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f32_uge:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_nlt_f32_e64 s[2:3], s2, v0
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f32_uge:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_nlt_f32_e64 s[2:3], s2, v0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 11)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f32_ult(ptr addrspace(1) %out, float %src) {
-; GFX11-LABEL: v_fcmp_f32_ult:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_nle_f32_e64 s[2:3], 0x42c80000, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f32_ult:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_nge_f32_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f32_ult:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_nge_f32_e64 s[2:3], s2, v0
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f32_ult:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_nge_f32_e64 s[2:3], s2, v0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 12)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f32_ule(ptr addrspace(1) %out, float %src) {
-; GFX11-LABEL: v_fcmp_f32_ule:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_nlt_f32_e64 s[2:3], 0x42c80000, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f32_ule:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ngt_f32_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f32_ule:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_ngt_f32_e64 s[2:3], s2, v0
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f32_ule:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x42c80000
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_ngt_f32_e64 s[2:3], s2, v0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 13)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f64_oeq(ptr addrspace(1) %out, double %src) {
-; GFX11-LABEL: v_fcmp_f64_oeq:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_eq_f64_e64 s[2:3], 0x40590000, s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f64_oeq:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_eq_f64_e64 s[2:3], s[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f64_oeq:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x40590000
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_eq_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f64_oeq:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40590000
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_eq_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 1)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f64_one(ptr addrspace(1) %out, double %src) {
-; GFX11-LABEL: v_fcmp_f64_one:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_neq_f64_e64 s[2:3], 0x40590000, s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f64_one:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_neq_f64_e64 s[2:3], s[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f64_one:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x40590000
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_neq_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f64_one:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40590000
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_neq_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 6)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f64_ogt(ptr addrspace(1) %out, double %src) {
-; GFX11-LABEL: v_fcmp_f64_ogt:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_lt_f64_e64 s[2:3], 0x40590000, s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f64_ogt:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_gt_f64_e64 s[2:3], s[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f64_ogt:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x40590000
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_gt_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f64_ogt:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40590000
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_gt_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 2)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f64_oge(ptr addrspace(1) %out, double %src) {
-; GFX11-LABEL: v_fcmp_f64_oge:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_le_f64_e64 s[2:3], 0x40590000, s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f64_oge:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ge_f64_e64 s[2:3], s[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f64_oge:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x40590000
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_ge_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f64_oge:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40590000
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_ge_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 3)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f64_olt(ptr addrspace(1) %out, double %src) {
-; GFX11-LABEL: v_fcmp_f64_olt:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_gt_f64_e64 s[2:3], 0x40590000, s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f64_olt:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_lt_f64_e64 s[2:3], s[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f64_olt:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x40590000
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_lt_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f64_olt:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40590000
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_lt_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 4)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f64_ole(ptr addrspace(1) %out, double %src) {
-; GFX11-LABEL: v_fcmp_f64_ole:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_ge_f64_e64 s[2:3], 0x40590000, s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f64_ole:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_le_f64_e64 s[2:3], s[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f64_ole:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x40590000
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_le_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f64_ole:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40590000
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_le_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 5)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f64_ueq(ptr addrspace(1) %out, double %src) {
-; GFX11-LABEL: v_fcmp_f64_ueq:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_nlg_f64_e64 s[2:3], 0x40590000, s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f64_ueq:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_nlg_f64_e64 s[2:3], s[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f64_ueq:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x40590000
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_nlg_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f64_ueq:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40590000
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_nlg_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 9)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f64_o(ptr addrspace(1) %out, double %src) {
-; GFX11-LABEL: v_fcmp_f64_o:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_o_f64_e64 s[2:3], 0x40590000, s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f64_o:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_o_f64_e64 s[2:3], s[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f64_o:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x40590000
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_o_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f64_o:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40590000
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_o_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 7)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f64_uo(ptr addrspace(1) %out, double %src) {
-; GFX11-LABEL: v_fcmp_f64_uo:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_u_f64_e64 s[2:3], 0x40590000, s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f64_uo:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_u_f64_e64 s[2:3], s[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f64_uo:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x40590000
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_u_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f64_uo:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40590000
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_u_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 8)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f64_une(ptr addrspace(1) %out, double %src) {
-; GFX11-LABEL: v_fcmp_f64_une:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_neq_f64_e64 s[2:3], 0x40590000, s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f64_une:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_neq_f64_e64 s[2:3], s[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f64_une:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x40590000
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_neq_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f64_une:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40590000
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_neq_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 14)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f64_ugt(ptr addrspace(1) %out, double %src) {
-; GFX11-LABEL: v_fcmp_f64_ugt:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_nge_f64_e64 s[2:3], 0x40590000, s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f64_ugt:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_nle_f64_e64 s[2:3], s[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f64_ugt:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x40590000
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_nle_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f64_ugt:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40590000
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_nle_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 10)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f64_uge(ptr addrspace(1) %out, double %src) {
-; GFX11-LABEL: v_fcmp_f64_uge:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_ngt_f64_e64 s[2:3], 0x40590000, s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f64_uge:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_nlt_f64_e64 s[2:3], s[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f64_uge:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x40590000
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_nlt_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f64_uge:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40590000
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 11)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f64_ult(ptr addrspace(1) %out, double %src) {
-; GFX11-LABEL: v_fcmp_f64_ult:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_nle_f64_e64 s[2:3], 0x40590000, s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f64_ult:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_nge_f64_e64 s[2:3], s[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f64_ult:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x40590000
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_nge_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f64_ult:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40590000
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_nge_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 12)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f64_ule(ptr addrspace(1) %out, double %src) {
-; GFX11-LABEL: v_fcmp_f64_ule:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_nlt_f64_e64 s[2:3], 0x40590000, s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f64_ule:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ngt_f64_e64 s[2:3], s[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f64_ule:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x40590000
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f64_ule:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40590000
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_ngt_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 13)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-
-define amdgpu_kernel void @v_fcmp_f16_oeq_with_fabs(ptr addrspace(1) %out, half %src, half %a) {
-; GFX11-LABEL: v_fcmp_f16_oeq_with_fabs:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_lshr_b32 s3, s2, 16
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cmp_eq_f16_e64 s[2:3], s2, |s3|
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-SDAG-LABEL: v_fcmp_f16_oeq_with_fabs:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-SDAG-NEXT: s_lshr_b32 s3, s2, 16
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s3
-; GFX9-SDAG-NEXT: v_cmp_eq_f16_e64 s[2:3], s2, |v0|
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-SDAG-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-SDAG-NEXT: s_endpgm
-;
-; GFX9-GISEL-LABEL: v_fcmp_f16_oeq_with_fabs:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-GISEL-NEXT: s_lshr_b32 s3, s2, 16
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-GISEL-NEXT: v_cmp_eq_f16_e64 s[2:3], v0, |s3|
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-GISEL-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f16_oeq_with_fabs:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: s_lshr_b32 s3, s2, 16
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s3
-; VI-SDAG-NEXT: v_cmp_eq_f16_e64 s[2:3], s2, |v0|
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f16_oeq_with_fabs:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: s_lshr_b32 s3, s2, 16
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_cmp_eq_f16_e64 s[2:3], v0, |s3|
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %temp = call half @llvm.fabs.f16(half %a)
- %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half %temp, i32 1)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-
-define amdgpu_kernel void @v_fcmp_f16_oeq_both_operands_with_fabs(ptr addrspace(1) %out, half %src, half %a) {
-; GFX11-LABEL: v_fcmp_f16_oeq_both_operands_with_fabs:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_lshr_b32 s3, s2, 16
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_cmp_eq_f16_e64 s[2:3], |s2|, |s3|
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-SDAG-LABEL: v_fcmp_f16_oeq_both_operands_with_fabs:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-SDAG-NEXT: s_lshr_b32 s3, s2, 16
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s3
-; GFX9-SDAG-NEXT: v_cmp_eq_f16_e64 s[2:3], |s2|, |v0|
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-SDAG-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-SDAG-NEXT: s_endpgm
-;
-; GFX9-GISEL-LABEL: v_fcmp_f16_oeq_both_operands_with_fabs:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-GISEL-NEXT: s_lshr_b32 s3, s2, 16
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-GISEL-NEXT: v_cmp_eq_f16_e64 s[2:3], |v0|, |s3|
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-GISEL-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f16_oeq_both_operands_with_fabs:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: s_lshr_b32 s3, s2, 16
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s3
-; VI-SDAG-NEXT: v_cmp_eq_f16_e64 s[2:3], |s2|, |v0|
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f16_oeq_both_operands_with_fabs:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: s_lshr_b32 s3, s2, 16
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_cmp_eq_f16_e64 s[2:3], |v0|, |s3|
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %temp = call half @llvm.fabs.f16(half %a)
- %src_input = call half @llvm.fabs.f16(half %src)
- %result = call i64 @llvm.amdgcn.fcmp.f16(half %src_input, half %temp, i32 1)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f16(ptr addrspace(1) %out, half %src) {
-; GFX11-SDAG-LABEL: v_fcmp_f16:
-; GFX11-SDAG: ; %bb.0:
-; GFX11-SDAG-NEXT: s_endpgm
-;
-; GFX11-GISEL-LABEL: v_fcmp_f16:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 0
-; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-NEXT: global_store_b64 v0, v[0:1], s[0:1]
-; GFX11-GISEL-NEXT: s_endpgm
-;
-; GFX9-SDAG-LABEL: v_fcmp_f16:
-; GFX9-SDAG: ; %bb.0:
-; GFX9-SDAG-NEXT: s_endpgm
-;
-; GFX9-GISEL-LABEL: v_fcmp_f16:
-; GFX9-GISEL: ; %bb.0:
-; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-GISEL-NEXT: global_store_dwordx2 v0, v[0:1], s[0:1]
-; GFX9-GISEL-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f16:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f16:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
-; VI-GISEL-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 -1)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-
-define amdgpu_kernel void @v_fcmp_f16_oeq(ptr addrspace(1) %out, half %src) {
-; GFX11-LABEL: v_fcmp_f16_oeq:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_eq_f16_e64 s[2:3], 0x5640, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f16_oeq:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_eq_f16_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f16_oeq:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x5640
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_eq_f16_e64 s[2:3], s2, v0
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f16_oeq:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x5640
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_eq_f16_e64 s[2:3], s2, v0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 1)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-
-define amdgpu_kernel void @v_fcmp_f16_one(ptr addrspace(1) %out, half %src) {
-; GFX11-LABEL: v_fcmp_f16_one:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_neq_f16_e64 s[2:3], 0x5640, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f16_one:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_neq_f16_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f16_one:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x5640
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_neq_f16_e64 s[2:3], s2, v0
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f16_one:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x5640
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_neq_f16_e64 s[2:3], s2, v0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 6)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-
-define amdgpu_kernel void @v_fcmp_f16_ogt(ptr addrspace(1) %out, half %src) {
-; GFX11-LABEL: v_fcmp_f16_ogt:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_lt_f16_e64 s[2:3], 0x5640, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f16_ogt:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_gt_f16_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f16_ogt:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x5640
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_gt_f16_e64 s[2:3], s2, v0
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f16_ogt:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x5640
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_gt_f16_e64 s[2:3], s2, v0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 2)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-
-define amdgpu_kernel void @v_fcmp_f16_oge(ptr addrspace(1) %out, half %src) {
-; GFX11-LABEL: v_fcmp_f16_oge:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_le_f16_e64 s[2:3], 0x5640, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f16_oge:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ge_f16_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f16_oge:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x5640
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_ge_f16_e64 s[2:3], s2, v0
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f16_oge:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x5640
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_ge_f16_e64 s[2:3], s2, v0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 3)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-
-define amdgpu_kernel void @v_fcmp_f16_olt(ptr addrspace(1) %out, half %src) {
-; GFX11-LABEL: v_fcmp_f16_olt:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_gt_f16_e64 s[2:3], 0x5640, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f16_olt:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_lt_f16_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f16_olt:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x5640
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_lt_f16_e64 s[2:3], s2, v0
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f16_olt:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x5640
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_lt_f16_e64 s[2:3], s2, v0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 4)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-
-define amdgpu_kernel void @v_fcmp_f16_ole(ptr addrspace(1) %out, half %src) {
-; GFX11-LABEL: v_fcmp_f16_ole:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_ge_f16_e64 s[2:3], 0x5640, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f16_ole:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_le_f16_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f16_ole:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x5640
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_le_f16_e64 s[2:3], s2, v0
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f16_ole:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x5640
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_le_f16_e64 s[2:3], s2, v0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 5)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-
-define amdgpu_kernel void @v_fcmp_f16_ueq(ptr addrspace(1) %out, half %src) {
-; GFX11-LABEL: v_fcmp_f16_ueq:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_nlg_f16_e64 s[2:3], 0x5640, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f16_ueq:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_nlg_f16_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f16_ueq:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x5640
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_nlg_f16_e64 s[2:3], s2, v0
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f16_ueq:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x5640
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_nlg_f16_e64 s[2:3], s2, v0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 9)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-
-define amdgpu_kernel void @v_fcmp_f16_une(ptr addrspace(1) %out, half %src) {
-; GFX11-LABEL: v_fcmp_f16_une:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_neq_f16_e64 s[2:3], 0x5640, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f16_une:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_neq_f16_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f16_une:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x5640
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_neq_f16_e64 s[2:3], s2, v0
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f16_une:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x5640
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_neq_f16_e64 s[2:3], s2, v0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 14)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-
-define amdgpu_kernel void @v_fcmp_f16_ugt(ptr addrspace(1) %out, half %src) {
-; GFX11-LABEL: v_fcmp_f16_ugt:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_nge_f16_e64 s[2:3], 0x5640, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f16_ugt:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_nle_f16_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f16_ugt:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x5640
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_nle_f16_e64 s[2:3], s2, v0
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f16_ugt:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x5640
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_nle_f16_e64 s[2:3], s2, v0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 10)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-
-define amdgpu_kernel void @v_fcmp_f16_uge(ptr addrspace(1) %out, half %src) {
-; GFX11-LABEL: v_fcmp_f16_uge:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_ngt_f16_e64 s[2:3], 0x5640, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f16_uge:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_nlt_f16_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f16_uge:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x5640
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_nlt_f16_e64 s[2:3], s2, v0
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f16_uge:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x5640
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_nlt_f16_e64 s[2:3], s2, v0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 11)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-
-define amdgpu_kernel void @v_fcmp_f16_ult(ptr addrspace(1) %out, half %src) {
-; GFX11-LABEL: v_fcmp_f16_ult:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_nle_f16_e64 s[2:3], 0x5640, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f16_ult:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_nge_f16_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f16_ult:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x5640
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_nge_f16_e64 s[2:3], s2, v0
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f16_ult:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x5640
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_nge_f16_e64 s[2:3], s2, v0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 12)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f16_o(ptr addrspace(1) %out, half %src) {
-; GFX11-LABEL: v_fcmp_f16_o:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_o_f16_e64 s[2:3], 0x5640, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f16_o:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_o_f16_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f16_o:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x5640
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_o_f16_e64 s[2:3], s2, v0
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f16_o:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x5640
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_o_f16_e64 s[2:3], s2, v0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 7)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f16_uo(ptr addrspace(1) %out, half %src) {
-; GFX11-LABEL: v_fcmp_f16_uo:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_u_f16_e64 s[2:3], 0x5640, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f16_uo:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_u_f16_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f16_uo:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x5640
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_u_f16_e64 s[2:3], s2, v0
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f16_uo:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x5640
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_u_f16_e64 s[2:3], s2, v0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 8)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_fcmp_f16_ule(ptr addrspace(1) %out, half %src) {
-; GFX11-LABEL: v_fcmp_f16_ule:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_nlt_f16_e64 s[2:3], 0x5640, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_fcmp_f16_ule:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ngt_f16_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; VI-SDAG-LABEL: v_fcmp_f16_ule:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x5640
-; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; VI-SDAG-NEXT: v_cmp_ngt_f16_e64 s[2:3], s2, v0
-; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, s2
-; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
-; VI-SDAG-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; VI-SDAG-NEXT: s_endpgm
-;
-; VI-GISEL-LABEL: v_fcmp_f16_ule:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x5640
-; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cmp_ngt_f16_e64 s[2:3], s2, v0
-; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-GISEL-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 13)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-attributes #0 = { nounwind readnone convergent }
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
deleted file mode 100644
index c7f9d8946bf01..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
+++ /dev/null
@@ -1,1717 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr="+wavefrontsize32" < %s | FileCheck -check-prefixes=GCN,GFX11,SDAG-GFX11 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr="+wavefrontsize32" < %s | FileCheck -check-prefixes=GCN,GFX10,SDAG-GFX10 %s
-
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr="+wavefrontsize32" < %s | FileCheck -check-prefixes=GCN,GFX11,GISEL-GFX11 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 -mattr="+wavefrontsize32" < %s | FileCheck -check-prefixes=GCN,GFX10,GISEL-GFX10 %s
-
-declare i32 @llvm.amdgcn.icmp.i32(i32, i32, i32) #0
-declare i32 @llvm.amdgcn.icmp.i64(i64, i64, i32) #0
-declare i32 @llvm.amdgcn.icmp.i16(i16, i16, i32) #0
-declare i32 @llvm.amdgcn.icmp.i1(i1, i1, i32) #0
-
-define amdgpu_kernel void @v_icmp_i32_eq(ptr addrspace(1) %out, i32 %src) {
-; SDAG-GFX11-LABEL: v_icmp_i32_eq:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0x64, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_i32_eq:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0x64, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_i32_eq:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0x64, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_i32_eq:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0x64, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 32)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i32(ptr addrspace(1) %out, i32 %src) {
-; SDAG-GFX11-LABEL: v_icmp_i32:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_i32:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_i32:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: global_store_b32 v0, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_i32:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: global_store_dword v0, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 30)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i32_ne(ptr addrspace(1) %out, i32 %src) {
-; SDAG-GFX11-LABEL: v_icmp_i32_ne:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_ne_u32_e64 s2, 0x64, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_i32_ne:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_ne_u32_e64 s2, 0x64, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_i32_ne:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_ne_u32_e64 s2, 0x64, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_i32_ne:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_ne_u32_e64 s2, 0x64, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 33)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i32_ugt(ptr addrspace(1) %out, i32 %src) {
-; SDAG-GFX11-LABEL: v_icmp_i32_ugt:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_lt_u32_e64 s2, 0x64, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_i32_ugt:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_lt_u32_e64 s2, 0x64, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_i32_ugt:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_lt_u32_e64 s2, 0x64, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_i32_ugt:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_lt_u32_e64 s2, 0x64, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 34)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i32_uge(ptr addrspace(1) %out, i32 %src) {
-; SDAG-GFX11-LABEL: v_icmp_i32_uge:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_le_u32_e64 s2, 0x64, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_i32_uge:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_le_u32_e64 s2, 0x64, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_i32_uge:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_le_u32_e64 s2, 0x64, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_i32_uge:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_le_u32_e64 s2, 0x64, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 35)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i32_ult(ptr addrspace(1) %out, i32 %src) {
-; SDAG-GFX11-LABEL: v_icmp_i32_ult:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_gt_u32_e64 s2, 0x64, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_i32_ult:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_gt_u32_e64 s2, 0x64, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_i32_ult:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_gt_u32_e64 s2, 0x64, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_i32_ult:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_gt_u32_e64 s2, 0x64, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 36)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i32_ule(ptr addrspace(1) %out, i32 %src) {
-; SDAG-GFX11-LABEL: v_icmp_i32_ule:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_ge_u32_e64 s2, 0x64, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_i32_ule:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_ge_u32_e64 s2, 0x64, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_i32_ule:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_ge_u32_e64 s2, 0x64, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_i32_ule:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_ge_u32_e64 s2, 0x64, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 37)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i32_sgt(ptr addrspace(1) %out, i32 %src) #1 {
-; SDAG-GFX11-LABEL: v_icmp_i32_sgt:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_lt_i32_e64 s2, 0x64, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_i32_sgt:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_lt_i32_e64 s2, 0x64, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_i32_sgt:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_lt_i32_e64 s2, 0x64, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_i32_sgt:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_lt_i32_e64 s2, 0x64, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 38)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i32_sge(ptr addrspace(1) %out, i32 %src) {
-; SDAG-GFX11-LABEL: v_icmp_i32_sge:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_le_i32_e64 s2, 0x64, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_i32_sge:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_le_i32_e64 s2, 0x64, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_i32_sge:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_le_i32_e64 s2, 0x64, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_i32_sge:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_le_i32_e64 s2, 0x64, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 39)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i32_slt(ptr addrspace(1) %out, i32 %src) {
-; SDAG-GFX11-LABEL: v_icmp_i32_slt:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_gt_i32_e64 s2, 0x64, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_i32_slt:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_gt_i32_e64 s2, 0x64, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_i32_slt:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_gt_i32_e64 s2, 0x64, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_i32_slt:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_gt_i32_e64 s2, 0x64, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 40)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i32_sle(ptr addrspace(1) %out, i32 %src) {
-; SDAG-GFX11-LABEL: v_icmp_i32_sle:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_ge_i32_e64 s2, 0x64, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_i32_sle:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_ge_i32_e64 s2, 0x64, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_i32_sle:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_ge_i32_e64 s2, 0x64, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_i32_sle:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_ge_i32_e64 s2, 0x64, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 41)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i64_eq(ptr addrspace(1) %out, i64 %src) {
-; SDAG-GFX11-LABEL: v_icmp_i64_eq:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_eq_u64_e64 s2, 0x64, s[2:3]
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_i64_eq:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_eq_u64_e64 s2, 0x64, s[2:3]
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_i64_eq:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_eq_u64_e64 s2, 0x64, s[2:3]
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_i64_eq:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_eq_u64_e64 s2, 0x64, s[2:3]
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 32)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i64_ne(ptr addrspace(1) %out, i64 %src) {
-; SDAG-GFX11-LABEL: v_icmp_i64_ne:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_ne_u64_e64 s2, 0x64, s[2:3]
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_i64_ne:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_ne_u64_e64 s2, 0x64, s[2:3]
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_i64_ne:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_ne_u64_e64 s2, 0x64, s[2:3]
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_i64_ne:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_ne_u64_e64 s2, 0x64, s[2:3]
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 33)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_u64_ugt(ptr addrspace(1) %out, i64 %src) {
-; SDAG-GFX11-LABEL: v_icmp_u64_ugt:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_lt_u64_e64 s2, 0x64, s[2:3]
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_u64_ugt:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_lt_u64_e64 s2, 0x64, s[2:3]
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_u64_ugt:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_lt_u64_e64 s2, 0x64, s[2:3]
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_u64_ugt:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_lt_u64_e64 s2, 0x64, s[2:3]
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 34)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_u64_uge(ptr addrspace(1) %out, i64 %src) {
-; SDAG-GFX11-LABEL: v_icmp_u64_uge:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_le_u64_e64 s2, 0x64, s[2:3]
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_u64_uge:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_le_u64_e64 s2, 0x64, s[2:3]
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_u64_uge:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_le_u64_e64 s2, 0x64, s[2:3]
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_u64_uge:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_le_u64_e64 s2, 0x64, s[2:3]
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 35)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_u64_ult(ptr addrspace(1) %out, i64 %src) {
-; SDAG-GFX11-LABEL: v_icmp_u64_ult:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_gt_u64_e64 s2, 0x64, s[2:3]
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_u64_ult:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_gt_u64_e64 s2, 0x64, s[2:3]
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_u64_ult:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_gt_u64_e64 s2, 0x64, s[2:3]
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_u64_ult:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_gt_u64_e64 s2, 0x64, s[2:3]
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 36)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_u64_ule(ptr addrspace(1) %out, i64 %src) {
-; SDAG-GFX11-LABEL: v_icmp_u64_ule:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_ge_u64_e64 s2, 0x64, s[2:3]
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_u64_ule:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_ge_u64_e64 s2, 0x64, s[2:3]
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_u64_ule:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_ge_u64_e64 s2, 0x64, s[2:3]
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_u64_ule:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_ge_u64_e64 s2, 0x64, s[2:3]
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 37)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i64_sgt(ptr addrspace(1) %out, i64 %src) {
-; SDAG-GFX11-LABEL: v_icmp_i64_sgt:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_lt_i64_e64 s2, 0x64, s[2:3]
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_i64_sgt:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_lt_i64_e64 s2, 0x64, s[2:3]
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_i64_sgt:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_lt_i64_e64 s2, 0x64, s[2:3]
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_i64_sgt:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_lt_i64_e64 s2, 0x64, s[2:3]
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 38)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i64_sge(ptr addrspace(1) %out, i64 %src) {
-; SDAG-GFX11-LABEL: v_icmp_i64_sge:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_le_i64_e64 s2, 0x64, s[2:3]
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_i64_sge:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_le_i64_e64 s2, 0x64, s[2:3]
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_i64_sge:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_le_i64_e64 s2, 0x64, s[2:3]
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_i64_sge:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_le_i64_e64 s2, 0x64, s[2:3]
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 39)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i64_slt(ptr addrspace(1) %out, i64 %src) {
-; SDAG-GFX11-LABEL: v_icmp_i64_slt:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_gt_i64_e64 s2, 0x64, s[2:3]
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_i64_slt:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_gt_i64_e64 s2, 0x64, s[2:3]
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_i64_slt:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_gt_i64_e64 s2, 0x64, s[2:3]
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_i64_slt:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_gt_i64_e64 s2, 0x64, s[2:3]
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 40)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i64_sle(ptr addrspace(1) %out, i64 %src) {
-; SDAG-GFX11-LABEL: v_icmp_i64_sle:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_ge_i64_e64 s2, 0x64, s[2:3]
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_i64_sle:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_ge_i64_e64 s2, 0x64, s[2:3]
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_i64_sle:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_ge_i64_e64 s2, 0x64, s[2:3]
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_i64_sle:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_ge_i64_e64 s2, 0x64, s[2:3]
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 41)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i16_eq(ptr addrspace(1) %out, i16 %src) {
-; SDAG-GFX11-LABEL: v_icmp_i16_eq:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_eq_u16_e64 s2, 0x64, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_i16_eq:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_eq_u16_e64 s2, 0x64, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_i16_eq:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_eq_u16_e64 s2, 0x64, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_i16_eq:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_eq_u16_e64 s2, 0x64, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 32)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i16(ptr addrspace(1) %out, i16 %src) {
-; SDAG-GFX11-LABEL: v_icmp_i16:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_i16:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_i16:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: global_store_b32 v0, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_i16:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: global_store_dword v0, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 30)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i16_ne(ptr addrspace(1) %out, i16 %src) {
-; SDAG-GFX11-LABEL: v_icmp_i16_ne:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_ne_u16_e64 s2, 0x64, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_i16_ne:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_ne_u16_e64 s2, 0x64, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_i16_ne:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_ne_u16_e64 s2, 0x64, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_i16_ne:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_ne_u16_e64 s2, 0x64, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 33)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i16_ugt(ptr addrspace(1) %out, i16 %src) {
-; SDAG-GFX11-LABEL: v_icmp_i16_ugt:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_lt_u16_e64 s2, 0x64, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_i16_ugt:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_lt_u16_e64 s2, 0x64, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_i16_ugt:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_lt_u16_e64 s2, 0x64, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_i16_ugt:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_lt_u16_e64 s2, 0x64, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 34)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i16_uge(ptr addrspace(1) %out, i16 %src) {
-; SDAG-GFX11-LABEL: v_icmp_i16_uge:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_le_u16_e64 s2, 0x64, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_i16_uge:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_le_u16_e64 s2, 0x64, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_i16_uge:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_le_u16_e64 s2, 0x64, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_i16_uge:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_le_u16_e64 s2, 0x64, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 35)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i16_ult(ptr addrspace(1) %out, i16 %src) {
-; SDAG-GFX11-LABEL: v_icmp_i16_ult:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_gt_u16_e64 s2, 0x64, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_i16_ult:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_gt_u16_e64 s2, 0x64, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_i16_ult:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_gt_u16_e64 s2, 0x64, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_i16_ult:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_gt_u16_e64 s2, 0x64, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 36)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i16_ule(ptr addrspace(1) %out, i16 %src) {
-; SDAG-GFX11-LABEL: v_icmp_i16_ule:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_ge_u16_e64 s2, 0x64, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_i16_ule:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_ge_u16_e64 s2, 0x64, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_i16_ule:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_ge_u16_e64 s2, 0x64, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_i16_ule:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_ge_u16_e64 s2, 0x64, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 37)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i16_sgt(ptr addrspace(1) %out, i16 %src) #1 {
-; SDAG-GFX11-LABEL: v_icmp_i16_sgt:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_lt_i16_e64 s2, 0x64, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_i16_sgt:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_lt_i16_e64 s2, 0x64, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_i16_sgt:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_lt_i16_e64 s2, 0x64, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_i16_sgt:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_lt_i16_e64 s2, 0x64, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 38)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i16_sge(ptr addrspace(1) %out, i16 %src) {
-; SDAG-GFX11-LABEL: v_icmp_i16_sge:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_le_i16_e64 s2, 0x64, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_i16_sge:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_le_i16_e64 s2, 0x64, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_i16_sge:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_le_i16_e64 s2, 0x64, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_i16_sge:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_le_i16_e64 s2, 0x64, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 39)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i16_slt(ptr addrspace(1) %out, i16 %src) {
-; SDAG-GFX11-LABEL: v_icmp_i16_slt:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_gt_i16_e64 s2, 0x64, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_i16_slt:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_gt_i16_e64 s2, 0x64, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_i16_slt:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_gt_i16_e64 s2, 0x64, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_i16_slt:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_gt_i16_e64 s2, 0x64, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 40)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i16_sle(ptr addrspace(1) %out, i16 %src) {
-; SDAG-GFX11-LABEL: v_icmp_i16_sle:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_clause 0x1
-; SDAG-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: v_cmp_ge_i16_e64 s2, 0x64, s2
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_i16_sle:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_clause 0x1
-; SDAG-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: v_cmp_ge_i16_e64 s2, 0x64, s2
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_i16_sle:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_clause 0x1
-; GISEL-GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: v_cmp_ge_i16_e64 s2, 0x64, s2
-; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_i16_sle:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_clause 0x1
-; GISEL-GFX10-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: v_cmp_ge_i16_e64 s2, 0x64, s2
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 41)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i1_ne0(ptr addrspace(1) %out, i32 %a, i32 %b) {
-; SDAG-GFX11-LABEL: v_icmp_i1_ne0:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: s_cmp_gt_u32 s2, 1
-; SDAG-GFX11-NEXT: s_cselect_b32 s2, -1, 0
-; SDAG-GFX11-NEXT: s_cmp_gt_u32 s3, 2
-; SDAG-GFX11-NEXT: s_cselect_b32 s3, -1, 0
-; SDAG-GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; SDAG-GFX11-NEXT: s_and_b32 s2, s2, s3
-; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: v_icmp_i1_ne0:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
-; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX10-NEXT: s_cmp_gt_u32 s2, 1
-; SDAG-GFX10-NEXT: s_cselect_b32 s2, -1, 0
-; SDAG-GFX10-NEXT: s_cmp_gt_u32 s3, 2
-; SDAG-GFX10-NEXT: s_cselect_b32 s3, -1, 0
-; SDAG-GFX10-NEXT: s_and_b32 s2, s2, s3
-; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
-; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_i1_ne0:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: s_cmp_gt_u32 s2, 1
-; GISEL-GFX11-NEXT: s_cselect_b32 s2, 1, 0
-; GISEL-GFX11-NEXT: s_cmp_gt_u32 s3, 2
-; GISEL-GFX11-NEXT: s_cselect_b32 s3, 1, 0
-; GISEL-GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GISEL-GFX11-NEXT: s_and_b32 s2, s2, s3
-; GISEL-GFX11-NEXT: s_cmp_lg_u32 s2, 0
-; GISEL-GFX11-NEXT: s_cselect_b32 s2, exec_lo, 0
-; GISEL-GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: v_icmp_i1_ne0:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX10-NEXT: s_cmp_gt_u32 s2, 1
-; GISEL-GFX10-NEXT: s_cselect_b32 s2, 1, 0
-; GISEL-GFX10-NEXT: s_cmp_gt_u32 s3, 2
-; GISEL-GFX10-NEXT: s_cselect_b32 s3, 1, 0
-; GISEL-GFX10-NEXT: s_and_b32 s2, s2, s3
-; GISEL-GFX10-NEXT: s_cmp_lg_u32 s2, 0
-; GISEL-GFX10-NEXT: s_cselect_b32 s2, exec_lo, 0
-; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
-; GISEL-GFX10-NEXT: s_endpgm
- %c0 = icmp ugt i32 %a, 1
- %c1 = icmp ugt i32 %b, 2
- %src = and i1 %c0, %c1
- %result = call i32 @llvm.amdgcn.icmp.i1(i1 %src, i1 false, i32 33)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_ps i32 @v_icmp_i1_ne0_divergent(i32 %a) {
-; GCN-LABEL: v_icmp_i1_ne0_divergent:
-; GCN: ; %bb.0:
-; GCN-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GCN-NEXT: ; return to shader part epilog
- %cond = icmp eq i32 %a, 0
- %result = call i32 @llvm.amdgcn.icmp.i1(i1 %cond, i1 false, i32 33)
- ret i32 %result
-}
-
-define amdgpu_ps void @test_intr_icmp_i32_invalid_cc(ptr addrspace(1) %out, i32 %src) {
-; SDAG-GFX11-LABEL: test_intr_icmp_i32_invalid_cc:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-GFX10-LABEL: test_intr_icmp_i32_invalid_cc:
-; SDAG-GFX10: ; %bb.0:
-; SDAG-GFX10-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: test_intr_icmp_i32_invalid_cc:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: global_store_b32 v[0:1], v0, off
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-GFX10-LABEL: test_intr_icmp_i32_invalid_cc:
-; GISEL-GFX10: ; %bb.0:
-; GISEL-GFX10-NEXT: global_store_dword v[0:1], v0, off
-; GISEL-GFX10-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 9999)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-attributes #0 = { nounwind readnone convergent }
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GFX10: {{.*}}
-; GFX11: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
deleted file mode 100644
index b7c138d4bed09..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
+++ /dev/null
@@ -1,2072 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr="+wavefrontsize64" < %s | FileCheck -check-prefixes=GCN,GFX11,SDAG-GFX11 %s
-; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,VI,SDAG-VI %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,SDAG-GFX9 %s
-
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr="+wavefrontsize64" < %s | FileCheck -check-prefixes=GCN,GFX11,GISEL-GFX11 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,VI,GISEL-VI %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GISEL-GFX9 %s
-
-declare i64 @llvm.amdgcn.icmp.i32(i32, i32, i32) #0
-declare i64 @llvm.amdgcn.icmp.i64(i64, i64, i32) #0
-declare i64 @llvm.amdgcn.icmp.i16(i16, i16, i32) #0
-declare i64 @llvm.amdgcn.icmp.i1(i1, i1, i32) #0
-
-define amdgpu_kernel void @v_icmp_i32_eq(ptr addrspace(1) %out, i32 %src) {
-; GFX11-LABEL: v_icmp_i32_eq:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_eq_u32_e64 s[2:3], 0x64, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_i32_eq:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-VI-NEXT: v_cmp_eq_u32_e64 s[2:3], s2, v0
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
-; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
-; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; SDAG-VI-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_icmp_i32_eq:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_i32_eq:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: v_cmp_eq_u32_e64 s[2:3], s2, v0
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
-; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
-; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 32)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i32(ptr addrspace(1) %out, i32 %src) {
-; SDAG-GFX11-LABEL: v_icmp_i32:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_i32:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_endpgm
-;
-; SDAG-GFX9-LABEL: v_icmp_i32:
-; SDAG-GFX9: ; %bb.0:
-; SDAG-GFX9-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_i32:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: global_store_b64 v0, v[0:1], s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_i32:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s1
-; GISEL-VI-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
-;
-; GISEL-GFX9-LABEL: v_icmp_i32:
-; GISEL-GFX9: ; %bb.0:
-; GISEL-GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GISEL-GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX9-NEXT: global_store_dwordx2 v0, v[0:1], s[0:1]
-; GISEL-GFX9-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 30)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i32_ne(ptr addrspace(1) %out, i32 %src) {
-; GFX11-LABEL: v_icmp_i32_ne:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_ne_u32_e64 s[2:3], 0x64, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_i32_ne:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-VI-NEXT: v_cmp_ne_u32_e64 s[2:3], s2, v0
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
-; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
-; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; SDAG-VI-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_icmp_i32_ne:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_i32_ne:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: v_cmp_ne_u32_e64 s[2:3], s2, v0
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
-; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
-; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 33)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i32_ugt(ptr addrspace(1) %out, i32 %src) {
-; GFX11-LABEL: v_icmp_i32_ugt:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_lt_u32_e64 s[2:3], 0x64, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_i32_ugt:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-VI-NEXT: v_cmp_gt_u32_e64 s[2:3], s2, v0
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
-; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
-; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; SDAG-VI-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_icmp_i32_ugt:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_gt_u32_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_i32_ugt:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: v_cmp_gt_u32_e64 s[2:3], s2, v0
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
-; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
-; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 34)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i32_uge(ptr addrspace(1) %out, i32 %src) {
-; GFX11-LABEL: v_icmp_i32_uge:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_le_u32_e64 s[2:3], 0x64, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_i32_uge:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-VI-NEXT: v_cmp_ge_u32_e64 s[2:3], s2, v0
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
-; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
-; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; SDAG-VI-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_icmp_i32_uge:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ge_u32_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_i32_uge:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: v_cmp_ge_u32_e64 s[2:3], s2, v0
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
-; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
-; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 35)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i32_ult(ptr addrspace(1) %out, i32 %src) {
-; GFX11-LABEL: v_icmp_i32_ult:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_gt_u32_e64 s[2:3], 0x64, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_i32_ult:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-VI-NEXT: v_cmp_lt_u32_e64 s[2:3], s2, v0
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
-; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
-; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; SDAG-VI-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_icmp_i32_ult:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_lt_u32_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_i32_ult:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: v_cmp_lt_u32_e64 s[2:3], s2, v0
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
-; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
-; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 36)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i32_ule(ptr addrspace(1) %out, i32 %src) {
-; GFX11-LABEL: v_icmp_i32_ule:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_ge_u32_e64 s[2:3], 0x64, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_i32_ule:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-VI-NEXT: v_cmp_le_u32_e64 s[2:3], s2, v0
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
-; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
-; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; SDAG-VI-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_icmp_i32_ule:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_le_u32_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_i32_ule:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: v_cmp_le_u32_e64 s[2:3], s2, v0
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
-; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
-; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 37)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i32_sgt(ptr addrspace(1) %out, i32 %src) #1 {
-; GFX11-LABEL: v_icmp_i32_sgt:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_lt_i32_e64 s[2:3], 0x64, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_i32_sgt:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-VI-NEXT: v_cmp_gt_i32_e64 s[2:3], s2, v0
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
-; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
-; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; SDAG-VI-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_icmp_i32_sgt:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_gt_i32_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_i32_sgt:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: v_cmp_gt_i32_e64 s[2:3], s2, v0
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
-; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
-; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 38)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i32_sge(ptr addrspace(1) %out, i32 %src) {
-; GFX11-LABEL: v_icmp_i32_sge:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_le_i32_e64 s[2:3], 0x64, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_i32_sge:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-VI-NEXT: v_cmp_ge_i32_e64 s[2:3], s2, v0
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
-; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
-; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; SDAG-VI-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_icmp_i32_sge:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ge_i32_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_i32_sge:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: v_cmp_ge_i32_e64 s[2:3], s2, v0
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
-; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
-; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 39)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i32_slt(ptr addrspace(1) %out, i32 %src) {
-; GFX11-LABEL: v_icmp_i32_slt:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_gt_i32_e64 s[2:3], 0x64, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_i32_slt:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-VI-NEXT: v_cmp_lt_i32_e64 s[2:3], s2, v0
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
-; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
-; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; SDAG-VI-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_icmp_i32_slt:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_lt_i32_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_i32_slt:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: v_cmp_lt_i32_e64 s[2:3], s2, v0
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
-; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
-; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 40)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i32_sle(ptr addrspace(1) %out, i32 %src) {
-; GFX11-LABEL: v_icmp_i32_sle:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_ge_i32_e64 s[2:3], 0x64, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_i32_sle:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-VI-NEXT: v_cmp_le_i32_e64 s[2:3], s2, v0
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
-; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
-; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; SDAG-VI-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_icmp_i32_sle:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_le_i32_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_i32_sle:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: v_cmp_le_i32_e64 s[2:3], s2, v0
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
-; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
-; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 41)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i64_eq(ptr addrspace(1) %out, i64 %src) {
-; GFX11-LABEL: v_icmp_i64_eq:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_eq_u64_e64 s[2:3], 0x64, s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_i64_eq:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0
-; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-VI-NEXT: v_cmp_eq_u64_e64 s[2:3], s[2:3], v[0:1]
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v3, s1
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, s3
-; SDAG-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; SDAG-VI-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_icmp_i64_eq:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
-; GFX9-NEXT: v_mov_b32_e32 v1, 0
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_eq_u64_e64 s[2:3], s[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_i64_eq:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: v_cmp_eq_u64_e64 s[2:3], s[2:3], v[0:1]
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
-; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 32)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i64_ne(ptr addrspace(1) %out, i64 %src) {
-; GFX11-LABEL: v_icmp_i64_ne:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_ne_u64_e64 s[2:3], 0x64, s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_i64_ne:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0
-; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-VI-NEXT: v_cmp_ne_u64_e64 s[2:3], s[2:3], v[0:1]
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v3, s1
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, s3
-; SDAG-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; SDAG-VI-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_icmp_i64_ne:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
-; GFX9-NEXT: v_mov_b32_e32 v1, 0
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u64_e64 s[2:3], s[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_i64_ne:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: v_cmp_ne_u64_e64 s[2:3], s[2:3], v[0:1]
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
-; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 33)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_u64_ugt(ptr addrspace(1) %out, i64 %src) {
-; GFX11-LABEL: v_icmp_u64_ugt:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_lt_u64_e64 s[2:3], 0x64, s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_u64_ugt:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0
-; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-VI-NEXT: v_cmp_gt_u64_e64 s[2:3], s[2:3], v[0:1]
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v3, s1
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, s3
-; SDAG-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; SDAG-VI-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_icmp_u64_ugt:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
-; GFX9-NEXT: v_mov_b32_e32 v1, 0
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_gt_u64_e64 s[2:3], s[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_u64_ugt:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: v_cmp_gt_u64_e64 s[2:3], s[2:3], v[0:1]
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
-; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 34)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_u64_uge(ptr addrspace(1) %out, i64 %src) {
-; GFX11-LABEL: v_icmp_u64_uge:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_le_u64_e64 s[2:3], 0x64, s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_u64_uge:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0
-; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-VI-NEXT: v_cmp_ge_u64_e64 s[2:3], s[2:3], v[0:1]
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v3, s1
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, s3
-; SDAG-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; SDAG-VI-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_icmp_u64_uge:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
-; GFX9-NEXT: v_mov_b32_e32 v1, 0
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ge_u64_e64 s[2:3], s[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_u64_uge:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: v_cmp_ge_u64_e64 s[2:3], s[2:3], v[0:1]
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
-; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 35)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_u64_ult(ptr addrspace(1) %out, i64 %src) {
-; GFX11-LABEL: v_icmp_u64_ult:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_gt_u64_e64 s[2:3], 0x64, s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_u64_ult:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0
-; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-VI-NEXT: v_cmp_lt_u64_e64 s[2:3], s[2:3], v[0:1]
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v3, s1
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, s3
-; SDAG-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; SDAG-VI-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_icmp_u64_ult:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
-; GFX9-NEXT: v_mov_b32_e32 v1, 0
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_lt_u64_e64 s[2:3], s[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_u64_ult:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: v_cmp_lt_u64_e64 s[2:3], s[2:3], v[0:1]
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
-; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 36)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_u64_ule(ptr addrspace(1) %out, i64 %src) {
-; GFX11-LABEL: v_icmp_u64_ule:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_ge_u64_e64 s[2:3], 0x64, s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_u64_ule:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0
-; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-VI-NEXT: v_cmp_le_u64_e64 s[2:3], s[2:3], v[0:1]
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v3, s1
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, s3
-; SDAG-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; SDAG-VI-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_icmp_u64_ule:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
-; GFX9-NEXT: v_mov_b32_e32 v1, 0
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_le_u64_e64 s[2:3], s[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_u64_ule:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: v_cmp_le_u64_e64 s[2:3], s[2:3], v[0:1]
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
-; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 37)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i64_sgt(ptr addrspace(1) %out, i64 %src) {
-; GFX11-LABEL: v_icmp_i64_sgt:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_lt_i64_e64 s[2:3], 0x64, s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_i64_sgt:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0
-; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-VI-NEXT: v_cmp_gt_i64_e64 s[2:3], s[2:3], v[0:1]
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v3, s1
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, s3
-; SDAG-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; SDAG-VI-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_icmp_i64_sgt:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
-; GFX9-NEXT: v_mov_b32_e32 v1, 0
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_gt_i64_e64 s[2:3], s[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_i64_sgt:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: v_cmp_gt_i64_e64 s[2:3], s[2:3], v[0:1]
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
-; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 38)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i64_sge(ptr addrspace(1) %out, i64 %src) {
-; GFX11-LABEL: v_icmp_i64_sge:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_le_i64_e64 s[2:3], 0x64, s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_i64_sge:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0
-; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-VI-NEXT: v_cmp_ge_i64_e64 s[2:3], s[2:3], v[0:1]
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v3, s1
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, s3
-; SDAG-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; SDAG-VI-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_icmp_i64_sge:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
-; GFX9-NEXT: v_mov_b32_e32 v1, 0
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ge_i64_e64 s[2:3], s[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_i64_sge:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: v_cmp_ge_i64_e64 s[2:3], s[2:3], v[0:1]
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
-; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 39)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i64_slt(ptr addrspace(1) %out, i64 %src) {
-; GFX11-LABEL: v_icmp_i64_slt:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_gt_i64_e64 s[2:3], 0x64, s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_i64_slt:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0
-; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-VI-NEXT: v_cmp_lt_i64_e64 s[2:3], s[2:3], v[0:1]
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v3, s1
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, s3
-; SDAG-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; SDAG-VI-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_icmp_i64_slt:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
-; GFX9-NEXT: v_mov_b32_e32 v1, 0
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_lt_i64_e64 s[2:3], s[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_i64_slt:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: v_cmp_lt_i64_e64 s[2:3], s[2:3], v[0:1]
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
-; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 40)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i64_sle(ptr addrspace(1) %out, i64 %src) {
-; GFX11-LABEL: v_icmp_i64_sle:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_ge_i64_e64 s[2:3], 0x64, s[2:3]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_i64_sle:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0
-; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-VI-NEXT: v_cmp_le_i64_e64 s[2:3], s[2:3], v[0:1]
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v3, s1
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s2
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, s3
-; SDAG-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; SDAG-VI-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_icmp_i64_sle:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
-; GFX9-NEXT: v_mov_b32_e32 v1, 0
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_le_i64_e64 s[2:3], s[2:3], v[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_i64_sle:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: v_cmp_le_i64_e64 s[2:3], s[2:3], v[0:1]
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
-; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 41)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i16_eq(ptr addrspace(1) %out, i16 %src) {
-; GFX11-LABEL: v_icmp_i16_eq:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_eq_u16_e64 s[2:3], 0x64, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_i16_eq:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-VI-NEXT: v_cmp_eq_u16_e64 s[2:3], s2, v0
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
-; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
-; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; SDAG-VI-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_icmp_i16_eq:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_eq_u16_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_i16_eq:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: v_cmp_eq_u16_e64 s[2:3], s2, v0
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
-; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
-; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 32)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i16(ptr addrspace(1) %out, i16 %src) {
-; SDAG-GFX11-LABEL: v_icmp_i16:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_i16:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_endpgm
-;
-; SDAG-GFX9-LABEL: v_icmp_i16:
-; SDAG-GFX9: ; %bb.0:
-; SDAG-GFX9-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_i16:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: global_store_b64 v0, v[0:1], s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_i16:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s1
-; GISEL-VI-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
-;
-; GISEL-GFX9-LABEL: v_icmp_i16:
-; GISEL-GFX9: ; %bb.0:
-; GISEL-GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GISEL-GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX9-NEXT: global_store_dwordx2 v0, v[0:1], s[0:1]
-; GISEL-GFX9-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 30)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i16_ne(ptr addrspace(1) %out, i16 %src) {
-; GFX11-LABEL: v_icmp_i16_ne:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_ne_u16_e64 s[2:3], 0x64, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_i16_ne:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-VI-NEXT: v_cmp_ne_u16_e64 s[2:3], s2, v0
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
-; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
-; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; SDAG-VI-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_icmp_i16_ne:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ne_u16_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_i16_ne:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: v_cmp_ne_u16_e64 s[2:3], s2, v0
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
-; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
-; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 33)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i16_ugt(ptr addrspace(1) %out, i16 %src) {
-; GFX11-LABEL: v_icmp_i16_ugt:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_lt_u16_e64 s[2:3], 0x64, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_i16_ugt:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-VI-NEXT: v_cmp_gt_u16_e64 s[2:3], s2, v0
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
-; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
-; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; SDAG-VI-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_icmp_i16_ugt:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_gt_u16_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_i16_ugt:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: v_cmp_gt_u16_e64 s[2:3], s2, v0
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
-; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
-; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 34)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i16_uge(ptr addrspace(1) %out, i16 %src) {
-; GFX11-LABEL: v_icmp_i16_uge:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_le_u16_e64 s[2:3], 0x64, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_i16_uge:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-VI-NEXT: v_cmp_ge_u16_e64 s[2:3], s2, v0
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
-; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
-; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; SDAG-VI-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_icmp_i16_uge:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ge_u16_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_i16_uge:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: v_cmp_ge_u16_e64 s[2:3], s2, v0
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
-; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
-; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 35)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i16_ult(ptr addrspace(1) %out, i16 %src) {
-; GFX11-LABEL: v_icmp_i16_ult:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_gt_u16_e64 s[2:3], 0x64, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_i16_ult:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-VI-NEXT: v_cmp_lt_u16_e64 s[2:3], s2, v0
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
-; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
-; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; SDAG-VI-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_icmp_i16_ult:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_lt_u16_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_i16_ult:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: v_cmp_lt_u16_e64 s[2:3], s2, v0
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
-; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
-; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 36)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i16_ule(ptr addrspace(1) %out, i16 %src) {
-; GFX11-LABEL: v_icmp_i16_ule:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_ge_u16_e64 s[2:3], 0x64, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_i16_ule:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-VI-NEXT: v_cmp_le_u16_e64 s[2:3], s2, v0
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
-; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
-; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; SDAG-VI-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_icmp_i16_ule:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_le_u16_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_i16_ule:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: v_cmp_le_u16_e64 s[2:3], s2, v0
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
-; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
-; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 37)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i16_sgt(ptr addrspace(1) %out, i16 %src) #1 {
-; GFX11-LABEL: v_icmp_i16_sgt:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_lt_i16_e64 s[2:3], 0x64, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_i16_sgt:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-VI-NEXT: v_cmp_gt_i16_e64 s[2:3], s2, v0
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
-; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
-; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; SDAG-VI-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_icmp_i16_sgt:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_gt_i16_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_i16_sgt:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: v_cmp_gt_i16_e64 s[2:3], s2, v0
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
-; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
-; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 38)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i16_sge(ptr addrspace(1) %out, i16 %src) {
-; GFX11-LABEL: v_icmp_i16_sge:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_le_i16_e64 s[2:3], 0x64, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_i16_sge:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-VI-NEXT: v_cmp_ge_i16_e64 s[2:3], s2, v0
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
-; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
-; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; SDAG-VI-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_icmp_i16_sge:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ge_i16_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_i16_sge:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: v_cmp_ge_i16_e64 s[2:3], s2, v0
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
-; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
-; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 39)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i16_slt(ptr addrspace(1) %out, i16 %src) {
-; GFX11-LABEL: v_icmp_i16_slt:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_gt_i16_e64 s[2:3], 0x64, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_i16_slt:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-VI-NEXT: v_cmp_lt_i16_e64 s[2:3], s2, v0
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
-; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
-; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; SDAG-VI-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_icmp_i16_slt:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_lt_i16_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_i16_slt:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: v_cmp_lt_i16_e64 s[2:3], s2, v0
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
-; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
-; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 40)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i16_sle(ptr addrspace(1) %out, i16 %src) {
-; GFX11-LABEL: v_icmp_i16_sle:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_ge_i16_e64 s[2:3], 0x64, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_i16_sle:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-VI-NEXT: v_cmp_le_i16_e64 s[2:3], s2, v0
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
-; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
-; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; SDAG-VI-NEXT: s_endpgm
-;
-; GFX9-LABEL: v_icmp_i16_sle:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x64
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_cmp_le_i16_e64 s[2:3], s2, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX9-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_i16_sle:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x64
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: v_cmp_le_i16_e64 s[2:3], s2, v0
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
-; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
-; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 41)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @v_icmp_i1_ne0(ptr addrspace(1) %out, i32 %a, i32 %b) {
-; SDAG-GFX11-LABEL: v_icmp_i1_ne0:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; SDAG-GFX11-NEXT: v_mov_b32_e32 v2, 0
-; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX11-NEXT: s_cmp_gt_u32 s2, 1
-; SDAG-GFX11-NEXT: s_cselect_b64 s[4:5], -1, 0
-; SDAG-GFX11-NEXT: s_cmp_gt_u32 s3, 2
-; SDAG-GFX11-NEXT: s_cselect_b64 s[2:3], -1, 0
-; SDAG-GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; SDAG-GFX11-NEXT: s_and_b64 s[2:3], s[4:5], s[2:3]
-; SDAG-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; SDAG-GFX11-NEXT: v_mov_b32_e32 v1, s3
-; SDAG-GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: v_icmp_i1_ne0:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-VI-NEXT: s_cmp_gt_u32 s2, 1
-; SDAG-VI-NEXT: s_cselect_b64 s[4:5], -1, 0
-; SDAG-VI-NEXT: s_cmp_gt_u32 s3, 2
-; SDAG-VI-NEXT: s_cselect_b64 s[2:3], -1, 0
-; SDAG-VI-NEXT: s_and_b64 s[2:3], s[4:5], s[2:3]
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
-; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2
-; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3
-; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; SDAG-VI-NEXT: s_endpgm
-;
-; SDAG-GFX9-LABEL: v_icmp_i1_ne0:
-; SDAG-GFX9: ; %bb.0:
-; SDAG-GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; SDAG-GFX9-NEXT: v_mov_b32_e32 v2, 0
-; SDAG-GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; SDAG-GFX9-NEXT: s_cmp_gt_u32 s2, 1
-; SDAG-GFX9-NEXT: s_cselect_b64 s[4:5], -1, 0
-; SDAG-GFX9-NEXT: s_cmp_gt_u32 s3, 2
-; SDAG-GFX9-NEXT: s_cselect_b64 s[2:3], -1, 0
-; SDAG-GFX9-NEXT: s_and_b64 s[2:3], s[4:5], s[2:3]
-; SDAG-GFX9-NEXT: v_mov_b32_e32 v0, s2
-; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, s3
-; SDAG-GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; SDAG-GFX9-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: v_icmp_i1_ne0:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v2, 0
-; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX11-NEXT: s_cmp_gt_u32 s2, 1
-; GISEL-GFX11-NEXT: s_cselect_b32 s2, 1, 0
-; GISEL-GFX11-NEXT: s_cmp_gt_u32 s3, 2
-; GISEL-GFX11-NEXT: s_cselect_b32 s3, 1, 0
-; GISEL-GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GISEL-GFX11-NEXT: s_and_b32 s2, s2, s3
-; GISEL-GFX11-NEXT: s_cmp_lg_u32 s2, 0
-; GISEL-GFX11-NEXT: s_cselect_b64 s[2:3], exec, 0
-; GISEL-GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: v_icmp_i1_ne0:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-VI-NEXT: s_cmp_gt_u32 s2, 1
-; GISEL-VI-NEXT: s_cselect_b32 s2, 1, 0
-; GISEL-VI-NEXT: s_cmp_gt_u32 s3, 2
-; GISEL-VI-NEXT: s_cselect_b32 s3, 1, 0
-; GISEL-VI-NEXT: s_and_b32 s2, s2, s3
-; GISEL-VI-NEXT: s_cmp_lg_u32 s2, 0
-; GISEL-VI-NEXT: s_cselect_b64 s[2:3], exec, 0
-; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1
-; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0
-; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
-;
-; GISEL-GFX9-LABEL: v_icmp_i1_ne0:
-; GISEL-GFX9: ; %bb.0:
-; GISEL-GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GISEL-GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GISEL-GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GISEL-GFX9-NEXT: s_cmp_gt_u32 s2, 1
-; GISEL-GFX9-NEXT: s_cselect_b32 s2, 1, 0
-; GISEL-GFX9-NEXT: s_cmp_gt_u32 s3, 2
-; GISEL-GFX9-NEXT: s_cselect_b32 s3, 1, 0
-; GISEL-GFX9-NEXT: s_and_b32 s2, s2, s3
-; GISEL-GFX9-NEXT: s_cmp_lg_u32 s2, 0
-; GISEL-GFX9-NEXT: s_cselect_b64 s[2:3], exec, 0
-; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GISEL-GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GISEL-GFX9-NEXT: s_endpgm
- %c0 = icmp ugt i32 %a, 1
- %c1 = icmp ugt i32 %b, 2
- %src = and i1 %c0, %c1
- %result = call i64 @llvm.amdgcn.icmp.i1(i1 %src, i1 false, i32 33)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_ps i64 @v_icmp_i1_ne0_divergent(i32 %a) {
-; SDAG-GFX11-LABEL: v_icmp_i1_ne0_divergent:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v0
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; SDAG-GFX11-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-GFX11-NEXT: v_mov_b32_e32 v1, s1
-; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; SDAG-GFX11-NEXT: v_readfirstlane_b32 s0, v0
-; SDAG-GFX11-NEXT: v_readfirstlane_b32 s1, v1
-; SDAG-GFX11-NEXT: ; return to shader part epilog
-;
-; SDAG-VI-LABEL: v_icmp_i1_ne0_divergent:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v0
-; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
-; SDAG-VI-NEXT: v_readfirstlane_b32 s0, v0
-; SDAG-VI-NEXT: v_readfirstlane_b32 s1, v1
-; SDAG-VI-NEXT: ; return to shader part epilog
-;
-; SDAG-GFX9-LABEL: v_icmp_i1_ne0_divergent:
-; SDAG-GFX9: ; %bb.0:
-; SDAG-GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v0
-; SDAG-GFX9-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, s1
-; SDAG-GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; SDAG-GFX9-NEXT: v_readfirstlane_b32 s1, v1
-; SDAG-GFX9-NEXT: ; return to shader part epilog
-;
-; GISEL-GFX11-LABEL: v_icmp_i1_ne0_divergent:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v0
-; GISEL-GFX11-NEXT: ; return to shader part epilog
-;
-; GISEL-VI-LABEL: v_icmp_i1_ne0_divergent:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v0
-; GISEL-VI-NEXT: ; return to shader part epilog
-;
-; GISEL-GFX9-LABEL: v_icmp_i1_ne0_divergent:
-; GISEL-GFX9: ; %bb.0:
-; GISEL-GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v0
-; GISEL-GFX9-NEXT: ; return to shader part epilog
- %cond = icmp eq i32 %a, 0
- %result = call i64 @llvm.amdgcn.icmp.i1(i1 %cond, i1 false, i32 33)
- ret i64 %result
-}
-
-define amdgpu_ps void @test_intr_icmp_i32_invalid_cc(ptr addrspace(1) %out, i32 %src) {
-; SDAG-GFX11-LABEL: test_intr_icmp_i32_invalid_cc:
-; SDAG-GFX11: ; %bb.0:
-; SDAG-GFX11-NEXT: s_endpgm
-;
-; SDAG-VI-LABEL: test_intr_icmp_i32_invalid_cc:
-; SDAG-VI: ; %bb.0:
-; SDAG-VI-NEXT: s_endpgm
-;
-; SDAG-GFX9-LABEL: test_intr_icmp_i32_invalid_cc:
-; SDAG-GFX9: ; %bb.0:
-; SDAG-GFX9-NEXT: s_endpgm
-;
-; GISEL-GFX11-LABEL: test_intr_icmp_i32_invalid_cc:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: global_store_b64 v[0:1], v[0:1], off
-; GISEL-GFX11-NEXT: s_endpgm
-;
-; GISEL-VI-LABEL: test_intr_icmp_i32_invalid_cc:
-; GISEL-VI: ; %bb.0:
-; GISEL-VI-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
-; GISEL-VI-NEXT: s_endpgm
-;
-; GISEL-GFX9-LABEL: test_intr_icmp_i32_invalid_cc:
-; GISEL-GFX9: ; %bb.0:
-; GISEL-GFX9-NEXT: global_store_dwordx2 v[0:1], v[0:1], off
-; GISEL-GFX9-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 9999)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-attributes #0 = { nounwind readnone convergent }
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GCN: {{.*}}
-; VI: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll b/llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
index de401c02bf605..63cc9188a9ab4 100644
--- a/llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
@@ -1,47 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mattr=+wavefrontsize64 --global-isel=0 -mcpu=gfx1100 < %s | FileCheck -check-prefixes=CHECK %s
-define amdgpu_kernel void @icmp_test() {
-; CHECK-LABEL: icmp_test:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: v_cmp_eq_u16_e64 s[0:1], 0, 0
-; CHECK-NEXT: v_mov_b32_e32 v0, 0
-; CHECK-NEXT: s_cmp_eq_u64 s[0:1], 0
-; CHECK-NEXT: s_cselect_b32 s0, 1, 0
-; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; CHECK-NEXT: v_mov_b32_e32 v1, s0
-; CHECK-NEXT: ds_store_b32 v0, v1
-; CHECK-NEXT: s_endpgm
-entry:
- %icmp.intr = tail call i64 @llvm.amdgcn.icmp.i64.i16(i16 0, i16 0, i32 32)
- %cmp0 = icmp eq i64 %icmp.intr, 0
- %zext0 = zext i1 %cmp0 to i32
- store i32 %zext0, ptr addrspace(3) zeroinitializer, align 2147483648
- ret void
-}
-
-define amdgpu_kernel void @fcmp_test(half %x, half %y) {
-; CHECK-LABEL: fcmp_test:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: s_load_b32 s0, s[4:5], 0x0
-; CHECK-NEXT: v_mov_b32_e32 v0, 0
-; CHECK-NEXT: s_waitcnt lgkmcnt(0)
-; CHECK-NEXT: s_lshr_b32 s1, s0, 16
-; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; CHECK-NEXT: v_cmp_le_f16_e64 s[0:1], s0, s1
-; CHECK-NEXT: s_cmp_eq_u64 s[0:1], 0
-; CHECK-NEXT: s_cselect_b32 s0, 1, 0
-; CHECK-NEXT: v_mov_b32_e32 v1, s0
-; CHECK-NEXT: ds_store_b32 v0, v1
-; CHECK-NEXT: s_endpgm
-entry:
- %fcmp.intr = tail call i64 @llvm.amdgcn.fcmp.i64.f16(half %x, half %y, i32 5)
- %cmp0 = icmp eq i64 %fcmp.intr, 0
- %zext0 = zext i1 %cmp0 to i32
- store i32 %zext0, ptr addrspace(3) zeroinitializer, align 2147483648
- ret void
-}
-
define amdgpu_kernel void @ballot_test(half %x, half %y) {
; CHECK-LABEL: ballot_test:
; CHECK: ; %bb.0:
@@ -62,10 +21,6 @@ define amdgpu_kernel void @ballot_test(half %x, half %y) {
ret void
}
-declare i64 @llvm.amdgcn.icmp.i64.i16(i16, i16, i32 immarg) #0
-
-declare i64 @llvm.amdgcn.fcmp.i64.f16(half, half, i32 immarg) #0
-
declare i64 @llvm.amdgcn.ballot.i64(i1) #0
attributes #0 = { convergent nounwind readnone willreturn }
diff --git a/llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.ll b/llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.ll
index 3c32cbafef167..2a81ab55f5e0d 100644
--- a/llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.ll
+++ b/llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.ll
@@ -205,90 +205,5 @@ if:
endif:
ret i32 %x
}
-
-declare amdgpu_gfx void @check_live_outs_helper(i64) #0
-
-; In cases where the output operand cannot be safely removed,
-; don't apply the v_cmpx transformation.
-define amdgpu_cs void @check_live_outs(i32 %a, i32 %b) {
-; GCN-LABEL: check_live_outs:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
-; GCN-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
-; GCN-NEXT: s_mov_b32 s10, -1
-; GCN-NEXT: s_mov_b32 s11, 0x31c16000
-; GCN-NEXT: s_add_u32 s8, s8, s0
-; GCN-NEXT: v_cmp_eq_u32_e64 s0, v0, v1
-; GCN-NEXT: s_addc_u32 s9, s9, 0
-; GCN-NEXT: s_mov_b32 s32, 0
-; GCN-NEXT: s_and_saveexec_b32 s1, s0
-; GCN-NEXT: s_cbranch_execz .LBB6_2
-; GCN-NEXT: ; %bb.1: ; %l1
-; GCN-NEXT: s_getpc_b64 s[2:3]
-; GCN-NEXT: s_add_u32 s2, s2, check_live_outs_helper at gotpcrel32@lo+4
-; GCN-NEXT: s_addc_u32 s3, s3, check_live_outs_helper at gotpcrel32@hi+12
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
-; GCN-NEXT: v_mov_b32_e32 v1, 0
-; GCN-NEXT: s_mov_b64 s[0:1], s[8:9]
-; GCN-NEXT: s_mov_b64 s[2:3], s[10:11]
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
-; GCN-NEXT: .LBB6_2: ; %l2
-; GCN-NEXT: s_endpgm
- %cond = icmp eq i32 %a, %b
- %result = call i64 @llvm.amdgcn.icmp.i32(i32 %a, i32 %b, i32 32)
- br i1 %cond, label %l1, label %l2
-l1:
- call amdgpu_gfx void @check_live_outs_helper(i64 %result)
- br label %l2
-l2:
- ret void
-}
-
-; Omit the transformation if the s_and_saveexec instruction overwrites
-; any of the v_cmp source operands.
-define i32 @check_saveexec_overwrites_vcmp_source(i32 inreg %a, i32 inreg %b) {
-; GCN-LABEL: check_saveexec_overwrites_vcmp_source:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: s_cmp_lt_i32 s16, 0
-; GCN-NEXT: s_cbranch_scc1 .LBB7_2
-; GCN-NEXT: ; %bb.1: ; %if
-; GCN-NEXT: s_lshl_b32 s4, s16, 2
-; GCN-NEXT: s_or_b32 s4, s4, s17
-; GCN-NEXT: v_mov_b32_e32 v0, s4
-; GCN-NEXT: s_setpc_b64 s[30:31]
-; GCN-NEXT: .LBB7_2: ; %then
-; GCN-NEXT: v_cmp_eq_u32_e64 s4, s16, s17
-; GCN-NEXT: s_cmp_ge_i32 s4, s17
-; GCN-NEXT: s_cbranch_scc1 .LBB7_4
-; GCN-NEXT: ; %bb.3: ; %after
-; GCN-NEXT: v_mov_b32_e32 v0, s4
-; GCN-NEXT: s_setpc_b64 s[30:31]
-; GCN-NEXT: .LBB7_4: ; %end
-; GCN-NEXT: v_mov_b32_e32 v0, s16
-; GCN-NEXT: s_setpc_b64 s[30:31]
-entry:
- %0 = icmp sge i32 %a, 0
- br i1 %0, label %if, label %then
-
-if:
- %1 = shl i32 %a, 2
- %2 = or i32 %1, %b
- ret i32 %2
-
-then:
- %3 = call i64 @llvm.amdgcn.icmp.i32(i32 %a, i32 %b, i32 32)
- %4 = trunc i64 %3 to i32
- %5 = icmp slt i32 %4, %b
- br i1 %5, label %after, label %end
-
-after:
- ret i32 %4
-
-end:
- ret i32 %a
-}
-
-declare i64 @llvm.amdgcn.icmp.i32(i32, i32, i32) #0
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GCN: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/wave32.ll b/llvm/test/CodeGen/AMDGPU/wave32.ll
index d857d147a248d..a3aed67673212 100644
--- a/llvm/test/CodeGen/AMDGPU/wave32.ll
+++ b/llvm/test/CodeGen/AMDGPU/wave32.ll
@@ -2148,118 +2148,6 @@ main_body:
ret float %out.2
}
-define amdgpu_kernel void @test_intr_fcmp_i64(ptr addrspace(1) %out, float %src, float %a) #1 {
-; GFX1032-LABEL: test_intr_fcmp_i64:
-; GFX1032: ; %bb.0:
-; GFX1032-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX1032-NEXT: v_mov_b32_e32 v1, 0
-; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032-NEXT: v_cmp_eq_f32_e64 s2, s2, |s3|
-; GFX1032-NEXT: v_mov_b32_e32 v0, s2
-; GFX1032-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
-; GFX1032-NEXT: s_endpgm
-;
-; GFX1064-LABEL: test_intr_fcmp_i64:
-; GFX1064: ; %bb.0:
-; GFX1064-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX1064-NEXT: v_mov_b32_e32 v2, 0
-; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064-NEXT: v_cmp_eq_f32_e64 s[2:3], s2, |s3|
-; GFX1064-NEXT: v_mov_b32_e32 v0, s2
-; GFX1064-NEXT: v_mov_b32_e32 v1, s3
-; GFX1064-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX1064-NEXT: s_endpgm
- %temp = call float @llvm.fabs.f32(float %a)
- %result = call i64 @llvm.amdgcn.fcmp.i64.f32(float %src, float %temp, i32 1)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @test_intr_icmp_i64(ptr addrspace(1) %out, i32 %src) #1 {
-; GFX1032-LABEL: test_intr_icmp_i64:
-; GFX1032: ; %bb.0:
-; GFX1032-NEXT: s_clause 0x1
-; GFX1032-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX1032-NEXT: v_mov_b32_e32 v1, 0
-; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032-NEXT: v_cmp_eq_u32_e64 s2, 0x64, s2
-; GFX1032-NEXT: v_mov_b32_e32 v0, s2
-; GFX1032-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
-; GFX1032-NEXT: s_endpgm
-;
-; GFX1064-LABEL: test_intr_icmp_i64:
-; GFX1064: ; %bb.0:
-; GFX1064-NEXT: s_clause 0x1
-; GFX1064-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX1064-NEXT: v_mov_b32_e32 v2, 0
-; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064-NEXT: v_cmp_eq_u32_e64 s[2:3], 0x64, s2
-; GFX1064-NEXT: v_mov_b32_e32 v0, s2
-; GFX1064-NEXT: v_mov_b32_e32 v1, s3
-; GFX1064-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX1064-NEXT: s_endpgm
- %result = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %src, i32 100, i32 32)
- store i64 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @test_intr_fcmp_i32(ptr addrspace(1) %out, float %src, float %a) #1 {
-; GFX1032-LABEL: test_intr_fcmp_i32:
-; GFX1032: ; %bb.0:
-; GFX1032-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX1032-NEXT: v_mov_b32_e32 v0, 0
-; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032-NEXT: v_cmp_eq_f32_e64 s2, s2, |s3|
-; GFX1032-NEXT: v_mov_b32_e32 v1, s2
-; GFX1032-NEXT: global_store_dword v0, v1, s[0:1]
-; GFX1032-NEXT: s_endpgm
-;
-; GFX1064-LABEL: test_intr_fcmp_i32:
-; GFX1064: ; %bb.0:
-; GFX1064-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX1064-NEXT: v_mov_b32_e32 v0, 0
-; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064-NEXT: v_cmp_eq_f32_e64 s[2:3], s2, |s3|
-; GFX1064-NEXT: v_mov_b32_e32 v1, s2
-; GFX1064-NEXT: global_store_dword v0, v1, s[0:1]
-; GFX1064-NEXT: s_endpgm
- %temp = call float @llvm.fabs.f32(float %a)
- %result = call i32 @llvm.amdgcn.fcmp.i32.f32(float %src, float %temp, i32 1)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
-define amdgpu_kernel void @test_intr_icmp_i32(ptr addrspace(1) %out, i32 %src) #1 {
-; GFX1032-LABEL: test_intr_icmp_i32:
-; GFX1032: ; %bb.0:
-; GFX1032-NEXT: s_clause 0x1
-; GFX1032-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX1032-NEXT: v_mov_b32_e32 v0, 0
-; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032-NEXT: v_cmp_eq_u32_e64 s2, 0x64, s2
-; GFX1032-NEXT: v_mov_b32_e32 v1, s2
-; GFX1032-NEXT: global_store_dword v0, v1, s[0:1]
-; GFX1032-NEXT: s_endpgm
-;
-; GFX1064-LABEL: test_intr_icmp_i32:
-; GFX1064: ; %bb.0:
-; GFX1064-NEXT: s_clause 0x1
-; GFX1064-NEXT: s_load_dword s2, s[4:5], 0x2c
-; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX1064-NEXT: v_mov_b32_e32 v0, 0
-; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064-NEXT: v_cmp_eq_u32_e64 s[2:3], 0x64, s2
-; GFX1064-NEXT: v_mov_b32_e32 v1, s2
-; GFX1064-NEXT: global_store_dword v0, v1, s[0:1]
-; GFX1064-NEXT: s_endpgm
- %result = call i32 @llvm.amdgcn.icmp.i32.i32(i32 %src, i32 100, i32 32)
- store i32 %result, ptr addrspace(1) %out
- ret void
-}
-
define amdgpu_ps void @test_wqm_vote(float %a) #1 {
; GFX1032-LABEL: test_wqm_vote:
; GFX1032: ; %bb.0:
@@ -2269,12 +2157,12 @@ define amdgpu_ps void @test_wqm_vote(float %a) #1 {
; GFX1032-NEXT: s_wqm_b32 s1, vcc_lo
; GFX1032-NEXT: s_andn2_b32 s1, exec_lo, s1
; GFX1032-NEXT: s_andn2_b32 s0, s0, s1
-; GFX1032-NEXT: s_cbranch_scc0 .LBB44_2
+; GFX1032-NEXT: s_cbranch_scc0 .LBB40_2
; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: s_and_b32 exec_lo, exec_lo, s0
; GFX1032-NEXT: exp mrt0, off, off, off, off
; GFX1032-NEXT: s_endpgm
-; GFX1032-NEXT: .LBB44_2:
+; GFX1032-NEXT: .LBB40_2:
; GFX1032-NEXT: s_mov_b32 exec_lo, 0
; GFX1032-NEXT: exp null, off, off, off, off done vm
; GFX1032-NEXT: s_endpgm
@@ -2287,12 +2175,12 @@ define amdgpu_ps void @test_wqm_vote(float %a) #1 {
; GFX1064-NEXT: s_wqm_b64 s[2:3], vcc
; GFX1064-NEXT: s_andn2_b64 s[2:3], exec, s[2:3]
; GFX1064-NEXT: s_andn2_b64 s[0:1], s[0:1], s[2:3]
-; GFX1064-NEXT: s_cbranch_scc0 .LBB44_2
+; GFX1064-NEXT: s_cbranch_scc0 .LBB40_2
; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: s_and_b64 exec, exec, s[0:1]
; GFX1064-NEXT: exp mrt0, off, off, off, off
; GFX1064-NEXT: s_endpgm
-; GFX1064-NEXT: .LBB44_2:
+; GFX1064-NEXT: .LBB40_2:
; GFX1064-NEXT: s_mov_b64 exec, 0
; GFX1064-NEXT: exp null, off, off, off, off done vm
; GFX1064-NEXT: s_endpgm
@@ -2307,31 +2195,31 @@ define amdgpu_kernel void @test_branch_true() #2 {
; GFX1032-LABEL: test_branch_true:
; GFX1032: ; %bb.0: ; %entry
; GFX1032-NEXT: s_mov_b32 vcc_lo, exec_lo
-; GFX1032-NEXT: s_cbranch_execnz .LBB45_2
+; GFX1032-NEXT: s_cbranch_execnz .LBB41_2
; GFX1032-NEXT: ; %bb.1: ; %for.body.lr.ph
-; GFX1032-NEXT: s_branch .LBB45_3
-; GFX1032-NEXT: .LBB45_2: ; %Flow
-; GFX1032-NEXT: s_branch .LBB45_5
-; GFX1032-NEXT: .LBB45_3: ; %for.body
+; GFX1032-NEXT: s_branch .LBB41_3
+; GFX1032-NEXT: .LBB41_2: ; %Flow
+; GFX1032-NEXT: s_branch .LBB41_5
+; GFX1032-NEXT: .LBB41_3: ; %for.body
; GFX1032-NEXT: s_mov_b32 vcc_lo, 0
; GFX1032-NEXT: ; %bb.4: ; %for.end.loopexit
-; GFX1032-NEXT: s_branch .LBB45_2
-; GFX1032-NEXT: .LBB45_5: ; %for.end
+; GFX1032-NEXT: s_branch .LBB41_2
+; GFX1032-NEXT: .LBB41_5: ; %for.end
; GFX1032-NEXT: s_endpgm
;
; GFX1064-LABEL: test_branch_true:
; GFX1064: ; %bb.0: ; %entry
; GFX1064-NEXT: s_mov_b64 vcc, exec
-; GFX1064-NEXT: s_cbranch_execnz .LBB45_2
+; GFX1064-NEXT: s_cbranch_execnz .LBB41_2
; GFX1064-NEXT: ; %bb.1: ; %for.body.lr.ph
-; GFX1064-NEXT: s_branch .LBB45_3
-; GFX1064-NEXT: .LBB45_2: ; %Flow
-; GFX1064-NEXT: s_branch .LBB45_5
-; GFX1064-NEXT: .LBB45_3: ; %for.body
+; GFX1064-NEXT: s_branch .LBB41_3
+; GFX1064-NEXT: .LBB41_2: ; %Flow
+; GFX1064-NEXT: s_branch .LBB41_5
+; GFX1064-NEXT: .LBB41_3: ; %for.body
; GFX1064-NEXT: s_mov_b64 vcc, 0
; GFX1064-NEXT: ; %bb.4: ; %for.end.loopexit
-; GFX1064-NEXT: s_branch .LBB45_2
-; GFX1064-NEXT: .LBB45_5: ; %for.end
+; GFX1064-NEXT: s_branch .LBB41_2
+; GFX1064-NEXT: .LBB41_5: ; %for.end
; GFX1064-NEXT: s_endpgm
entry:
br i1 true, label %for.end, label %for.body.lr.ph
@@ -2373,14 +2261,14 @@ define amdgpu_kernel void @test_vccnz_ifcvt_triangle64(ptr addrspace(1) %out, pt
; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032-NEXT: v_cmp_neq_f64_e64 s4, s[2:3], 1.0
; GFX1032-NEXT: s_and_b32 vcc_lo, exec_lo, s4
-; GFX1032-NEXT: s_cbranch_vccnz .LBB47_2
+; GFX1032-NEXT: s_cbranch_vccnz .LBB43_2
; GFX1032-NEXT: ; %bb.1: ; %if
; GFX1032-NEXT: v_add_f64 v[0:1], s[2:3], s[2:3]
-; GFX1032-NEXT: s_branch .LBB47_3
-; GFX1032-NEXT: .LBB47_2:
+; GFX1032-NEXT: s_branch .LBB43_3
+; GFX1032-NEXT: .LBB43_2:
; GFX1032-NEXT: v_mov_b32_e32 v0, s2
; GFX1032-NEXT: v_mov_b32_e32 v1, s3
-; GFX1032-NEXT: .LBB47_3: ; %endif
+; GFX1032-NEXT: .LBB43_3: ; %endif
; GFX1032-NEXT: v_mov_b32_e32 v2, 0
; GFX1032-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX1032-NEXT: s_endpgm
@@ -2393,14 +2281,14 @@ define amdgpu_kernel void @test_vccnz_ifcvt_triangle64(ptr addrspace(1) %out, pt
; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064-NEXT: v_cmp_neq_f64_e64 s[4:5], s[2:3], 1.0
; GFX1064-NEXT: s_and_b64 vcc, exec, s[4:5]
-; GFX1064-NEXT: s_cbranch_vccnz .LBB47_2
+; GFX1064-NEXT: s_cbranch_vccnz .LBB43_2
; GFX1064-NEXT: ; %bb.1: ; %if
; GFX1064-NEXT: v_add_f64 v[0:1], s[2:3], s[2:3]
-; GFX1064-NEXT: s_branch .LBB47_3
-; GFX1064-NEXT: .LBB47_2:
+; GFX1064-NEXT: s_branch .LBB43_3
+; GFX1064-NEXT: .LBB43_2:
; GFX1064-NEXT: v_mov_b32_e32 v0, s2
; GFX1064-NEXT: v_mov_b32_e32 v1, s3
-; GFX1064-NEXT: .LBB47_3: ; %endif
+; GFX1064-NEXT: .LBB43_3: ; %endif
; GFX1064-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX1064-NEXT: s_endpgm
@@ -2481,618 +2369,6 @@ main_body:
ret float %s.10
}
-define amdgpu_kernel void @icmp64(i32 %n, i32 %s) #1 {
-; GFX1032-LABEL: icmp64:
-; GFX1032: ; %bb.0: ; %entry
-; GFX1032-NEXT: s_load_dword s0, s[4:5], 0x28
-; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032-NEXT: v_cvt_f32_u32_e32 v1, s0
-; GFX1032-NEXT: s_sub_i32 s1, 0, s0
-; GFX1032-NEXT: v_rcp_f32_e32 v1, v1
-; GFX1032-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
-; GFX1032-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX1032-NEXT: v_mul_lo_u32 v2, s1, v1
-; GFX1032-NEXT: s_brev_b32 s1, 1
-; GFX1032-NEXT: v_mul_hi_u32 v2, v1, v2
-; GFX1032-NEXT: v_add_nc_u32_e32 v1, v1, v2
-; GFX1032-NEXT: v_mul_hi_u32 v1, v0, v1
-; GFX1032-NEXT: v_mul_lo_u32 v1, v1, s0
-; GFX1032-NEXT: v_sub_nc_u32_e32 v0, v0, v1
-; GFX1032-NEXT: v_subrev_nc_u32_e32 v1, s0, v0
-; GFX1032-NEXT: v_cmp_le_u32_e32 vcc_lo, s0, v0
-; GFX1032-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX1032-NEXT: v_subrev_nc_u32_e32 v1, s0, v0
-; GFX1032-NEXT: v_cmp_le_u32_e32 vcc_lo, s0, v0
-; GFX1032-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX1032-NEXT: s_lshr_b32 s0, vcc_lo, 1
-; GFX1032-NEXT: s_ff1_i32_b64 s0, s[0:1]
-; GFX1032-NEXT: s_cmp_gt_u32 s0, 9
-; GFX1032-NEXT: s_cselect_b32 s0, -1, 0
-; GFX1032-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX1032-NEXT: s_and_saveexec_b32 s1, s0
-; GFX1032-NEXT: ; %bb.1: ; %if.then
-; GFX1032-NEXT: ; divergent unreachable
-; GFX1032-NEXT: ; %bb.2: ; %UnifiedReturnBlock
-; GFX1032-NEXT: s_endpgm
-;
-; GFX1064-LABEL: icmp64:
-; GFX1064: ; %bb.0: ; %entry
-; GFX1064-NEXT: s_load_dword s0, s[4:5], 0x28
-; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064-NEXT: v_cvt_f32_u32_e32 v1, s0
-; GFX1064-NEXT: s_sub_i32 s1, 0, s0
-; GFX1064-NEXT: v_rcp_f32_e32 v1, v1
-; GFX1064-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
-; GFX1064-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX1064-NEXT: v_mul_lo_u32 v2, s1, v1
-; GFX1064-NEXT: v_mul_hi_u32 v2, v1, v2
-; GFX1064-NEXT: v_add_nc_u32_e32 v1, v1, v2
-; GFX1064-NEXT: v_mul_hi_u32 v1, v0, v1
-; GFX1064-NEXT: v_mul_lo_u32 v1, v1, s0
-; GFX1064-NEXT: v_sub_nc_u32_e32 v0, v0, v1
-; GFX1064-NEXT: v_subrev_nc_u32_e32 v1, s0, v0
-; GFX1064-NEXT: v_cmp_le_u32_e32 vcc, s0, v0
-; GFX1064-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX1064-NEXT: v_subrev_nc_u32_e32 v1, s0, v0
-; GFX1064-NEXT: v_cmp_le_u32_e32 vcc, s0, v0
-; GFX1064-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX1064-NEXT: s_lshr_b64 s[0:1], vcc, 1
-; GFX1064-NEXT: s_bitset1_b32 s1, 31
-; GFX1064-NEXT: s_ff1_i32_b64 s0, s[0:1]
-; GFX1064-NEXT: s_cmp_gt_u32 s0, 9
-; GFX1064-NEXT: s_cselect_b64 s[0:1], -1, 0
-; GFX1064-NEXT: s_and_b64 s[0:1], vcc, s[0:1]
-; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], s[0:1]
-; GFX1064-NEXT: ; %bb.1: ; %if.then
-; GFX1064-NEXT: ; divergent unreachable
-; GFX1064-NEXT: ; %bb.2: ; %UnifiedReturnBlock
-; GFX1064-NEXT: s_endpgm
-entry:
- %id = tail call i32 @llvm.amdgcn.workitem.id.x()
- %mul4 = mul nsw i32 %s, %n
- %cmp = icmp slt i32 0, %mul4
- br label %if.end
-
-if.end: ; preds = %entry
- %rem = urem i32 %id, %s
- %icmp = tail call i64 @llvm.amdgcn.icmp.i64.i32(i32 %rem, i32 0, i32 32)
- %shr = lshr i64 %icmp, 1
- %notmask = shl nsw i64 -1, 0
- %and = and i64 %notmask, %shr
- %or = or i64 %and, -9223372036854775808
- %cttz = tail call i64 @llvm.cttz.i64(i64 %or, i1 true)
- %cast = trunc i64 %cttz to i32
- %cmp3 = icmp ugt i32 10, %cast
- %cmp6 = icmp ne i32 %rem, 0
- %brmerge = or i1 %cmp6, %cmp3
- br i1 %brmerge, label %if.end2, label %if.then
-
-if.then: ; preds = %if.end
- unreachable
-
-if.end2: ; preds = %if.end
- ret void
-}
-
-define amdgpu_kernel void @fcmp64(float %n, float %s) #1 {
-; GFX1032-LABEL: fcmp64:
-; GFX1032: ; %bb.0: ; %entry
-; GFX1032-NEXT: s_load_dword s0, s[4:5], 0x28
-; GFX1032-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX1032-NEXT: ; implicit-def: $vgpr1
-; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032-NEXT: v_cmp_ngt_f32_e64 s1, v0, |s0|
-; GFX1032-NEXT: s_and_saveexec_b32 s2, s1
-; GFX1032-NEXT: s_xor_b32 s1, exec_lo, s2
-; GFX1032-NEXT: ; %bb.1: ; %frem.else
-; GFX1032-NEXT: v_and_b32_e32 v1, 0x80000000, v0
-; GFX1032-NEXT: v_cmp_eq_f32_e64 vcc_lo, v0, |s0|
-; GFX1032-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc_lo
-; GFX1032-NEXT: ; implicit-def: $vgpr0
-; GFX1032-NEXT: ; %bb.2: ; %Flow13
-; GFX1032-NEXT: s_andn2_saveexec_b32 s1, s1
-; GFX1032-NEXT: s_cbranch_execz .LBB51_8
-; GFX1032-NEXT: ; %bb.3: ; %frem.compute
-; GFX1032-NEXT: v_frexp_mant_f32_e64 v1, |s0|
-; GFX1032-NEXT: v_frexp_exp_i32_f32_e32 v7, v0
-; GFX1032-NEXT: v_frexp_mant_f32_e32 v8, v0
-; GFX1032-NEXT: v_ldexp_f32 v1, v1, 1
-; GFX1032-NEXT: v_div_scale_f32 v2, s2, v1, v1, 1.0
-; GFX1032-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v1, 1.0
-; GFX1032-NEXT: v_rcp_f32_e32 v3, v2
-; GFX1032-NEXT: v_fma_f32 v4, -v2, v3, 1.0
-; GFX1032-NEXT: v_fmac_f32_e32 v3, v4, v3
-; GFX1032-NEXT: v_mul_f32_e32 v4, v5, v3
-; GFX1032-NEXT: v_fma_f32 v6, -v2, v4, v5
-; GFX1032-NEXT: v_fmac_f32_e32 v4, v6, v3
-; GFX1032-NEXT: v_frexp_exp_i32_f32_e32 v6, s0
-; GFX1032-NEXT: v_fma_f32 v5, -v2, v4, v5
-; GFX1032-NEXT: v_add_nc_u32_e32 v2, -1, v6
-; GFX1032-NEXT: v_div_fmas_f32 v3, v5, v3, v4
-; GFX1032-NEXT: v_xad_u32 v4, v2, -1, v7
-; GFX1032-NEXT: v_ldexp_f32 v5, v8, 12
-; GFX1032-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; GFX1032-NEXT: v_cmp_lt_i32_e32 vcc_lo, 12, v4
-; GFX1032-NEXT: s_and_saveexec_b32 s2, vcc_lo
-; GFX1032-NEXT: s_cbranch_execz .LBB51_7
-; GFX1032-NEXT: ; %bb.4: ; %frem.loop_body.preheader
-; GFX1032-NEXT: v_sub_nc_u32_e32 v4, v7, v6
-; GFX1032-NEXT: s_mov_b32 s3, 0
-; GFX1032-NEXT: v_add_nc_u32_e32 v4, 12, v4
-; GFX1032-NEXT: .LBB51_5: ; %frem.loop_body
-; GFX1032-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1032-NEXT: v_mov_b32_e32 v6, v5
-; GFX1032-NEXT: v_add_nc_u32_e32 v4, -12, v4
-; GFX1032-NEXT: v_mul_f32_e32 v5, v6, v3
-; GFX1032-NEXT: v_rndne_f32_e32 v5, v5
-; GFX1032-NEXT: v_fma_f32 v5, -v5, v1, v6
-; GFX1032-NEXT: v_add_f32_e32 v7, v5, v1
-; GFX1032-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v5
-; GFX1032-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
-; GFX1032-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v4
-; GFX1032-NEXT: v_ldexp_f32 v5, v5, 12
-; GFX1032-NEXT: s_or_b32 s3, vcc_lo, s3
-; GFX1032-NEXT: s_andn2_b32 exec_lo, exec_lo, s3
-; GFX1032-NEXT: s_cbranch_execnz .LBB51_5
-; GFX1032-NEXT: ; %bb.6: ; %Flow
-; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s3
-; GFX1032-NEXT: v_mov_b32_e32 v5, v6
-; GFX1032-NEXT: .LBB51_7: ; %Flow12
-; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2
-; GFX1032-NEXT: v_add_nc_u32_e32 v4, -11, v4
-; GFX1032-NEXT: v_ldexp_f32 v4, v5, v4
-; GFX1032-NEXT: v_mul_f32_e32 v3, v4, v3
-; GFX1032-NEXT: v_rndne_f32_e32 v3, v3
-; GFX1032-NEXT: v_fma_f32 v3, -v3, v1, v4
-; GFX1032-NEXT: v_add_f32_e32 v1, v3, v1
-; GFX1032-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
-; GFX1032-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
-; GFX1032-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX1032-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v0
-; GFX1032-NEXT: .LBB51_8: ; %Flow14
-; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX1032-NEXT: v_cmp_lg_f32_e64 vcc_lo, s0, 0
-; GFX1032-NEXT: s_brev_b32 s1, 1
-; GFX1032-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX1032-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0
-; GFX1032-NEXT: s_lshr_b32 s0, vcc_lo, 1
-; GFX1032-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v0
-; GFX1032-NEXT: s_ff1_i32_b64 s0, s[0:1]
-; GFX1032-NEXT: s_cmp_gt_u32 s0, 9
-; GFX1032-NEXT: s_cselect_b32 s0, -1, 0
-; GFX1032-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX1032-NEXT: s_and_saveexec_b32 s1, s0
-; GFX1032-NEXT: ; %bb.9: ; %if.then
-; GFX1032-NEXT: ; divergent unreachable
-; GFX1032-NEXT: ; %bb.10: ; %UnifiedReturnBlock
-; GFX1032-NEXT: s_endpgm
-;
-; GFX1064-LABEL: fcmp64:
-; GFX1064: ; %bb.0: ; %entry
-; GFX1064-NEXT: s_load_dword s6, s[4:5], 0x28
-; GFX1064-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX1064-NEXT: ; implicit-def: $vgpr1
-; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064-NEXT: v_cmp_ngt_f32_e64 s[0:1], v0, |s6|
-; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], s[0:1]
-; GFX1064-NEXT: s_xor_b64 s[0:1], exec, s[2:3]
-; GFX1064-NEXT: ; %bb.1: ; %frem.else
-; GFX1064-NEXT: v_and_b32_e32 v1, 0x80000000, v0
-; GFX1064-NEXT: v_cmp_eq_f32_e64 vcc, v0, |s6|
-; GFX1064-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc
-; GFX1064-NEXT: ; implicit-def: $vgpr0
-; GFX1064-NEXT: ; %bb.2: ; %Flow13
-; GFX1064-NEXT: s_andn2_saveexec_b64 s[0:1], s[0:1]
-; GFX1064-NEXT: s_cbranch_execz .LBB51_8
-; GFX1064-NEXT: ; %bb.3: ; %frem.compute
-; GFX1064-NEXT: v_frexp_mant_f32_e64 v1, |s6|
-; GFX1064-NEXT: v_frexp_exp_i32_f32_e32 v7, v0
-; GFX1064-NEXT: v_frexp_mant_f32_e32 v8, v0
-; GFX1064-NEXT: v_ldexp_f32 v1, v1, 1
-; GFX1064-NEXT: v_div_scale_f32 v2, s[2:3], v1, v1, 1.0
-; GFX1064-NEXT: v_div_scale_f32 v5, vcc, 1.0, v1, 1.0
-; GFX1064-NEXT: v_rcp_f32_e32 v3, v2
-; GFX1064-NEXT: v_fma_f32 v4, -v2, v3, 1.0
-; GFX1064-NEXT: v_fmac_f32_e32 v3, v4, v3
-; GFX1064-NEXT: v_mul_f32_e32 v4, v5, v3
-; GFX1064-NEXT: v_fma_f32 v6, -v2, v4, v5
-; GFX1064-NEXT: v_fmac_f32_e32 v4, v6, v3
-; GFX1064-NEXT: v_frexp_exp_i32_f32_e32 v6, s6
-; GFX1064-NEXT: v_fma_f32 v5, -v2, v4, v5
-; GFX1064-NEXT: v_add_nc_u32_e32 v2, -1, v6
-; GFX1064-NEXT: v_div_fmas_f32 v3, v5, v3, v4
-; GFX1064-NEXT: v_xad_u32 v4, v2, -1, v7
-; GFX1064-NEXT: v_ldexp_f32 v5, v8, 12
-; GFX1064-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; GFX1064-NEXT: v_cmp_lt_i32_e32 vcc, 12, v4
-; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], vcc
-; GFX1064-NEXT: s_cbranch_execz .LBB51_7
-; GFX1064-NEXT: ; %bb.4: ; %frem.loop_body.preheader
-; GFX1064-NEXT: v_sub_nc_u32_e32 v4, v7, v6
-; GFX1064-NEXT: s_mov_b64 s[4:5], 0
-; GFX1064-NEXT: v_add_nc_u32_e32 v4, 12, v4
-; GFX1064-NEXT: .LBB51_5: ; %frem.loop_body
-; GFX1064-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1064-NEXT: v_mov_b32_e32 v6, v5
-; GFX1064-NEXT: v_add_nc_u32_e32 v4, -12, v4
-; GFX1064-NEXT: v_mul_f32_e32 v5, v6, v3
-; GFX1064-NEXT: v_rndne_f32_e32 v5, v5
-; GFX1064-NEXT: v_fma_f32 v5, -v5, v1, v6
-; GFX1064-NEXT: v_add_f32_e32 v7, v5, v1
-; GFX1064-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
-; GFX1064-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
-; GFX1064-NEXT: v_cmp_gt_i32_e32 vcc, 13, v4
-; GFX1064-NEXT: v_ldexp_f32 v5, v5, 12
-; GFX1064-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
-; GFX1064-NEXT: s_andn2_b64 exec, exec, s[4:5]
-; GFX1064-NEXT: s_cbranch_execnz .LBB51_5
-; GFX1064-NEXT: ; %bb.6: ; %Flow
-; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX1064-NEXT: v_mov_b32_e32 v5, v6
-; GFX1064-NEXT: .LBB51_7: ; %Flow12
-; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX1064-NEXT: v_add_nc_u32_e32 v4, -11, v4
-; GFX1064-NEXT: v_ldexp_f32 v4, v5, v4
-; GFX1064-NEXT: v_mul_f32_e32 v3, v4, v3
-; GFX1064-NEXT: v_rndne_f32_e32 v3, v3
-; GFX1064-NEXT: v_fma_f32 v3, -v3, v1, v4
-; GFX1064-NEXT: v_add_f32_e32 v1, v3, v1
-; GFX1064-NEXT: v_cmp_gt_f32_e32 vcc, 0, v3
-; GFX1064-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; GFX1064-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX1064-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v0
-; GFX1064-NEXT: .LBB51_8: ; %Flow14
-; GFX1064-NEXT: s_or_b64 exec, exec, s[0:1]
-; GFX1064-NEXT: v_cmp_lg_f32_e64 vcc, s6, 0
-; GFX1064-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc
-; GFX1064-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0
-; GFX1064-NEXT: s_lshr_b64 s[0:1], vcc, 1
-; GFX1064-NEXT: v_cmp_nlg_f32_e32 vcc, 0, v0
-; GFX1064-NEXT: s_bitset1_b32 s1, 31
-; GFX1064-NEXT: s_ff1_i32_b64 s0, s[0:1]
-; GFX1064-NEXT: s_cmp_gt_u32 s0, 9
-; GFX1064-NEXT: s_cselect_b64 s[0:1], -1, 0
-; GFX1064-NEXT: s_and_b64 s[0:1], vcc, s[0:1]
-; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], s[0:1]
-; GFX1064-NEXT: ; %bb.9: ; %if.then
-; GFX1064-NEXT: ; divergent unreachable
-; GFX1064-NEXT: ; %bb.10: ; %UnifiedReturnBlock
-; GFX1064-NEXT: s_endpgm
-entry:
- %id = tail call i32 @llvm.amdgcn.workitem.id.x()
- %id.f = uitofp i32 %id to float
- %mul4 = fmul float %s, %n
- %cmp = fcmp ult float 0.0, %mul4
- br label %if.end
-
-if.end: ; preds = %entry
- %rem.f = frem float %id.f, %s
- %fcmp = tail call i64 @llvm.amdgcn.fcmp.i64.f32(float %rem.f, float 0.0, i32 1)
- %shr = lshr i64 %fcmp, 1
- %notmask = shl nsw i64 -1, 0
- %and = and i64 %notmask, %shr
- %or = or i64 %and, -9223372036854775808
- %cttz = tail call i64 @llvm.cttz.i64(i64 %or, i1 true)
- %cast = trunc i64 %cttz to i32
- %cmp3 = icmp ugt i32 10, %cast
- %cmp6 = fcmp one float %rem.f, 0.0
- %brmerge = or i1 %cmp6, %cmp3
- br i1 %brmerge, label %if.end2, label %if.then
-
-if.then: ; preds = %if.end
- unreachable
-
-if.end2: ; preds = %if.end
- ret void
-}
-
-define amdgpu_kernel void @icmp32(i32 %n, i32 %s) #1 {
-; GFX1032-LABEL: icmp32:
-; GFX1032: ; %bb.0: ; %entry
-; GFX1032-NEXT: s_load_dword s0, s[4:5], 0x28
-; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032-NEXT: v_cvt_f32_u32_e32 v1, s0
-; GFX1032-NEXT: s_sub_i32 s1, 0, s0
-; GFX1032-NEXT: v_rcp_f32_e32 v1, v1
-; GFX1032-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
-; GFX1032-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX1032-NEXT: v_mul_lo_u32 v2, s1, v1
-; GFX1032-NEXT: v_mul_hi_u32 v2, v1, v2
-; GFX1032-NEXT: v_add_nc_u32_e32 v1, v1, v2
-; GFX1032-NEXT: v_mul_hi_u32 v1, v0, v1
-; GFX1032-NEXT: v_mul_lo_u32 v1, v1, s0
-; GFX1032-NEXT: v_sub_nc_u32_e32 v0, v0, v1
-; GFX1032-NEXT: v_subrev_nc_u32_e32 v1, s0, v0
-; GFX1032-NEXT: v_cmp_le_u32_e32 vcc_lo, s0, v0
-; GFX1032-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX1032-NEXT: v_subrev_nc_u32_e32 v1, s0, v0
-; GFX1032-NEXT: v_cmp_le_u32_e32 vcc_lo, s0, v0
-; GFX1032-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX1032-NEXT: s_lshr_b32 s0, vcc_lo, 1
-; GFX1032-NEXT: s_bitset1_b32 s0, 31
-; GFX1032-NEXT: s_ff1_i32_b32 s0, s0
-; GFX1032-NEXT: s_cmp_gt_u32 s0, 9
-; GFX1032-NEXT: s_cselect_b32 s0, -1, 0
-; GFX1032-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX1032-NEXT: s_and_saveexec_b32 s1, s0
-; GFX1032-NEXT: ; %bb.1: ; %if.then
-; GFX1032-NEXT: ; divergent unreachable
-; GFX1032-NEXT: ; %bb.2: ; %UnifiedReturnBlock
-; GFX1032-NEXT: s_endpgm
-;
-; GFX1064-LABEL: icmp32:
-; GFX1064: ; %bb.0: ; %entry
-; GFX1064-NEXT: s_load_dword s0, s[4:5], 0x28
-; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064-NEXT: v_cvt_f32_u32_e32 v1, s0
-; GFX1064-NEXT: s_sub_i32 s1, 0, s0
-; GFX1064-NEXT: v_rcp_f32_e32 v1, v1
-; GFX1064-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
-; GFX1064-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX1064-NEXT: v_mul_lo_u32 v2, s1, v1
-; GFX1064-NEXT: v_mul_hi_u32 v2, v1, v2
-; GFX1064-NEXT: v_add_nc_u32_e32 v1, v1, v2
-; GFX1064-NEXT: v_mul_hi_u32 v1, v0, v1
-; GFX1064-NEXT: v_mul_lo_u32 v1, v1, s0
-; GFX1064-NEXT: v_sub_nc_u32_e32 v0, v0, v1
-; GFX1064-NEXT: v_subrev_nc_u32_e32 v1, s0, v0
-; GFX1064-NEXT: v_cmp_le_u32_e32 vcc, s0, v0
-; GFX1064-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX1064-NEXT: v_subrev_nc_u32_e32 v1, s0, v0
-; GFX1064-NEXT: v_cmp_le_u32_e32 vcc, s0, v0
-; GFX1064-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX1064-NEXT: s_lshr_b32 s0, vcc_lo, 1
-; GFX1064-NEXT: s_bitset1_b32 s0, 31
-; GFX1064-NEXT: s_ff1_i32_b32 s0, s0
-; GFX1064-NEXT: s_cmp_gt_u32 s0, 9
-; GFX1064-NEXT: s_cselect_b64 s[0:1], -1, 0
-; GFX1064-NEXT: s_and_b64 s[0:1], vcc, s[0:1]
-; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], s[0:1]
-; GFX1064-NEXT: ; %bb.1: ; %if.then
-; GFX1064-NEXT: ; divergent unreachable
-; GFX1064-NEXT: ; %bb.2: ; %UnifiedReturnBlock
-; GFX1064-NEXT: s_endpgm
-entry:
- %id = tail call i32 @llvm.amdgcn.workitem.id.x()
- %mul4 = mul nsw i32 %s, %n
- %cmp = icmp slt i32 0, %mul4
- br label %if.end
-
-if.end: ; preds = %entry
- %rem = urem i32 %id, %s
- %icmp = tail call i32 @llvm.amdgcn.icmp.i32.i32(i32 %rem, i32 0, i32 32)
- %shr = lshr i32 %icmp, 1
- %notmask = shl nsw i32 -1, 0
- %and = and i32 %notmask, %shr
- %or = or i32 %and, 2147483648
- %cttz = tail call i32 @llvm.cttz.i32(i32 %or, i1 true)
- %cmp3 = icmp ugt i32 10, %cttz
- %cmp6 = icmp ne i32 %rem, 0
- %brmerge = or i1 %cmp6, %cmp3
- br i1 %brmerge, label %if.end2, label %if.then
-
-if.then: ; preds = %if.end
- unreachable
-
-if.end2: ; preds = %if.end
- ret void
-}
-
-define amdgpu_kernel void @fcmp32(float %n, float %s) #1 {
-; GFX1032-LABEL: fcmp32:
-; GFX1032: ; %bb.0: ; %entry
-; GFX1032-NEXT: s_load_dword s0, s[4:5], 0x28
-; GFX1032-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX1032-NEXT: ; implicit-def: $vgpr1
-; GFX1032-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032-NEXT: v_cmp_ngt_f32_e64 s1, v0, |s0|
-; GFX1032-NEXT: s_and_saveexec_b32 s2, s1
-; GFX1032-NEXT: s_xor_b32 s1, exec_lo, s2
-; GFX1032-NEXT: ; %bb.1: ; %frem.else
-; GFX1032-NEXT: v_and_b32_e32 v1, 0x80000000, v0
-; GFX1032-NEXT: v_cmp_eq_f32_e64 vcc_lo, v0, |s0|
-; GFX1032-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc_lo
-; GFX1032-NEXT: ; implicit-def: $vgpr0
-; GFX1032-NEXT: ; %bb.2: ; %Flow13
-; GFX1032-NEXT: s_andn2_saveexec_b32 s1, s1
-; GFX1032-NEXT: s_cbranch_execz .LBB53_8
-; GFX1032-NEXT: ; %bb.3: ; %frem.compute
-; GFX1032-NEXT: v_frexp_mant_f32_e64 v1, |s0|
-; GFX1032-NEXT: v_frexp_exp_i32_f32_e32 v7, v0
-; GFX1032-NEXT: v_frexp_mant_f32_e32 v8, v0
-; GFX1032-NEXT: v_ldexp_f32 v1, v1, 1
-; GFX1032-NEXT: v_div_scale_f32 v2, s2, v1, v1, 1.0
-; GFX1032-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v1, 1.0
-; GFX1032-NEXT: v_rcp_f32_e32 v3, v2
-; GFX1032-NEXT: v_fma_f32 v4, -v2, v3, 1.0
-; GFX1032-NEXT: v_fmac_f32_e32 v3, v4, v3
-; GFX1032-NEXT: v_mul_f32_e32 v4, v5, v3
-; GFX1032-NEXT: v_fma_f32 v6, -v2, v4, v5
-; GFX1032-NEXT: v_fmac_f32_e32 v4, v6, v3
-; GFX1032-NEXT: v_frexp_exp_i32_f32_e32 v6, s0
-; GFX1032-NEXT: v_fma_f32 v5, -v2, v4, v5
-; GFX1032-NEXT: v_add_nc_u32_e32 v2, -1, v6
-; GFX1032-NEXT: v_div_fmas_f32 v3, v5, v3, v4
-; GFX1032-NEXT: v_xad_u32 v4, v2, -1, v7
-; GFX1032-NEXT: v_ldexp_f32 v5, v8, 12
-; GFX1032-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; GFX1032-NEXT: v_cmp_lt_i32_e32 vcc_lo, 12, v4
-; GFX1032-NEXT: s_and_saveexec_b32 s2, vcc_lo
-; GFX1032-NEXT: s_cbranch_execz .LBB53_7
-; GFX1032-NEXT: ; %bb.4: ; %frem.loop_body.preheader
-; GFX1032-NEXT: v_sub_nc_u32_e32 v4, v7, v6
-; GFX1032-NEXT: s_mov_b32 s3, 0
-; GFX1032-NEXT: v_add_nc_u32_e32 v4, 12, v4
-; GFX1032-NEXT: .LBB53_5: ; %frem.loop_body
-; GFX1032-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1032-NEXT: v_mov_b32_e32 v6, v5
-; GFX1032-NEXT: v_add_nc_u32_e32 v4, -12, v4
-; GFX1032-NEXT: v_mul_f32_e32 v5, v6, v3
-; GFX1032-NEXT: v_rndne_f32_e32 v5, v5
-; GFX1032-NEXT: v_fma_f32 v5, -v5, v1, v6
-; GFX1032-NEXT: v_add_f32_e32 v7, v5, v1
-; GFX1032-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v5
-; GFX1032-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
-; GFX1032-NEXT: v_cmp_gt_i32_e32 vcc_lo, 13, v4
-; GFX1032-NEXT: v_ldexp_f32 v5, v5, 12
-; GFX1032-NEXT: s_or_b32 s3, vcc_lo, s3
-; GFX1032-NEXT: s_andn2_b32 exec_lo, exec_lo, s3
-; GFX1032-NEXT: s_cbranch_execnz .LBB53_5
-; GFX1032-NEXT: ; %bb.6: ; %Flow
-; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s3
-; GFX1032-NEXT: v_mov_b32_e32 v5, v6
-; GFX1032-NEXT: .LBB53_7: ; %Flow12
-; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2
-; GFX1032-NEXT: v_add_nc_u32_e32 v4, -11, v4
-; GFX1032-NEXT: v_ldexp_f32 v4, v5, v4
-; GFX1032-NEXT: v_mul_f32_e32 v3, v4, v3
-; GFX1032-NEXT: v_rndne_f32_e32 v3, v3
-; GFX1032-NEXT: v_fma_f32 v3, -v3, v1, v4
-; GFX1032-NEXT: v_add_f32_e32 v1, v3, v1
-; GFX1032-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
-; GFX1032-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
-; GFX1032-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX1032-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v0
-; GFX1032-NEXT: .LBB53_8: ; %Flow14
-; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX1032-NEXT: v_cmp_lg_f32_e64 vcc_lo, s0, 0
-; GFX1032-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
-; GFX1032-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0
-; GFX1032-NEXT: s_lshr_b32 s0, vcc_lo, 1
-; GFX1032-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v0
-; GFX1032-NEXT: s_bitset1_b32 s0, 31
-; GFX1032-NEXT: s_ff1_i32_b32 s0, s0
-; GFX1032-NEXT: s_cmp_gt_u32 s0, 9
-; GFX1032-NEXT: s_cselect_b32 s0, -1, 0
-; GFX1032-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX1032-NEXT: s_and_saveexec_b32 s1, s0
-; GFX1032-NEXT: ; %bb.9: ; %if.then
-; GFX1032-NEXT: ; divergent unreachable
-; GFX1032-NEXT: ; %bb.10: ; %UnifiedReturnBlock
-; GFX1032-NEXT: s_endpgm
-;
-; GFX1064-LABEL: fcmp32:
-; GFX1064: ; %bb.0: ; %entry
-; GFX1064-NEXT: s_load_dword s6, s[4:5], 0x28
-; GFX1064-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX1064-NEXT: ; implicit-def: $vgpr1
-; GFX1064-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064-NEXT: v_cmp_ngt_f32_e64 s[0:1], v0, |s6|
-; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], s[0:1]
-; GFX1064-NEXT: s_xor_b64 s[0:1], exec, s[2:3]
-; GFX1064-NEXT: ; %bb.1: ; %frem.else
-; GFX1064-NEXT: v_and_b32_e32 v1, 0x80000000, v0
-; GFX1064-NEXT: v_cmp_eq_f32_e64 vcc, v0, |s6|
-; GFX1064-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc
-; GFX1064-NEXT: ; implicit-def: $vgpr0
-; GFX1064-NEXT: ; %bb.2: ; %Flow13
-; GFX1064-NEXT: s_andn2_saveexec_b64 s[0:1], s[0:1]
-; GFX1064-NEXT: s_cbranch_execz .LBB53_8
-; GFX1064-NEXT: ; %bb.3: ; %frem.compute
-; GFX1064-NEXT: v_frexp_mant_f32_e64 v1, |s6|
-; GFX1064-NEXT: v_frexp_exp_i32_f32_e32 v7, v0
-; GFX1064-NEXT: v_frexp_mant_f32_e32 v8, v0
-; GFX1064-NEXT: v_ldexp_f32 v1, v1, 1
-; GFX1064-NEXT: v_div_scale_f32 v2, s[2:3], v1, v1, 1.0
-; GFX1064-NEXT: v_div_scale_f32 v5, vcc, 1.0, v1, 1.0
-; GFX1064-NEXT: v_rcp_f32_e32 v3, v2
-; GFX1064-NEXT: v_fma_f32 v4, -v2, v3, 1.0
-; GFX1064-NEXT: v_fmac_f32_e32 v3, v4, v3
-; GFX1064-NEXT: v_mul_f32_e32 v4, v5, v3
-; GFX1064-NEXT: v_fma_f32 v6, -v2, v4, v5
-; GFX1064-NEXT: v_fmac_f32_e32 v4, v6, v3
-; GFX1064-NEXT: v_frexp_exp_i32_f32_e32 v6, s6
-; GFX1064-NEXT: v_fma_f32 v5, -v2, v4, v5
-; GFX1064-NEXT: v_add_nc_u32_e32 v2, -1, v6
-; GFX1064-NEXT: v_div_fmas_f32 v3, v5, v3, v4
-; GFX1064-NEXT: v_xad_u32 v4, v2, -1, v7
-; GFX1064-NEXT: v_ldexp_f32 v5, v8, 12
-; GFX1064-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
-; GFX1064-NEXT: v_cmp_lt_i32_e32 vcc, 12, v4
-; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], vcc
-; GFX1064-NEXT: s_cbranch_execz .LBB53_7
-; GFX1064-NEXT: ; %bb.4: ; %frem.loop_body.preheader
-; GFX1064-NEXT: v_sub_nc_u32_e32 v4, v7, v6
-; GFX1064-NEXT: s_mov_b64 s[4:5], 0
-; GFX1064-NEXT: v_add_nc_u32_e32 v4, 12, v4
-; GFX1064-NEXT: .LBB53_5: ; %frem.loop_body
-; GFX1064-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX1064-NEXT: v_mov_b32_e32 v6, v5
-; GFX1064-NEXT: v_add_nc_u32_e32 v4, -12, v4
-; GFX1064-NEXT: v_mul_f32_e32 v5, v6, v3
-; GFX1064-NEXT: v_rndne_f32_e32 v5, v5
-; GFX1064-NEXT: v_fma_f32 v5, -v5, v1, v6
-; GFX1064-NEXT: v_add_f32_e32 v7, v5, v1
-; GFX1064-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5
-; GFX1064-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
-; GFX1064-NEXT: v_cmp_gt_i32_e32 vcc, 13, v4
-; GFX1064-NEXT: v_ldexp_f32 v5, v5, 12
-; GFX1064-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
-; GFX1064-NEXT: s_andn2_b64 exec, exec, s[4:5]
-; GFX1064-NEXT: s_cbranch_execnz .LBB53_5
-; GFX1064-NEXT: ; %bb.6: ; %Flow
-; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX1064-NEXT: v_mov_b32_e32 v5, v6
-; GFX1064-NEXT: .LBB53_7: ; %Flow12
-; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX1064-NEXT: v_add_nc_u32_e32 v4, -11, v4
-; GFX1064-NEXT: v_ldexp_f32 v4, v5, v4
-; GFX1064-NEXT: v_mul_f32_e32 v3, v4, v3
-; GFX1064-NEXT: v_rndne_f32_e32 v3, v3
-; GFX1064-NEXT: v_fma_f32 v3, -v3, v1, v4
-; GFX1064-NEXT: v_add_f32_e32 v1, v3, v1
-; GFX1064-NEXT: v_cmp_gt_f32_e32 vcc, 0, v3
-; GFX1064-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; GFX1064-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX1064-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v0
-; GFX1064-NEXT: .LBB53_8: ; %Flow14
-; GFX1064-NEXT: s_or_b64 exec, exec, s[0:1]
-; GFX1064-NEXT: v_cmp_lg_f32_e64 vcc, s6, 0
-; GFX1064-NEXT: v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc
-; GFX1064-NEXT: v_cmp_eq_f32_e32 vcc, 0, v0
-; GFX1064-NEXT: s_lshr_b32 s0, vcc_lo, 1
-; GFX1064-NEXT: v_cmp_nlg_f32_e32 vcc, 0, v0
-; GFX1064-NEXT: s_bitset1_b32 s0, 31
-; GFX1064-NEXT: s_ff1_i32_b32 s0, s0
-; GFX1064-NEXT: s_cmp_gt_u32 s0, 9
-; GFX1064-NEXT: s_cselect_b64 s[0:1], -1, 0
-; GFX1064-NEXT: s_and_b64 s[0:1], vcc, s[0:1]
-; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], s[0:1]
-; GFX1064-NEXT: ; %bb.9: ; %if.then
-; GFX1064-NEXT: ; divergent unreachable
-; GFX1064-NEXT: ; %bb.10: ; %UnifiedReturnBlock
-; GFX1064-NEXT: s_endpgm
-entry:
- %id = tail call i32 @llvm.amdgcn.workitem.id.x()
- %id.f = uitofp i32 %id to float
- %mul4 = fmul float %s, %n
- %cmp = fcmp ult float 0.0, %mul4
- br label %if.end
-
-if.end: ; preds = %entry
- %rem.f = frem float %id.f, %s
- %fcmp = tail call i32 @llvm.amdgcn.fcmp.i32.f32(float %rem.f, float 0.0, i32 1)
- %shr = lshr i32 %fcmp, 1
- %notmask = shl nsw i32 -1, 0
- %and = and i32 %notmask, %shr
- %or = or i32 %and, 2147483648
- %cttz = tail call i32 @llvm.cttz.i32(i32 %or, i1 true)
- %cmp3 = icmp ugt i32 10, %cttz
- %cmp6 = fcmp one float %rem.f, 0.0
- %brmerge = or i1 %cmp6, %cmp3
- br i1 %brmerge, label %if.end2, label %if.then
-
-if.then: ; preds = %if.end
- unreachable
-
-if.end2: ; preds = %if.end
- ret void
-}
-
declare void @external_void_func_void() #1
define void @callee_no_stack_with_call() #1 {
@@ -3183,10 +2459,6 @@ declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32)
declare float @llvm.amdgcn.struct.ptr.buffer.load.f32(ptr addrspace(8), i32, i32, i32, i32 immarg)
declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32)
declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32)
-declare i64 @llvm.amdgcn.fcmp.i64.f32(float, float, i32)
-declare i64 @llvm.amdgcn.icmp.i64.i32(i32, i32, i32)
-declare i32 @llvm.amdgcn.fcmp.i32.f32(float, float, i32)
-declare i32 @llvm.amdgcn.icmp.i32.i32(i32, i32, i32)
declare void @llvm.amdgcn.kill(i1)
declare i1 @llvm.amdgcn.wqm.vote(i1)
declare i1 @llvm.amdgcn.ps.live()
diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll b/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
index 0bedef0d93a59..90e7f8a28af01 100644
--- a/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
+++ b/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
@@ -1851,762 +1851,6 @@ define void @exp_compr_disabled_inputs_to_undef(<2 x half> %xy, <2 x half> %zw)
ret void
}
-; --------------------------------------------------------------------
-; llvm.amdgcn.icmp
-; --------------------------------------------------------------------
-
-declare i64 @llvm.amdgcn.icmp.i64.i32(i32, i32, i32 immarg) nounwind readnone convergent
-declare i64 @llvm.amdgcn.icmp.i64.i64(i64, i64, i32 immarg) nounwind readnone convergent
-declare i64 @llvm.amdgcn.icmp.i64.i1(i1, i1, i32 immarg) nounwind readnone convergent
-
-define i64 @invalid_icmp_code(i32 %a, i32 %b) {
-; CHECK-LABEL: @invalid_icmp_code(
-; CHECK-NEXT: [[UNDER:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[A:%.*]], i32 [[B:%.*]], i32 31)
-; CHECK-NEXT: [[OVER:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[A]], i32 [[B]], i32 42)
-; CHECK-NEXT: [[OR:%.*]] = or i64 [[UNDER]], [[OVER]]
-; CHECK-NEXT: ret i64 [[OR]]
-;
- %under = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %a, i32 %b, i32 31)
- %over = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %a, i32 %b, i32 42)
- %or = or i64 %under, %over
- ret i64 %or
-}
-
-define i64 @icmp_constant_inputs_false() {
-; CHECK-LABEL: @icmp_constant_inputs_false(
-; CHECK-NEXT: ret i64 0
-;
- %result = call i64 @llvm.amdgcn.icmp.i64.i32(i32 9, i32 8, i32 32)
- ret i64 %result
-}
-
-define i64 @icmp_constant_inputs_true() {
-; CHECK-LABEL: @icmp_constant_inputs_true(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 true)
-; CHECK-NEXT: [[RESULT:%.*]] = zext i32 [[TMP1]] to i64
-; CHECK-NEXT: ret i64 [[RESULT]]
-;
- %result = call i64 @llvm.amdgcn.icmp.i64.i32(i32 9, i32 8, i32 34)
- ret i64 %result
-}
-
-define i64 @icmp_constant_to_rhs_slt(i32 %x) {
-; CHECK-LABEL: @icmp_constant_to_rhs_slt(
-; CHECK-NEXT: [[RESULT:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[X:%.*]], i32 9, i32 38)
-; CHECK-NEXT: ret i64 [[RESULT]]
-;
- %result = call i64 @llvm.amdgcn.icmp.i64.i32(i32 9, i32 %x, i32 40)
- ret i64 %result
-}
-
-define i64 @fold_icmp_ne_0_zext_icmp_eq_i32(i32 %a, i32 %b) {
-; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_eq_i32(
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[A:%.*]], i32 [[B:%.*]], i32 32)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp eq i32 %a, %b
- %zext.cmp = zext i1 %cmp to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_ne_0_zext_icmp_ne_i32(i32 %a, i32 %b) {
-; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_ne_i32(
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[A:%.*]], i32 [[B:%.*]], i32 33)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp ne i32 %a, %b
- %zext.cmp = zext i1 %cmp to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_ne_0_zext_icmp_sle_i32(i32 %a, i32 %b) {
-; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_sle_i32(
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[A:%.*]], i32 [[B:%.*]], i32 41)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp sle i32 %a, %b
- %zext.cmp = zext i1 %cmp to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_ne_0_zext_icmp_ugt_i64(i64 %a, i64 %b) {
-; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_ugt_i64(
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i64(i64 [[A:%.*]], i64 [[B:%.*]], i32 34)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp ugt i64 %a, %b
- %zext.cmp = zext i1 %cmp to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_ne_0_zext_icmp_ult_swap_i64(i64 %a, i64 %b) {
-; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_ult_swap_i64(
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i64(i64 [[A:%.*]], i64 [[B:%.*]], i32 34)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp ugt i64 %a, %b
- %zext.cmp = zext i1 %cmp to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 0, i32 %zext.cmp, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_ne_0_zext_fcmp_oeq_f32(float %a, float %b) {
-; CHECK-LABEL: @fold_icmp_ne_0_zext_fcmp_oeq_f32(
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.fcmp.i64.f32(float [[A:%.*]], float [[B:%.*]], i32 1)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = fcmp oeq float %a, %b
- %zext.cmp = zext i1 %cmp to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_ne_0_zext_fcmp_une_f32(float %a, float %b) {
-; CHECK-LABEL: @fold_icmp_ne_0_zext_fcmp_une_f32(
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.fcmp.i64.f32(float [[A:%.*]], float [[B:%.*]], i32 14)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = fcmp une float %a, %b
- %zext.cmp = zext i1 %cmp to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_ne_0_zext_fcmp_olt_f64(double %a, double %b) {
-; CHECK-LABEL: @fold_icmp_ne_0_zext_fcmp_olt_f64(
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.fcmp.i64.f64(double [[A:%.*]], double [[B:%.*]], i32 4)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = fcmp olt double %a, %b
- %zext.cmp = zext i1 %cmp to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_sext_icmp_ne_0_i32(i32 %a, i32 %b) {
-; CHECK-LABEL: @fold_icmp_sext_icmp_ne_0_i32(
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[A:%.*]], i32 [[B:%.*]], i32 32)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp eq i32 %a, %b
- %sext.cmp = sext i1 %cmp to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %sext.cmp, i32 0, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_eq_0_zext_icmp_eq_i32(i32 %a, i32 %b) {
-; CHECK-LABEL: @fold_icmp_eq_0_zext_icmp_eq_i32(
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[A:%.*]], i32 [[B:%.*]], i32 33)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp eq i32 %a, %b
- %zext.cmp = zext i1 %cmp to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 32)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_eq_0_zext_icmp_slt_i32(i32 %a, i32 %b) {
-; CHECK-LABEL: @fold_icmp_eq_0_zext_icmp_slt_i32(
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[A:%.*]], i32 [[B:%.*]], i32 39)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp slt i32 %a, %b
- %zext.cmp = zext i1 %cmp to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 32)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_eq_0_zext_fcmp_oeq_f32(float %a, float %b) {
-; CHECK-LABEL: @fold_icmp_eq_0_zext_fcmp_oeq_f32(
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.fcmp.i64.f32(float [[A:%.*]], float [[B:%.*]], i32 14)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = fcmp oeq float %a, %b
- %zext.cmp = zext i1 %cmp to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 32)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_eq_0_zext_fcmp_ule_f32(float %a, float %b) {
-; CHECK-LABEL: @fold_icmp_eq_0_zext_fcmp_ule_f32(
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.fcmp.i64.f32(float [[A:%.*]], float [[B:%.*]], i32 2)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = fcmp ule float %a, %b
- %zext.cmp = zext i1 %cmp to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 32)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_eq_0_zext_fcmp_ogt_f32(float %a, float %b) {
-; CHECK-LABEL: @fold_icmp_eq_0_zext_fcmp_ogt_f32(
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.fcmp.i64.f32(float [[A:%.*]], float [[B:%.*]], i32 13)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = fcmp ogt float %a, %b
- %zext.cmp = zext i1 %cmp to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 32)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_zext_icmp_eq_1_i32(i32 %a, i32 %b) {
-; CHECK-LABEL: @fold_icmp_zext_icmp_eq_1_i32(
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[A:%.*]], i32 [[B:%.*]], i32 32)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp eq i32 %a, %b
- %zext.cmp = zext i1 %cmp to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 1, i32 32)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_zext_argi1_eq_1_i32(i1 %cond) {
-; CHECK-LABEL: @fold_icmp_zext_argi1_eq_1_i32(
-; CHECK-NEXT: [[ZEXT_COND:%.*]] = zext i1 [[COND:%.*]] to i32
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[ZEXT_COND]], i32 0, i32 33)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %zext.cond = zext i1 %cond to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cond, i32 1, i32 32)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_zext_argi1_eq_neg1_i32(i1 %cond) {
-; CHECK-LABEL: @fold_icmp_zext_argi1_eq_neg1_i32(
-; CHECK-NEXT: [[ZEXT_COND:%.*]] = zext i1 [[COND:%.*]] to i32
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[ZEXT_COND]], i32 -1, i32 32)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %zext.cond = zext i1 %cond to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cond, i32 -1, i32 32)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_sext_argi1_eq_1_i32(i1 %cond) {
-; CHECK-LABEL: @fold_icmp_sext_argi1_eq_1_i32(
-; CHECK-NEXT: [[SEXT_COND:%.*]] = sext i1 [[COND:%.*]] to i32
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[SEXT_COND]], i32 1, i32 32)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %sext.cond = sext i1 %cond to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %sext.cond, i32 1, i32 32)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_sext_argi1_eq_neg1_i32(i1 %cond) {
-; CHECK-LABEL: @fold_icmp_sext_argi1_eq_neg1_i32(
-; CHECK-NEXT: [[SEXT_COND:%.*]] = sext i1 [[COND:%.*]] to i32
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[SEXT_COND]], i32 0, i32 33)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %sext.cond = sext i1 %cond to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %sext.cond, i32 -1, i32 32)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_sext_argi1_eq_neg1_i64(i1 %cond) {
-; CHECK-LABEL: @fold_icmp_sext_argi1_eq_neg1_i64(
-; CHECK-NEXT: [[SEXT_COND:%.*]] = sext i1 [[COND:%.*]] to i64
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i64(i64 [[SEXT_COND]], i64 0, i32 33)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %sext.cond = sext i1 %cond to i64
- %mask = call i64 @llvm.amdgcn.icmp.i64.i64(i64 %sext.cond, i64 -1, i32 32)
- ret i64 %mask
-}
-
-; TODO: Should be able to fold to false
-define i64 @fold_icmp_sext_icmp_eq_1_i32(i32 %a, i32 %b) {
-; CHECK-LABEL: @fold_icmp_sext_icmp_eq_1_i32(
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[SEXT_CMP:%.*]] = sext i1 [[CMP]] to i32
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[SEXT_CMP]], i32 1, i32 32)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp eq i32 %a, %b
- %sext.cmp = sext i1 %cmp to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %sext.cmp, i32 1, i32 32)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_sext_icmp_eq_neg1_i32(i32 %a, i32 %b) {
-; CHECK-LABEL: @fold_icmp_sext_icmp_eq_neg1_i32(
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[A:%.*]], i32 [[B:%.*]], i32 32)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp eq i32 %a, %b
- %sext.cmp = sext i1 %cmp to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %sext.cmp, i32 -1, i32 32)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_sext_icmp_sge_neg1_i32(i32 %a, i32 %b) {
-; CHECK-LABEL: @fold_icmp_sext_icmp_sge_neg1_i32(
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[A:%.*]], i32 [[B:%.*]], i32 39)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp sge i32 %a, %b
- %sext.cmp = sext i1 %cmp to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %sext.cmp, i32 -1, i32 32)
- ret i64 %mask
-}
-
-define i64 @fold_not_icmp_ne_0_zext_icmp_sle_i32(i32 %a, i32 %b) {
-; CHECK-LABEL: @fold_not_icmp_ne_0_zext_icmp_sle_i32(
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[A:%.*]], i32 [[B:%.*]], i32 38)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp sle i32 %a, %b
- %not = xor i1 %cmp, true
- %zext.cmp = zext i1 %not to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_ne_0_zext_icmp_eq_i4(i4 %a, i4 %b) {
-; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_eq_i4(
-; CHECK-NEXT: [[TMP1:%.*]] = zext i4 [[A:%.*]] to i16
-; CHECK-NEXT: [[TMP2:%.*]] = zext i4 [[B:%.*]] to i16
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i16(i16 [[TMP1]], i16 [[TMP2]], i32 32)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp eq i4 %a, %b
- %zext.cmp = zext i1 %cmp to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_ne_0_zext_icmp_eq_i8(i8 %a, i8 %b) {
-; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_eq_i8(
-; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i16
-; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[B:%.*]] to i16
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i16(i16 [[TMP1]], i16 [[TMP2]], i32 32)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp eq i8 %a, %b
- %zext.cmp = zext i1 %cmp to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_ne_0_zext_icmp_eq_i16(i16 %a, i16 %b) {
-; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_eq_i16(
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i16(i16 [[A:%.*]], i16 [[B:%.*]], i32 32)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp eq i16 %a, %b
- %zext.cmp = zext i1 %cmp to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_ne_0_zext_icmp_eq_i36(i36 %a, i36 %b) {
-; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_eq_i36(
-; CHECK-NEXT: [[TMP1:%.*]] = zext i36 [[A:%.*]] to i64
-; CHECK-NEXT: [[TMP2:%.*]] = zext i36 [[B:%.*]] to i64
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i64(i64 [[TMP1]], i64 [[TMP2]], i32 32)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp eq i36 %a, %b
- %zext.cmp = zext i1 %cmp to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_ne_0_zext_icmp_eq_i128(i128 %a, i128 %b) {
-; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_eq_i128(
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i128 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[ZEXT_CMP:%.*]] = zext i1 [[CMP]] to i32
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[ZEXT_CMP]], i32 0, i32 33)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp eq i128 %a, %b
- %zext.cmp = zext i1 %cmp to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_ne_0_zext_fcmp_oeq_f16(half %a, half %b) {
-; CHECK-LABEL: @fold_icmp_ne_0_zext_fcmp_oeq_f16(
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.fcmp.i64.f16(half [[A:%.*]], half [[B:%.*]], i32 1)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = fcmp oeq half %a, %b
- %zext.cmp = zext i1 %cmp to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_ne_0_zext_fcmp_oeq_f128(fp128 %a, fp128 %b) {
-; CHECK-LABEL: @fold_icmp_ne_0_zext_fcmp_oeq_f128(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq fp128 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[ZEXT_CMP:%.*]] = zext i1 [[CMP]] to i32
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[ZEXT_CMP]], i32 0, i32 33)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = fcmp oeq fp128 %a, %b
- %zext.cmp = zext i1 %cmp to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_ne_0_zext_icmp_slt_i4(i4 %a, i4 %b) {
-; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_slt_i4(
-; CHECK-NEXT: [[TMP1:%.*]] = sext i4 [[A:%.*]] to i16
-; CHECK-NEXT: [[TMP2:%.*]] = sext i4 [[B:%.*]] to i16
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i16(i16 [[TMP1]], i16 [[TMP2]], i32 40)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp slt i4 %a, %b
- %zext.cmp = zext i1 %cmp to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_ne_0_zext_icmp_slt_i8(i8 %a, i8 %b) {
-; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_slt_i8(
-; CHECK-NEXT: [[TMP1:%.*]] = sext i8 [[A:%.*]] to i16
-; CHECK-NEXT: [[TMP2:%.*]] = sext i8 [[B:%.*]] to i16
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i16(i16 [[TMP1]], i16 [[TMP2]], i32 40)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp slt i8 %a, %b
- %zext.cmp = zext i1 %cmp to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_ne_0_zext_icmp_slt_i16(i16 %a, i16 %b) {
-; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_slt_i16(
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i16(i16 [[A:%.*]], i16 [[B:%.*]], i32 40)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp slt i16 %a, %b
- %zext.cmp = zext i1 %cmp to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_ne_0_zext_icmp_ult_i4(i4 %a, i4 %b) {
-; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_ult_i4(
-; CHECK-NEXT: [[TMP1:%.*]] = zext i4 [[A:%.*]] to i16
-; CHECK-NEXT: [[TMP2:%.*]] = zext i4 [[B:%.*]] to i16
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i16(i16 [[TMP1]], i16 [[TMP2]], i32 36)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp ult i4 %a, %b
- %zext.cmp = zext i1 %cmp to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_ne_0_zext_icmp_ult_i8(i8 %a, i8 %b) {
-; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_ult_i8(
-; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i16
-; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[B:%.*]] to i16
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i16(i16 [[TMP1]], i16 [[TMP2]], i32 36)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp ult i8 %a, %b
- %zext.cmp = zext i1 %cmp to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_ne_0_zext_icmp_ult_i16(i16 %a, i16 %b) {
-; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_ult_i16(
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i16(i16 [[A:%.*]], i16 [[B:%.*]], i32 36)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp ult i16 %a, %b
- %zext.cmp = zext i1 %cmp to i32
- %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)
- ret i64 %mask
-}
-
-; 1-bit NE comparisons
-
-define i64 @fold_icmp_i1_ne_0_icmp_eq_i1(i32 %a, i32 %b) {
-; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_eq_i1(
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp eq i32 %a, %b
- %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_i1_ne_0_icmp_ne_i1(i32 %a, i32 %b) {
-; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_ne_i1(
-; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp ne i32 %a, %b
- %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_i1_ne_0_icmp_sle_i1(i32 %a, i32 %b) {
-; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_sle_i1(
-; CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp sle i32 %a, %b
- %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_i1_ne_0_icmp_ugt_i64(i64 %a, i64 %b) {
-; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_ugt_i64(
-; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i64 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp ugt i64 %a, %b
- %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_i1_ne_0_icmp_ult_swap_i64(i64 %a, i64 %b) {
-; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_ult_swap_i64(
-; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i64 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp ugt i64 %a, %b
- %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 false, i1 %cmp, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_i1_ne_0_fcmp_oeq_f32(float %a, float %b) {
-; CHECK-LABEL: @fold_icmp_i1_ne_0_fcmp_oeq_f32(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = fcmp oeq float %a, %b
- %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_i1_ne_0_fcmp_une_f32(float %a, float %b) {
-; CHECK-LABEL: @fold_icmp_i1_ne_0_fcmp_une_f32(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp une float [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = fcmp une float %a, %b
- %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_i1_ne_0_fcmp_olt_f64(double %a, double %b) {
-; CHECK-LABEL: @fold_icmp_i1_ne_0_fcmp_olt_f64(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp olt double [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = fcmp olt double %a, %b
- %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_i1_ne_0_icmp_eq_i4(i4 %a, i4 %b) {
-; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_eq_i4(
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i4 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp eq i4 %a, %b
- %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_i1_ne_0_icmp_eq_i8(i8 %a, i8 %b) {
-; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_eq_i8(
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp eq i8 %a, %b
- %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_i1_ne_0_icmp_eq_i16(i16 %a, i16 %b) {
-; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_eq_i16(
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp eq i16 %a, %b
- %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_i1_ne_0_icmp_eq_i36(i36 %a, i36 %b) {
-; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_eq_i36(
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i36 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp eq i36 %a, %b
- %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_i1_ne_0_icmp_eq_i128(i128 %a, i128 %b) {
-; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_eq_i128(
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i128 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp eq i128 %a, %b
- %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_i1_ne_0_fcmp_oeq_f16(half %a, half %b) {
-; CHECK-LABEL: @fold_icmp_i1_ne_0_fcmp_oeq_f16(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq half [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = fcmp oeq half %a, %b
- %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_i1_ne_0_fcmp_oeq_f128(fp128 %a, fp128 %b) {
-; CHECK-LABEL: @fold_icmp_i1_ne_0_fcmp_oeq_f128(
-; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq fp128 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = fcmp oeq fp128 %a, %b
- %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_i1_ne_0_icmp_slt_i4(i4 %a, i4 %b) {
-; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_slt_i4(
-; CHECK-NEXT: [[CMP:%.*]] = icmp slt i4 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp slt i4 %a, %b
- %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_i1_ne_0_icmp_slt_i8(i8 %a, i8 %b) {
-; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_slt_i8(
-; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp slt i8 %a, %b
- %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_i1_ne_0_icmp_slt_i16(i16 %a, i16 %b) {
-; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_slt_i16(
-; CHECK-NEXT: [[CMP:%.*]] = icmp slt i16 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp slt i16 %a, %b
- %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_i1_ne_0_icmp_ult_i4(i4 %a, i4 %b) {
-; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_ult_i4(
-; CHECK-NEXT: [[CMP:%.*]] = icmp ult i4 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp ult i4 %a, %b
- %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_i1_ne_0_icmp_ult_i8(i8 %a, i8 %b) {
-; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_ult_i8(
-; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp ult i8 %a, %b
- %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)
- ret i64 %mask
-}
-
-define i64 @fold_icmp_i1_ne_0_icmp_ult_i16(i16 %a, i16 %b) {
-; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_ult_i16(
-; CHECK-NEXT: [[CMP:%.*]] = icmp ult i16 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)
-; CHECK-NEXT: ret i64 [[MASK]]
-;
- %cmp = icmp ult i16 %a, %b
- %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)
- ret i64 %mask
-}
-
-; --------------------------------------------------------------------
-; llvm.amdgcn.fcmp
-; --------------------------------------------------------------------
-
-declare i64 @llvm.amdgcn.fcmp.i64.f32(float, float, i32 immarg) nounwind readnone convergent
-
-define i64 @invalid_fcmp_code(float %a, float %b) {
-; CHECK-LABEL: @invalid_fcmp_code(
-; CHECK-NEXT: [[UNDER:%.*]] = call i64 @llvm.amdgcn.fcmp.i64.f32(float [[A:%.*]], float [[B:%.*]], i32 -1)
-; CHECK-NEXT: [[OVER:%.*]] = call i64 @llvm.amdgcn.fcmp.i64.f32(float [[A]], float [[B]], i32 16)
-; CHECK-NEXT: [[OR:%.*]] = or i64 [[UNDER]], [[OVER]]
-; CHECK-NEXT: ret i64 [[OR]]
-;
- %under = call i64 @llvm.amdgcn.fcmp.i64.f32(float %a, float %b, i32 -1)
- %over = call i64 @llvm.amdgcn.fcmp.i64.f32(float %a, float %b, i32 16)
- %or = or i64 %under, %over
- ret i64 %or
-}
-
-define i64 @fcmp_constant_inputs_false() {
-; CHECK-LABEL: @fcmp_constant_inputs_false(
-; CHECK-NEXT: ret i64 0
-;
- %result = call i64 @llvm.amdgcn.fcmp.i64.f32(float 2.0, float 4.0, i32 1)
- ret i64 %result
-}
-
-define i64 @fcmp_constant_inputs_true() {
-; CHECK-LABEL: @fcmp_constant_inputs_true(
-; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 true)
-; CHECK-NEXT: [[RESULT:%.*]] = zext i32 [[TMP1]] to i64
-; CHECK-NEXT: ret i64 [[RESULT]]
-;
- %result = call i64 @llvm.amdgcn.fcmp.i64.f32(float 2.0, float 4.0, i32 4)
- ret i64 %result
-}
-
-define i64 @fcmp_constant_to_rhs_olt(float %x) {
-; CHECK-LABEL: @fcmp_constant_to_rhs_olt(
-; CHECK-NEXT: [[RESULT:%.*]] = call i64 @llvm.amdgcn.fcmp.i64.f32(float [[X:%.*]], float 4.000000e+00, i32 2)
-; CHECK-NEXT: ret i64 [[RESULT]]
-;
- %result = call i64 @llvm.amdgcn.fcmp.i64.f32(float 4.0, float %x, i32 4)
- ret i64 %result
-}
-
; --------------------------------------------------------------------
; llvm.amdgcn.ballot
; --------------------------------------------------------------------
diff --git a/llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll b/llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll
index 821e59a9bafb8..9f539b4105577 100644
--- a/llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll
+++ b/llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll
@@ -109,25 +109,6 @@ define void @exp_compr_invalid_inputs(i32 %tgt, i32 %en, i1 %bool) {
ret void
}
-declare i64 @llvm.amdgcn.icmp.i64.i32(i32, i32, i32)
-
-define i64 @invalid_nonconstant_icmp_code(i32 %a, i32 %b, i32 %c) {
- ; CHECK: immarg operand has non-immediate parameter
- ; CHECK-NEXT: i32 %c
- ; CHECK-NEXT: %result = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %a, i32 %b, i32 %c)
- %result = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %a, i32 %b, i32 %c)
- ret i64 %result
-}
-
-declare i64 @llvm.amdgcn.fcmp.i64.f32(float, float, i32)
-define i64 @invalid_nonconstant_fcmp_code(float %a, float %b, i32 %c) {
- ; CHECK: immarg operand has non-immediate parameter
- ; CHECK-NEXT: i32 %c
- ; CHECK-NEXT: %result = call i64 @llvm.amdgcn.fcmp.i64.f32(float %a, float %b, i32 %c)
- %result = call i64 @llvm.amdgcn.fcmp.i64.f32(float %a, float %b, i32 %c)
- ret i64 %result
-}
-
declare { float, i1 } @llvm.amdgcn.div.scale.f32(float, float, i1)
define amdgpu_kernel void @test_div_scale_f32_val_undef_undef(ptr addrspace(1) %out) {
; CHECK: immarg operand has non-immediate parameter
>From 8007f933afbcce551d49d2c30ba374e5f9e4c62f Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Fri, 10 Jul 2026 12:34:35 +0100
Subject: [PATCH 2/2] Auto-upgrade old intrinsics
---
llvm/lib/IR/AutoUpgrade.cpp | 22 ++++++++++++
.../autoupgrade-amdgcn-intrinsics.ll | 35 +++++++++++++++++++
2 files changed, 57 insertions(+)
create mode 100644 llvm/test/Assembler/autoupgrade-amdgcn-intrinsics.ll
diff --git a/llvm/lib/IR/AutoUpgrade.cpp b/llvm/lib/IR/AutoUpgrade.cpp
index 229c7757db3dc..9fefc4e9d337f 100644
--- a/llvm/lib/IR/AutoUpgrade.cpp
+++ b/llvm/lib/IR/AutoUpgrade.cpp
@@ -1414,6 +1414,11 @@ static bool upgradeIntrinsicFunction1(Function *F, Function *&NewFn,
}
}
+ if (Name.starts_with("fcmp.") || Name.starts_with("icmp.")) {
+ NewFn = nullptr;
+ return true;
+ }
+
if (Name.starts_with("ldexp.")) {
// Target specific intrinsic became redundant
NewFn = Intrinsic::getOrInsertDeclaration(
@@ -4926,6 +4931,23 @@ static Value *upgradeAMDGCNIntrinsicCall(StringRef Name, CallBase *CI,
}
}
+ if (Name.starts_with("fcmp.") || Name.starts_with("icmp.")) {
+ Value *LHS = CI->getArgOperand(0);
+ Value *RHS = CI->getArgOperand(1);
+ CmpInst::Predicate Pred = static_cast<CmpInst::Predicate>(
+ cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue());
+ Value *Cmp = Builder.CreateCmp(Pred, LHS, RHS);
+ CallInst *NewCall = Builder.CreateIntrinsicWithoutFolding(
+ CI->getType(), Intrinsic::amdgcn_ballot, Cmp);
+ NewCall->setTailCallKind(cast<CallInst>(CI)->getTailCallKind());
+ NewCall->setCallingConv(CI->getCallingConv());
+ NewCall->setDebugLoc(CI->getDebugLoc());
+ NewCall->copyMetadata(*CI);
+ NewCall->takeName(CI);
+ // TODO: Copy per-argument attributes over to Cmp or NewCall as appropriate.
+ return NewCall;
+ }
+
AtomicRMWInst::BinOp RMWOp =
StringSwitch<AtomicRMWInst::BinOp>(Name)
.StartsWith("ds.fadd", AtomicRMWInst::FAdd)
diff --git a/llvm/test/Assembler/autoupgrade-amdgcn-intrinsics.ll b/llvm/test/Assembler/autoupgrade-amdgcn-intrinsics.ll
new file mode 100644
index 0000000000000..1e8e19b0f87c5
--- /dev/null
+++ b/llvm/test/Assembler/autoupgrade-amdgcn-intrinsics.ll
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -S < %s | FileCheck %s
+
+define i32 @w32_icmp_eq_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: define i32 @w32_icmp_eq_i32(
+; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[X]], [[Y]]
+; CHECK-NEXT: [[RET:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP1]])
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %ret = call i32 @llvm.amdgcn.icmp.i32.i32(i32 %x, i32 %y, i32 32)
+ ret i32 %ret
+}
+
+define i64 @w64_fcmp_ugt_float(float %x, float %y) {
+; CHECK-LABEL: define i64 @w64_fcmp_ugt_float(
+; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) {
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp ugt float [[X]], [[Y]]
+; CHECK-NEXT: [[RET:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP1]])
+; CHECK-NEXT: ret i64 [[RET]]
+;
+ %ret = call i64 @llvm.amdgcn.icmp.i64.f32(float %x, float %y, i32 10)
+ ret i64 %ret
+}
+
+define i32 @w32_fcmp_oge_double(double %x, double %y) {
+; CHECK-LABEL: define i32 @w32_fcmp_oge_double(
+; CHECK-SAME: double [[X:%.*]], double [[Y:%.*]]) {
+; CHECK-NEXT: [[TMP1:%.*]] = fcmp oge double [[X]], [[Y]]
+; CHECK-NEXT: [[RET:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[TMP1]])
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %ret = call i32 @llvm.amdgcn.icmp.i64.f64(double %x, double %y, i32 3)
+ ret i32 %ret
+}
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