[clang] [llvm] [X86] Add ACE v1 (AI Compute Extensions) support (PR #208408)

[via cfe-commits]

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@@ -389,3 +392,65 @@ let Features = "movrs,avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>]
 let Features = "movrs,avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
   def vmovrsw512 : X86Builtin<"_Vector<32, short>(_Vector<32, short const *>)">;
 }
+
+// ACE (AI Compute Extensions) Builtins
+// Tile movement - single builtin handles both immediate and register index forms
+// The lowering code checks if index is constant and selects appropriate instruction
+let Features = "acev1", Attributes = [NoThrow] in {
+  def tilesetcol : X86Builtin<"void(_Constant unsigned char, _Vector<16, int>, unsigned int)">;
+  // ACE tilemovrow writes TO tile (AMX tilemovrow reads FROM tile)
+  def tilesetrow : X86Builtin<"void(_Constant unsigned char, _Vector<16, int>, unsigned int)">;
+}
+
+// Tile movement internal (for IR-level operations)
+let Features = "acev1", Attributes = [NoThrow] in {
+  def tilesetcol_internal : X86Builtin<"_Vector<256, int>(unsigned short, unsigned short, _Vector<16, int>, unsigned int)">;
+  // ACE tilemovrow_to_tile writes TO tile (AMX tilemovrow reads FROM tile)
+  def tilesetrow_internal : X86Builtin<"_Vector<256, int>(unsigned short, unsigned short, _Vector<16, int>, unsigned int)">;
+}
+
+// BSR management
+let Features = "acev1", Attributes = [NoThrow] in {
+  def bsrinit : X86Builtin<"void()">;
+  def bsrmovf : X86Builtin<"void(_Vector<16, int>, _Vector<16, int>)">;
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mahesh-attarde wrote:

Except `bsrinit` we need to add Attribute  RequiredVectorWidth<512>.

https://github.com/llvm/llvm-project/pull/208408