[clang] [llvm] [RISCV] Add support for vector registers with -fzero-call-used-regs (PR #206206)

[Lucas Chollet via cfe-commits]

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@@ -6069,6 +6069,11 @@ foreach lmul = MxList in {
   }
 }
 
+// Used by -fzero-call-used-regs to zero out registers.
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+def PseudoClearVR : Pseudo<(outs VR:$vd), (ins), []>,
+                    PseudoInstExpansion<(VMV_V_I VR:$vd, 0)>;
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LucasChollet wrote:

> Any particular reason why we use a pseudo here instead of emitting a PseudoVMV_V_I directly?

I started to use pseudos to bypass dead code optimizations that would otherwise remove the clearing instructions. I tested your suggestion and vector instructions don't seem to be affected in the same way, so I guess we could emit PseudoVMV_V_I directly if this is preferred.

> I'm not sure if you need to specify uses=[VL, VType] here to prevent the pseudo from getting reordered past the vsetvli

Seems safer to have that, I added it.

https://github.com/llvm/llvm-project/pull/206206