[clang] [llvm] [AArch64] Add initial support for -mcpu=rigel. (PR #208017)
Ricardo Jesus via cfe-commits
cfe-commits at lists.llvm.org
Wed Jul 8 00:55:22 PDT 2026
https://github.com/rj-jesus updated https://github.com/llvm/llvm-project/pull/208017
>From 29c3217f768293988fdd16926bda1ab6518d4776 Mon Sep 17 00:00:00 2001
From: Ricardo Jesus <rjj at nvidia.com>
Date: Thu, 11 Jun 2026 09:57:58 -0700
Subject: [PATCH 1/2] [AArch64] Add initial support for -mcpu=rigel.
This patch adds support for the NVIDIA Rigel core.
This does not add any special tuning decisions, and those may come
later.
---
clang/test/Driver/aarch64-nvidia-rigel.c | 13 +++
.../print-enabled-extensions/aarch64-rigel.c | 81 +++++++++++++++++++
.../Misc/target-invalid-cpu-note/aarch64.c | 1 +
llvm/lib/Target/AArch64/AArch64Processors.td | 4 +
llvm/lib/TargetParser/Host.cpp | 2 +
llvm/test/CodeGen/AArch64/cpus.ll | 1 +
llvm/unittests/TargetParser/Host.cpp | 8 ++
.../TargetParser/TargetParserTest.cpp | 3 +-
8 files changed, 112 insertions(+), 1 deletion(-)
create mode 100644 clang/test/Driver/aarch64-nvidia-rigel.c
create mode 100644 clang/test/Driver/print-enabled-extensions/aarch64-rigel.c
diff --git a/clang/test/Driver/aarch64-nvidia-rigel.c b/clang/test/Driver/aarch64-nvidia-rigel.c
new file mode 100644
index 0000000000000..0f9a62d0f3e2a
--- /dev/null
+++ b/clang/test/Driver/aarch64-nvidia-rigel.c
@@ -0,0 +1,13 @@
+// RUN: %clang --target=aarch64 -mcpu=rigel -### -c %s 2>&1 | FileCheck -check-prefix=rigel %s
+// RUN: %clang --target=aarch64 -mlittle-endian -mcpu=rigel -### -c %s 2>&1 | FileCheck -check-prefix=rigel %s
+// RUN: %clang --target=aarch64 -mtune=rigel -### -c %s 2>&1 | FileCheck -check-prefix=rigel-TUNE %s
+// RUN: %clang --target=aarch64 -mlittle-endian -mtune=rigel -### -c %s 2>&1 | FileCheck -check-prefix=rigel-TUNE %s
+// rigel: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "rigel"
+// rigel-TUNE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" {{.*}} "-tune-cpu" "rigel"
+
+// RUN: %clang --target=arm64 -mcpu=rigel -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-rigel %s
+// RUN: %clang --target=arm64 -mlittle-endian -mcpu=rigel -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-rigel %s
+// RUN: %clang --target=arm64 -mtune=rigel -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-rigel-TUNE %s
+// RUN: %clang --target=arm64 -mlittle-endian -mtune=rigel -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-rigel-TUNE %s
+// ARM64-rigel: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "rigel"
+// ARM64-rigel-TUNE: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "generic" {{.*}} "-tune-cpu" "rigel"
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-rigel.c b/clang/test/Driver/print-enabled-extensions/aarch64-rigel.c
new file mode 100644
index 0000000000000..a8a85a74445e7
--- /dev/null
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-rigel.c
@@ -0,0 +1,81 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=rigel | FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s
+
+// CHECK: Extensions enabled for the given AArch64 target
+// CHECK-EMPTY:
+// CHECK-NEXT: Architecture Feature(s) Description
+// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension
+// CHECK-NEXT: FEAT_AMUv1p1 Enable Armv8.6-A Activity Monitors Virtualization support
+// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
+// CHECK-NEXT: FEAT_BF16 Enable BFloat16 Extension
+// CHECK-NEXT: FEAT_BRBE Enable Branch Record Buffer Extension
+// CHECK-NEXT: FEAT_BTI Enable Branch Target Identification
+// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets
+// CHECK-NEXT: FEAT_CHK Enable Armv8.0-A Check Feature Status Extension
+// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
+// CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction
+// CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions
+// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
+// CHECK-NEXT: FEAT_DPB2 Enable Armv8.5-A Cache Clean to Point of Deep Persistence
+// CHECK-NEXT: FEAT_DotProd Enable dot product support
+// CHECK-NEXT: FEAT_ECV Enable enhanced counter virtualization extension
+// CHECK-NEXT: FEAT_ETE Enable Embedded Trace Extension
+// CHECK-NEXT: FEAT_FAMINMAX Enable FAMIN and FAMAX instructions
+// CHECK-NEXT: FEAT_FCMA Enable Armv8.3-A Floating-point complex number support
+// CHECK-NEXT: FEAT_FGT Enable fine grained virtualization traps extension
+// CHECK-NEXT: FEAT_FHM Enable FP16 FML instructions
+// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
+// CHECK-NEXT: FEAT_FP16 Enable half-precision floating-point data processing
+// CHECK-NEXT: FEAT_FP8 Enable FP8 instructions
+// CHECK-NEXT: FEAT_FP8DOT2 Enable FP8 2-way dot instructions
+// CHECK-NEXT: FEAT_FP8DOT4 Enable FP8 4-way dot instructions
+// CHECK-NEXT: FEAT_FP8FMA Enable Armv9.5-A FP8 multiply-add instructions
+// CHECK-NEXT: FEAT_FPAC Enable Armv8.3-A Pointer Authentication Faulting enhancement
+// CHECK-NEXT: FEAT_FRINTTS Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int
+// CHECK-NEXT: FEAT_FlagM Enable Armv8.4-A Flag Manipulation instructions
+// CHECK-NEXT: FEAT_FlagM2 Enable alternative NZCV format for floating point comparisons
+// CHECK-NEXT: FEAT_HCX Enable Armv8.7-A HCRX_EL2 system register
+// CHECK-NEXT: FEAT_I8MM Enable Matrix Multiply Int8 Extension
+// CHECK-NEXT: FEAT_JSCVT Enable Armv8.3-A JavaScript FP conversion instructions
+// CHECK-NEXT: FEAT_LOR Enable Armv8.1-A Limited Ordering Regions extension
+// CHECK-NEXT: FEAT_LRCPC Enable support for RCPC extension
+// CHECK-NEXT: FEAT_LRCPC2 Enable Armv8.4-A RCPC instructions with Immediate Offsets
+// CHECK-NEXT: FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA Enable Armv8.7-A LD64B/ST64B Accelerator Extension
+// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
+// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
+// CHECK-NEXT: FEAT_LUT Enable Lookup Table instructions
+// CHECK-NEXT: FEAT_MEC Enable Memory Encryption Contexts Extension
+// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension
+// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
+// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement
+// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
+// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
+// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
+// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
+// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
+// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
+// CHECK-NEXT: FEAT_RME Enable Realm Management Extension
+// CHECK-NEXT: FEAT_RNG Enable Random Number generation instructions
+// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier
+// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
+// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
+// CHECK-NEXT: FEAT_SHA3, FEAT_SHA512 Enable SHA512 and SHA3 support
+// CHECK-NEXT: FEAT_SM4, FEAT_SM3 Enable SM3 and SM4 support
+// CHECK-NEXT: FEAT_SPE Enable Statistical Profiling extension
+// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
+// CHECK-NEXT: FEAT_SPEv1p2 Enable extra register in the Statistical Profiling Extension
+// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
+// CHECK-NEXT: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions
+// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions
+// CHECK-NEXT: FEAT_SVE_AES, FEAT_SVE_PMULL128 Enable SVE AES and quadword SVE polynomial multiply instructions
+// CHECK-NEXT: FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions
+// CHECK-NEXT: FEAT_SVE_SHA3 Enable SVE SHA3 instructions
+// CHECK-NEXT: FEAT_SVE_SM4 Enable SVE SM4 instructions
+// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
+// CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension
+// CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension
+// CHECK-NEXT: FEAT_UAO Enable Armv8.2-A UAO PState
+// CHECK-NEXT: FEAT_VHE Enable Armv8.1-A Virtual Host extension
+// CHECK-NEXT: FEAT_WFxT Enable Armv8.7-A WFET and WFIT instruction
+// CHECK-NEXT: FEAT_XS Enable Armv8.7-A limited-TLB-maintenance instruction
diff --git a/clang/test/Misc/target-invalid-cpu-note/aarch64.c b/clang/test/Misc/target-invalid-cpu-note/aarch64.c
index 8bb01fa4bc6d0..74b06db2d4f2f 100644
--- a/clang/test/Misc/target-invalid-cpu-note/aarch64.c
+++ b/clang/test/Misc/target-invalid-cpu-note/aarch64.c
@@ -99,6 +99,7 @@
// CHECK-SAME: {{^}}, neoverse-v3ae
// CHECK-SAME: {{^}}, olympus
// CHECK-SAME: {{^}}, oryon-1
+// CHECK-SAME: {{^}}, rigel
// CHECK-SAME: {{^}}, saphira
// CHECK-SAME: {{^}}, thunderx
// CHECK-SAME: {{^}}, thunderx2t99
diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td
index 1c8d5ec34e71e..8aab8e30b5ce8 100644
--- a/llvm/lib/Target/AArch64/AArch64Processors.td
+++ b/llvm/lib/Target/AArch64/AArch64Processors.td
@@ -1491,6 +1491,10 @@ def : ProcessorModel<"carmel", NoSchedModel, ProcessorFeatures.Carmel,
def : ProcessorModel<"olympus", OlympusModel, ProcessorFeatures.Olympus,
[TuneOlympus]>;
+// NVIDIA Rigel
+def : ProcessorModel<"rigel", OlympusModel, ProcessorFeatures.Olympus,
+ [TuneOlympus]>;
+
// Ampere Computing
def : ProcessorModel<"ampere1", Ampere1Model, ProcessorFeatures.Ampere1,
[TuneAmpere1]>;
diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp
index 4337a7d2dc2c9..a2db5c077698a 100644
--- a/llvm/lib/TargetParser/Host.cpp
+++ b/llvm/lib/TargetParser/Host.cpp
@@ -292,6 +292,8 @@ getHostCPUNameForARMFromComponents(StringRef Implementer, StringRef Hardware,
.Case("0x004", "carmel")
.Case("0x10", "olympus")
.Case("0x010", "olympus")
+ .Case("0x11", "rigel")
+ .Case("0x011", "rigel")
.Default("generic");
}
diff --git a/llvm/test/CodeGen/AArch64/cpus.ll b/llvm/test/CodeGen/AArch64/cpus.ll
index 8bc758a6a432b..05acc429587a5 100644
--- a/llvm/test/CodeGen/AArch64/cpus.ll
+++ b/llvm/test/CodeGen/AArch64/cpus.ll
@@ -4,6 +4,7 @@
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=generic 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=carmel 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=olympus 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=rigel 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a35 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a34 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a53 2>&1 | FileCheck %s
diff --git a/llvm/unittests/TargetParser/Host.cpp b/llvm/unittests/TargetParser/Host.cpp
index 4a63293960c02..62f2278cea66b 100644
--- a/llvm/unittests/TargetParser/Host.cpp
+++ b/llvm/unittests/TargetParser/Host.cpp
@@ -370,6 +370,14 @@ CPU revision : 0
"CPU part : 0x010"),
"olympus");
+ EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x4e\n"
+ "CPU part : 0x11"),
+ "rigel");
+
+ EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x4e\n"
+ "CPU part : 0x011"),
+ "rigel");
+
// Snapdragon mixed implementer quirk
const std::string Snapdragon865ProcCPUInfo = R"(
processor : 0
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index a975c3039e7f4..4d6128ee950f1 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1210,6 +1210,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64CPUTestParams("gb10", "armv9.2-a"),
AArch64CPUTestParams("grace", "armv9-a"),
AArch64CPUTestParams("olympus", "armv9.2-a"),
+ AArch64CPUTestParams("rigel", "armv9.2-a"),
AArch64CPUTestParams("saphira", "armv8.4-a"),
AArch64CPUTestParams("oryon-1", "armv8.6-a")),
AArch64CPUTestParams::PrintToStringParamName);
@@ -1305,7 +1306,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64CPUAliasTestParams::PrintToStringParamName);
// Note: number of CPUs includes aliases.
-static constexpr unsigned NumAArch64CPUArchs = 100;
+static constexpr unsigned NumAArch64CPUArchs = 101;
TEST(TargetParserTest, testAArch64CPUArchList) {
SmallVector<StringRef, NumAArch64CPUArchs> List;
>From c7747dbe109c0f80b02ad3198caf2a7c7e6646c3 Mon Sep 17 00:00:00 2001
From: Ricardo Jesus <rjj at nvidia.com>
Date: Wed, 8 Jul 2026 00:41:25 -0700
Subject: [PATCH 2/2] Add release note.
---
clang/docs/ReleaseNotes.md | 1 +
1 file changed, 1 insertion(+)
diff --git a/clang/docs/ReleaseNotes.md b/clang/docs/ReleaseNotes.md
index cc85604343da9..fad4fee3ac3da 100644
--- a/clang/docs/ReleaseNotes.md
+++ b/clang/docs/ReleaseNotes.md
@@ -960,6 +960,7 @@ latest release, please see the [Clang Web Site](https://clang.llvm.org) or the
- Arm AGI CPU (armagicpu).
- Hisilicon hip12 core (hip12).
+ - NVIDIA Rigel core (rigel).
#### Android Support
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