[clang] [llvm] [CodeGenPrepare] Failure to hoist bitcast to legal type causes register splitting (PR #207568)

[Simon Pilgrim via cfe-commits]

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@@ -1488,6 +1488,61 @@ static bool SinkCast(CastInst *CI) {
   return MadeChange;
 }
 
+/// Hoists bitcasts to the source block to reduce register pressure
+static bool optimizeBitCast(BitCastInst *BCI, const TargetLowering &TLI,
+                            const DataLayout &DL) {
+  auto *SrcInst = dyn_cast<Instruction>(BCI->getOperand(0));
+  if (!SrcInst || SrcInst->getParent() == BCI->getParent() ||
+      SrcInst->isTerminator())
+    return false;
+
+  EVT SrcVT = TLI.getValueType(DL, SrcInst->getType());
+  EVT DestVT = TLI.getValueType(DL, BCI->getType());
+
+  // Bail out on scalable vectors and illegal destination types
+  if (SrcVT.isScalableVector() || DestVT.isScalableVector() ||
+      !TLI.isTypeLegal(DestVT))
+    return false;
+
+  // Only hoist if it reduces physical register count
+  if (TLI.getNumRegisters(BCI->getContext(), SrcVT) <=
+      TLI.getNumRegisters(BCI->getContext(), DestVT))
+    return false;
+
+  // Prevent large cross-domain scalar hoists
+  Type *DestTy = BCI->getType();
+  Type *SrcTy = SrcInst->getType();
+  bool IsCrossDomain = DestTy->isFPOrFPVectorTy() != SrcTy->isFPOrFPVectorTy();
+  bool IsLargeScalar = !DestTy->isVectorTy() &&
+                       DL.getTypeSizeInBits(DestTy).getFixedValue() > 64;
+  if (IsCrossDomain && IsLargeScalar)
+    return false;
+
+  // SelectionDAG Guard to prevent breaking atomic loop layout
+  auto IsAtomic = [](const Value *V) {
+    const auto *I = dyn_cast<Instruction>(V);
+    return I && I->isAtomic();
+  };
----------------
RKSimon wrote:

all of this is scaring me - what regressions did you find that led to this?

https://github.com/llvm/llvm-project/pull/207568