[clang] [llvm] [Clang][RISCV] Add CORE-V (XCV) builtins for CV32E40P (PR #204881)

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VittorioBurani wrote:

@lenary I added cross-project-tests for the CORE-V builtins, one file per header (mac, elw, bitmanip, simd, and alu), modeled on `riscv_packed_simd.c` as you suggested. Each compiles the <riscv_corev_*.h> wrappers at -O2 and
checks the emitted assembly. The alu file covers the already-upstream XCValu extension which had no cross-project test yet.

They are the top commit on this PR right now. Do you want them here, or would you prefer them in a separate follow-up PR?

https://github.com/llvm/llvm-project/pull/204881