[clang] [CIR][test] Use global instcombine RUN line in AArch64 neon add.c (PR #206292)
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Sat Jun 27 18:25:01 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-clang
Author: Vicky Nguyen (iamvickynguyen)
<details>
<summary>Changes</summary>
Related to https://github.com/llvm/llvm-project/issues/185382
Follow-up to https://github.com/llvm/llvm-project/pull/204989
Include `instcombine` into the global LLVM RUN line and remove the separate `LLVM-IC` prefix that only covered the narrowing-addition tests in `clang/test/CodeGen/AArch64/neon/add.c`.
Update LLVM CHECK to match the `instcombine` output: bitcast checks are dropped, the inferred `nsw`/`nuw` flags are added on the widening adds, and unused shuffle operands are canonicalized to `poison`.
---
Patch is 64.78 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/206292.diff
1 Files Affected:
- (modified) clang/test/CodeGen/AArch64/neon/add.c (+298-364)
``````````diff
diff --git a/clang/test/CodeGen/AArch64/neon/add.c b/clang/test/CodeGen/AArch64/neon/add.c
index 7e557dd905068..e9dcddef3093c 100644
--- a/clang/test/CodeGen/AArch64/neon/add.c
+++ b/clang/test/CodeGen/AArch64/neon/add.c
@@ -1,11 +1,8 @@
// REQUIRES: aarch64-registered-target || arm-registered-target
-// RUN: %clang_cc1_cg_arm64_neon -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefix=LLVM
-// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon -fclangir -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefix=LLVM %}
+// RUN: %clang_cc1_cg_arm64_neon -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa,instcombine | FileCheck %s --check-prefix=LLVM
+// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon -fclangir -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa,instcombine | FileCheck %s --check-prefix=LLVM %}
// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon -fclangir -emit-cir %s -disable-O0-optnone | FileCheck %s --check-prefix=CIR %}
-// Narrowing-addition checks use instcombine to fold no-op bitcasts (LLVM-IC prefix).
-// RUN: %clang_cc1_cg_arm64_neon -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa,instcombine | FileCheck %s --check-prefix=LLVM-IC
-// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon -fclangir -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa,instcombine | FileCheck %s --check-prefix=LLVM-IC %}
#include <arm_neon.h>
@@ -278,11 +275,8 @@ poly16x4_t test_vadd_p16(poly16x4_t a, poly16x4_t b) {
// CIR: cir.xor {{.*}} : !cir.vector<8 x !u8i>
// LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]], <4 x i16> {{.*}} [[B:%.*]])
- // LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
- // LLVM-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>
- // LLVM-NEXT: [[TMP2:%.*]] = xor <8 x i8> [[TMP0]], [[TMP1]]
- // LLVM-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>
- // LLVM-NEXT: ret <4 x i16> [[TMP3]]
+ // LLVM: [[TMP0:%.*]] = xor <4 x i16> [[A]], [[B]]
+ // LLVM-NEXT: ret <4 x i16> [[TMP0]]
return vadd_p16(a, b);
}
@@ -292,11 +286,8 @@ poly64x1_t test_vadd_p64(poly64x1_t a, poly64x1_t b) {
// CIR: cir.xor {{.*}} : !cir.vector<8 x !u8i>
// LLVM-SAME: <1 x i64> {{.*}} [[A:%.*]], <1 x i64> {{.*}} [[B:%.*]])
- // LLVM: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>
- // LLVM-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>
- // LLVM-NEXT: [[TMP2:%.*]] = xor <8 x i8> [[TMP0]], [[TMP1]]
- // LLVM-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x i64>
- // LLVM-NEXT: ret <1 x i64> [[TMP3]]
+ // LLVM: [[TMP0:%.*]] = xor <1 x i64> [[A]], [[B]]
+ // LLVM-NEXT: ret <1 x i64> [[TMP0]]
return vadd_p64(a, b);
}
@@ -317,11 +308,8 @@ poly16x8_t test_vaddq_p16(poly16x8_t a, poly16x8_t b) {
// CIR: cir.xor {{.*}} : !cir.vector<16 x !u8i>
// LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]], <8 x i16> {{.*}} [[B:%.*]])
- // LLVM: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
- // LLVM-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>
- // LLVM-NEXT: [[TMP2:%.*]] = xor <16 x i8> [[TMP0]], [[TMP1]]
- // LLVM-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x i16>
- // LLVM-NEXT: ret <8 x i16> [[TMP3]]
+ // LLVM: [[TMP0:%.*]] = xor <8 x i16> [[A]], [[B]]
+ // LLVM-NEXT: ret <8 x i16> [[TMP0]]
return vaddq_p16(a, b);
}
@@ -331,11 +319,8 @@ poly64x2_t test_vaddq_p64(poly64x2_t a, poly64x2_t b) {
// CIR: cir.xor {{.*}} : !cir.vector<16 x !u8i>
// LLVM-SAME: <2 x i64> {{.*}} [[A:%.*]], <2 x i64> {{.*}} [[B:%.*]])
- // LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>
- // LLVM-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>
- // LLVM-NEXT: [[TMP2:%.*]] = xor <16 x i8> [[TMP0]], [[TMP1]]
- // LLVM-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64>
- // LLVM-NEXT: ret <2 x i64> [[TMP3]]
+ // LLVM: [[TMP0:%.*]] = xor <2 x i64> [[A]], [[B]]
+ // LLVM-NEXT: ret <2 x i64> [[TMP0]]
return vaddq_p64(a, b);
}
@@ -345,11 +330,8 @@ poly128_t test_vaddq_p128(poly128_t a, poly128_t b) {
// CIR: cir.xor {{.*}} : !cir.vector<16 x !u8i>
// LLVM-SAME: i128 {{.*}} [[A:%.*]], i128 {{.*}} [[B:%.*]])
- // LLVM: [[TMP0:%.*]] = bitcast i128 [[A]] to <16 x i8>
- // LLVM-NEXT: [[TMP1:%.*]] = bitcast i128 [[B]] to <16 x i8>
- // LLVM-NEXT: [[TMP2:%.*]] = xor <16 x i8> [[TMP0]], [[TMP1]]
- // LLVM-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP2]] to i128
- // LLVM-NEXT: ret i128 [[TMP3]]
+ // LLVM: [[TMP0:%.*]] = xor i128 [[A]], [[B]]
+ // LLVM-NEXT: ret i128 [[TMP0]]
return vaddq_p128(a, b);
}
@@ -366,7 +348,7 @@ int16x8_t test_vaddl_s8(int8x8_t a, int8x8_t b) {
// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]], <8 x i8> {{.*}} [[B:%.*]])
// LLVM: [[VMOVL_I5_I:%.*]] = sext <8 x i8> [[A]] to <8 x i16>
// LLVM-NEXT: [[VMOVL_I_I:%.*]] = sext <8 x i8> [[B]] to <8 x i16>
- // LLVM-NEXT: [[ADD_I:%.*]] = add <8 x i16> [[VMOVL_I5_I]], [[VMOVL_I_I]]
+ // LLVM-NEXT: [[ADD_I:%.*]] = add nsw <8 x i16> [[VMOVL_I5_I]], [[VMOVL_I_I]]
// LLVM-NEXT: ret <8 x i16> [[ADD_I]]
return vaddl_s8(a, b);
}
@@ -377,13 +359,9 @@ int32x4_t test_vaddl_s16(int16x4_t a, int16x4_t b) {
// CIR: cir.add {{.*}} : !cir.vector<4 x !s32i>
// LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]], <4 x i16> {{.*}} [[B:%.*]])
- // LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
- // LLVM-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
- // LLVM-NEXT: [[VMOVL_I5_I:%.*]] = sext <4 x i16> [[TMP1]] to <4 x i32>
- // LLVM-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>
- // LLVM-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>
- // LLVM-NEXT: [[VMOVL_I_I:%.*]] = sext <4 x i16> [[TMP3]] to <4 x i32>
- // LLVM-NEXT: [[ADD_I:%.*]] = add <4 x i32> [[VMOVL_I5_I]], [[VMOVL_I_I]]
+ // LLVM: [[VMOVL_I5_I:%.*]] = sext <4 x i16> [[A]] to <4 x i32>
+ // LLVM-NEXT: [[VMOVL_I_I:%.*]] = sext <4 x i16> [[B]] to <4 x i32>
+ // LLVM-NEXT: [[ADD_I:%.*]] = add nsw <4 x i32> [[VMOVL_I5_I]], [[VMOVL_I_I]]
// LLVM-NEXT: ret <4 x i32> [[ADD_I]]
return vaddl_s16(a, b);
}
@@ -394,13 +372,9 @@ int64x2_t test_vaddl_s32(int32x2_t a, int32x2_t b) {
// CIR: cir.add {{.*}} : !cir.vector<2 x !s64i>
// LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]], <2 x i32> {{.*}} [[B:%.*]])
- // LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>
- // LLVM-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
- // LLVM-NEXT: [[VMOVL_I5_I:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64>
- // LLVM-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>
- // LLVM-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32>
- // LLVM-NEXT: [[VMOVL_I_I:%.*]] = sext <2 x i32> [[TMP3]] to <2 x i64>
- // LLVM-NEXT: [[ADD_I:%.*]] = add <2 x i64> [[VMOVL_I5_I]], [[VMOVL_I_I]]
+ // LLVM: [[VMOVL_I5_I:%.*]] = sext <2 x i32> [[A]] to <2 x i64>
+ // LLVM-NEXT: [[VMOVL_I_I:%.*]] = sext <2 x i32> [[B]] to <2 x i64>
+ // LLVM-NEXT: [[ADD_I:%.*]] = add nsw <2 x i64> [[VMOVL_I5_I]], [[VMOVL_I_I]]
// LLVM-NEXT: ret <2 x i64> [[ADD_I]]
return vaddl_s32(a, b);
}
@@ -413,7 +387,7 @@ uint16x8_t test_vaddl_u8(uint8x8_t a, uint8x8_t b) {
// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]], <8 x i8> {{.*}} [[B:%.*]])
// LLVM: [[VMOVL_I5_I:%.*]] = zext <8 x i8> [[A]] to <8 x i16>
// LLVM-NEXT: [[VMOVL_I_I:%.*]] = zext <8 x i8> [[B]] to <8 x i16>
- // LLVM-NEXT: [[ADD_I:%.*]] = add <8 x i16> [[VMOVL_I5_I]], [[VMOVL_I_I]]
+ // LLVM-NEXT: [[ADD_I:%.*]] = add nuw nsw <8 x i16> [[VMOVL_I5_I]], [[VMOVL_I_I]]
// LLVM-NEXT: ret <8 x i16> [[ADD_I]]
return vaddl_u8(a, b);
}
@@ -424,13 +398,9 @@ uint32x4_t test_vaddl_u16(uint16x4_t a, uint16x4_t b) {
// CIR: cir.add {{.*}} : !cir.vector<4 x !u32i>
// LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]], <4 x i16> {{.*}} [[B:%.*]])
- // LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
- // LLVM-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
- // LLVM-NEXT: [[VMOVL_I5_I:%.*]] = zext <4 x i16> [[TMP1]] to <4 x i32>
- // LLVM-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>
- // LLVM-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>
- // LLVM-NEXT: [[VMOVL_I_I:%.*]] = zext <4 x i16> [[TMP3]] to <4 x i32>
- // LLVM-NEXT: [[ADD_I:%.*]] = add <4 x i32> [[VMOVL_I5_I]], [[VMOVL_I_I]]
+ // LLVM: [[VMOVL_I5_I:%.*]] = zext <4 x i16> [[A]] to <4 x i32>
+ // LLVM-NEXT: [[VMOVL_I_I:%.*]] = zext <4 x i16> [[B]] to <4 x i32>
+ // LLVM-NEXT: [[ADD_I:%.*]] = add nuw nsw <4 x i32> [[VMOVL_I5_I]], [[VMOVL_I_I]]
// LLVM-NEXT: ret <4 x i32> [[ADD_I]]
return vaddl_u16(a, b);
}
@@ -441,13 +411,9 @@ uint64x2_t test_vaddl_u32(uint32x2_t a, uint32x2_t b) {
// CIR: cir.add {{.*}} : !cir.vector<2 x !u64i>
// LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]], <2 x i32> {{.*}} [[B:%.*]])
- // LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>
- // LLVM-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
- // LLVM-NEXT: [[VMOVL_I5_I:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
- // LLVM-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>
- // LLVM-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32>
- // LLVM-NEXT: [[VMOVL_I_I:%.*]] = zext <2 x i32> [[TMP3]] to <2 x i64>
- // LLVM-NEXT: [[ADD_I:%.*]] = add <2 x i64> [[VMOVL_I5_I]], [[VMOVL_I_I]]
+ // LLVM: [[VMOVL_I5_I:%.*]] = zext <2 x i32> [[A]] to <2 x i64>
+ // LLVM-NEXT: [[VMOVL_I_I:%.*]] = zext <2 x i32> [[B]] to <2 x i64>
+ // LLVM-NEXT: [[ADD_I:%.*]] = add nuw nsw <2 x i64> [[VMOVL_I5_I]], [[VMOVL_I_I]]
// LLVM-NEXT: ret <2 x i64> [[ADD_I]]
return vaddl_u32(a, b);
}
@@ -458,11 +424,11 @@ int16x8_t test_vaddl_high_s8(int8x16_t a, int8x16_t b) {
// CIR: cir.add {{.*}} : !cir.vector<8 x !s16i>
// LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]], <16 x i8> {{.*}} [[B:%.*]])
- // LLVM: [[SHUFFLE_I_I12_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ // LLVM: [[SHUFFLE_I_I12_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// LLVM-NEXT: [[TMP0:%.*]] = sext <8 x i8> [[SHUFFLE_I_I12_I]] to <8 x i16>
- // LLVM-NEXT: [[SHUFFLE_I_I_I:%.*]] = shufflevector <16 x i8> [[B]], <16 x i8> [[B]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ // LLVM-NEXT: [[SHUFFLE_I_I_I:%.*]] = shufflevector <16 x i8> [[B]], <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// LLVM-NEXT: [[TMP1:%.*]] = sext <8 x i8> [[SHUFFLE_I_I_I]] to <8 x i16>
- // LLVM-NEXT: [[ADD_I:%.*]] = add <8 x i16> [[TMP0]], [[TMP1]]
+ // LLVM-NEXT: [[ADD_I:%.*]] = add nsw <8 x i16> [[TMP0]], [[TMP1]]
// LLVM-NEXT: ret <8 x i16> [[ADD_I]]
return vaddl_high_s8(a, b);
}
@@ -473,15 +439,11 @@ int32x4_t test_vaddl_high_s16(int16x8_t a, int16x8_t b) {
// CIR: cir.add {{.*}} : !cir.vector<4 x !s32i>
// LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]], <8 x i16> {{.*}} [[B:%.*]])
- // LLVM: [[SHUFFLE_I_I12_I:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> [[A]], <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- // LLVM-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I_I12_I]] to <8 x i8>
- // LLVM-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
- // LLVM-NEXT: [[TMP2:%.*]] = sext <4 x i16> [[TMP1]] to <4 x i32>
- // LLVM-NEXT: [[SHUFFLE_I_I_I:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> [[B]], <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- // LLVM-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[SHUFFLE_I_I_I]] to <8 x i8>
- // LLVM-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x i16>
- // LLVM-NEXT: [[TMP5:%.*]] = sext <4 x i16> [[TMP4]] to <4 x i32>
- // LLVM-NEXT: [[ADD_I:%.*]] = add <4 x i32> [[TMP2]], [[TMP5]]
+ // LLVM: [[SHUFFLE_I_I12_I:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ // LLVM-NEXT: [[TMP0:%.*]] = sext <4 x i16> [[SHUFFLE_I_I12_I]] to <4 x i32>
+ // LLVM-NEXT: [[SHUFFLE_I_I_I:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ // LLVM-NEXT: [[TMP1:%.*]] = sext <4 x i16> [[SHUFFLE_I_I_I]] to <4 x i32>
+ // LLVM-NEXT: [[ADD_I:%.*]] = add nsw <4 x i32> [[TMP0]], [[TMP1]]
// LLVM-NEXT: ret <4 x i32> [[ADD_I]]
return vaddl_high_s16(a, b);
}
@@ -492,15 +454,11 @@ int64x2_t test_vaddl_high_s32(int32x4_t a, int32x4_t b) {
// CIR: cir.add {{.*}} : !cir.vector<2 x !s64i>
// LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]], <4 x i32> {{.*}} [[B:%.*]])
- // LLVM: [[SHUFFLE_I_I12_I:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> [[A]], <2 x i32> <i32 2, i32 3>
- // LLVM-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I_I12_I]] to <8 x i8>
- // LLVM-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
- // LLVM-NEXT: [[TMP2:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64>
- // LLVM-NEXT: [[SHUFFLE_I_I_I:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> [[B]], <2 x i32> <i32 2, i32 3>
- // LLVM-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[SHUFFLE_I_I_I]] to <8 x i8>
- // LLVM-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x i32>
- // LLVM-NEXT: [[TMP5:%.*]] = sext <2 x i32> [[TMP4]] to <2 x i64>
- // LLVM-NEXT: [[ADD_I:%.*]] = add <2 x i64> [[TMP2]], [[TMP5]]
+ // LLVM: [[SHUFFLE_I_I12_I:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> poison, <2 x i32> <i32 2, i32 3>
+ // LLVM-NEXT: [[TMP0:%.*]] = sext <2 x i32> [[SHUFFLE_I_I12_I]] to <2 x i64>
+ // LLVM-NEXT: [[SHUFFLE_I_I_I:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> poison, <2 x i32> <i32 2, i32 3>
+ // LLVM-NEXT: [[TMP1:%.*]] = sext <2 x i32> [[SHUFFLE_I_I_I]] to <2 x i64>
+ // LLVM-NEXT: [[ADD_I:%.*]] = add nsw <2 x i64> [[TMP0]], [[TMP1]]
// LLVM-NEXT: ret <2 x i64> [[ADD_I]]
return vaddl_high_s32(a, b);
}
@@ -511,11 +469,11 @@ uint16x8_t test_vaddl_high_u8(uint8x16_t a, uint8x16_t b) {
// CIR: cir.add {{.*}} : !cir.vector<8 x !u16i>
// LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]], <16 x i8> {{.*}} [[B:%.*]])
- // LLVM: [[SHUFFLE_I_I12_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ // LLVM: [[SHUFFLE_I_I12_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// LLVM-NEXT: [[TMP0:%.*]] = zext <8 x i8> [[SHUFFLE_I_I12_I]] to <8 x i16>
- // LLVM-NEXT: [[SHUFFLE_I_I_I:%.*]] = shufflevector <16 x i8> [[B]], <16 x i8> [[B]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ // LLVM-NEXT: [[SHUFFLE_I_I_I:%.*]] = shufflevector <16 x i8> [[B]], <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// LLVM-NEXT: [[TMP1:%.*]] = zext <8 x i8> [[SHUFFLE_I_I_I]] to <8 x i16>
- // LLVM-NEXT: [[ADD_I:%.*]] = add <8 x i16> [[TMP0]], [[TMP1]]
+ // LLVM-NEXT: [[ADD_I:%.*]] = add nuw nsw <8 x i16> [[TMP0]], [[TMP1]]
// LLVM-NEXT: ret <8 x i16> [[ADD_I]]
return vaddl_high_u8(a, b);
}
@@ -526,15 +484,11 @@ uint32x4_t test_vaddl_high_u16(uint16x8_t a, uint16x8_t b) {
// CIR: cir.add {{.*}} : !cir.vector<4 x !u32i>
// LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]], <8 x i16> {{.*}} [[B:%.*]])
- // LLVM: [[SHUFFLE_I_I12_I:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> [[A]], <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- // LLVM-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I_I12_I]] to <8 x i8>
- // LLVM-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
- // LLVM-NEXT: [[TMP2:%.*]] = zext <4 x i16> [[TMP1]] to <4 x i32>
- // LLVM-NEXT: [[SHUFFLE_I_I_I:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> [[B]], <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- // LLVM-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[SHUFFLE_I_I_I]] to <8 x i8>
- // LLVM-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP3]] to <4 x i16>
- // LLVM-NEXT: [[TMP5:%.*]] = zext <4 x i16> [[TMP4]] to <4 x i32>
- // LLVM-NEXT: [[ADD_I:%.*]] = add <4 x i32> [[TMP2]], [[TMP5]]
+ // LLVM: [[SHUFFLE_I_I12_I:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ // LLVM-NEXT: [[TMP0:%.*]] = zext <4 x i16> [[SHUFFLE_I_I12_I]] to <4 x i32>
+ // LLVM-NEXT: [[SHUFFLE_I_I_I:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ // LLVM-NEXT: [[TMP1:%.*]] = zext <4 x i16> [[SHUFFLE_I_I_I]] to <4 x i32>
+ // LLVM-NEXT: [[ADD_I:%.*]] = add nuw nsw <4 x i32> [[TMP0]], [[TMP1]]
// LLVM-NEXT: ret <4 x i32> [[ADD_I]]
return vaddl_high_u16(a, b);
}
@@ -545,15 +499,11 @@ uint64x2_t test_vaddl_high_u32(uint32x4_t a, uint32x4_t b) {
// CIR: cir.add {{.*}} : !cir.vector<2 x !u64i>
// LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]], <4 x i32> {{.*}} [[B:%.*]])
- // LLVM: [[SHUFFLE_I_I12_I:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> [[A]], <2 x i32> <i32 2, i32 3>
- // LLVM-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I_I12_I]] to <8 x i8>
- // LLVM-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
- // LLVM-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
- // LLVM-NEXT: [[SHUFFLE_I_I_I:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> [[B]], <2 x i32> <i32 2, i32 3>
- // LLVM-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[SHUFFLE_I_I_I]] to <8 x i8>
- // LLVM-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP3]] to <2 x i32>
- // LLVM-NEXT: [[TMP5:%.*]] = zext <2 x i32> [[TMP4]] to <2 x i64>
- // LLVM-NEXT: [[ADD_I:%.*]] = add <2 x i64> [[TMP2]], [[TMP5]]
+ // LLVM: [[SHUFFLE_I_I12_I:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> poison, <2 x i32> <i32 2, i32 3>
+ // LLVM-NEXT: [[TMP0:%.*]] = zext <2 x i32> [[SHUFFLE_I_I12_I]] to <2 x i64>
+ // LLVM-NEXT: [[SHUFFLE_I_I_I:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> poison, <2 x i32> <i32 2, i32 3>
+ // LLVM-NEXT: [[TMP1:%.*]] = zext <2 x i32> [[SHUFFLE_I_I_I]] to <2 x i64>
+ // LLVM-NEXT: [[ADD_I:%.*]] = add nuw nsw <2 x i64> [[TMP0]], [[TMP1]]
// LLVM-NEXT: ret <2 x i64> [[ADD_I]]
return vaddl_high_u32(a, b);
}
@@ -576,9 +526,7 @@ int32x4_t test_vaddw_s16(int32x4_t a, int16x4_t b) {
// CIR: cir.add {{.*}} : !cir.vector<4 x !s32i>
// LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]], <4 x i16> {{.*}} [[B:%.*]])
- // LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>
- // LLVM-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
- // LLVM-NEXT: [[VMOVL_I_I:%.*]] = sext <4 x i16> [[TMP1]] to <4 x i32>
+ // LLVM: [[VMOVL_I_I:%.*]] = sext <4 x i16> [[B]] to <4 x i32>
// LLVM-NEXT: [[ADD_I:%.*]] = add <4 x i32> [[A]], [[VMOVL_I_I]]
// LLVM-NEXT: ret <4 x i32> [[ADD_I]]
return vaddw_s16(a, b);
@@ -590,9 +538,7 @@ int64x2_t test_vaddw_s32(int64x2_t a, int32x2_t b) {
// CIR: cir.add {{.*}} : !cir.vector<2 x !s64i>
// LLVM-SAME: <2 x i64> {{.*}} [[A:%.*]], <2 x i32> {{.*}} [[B:%.*]])
- // LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>
- // LLVM-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
- // LLVM-NEXT: [[VMOVL_I_I:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64>
+ // LLVM: [[VMOVL_I_I:%.*]] = sext <2 x i32> [[B]] to <2 x i64>
// LLVM-NEXT: [[ADD_I:%.*]] = add <2 x i64> [[A]], [[VMOVL_I_I]]
// LLVM-NEXT: ret <2 x i64> [[ADD_I]]
return vaddw_s32(a, b);
@@ -616,9 +562,7 @@ uint32x4_t test_vaddw_u16(uint32x4_t a, uint16x4_t b) {
// CIR: cir.add {{.*}} : !cir.vector<4 x !u32i>
// LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]], <4 x i16> {{.*}} [[B:%.*]])
- // LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>
- // LLVM-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
- // LLVM-NEXT: [[VMOVL_I_I:%.*]] = zext <4 x i16> [[TMP1]] to <4 x i32>
+ // LLVM: [[VMOVL_I_I:%.*]] = zext <4 x i16> [[B]] to <4 x i32>
// LLVM-NEXT: [[ADD_I:%.*]] = add <4 x i32> [[A]...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/206292
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