[clang] [llvm] [OpenMP][Offload] Use argument pointer array in host kernels (PR #205355)
Piotr Balcer via cfe-commits
cfe-commits at lists.llvm.org
Tue Jun 23 07:17:09 PDT 2026
https://github.com/pbalcer created https://github.com/llvm/llvm-project/pull/205355
This is a follow-up to #194333, which changed liboffload's kernel launch interface to take an array of pointers to arguments instead of a contiguous argument buffer, but left the old path intact for OpenMP, to be cleaned up iteratively in later changes.
This patch modifies the offload host kernels, and the OpenMP clang codegen, to also use argument pointer arrays. The host was the only plugin that did not support the new submission path. With it converted, OpenMP can migrate to use the new path in all scenarios, after which everything related to contiguous argument buffer and its construction can be removed from plugin interface and the backends.
The change itself is fairly straightforward. The bulk of the diff is automated test updates. In the runtime, the host kernel signature becomes an array of pointers (void **), and the codegen is updated to match. With each argument being a pointer, the kernel function now adds one load to read the argument's value.
Assisted-by: Claude
>From 5b4415e21255f8a560ba8d98024365c48604edf8 Mon Sep 17 00:00:00 2001
From: Piotr Balcer <piotr.balcer at intel.com>
Date: Wed, 10 Jun 2026 12:06:21 +0000
Subject: [PATCH] [OpenMP][Offload] Use argument pointer array in host kernels
This is a follow-up to #194333, which changed liboffload's kernel launch
interface to take an array of pointers to arguments instead of a
contiguous argument buffer, but left the old path intact for OpenMP,
to be cleaned up iteratively in later changes.
This patch modifies the offload host kernels, and the OpenMP clang
codegen, to also use argument pointer arrays. The host was the only
plugin that did not support the new submission path. With it converted,
OpenMP can migrate to use the new path in all scenarios, after which
everything related to contiguous argument buffer and its construction
can be removed from plugin interface and the backends.
The change itself is fairly straightforward. The bulk of the diff
is automated test updates. In the runtime, the host kernel
signature becomes an array of pointers (void **), and the codegen
is updated to match. With each argument being a pointer, the kernel
function now adds one load to read the argument's value.
Assisted-by: Claude
---
clang/lib/CodeGen/CGStmtOpenMP.cpp | 35 +-
clang/test/OpenMP/distribute_codegen.cpp | 150 +-
clang/test/OpenMP/distribute_simd_codegen.cpp | 328 ++-
.../target_dyn_groupprivate_codegen.cpp | 278 ++-
.../OpenMP/target_firstprivate_codegen.cpp | 1068 +++++----
.../target_ompx_dyn_cgroup_mem_codegen.cpp | 278 ++-
clang/test/OpenMP/target_parallel_codegen.cpp | 560 +++--
.../OpenMP/target_parallel_for_codegen.cpp | 644 +++---
.../target_parallel_for_simd_codegen.cpp | 2002 ++++++++--------
...target_parallel_generic_loop_codegen-2.cpp | 80 +-
.../OpenMP/target_parallel_if_codegen.cpp | 266 ++-
.../target_parallel_num_threads_codegen.cpp | 250 +-
...et_parallel_num_threads_strict_codegen.cpp | 380 ++--
clang/test/OpenMP/target_private_codegen.cpp | 5 +-
.../OpenMP/target_task_affinity_codegen.cpp | 162 +-
clang/test/OpenMP/target_teams_codegen.cpp | 860 +++----
.../target_teams_distribute_codegen.cpp | 760 ++++---
..._teams_distribute_parallel_for_codegen.cpp | 150 +-
...bute_parallel_for_firstprivate_codegen.cpp | 216 +-
...istribute_parallel_for_private_codegen.cpp | 25 +-
...s_distribute_parallel_for_simd_codegen.cpp | 196 +-
...parallel_for_simd_firstprivate_codegen.cpp | 216 +-
...bute_parallel_for_simd_private_codegen.cpp | 25 +-
.../target_teams_distribute_simd_codegen.cpp | 2010 +++++++++--------
.../target_teams_generic_loop_codegen-1.cpp | 150 +-
...get_teams_generic_loop_private_codegen.cpp | 25 +-
.../test/OpenMP/target_teams_map_codegen.cpp | 296 +--
.../OpenMP/target_teams_num_teams_codegen.cpp | 250 +-
.../target_teams_thread_limit_codegen.cpp | 268 ++-
clang/test/OpenMP/teams_codegen.cpp | 156 +-
offload/plugins-nextgen/host/src/rtl.cpp | 7 +-
31 files changed, 6683 insertions(+), 5413 deletions(-)
diff --git a/clang/lib/CodeGen/CGStmtOpenMP.cpp b/clang/lib/CodeGen/CGStmtOpenMP.cpp
index 314f4e14dd1d2..95fd6694437fe 100644
--- a/clang/lib/CodeGen/CGStmtOpenMP.cpp
+++ b/clang/lib/CodeGen/CGStmtOpenMP.cpp
@@ -751,8 +751,7 @@ static llvm::Function *emitOutlinedFunctionPrologueAggregate(
Address ContextAddr = CGF.GetAddrOfLocalVar(CD->getContextParam());
ContextV = CGF.Builder.CreateLoad(ContextAddr);
- // The runtime passes arguments as a flat array of promoted intptr_t values.
- llvm::Type *IntPtrTy = CGF.IntPtrTy;
+ // The runtime passes arguments as an array of pointers.
llvm::Type *PtrTy = CGF.Builder.getPtrTy();
llvm::Align PtrAlign = CGM.getDataLayout().getPointerABIAlignment(0);
CharUnits SlotAlign = CharUnits::fromQuantity(PtrAlign.value());
@@ -760,11 +759,12 @@ static llvm::Function *emitOutlinedFunctionPrologueAggregate(
for (auto [FD, C, FieldIdx] :
llvm::zip(RD->fields(), CS.captures(),
llvm::seq<unsigned>(RD->getNumFields()))) {
- llvm::Value *Slot =
- CGF.Builder.CreateConstInBoundsGEP1_32(IntPtrTy, ContextV, FieldIdx);
+ llvm::Value *SlotPtr =
+ CGF.Builder.CreateConstInBoundsGEP1_32(PtrTy, ContextV, FieldIdx);
+ llvm::Value *Slot = CGF.Builder.CreateAlignedLoad(PtrTy, SlotPtr, PtrAlign);
- // Generate the appropriate load from the GEP into the __context struct.
- // This includes all of the user arguments as well as the implicit kernel
+ // Generate the appropriate load from the per-argument storage. This
+ // includes all of the user arguments as well as the implicit kernel
// argument pointer.
if (C.capturesVariableByCopy() && FD->getType()->isAnyPointerType()) {
const VarDecl *CurVD = C.getCapturedVar();
@@ -973,11 +973,14 @@ llvm::Function *CodeGenFunction::GenerateOpenMPCapturedStmtFunctionAggregate(
const ImplicitParamDecl *Param = CD->getParam(I);
if (Param == CD->getContextParam())
continue;
- llvm::Value *ParamAddr = Builder.CreateConstInBoundsGEP1_32(
- IntPtrTy, ContextV, FieldIdx, Twine(Param->getName()) + ".addr");
+ llvm::Align PtrAlign = CGM.getDataLayout().getPointerABIAlignment(0);
+ llvm::Value *SlotPtr = Builder.CreateConstInBoundsGEP1_32(
+ Builder.getPtrTy(), ContextV, FieldIdx,
+ Twine(Param->getName()) + ".addr");
+ llvm::Value *ParamAddr =
+ Builder.CreateAlignedLoad(Builder.getPtrTy(), SlotPtr, PtrAlign);
llvm::Value *ParamVal = Builder.CreateAlignedLoad(
- Builder.getPtrTy(), ParamAddr,
- CGM.getDataLayout().getPointerABIAlignment(0), Param->getName());
+ Builder.getPtrTy(), ParamAddr, PtrAlign, Param->getName());
Address ParamLocalAddr =
CreateMemTemp(Param->getType(), Param->getName());
Builder.CreateStore(ParamVal, ParamLocalAddr);
@@ -1016,8 +1019,10 @@ llvm::Function *CodeGenFunction::GenerateOpenMPCapturedStmtFunctionAggregate(
for (auto [FD, InnerParam, SlotIdx] : llvm::zip(
RD->fields(), F->args(), llvm::seq<unsigned>(RD->getNumFields()))) {
- llvm::Value *Slot = WrapperCGF.Builder.CreateConstInBoundsGEP1_32(
- WrapperCGF.IntPtrTy, WrapperContextV, SlotIdx);
+ llvm::Value *SlotPtr = WrapperCGF.Builder.CreateConstInBoundsGEP1_32(
+ WrapperCGF.Builder.getPtrTy(), WrapperContextV, SlotIdx);
+ llvm::Value *Slot = WrapperCGF.Builder.CreateAlignedLoad(
+ WrapperCGF.Builder.getPtrTy(), SlotPtr, PtrAlign);
llvm::Value *Val = WrapperCGF.Builder.CreateAlignedLoad(
InnerParam.getType(), Slot, PtrAlign, InnerParam.getName());
CallArgs.push_back(Val);
@@ -1026,8 +1031,10 @@ llvm::Function *CodeGenFunction::GenerateOpenMPCapturedStmtFunctionAggregate(
// Handle the load from the implicit dyn_ptr at the end of the __context.
unsigned SlotIdx = RD->getNumFields();
auto InnerParam = F->arg_begin() + SlotIdx;
- llvm::Value *Slot = WrapperCGF.Builder.CreateConstInBoundsGEP1_32(
- WrapperCGF.IntPtrTy, WrapperContextV, SlotIdx);
+ llvm::Value *SlotPtr = WrapperCGF.Builder.CreateConstInBoundsGEP1_32(
+ WrapperCGF.Builder.getPtrTy(), WrapperContextV, SlotIdx);
+ llvm::Value *Slot = WrapperCGF.Builder.CreateAlignedLoad(
+ WrapperCGF.Builder.getPtrTy(), SlotPtr, PtrAlign);
llvm::Value *Val = WrapperCGF.Builder.CreateAlignedLoad(
InnerParam->getType(), Slot, PtrAlign, InnerParam->getName());
CallArgs.push_back(Val);
diff --git a/clang/test/OpenMP/distribute_codegen.cpp b/clang/test/OpenMP/distribute_codegen.cpp
index afd18e91911dd..f5b9a3a5d7c9e 100644
--- a/clang/test/OpenMP/distribute_codegen.cpp
+++ b/clang/test/OpenMP/distribute_codegen.cpp
@@ -2033,12 +2033,17 @@ int fint(void) { return ftemplate<int>(); }
// CHECK17-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK17-NEXT: [[C:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK17-NEXT: [[D:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK17-NEXT: [[A:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK17-NEXT: [[B:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK17-NEXT: [[C:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK17-NEXT: [[D:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK17-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
// CHECK17-NEXT: ret void
@@ -2145,12 +2150,17 @@ int fint(void) { return ftemplate<int>(); }
// CHECK17-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK17-NEXT: [[C:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK17-NEXT: [[D:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK17-NEXT: [[A:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK17-NEXT: [[B:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK17-NEXT: [[C:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK17-NEXT: [[D:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK17-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
// CHECK17-NEXT: ret void
@@ -2257,12 +2267,17 @@ int fint(void) { return ftemplate<int>(); }
// CHECK17-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK17-NEXT: [[C:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK17-NEXT: [[D:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK17-NEXT: [[A:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK17-NEXT: [[B:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK17-NEXT: [[C:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK17-NEXT: [[D:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK17-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
// CHECK17-NEXT: ret void
@@ -2387,11 +2402,13 @@ int fint(void) { return ftemplate<int>(); }
// CHECK17-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK17-NEXT: [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 8
-// CHECK17-NEXT: store i8 [[TMP2]], ptr [[A]], align 1
-// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i8, ptr [[TMP2]], align 8
+// CHECK17-NEXT: store i8 [[TMP3]], ptr [[A]], align 1
+// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 8
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92.omp_outlined, ptr [[A]])
// CHECK17-NEXT: ret void
@@ -2498,11 +2515,13 @@ int fint(void) { return ftemplate<int>(); }
// CHECK17-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK17-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 8
-// CHECK17-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
-// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 8
+// CHECK17-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
+// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 8
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108.omp_outlined, ptr [[AA]])
// CHECK17-NEXT: ret void
@@ -2597,12 +2616,17 @@ int fint(void) { return ftemplate<int>(); }
// CHECK19-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK19-NEXT: [[C:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK19-NEXT: [[D:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK19-NEXT: [[A:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK19-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK19-NEXT: [[B:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK19-NEXT: [[C:%.*]] = load ptr, ptr [[TMP3]], align 4
+// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK19-NEXT: [[D:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK19-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l56.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
// CHECK19-NEXT: ret void
@@ -2705,12 +2729,17 @@ int fint(void) { return ftemplate<int>(); }
// CHECK19-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK19-NEXT: [[C:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK19-NEXT: [[D:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK19-NEXT: [[A:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK19-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK19-NEXT: [[B:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK19-NEXT: [[C:%.*]] = load ptr, ptr [[TMP3]], align 4
+// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK19-NEXT: [[D:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK19-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l68.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
// CHECK19-NEXT: ret void
@@ -2813,12 +2842,17 @@ int fint(void) { return ftemplate<int>(); }
// CHECK19-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK19-NEXT: [[C:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK19-NEXT: [[D:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK19-NEXT: [[A:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK19-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK19-NEXT: [[B:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK19-NEXT: [[C:%.*]] = load ptr, ptr [[TMP3]], align 4
+// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK19-NEXT: [[D:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK19-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l80.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
// CHECK19-NEXT: ret void
@@ -2939,11 +2973,13 @@ int fint(void) { return ftemplate<int>(); }
// CHECK19-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK19-NEXT: [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 4
-// CHECK19-NEXT: store i8 [[TMP2]], ptr [[A]], align 1
-// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = load i8, ptr [[TMP2]], align 4
+// CHECK19-NEXT: store i8 [[TMP3]], ptr [[A]], align 1
+// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 4
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l92.omp_outlined, ptr [[A]])
// CHECK19-NEXT: ret void
@@ -3050,11 +3086,13 @@ int fint(void) { return ftemplate<int>(); }
// CHECK19-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK19-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 4
-// CHECK19-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
-// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 4
+// CHECK19-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
+// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 4
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l108.omp_outlined, ptr [[AA]])
// CHECK19-NEXT: ret void
diff --git a/clang/test/OpenMP/distribute_simd_codegen.cpp b/clang/test/OpenMP/distribute_simd_codegen.cpp
index 329978c9a01e6..a160bc5b0b5ac 100644
--- a/clang/test/OpenMP/distribute_simd_codegen.cpp
+++ b/clang/test/OpenMP/distribute_simd_codegen.cpp
@@ -5627,12 +5627,17 @@ int fint(void) { return ftemplate<int>(); }
// CHECK17-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK17-NEXT: [[C:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK17-NEXT: [[D:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK17-NEXT: [[A:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK17-NEXT: [[B:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK17-NEXT: [[C:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK17-NEXT: [[D:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK17-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
// CHECK17-NEXT: ret void
@@ -5748,12 +5753,17 @@ int fint(void) { return ftemplate<int>(); }
// CHECK17-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK17-NEXT: [[C:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK17-NEXT: [[D:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK17-NEXT: [[A:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK17-NEXT: [[B:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK17-NEXT: [[C:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK17-NEXT: [[D:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK17-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
// CHECK17-NEXT: ret void
@@ -5867,12 +5877,17 @@ int fint(void) { return ftemplate<int>(); }
// CHECK17-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK17-NEXT: [[C:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK17-NEXT: [[D:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK17-NEXT: [[A:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK17-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK17-NEXT: [[B:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK17-NEXT: [[C:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK17-NEXT: [[D:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK17-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
// CHECK17-NEXT: ret void
@@ -6005,14 +6020,17 @@ int fint(void) { return ftemplate<int>(); }
// CHECK17-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK17-NEXT: [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 8
-// CHECK17-NEXT: store i8 [[TMP2]], ptr [[I]], align 1
-// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK17-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 8
-// CHECK17-NEXT: store i8 [[TMP4]], ptr [[A]], align 1
-// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i8, ptr [[TMP2]], align 8
+// CHECK17-NEXT: store i8 [[TMP3]], ptr [[I]], align 1
+// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK17-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK17-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 8
+// CHECK17-NEXT: store i8 [[TMP6]], ptr [[A]], align 1
+// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK17-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 8
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I]], ptr [[A]])
// CHECK17-NEXT: ret void
@@ -6140,11 +6158,13 @@ int fint(void) { return ftemplate<int>(); }
// CHECK17-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK17-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 8
-// CHECK17-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
-// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 8
+// CHECK17-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
+// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 8
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA]])
// CHECK17-NEXT: ret void
@@ -6246,12 +6266,17 @@ int fint(void) { return ftemplate<int>(); }
// CHECK19-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK19-NEXT: [[C:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK19-NEXT: [[D:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK19-NEXT: [[A:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK19-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK19-NEXT: [[B:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK19-NEXT: [[C:%.*]] = load ptr, ptr [[TMP3]], align 4
+// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK19-NEXT: [[D:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK19-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
// CHECK19-NEXT: ret void
@@ -6363,12 +6388,17 @@ int fint(void) { return ftemplate<int>(); }
// CHECK19-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK19-NEXT: [[C:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK19-NEXT: [[D:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK19-NEXT: [[A:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK19-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK19-NEXT: [[B:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK19-NEXT: [[C:%.*]] = load ptr, ptr [[TMP3]], align 4
+// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK19-NEXT: [[D:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK19-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
// CHECK19-NEXT: ret void
@@ -6478,12 +6508,17 @@ int fint(void) { return ftemplate<int>(); }
// CHECK19-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK19-NEXT: [[C:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK19-NEXT: [[D:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK19-NEXT: [[A:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK19-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK19-NEXT: [[B:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK19-NEXT: [[C:%.*]] = load ptr, ptr [[TMP3]], align 4
+// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK19-NEXT: [[D:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK19-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
// CHECK19-NEXT: ret void
@@ -6612,14 +6647,17 @@ int fint(void) { return ftemplate<int>(); }
// CHECK19-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK19-NEXT: [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 4
-// CHECK19-NEXT: store i8 [[TMP2]], ptr [[I]], align 1
-// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK19-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 4
-// CHECK19-NEXT: store i8 [[TMP4]], ptr [[A]], align 1
-// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = load i8, ptr [[TMP2]], align 4
+// CHECK19-NEXT: store i8 [[TMP3]], ptr [[I]], align 1
+// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK19-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK19-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 4
+// CHECK19-NEXT: store i8 [[TMP6]], ptr [[A]], align 1
+// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 4
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I]], ptr [[A]])
// CHECK19-NEXT: ret void
@@ -6747,11 +6785,13 @@ int fint(void) { return ftemplate<int>(); }
// CHECK19-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK19-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 4
-// CHECK19-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
-// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 4
+// CHECK19-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
+// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 4
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA]])
// CHECK19-NEXT: ret void
@@ -6853,12 +6893,17 @@ int fint(void) { return ftemplate<int>(); }
// CHECK21-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK21-NEXT: [[B:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK21-NEXT: [[C:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK21-NEXT: [[D:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK21-NEXT: [[A:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK21-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK21-NEXT: [[B:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK21-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK21-NEXT: [[C:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK21-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK21-NEXT: [[D:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK21-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
// CHECK21-NEXT: ret void
@@ -6974,12 +7019,17 @@ int fint(void) { return ftemplate<int>(); }
// CHECK21-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK21-NEXT: [[B:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK21-NEXT: [[C:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK21-NEXT: [[D:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK21-NEXT: [[A:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK21-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK21-NEXT: [[B:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK21-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK21-NEXT: [[C:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK21-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK21-NEXT: [[D:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK21-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
// CHECK21-NEXT: ret void
@@ -7093,12 +7143,17 @@ int fint(void) { return ftemplate<int>(); }
// CHECK21-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK21-NEXT: [[B:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK21-NEXT: [[C:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK21-NEXT: [[D:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK21-NEXT: [[A:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK21-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK21-NEXT: [[B:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK21-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK21-NEXT: [[C:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK21-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK21-NEXT: [[D:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK21-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
// CHECK21-NEXT: ret void
@@ -7231,14 +7286,17 @@ int fint(void) { return ftemplate<int>(); }
// CHECK21-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK21-NEXT: [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 8
-// CHECK21-NEXT: store i8 [[TMP2]], ptr [[I]], align 1
-// CHECK21-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK21-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 8
-// CHECK21-NEXT: store i8 [[TMP4]], ptr [[A]], align 1
-// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK21-NEXT: [[TMP3:%.*]] = load i8, ptr [[TMP2]], align 8
+// CHECK21-NEXT: store i8 [[TMP3]], ptr [[I]], align 1
+// CHECK21-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK21-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK21-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 8
+// CHECK21-NEXT: store i8 [[TMP6]], ptr [[A]], align 1
+// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK21-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 8
// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I]], ptr [[A]])
// CHECK21-NEXT: ret void
@@ -7397,11 +7455,13 @@ int fint(void) { return ftemplate<int>(); }
// CHECK21-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK21-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 8
-// CHECK21-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
-// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK21-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 8
+// CHECK21-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
+// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK21-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 8
// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA]])
// CHECK21-NEXT: ret void
@@ -7503,12 +7563,17 @@ int fint(void) { return ftemplate<int>(); }
// CHECK23-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK23-NEXT: [[B:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK23-NEXT: [[C:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK23-NEXT: [[D:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK23-NEXT: [[A:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK23-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK23-NEXT: [[B:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK23-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK23-NEXT: [[C:%.*]] = load ptr, ptr [[TMP3]], align 4
+// CHECK23-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK23-NEXT: [[D:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK23-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z23without_schedule_clausePfS_S_S__l70.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
// CHECK23-NEXT: ret void
@@ -7620,12 +7685,17 @@ int fint(void) { return ftemplate<int>(); }
// CHECK23-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK23-NEXT: [[B:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK23-NEXT: [[C:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK23-NEXT: [[D:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK23-NEXT: [[A:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK23-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK23-NEXT: [[B:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK23-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK23-NEXT: [[C:%.*]] = load ptr, ptr [[TMP3]], align 4
+// CHECK23-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK23-NEXT: [[D:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK23-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18static_not_chunkedPfS_S_S__l86.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
// CHECK23-NEXT: ret void
@@ -7735,12 +7805,17 @@ int fint(void) { return ftemplate<int>(); }
// CHECK23-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK23-NEXT: [[B:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK23-NEXT: [[C:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK23-NEXT: [[D:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK23-NEXT: [[A:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK23-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK23-NEXT: [[B:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK23-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK23-NEXT: [[C:%.*]] = load ptr, ptr [[TMP3]], align 4
+// CHECK23-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK23-NEXT: [[D:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK23-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14static_chunkedPfS_S_S__l103.omp_outlined, ptr [[A]], ptr [[B]], ptr [[C]], ptr [[D]])
// CHECK23-NEXT: ret void
@@ -7869,14 +7944,17 @@ int fint(void) { return ftemplate<int>(); }
// CHECK23-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK23-NEXT: [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 4
-// CHECK23-NEXT: store i8 [[TMP2]], ptr [[I]], align 1
-// CHECK23-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK23-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 4
-// CHECK23-NEXT: store i8 [[TMP4]], ptr [[A]], align 1
-// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK23-NEXT: [[TMP3:%.*]] = load i8, ptr [[TMP2]], align 4
+// CHECK23-NEXT: store i8 [[TMP3]], ptr [[I]], align 1
+// CHECK23-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK23-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK23-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 4
+// CHECK23-NEXT: store i8 [[TMP6]], ptr [[A]], align 1
+// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK23-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 4
// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z12test_precondv_l115.omp_outlined, ptr [[I]], ptr [[A]])
// CHECK23-NEXT: ret void
@@ -8035,11 +8113,13 @@ int fint(void) { return ftemplate<int>(); }
// CHECK23-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK23-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 4
-// CHECK23-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
-// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK23-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 4
+// CHECK23-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
+// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK23-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 4
// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_v_l135.omp_outlined, ptr [[AA]])
// CHECK23-NEXT: ret void
diff --git a/clang/test/OpenMP/target_dyn_groupprivate_codegen.cpp b/clang/test/OpenMP/target_dyn_groupprivate_codegen.cpp
index 353686c9d9953..7501c51faac3e 100644
--- a/clang/test/OpenMP/target_dyn_groupprivate_codegen.cpp
+++ b/clang/test/OpenMP/target_dyn_groupprivate_codegen.cpp
@@ -969,7 +969,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META32]]
// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META32]]
// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META32]]
-// CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]]) #[[ATTR2]]
+// CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]]) #[[ATTR2]], !inline_history [[META33:![0-9]+]]
// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META32]]
// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META32]]
// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META32]]
@@ -1900,7 +1900,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META33]]
// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META33]]
// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META33]]
-// CHECK3-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]]) #[[ATTR2]]
+// CHECK3-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]]) #[[ATTR2]], !inline_history [[META34:![0-9]+]]
// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias [[META33]]
// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias [[META33]]
// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias [[META33]]
@@ -2020,24 +2020,28 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK9-NEXT: store i32 [[TMP3]], ptr [[N]], align 4
-// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
-// CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
+// CHECK9-NEXT: store i32 [[TMP4]], ptr [[N]], align 4
+// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 8
-// CHECK9-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8
+// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 8
+// CHECK9-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP11]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 8
-// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP8]], i32 0)
-// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[N]], align 4
-// CHECK9-NEXT: store i32 [[TMP9]], ptr [[N_CASTED]], align 4
-// CHECK9-NEXT: [[TMP10:%.*]] = load i64, ptr [[N_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l71.omp_outlined, i64 [[TMP10]])
+// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP12]], i32 0)
+// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[N]], align 4
+// CHECK9-NEXT: store i32 [[TMP13]], ptr [[N_CASTED]], align 4
+// CHECK9-NEXT: [[TMP14:%.*]] = load i64, ptr [[N_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l71.omp_outlined, i64 [[TMP14]])
// CHECK9-NEXT: ret void
//
//
@@ -2255,11 +2259,13 @@ int bar(int n){
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK9-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK9-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l75.omp_outlined)
// CHECK9-NEXT: ret void
@@ -2285,21 +2291,25 @@ int bar(int n){
// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK9-NEXT: store i32 [[TMP3]], ptr [[B]], align 4
-// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
-// CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: store i32 [[TMP5]], ptr [[B]], align 4
+// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
+// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 8
+// CHECK9-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK9-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP9]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[B]], align 4
-// CHECK9-NEXT: store i32 [[TMP6]], ptr [[B_CASTED]], align 4
-// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[B_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l88.omp_outlined, ptr [[THIS]], i64 [[TMP7]])
+// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[B]], align 4
+// CHECK9-NEXT: store i32 [[TMP10]], ptr [[B_CASTED]], align 4
+// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[B_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l88.omp_outlined, ptr [[THIS]], i64 [[TMP11]])
// CHECK9-NEXT: ret void
//
//
@@ -2330,10 +2340,12 @@ int bar(int n){
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 8
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP3]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS]], i32 0, i32 0
// CHECK9-NEXT: store double 2.500000e+00, ptr [[A]], align 8
@@ -2347,8 +2359,9 @@ int bar(int n){
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP1]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l55.omp_outlined)
// CHECK9-NEXT: ret void
@@ -2377,28 +2390,32 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
-// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 8
-// CHECK9-NEXT: store i16 [[TMP5]], ptr [[B]], align 2
-// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
+// CHECK9-NEXT: store i32 [[TMP4]], ptr [[A]], align 4
+// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 8
-// CHECK9-NEXT: store i16 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 2
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: store i16 [[TMP7]], ptr [[B]], align 2
+// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8
+// CHECK9-NEXT: [[TMP10:%.*]] = load i16, ptr [[TMP9]], align 8
+// CHECK9-NEXT: store i16 [[TMP10]], ptr [[DOTCAPTURE_EXPR_]], align 2
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP11]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP8:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2
-// CHECK9-NEXT: [[TMP9:%.*]] = sext i16 [[TMP8]] to i32
-// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP9]], i32 0)
-// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
-// CHECK9-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
-// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP12:%.*]] = load i16, ptr [[B]], align 2
-// CHECK9-NEXT: store i16 [[TMP12]], ptr [[B_CASTED]], align 2
-// CHECK9-NEXT: [[TMP13:%.*]] = load i64, ptr [[B_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l60.omp_outlined, i64 [[TMP11]], i64 [[TMP13]])
+// CHECK9-NEXT: [[TMP12:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2
+// CHECK9-NEXT: [[TMP13:%.*]] = sext i16 [[TMP12]] to i32
+// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP13]], i32 0)
+// CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4
+// CHECK9-NEXT: store i32 [[TMP14]], ptr [[A_CASTED]], align 4
+// CHECK9-NEXT: [[TMP15:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK9-NEXT: [[TMP16:%.*]] = load i16, ptr [[B]], align 2
+// CHECK9-NEXT: store i16 [[TMP16]], ptr [[B_CASTED]], align 2
+// CHECK9-NEXT: [[TMP17:%.*]] = load i64, ptr [[B_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l60.omp_outlined, i64 [[TMP15]], i64 [[TMP17]])
// CHECK9-NEXT: ret void
//
//
@@ -2433,24 +2450,28 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK11-NEXT: store i32 [[TMP3]], ptr [[N]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK11-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
+// CHECK11-NEXT: store i32 [[TMP4]], ptr [[N]], align 4
+// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
-// CHECK11-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 4
+// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
+// CHECK11-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK11-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP11]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 4
-// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP8]], i32 0)
-// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[N]], align 4
-// CHECK11-NEXT: store i32 [[TMP9]], ptr [[N_CASTED]], align 4
-// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[N_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l71.omp_outlined, i32 [[TMP10]])
+// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP12]], i32 0)
+// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[N]], align 4
+// CHECK11-NEXT: store i32 [[TMP13]], ptr [[N_CASTED]], align 4
+// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[N_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l71.omp_outlined, i32 [[TMP14]])
// CHECK11-NEXT: ret void
//
//
@@ -2664,11 +2685,13 @@ int bar(int n){
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK11-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK11-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l75.omp_outlined)
// CHECK11-NEXT: ret void
@@ -2694,21 +2717,25 @@ int bar(int n){
// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK11-NEXT: store i32 [[TMP3]], ptr [[B]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK11-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: store i32 [[TMP5]], ptr [[B]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
+// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
+// CHECK11-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP9]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[B]], align 4
-// CHECK11-NEXT: store i32 [[TMP6]], ptr [[B_CASTED]], align 4
-// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[B_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l88.omp_outlined, ptr [[THIS]], i32 [[TMP7]])
+// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[B]], align 4
+// CHECK11-NEXT: store i32 [[TMP10]], ptr [[B_CASTED]], align 4
+// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[B_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l88.omp_outlined, ptr [[THIS]], i32 [[TMP11]])
// CHECK11-NEXT: ret void
//
//
@@ -2739,10 +2766,12 @@ int bar(int n){
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP3]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS]], i32 0, i32 0
// CHECK11-NEXT: store double 2.500000e+00, ptr [[A]], align 4
@@ -2756,8 +2785,9 @@ int bar(int n){
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP1]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l55.omp_outlined)
// CHECK11-NEXT: ret void
@@ -2786,28 +2816,32 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 4
-// CHECK11-NEXT: store i16 [[TMP5]], ptr [[B]], align 2
-// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
+// CHECK11-NEXT: store i32 [[TMP4]], ptr [[A]], align 4
+// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 4
-// CHECK11-NEXT: store i16 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 2
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: store i16 [[TMP7]], ptr [[B]], align 2
+// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 4
+// CHECK11-NEXT: [[TMP10:%.*]] = load i16, ptr [[TMP9]], align 4
+// CHECK11-NEXT: store i16 [[TMP10]], ptr [[DOTCAPTURE_EXPR_]], align 2
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK11-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP11]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP8:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2
-// CHECK11-NEXT: [[TMP9:%.*]] = sext i16 [[TMP8]] to i32
-// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP9]], i32 0)
-// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
-// CHECK11-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP12:%.*]] = load i16, ptr [[B]], align 2
-// CHECK11-NEXT: store i16 [[TMP12]], ptr [[B_CASTED]], align 2
-// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l60.omp_outlined, i32 [[TMP11]], i32 [[TMP13]])
+// CHECK11-NEXT: [[TMP12:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2
+// CHECK11-NEXT: [[TMP13:%.*]] = sext i16 [[TMP12]] to i32
+// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP13]], i32 0)
+// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4
+// CHECK11-NEXT: store i32 [[TMP14]], ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP16:%.*]] = load i16, ptr [[B]], align 2
+// CHECK11-NEXT: store i16 [[TMP16]], ptr [[B_CASTED]], align 2
+// CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[B_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l60.omp_outlined, i32 [[TMP15]], i32 [[TMP17]])
// CHECK11-NEXT: ret void
//
//
diff --git a/clang/test/OpenMP/target_firstprivate_codegen.cpp b/clang/test/OpenMP/target_firstprivate_codegen.cpp
index 57c35327b234d..aba714e973e05 100644
--- a/clang/test/OpenMP/target_firstprivate_codegen.cpp
+++ b/clang/test/OpenMP/target_firstprivate_codegen.cpp
@@ -10161,15 +10161,19 @@ int bar(int n, double *ptr) {
// TCHECK-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// TCHECK-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// TCHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// TCHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// TCHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// TCHECK-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// TCHECK-NEXT: [[P:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// TCHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// TCHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
-// TCHECK-NEXT: store i32 [[TMP4]], ptr [[GA]], align 4
-// TCHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// TCHECK-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// TCHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// TCHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// TCHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// TCHECK-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// TCHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// TCHECK-NEXT: [[P:%.*]] = load ptr, ptr [[TMP4]], align 8
+// TCHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// TCHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8
+// TCHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 8
+// TCHECK-NEXT: store i32 [[TMP7]], ptr [[GA]], align 4
+// TCHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// TCHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// TCHECK-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP8]], align 8
// TCHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// TCHECK-NEXT: ret void
//
@@ -10189,46 +10193,56 @@ int bar(int n, double *ptr) {
// TCHECK-NEXT: [[D5:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
// TCHECK-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// TCHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// TCHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// TCHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 8
-// TCHECK-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
-// TCHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// TCHECK-NEXT: [[B:%.*]] = load ptr, ptr [[TMP3]], align 8
-// TCHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// TCHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8
-// TCHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// TCHECK-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP6]], align 8
-// TCHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// TCHECK-NEXT: [[C:%.*]] = load ptr, ptr [[TMP7]], align 8
-// TCHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
-// TCHECK-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8
-// TCHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 6
-// TCHECK-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
-// TCHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 7
-// TCHECK-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP12]], align 8
-// TCHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 8
-// TCHECK-NEXT: [[D:%.*]] = load ptr, ptr [[TMP13]], align 8
-// TCHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 9
-// TCHECK-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// TCHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// TCHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// TCHECK-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 8
+// TCHECK-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
+// TCHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// TCHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// TCHECK-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 8
+// TCHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// TCHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
+// TCHECK-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP7]], align 8
+// TCHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// TCHECK-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8
+// TCHECK-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP10]], align 8
+// TCHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// TCHECK-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8
+// TCHECK-NEXT: [[C:%.*]] = load ptr, ptr [[TMP12]], align 8
+// TCHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// TCHECK-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8
+// TCHECK-NEXT: [[TMP15:%.*]] = load i64, ptr [[TMP14]], align 8
+// TCHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 6
+// TCHECK-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8
+// TCHECK-NEXT: [[TMP18:%.*]] = load i64, ptr [[TMP17]], align 8
+// TCHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 7
+// TCHECK-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8
+// TCHECK-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP20]], align 8
+// TCHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 8
+// TCHECK-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 8
+// TCHECK-NEXT: [[D:%.*]] = load ptr, ptr [[TMP22]], align 8
+// TCHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 9
+// TCHECK-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// TCHECK-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP23]], align 8
// TCHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B2]], ptr align 4 [[B]], i64 40, i1 false)
-// TCHECK-NEXT: [[TMP14:%.*]] = call ptr @llvm.stacksave.p0()
-// TCHECK-NEXT: store ptr [[TMP14]], ptr [[SAVED_STACK]], align 8
-// TCHECK-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP5]], align 4
-// TCHECK-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR0]], align 8
-// TCHECK-NEXT: [[TMP15:%.*]] = mul nuw i64 [[TMP5]], 4
-// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VLA]], ptr align 4 [[BN]], i64 [[TMP15]], i1 false)
+// TCHECK-NEXT: [[TMP24:%.*]] = call ptr @llvm.stacksave.p0()
+// TCHECK-NEXT: store ptr [[TMP24]], ptr [[SAVED_STACK]], align 8
+// TCHECK-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP8]], align 4
+// TCHECK-NEXT: store i64 [[TMP8]], ptr [[__VLA_EXPR0]], align 8
+// TCHECK-NEXT: [[TMP25:%.*]] = mul nuw i64 [[TMP8]], 4
+// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VLA]], ptr align 4 [[BN]], i64 [[TMP25]], i1 false)
// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[C3]], ptr align 8 [[C]], i64 400, i1 false)
-// TCHECK-NEXT: [[TMP16:%.*]] = mul nuw i64 [[TMP9]], [[TMP11]]
-// TCHECK-NEXT: [[VLA4:%.*]] = alloca double, i64 [[TMP16]], align 8
-// TCHECK-NEXT: store i64 [[TMP9]], ptr [[__VLA_EXPR1]], align 8
-// TCHECK-NEXT: store i64 [[TMP11]], ptr [[__VLA_EXPR2]], align 8
-// TCHECK-NEXT: [[TMP17:%.*]] = mul nuw i64 [[TMP9]], [[TMP11]]
-// TCHECK-NEXT: [[TMP18:%.*]] = mul nuw i64 [[TMP17]], 8
-// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[VLA4]], ptr align 8 [[CN]], i64 [[TMP18]], i1 false)
+// TCHECK-NEXT: [[TMP26:%.*]] = mul nuw i64 [[TMP15]], [[TMP18]]
+// TCHECK-NEXT: [[VLA4:%.*]] = alloca double, i64 [[TMP26]], align 8
+// TCHECK-NEXT: store i64 [[TMP15]], ptr [[__VLA_EXPR1]], align 8
+// TCHECK-NEXT: store i64 [[TMP18]], ptr [[__VLA_EXPR2]], align 8
+// TCHECK-NEXT: [[TMP27:%.*]] = mul nuw i64 [[TMP15]], [[TMP18]]
+// TCHECK-NEXT: [[TMP28:%.*]] = mul nuw i64 [[TMP27]], 8
+// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[VLA4]], ptr align 8 [[CN]], i64 [[TMP28]], i1 false)
// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[D5]], ptr align 8 [[D]], i64 16, i1 false)
-// TCHECK-NEXT: [[TMP19:%.*]] = load i16, ptr [[AA]], align 2
-// TCHECK-NEXT: [[CONV:%.*]] = sext i16 [[TMP19]] to i32
+// TCHECK-NEXT: [[TMP29:%.*]] = load i16, ptr [[AA]], align 2
+// TCHECK-NEXT: [[CONV:%.*]] = sext i16 [[TMP29]] to i32
// TCHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
// TCHECK-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD]] to i16
// TCHECK-NEXT: store i16 [[CONV6]], ptr [[AA]], align 2
@@ -10239,16 +10253,16 @@ int bar(int n, double *ptr) {
// TCHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C3]], i64 0, i64 1
// TCHECK-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX8]], i64 0, i64 2
// TCHECK-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX9]], align 8
-// TCHECK-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP11]]
-// TCHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds double, ptr [[VLA4]], i64 [[TMP20]]
+// TCHECK-NEXT: [[TMP30:%.*]] = mul nsw i64 1, [[TMP18]]
+// TCHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds double, ptr [[VLA4]], i64 [[TMP30]]
// TCHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX10]], i64 3
// TCHECK-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX11]], align 8
// TCHECK-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D5]], i32 0, i32 0
// TCHECK-NEXT: store i64 1, ptr [[X]], align 8
// TCHECK-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D5]], i32 0, i32 1
// TCHECK-NEXT: store i8 1, ptr [[Y]], align 8
-// TCHECK-NEXT: [[TMP21:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
-// TCHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP21]])
+// TCHECK-NEXT: [[TMP31:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
+// TCHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP31]])
// TCHECK-NEXT: ret void
//
//
@@ -10259,22 +10273,25 @@ int bar(int n, double *ptr) {
// TCHECK-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// TCHECK-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// TCHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// TCHECK-NEXT: [[PTR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// TCHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// TCHECK-NEXT: [[E:%.*]] = load ptr, ptr [[TMP1]], align 8
-// TCHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// TCHECK-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// TCHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// TCHECK-NEXT: [[PTR:%.*]] = load ptr, ptr [[TMP1]], align 8
+// TCHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// TCHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// TCHECK-NEXT: [[E:%.*]] = load ptr, ptr [[TMP3]], align 8
+// TCHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// TCHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// TCHECK-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 8
// TCHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// TCHECK-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0:%.*]], ptr [[E]], i32 0, i32 0
-// TCHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[X]], align 4
-// TCHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double
-// TCHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[PTR]], align 8
-// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i64 0
+// TCHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[X]], align 4
+// TCHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
+// TCHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[PTR]], align 8
+// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 0
// TCHECK-NEXT: store double [[CONV]], ptr [[ARRAYIDX]], align 8
-// TCHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[PTR]], align 8
-// TCHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, ptr [[TMP4]], i64 0
-// TCHECK-NEXT: [[TMP5:%.*]] = load double, ptr [[ARRAYIDX2]], align 8
-// TCHECK-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
+// TCHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[PTR]], align 8
+// TCHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, ptr [[TMP7]], i64 0
+// TCHECK-NEXT: [[TMP8:%.*]] = load double, ptr [[ARRAYIDX2]], align 8
+// TCHECK-NEXT: [[INC:%.*]] = fadd double [[TMP8]], 1.000000e+00
// TCHECK-NEXT: store double [[INC]], ptr [[ARRAYIDX2]], align 8
// TCHECK-NEXT: ret void
//
@@ -10289,29 +10306,33 @@ int bar(int n, double *ptr) {
// TCHECK-NEXT: [[B2:%.*]] = alloca [10 x i32], align 4
// TCHECK-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// TCHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// TCHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// TCHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// TCHECK-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// TCHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// TCHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 8
-// TCHECK-NEXT: store i8 [[TMP4]], ptr [[AAA]], align 1
-// TCHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// TCHECK-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 8
-// TCHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// TCHECK-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// TCHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// TCHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// TCHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// TCHECK-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// TCHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// TCHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// TCHECK-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 8
+// TCHECK-NEXT: store i8 [[TMP6]], ptr [[AAA]], align 1
+// TCHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// TCHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8
+// TCHECK-NEXT: [[B:%.*]] = load ptr, ptr [[TMP8]], align 8
+// TCHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// TCHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// TCHECK-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP9]], align 8
// TCHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B2]], ptr align 4 [[B]], i64 40, i1 false)
-// TCHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// TCHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1
+// TCHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
+// TCHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], 1
// TCHECK-NEXT: store i32 [[ADD]], ptr [[A]], align 4
-// TCHECK-NEXT: [[TMP7:%.*]] = load i8, ptr [[AAA]], align 1
-// TCHECK-NEXT: [[CONV:%.*]] = sext i8 [[TMP7]] to i32
+// TCHECK-NEXT: [[TMP11:%.*]] = load i8, ptr [[AAA]], align 1
+// TCHECK-NEXT: [[CONV:%.*]] = sext i8 [[TMP11]] to i32
// TCHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
// TCHECK-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i8
// TCHECK-NEXT: store i8 [[CONV4]], ptr [[AAA]], align 1
// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B2]], i64 0, i64 2
-// TCHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-// TCHECK-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP8]], 1
+// TCHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
+// TCHECK-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], 1
// TCHECK-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4
// TCHECK-NEXT: ret void
//
@@ -10327,45 +10348,51 @@ int bar(int n, double *ptr) {
// TCHECK-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
// TCHECK-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// TCHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// TCHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// TCHECK-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 8
-// TCHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// TCHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// TCHECK-NEXT: store i32 [[TMP3]], ptr [[B]], align 4
-// TCHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// TCHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8
-// TCHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// TCHECK-NEXT: [[TMP7:%.*]] = load i64, ptr [[TMP6]], align 8
-// TCHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// TCHECK-NEXT: [[C:%.*]] = load ptr, ptr [[TMP8]], align 8
-// TCHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
-// TCHECK-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// TCHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// TCHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// TCHECK-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 8
+// TCHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// TCHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8
+// TCHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
+// TCHECK-NEXT: store i32 [[TMP5]], ptr [[B]], align 4
+// TCHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// TCHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
+// TCHECK-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP7]], align 8
+// TCHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// TCHECK-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8
+// TCHECK-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
+// TCHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// TCHECK-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8
+// TCHECK-NEXT: [[C:%.*]] = load ptr, ptr [[TMP13]], align 8
+// TCHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// TCHECK-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// TCHECK-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP14]], align 8
// TCHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// TCHECK-NEXT: [[TMP9:%.*]] = call ptr @llvm.stacksave.p0()
-// TCHECK-NEXT: store ptr [[TMP9]], ptr [[SAVED_STACK]], align 8
-// TCHECK-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP5]], [[TMP7]]
-// TCHECK-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP10]], align 2
-// TCHECK-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR0]], align 8
-// TCHECK-NEXT: store i64 [[TMP7]], ptr [[__VLA_EXPR1]], align 8
-// TCHECK-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP5]], [[TMP7]]
-// TCHECK-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], 2
-// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 2 [[VLA]], ptr align 2 [[C]], i64 [[TMP12]], i1 false)
-// TCHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[B]], align 4
-// TCHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP13]] to double
+// TCHECK-NEXT: [[TMP15:%.*]] = call ptr @llvm.stacksave.p0()
+// TCHECK-NEXT: store ptr [[TMP15]], ptr [[SAVED_STACK]], align 8
+// TCHECK-NEXT: [[TMP16:%.*]] = mul nuw i64 [[TMP8]], [[TMP11]]
+// TCHECK-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP16]], align 2
+// TCHECK-NEXT: store i64 [[TMP8]], ptr [[__VLA_EXPR0]], align 8
+// TCHECK-NEXT: store i64 [[TMP11]], ptr [[__VLA_EXPR1]], align 8
+// TCHECK-NEXT: [[TMP17:%.*]] = mul nuw i64 [[TMP8]], [[TMP11]]
+// TCHECK-NEXT: [[TMP18:%.*]] = mul nuw i64 [[TMP17]], 2
+// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 2 [[VLA]], ptr align 2 [[C]], i64 [[TMP18]], i1 false)
+// TCHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[B]], align 4
+// TCHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP19]] to double
// TCHECK-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
// TCHECK-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS]], i32 0, i32 0
// TCHECK-NEXT: store double [[ADD]], ptr [[A]], align 8
// TCHECK-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS]], i32 0, i32 0
-// TCHECK-NEXT: [[TMP14:%.*]] = load double, ptr [[A2]], align 8
-// TCHECK-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
+// TCHECK-NEXT: [[TMP20:%.*]] = load double, ptr [[A2]], align 8
+// TCHECK-NEXT: [[INC:%.*]] = fadd double [[TMP20]], 1.000000e+00
// TCHECK-NEXT: store double [[INC]], ptr [[A2]], align 8
// TCHECK-NEXT: [[CONV3:%.*]] = fptosi double [[INC]] to i16
-// TCHECK-NEXT: [[TMP15:%.*]] = mul nsw i64 1, [[TMP7]]
-// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP15]]
+// TCHECK-NEXT: [[TMP21:%.*]] = mul nsw i64 1, [[TMP11]]
+// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP21]]
// TCHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
// TCHECK-NEXT: store i16 [[CONV3]], ptr [[ARRAYIDX4]], align 2
-// TCHECK-NEXT: [[TMP16:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
-// TCHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP16]])
+// TCHECK-NEXT: [[TMP22:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
+// TCHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP22]])
// TCHECK-NEXT: ret void
//
//
@@ -10378,21 +10405,24 @@ int bar(int n, double *ptr) {
// TCHECK-NEXT: [[B2:%.*]] = alloca [10 x i32], align 4
// TCHECK-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// TCHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// TCHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// TCHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// TCHECK-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// TCHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// TCHECK-NEXT: [[B:%.*]] = load ptr, ptr [[TMP3]], align 8
-// TCHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// TCHECK-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// TCHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// TCHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// TCHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// TCHECK-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// TCHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// TCHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// TCHECK-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 8
+// TCHECK-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// TCHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// TCHECK-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP6]], align 8
// TCHECK-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B2]], ptr align 4 [[B]], i64 40, i1 false)
-// TCHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4
-// TCHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], 1
+// TCHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4
+// TCHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 1
// TCHECK-NEXT: store i32 [[ADD]], ptr [[A]], align 4
// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B2]], i64 0, i64 2
-// TCHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-// TCHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
+// TCHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
+// TCHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// TCHECK-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4
// TCHECK-NEXT: ret void
//
@@ -10406,15 +10436,19 @@ int bar(int n, double *ptr) {
// TCHECK1-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// TCHECK1-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// TCHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// TCHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// TCHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// TCHECK1-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// TCHECK1-NEXT: [[P:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// TCHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// TCHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
-// TCHECK1-NEXT: store i32 [[TMP4]], ptr [[GA]], align 4
-// TCHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// TCHECK1-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// TCHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// TCHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// TCHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// TCHECK1-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// TCHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// TCHECK1-NEXT: [[P:%.*]] = load ptr, ptr [[TMP4]], align 8
+// TCHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// TCHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8
+// TCHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 8
+// TCHECK1-NEXT: store i32 [[TMP7]], ptr [[GA]], align 4
+// TCHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// TCHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// TCHECK1-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP8]], align 8
// TCHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// TCHECK1-NEXT: ret void
//
@@ -10434,46 +10468,56 @@ int bar(int n, double *ptr) {
// TCHECK1-NEXT: [[D5:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
// TCHECK1-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// TCHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// TCHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// TCHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 8
-// TCHECK1-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
-// TCHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// TCHECK1-NEXT: [[B:%.*]] = load ptr, ptr [[TMP3]], align 8
-// TCHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// TCHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8
-// TCHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// TCHECK1-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP6]], align 8
-// TCHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// TCHECK1-NEXT: [[C:%.*]] = load ptr, ptr [[TMP7]], align 8
-// TCHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
-// TCHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8
-// TCHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 6
-// TCHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
-// TCHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 7
-// TCHECK1-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP12]], align 8
-// TCHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 8
-// TCHECK1-NEXT: [[D:%.*]] = load ptr, ptr [[TMP13]], align 8
-// TCHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 9
-// TCHECK1-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// TCHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// TCHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// TCHECK1-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 8
+// TCHECK1-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
+// TCHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// TCHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// TCHECK1-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 8
+// TCHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// TCHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
+// TCHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP7]], align 8
+// TCHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// TCHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8
+// TCHECK1-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP10]], align 8
+// TCHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// TCHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8
+// TCHECK1-NEXT: [[C:%.*]] = load ptr, ptr [[TMP12]], align 8
+// TCHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// TCHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8
+// TCHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[TMP14]], align 8
+// TCHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 6
+// TCHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8
+// TCHECK1-NEXT: [[TMP18:%.*]] = load i64, ptr [[TMP17]], align 8
+// TCHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 7
+// TCHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8
+// TCHECK1-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP20]], align 8
+// TCHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 8
+// TCHECK1-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 8
+// TCHECK1-NEXT: [[D:%.*]] = load ptr, ptr [[TMP22]], align 8
+// TCHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 9
+// TCHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// TCHECK1-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP23]], align 8
// TCHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B2]], ptr align 4 [[B]], i64 40, i1 false)
-// TCHECK1-NEXT: [[TMP14:%.*]] = call ptr @llvm.stacksave.p0()
-// TCHECK1-NEXT: store ptr [[TMP14]], ptr [[SAVED_STACK]], align 8
-// TCHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP5]], align 4
-// TCHECK1-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR0]], align 8
-// TCHECK1-NEXT: [[TMP15:%.*]] = mul nuw i64 [[TMP5]], 4
-// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VLA]], ptr align 4 [[BN]], i64 [[TMP15]], i1 false)
+// TCHECK1-NEXT: [[TMP24:%.*]] = call ptr @llvm.stacksave.p0()
+// TCHECK1-NEXT: store ptr [[TMP24]], ptr [[SAVED_STACK]], align 8
+// TCHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP8]], align 4
+// TCHECK1-NEXT: store i64 [[TMP8]], ptr [[__VLA_EXPR0]], align 8
+// TCHECK1-NEXT: [[TMP25:%.*]] = mul nuw i64 [[TMP8]], 4
+// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VLA]], ptr align 4 [[BN]], i64 [[TMP25]], i1 false)
// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[C3]], ptr align 8 [[C]], i64 400, i1 false)
-// TCHECK1-NEXT: [[TMP16:%.*]] = mul nuw i64 [[TMP9]], [[TMP11]]
-// TCHECK1-NEXT: [[VLA4:%.*]] = alloca double, i64 [[TMP16]], align 8
-// TCHECK1-NEXT: store i64 [[TMP9]], ptr [[__VLA_EXPR1]], align 8
-// TCHECK1-NEXT: store i64 [[TMP11]], ptr [[__VLA_EXPR2]], align 8
-// TCHECK1-NEXT: [[TMP17:%.*]] = mul nuw i64 [[TMP9]], [[TMP11]]
-// TCHECK1-NEXT: [[TMP18:%.*]] = mul nuw i64 [[TMP17]], 8
-// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[VLA4]], ptr align 8 [[CN]], i64 [[TMP18]], i1 false)
+// TCHECK1-NEXT: [[TMP26:%.*]] = mul nuw i64 [[TMP15]], [[TMP18]]
+// TCHECK1-NEXT: [[VLA4:%.*]] = alloca double, i64 [[TMP26]], align 8
+// TCHECK1-NEXT: store i64 [[TMP15]], ptr [[__VLA_EXPR1]], align 8
+// TCHECK1-NEXT: store i64 [[TMP18]], ptr [[__VLA_EXPR2]], align 8
+// TCHECK1-NEXT: [[TMP27:%.*]] = mul nuw i64 [[TMP15]], [[TMP18]]
+// TCHECK1-NEXT: [[TMP28:%.*]] = mul nuw i64 [[TMP27]], 8
+// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[VLA4]], ptr align 8 [[CN]], i64 [[TMP28]], i1 false)
// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[D5]], ptr align 8 [[D]], i64 16, i1 false)
-// TCHECK1-NEXT: [[TMP19:%.*]] = load i16, ptr [[AA]], align 2
-// TCHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP19]] to i32
+// TCHECK1-NEXT: [[TMP29:%.*]] = load i16, ptr [[AA]], align 2
+// TCHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP29]] to i32
// TCHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
// TCHECK1-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD]] to i16
// TCHECK1-NEXT: store i16 [[CONV6]], ptr [[AA]], align 2
@@ -10484,16 +10528,16 @@ int bar(int n, double *ptr) {
// TCHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C3]], i64 0, i64 1
// TCHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX8]], i64 0, i64 2
// TCHECK1-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX9]], align 8
-// TCHECK1-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP11]]
-// TCHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds double, ptr [[VLA4]], i64 [[TMP20]]
+// TCHECK1-NEXT: [[TMP30:%.*]] = mul nsw i64 1, [[TMP18]]
+// TCHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds double, ptr [[VLA4]], i64 [[TMP30]]
// TCHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX10]], i64 3
// TCHECK1-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX11]], align 8
// TCHECK1-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D5]], i32 0, i32 0
// TCHECK1-NEXT: store i64 1, ptr [[X]], align 8
// TCHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D5]], i32 0, i32 1
// TCHECK1-NEXT: store i8 1, ptr [[Y]], align 8
-// TCHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
-// TCHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP21]])
+// TCHECK1-NEXT: [[TMP31:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
+// TCHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP31]])
// TCHECK1-NEXT: ret void
//
//
@@ -10504,22 +10548,25 @@ int bar(int n, double *ptr) {
// TCHECK1-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// TCHECK1-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// TCHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// TCHECK1-NEXT: [[PTR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// TCHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// TCHECK1-NEXT: [[E:%.*]] = load ptr, ptr [[TMP1]], align 8
-// TCHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// TCHECK1-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// TCHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// TCHECK1-NEXT: [[PTR:%.*]] = load ptr, ptr [[TMP1]], align 8
+// TCHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// TCHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// TCHECK1-NEXT: [[E:%.*]] = load ptr, ptr [[TMP3]], align 8
+// TCHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// TCHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// TCHECK1-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 8
// TCHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// TCHECK1-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0:%.*]], ptr [[E]], i32 0, i32 0
-// TCHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[X]], align 4
-// TCHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double
-// TCHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[PTR]], align 8
-// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i64 0
+// TCHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[X]], align 4
+// TCHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
+// TCHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[PTR]], align 8
+// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 0
// TCHECK1-NEXT: store double [[CONV]], ptr [[ARRAYIDX]], align 8
-// TCHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[PTR]], align 8
-// TCHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, ptr [[TMP4]], i64 0
-// TCHECK1-NEXT: [[TMP5:%.*]] = load double, ptr [[ARRAYIDX2]], align 8
-// TCHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
+// TCHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[PTR]], align 8
+// TCHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, ptr [[TMP7]], i64 0
+// TCHECK1-NEXT: [[TMP8:%.*]] = load double, ptr [[ARRAYIDX2]], align 8
+// TCHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP8]], 1.000000e+00
// TCHECK1-NEXT: store double [[INC]], ptr [[ARRAYIDX2]], align 8
// TCHECK1-NEXT: ret void
//
@@ -10534,29 +10581,33 @@ int bar(int n, double *ptr) {
// TCHECK1-NEXT: [[B2:%.*]] = alloca [10 x i32], align 4
// TCHECK1-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// TCHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// TCHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// TCHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// TCHECK1-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// TCHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// TCHECK1-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 8
-// TCHECK1-NEXT: store i8 [[TMP4]], ptr [[AAA]], align 1
-// TCHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// TCHECK1-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 8
-// TCHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// TCHECK1-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// TCHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// TCHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// TCHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// TCHECK1-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// TCHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// TCHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// TCHECK1-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 8
+// TCHECK1-NEXT: store i8 [[TMP6]], ptr [[AAA]], align 1
+// TCHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// TCHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8
+// TCHECK1-NEXT: [[B:%.*]] = load ptr, ptr [[TMP8]], align 8
+// TCHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// TCHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// TCHECK1-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP9]], align 8
// TCHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B2]], ptr align 4 [[B]], i64 40, i1 false)
-// TCHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// TCHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1
+// TCHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
+// TCHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], 1
// TCHECK1-NEXT: store i32 [[ADD]], ptr [[A]], align 4
-// TCHECK1-NEXT: [[TMP7:%.*]] = load i8, ptr [[AAA]], align 1
-// TCHECK1-NEXT: [[CONV:%.*]] = sext i8 [[TMP7]] to i32
+// TCHECK1-NEXT: [[TMP11:%.*]] = load i8, ptr [[AAA]], align 1
+// TCHECK1-NEXT: [[CONV:%.*]] = sext i8 [[TMP11]] to i32
// TCHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
// TCHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i8
// TCHECK1-NEXT: store i8 [[CONV4]], ptr [[AAA]], align 1
// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B2]], i64 0, i64 2
-// TCHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-// TCHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP8]], 1
+// TCHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
+// TCHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], 1
// TCHECK1-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4
// TCHECK1-NEXT: ret void
//
@@ -10572,45 +10623,51 @@ int bar(int n, double *ptr) {
// TCHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
// TCHECK1-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// TCHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// TCHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// TCHECK1-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 8
-// TCHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// TCHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// TCHECK1-NEXT: store i32 [[TMP3]], ptr [[B]], align 4
-// TCHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// TCHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8
-// TCHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// TCHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[TMP6]], align 8
-// TCHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// TCHECK1-NEXT: [[C:%.*]] = load ptr, ptr [[TMP8]], align 8
-// TCHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
-// TCHECK1-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// TCHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// TCHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// TCHECK1-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 8
+// TCHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// TCHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8
+// TCHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
+// TCHECK1-NEXT: store i32 [[TMP5]], ptr [[B]], align 4
+// TCHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// TCHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
+// TCHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP7]], align 8
+// TCHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// TCHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8
+// TCHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
+// TCHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// TCHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8
+// TCHECK1-NEXT: [[C:%.*]] = load ptr, ptr [[TMP13]], align 8
+// TCHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// TCHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// TCHECK1-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP14]], align 8
// TCHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// TCHECK1-NEXT: [[TMP9:%.*]] = call ptr @llvm.stacksave.p0()
-// TCHECK1-NEXT: store ptr [[TMP9]], ptr [[SAVED_STACK]], align 8
-// TCHECK1-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP5]], [[TMP7]]
-// TCHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP10]], align 2
-// TCHECK1-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR0]], align 8
-// TCHECK1-NEXT: store i64 [[TMP7]], ptr [[__VLA_EXPR1]], align 8
-// TCHECK1-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP5]], [[TMP7]]
-// TCHECK1-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], 2
-// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 2 [[VLA]], ptr align 2 [[C]], i64 [[TMP12]], i1 false)
-// TCHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[B]], align 4
-// TCHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP13]] to double
+// TCHECK1-NEXT: [[TMP15:%.*]] = call ptr @llvm.stacksave.p0()
+// TCHECK1-NEXT: store ptr [[TMP15]], ptr [[SAVED_STACK]], align 8
+// TCHECK1-NEXT: [[TMP16:%.*]] = mul nuw i64 [[TMP8]], [[TMP11]]
+// TCHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP16]], align 2
+// TCHECK1-NEXT: store i64 [[TMP8]], ptr [[__VLA_EXPR0]], align 8
+// TCHECK1-NEXT: store i64 [[TMP11]], ptr [[__VLA_EXPR1]], align 8
+// TCHECK1-NEXT: [[TMP17:%.*]] = mul nuw i64 [[TMP8]], [[TMP11]]
+// TCHECK1-NEXT: [[TMP18:%.*]] = mul nuw i64 [[TMP17]], 2
+// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 2 [[VLA]], ptr align 2 [[C]], i64 [[TMP18]], i1 false)
+// TCHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[B]], align 4
+// TCHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP19]] to double
// TCHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
// TCHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS]], i32 0, i32 0
// TCHECK1-NEXT: store double [[ADD]], ptr [[A]], align 8
// TCHECK1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS]], i32 0, i32 0
-// TCHECK1-NEXT: [[TMP14:%.*]] = load double, ptr [[A2]], align 8
-// TCHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
+// TCHECK1-NEXT: [[TMP20:%.*]] = load double, ptr [[A2]], align 8
+// TCHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP20]], 1.000000e+00
// TCHECK1-NEXT: store double [[INC]], ptr [[A2]], align 8
// TCHECK1-NEXT: [[CONV3:%.*]] = fptosi double [[INC]] to i16
-// TCHECK1-NEXT: [[TMP15:%.*]] = mul nsw i64 1, [[TMP7]]
-// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP15]]
+// TCHECK1-NEXT: [[TMP21:%.*]] = mul nsw i64 1, [[TMP11]]
+// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP21]]
// TCHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
// TCHECK1-NEXT: store i16 [[CONV3]], ptr [[ARRAYIDX4]], align 2
-// TCHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
-// TCHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP16]])
+// TCHECK1-NEXT: [[TMP22:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
+// TCHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP22]])
// TCHECK1-NEXT: ret void
//
//
@@ -10623,21 +10680,24 @@ int bar(int n, double *ptr) {
// TCHECK1-NEXT: [[B2:%.*]] = alloca [10 x i32], align 4
// TCHECK1-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// TCHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// TCHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// TCHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// TCHECK1-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// TCHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// TCHECK1-NEXT: [[B:%.*]] = load ptr, ptr [[TMP3]], align 8
-// TCHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// TCHECK1-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// TCHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// TCHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// TCHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// TCHECK1-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// TCHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// TCHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// TCHECK1-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 8
+// TCHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// TCHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// TCHECK1-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP6]], align 8
// TCHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B2]], ptr align 4 [[B]], i64 40, i1 false)
-// TCHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4
-// TCHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], 1
+// TCHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4
+// TCHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 1
// TCHECK1-NEXT: store i32 [[ADD]], ptr [[A]], align 4
// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B2]], i64 0, i64 2
-// TCHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-// TCHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
+// TCHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
+// TCHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// TCHECK1-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4
// TCHECK1-NEXT: ret void
//
@@ -10651,15 +10711,19 @@ int bar(int n, double *ptr) {
// TCHECK2-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// TCHECK2-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// TCHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// TCHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// TCHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// TCHECK2-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// TCHECK2-NEXT: [[P:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// TCHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// TCHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-// TCHECK2-NEXT: store i32 [[TMP4]], ptr [[GA]], align 4
-// TCHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// TCHECK2-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// TCHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// TCHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// TCHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// TCHECK2-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// TCHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// TCHECK2-NEXT: [[P:%.*]] = load ptr, ptr [[TMP4]], align 4
+// TCHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// TCHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4
+// TCHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+// TCHECK2-NEXT: store i32 [[TMP7]], ptr [[GA]], align 4
+// TCHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// TCHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// TCHECK2-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP8]], align 4
// TCHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// TCHECK2-NEXT: ret void
//
@@ -10679,46 +10743,56 @@ int bar(int n, double *ptr) {
// TCHECK2-NEXT: [[D5:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
// TCHECK2-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// TCHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// TCHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// TCHECK2-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 4
-// TCHECK2-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
-// TCHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// TCHECK2-NEXT: [[B:%.*]] = load ptr, ptr [[TMP3]], align 4
-// TCHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// TCHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// TCHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// TCHECK2-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP6]], align 4
-// TCHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// TCHECK2-NEXT: [[C:%.*]] = load ptr, ptr [[TMP7]], align 4
-// TCHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
-// TCHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
-// TCHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 6
-// TCHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
-// TCHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 7
-// TCHECK2-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP12]], align 4
-// TCHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 8
-// TCHECK2-NEXT: [[D:%.*]] = load ptr, ptr [[TMP13]], align 4
-// TCHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 9
-// TCHECK2-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// TCHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// TCHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// TCHECK2-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 4
+// TCHECK2-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
+// TCHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// TCHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// TCHECK2-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 4
+// TCHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// TCHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
+// TCHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
+// TCHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// TCHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4
+// TCHECK2-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP10]], align 4
+// TCHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// TCHECK2-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 4
+// TCHECK2-NEXT: [[C:%.*]] = load ptr, ptr [[TMP12]], align 4
+// TCHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// TCHECK2-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 4
+// TCHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4
+// TCHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 6
+// TCHECK2-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 4
+// TCHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4
+// TCHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 7
+// TCHECK2-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 4
+// TCHECK2-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP20]], align 4
+// TCHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 8
+// TCHECK2-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 4
+// TCHECK2-NEXT: [[D:%.*]] = load ptr, ptr [[TMP22]], align 4
+// TCHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 9
+// TCHECK2-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// TCHECK2-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP23]], align 4
// TCHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B2]], ptr align 4 [[B]], i32 40, i1 false)
-// TCHECK2-NEXT: [[TMP14:%.*]] = call ptr @llvm.stacksave.p0()
-// TCHECK2-NEXT: store ptr [[TMP14]], ptr [[SAVED_STACK]], align 4
-// TCHECK2-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP5]], align 4
-// TCHECK2-NEXT: store i32 [[TMP5]], ptr [[__VLA_EXPR0]], align 4
-// TCHECK2-NEXT: [[TMP15:%.*]] = mul nuw i32 [[TMP5]], 4
-// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VLA]], ptr align 4 [[BN]], i32 [[TMP15]], i1 false)
+// TCHECK2-NEXT: [[TMP24:%.*]] = call ptr @llvm.stacksave.p0()
+// TCHECK2-NEXT: store ptr [[TMP24]], ptr [[SAVED_STACK]], align 4
+// TCHECK2-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP8]], align 4
+// TCHECK2-NEXT: store i32 [[TMP8]], ptr [[__VLA_EXPR0]], align 4
+// TCHECK2-NEXT: [[TMP25:%.*]] = mul nuw i32 [[TMP8]], 4
+// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VLA]], ptr align 4 [[BN]], i32 [[TMP25]], i1 false)
// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[C3]], ptr align 8 [[C]], i32 400, i1 false)
-// TCHECK2-NEXT: [[TMP16:%.*]] = mul nuw i32 [[TMP9]], [[TMP11]]
-// TCHECK2-NEXT: [[VLA4:%.*]] = alloca double, i32 [[TMP16]], align 8
-// TCHECK2-NEXT: store i32 [[TMP9]], ptr [[__VLA_EXPR1]], align 4
-// TCHECK2-NEXT: store i32 [[TMP11]], ptr [[__VLA_EXPR2]], align 4
-// TCHECK2-NEXT: [[TMP17:%.*]] = mul nuw i32 [[TMP9]], [[TMP11]]
-// TCHECK2-NEXT: [[TMP18:%.*]] = mul nuw i32 [[TMP17]], 8
-// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[VLA4]], ptr align 8 [[CN]], i32 [[TMP18]], i1 false)
+// TCHECK2-NEXT: [[TMP26:%.*]] = mul nuw i32 [[TMP15]], [[TMP18]]
+// TCHECK2-NEXT: [[VLA4:%.*]] = alloca double, i32 [[TMP26]], align 8
+// TCHECK2-NEXT: store i32 [[TMP15]], ptr [[__VLA_EXPR1]], align 4
+// TCHECK2-NEXT: store i32 [[TMP18]], ptr [[__VLA_EXPR2]], align 4
+// TCHECK2-NEXT: [[TMP27:%.*]] = mul nuw i32 [[TMP15]], [[TMP18]]
+// TCHECK2-NEXT: [[TMP28:%.*]] = mul nuw i32 [[TMP27]], 8
+// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[VLA4]], ptr align 8 [[CN]], i32 [[TMP28]], i1 false)
// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[D5]], ptr align 4 [[D]], i32 12, i1 false)
-// TCHECK2-NEXT: [[TMP19:%.*]] = load i16, ptr [[AA]], align 2
-// TCHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP19]] to i32
+// TCHECK2-NEXT: [[TMP29:%.*]] = load i16, ptr [[AA]], align 2
+// TCHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP29]] to i32
// TCHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
// TCHECK2-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD]] to i16
// TCHECK2-NEXT: store i16 [[CONV6]], ptr [[AA]], align 2
@@ -10729,16 +10803,16 @@ int bar(int n, double *ptr) {
// TCHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C3]], i32 0, i32 1
// TCHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX8]], i32 0, i32 2
// TCHECK2-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX9]], align 8
-// TCHECK2-NEXT: [[TMP20:%.*]] = mul nsw i32 1, [[TMP11]]
-// TCHECK2-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds double, ptr [[VLA4]], i32 [[TMP20]]
+// TCHECK2-NEXT: [[TMP30:%.*]] = mul nsw i32 1, [[TMP18]]
+// TCHECK2-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds double, ptr [[VLA4]], i32 [[TMP30]]
// TCHECK2-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX10]], i32 3
// TCHECK2-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX11]], align 8
// TCHECK2-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D5]], i32 0, i32 0
// TCHECK2-NEXT: store i64 1, ptr [[X]], align 4
// TCHECK2-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D5]], i32 0, i32 1
// TCHECK2-NEXT: store i8 1, ptr [[Y]], align 4
-// TCHECK2-NEXT: [[TMP21:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
-// TCHECK2-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP21]])
+// TCHECK2-NEXT: [[TMP31:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
+// TCHECK2-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP31]])
// TCHECK2-NEXT: ret void
//
//
@@ -10749,22 +10823,25 @@ int bar(int n, double *ptr) {
// TCHECK2-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// TCHECK2-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// TCHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// TCHECK2-NEXT: [[PTR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// TCHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// TCHECK2-NEXT: [[E:%.*]] = load ptr, ptr [[TMP1]], align 4
-// TCHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// TCHECK2-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// TCHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// TCHECK2-NEXT: [[PTR:%.*]] = load ptr, ptr [[TMP1]], align 4
+// TCHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// TCHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// TCHECK2-NEXT: [[E:%.*]] = load ptr, ptr [[TMP3]], align 4
+// TCHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// TCHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// TCHECK2-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 4
// TCHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// TCHECK2-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0:%.*]], ptr [[E]], i32 0, i32 0
-// TCHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[X]], align 4
-// TCHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double
-// TCHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[PTR]], align 4
-// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i32 0
+// TCHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[X]], align 4
+// TCHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
+// TCHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[PTR]], align 4
+// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 0
// TCHECK2-NEXT: store double [[CONV]], ptr [[ARRAYIDX]], align 4
-// TCHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[PTR]], align 4
-// TCHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, ptr [[TMP4]], i32 0
-// TCHECK2-NEXT: [[TMP5:%.*]] = load double, ptr [[ARRAYIDX2]], align 4
-// TCHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
+// TCHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[PTR]], align 4
+// TCHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, ptr [[TMP7]], i32 0
+// TCHECK2-NEXT: [[TMP8:%.*]] = load double, ptr [[ARRAYIDX2]], align 4
+// TCHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP8]], 1.000000e+00
// TCHECK2-NEXT: store double [[INC]], ptr [[ARRAYIDX2]], align 4
// TCHECK2-NEXT: ret void
//
@@ -10779,29 +10856,33 @@ int bar(int n, double *ptr) {
// TCHECK2-NEXT: [[B2:%.*]] = alloca [10 x i32], align 4
// TCHECK2-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// TCHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// TCHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// TCHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// TCHECK2-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// TCHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// TCHECK2-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 4
-// TCHECK2-NEXT: store i8 [[TMP4]], ptr [[AAA]], align 1
-// TCHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// TCHECK2-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 4
-// TCHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// TCHECK2-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// TCHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// TCHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// TCHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// TCHECK2-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// TCHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// TCHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// TCHECK2-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 4
+// TCHECK2-NEXT: store i8 [[TMP6]], ptr [[AAA]], align 1
+// TCHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// TCHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4
+// TCHECK2-NEXT: [[B:%.*]] = load ptr, ptr [[TMP8]], align 4
+// TCHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// TCHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// TCHECK2-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP9]], align 4
// TCHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B2]], ptr align 4 [[B]], i32 40, i1 false)
-// TCHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// TCHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1
+// TCHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
+// TCHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], 1
// TCHECK2-NEXT: store i32 [[ADD]], ptr [[A]], align 4
-// TCHECK2-NEXT: [[TMP7:%.*]] = load i8, ptr [[AAA]], align 1
-// TCHECK2-NEXT: [[CONV:%.*]] = sext i8 [[TMP7]] to i32
+// TCHECK2-NEXT: [[TMP11:%.*]] = load i8, ptr [[AAA]], align 1
+// TCHECK2-NEXT: [[CONV:%.*]] = sext i8 [[TMP11]] to i32
// TCHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
// TCHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i8
// TCHECK2-NEXT: store i8 [[CONV4]], ptr [[AAA]], align 1
// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B2]], i32 0, i32 2
-// TCHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-// TCHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP8]], 1
+// TCHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
+// TCHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], 1
// TCHECK2-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4
// TCHECK2-NEXT: ret void
//
@@ -10817,45 +10898,51 @@ int bar(int n, double *ptr) {
// TCHECK2-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
// TCHECK2-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// TCHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// TCHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// TCHECK2-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 4
-// TCHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// TCHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// TCHECK2-NEXT: store i32 [[TMP3]], ptr [[B]], align 4
-// TCHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
+// TCHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// TCHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// TCHECK2-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 4
+// TCHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// TCHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4
// TCHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// TCHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// TCHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
-// TCHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// TCHECK2-NEXT: [[C:%.*]] = load ptr, ptr [[TMP8]], align 4
-// TCHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
-// TCHECK2-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// TCHECK2-NEXT: store i32 [[TMP5]], ptr [[B]], align 4
+// TCHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// TCHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
+// TCHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
+// TCHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// TCHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4
+// TCHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
+// TCHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// TCHECK2-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 4
+// TCHECK2-NEXT: [[C:%.*]] = load ptr, ptr [[TMP13]], align 4
+// TCHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// TCHECK2-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// TCHECK2-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP14]], align 4
// TCHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// TCHECK2-NEXT: [[TMP9:%.*]] = call ptr @llvm.stacksave.p0()
-// TCHECK2-NEXT: store ptr [[TMP9]], ptr [[SAVED_STACK]], align 4
-// TCHECK2-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP5]], [[TMP7]]
-// TCHECK2-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP10]], align 2
-// TCHECK2-NEXT: store i32 [[TMP5]], ptr [[__VLA_EXPR0]], align 4
-// TCHECK2-NEXT: store i32 [[TMP7]], ptr [[__VLA_EXPR1]], align 4
-// TCHECK2-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP5]], [[TMP7]]
-// TCHECK2-NEXT: [[TMP12:%.*]] = mul nuw i32 [[TMP11]], 2
-// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 2 [[VLA]], ptr align 2 [[C]], i32 [[TMP12]], i1 false)
-// TCHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[B]], align 4
-// TCHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP13]] to double
+// TCHECK2-NEXT: [[TMP15:%.*]] = call ptr @llvm.stacksave.p0()
+// TCHECK2-NEXT: store ptr [[TMP15]], ptr [[SAVED_STACK]], align 4
+// TCHECK2-NEXT: [[TMP16:%.*]] = mul nuw i32 [[TMP8]], [[TMP11]]
+// TCHECK2-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP16]], align 2
+// TCHECK2-NEXT: store i32 [[TMP8]], ptr [[__VLA_EXPR0]], align 4
+// TCHECK2-NEXT: store i32 [[TMP11]], ptr [[__VLA_EXPR1]], align 4
+// TCHECK2-NEXT: [[TMP17:%.*]] = mul nuw i32 [[TMP8]], [[TMP11]]
+// TCHECK2-NEXT: [[TMP18:%.*]] = mul nuw i32 [[TMP17]], 2
+// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 2 [[VLA]], ptr align 2 [[C]], i32 [[TMP18]], i1 false)
+// TCHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[B]], align 4
+// TCHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP19]] to double
// TCHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
// TCHECK2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS]], i32 0, i32 0
// TCHECK2-NEXT: store double [[ADD]], ptr [[A]], align 4
// TCHECK2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS]], i32 0, i32 0
-// TCHECK2-NEXT: [[TMP14:%.*]] = load double, ptr [[A2]], align 4
-// TCHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
+// TCHECK2-NEXT: [[TMP20:%.*]] = load double, ptr [[A2]], align 4
+// TCHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP20]], 1.000000e+00
// TCHECK2-NEXT: store double [[INC]], ptr [[A2]], align 4
// TCHECK2-NEXT: [[CONV3:%.*]] = fptosi double [[INC]] to i16
-// TCHECK2-NEXT: [[TMP15:%.*]] = mul nsw i32 1, [[TMP7]]
-// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP15]]
+// TCHECK2-NEXT: [[TMP21:%.*]] = mul nsw i32 1, [[TMP11]]
+// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP21]]
// TCHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
// TCHECK2-NEXT: store i16 [[CONV3]], ptr [[ARRAYIDX4]], align 2
-// TCHECK2-NEXT: [[TMP16:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
-// TCHECK2-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP16]])
+// TCHECK2-NEXT: [[TMP22:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
+// TCHECK2-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP22]])
// TCHECK2-NEXT: ret void
//
//
@@ -10868,21 +10955,24 @@ int bar(int n, double *ptr) {
// TCHECK2-NEXT: [[B2:%.*]] = alloca [10 x i32], align 4
// TCHECK2-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// TCHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// TCHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// TCHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// TCHECK2-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// TCHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// TCHECK2-NEXT: [[B:%.*]] = load ptr, ptr [[TMP3]], align 4
-// TCHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// TCHECK2-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// TCHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// TCHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// TCHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// TCHECK2-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// TCHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// TCHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// TCHECK2-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 4
+// TCHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// TCHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// TCHECK2-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP6]], align 4
// TCHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B2]], ptr align 4 [[B]], i32 40, i1 false)
-// TCHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4
-// TCHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], 1
+// TCHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4
+// TCHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 1
// TCHECK2-NEXT: store i32 [[ADD]], ptr [[A]], align 4
// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B2]], i32 0, i32 2
-// TCHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-// TCHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
+// TCHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
+// TCHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// TCHECK2-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4
// TCHECK2-NEXT: ret void
//
@@ -10896,15 +10986,19 @@ int bar(int n, double *ptr) {
// TCHECK3-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// TCHECK3-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// TCHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// TCHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// TCHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// TCHECK3-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// TCHECK3-NEXT: [[P:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// TCHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// TCHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-// TCHECK3-NEXT: store i32 [[TMP4]], ptr [[GA]], align 4
-// TCHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// TCHECK3-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// TCHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// TCHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// TCHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// TCHECK3-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// TCHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// TCHECK3-NEXT: [[P:%.*]] = load ptr, ptr [[TMP4]], align 4
+// TCHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// TCHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4
+// TCHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+// TCHECK3-NEXT: store i32 [[TMP7]], ptr [[GA]], align 4
+// TCHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// TCHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// TCHECK3-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP8]], align 4
// TCHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// TCHECK3-NEXT: ret void
//
@@ -10924,46 +11018,56 @@ int bar(int n, double *ptr) {
// TCHECK3-NEXT: [[D5:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
// TCHECK3-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// TCHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// TCHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// TCHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 4
-// TCHECK3-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
-// TCHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// TCHECK3-NEXT: [[B:%.*]] = load ptr, ptr [[TMP3]], align 4
-// TCHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// TCHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// TCHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// TCHECK3-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP6]], align 4
-// TCHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// TCHECK3-NEXT: [[C:%.*]] = load ptr, ptr [[TMP7]], align 4
-// TCHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
-// TCHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
-// TCHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 6
-// TCHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
-// TCHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 7
-// TCHECK3-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP12]], align 4
-// TCHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 8
-// TCHECK3-NEXT: [[D:%.*]] = load ptr, ptr [[TMP13]], align 4
-// TCHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 9
-// TCHECK3-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// TCHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// TCHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// TCHECK3-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 4
+// TCHECK3-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
+// TCHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// TCHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// TCHECK3-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 4
+// TCHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// TCHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
+// TCHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
+// TCHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// TCHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4
+// TCHECK3-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP10]], align 4
+// TCHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// TCHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 4
+// TCHECK3-NEXT: [[C:%.*]] = load ptr, ptr [[TMP12]], align 4
+// TCHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// TCHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 4
+// TCHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4
+// TCHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 6
+// TCHECK3-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 4
+// TCHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4
+// TCHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 7
+// TCHECK3-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 4
+// TCHECK3-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP20]], align 4
+// TCHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 8
+// TCHECK3-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 4
+// TCHECK3-NEXT: [[D:%.*]] = load ptr, ptr [[TMP22]], align 4
+// TCHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 9
+// TCHECK3-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// TCHECK3-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP23]], align 4
// TCHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B2]], ptr align 4 [[B]], i32 40, i1 false)
-// TCHECK3-NEXT: [[TMP14:%.*]] = call ptr @llvm.stacksave.p0()
-// TCHECK3-NEXT: store ptr [[TMP14]], ptr [[SAVED_STACK]], align 4
-// TCHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP5]], align 4
-// TCHECK3-NEXT: store i32 [[TMP5]], ptr [[__VLA_EXPR0]], align 4
-// TCHECK3-NEXT: [[TMP15:%.*]] = mul nuw i32 [[TMP5]], 4
-// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VLA]], ptr align 4 [[BN]], i32 [[TMP15]], i1 false)
+// TCHECK3-NEXT: [[TMP24:%.*]] = call ptr @llvm.stacksave.p0()
+// TCHECK3-NEXT: store ptr [[TMP24]], ptr [[SAVED_STACK]], align 4
+// TCHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP8]], align 4
+// TCHECK3-NEXT: store i32 [[TMP8]], ptr [[__VLA_EXPR0]], align 4
+// TCHECK3-NEXT: [[TMP25:%.*]] = mul nuw i32 [[TMP8]], 4
+// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VLA]], ptr align 4 [[BN]], i32 [[TMP25]], i1 false)
// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[C3]], ptr align 8 [[C]], i32 400, i1 false)
-// TCHECK3-NEXT: [[TMP16:%.*]] = mul nuw i32 [[TMP9]], [[TMP11]]
-// TCHECK3-NEXT: [[VLA4:%.*]] = alloca double, i32 [[TMP16]], align 8
-// TCHECK3-NEXT: store i32 [[TMP9]], ptr [[__VLA_EXPR1]], align 4
-// TCHECK3-NEXT: store i32 [[TMP11]], ptr [[__VLA_EXPR2]], align 4
-// TCHECK3-NEXT: [[TMP17:%.*]] = mul nuw i32 [[TMP9]], [[TMP11]]
-// TCHECK3-NEXT: [[TMP18:%.*]] = mul nuw i32 [[TMP17]], 8
-// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[VLA4]], ptr align 8 [[CN]], i32 [[TMP18]], i1 false)
+// TCHECK3-NEXT: [[TMP26:%.*]] = mul nuw i32 [[TMP15]], [[TMP18]]
+// TCHECK3-NEXT: [[VLA4:%.*]] = alloca double, i32 [[TMP26]], align 8
+// TCHECK3-NEXT: store i32 [[TMP15]], ptr [[__VLA_EXPR1]], align 4
+// TCHECK3-NEXT: store i32 [[TMP18]], ptr [[__VLA_EXPR2]], align 4
+// TCHECK3-NEXT: [[TMP27:%.*]] = mul nuw i32 [[TMP15]], [[TMP18]]
+// TCHECK3-NEXT: [[TMP28:%.*]] = mul nuw i32 [[TMP27]], 8
+// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[VLA4]], ptr align 8 [[CN]], i32 [[TMP28]], i1 false)
// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[D5]], ptr align 4 [[D]], i32 12, i1 false)
-// TCHECK3-NEXT: [[TMP19:%.*]] = load i16, ptr [[AA]], align 2
-// TCHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP19]] to i32
+// TCHECK3-NEXT: [[TMP29:%.*]] = load i16, ptr [[AA]], align 2
+// TCHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP29]] to i32
// TCHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
// TCHECK3-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD]] to i16
// TCHECK3-NEXT: store i16 [[CONV6]], ptr [[AA]], align 2
@@ -10974,16 +11078,16 @@ int bar(int n, double *ptr) {
// TCHECK3-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C3]], i32 0, i32 1
// TCHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX8]], i32 0, i32 2
// TCHECK3-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX9]], align 8
-// TCHECK3-NEXT: [[TMP20:%.*]] = mul nsw i32 1, [[TMP11]]
-// TCHECK3-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds double, ptr [[VLA4]], i32 [[TMP20]]
+// TCHECK3-NEXT: [[TMP30:%.*]] = mul nsw i32 1, [[TMP18]]
+// TCHECK3-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds double, ptr [[VLA4]], i32 [[TMP30]]
// TCHECK3-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX10]], i32 3
// TCHECK3-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX11]], align 8
// TCHECK3-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D5]], i32 0, i32 0
// TCHECK3-NEXT: store i64 1, ptr [[X]], align 4
// TCHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[D5]], i32 0, i32 1
// TCHECK3-NEXT: store i8 1, ptr [[Y]], align 4
-// TCHECK3-NEXT: [[TMP21:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
-// TCHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP21]])
+// TCHECK3-NEXT: [[TMP31:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
+// TCHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP31]])
// TCHECK3-NEXT: ret void
//
//
@@ -10994,22 +11098,25 @@ int bar(int n, double *ptr) {
// TCHECK3-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// TCHECK3-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// TCHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// TCHECK3-NEXT: [[PTR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// TCHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// TCHECK3-NEXT: [[E:%.*]] = load ptr, ptr [[TMP1]], align 4
-// TCHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// TCHECK3-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// TCHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// TCHECK3-NEXT: [[PTR:%.*]] = load ptr, ptr [[TMP1]], align 4
+// TCHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// TCHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// TCHECK3-NEXT: [[E:%.*]] = load ptr, ptr [[TMP3]], align 4
+// TCHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// TCHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// TCHECK3-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 4
// TCHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// TCHECK3-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT_0:%.*]], ptr [[E]], i32 0, i32 0
-// TCHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[X]], align 4
-// TCHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double
-// TCHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[PTR]], align 4
-// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i32 0
+// TCHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[X]], align 4
+// TCHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
+// TCHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[PTR]], align 4
+// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 0
// TCHECK3-NEXT: store double [[CONV]], ptr [[ARRAYIDX]], align 4
-// TCHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[PTR]], align 4
-// TCHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, ptr [[TMP4]], i32 0
-// TCHECK3-NEXT: [[TMP5:%.*]] = load double, ptr [[ARRAYIDX2]], align 4
-// TCHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
+// TCHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[PTR]], align 4
+// TCHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, ptr [[TMP7]], i32 0
+// TCHECK3-NEXT: [[TMP8:%.*]] = load double, ptr [[ARRAYIDX2]], align 4
+// TCHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP8]], 1.000000e+00
// TCHECK3-NEXT: store double [[INC]], ptr [[ARRAYIDX2]], align 4
// TCHECK3-NEXT: ret void
//
@@ -11024,29 +11131,33 @@ int bar(int n, double *ptr) {
// TCHECK3-NEXT: [[B2:%.*]] = alloca [10 x i32], align 4
// TCHECK3-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// TCHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// TCHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// TCHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// TCHECK3-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// TCHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// TCHECK3-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 4
-// TCHECK3-NEXT: store i8 [[TMP4]], ptr [[AAA]], align 1
-// TCHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// TCHECK3-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 4
-// TCHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// TCHECK3-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// TCHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// TCHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// TCHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// TCHECK3-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// TCHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// TCHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// TCHECK3-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 4
+// TCHECK3-NEXT: store i8 [[TMP6]], ptr [[AAA]], align 1
+// TCHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// TCHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4
+// TCHECK3-NEXT: [[B:%.*]] = load ptr, ptr [[TMP8]], align 4
+// TCHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// TCHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// TCHECK3-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP9]], align 4
// TCHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B2]], ptr align 4 [[B]], i32 40, i1 false)
-// TCHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// TCHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1
+// TCHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
+// TCHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], 1
// TCHECK3-NEXT: store i32 [[ADD]], ptr [[A]], align 4
-// TCHECK3-NEXT: [[TMP7:%.*]] = load i8, ptr [[AAA]], align 1
-// TCHECK3-NEXT: [[CONV:%.*]] = sext i8 [[TMP7]] to i32
+// TCHECK3-NEXT: [[TMP11:%.*]] = load i8, ptr [[AAA]], align 1
+// TCHECK3-NEXT: [[CONV:%.*]] = sext i8 [[TMP11]] to i32
// TCHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
// TCHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i8
// TCHECK3-NEXT: store i8 [[CONV4]], ptr [[AAA]], align 1
// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B2]], i32 0, i32 2
-// TCHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-// TCHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP8]], 1
+// TCHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
+// TCHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], 1
// TCHECK3-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4
// TCHECK3-NEXT: ret void
//
@@ -11062,45 +11173,51 @@ int bar(int n, double *ptr) {
// TCHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
// TCHECK3-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// TCHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// TCHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// TCHECK3-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 4
-// TCHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// TCHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// TCHECK3-NEXT: store i32 [[TMP3]], ptr [[B]], align 4
-// TCHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
+// TCHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// TCHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// TCHECK3-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 4
+// TCHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// TCHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4
// TCHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// TCHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// TCHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
-// TCHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// TCHECK3-NEXT: [[C:%.*]] = load ptr, ptr [[TMP8]], align 4
-// TCHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
-// TCHECK3-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// TCHECK3-NEXT: store i32 [[TMP5]], ptr [[B]], align 4
+// TCHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// TCHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
+// TCHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
+// TCHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// TCHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4
+// TCHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
+// TCHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// TCHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 4
+// TCHECK3-NEXT: [[C:%.*]] = load ptr, ptr [[TMP13]], align 4
+// TCHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// TCHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// TCHECK3-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP14]], align 4
// TCHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// TCHECK3-NEXT: [[TMP9:%.*]] = call ptr @llvm.stacksave.p0()
-// TCHECK3-NEXT: store ptr [[TMP9]], ptr [[SAVED_STACK]], align 4
-// TCHECK3-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP5]], [[TMP7]]
-// TCHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP10]], align 2
-// TCHECK3-NEXT: store i32 [[TMP5]], ptr [[__VLA_EXPR0]], align 4
-// TCHECK3-NEXT: store i32 [[TMP7]], ptr [[__VLA_EXPR1]], align 4
-// TCHECK3-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP5]], [[TMP7]]
-// TCHECK3-NEXT: [[TMP12:%.*]] = mul nuw i32 [[TMP11]], 2
-// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 2 [[VLA]], ptr align 2 [[C]], i32 [[TMP12]], i1 false)
-// TCHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[B]], align 4
-// TCHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP13]] to double
+// TCHECK3-NEXT: [[TMP15:%.*]] = call ptr @llvm.stacksave.p0()
+// TCHECK3-NEXT: store ptr [[TMP15]], ptr [[SAVED_STACK]], align 4
+// TCHECK3-NEXT: [[TMP16:%.*]] = mul nuw i32 [[TMP8]], [[TMP11]]
+// TCHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP16]], align 2
+// TCHECK3-NEXT: store i32 [[TMP8]], ptr [[__VLA_EXPR0]], align 4
+// TCHECK3-NEXT: store i32 [[TMP11]], ptr [[__VLA_EXPR1]], align 4
+// TCHECK3-NEXT: [[TMP17:%.*]] = mul nuw i32 [[TMP8]], [[TMP11]]
+// TCHECK3-NEXT: [[TMP18:%.*]] = mul nuw i32 [[TMP17]], 2
+// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 2 [[VLA]], ptr align 2 [[C]], i32 [[TMP18]], i1 false)
+// TCHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[B]], align 4
+// TCHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP19]] to double
// TCHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
// TCHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS]], i32 0, i32 0
// TCHECK3-NEXT: store double [[ADD]], ptr [[A]], align 4
// TCHECK3-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[THIS]], i32 0, i32 0
-// TCHECK3-NEXT: [[TMP14:%.*]] = load double, ptr [[A2]], align 4
-// TCHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
+// TCHECK3-NEXT: [[TMP20:%.*]] = load double, ptr [[A2]], align 4
+// TCHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP20]], 1.000000e+00
// TCHECK3-NEXT: store double [[INC]], ptr [[A2]], align 4
// TCHECK3-NEXT: [[CONV3:%.*]] = fptosi double [[INC]] to i16
-// TCHECK3-NEXT: [[TMP15:%.*]] = mul nsw i32 1, [[TMP7]]
-// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP15]]
+// TCHECK3-NEXT: [[TMP21:%.*]] = mul nsw i32 1, [[TMP11]]
+// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP21]]
// TCHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
// TCHECK3-NEXT: store i16 [[CONV3]], ptr [[ARRAYIDX4]], align 2
-// TCHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
-// TCHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP16]])
+// TCHECK3-NEXT: [[TMP22:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
+// TCHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP22]])
// TCHECK3-NEXT: ret void
//
//
@@ -11113,21 +11230,24 @@ int bar(int n, double *ptr) {
// TCHECK3-NEXT: [[B2:%.*]] = alloca [10 x i32], align 4
// TCHECK3-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// TCHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// TCHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// TCHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// TCHECK3-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// TCHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// TCHECK3-NEXT: [[B:%.*]] = load ptr, ptr [[TMP3]], align 4
-// TCHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// TCHECK3-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// TCHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// TCHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// TCHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// TCHECK3-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// TCHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// TCHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// TCHECK3-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 4
+// TCHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// TCHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// TCHECK3-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP6]], align 4
// TCHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B2]], ptr align 4 [[B]], i32 40, i1 false)
-// TCHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4
-// TCHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], 1
+// TCHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4
+// TCHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 1
// TCHECK3-NEXT: store i32 [[ADD]], ptr [[A]], align 4
// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B2]], i32 0, i32 2
-// TCHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-// TCHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
+// TCHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
+// TCHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
// TCHECK3-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4
// TCHECK3-NEXT: ret void
//
diff --git a/clang/test/OpenMP/target_ompx_dyn_cgroup_mem_codegen.cpp b/clang/test/OpenMP/target_ompx_dyn_cgroup_mem_codegen.cpp
index af8c1e223705e..62e51ed0cf090 100644
--- a/clang/test/OpenMP/target_ompx_dyn_cgroup_mem_codegen.cpp
+++ b/clang/test/OpenMP/target_ompx_dyn_cgroup_mem_codegen.cpp
@@ -1002,7 +1002,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META32]]
// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META32]]
// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META32]]
-// CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]]) #[[ATTR2]]
+// CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]]) #[[ATTR2]], !inline_history [[META33:![0-9]+]]
// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META32]]
// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META32]]
// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META32]]
@@ -1933,7 +1933,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META33]]
// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META33]]
// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META33]]
-// CHECK3-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]]) #[[ATTR2]]
+// CHECK3-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]]) #[[ATTR2]], !inline_history [[META34:![0-9]+]]
// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias [[META33]]
// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias [[META33]]
// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias [[META33]]
@@ -2053,24 +2053,28 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK9-NEXT: store i32 [[TMP3]], ptr [[N]], align 4
-// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
-// CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
+// CHECK9-NEXT: store i32 [[TMP4]], ptr [[N]], align 4
+// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 8
-// CHECK9-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8
+// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 8
+// CHECK9-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP11]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 8
-// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP8]], i32 0)
-// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[N]], align 4
-// CHECK9-NEXT: store i32 [[TMP9]], ptr [[N_CASTED]], align 4
-// CHECK9-NEXT: [[TMP10:%.*]] = load i64, ptr [[N_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined, i64 [[TMP10]])
+// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP12]], i32 0)
+// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[N]], align 4
+// CHECK9-NEXT: store i32 [[TMP13]], ptr [[N_CASTED]], align 4
+// CHECK9-NEXT: [[TMP14:%.*]] = load i64, ptr [[N_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined, i64 [[TMP14]])
// CHECK9-NEXT: ret void
//
//
@@ -2288,11 +2292,13 @@ int bar(int n){
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK9-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK9-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.omp_outlined)
// CHECK9-NEXT: ret void
@@ -2318,21 +2324,25 @@ int bar(int n){
// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK9-NEXT: store i32 [[TMP3]], ptr [[B]], align 4
-// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
-// CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: store i32 [[TMP5]], ptr [[B]], align 4
+// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
+// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 8
+// CHECK9-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK9-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP9]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[B]], align 4
-// CHECK9-NEXT: store i32 [[TMP6]], ptr [[B_CASTED]], align 4
-// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[B_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[THIS]], i64 [[TMP7]])
+// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[B]], align 4
+// CHECK9-NEXT: store i32 [[TMP10]], ptr [[B_CASTED]], align 4
+// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[B_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[THIS]], i64 [[TMP11]])
// CHECK9-NEXT: ret void
//
//
@@ -2363,10 +2373,12 @@ int bar(int n){
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 8
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP3]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS]], i32 0, i32 0
// CHECK9-NEXT: store double 2.500000e+00, ptr [[A]], align 8
@@ -2380,8 +2392,9 @@ int bar(int n){
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP1]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.omp_outlined)
// CHECK9-NEXT: ret void
@@ -2410,28 +2423,32 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
-// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 8
-// CHECK9-NEXT: store i16 [[TMP5]], ptr [[B]], align 2
-// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
+// CHECK9-NEXT: store i32 [[TMP4]], ptr [[A]], align 4
+// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 8
-// CHECK9-NEXT: store i16 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 2
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: store i16 [[TMP7]], ptr [[B]], align 2
+// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8
+// CHECK9-NEXT: [[TMP10:%.*]] = load i16, ptr [[TMP9]], align 8
+// CHECK9-NEXT: store i16 [[TMP10]], ptr [[DOTCAPTURE_EXPR_]], align 2
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP11]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP8:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2
-// CHECK9-NEXT: [[TMP9:%.*]] = sext i16 [[TMP8]] to i32
-// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP9]], i32 0)
-// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
-// CHECK9-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
-// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP12:%.*]] = load i16, ptr [[B]], align 2
-// CHECK9-NEXT: store i16 [[TMP12]], ptr [[B_CASTED]], align 2
-// CHECK9-NEXT: [[TMP13:%.*]] = load i64, ptr [[B_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i64 [[TMP11]], i64 [[TMP13]])
+// CHECK9-NEXT: [[TMP12:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2
+// CHECK9-NEXT: [[TMP13:%.*]] = sext i16 [[TMP12]] to i32
+// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP13]], i32 0)
+// CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4
+// CHECK9-NEXT: store i32 [[TMP14]], ptr [[A_CASTED]], align 4
+// CHECK9-NEXT: [[TMP15:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK9-NEXT: [[TMP16:%.*]] = load i16, ptr [[B]], align 2
+// CHECK9-NEXT: store i16 [[TMP16]], ptr [[B_CASTED]], align 2
+// CHECK9-NEXT: [[TMP17:%.*]] = load i64, ptr [[B_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i64 [[TMP15]], i64 [[TMP17]])
// CHECK9-NEXT: ret void
//
//
@@ -2466,24 +2483,28 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK11-NEXT: store i32 [[TMP3]], ptr [[N]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK11-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
+// CHECK11-NEXT: store i32 [[TMP4]], ptr [[N]], align 4
+// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
-// CHECK11-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 4
+// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
+// CHECK11-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK11-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP11]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 4
-// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP8]], i32 0)
-// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[N]], align 4
-// CHECK11-NEXT: store i32 [[TMP9]], ptr [[N_CASTED]], align 4
-// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[N_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined, i32 [[TMP10]])
+// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP12]], i32 0)
+// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[N]], align 4
+// CHECK11-NEXT: store i32 [[TMP13]], ptr [[N_CASTED]], align 4
+// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[N_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined, i32 [[TMP14]])
// CHECK11-NEXT: ret void
//
//
@@ -2697,11 +2718,13 @@ int bar(int n){
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK11-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK11-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.omp_outlined)
// CHECK11-NEXT: ret void
@@ -2727,21 +2750,25 @@ int bar(int n){
// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK11-NEXT: store i32 [[TMP3]], ptr [[B]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK11-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: store i32 [[TMP5]], ptr [[B]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
+// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
+// CHECK11-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP9]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[B]], align 4
-// CHECK11-NEXT: store i32 [[TMP6]], ptr [[B_CASTED]], align 4
-// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[B_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[THIS]], i32 [[TMP7]])
+// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[B]], align 4
+// CHECK11-NEXT: store i32 [[TMP10]], ptr [[B_CASTED]], align 4
+// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[B_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[THIS]], i32 [[TMP11]])
// CHECK11-NEXT: ret void
//
//
@@ -2772,10 +2799,12 @@ int bar(int n){
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP3]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS]], i32 0, i32 0
// CHECK11-NEXT: store double 2.500000e+00, ptr [[A]], align 4
@@ -2789,8 +2818,9 @@ int bar(int n){
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP1]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.omp_outlined)
// CHECK11-NEXT: ret void
@@ -2819,28 +2849,32 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 4
-// CHECK11-NEXT: store i16 [[TMP5]], ptr [[B]], align 2
-// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
+// CHECK11-NEXT: store i32 [[TMP4]], ptr [[A]], align 4
+// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 4
-// CHECK11-NEXT: store i16 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 2
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: store i16 [[TMP7]], ptr [[B]], align 2
+// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 4
+// CHECK11-NEXT: [[TMP10:%.*]] = load i16, ptr [[TMP9]], align 4
+// CHECK11-NEXT: store i16 [[TMP10]], ptr [[DOTCAPTURE_EXPR_]], align 2
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK11-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP11]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP8:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2
-// CHECK11-NEXT: [[TMP9:%.*]] = sext i16 [[TMP8]] to i32
-// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP9]], i32 0)
-// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
-// CHECK11-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP12:%.*]] = load i16, ptr [[B]], align 2
-// CHECK11-NEXT: store i16 [[TMP12]], ptr [[B_CASTED]], align 2
-// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i32 [[TMP11]], i32 [[TMP13]])
+// CHECK11-NEXT: [[TMP12:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2
+// CHECK11-NEXT: [[TMP13:%.*]] = sext i16 [[TMP12]] to i32
+// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP13]], i32 0)
+// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4
+// CHECK11-NEXT: store i32 [[TMP14]], ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP16:%.*]] = load i16, ptr [[B]], align 2
+// CHECK11-NEXT: store i16 [[TMP16]], ptr [[B_CASTED]], align 2
+// CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[B_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i32 [[TMP15]], i32 [[TMP17]])
// CHECK11-NEXT: ret void
//
//
diff --git a/clang/test/OpenMP/target_parallel_codegen.cpp b/clang/test/OpenMP/target_parallel_codegen.cpp
index 266da5f073912..07fcf8354f4fb 100644
--- a/clang/test/OpenMP/target_parallel_codegen.cpp
+++ b/clang/test/OpenMP/target_parallel_codegen.cpp
@@ -682,7 +682,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META27]]
// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META27]]
// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META27]]
-// CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]]) #[[ATTR3]]
+// CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]]) #[[ATTR3]], !inline_history [[META28:![0-9]+]]
// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META27]]
// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META27]]
// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META27]]
@@ -859,14 +859,14 @@ int bar(int n){
// CHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8
// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META28:![0-9]+]], !align [[META29:![0-9]+]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META29:![0-9]+]], !align [[META30:![0-9]+]]
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META28]], !align [[META29]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META28]], !align [[META30:![0-9]+]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META29]], !align [[META30]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META29]], !align [[META31:![0-9]+]]
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META28]], !align [[META30]]
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META28]], !align [[META30]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META29]], !align [[META31]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META29]], !align [[META31]]
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
@@ -899,14 +899,14 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
// CHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8
// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META28]], !align [[META29]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META29]], !align [[META30]]
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META28]], !align [[META29]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META28]], !align [[META30]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META29]], !align [[META30]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META29]], !align [[META31]]
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META28]], !align [[META30]]
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META28]], !align [[META30]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META29]], !align [[META31]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META29]], !align [[META31]]
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4
@@ -1326,7 +1326,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META28]], !align [[META31:![0-9]+]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META29]], !align [[META32:![0-9]+]]
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8
@@ -1354,7 +1354,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META28]], !align [[META31]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META29]], !align [[META32]]
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
@@ -1388,7 +1388,7 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META28]], !align [[META29]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META29]], !align [[META30]]
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
@@ -1417,7 +1417,7 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META28]], !align [[META29]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META29]], !align [[META30]]
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4
@@ -1451,7 +1451,7 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META28]], !align [[META29]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META29]], !align [[META30]]
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
@@ -1475,7 +1475,7 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META28]], !align [[META29]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META29]], !align [[META30]]
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4
@@ -1882,7 +1882,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META28]]
// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META28]]
// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META28]]
-// CHECK3-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]]) #[[ATTR3]]
+// CHECK3-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]]) #[[ATTR3]], !inline_history [[META29:![0-9]+]]
// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias [[META28]]
// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias [[META28]]
// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias [[META28]]
@@ -2059,14 +2059,14 @@ int bar(int n){
// CHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4
// CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META29:![0-9]+]], !align [[META30:![0-9]+]]
+// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META30:![0-9]+]], !align [[META31:![0-9]+]]
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
-// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4, !nonnull [[META29]], !align [[META30]]
-// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META29]], !align [[META30]]
+// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4, !nonnull [[META30]], !align [[META31]]
+// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META30]], !align [[META31]]
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
-// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4, !nonnull [[META29]], !align [[META30]]
-// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META29]], !align [[META30]]
+// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4, !nonnull [[META30]], !align [[META31]]
+// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META30]], !align [[META31]]
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
@@ -2099,14 +2099,14 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
// CHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4
// CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
-// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META29]], !align [[META30]]
+// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META30]], !align [[META31]]
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
-// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4, !nonnull [[META29]], !align [[META30]]
-// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META29]], !align [[META30]]
+// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4, !nonnull [[META30]], !align [[META31]]
+// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META30]], !align [[META31]]
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
-// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4, !nonnull [[META29]], !align [[META30]]
-// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META29]], !align [[META30]]
+// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4, !nonnull [[META30]], !align [[META31]]
+// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META30]], !align [[META31]]
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
// CHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4
@@ -2526,7 +2526,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
-// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META29]], !align [[META31:![0-9]+]]
+// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META30]], !align [[META32:![0-9]+]]
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
@@ -2554,7 +2554,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
-// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META29]], !align [[META31]]
+// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META30]], !align [[META32]]
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
// CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
@@ -2588,7 +2588,7 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META29]], !align [[META30]]
+// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META30]], !align [[META31]]
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
@@ -2617,7 +2617,7 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
// CHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
-// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META29]], !align [[META30]]
+// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META30]], !align [[META31]]
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4
@@ -2651,7 +2651,7 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META29]], !align [[META30]]
+// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META30]], !align [[META31]]
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
@@ -2675,7 +2675,7 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
-// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META29]], !align [[META30]]
+// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META30]], !align [[META31]]
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
// CHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4
@@ -2698,8 +2698,9 @@ int bar(int n){
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP1]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.omp_outlined)
// CHECK9-NEXT: ret void
@@ -2724,16 +2725,18 @@ int bar(int n){
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 8
-// CHECK9-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 8
+// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
-// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined, i64 [[TMP4]])
+// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK9-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 2
+// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined, i64 [[TMP6]])
// CHECK9-NEXT: ret void
//
//
@@ -2774,22 +2777,25 @@ int bar(int n){
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
-// CHECK9-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK9-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 8
+// CHECK9-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
-// CHECK9-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4
-// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK9-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
-// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.omp_outlined, i64 [[TMP6]], i64 [[TMP8]])
+// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
+// CHECK9-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
+// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK9-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK9-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
+// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.omp_outlined, i64 [[TMP9]], i64 [[TMP11]])
// CHECK9-NEXT: ret void
//
//
@@ -2824,32 +2830,42 @@ int bar(int n){
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP3]], align 8
-// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8
-// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK9-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP6]], align 8
-// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK9-NEXT: [[C:%.*]] = load ptr, ptr [[TMP7]], align 8
-// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
-// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8
-// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 6
-// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
-// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 7
-// CHECK9-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP12]], align 8
-// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 8
-// CHECK9-NEXT: [[D:%.*]] = load ptr, ptr [[TMP13]], align 8
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 9
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 8
+// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
+// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP7]], align 8
+// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8
+// CHECK9-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP10]], align 8
+// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK9-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8
+// CHECK9-NEXT: [[C:%.*]] = load ptr, ptr [[TMP12]], align 8
+// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8
+// CHECK9-NEXT: [[TMP15:%.*]] = load i64, ptr [[TMP14]], align 8
+// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 6
+// CHECK9-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8
+// CHECK9-NEXT: [[TMP18:%.*]] = load i64, ptr [[TMP17]], align 8
+// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 7
+// CHECK9-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8
+// CHECK9-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP20]], align 8
+// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 8
+// CHECK9-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 8
+// CHECK9-NEXT: [[D:%.*]] = load ptr, ptr [[TMP22]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 9
+// CHECK9-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP23]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4
-// CHECK9-NEXT: store i32 [[TMP14]], ptr [[A_CASTED]], align 4
-// CHECK9-NEXT: [[TMP15:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.omp_outlined, i64 [[TMP15]], ptr [[B]], i64 [[TMP5]], ptr [[BN]], ptr [[C]], i64 [[TMP9]], i64 [[TMP11]], ptr [[CN]], ptr [[D]])
+// CHECK9-NEXT: [[TMP24:%.*]] = load i32, ptr [[A]], align 4
+// CHECK9-NEXT: store i32 [[TMP24]], ptr [[A_CASTED]], align 4
+// CHECK9-NEXT: [[TMP25:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.omp_outlined, i64 [[TMP25]], ptr [[B]], i64 [[TMP8]], ptr [[BN]], ptr [[C]], i64 [[TMP15]], i64 [[TMP18]], ptr [[CN]], ptr [[D]])
// CHECK9-NEXT: ret void
//
//
@@ -2938,30 +2954,35 @@ int bar(int n){
// CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
-// CHECK9-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK9-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 8
-// CHECK9-NEXT: store i8 [[TMP6]], ptr [[AAA]], align 1
-// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP7]], align 8
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK9-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 8
+// CHECK9-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8
+// CHECK9-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 8
+// CHECK9-NEXT: store i8 [[TMP9]], ptr [[AAA]], align 1
+// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8
+// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP11]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK9-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP12]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
-// CHECK9-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
-// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK9-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
-// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK9-NEXT: [[TMP12:%.*]] = load i8, ptr [[AAA]], align 1
-// CHECK9-NEXT: store i8 [[TMP12]], ptr [[AAA_CASTED]], align 1
-// CHECK9-NEXT: [[TMP13:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], ptr [[B]])
+// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[A]], align 4
+// CHECK9-NEXT: store i32 [[TMP13]], ptr [[A_CASTED]], align 4
+// CHECK9-NEXT: [[TMP14:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK9-NEXT: [[TMP15:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK9-NEXT: store i16 [[TMP15]], ptr [[AA_CASTED]], align 2
+// CHECK9-NEXT: [[TMP16:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK9-NEXT: [[TMP17:%.*]] = load i8, ptr [[AAA]], align 1
+// CHECK9-NEXT: store i8 [[TMP17]], ptr [[AAA_CASTED]], align 1
+// CHECK9-NEXT: [[TMP18:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.omp_outlined, i64 [[TMP14]], i64 [[TMP16]], i64 [[TMP18]], ptr [[B]])
// CHECK9-NEXT: ret void
//
//
@@ -3010,24 +3031,30 @@ int bar(int n){
// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK9-NEXT: store i32 [[TMP3]], ptr [[B]], align 4
-// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8
-// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[TMP6]], align 8
-// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK9-NEXT: [[C:%.*]] = load ptr, ptr [[TMP8]], align 8
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
+// CHECK9-NEXT: store i32 [[TMP5]], ptr [[B]], align 4
+// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
+// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP7]], align 8
+// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8
+// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
+// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK9-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8
+// CHECK9-NEXT: [[C:%.*]] = load ptr, ptr [[TMP13]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP14]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4
-// CHECK9-NEXT: store i32 [[TMP9]], ptr [[B_CASTED]], align 4
-// CHECK9-NEXT: [[TMP10:%.*]] = load i64, ptr [[B_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[THIS]], i64 [[TMP10]], i64 [[TMP5]], i64 [[TMP7]], ptr [[C]])
+// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[B]], align 4
+// CHECK9-NEXT: store i32 [[TMP15]], ptr [[B_CASTED]], align 4
+// CHECK9-NEXT: [[TMP16:%.*]] = load i64, ptr [[B_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[THIS]], i64 [[TMP16]], i64 [[TMP8]], i64 [[TMP11]], ptr [[C]])
// CHECK9-NEXT: ret void
//
//
@@ -3080,24 +3107,28 @@ int bar(int n){
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
-// CHECK9-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 8
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK9-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 8
+// CHECK9-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8
+// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP8]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK9-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP9]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// CHECK9-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4
-// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK9-NEXT: store i16 [[TMP8]], ptr [[AA_CASTED]], align 2
-// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.omp_outlined, i64 [[TMP7]], i64 [[TMP9]], ptr [[B]])
+// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
+// CHECK9-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
+// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK9-NEXT: [[TMP12:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK9-NEXT: store i16 [[TMP12]], ptr [[AA_CASTED]], align 2
+// CHECK9-NEXT: [[TMP13:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.omp_outlined, i64 [[TMP11]], i64 [[TMP13]], ptr [[B]])
// CHECK9-NEXT: ret void
//
//
@@ -3137,8 +3168,9 @@ int bar(int n){
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP1]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.omp_outlined)
// CHECK11-NEXT: ret void
@@ -3163,16 +3195,18 @@ int bar(int n){
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 4
-// CHECK11-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 4
+// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
-// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined, i32 [[TMP4]])
+// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK11-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 2
+// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined, i32 [[TMP6]])
// CHECK11-NEXT: ret void
//
//
@@ -3213,22 +3247,25 @@ int bar(int n){
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
-// CHECK11-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 4
+// CHECK11-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
-// CHECK11-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK11-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
-// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.omp_outlined, i32 [[TMP6]], i32 [[TMP8]])
+// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
+// CHECK11-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK11-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
+// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.omp_outlined, i32 [[TMP9]], i32 [[TMP11]])
// CHECK11-NEXT: ret void
//
//
@@ -3263,32 +3300,42 @@ int bar(int n){
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP3]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK11-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP6]], align 4
-// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK11-NEXT: [[C:%.*]] = load ptr, ptr [[TMP7]], align 4
-// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
-// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
-// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 6
-// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
-// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 7
-// CHECK11-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP12]], align 4
-// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 8
-// CHECK11-NEXT: [[D:%.*]] = load ptr, ptr [[TMP13]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 9
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
+// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
+// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4
+// CHECK11-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP10]], align 4
+// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 4
+// CHECK11-NEXT: [[C:%.*]] = load ptr, ptr [[TMP12]], align 4
+// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK11-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 4
+// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4
+// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 6
+// CHECK11-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 4
+// CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4
+// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 7
+// CHECK11-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 4
+// CHECK11-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP20]], align 4
+// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 8
+// CHECK11-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 4
+// CHECK11-NEXT: [[D:%.*]] = load ptr, ptr [[TMP22]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 9
+// CHECK11-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP23]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4
-// CHECK11-NEXT: store i32 [[TMP14]], ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.omp_outlined, i32 [[TMP15]], ptr [[B]], i32 [[TMP5]], ptr [[BN]], ptr [[C]], i32 [[TMP9]], i32 [[TMP11]], ptr [[CN]], ptr [[D]])
+// CHECK11-NEXT: [[TMP24:%.*]] = load i32, ptr [[A]], align 4
+// CHECK11-NEXT: store i32 [[TMP24]], ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP25:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.omp_outlined, i32 [[TMP25]], ptr [[B]], i32 [[TMP8]], ptr [[BN]], ptr [[C]], i32 [[TMP15]], i32 [[TMP18]], ptr [[CN]], ptr [[D]])
// CHECK11-NEXT: ret void
//
//
@@ -3377,30 +3424,35 @@ int bar(int n){
// CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
-// CHECK11-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK11-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 4
-// CHECK11-NEXT: store i8 [[TMP6]], ptr [[AAA]], align 1
-// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP7]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 4
+// CHECK11-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4
+// CHECK11-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 4
+// CHECK11-NEXT: store i8 [[TMP9]], ptr [[AAA]], align 1
+// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK11-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 4
+// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP11]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP12]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
-// CHECK11-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK11-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
-// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK11-NEXT: [[TMP12:%.*]] = load i8, ptr [[AAA]], align 1
-// CHECK11-NEXT: store i8 [[TMP12]], ptr [[AAA_CASTED]], align 1
-// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.omp_outlined, i32 [[TMP9]], i32 [[TMP11]], i32 [[TMP13]], ptr [[B]])
+// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[A]], align 4
+// CHECK11-NEXT: store i32 [[TMP13]], ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP15:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK11-NEXT: store i16 [[TMP15]], ptr [[AA_CASTED]], align 2
+// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK11-NEXT: [[TMP17:%.*]] = load i8, ptr [[AAA]], align 1
+// CHECK11-NEXT: store i8 [[TMP17]], ptr [[AAA_CASTED]], align 1
+// CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.omp_outlined, i32 [[TMP14]], i32 [[TMP16]], i32 [[TMP18]], ptr [[B]])
// CHECK11-NEXT: ret void
//
//
@@ -3449,24 +3501,30 @@ int bar(int n){
// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK11-NEXT: store i32 [[TMP3]], ptr [[B]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
-// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK11-NEXT: [[C:%.*]] = load ptr, ptr [[TMP8]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: store i32 [[TMP5]], ptr [[B]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
+// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
+// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4
+// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
+// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK11-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 4
+// CHECK11-NEXT: [[C:%.*]] = load ptr, ptr [[TMP13]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK11-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP14]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4
-// CHECK11-NEXT: store i32 [[TMP9]], ptr [[B_CASTED]], align 4
-// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[B_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[THIS]], i32 [[TMP10]], i32 [[TMP5]], i32 [[TMP7]], ptr [[C]])
+// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[B]], align 4
+// CHECK11-NEXT: store i32 [[TMP15]], ptr [[B_CASTED]], align 4
+// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[B_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[THIS]], i32 [[TMP16]], i32 [[TMP8]], i32 [[TMP11]], ptr [[C]])
// CHECK11-NEXT: ret void
//
//
@@ -3519,24 +3577,28 @@ int bar(int n){
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
-// CHECK11-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 4
+// CHECK11-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4
+// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP8]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP9]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// CHECK11-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK11-NEXT: store i16 [[TMP8]], ptr [[AA_CASTED]], align 2
-// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.omp_outlined, i32 [[TMP7]], i32 [[TMP9]], ptr [[B]])
+// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
+// CHECK11-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP12:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK11-NEXT: store i16 [[TMP12]], ptr [[AA_CASTED]], align 2
+// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.omp_outlined, i32 [[TMP11]], i32 [[TMP13]], ptr [[B]])
// CHECK11-NEXT: ret void
//
//
diff --git a/clang/test/OpenMP/target_parallel_for_codegen.cpp b/clang/test/OpenMP/target_parallel_for_codegen.cpp
index d585eb9cbd36e..1692f1548f435 100644
--- a/clang/test/OpenMP/target_parallel_for_codegen.cpp
+++ b/clang/test/OpenMP/target_parallel_for_codegen.cpp
@@ -1076,7 +1076,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META30]]
// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META30]]
// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META30]]
-// CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
+// CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]], !inline_history [[META31:![0-9]+]]
// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META30]]
// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META30]]
// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META30]]
@@ -1248,14 +1248,14 @@ int bar(int n){
// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META31:![0-9]+]], !align [[META32:![0-9]+]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META32:![0-9]+]], !align [[META33:![0-9]+]]
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META31]], !align [[META32]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META31]], !align [[META33:![0-9]+]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META32]], !align [[META33]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META32]], !align [[META34:![0-9]+]]
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META31]], !align [[META33]]
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META31]], !align [[META33]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META32]], !align [[META34]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META32]], !align [[META34]]
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
@@ -1300,14 +1300,14 @@ int bar(int n){
// CHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8
// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META31]], !align [[META32]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META32]], !align [[META33]]
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META31]], !align [[META32]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META31]], !align [[META33]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META32]], !align [[META33]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META32]], !align [[META34]]
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META31]], !align [[META33]]
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META31]], !align [[META33]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META32]], !align [[META34]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META32]], !align [[META34]]
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK1-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -1789,7 +1789,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META31]], !align [[META34:![0-9]+]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META32]], !align [[META35:![0-9]+]]
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8
@@ -1824,7 +1824,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META31]], !align [[META34]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META32]], !align [[META35]]
// CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
// CHECK1-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8
// CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
@@ -1901,7 +1901,7 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META31]], !align [[META32]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META32]], !align [[META33]]
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
@@ -1932,7 +1932,7 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META31]], !align [[META32]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META32]], !align [[META33]]
// CHECK1-NEXT: ret void
//
//
@@ -1949,7 +1949,7 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META31]], !align [[META32]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META32]], !align [[META33]]
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
@@ -1980,7 +1980,7 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META31]], !align [[META32]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META32]], !align [[META33]]
// CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
// CHECK1-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8
// CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
@@ -2803,7 +2803,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META33]]
// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META33]]
// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META33]]
-// CHECK3-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
+// CHECK3-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]], !inline_history [[META34:![0-9]+]]
// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias [[META33]]
// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias [[META33]]
// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias [[META33]]
@@ -3516,7 +3516,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
-// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META19]], !align [[META34:![0-9]+]]
+// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META19]], !align [[META35:![0-9]+]]
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
@@ -3551,7 +3551,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
-// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META19]], !align [[META34]]
+// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META19]], !align [[META35]]
// CHECK3-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
// CHECK3-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8
// CHECK3-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
@@ -3773,8 +3773,9 @@ int bar(int n){
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP1]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined)
// CHECK9-NEXT: ret void
@@ -3870,28 +3871,32 @@ int bar(int n){
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 8
-// CHECK9-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
-// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
-// CHECK9-NEXT: store i32 [[TMP4]], ptr [[LIN]], align 4
-// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 8
+// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
+// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 8
-// CHECK9-NEXT: store i32 [[TMP6]], ptr [[A]], align 4
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: store i32 [[TMP6]], ptr [[LIN]], align 4
+// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8
+// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 8
+// CHECK9-NEXT: store i32 [[TMP9]], ptr [[A]], align 4
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP10]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK9-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
-// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[LIN]], align 4
-// CHECK9-NEXT: store i32 [[TMP9]], ptr [[LIN_CASTED]], align 4
-// CHECK9-NEXT: [[TMP10:%.*]] = load i64, ptr [[LIN_CASTED]], align 8
-// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[A]], align 4
-// CHECK9-NEXT: store i32 [[TMP11]], ptr [[A_CASTED]], align 4
-// CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined, i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]])
+// CHECK9-NEXT: [[TMP11:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK9-NEXT: store i16 [[TMP11]], ptr [[AA_CASTED]], align 2
+// CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[LIN]], align 4
+// CHECK9-NEXT: store i32 [[TMP13]], ptr [[LIN_CASTED]], align 4
+// CHECK9-NEXT: [[TMP14:%.*]] = load i64, ptr [[LIN_CASTED]], align 8
+// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[A]], align 4
+// CHECK9-NEXT: store i32 [[TMP15]], ptr [[A_CASTED]], align 4
+// CHECK9-NEXT: [[TMP16:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined, i64 [[TMP12]], i64 [[TMP14]], i64 [[TMP16]])
// CHECK9-NEXT: ret void
//
//
@@ -4021,22 +4026,25 @@ int bar(int n){
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
-// CHECK9-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK9-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 8
+// CHECK9-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
-// CHECK9-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4
-// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK9-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
-// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i64 [[TMP6]], i64 [[TMP8]])
+// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
+// CHECK9-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
+// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK9-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK9-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
+// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i64 [[TMP9]], i64 [[TMP11]])
// CHECK9-NEXT: ret void
//
//
@@ -4124,38 +4132,49 @@ int bar(int n){
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP3]], align 8
-// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8
-// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK9-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP6]], align 8
-// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK9-NEXT: [[C:%.*]] = load ptr, ptr [[TMP7]], align 8
-// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
-// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8
-// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 6
-// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
-// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 7
-// CHECK9-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP12]], align 8
-// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 8
-// CHECK9-NEXT: [[D:%.*]] = load ptr, ptr [[TMP13]], align 8
-// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 9
-// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 8
-// CHECK9-NEXT: store i32 [[TMP15]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 10
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 8
+// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
+// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP7]], align 8
+// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8
+// CHECK9-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP10]], align 8
+// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK9-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8
+// CHECK9-NEXT: [[C:%.*]] = load ptr, ptr [[TMP12]], align 8
+// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8
+// CHECK9-NEXT: [[TMP15:%.*]] = load i64, ptr [[TMP14]], align 8
+// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 6
+// CHECK9-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8
+// CHECK9-NEXT: [[TMP18:%.*]] = load i64, ptr [[TMP17]], align 8
+// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 7
+// CHECK9-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8
+// CHECK9-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP20]], align 8
+// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 8
+// CHECK9-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 8
+// CHECK9-NEXT: [[D:%.*]] = load ptr, ptr [[TMP22]], align 8
+// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 9
+// CHECK9-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 8
+// CHECK9-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 8
+// CHECK9-NEXT: store i32 [[TMP25]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 10
+// CHECK9-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP26]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[A]], align 4
-// CHECK9-NEXT: store i32 [[TMP16]], ptr [[A_CASTED]], align 4
-// CHECK9-NEXT: [[TMP17:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: store i32 [[TMP18]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
-// CHECK9-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i64 [[TMP17]], ptr [[B]], i64 [[TMP5]], ptr [[BN]], ptr [[C]], i64 [[TMP9]], i64 [[TMP11]], ptr [[CN]], ptr [[D]], i64 [[TMP19]])
+// CHECK9-NEXT: [[TMP27:%.*]] = load i32, ptr [[A]], align 4
+// CHECK9-NEXT: store i32 [[TMP27]], ptr [[A_CASTED]], align 4
+// CHECK9-NEXT: [[TMP28:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK9-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: store i32 [[TMP29]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
+// CHECK9-NEXT: [[TMP30:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i64 [[TMP28]], ptr [[B]], i64 [[TMP8]], ptr [[BN]], ptr [[C]], i64 [[TMP15]], i64 [[TMP18]], ptr [[CN]], ptr [[D]], i64 [[TMP30]])
// CHECK9-NEXT: ret void
//
//
@@ -4315,30 +4334,35 @@ int bar(int n){
// CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
-// CHECK9-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK9-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 8
-// CHECK9-NEXT: store i8 [[TMP6]], ptr [[AAA]], align 1
-// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP7]], align 8
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK9-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 8
+// CHECK9-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8
+// CHECK9-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 8
+// CHECK9-NEXT: store i8 [[TMP9]], ptr [[AAA]], align 1
+// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8
+// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP11]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK9-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP12]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
-// CHECK9-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
-// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK9-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
-// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK9-NEXT: [[TMP12:%.*]] = load i8, ptr [[AAA]], align 1
-// CHECK9-NEXT: store i8 [[TMP12]], ptr [[AAA_CASTED]], align 1
-// CHECK9-NEXT: [[TMP13:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], ptr [[B]])
+// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[A]], align 4
+// CHECK9-NEXT: store i32 [[TMP13]], ptr [[A_CASTED]], align 4
+// CHECK9-NEXT: [[TMP14:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK9-NEXT: [[TMP15:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK9-NEXT: store i16 [[TMP15]], ptr [[AA_CASTED]], align 2
+// CHECK9-NEXT: [[TMP16:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK9-NEXT: [[TMP17:%.*]] = load i8, ptr [[AAA]], align 1
+// CHECK9-NEXT: store i8 [[TMP17]], ptr [[AAA_CASTED]], align 1
+// CHECK9-NEXT: [[TMP18:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined, i64 [[TMP14]], i64 [[TMP16]], i64 [[TMP18]], ptr [[B]])
// CHECK9-NEXT: ret void
//
//
@@ -4372,24 +4396,30 @@ int bar(int n){
// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK9-NEXT: store i32 [[TMP3]], ptr [[B]], align 4
-// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8
-// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[TMP6]], align 8
-// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK9-NEXT: [[C:%.*]] = load ptr, ptr [[TMP8]], align 8
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
+// CHECK9-NEXT: store i32 [[TMP5]], ptr [[B]], align 4
+// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
+// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP7]], align 8
+// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8
+// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
+// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK9-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8
+// CHECK9-NEXT: [[C:%.*]] = load ptr, ptr [[TMP13]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP14]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4
-// CHECK9-NEXT: store i32 [[TMP9]], ptr [[B_CASTED]], align 4
-// CHECK9-NEXT: [[TMP10:%.*]] = load i64, ptr [[B_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined, ptr [[THIS]], i64 [[TMP10]], i64 [[TMP5]], i64 [[TMP7]], ptr [[C]])
+// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[B]], align 4
+// CHECK9-NEXT: store i32 [[TMP15]], ptr [[B_CASTED]], align 4
+// CHECK9-NEXT: [[TMP16:%.*]] = load i64, ptr [[B_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined, ptr [[THIS]], i64 [[TMP16]], i64 [[TMP8]], i64 [[TMP11]], ptr [[C]])
// CHECK9-NEXT: ret void
//
//
@@ -4492,24 +4522,28 @@ int bar(int n){
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
-// CHECK9-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 8
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK9-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 8
+// CHECK9-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8
+// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP8]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK9-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP9]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// CHECK9-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4
-// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK9-NEXT: store i16 [[TMP8]], ptr [[AA_CASTED]], align 2
-// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined, i64 [[TMP7]], i64 [[TMP9]], ptr [[B]])
+// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
+// CHECK9-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
+// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK9-NEXT: [[TMP12:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK9-NEXT: store i16 [[TMP12]], ptr [[AA_CASTED]], align 2
+// CHECK9-NEXT: [[TMP13:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined, i64 [[TMP11]], i64 [[TMP13]], ptr [[B]])
// CHECK9-NEXT: ret void
//
//
@@ -4599,8 +4633,9 @@ int bar(int n){
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP1]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined)
// CHECK11-NEXT: ret void
@@ -4696,28 +4731,32 @@ int bar(int n){
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 4
-// CHECK11-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
-// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-// CHECK11-NEXT: store i32 [[TMP4]], ptr [[LIN]], align 4
-// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 4
+// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
+// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
-// CHECK11-NEXT: store i32 [[TMP6]], ptr [[A]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: store i32 [[TMP6]], ptr [[LIN]], align 4
+// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4
+// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
+// CHECK11-NEXT: store i32 [[TMP9]], ptr [[A]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP10]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK11-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
-// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[LIN]], align 4
-// CHECK11-NEXT: store i32 [[TMP9]], ptr [[LIN_CASTED]], align 4
-// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[LIN_CASTED]], align 4
-// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[A]], align 4
-// CHECK11-NEXT: store i32 [[TMP11]], ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined, i32 [[TMP8]], i32 [[TMP10]], i32 [[TMP12]])
+// CHECK11-NEXT: [[TMP11:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK11-NEXT: store i16 [[TMP11]], ptr [[AA_CASTED]], align 2
+// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[LIN]], align 4
+// CHECK11-NEXT: store i32 [[TMP13]], ptr [[LIN_CASTED]], align 4
+// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[LIN_CASTED]], align 4
+// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[A]], align 4
+// CHECK11-NEXT: store i32 [[TMP15]], ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined, i32 [[TMP12]], i32 [[TMP14]], i32 [[TMP16]])
// CHECK11-NEXT: ret void
//
//
@@ -4847,22 +4886,25 @@ int bar(int n){
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
-// CHECK11-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 4
+// CHECK11-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
-// CHECK11-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK11-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
-// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i32 [[TMP6]], i32 [[TMP8]])
+// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
+// CHECK11-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK11-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
+// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i32 [[TMP9]], i32 [[TMP11]])
// CHECK11-NEXT: ret void
//
//
@@ -4950,38 +4992,49 @@ int bar(int n){
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP3]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK11-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP6]], align 4
-// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK11-NEXT: [[C:%.*]] = load ptr, ptr [[TMP7]], align 4
-// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
-// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
-// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 6
-// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
-// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 7
-// CHECK11-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP12]], align 4
-// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 8
-// CHECK11-NEXT: [[D:%.*]] = load ptr, ptr [[TMP13]], align 4
-// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 9
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
+// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
+// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4
+// CHECK11-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP10]], align 4
+// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 4
+// CHECK11-NEXT: [[C:%.*]] = load ptr, ptr [[TMP12]], align 4
+// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK11-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 4
// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4
-// CHECK11-NEXT: store i32 [[TMP15]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 10
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 6
+// CHECK11-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 4
+// CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4
+// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 7
+// CHECK11-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 4
+// CHECK11-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP20]], align 4
+// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 8
+// CHECK11-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 4
+// CHECK11-NEXT: [[D:%.*]] = load ptr, ptr [[TMP22]], align 4
+// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 9
+// CHECK11-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 4
+// CHECK11-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 4
+// CHECK11-NEXT: store i32 [[TMP25]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 10
+// CHECK11-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP26]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[A]], align 4
-// CHECK11-NEXT: store i32 [[TMP16]], ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: store i32 [[TMP18]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
-// CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i32 [[TMP17]], ptr [[B]], i32 [[TMP5]], ptr [[BN]], ptr [[C]], i32 [[TMP9]], i32 [[TMP11]], ptr [[CN]], ptr [[D]], i32 [[TMP19]])
+// CHECK11-NEXT: [[TMP27:%.*]] = load i32, ptr [[A]], align 4
+// CHECK11-NEXT: store i32 [[TMP27]], ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP28:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: store i32 [[TMP29]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
+// CHECK11-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i32 [[TMP28]], ptr [[B]], i32 [[TMP8]], ptr [[BN]], ptr [[C]], i32 [[TMP15]], i32 [[TMP18]], ptr [[CN]], ptr [[D]], i32 [[TMP30]])
// CHECK11-NEXT: ret void
//
//
@@ -5141,30 +5194,35 @@ int bar(int n){
// CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
-// CHECK11-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK11-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 4
-// CHECK11-NEXT: store i8 [[TMP6]], ptr [[AAA]], align 1
-// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP7]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 4
+// CHECK11-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4
+// CHECK11-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 4
+// CHECK11-NEXT: store i8 [[TMP9]], ptr [[AAA]], align 1
+// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK11-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 4
+// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP11]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP12]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
-// CHECK11-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK11-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
-// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK11-NEXT: [[TMP12:%.*]] = load i8, ptr [[AAA]], align 1
-// CHECK11-NEXT: store i8 [[TMP12]], ptr [[AAA_CASTED]], align 1
-// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined, i32 [[TMP9]], i32 [[TMP11]], i32 [[TMP13]], ptr [[B]])
+// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[A]], align 4
+// CHECK11-NEXT: store i32 [[TMP13]], ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP15:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK11-NEXT: store i16 [[TMP15]], ptr [[AA_CASTED]], align 2
+// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK11-NEXT: [[TMP17:%.*]] = load i8, ptr [[AAA]], align 1
+// CHECK11-NEXT: store i8 [[TMP17]], ptr [[AAA_CASTED]], align 1
+// CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined, i32 [[TMP14]], i32 [[TMP16]], i32 [[TMP18]], ptr [[B]])
// CHECK11-NEXT: ret void
//
//
@@ -5198,24 +5256,30 @@ int bar(int n){
// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK11-NEXT: store i32 [[TMP3]], ptr [[B]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
-// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK11-NEXT: [[C:%.*]] = load ptr, ptr [[TMP8]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: store i32 [[TMP5]], ptr [[B]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
+// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
+// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4
+// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
+// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK11-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 4
+// CHECK11-NEXT: [[C:%.*]] = load ptr, ptr [[TMP13]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK11-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP14]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4
-// CHECK11-NEXT: store i32 [[TMP9]], ptr [[B_CASTED]], align 4
-// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[B_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined, ptr [[THIS]], i32 [[TMP10]], i32 [[TMP5]], i32 [[TMP7]], ptr [[C]])
+// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[B]], align 4
+// CHECK11-NEXT: store i32 [[TMP15]], ptr [[B_CASTED]], align 4
+// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[B_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined, ptr [[THIS]], i32 [[TMP16]], i32 [[TMP8]], i32 [[TMP11]], ptr [[C]])
// CHECK11-NEXT: ret void
//
//
@@ -5318,24 +5382,28 @@ int bar(int n){
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
-// CHECK11-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 4
+// CHECK11-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4
+// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP8]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP9]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// CHECK11-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK11-NEXT: store i16 [[TMP8]], ptr [[AA_CASTED]], align 2
-// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined, i32 [[TMP7]], i32 [[TMP9]], ptr [[B]])
+// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
+// CHECK11-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP12:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK11-NEXT: store i16 [[TMP12]], ptr [[AA_CASTED]], align 2
+// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined, i32 [[TMP11]], i32 [[TMP13]], ptr [[B]])
// CHECK11-NEXT: ret void
//
//
@@ -6188,7 +6256,7 @@ int bar(int n){
// CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META30]]
// CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META30]]
// CHECK17-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META30]]
-// CHECK17-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
+// CHECK17-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]], !inline_history [[META31:![0-9]+]]
// CHECK17-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META30]]
// CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META30]]
// CHECK17-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META30]]
@@ -6360,14 +6428,14 @@ int bar(int n){
// CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META31:![0-9]+]], !align [[META32:![0-9]+]]
+// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META32:![0-9]+]], !align [[META33:![0-9]+]]
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META31]], !align [[META32]]
-// CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META31]], !align [[META33:![0-9]+]]
+// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META32]], !align [[META33]]
+// CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META32]], !align [[META34:![0-9]+]]
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
-// CHECK17-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META31]], !align [[META33]]
-// CHECK17-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META31]], !align [[META33]]
+// CHECK17-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META32]], !align [[META34]]
+// CHECK17-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META32]], !align [[META34]]
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK17-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
// CHECK17-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
@@ -6412,14 +6480,14 @@ int bar(int n){
// CHECK17-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8
// CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
-// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META31]], !align [[META32]]
+// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META32]], !align [[META33]]
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META31]], !align [[META32]]
-// CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META31]], !align [[META33]]
+// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META32]], !align [[META33]]
+// CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META32]], !align [[META34]]
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
-// CHECK17-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META31]], !align [[META33]]
-// CHECK17-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META31]], !align [[META33]]
+// CHECK17-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META32]], !align [[META34]]
+// CHECK17-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META32]], !align [[META34]]
// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK17-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4
// CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -6901,7 +6969,7 @@ int bar(int n){
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
-// CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META31]], !align [[META34:![0-9]+]]
+// CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META32]], !align [[META35:![0-9]+]]
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
// CHECK17-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8
@@ -6936,7 +7004,7 @@ int bar(int n){
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
-// CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META31]], !align [[META34]]
+// CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META32]], !align [[META35]]
// CHECK17-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
// CHECK17-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8
// CHECK17-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
@@ -7013,7 +7081,7 @@ int bar(int n){
// CHECK17-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META31]], !align [[META32]]
+// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META32]], !align [[META33]]
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK17-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
@@ -7044,7 +7112,7 @@ int bar(int n){
// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
-// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META31]], !align [[META32]]
+// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META32]], !align [[META33]]
// CHECK17-NEXT: ret void
//
//
@@ -7061,7 +7129,7 @@ int bar(int n){
// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META31]], !align [[META32]]
+// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META32]], !align [[META33]]
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK17-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
@@ -7092,7 +7160,7 @@ int bar(int n){
// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
-// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META31]], !align [[META32]]
+// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META32]], !align [[META33]]
// CHECK17-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
// CHECK17-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8
// CHECK17-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
@@ -7915,7 +7983,7 @@ int bar(int n){
// CHECK19-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META33]]
// CHECK19-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META33]]
// CHECK19-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META33]]
-// CHECK19-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
+// CHECK19-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]], !inline_history [[META34:![0-9]+]]
// CHECK19-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias [[META33]]
// CHECK19-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias [[META33]]
// CHECK19-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias [[META33]]
@@ -8628,7 +8696,7 @@ int bar(int n){
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
-// CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META19]], !align [[META34:![0-9]+]]
+// CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META19]], !align [[META35:![0-9]+]]
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
// CHECK19-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
@@ -8663,7 +8731,7 @@ int bar(int n){
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
-// CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META19]], !align [[META34]]
+// CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META19]], !align [[META35]]
// CHECK19-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
// CHECK19-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8
// CHECK19-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
diff --git a/clang/test/OpenMP/target_parallel_for_simd_codegen.cpp b/clang/test/OpenMP/target_parallel_for_simd_codegen.cpp
index 5efed69be52be..d7bbae5effb99 100644
--- a/clang/test/OpenMP/target_parallel_for_simd_codegen.cpp
+++ b/clang/test/OpenMP/target_parallel_for_simd_codegen.cpp
@@ -789,7 +789,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META31]]
// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META31]]
// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META31]]
-// CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]]) #[[ATTR3]]
+// CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]]) #[[ATTR3]], !inline_history [[META32:![0-9]+]]
// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META31]]
// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META31]]
// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META31]]
@@ -889,32 +889,32 @@ int bar(int n){
// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32:![0-9]+]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]]
// CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]]
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
-// CHECK1-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP32]]
-// CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP32]]
-// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK1-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP33]]
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]]
// CHECK1-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
// CHECK1-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV]]
-// CHECK1-NEXT: store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP32]]
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK1-NEXT: store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP33]]
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]]
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK1-NEXT: store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK1-NEXT: store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]]
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]]
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
+// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
// CHECK1: omp.inner.for.end:
// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK1: omp.dispatch.inc:
@@ -1020,44 +1020,44 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP35:![0-9]+]]
-// CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP35]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP36:![0-9]+]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP36]]
// CHECK1-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
// CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP35]]
+// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP36]]
// CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
// CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
-// CHECK1-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP35]]
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP35]]
+// CHECK1-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP36]]
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP36]]
// CHECK1-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64
-// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP35]]
-// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP35]]
+// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP36]]
+// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP36]]
// CHECK1-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]]
// CHECK1-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]]
// CHECK1-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32
-// CHECK1-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP35]]
-// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP35]]
+// CHECK1-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP36]]
+// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP36]]
// CHECK1-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64
-// CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP35]]
-// CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP35]]
+// CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP36]]
+// CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP36]]
// CHECK1-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK1-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]]
// CHECK1-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32
-// CHECK1-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP35]]
-// CHECK1-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP35]]
+// CHECK1-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP36]]
+// CHECK1-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP36]]
// CHECK1-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32
// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1
// CHECK1-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16
-// CHECK1-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP35]]
+// CHECK1-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP36]]
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP35]]
+// CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP36]]
// CHECK1-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1
-// CHECK1-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP35]]
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]]
+// CHECK1-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP36]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
// CHECK1: omp.inner.for.end:
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK1: omp.loop.exit:
@@ -1143,32 +1143,32 @@ int bar(int n){
// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38:![0-9]+]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP38]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39:![0-9]+]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP39]]
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]]
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK1-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK1-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP38]]
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP38]]
+// CHECK1-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP39]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP39]]
// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP38]]
-// CHECK1-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP38]]
+// CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP39]]
+// CHECK1-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP39]]
// CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK1-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP38]]
+// CHECK1-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP39]]
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]]
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]]
// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]]
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]]
+// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]
// CHECK1: omp.inner.for.end:
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK1: omp.loop.exit:
@@ -1210,14 +1210,14 @@ int bar(int n){
// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META41:![0-9]+]], !align [[META42:![0-9]+]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META42:![0-9]+]], !align [[META43:![0-9]+]]
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META41]], !align [[META42]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META41]], !align [[META43:![0-9]+]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META42]], !align [[META43]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META42]], !align [[META44:![0-9]+]]
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META41]], !align [[META43]]
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META41]], !align [[META43]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META42]], !align [[META44]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META42]], !align [[META44]]
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
@@ -1262,14 +1262,14 @@ int bar(int n){
// CHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8
// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META41]], !align [[META42]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META42]], !align [[META43]]
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META41]], !align [[META42]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META41]], !align [[META43]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META42]], !align [[META43]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META42]], !align [[META44]]
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META41]], !align [[META43]]
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META41]], !align [[META43]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META42]], !align [[META44]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META42]], !align [[META44]]
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK1-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -1300,60 +1300,60 @@ int bar(int n){
// CHECK1: omp.dispatch.body:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44:![0-9]+]]
-// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45:![0-9]+]]
+// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK1-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8
-// CHECK1-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP44]]
-// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP45]]
+// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
-// CHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2
-// CHECK1-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double
// CHECK1-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
// CHECK1-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
-// CHECK1-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3
-// CHECK1-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
// CHECK1-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
// CHECK1-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
-// CHECK1-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1
// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2
-// CHECK1-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
-// CHECK1-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]]
// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 3
-// CHECK1-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
-// CHECK1-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
-// CHECK1-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
-// CHECK1-NEXT: store i64 [[ADD20]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: store i64 [[ADD20]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
-// CHECK1-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
// CHECK1-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
// CHECK1-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
-// CHECK1-NEXT: store i8 [[CONV23]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: store i8 [[CONV23]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
-// CHECK1-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]]
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]]
+// CHECK1-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]]
// CHECK1: omp.inner.for.end:
// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK1: omp.dispatch.inc:
@@ -1758,7 +1758,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META41]], !align [[META47:![0-9]+]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META42]], !align [[META48:![0-9]+]]
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8
@@ -1793,7 +1793,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META41]], !align [[META47]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META42]], !align [[META48]]
// CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
// CHECK1-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8
// CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
@@ -1816,37 +1816,37 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 8
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP48:![0-9]+]]
-// CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP48]]
+// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP49:![0-9]+]]
+// CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP49]]
// CHECK1-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP48]]
+// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP49]]
// CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
// CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
-// CHECK1-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP48]]
-// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP48]]
+// CHECK1-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP49]]
+// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP49]]
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
-// CHECK1-NEXT: store double [[ADD]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP48]]
+// CHECK1-NEXT: store double [[ADD]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP49]]
// CHECK1-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
-// CHECK1-NEXT: [[TMP13:%.*]] = load double, ptr [[A4]], align 8, !llvm.access.group [[ACC_GRP48]]
+// CHECK1-NEXT: [[TMP13:%.*]] = load double, ptr [[A4]], align 8, !llvm.access.group [[ACC_GRP49]]
// CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
-// CHECK1-NEXT: store double [[INC]], ptr [[A4]], align 8, !llvm.access.group [[ACC_GRP48]]
+// CHECK1-NEXT: store double [[INC]], ptr [[A4]], align 8, !llvm.access.group [[ACC_GRP49]]
// CHECK1-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
// CHECK1-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP14]]
// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
-// CHECK1-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP48]]
+// CHECK1-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP49]]
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP48]]
+// CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP49]]
// CHECK1-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1
-// CHECK1-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP48]]
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP49:![0-9]+]]
+// CHECK1-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP49]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP50:![0-9]+]]
// CHECK1: omp.inner.for.end:
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK1: omp.loop.exit:
@@ -1877,7 +1877,7 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META41]], !align [[META42]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META42]], !align [[META43]]
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
@@ -1908,7 +1908,7 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META41]], !align [[META42]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META42]], !align [[META43]]
// CHECK1-NEXT: ret void
//
//
@@ -1925,7 +1925,7 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META41]], !align [[META42]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META42]], !align [[META43]]
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
@@ -1956,7 +1956,7 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META41]], !align [[META42]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META42]], !align [[META43]]
// CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
// CHECK1-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8
// CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
@@ -1979,35 +1979,35 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP51:![0-9]+]]
-// CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP51]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP52:![0-9]+]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP52]]
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP51]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP52]]
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
-// CHECK1-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP51]]
-// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP51]]
+// CHECK1-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP52]]
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP52]]
// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP51]]
-// CHECK1-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP51]]
+// CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP52]]
+// CHECK1-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP52]]
// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
// CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK1-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP51]]
+// CHECK1-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP52]]
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2
-// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP51]]
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP52]]
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK1-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP51]]
+// CHECK1-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP52]]
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP51]]
+// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP52]]
// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1
-// CHECK1-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP51]]
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP52:![0-9]+]]
+// CHECK1-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP52]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP53:![0-9]+]]
// CHECK1: omp.inner.for.end:
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK1: omp.loop.exit:
@@ -2514,7 +2514,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META32]]
// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META32]]
// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META32]]
-// CHECK3-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]]) #[[ATTR3]]
+// CHECK3-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]]) #[[ATTR3]], !inline_history [[META33:![0-9]+]]
// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias [[META32]]
// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias [[META32]]
// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias [[META32]]
@@ -2563,7 +2563,7 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK3-NEXT: store ptr [[K]], ptr [[K_ADDR]], align 4
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 4, !nonnull [[META33:![0-9]+]], !align [[META34:![0-9]+]]
+// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 4, !nonnull [[META34:![0-9]+]], !align [[META35:![0-9]+]]
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
@@ -2591,7 +2591,7 @@ int bar(int n){
// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK3-NEXT: store ptr [[K]], ptr [[K_ADDR]], align 4
-// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 4, !nonnull [[META33]], !align [[META34]]
+// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 4, !nonnull [[META34]], !align [[META35]]
// CHECK3-NEXT: [[TMP1:%.*]] = load i64, ptr [[TMP0]], align 8
// CHECK3-NEXT: store i64 [[TMP1]], ptr [[DOTLINEAR_START]], align 8
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
@@ -2612,32 +2612,32 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK3: omp.inner.for.cond:
-// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35:![0-9]+]]
-// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP35]]
+// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]]
+// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP36]]
// CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK3: omp.inner.for.body:
-// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]]
+// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
-// CHECK3-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP35]]
-// CHECK3-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP35]]
-// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]]
+// CHECK3-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP36]]
+// CHECK3-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP36]]
+// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]
// CHECK3-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3
// CHECK3-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]
-// CHECK3-NEXT: store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP35]]
-// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]]
+// CHECK3-NEXT: store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP36]]
+// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]]
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK3-NEXT: store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]]
+// CHECK3-NEXT: store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]]
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK3: omp.inner.for.inc:
-// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]]
+// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
-// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]]
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]]
+// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]
+// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
// CHECK3: omp.inner.for.end:
// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK3: omp.dispatch.inc:
@@ -2743,44 +2743,44 @@ int bar(int n){
// CHECK3-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK3: omp.inner.for.cond:
-// CHECK3-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38:![0-9]+]]
-// CHECK3-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP38]]
+// CHECK3-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39:![0-9]+]]
+// CHECK3-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP39]]
// CHECK3-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
// CHECK3-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK3: omp.inner.for.body:
-// CHECK3-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]]
+// CHECK3-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]]
// CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
// CHECK3-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
-// CHECK3-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP38]]
-// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP38]]
+// CHECK3-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP39]]
+// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP39]]
// CHECK3-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64
-// CHECK3-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]]
-// CHECK3-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP38]]
+// CHECK3-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]]
+// CHECK3-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP39]]
// CHECK3-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]]
// CHECK3-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]]
// CHECK3-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32
-// CHECK3-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP38]]
-// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP38]]
+// CHECK3-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP39]]
+// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP39]]
// CHECK3-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64
-// CHECK3-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]]
-// CHECK3-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP38]]
+// CHECK3-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]]
+// CHECK3-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP39]]
// CHECK3-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK3-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]]
// CHECK3-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32
-// CHECK3-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP38]]
-// CHECK3-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP38]]
+// CHECK3-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP39]]
+// CHECK3-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP39]]
// CHECK3-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32
// CHECK3-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1
// CHECK3-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16
-// CHECK3-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP38]]
+// CHECK3-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP39]]
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK3: omp.inner.for.inc:
-// CHECK3-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]]
+// CHECK3-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]]
// CHECK3-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1
-// CHECK3-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]]
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]]
+// CHECK3-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]]
+// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]
// CHECK3: omp.inner.for.end:
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK3: omp.loop.exit:
@@ -2866,32 +2866,32 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK3: omp.inner.for.cond:
-// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP41:![0-9]+]]
-// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP41]]
+// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42:![0-9]+]]
+// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP42]]
// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK3: omp.inner.for.body:
-// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP41]]
+// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]]
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK3-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP41]]
-// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP41]]
+// CHECK3-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP42]]
+// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP42]]
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP41]]
-// CHECK3-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP41]]
+// CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP42]]
+// CHECK3-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP42]]
// CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK3-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP41]]
+// CHECK3-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP42]]
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK3: omp.inner.for.inc:
-// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP41]]
+// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]]
// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK3-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP41]]
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP42:![0-9]+]]
+// CHECK3-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]]
+// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]]
// CHECK3: omp.inner.for.end:
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK3: omp.loop.exit:
@@ -2933,14 +2933,14 @@ int bar(int n){
// CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META33]], !align [[META34]]
+// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META34]], !align [[META35]]
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
-// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4, !nonnull [[META33]], !align [[META34]]
-// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META33]], !align [[META34]]
+// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4, !nonnull [[META34]], !align [[META35]]
+// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META34]], !align [[META35]]
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
-// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4, !nonnull [[META33]], !align [[META34]]
-// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META33]], !align [[META34]]
+// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4, !nonnull [[META34]], !align [[META35]]
+// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META34]], !align [[META35]]
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
@@ -2985,14 +2985,14 @@ int bar(int n){
// CHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4
// CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
-// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META33]], !align [[META34]]
+// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META34]], !align [[META35]]
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
-// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4, !nonnull [[META33]], !align [[META34]]
-// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META33]], !align [[META34]]
+// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4, !nonnull [[META34]], !align [[META35]]
+// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META34]], !align [[META35]]
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
-// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4, !nonnull [[META33]], !align [[META34]]
-// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META33]], !align [[META34]]
+// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4, !nonnull [[META34]], !align [[META35]]
+// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META34]], !align [[META35]]
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK3-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4
// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -3023,60 +3023,60 @@ int bar(int n){
// CHECK3: omp.dispatch.body:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK3: omp.inner.for.cond:
-// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44:![0-9]+]]
-// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45:![0-9]+]]
+// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
// CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK3: omp.inner.for.body:
-// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8
-// CHECK3-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP44]]
-// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP45]]
+// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
-// CHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2
-// CHECK3-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double
// CHECK3-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
// CHECK3-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
-// CHECK3-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3
-// CHECK3-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
// CHECK3-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
// CHECK3-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
-// CHECK3-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1
// CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2
-// CHECK3-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
-// CHECK3-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
// CHECK3-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]]
// CHECK3-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 3
-// CHECK3-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
-// CHECK3-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
-// CHECK3-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
-// CHECK3-NEXT: store i64 [[ADD20]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: store i64 [[ADD20]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
-// CHECK3-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
// CHECK3-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
// CHECK3-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
-// CHECK3-NEXT: store i8 [[CONV23]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: store i8 [[CONV23]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK3: omp.inner.for.inc:
-// CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
-// CHECK3-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]]
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]]
+// CHECK3-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]
+// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]]
// CHECK3: omp.inner.for.end:
// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK3: omp.dispatch.inc:
@@ -3481,7 +3481,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
-// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META33]], !align [[META47:![0-9]+]]
+// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META34]], !align [[META48:![0-9]+]]
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
@@ -3516,7 +3516,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
-// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META33]], !align [[META47]]
+// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META34]], !align [[META48]]
// CHECK3-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
// CHECK3-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8
// CHECK3-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
@@ -3539,37 +3539,37 @@ int bar(int n){
// CHECK3-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 8
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK3: omp.inner.for.cond:
-// CHECK3-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP48:![0-9]+]]
-// CHECK3-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP48]]
+// CHECK3-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP49:![0-9]+]]
+// CHECK3-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP49]]
// CHECK3-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK3: omp.inner.for.body:
-// CHECK3-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP48]]
+// CHECK3-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP49]]
// CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
// CHECK3-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
-// CHECK3-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP48]]
-// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP48]]
+// CHECK3-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP49]]
+// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP49]]
// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
-// CHECK3-NEXT: store double [[ADD]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP48]]
+// CHECK3-NEXT: store double [[ADD]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP49]]
// CHECK3-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
-// CHECK3-NEXT: [[TMP13:%.*]] = load double, ptr [[A4]], align 4, !llvm.access.group [[ACC_GRP48]]
+// CHECK3-NEXT: [[TMP13:%.*]] = load double, ptr [[A4]], align 4, !llvm.access.group [[ACC_GRP49]]
// CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
-// CHECK3-NEXT: store double [[INC]], ptr [[A4]], align 4, !llvm.access.group [[ACC_GRP48]]
+// CHECK3-NEXT: store double [[INC]], ptr [[A4]], align 4, !llvm.access.group [[ACC_GRP49]]
// CHECK3-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
// CHECK3-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP14]]
// CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
-// CHECK3-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP48]]
+// CHECK3-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP49]]
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK3: omp.inner.for.inc:
-// CHECK3-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP48]]
+// CHECK3-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP49]]
// CHECK3-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1
-// CHECK3-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP48]]
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP49:![0-9]+]]
+// CHECK3-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP49]]
+// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP50:![0-9]+]]
// CHECK3: omp.inner.for.end:
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK3: omp.loop.exit:
@@ -3600,7 +3600,7 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META33]], !align [[META34]]
+// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META34]], !align [[META35]]
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
@@ -3631,7 +3631,7 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
// CHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
-// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META33]], !align [[META34]]
+// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META34]], !align [[META35]]
// CHECK3-NEXT: ret void
//
//
@@ -3648,7 +3648,7 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META33]], !align [[META34]]
+// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META34]], !align [[META35]]
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
@@ -3679,7 +3679,7 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
-// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META33]], !align [[META34]]
+// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META34]], !align [[META35]]
// CHECK3-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
// CHECK3-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8
// CHECK3-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
@@ -3702,35 +3702,35 @@ int bar(int n){
// CHECK3-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK3: omp.inner.for.cond:
-// CHECK3-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP51:![0-9]+]]
-// CHECK3-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP51]]
+// CHECK3-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP52:![0-9]+]]
+// CHECK3-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP52]]
// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK3: omp.inner.for.body:
-// CHECK3-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP51]]
+// CHECK3-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP52]]
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
-// CHECK3-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP51]]
-// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP51]]
+// CHECK3-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP52]]
+// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP52]]
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP51]]
-// CHECK3-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP51]]
+// CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP52]]
+// CHECK3-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP52]]
// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
// CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK3-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP51]]
+// CHECK3-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP52]]
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2
-// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP51]]
+// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP52]]
// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK3-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP51]]
+// CHECK3-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP52]]
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK3: omp.inner.for.inc:
-// CHECK3-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP51]]
+// CHECK3-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP52]]
// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1
-// CHECK3-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP51]]
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP52:![0-9]+]]
+// CHECK3-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP52]]
+// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP53:![0-9]+]]
// CHECK3: omp.inner.for.end:
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK3: omp.loop.exit:
@@ -4241,7 +4241,7 @@ int bar(int n){
// CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META31]]
// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META31]]
// CHECK5-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META31]]
-// CHECK5-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]]) #[[ATTR3]]
+// CHECK5-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]]) #[[ATTR3]], !inline_history [[META32:![0-9]+]]
// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META31]]
// CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META31]]
// CHECK5-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META31]]
@@ -4341,32 +4341,32 @@ int bar(int n){
// CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK5: omp.inner.for.cond:
-// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32:![0-9]+]]
-// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]]
+// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]]
// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body:
-// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]]
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
-// CHECK5-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP32]]
-// CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP32]]
-// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK5-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]]
+// CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP33]]
+// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]]
// CHECK5-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
// CHECK5-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV]]
-// CHECK5-NEXT: store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP32]]
-// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK5-NEXT: store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP33]]
+// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]]
// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK5-NEXT: store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK5-NEXT: store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]]
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK5: omp.body.continue:
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK5: omp.inner.for.inc:
-// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]]
// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK5-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
+// CHECK5-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
// CHECK5: omp.inner.for.end:
// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK5: omp.dispatch.inc:
@@ -4472,44 +4472,44 @@ int bar(int n){
// CHECK5-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK5: omp.inner.for.cond:
-// CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP35:![0-9]+]]
-// CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP35]]
+// CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP36:![0-9]+]]
+// CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP36]]
// CHECK5-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
// CHECK5-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body:
-// CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP35]]
+// CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP36]]
// CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
// CHECK5-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
-// CHECK5-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP35]]
-// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP35]]
+// CHECK5-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP36]]
+// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP36]]
// CHECK5-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64
-// CHECK5-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP35]]
-// CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP35]]
+// CHECK5-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP36]]
+// CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP36]]
// CHECK5-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]]
// CHECK5-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]]
// CHECK5-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32
-// CHECK5-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP35]]
-// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP35]]
+// CHECK5-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP36]]
+// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP36]]
// CHECK5-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64
-// CHECK5-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP35]]
-// CHECK5-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP35]]
+// CHECK5-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP36]]
+// CHECK5-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP36]]
// CHECK5-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK5-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]]
// CHECK5-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32
-// CHECK5-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP35]]
-// CHECK5-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP35]]
+// CHECK5-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP36]]
+// CHECK5-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP36]]
// CHECK5-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32
// CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1
// CHECK5-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16
-// CHECK5-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP35]]
+// CHECK5-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP36]]
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK5: omp.body.continue:
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK5: omp.inner.for.inc:
-// CHECK5-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP35]]
+// CHECK5-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP36]]
// CHECK5-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1
-// CHECK5-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP35]]
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]]
+// CHECK5-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP36]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
// CHECK5: omp.inner.for.end:
// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK5: omp.loop.exit:
@@ -4595,32 +4595,32 @@ int bar(int n){
// CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK5: omp.inner.for.cond:
-// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38:![0-9]+]]
-// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP38]]
+// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39:![0-9]+]]
+// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP39]]
// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body:
-// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]]
+// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]]
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK5-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP38]]
-// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP38]]
+// CHECK5-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP39]]
+// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP39]]
// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK5-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP38]]
-// CHECK5-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP38]]
+// CHECK5-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP39]]
+// CHECK5-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP39]]
// CHECK5-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK5-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK5-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP38]]
+// CHECK5-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP39]]
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK5: omp.body.continue:
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK5: omp.inner.for.inc:
-// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]]
+// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]]
// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK5-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]]
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]]
+// CHECK5-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]
// CHECK5: omp.inner.for.end:
// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK5: omp.loop.exit:
@@ -4662,14 +4662,14 @@ int bar(int n){
// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META41:![0-9]+]], !align [[META42:![0-9]+]]
+// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META42:![0-9]+]], !align [[META43:![0-9]+]]
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
-// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META41]], !align [[META42]]
-// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META41]], !align [[META43:![0-9]+]]
+// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META42]], !align [[META43]]
+// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META42]], !align [[META44:![0-9]+]]
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
// CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
-// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META41]], !align [[META43]]
-// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META41]], !align [[META43]]
+// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META42]], !align [[META44]]
+// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META42]], !align [[META44]]
// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
// CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
@@ -4714,14 +4714,14 @@ int bar(int n){
// CHECK5-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8
// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
-// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META41]], !align [[META42]]
+// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META42]], !align [[META43]]
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
-// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META41]], !align [[META42]]
-// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META41]], !align [[META43]]
+// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META42]], !align [[META43]]
+// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META42]], !align [[META44]]
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
// CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
-// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META41]], !align [[META43]]
-// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META41]], !align [[META43]]
+// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META42]], !align [[META44]]
+// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META42]], !align [[META44]]
// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK5-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4
// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -4752,60 +4752,60 @@ int bar(int n){
// CHECK5: omp.dispatch.body:
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK5: omp.inner.for.cond:
-// CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44:![0-9]+]]
-// CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45:![0-9]+]]
+// CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
// CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body:
-// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8
-// CHECK5-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP44]]
-// CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK5-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP45]]
+// CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
-// CHECK5-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK5-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2
-// CHECK5-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK5-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK5-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double
// CHECK5-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
// CHECK5-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
-// CHECK5-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK5-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3
-// CHECK5-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK5-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK5-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
// CHECK5-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
// CHECK5-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
-// CHECK5-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK5-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK5-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1
// CHECK5-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2
-// CHECK5-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK5-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK5-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
-// CHECK5-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK5-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK5-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
// CHECK5-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]]
// CHECK5-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 3
-// CHECK5-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK5-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK5-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
-// CHECK5-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK5-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK5-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
-// CHECK5-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK5-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK5-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
-// CHECK5-NEXT: store i64 [[ADD20]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK5-NEXT: store i64 [[ADD20]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK5-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
-// CHECK5-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK5-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK5-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
// CHECK5-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
// CHECK5-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
-// CHECK5-NEXT: store i8 [[CONV23]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK5-NEXT: store i8 [[CONV23]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK5: omp.body.continue:
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK5: omp.inner.for.inc:
-// CHECK5-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK5-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK5-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
-// CHECK5-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]]
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]]
+// CHECK5-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]]
// CHECK5: omp.inner.for.end:
// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK5: omp.dispatch.inc:
@@ -5237,7 +5237,7 @@ int bar(int n){
// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
-// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META41]], !align [[META47:![0-9]+]]
+// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META42]], !align [[META48:![0-9]+]]
// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_ADDR]], align 4
// CHECK5-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4
// CHECK5-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8
@@ -5292,7 +5292,7 @@ int bar(int n){
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
-// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META41]], !align [[META47]]
+// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META42]], !align [[META48]]
// CHECK5-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
// CHECK5-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8
// CHECK5-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
@@ -5319,37 +5319,37 @@ int bar(int n){
// CHECK5-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_IV]], align 8
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK5: omp.inner.for.cond:
-// CHECK5-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP48:![0-9]+]]
-// CHECK5-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP48]]
+// CHECK5-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP49:![0-9]+]]
+// CHECK5-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP49]]
// CHECK5-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]]
// CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body:
-// CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP48]]
+// CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP49]]
// CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400
// CHECK5-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
-// CHECK5-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP48]]
-// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP48]]
+// CHECK5-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP49]]
+// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP49]]
// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP13]] to double
// CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
-// CHECK5-NEXT: store double [[ADD]], ptr [[A]], align 8, !nontemporal [[META49:![0-9]+]], !llvm.access.group [[ACC_GRP48]]
+// CHECK5-NEXT: store double [[ADD]], ptr [[A]], align 8, !nontemporal [[META50:![0-9]+]], !llvm.access.group [[ACC_GRP49]]
// CHECK5-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
-// CHECK5-NEXT: [[TMP14:%.*]] = load double, ptr [[A4]], align 8, !nontemporal [[META49]], !llvm.access.group [[ACC_GRP48]]
+// CHECK5-NEXT: [[TMP14:%.*]] = load double, ptr [[A4]], align 8, !nontemporal [[META50]], !llvm.access.group [[ACC_GRP49]]
// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
-// CHECK5-NEXT: store double [[INC]], ptr [[A4]], align 8, !nontemporal [[META49]], !llvm.access.group [[ACC_GRP48]]
+// CHECK5-NEXT: store double [[INC]], ptr [[A4]], align 8, !nontemporal [[META50]], !llvm.access.group [[ACC_GRP49]]
// CHECK5-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
// CHECK5-NEXT: [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]]
// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP15]]
// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
-// CHECK5-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP48]]
+// CHECK5-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP49]]
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK5: omp.body.continue:
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK5: omp.inner.for.inc:
-// CHECK5-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP48]]
+// CHECK5-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP49]]
// CHECK5-NEXT: [[ADD7:%.*]] = add i64 [[TMP16]], 1
-// CHECK5-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP48]]
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP50:![0-9]+]]
+// CHECK5-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP49]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP51:![0-9]+]]
// CHECK5: omp.inner.for.end:
// CHECK5-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK5: omp_if.else:
@@ -5401,7 +5401,7 @@ int bar(int n){
// CHECK5-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK5-NEXT: [[ADD28:%.*]] = add i64 [[TMP28]], 1
// CHECK5-NEXT: store i64 [[ADD28]], ptr [[DOTOMP_IV]], align 8
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP52:![0-9]+]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP53:![0-9]+]]
// CHECK5: omp.inner.for.end29:
// CHECK5-NEXT: br label [[OMP_IF_END]]
// CHECK5: omp_if.end:
@@ -5436,7 +5436,7 @@ int bar(int n){
// CHECK5-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META41]], !align [[META42]]
+// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META42]], !align [[META43]]
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
// CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
@@ -5467,7 +5467,7 @@ int bar(int n){
// CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
// CHECK5-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
-// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META41]], !align [[META42]]
+// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META42]], !align [[META43]]
// CHECK5-NEXT: ret void
//
//
@@ -5484,7 +5484,7 @@ int bar(int n){
// CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META41]], !align [[META42]]
+// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META42]], !align [[META43]]
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
// CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
@@ -5515,7 +5515,7 @@ int bar(int n){
// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
// CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
-// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META41]], !align [[META42]]
+// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META42]], !align [[META43]]
// CHECK5-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
// CHECK5-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8
// CHECK5-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
@@ -5538,35 +5538,35 @@ int bar(int n){
// CHECK5-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK5: omp.inner.for.cond:
-// CHECK5-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP54:![0-9]+]]
-// CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP54]]
+// CHECK5-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP55:![0-9]+]]
+// CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP55]]
// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body:
-// CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP54]]
+// CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP55]]
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
-// CHECK5-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP54]]
-// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP54]]
+// CHECK5-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP55]]
+// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP55]]
// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK5-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP54]]
-// CHECK5-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP54]]
+// CHECK5-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP55]]
+// CHECK5-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP55]]
// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32
// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
// CHECK5-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK5-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP54]]
+// CHECK5-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP55]]
// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2
-// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP54]]
+// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP55]]
// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK5-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP54]]
+// CHECK5-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP55]]
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK5: omp.body.continue:
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK5: omp.inner.for.inc:
-// CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP54]]
+// CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP55]]
// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1
-// CHECK5-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP54]]
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP55:![0-9]+]]
+// CHECK5-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP55]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP56:![0-9]+]]
// CHECK5: omp.inner.for.end:
// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK5: omp.loop.exit:
@@ -6073,7 +6073,7 @@ int bar(int n){
// CHECK7-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META32]]
// CHECK7-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META32]]
// CHECK7-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META32]]
-// CHECK7-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]]) #[[ATTR3]]
+// CHECK7-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]]) #[[ATTR3]], !inline_history [[META33:![0-9]+]]
// CHECK7-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias [[META32]]
// CHECK7-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias [[META32]]
// CHECK7-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias [[META32]]
@@ -6122,7 +6122,7 @@ int bar(int n){
// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK7-NEXT: store ptr [[K]], ptr [[K_ADDR]], align 4
// CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 4, !nonnull [[META33:![0-9]+]], !align [[META34:![0-9]+]]
+// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 4, !nonnull [[META34:![0-9]+]], !align [[META35:![0-9]+]]
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK7-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
@@ -6150,7 +6150,7 @@ int bar(int n){
// CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK7-NEXT: store ptr [[K]], ptr [[K_ADDR]], align 4
-// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 4, !nonnull [[META33]], !align [[META34]]
+// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 4, !nonnull [[META34]], !align [[META35]]
// CHECK7-NEXT: [[TMP1:%.*]] = load i64, ptr [[TMP0]], align 8
// CHECK7-NEXT: store i64 [[TMP1]], ptr [[DOTLINEAR_START]], align 8
// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
@@ -6171,32 +6171,32 @@ int bar(int n){
// CHECK7-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK7: omp.inner.for.cond:
-// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35:![0-9]+]]
-// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP35]]
+// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]]
+// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP36]]
// CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK7: omp.inner.for.body:
-// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]]
+// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]
// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
-// CHECK7-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP35]]
-// CHECK7-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP35]]
-// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]]
+// CHECK7-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP36]]
+// CHECK7-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP36]]
+// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]
// CHECK7-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3
// CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64
// CHECK7-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]
-// CHECK7-NEXT: store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP35]]
-// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]]
+// CHECK7-NEXT: store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP36]]
+// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]]
// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK7-NEXT: store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]]
+// CHECK7-NEXT: store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]]
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK7: omp.body.continue:
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK7: omp.inner.for.inc:
-// CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]]
+// CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]
// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
-// CHECK7-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]]
-// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]]
+// CHECK7-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]
+// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
// CHECK7: omp.inner.for.end:
// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK7: omp.dispatch.inc:
@@ -6302,44 +6302,44 @@ int bar(int n){
// CHECK7-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK7: omp.inner.for.cond:
-// CHECK7-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38:![0-9]+]]
-// CHECK7-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP38]]
+// CHECK7-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39:![0-9]+]]
+// CHECK7-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP39]]
// CHECK7-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
// CHECK7-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK7: omp.inner.for.body:
-// CHECK7-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]]
+// CHECK7-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]]
// CHECK7-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
// CHECK7-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
-// CHECK7-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP38]]
-// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP38]]
+// CHECK7-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP39]]
+// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP39]]
// CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64
-// CHECK7-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]]
-// CHECK7-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP38]]
+// CHECK7-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]]
+// CHECK7-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP39]]
// CHECK7-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]]
// CHECK7-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]]
// CHECK7-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32
-// CHECK7-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP38]]
-// CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP38]]
+// CHECK7-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4, !llvm.access.group [[ACC_GRP39]]
+// CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP39]]
// CHECK7-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64
-// CHECK7-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]]
-// CHECK7-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP38]]
+// CHECK7-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]]
+// CHECK7-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP39]]
// CHECK7-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]]
// CHECK7-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]]
// CHECK7-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32
-// CHECK7-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP38]]
-// CHECK7-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP38]]
+// CHECK7-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP39]]
+// CHECK7-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP39]]
// CHECK7-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32
// CHECK7-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1
// CHECK7-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16
-// CHECK7-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP38]]
+// CHECK7-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP39]]
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK7: omp.body.continue:
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK7: omp.inner.for.inc:
-// CHECK7-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]]
+// CHECK7-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]]
// CHECK7-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1
-// CHECK7-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]]
-// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]]
+// CHECK7-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]]
+// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]
// CHECK7: omp.inner.for.end:
// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK7: omp.loop.exit:
@@ -6425,32 +6425,32 @@ int bar(int n){
// CHECK7-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK7: omp.inner.for.cond:
-// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP41:![0-9]+]]
-// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP41]]
+// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42:![0-9]+]]
+// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP42]]
// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK7: omp.inner.for.body:
-// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP41]]
+// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]]
// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
// CHECK7-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16
-// CHECK7-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP41]]
-// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP41]]
+// CHECK7-NEXT: store i16 [[CONV]], ptr [[IT]], align 2, !llvm.access.group [[ACC_GRP42]]
+// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP42]]
// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK7-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP41]]
-// CHECK7-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP41]]
+// CHECK7-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP42]]
+// CHECK7-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP42]]
// CHECK7-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
// CHECK7-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
-// CHECK7-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP41]]
+// CHECK7-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP42]]
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK7: omp.body.continue:
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK7: omp.inner.for.inc:
-// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP41]]
+// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]]
// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK7-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP41]]
-// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP42:![0-9]+]]
+// CHECK7-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]]
+// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]]
// CHECK7: omp.inner.for.end:
// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK7: omp.loop.exit:
@@ -6492,14 +6492,14 @@ int bar(int n){
// CHECK7-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META33]], !align [[META34]]
+// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META34]], !align [[META35]]
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
-// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4, !nonnull [[META33]], !align [[META34]]
-// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META33]], !align [[META34]]
+// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4, !nonnull [[META34]], !align [[META35]]
+// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META34]], !align [[META35]]
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
-// CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4, !nonnull [[META33]], !align [[META34]]
-// CHECK7-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META33]], !align [[META34]]
+// CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4, !nonnull [[META34]], !align [[META35]]
+// CHECK7-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META34]], !align [[META35]]
// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK7-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
// CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
@@ -6544,14 +6544,14 @@ int bar(int n){
// CHECK7-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4
// CHECK7-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
// CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
-// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META33]], !align [[META34]]
+// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META34]], !align [[META35]]
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
-// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4, !nonnull [[META33]], !align [[META34]]
-// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META33]], !align [[META34]]
+// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4, !nonnull [[META34]], !align [[META35]]
+// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META34]], !align [[META35]]
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
-// CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4, !nonnull [[META33]], !align [[META34]]
-// CHECK7-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META33]], !align [[META34]]
+// CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4, !nonnull [[META34]], !align [[META35]]
+// CHECK7-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META34]], !align [[META35]]
// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK7-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4
// CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -6582,60 +6582,60 @@ int bar(int n){
// CHECK7: omp.dispatch.body:
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK7: omp.inner.for.cond:
-// CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44:![0-9]+]]
-// CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45:![0-9]+]]
+// CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK7-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
// CHECK7-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK7: omp.inner.for.body:
-// CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
// CHECK7-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8
-// CHECK7-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP44]]
-// CHECK7-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK7-NEXT: store i8 [[CONV]], ptr [[IT]], align 1, !llvm.access.group [[ACC_GRP45]]
+// CHECK7-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
-// CHECK7-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK7-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2
-// CHECK7-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK7-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK7-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double
// CHECK7-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
// CHECK7-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
-// CHECK7-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK7-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3
-// CHECK7-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK7-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK7-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
// CHECK7-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
// CHECK7-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
-// CHECK7-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK7-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK7-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1
// CHECK7-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2
-// CHECK7-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK7-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK7-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
-// CHECK7-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK7-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK7-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
// CHECK7-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]]
// CHECK7-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 3
-// CHECK7-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK7-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK7-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
-// CHECK7-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK7-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK7-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
-// CHECK7-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK7-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK7-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
-// CHECK7-NEXT: store i64 [[ADD20]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK7-NEXT: store i64 [[ADD20]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK7-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
-// CHECK7-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK7-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK7-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
// CHECK7-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
// CHECK7-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
-// CHECK7-NEXT: store i8 [[CONV23]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK7-NEXT: store i8 [[CONV23]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK7: omp.body.continue:
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK7: omp.inner.for.inc:
-// CHECK7-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK7-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK7-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
-// CHECK7-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]]
-// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]]
+// CHECK7-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]
+// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]]
// CHECK7: omp.inner.for.end:
// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK7: omp.dispatch.inc:
@@ -7067,7 +7067,7 @@ int bar(int n){
// CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
-// CHECK7-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META33]], !align [[META47:![0-9]+]]
+// CHECK7-NEXT: [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META34]], !align [[META48:![0-9]+]]
// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_ADDR]], align 4
// CHECK7-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4
// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 4
@@ -7122,7 +7122,7 @@ int bar(int n){
// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
-// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META33]], !align [[META47]]
+// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META34]], !align [[META48]]
// CHECK7-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
// CHECK7-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8
// CHECK7-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
@@ -7149,37 +7149,37 @@ int bar(int n){
// CHECK7-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_IV]], align 8
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK7: omp.inner.for.cond:
-// CHECK7-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP48:![0-9]+]]
-// CHECK7-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP48]]
+// CHECK7-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP49:![0-9]+]]
+// CHECK7-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP49]]
// CHECK7-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]]
// CHECK7-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK7: omp.inner.for.body:
-// CHECK7-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP48]]
+// CHECK7-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP49]]
// CHECK7-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400
// CHECK7-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
-// CHECK7-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP48]]
-// CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP48]]
+// CHECK7-NEXT: store i64 [[SUB]], ptr [[IT]], align 8, !llvm.access.group [[ACC_GRP49]]
+// CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP49]]
// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP13]] to double
// CHECK7-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
-// CHECK7-NEXT: store double [[ADD]], ptr [[A]], align 4, !nontemporal [[META49:![0-9]+]], !llvm.access.group [[ACC_GRP48]]
+// CHECK7-NEXT: store double [[ADD]], ptr [[A]], align 4, !nontemporal [[META50:![0-9]+]], !llvm.access.group [[ACC_GRP49]]
// CHECK7-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
-// CHECK7-NEXT: [[TMP14:%.*]] = load double, ptr [[A4]], align 4, !nontemporal [[META49]], !llvm.access.group [[ACC_GRP48]]
+// CHECK7-NEXT: [[TMP14:%.*]] = load double, ptr [[A4]], align 4, !nontemporal [[META50]], !llvm.access.group [[ACC_GRP49]]
// CHECK7-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
-// CHECK7-NEXT: store double [[INC]], ptr [[A4]], align 4, !nontemporal [[META49]], !llvm.access.group [[ACC_GRP48]]
+// CHECK7-NEXT: store double [[INC]], ptr [[A4]], align 4, !nontemporal [[META50]], !llvm.access.group [[ACC_GRP49]]
// CHECK7-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
// CHECK7-NEXT: [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]]
// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP15]]
// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
-// CHECK7-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP48]]
+// CHECK7-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP49]]
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK7: omp.body.continue:
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK7: omp.inner.for.inc:
-// CHECK7-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP48]]
+// CHECK7-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP49]]
// CHECK7-NEXT: [[ADD7:%.*]] = add i64 [[TMP16]], 1
-// CHECK7-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP48]]
-// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP50:![0-9]+]]
+// CHECK7-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP49]]
+// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP51:![0-9]+]]
// CHECK7: omp.inner.for.end:
// CHECK7-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK7: omp_if.else:
@@ -7231,7 +7231,7 @@ int bar(int n){
// CHECK7-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
// CHECK7-NEXT: [[ADD28:%.*]] = add i64 [[TMP28]], 1
// CHECK7-NEXT: store i64 [[ADD28]], ptr [[DOTOMP_IV]], align 8
-// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP52:![0-9]+]]
+// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP53:![0-9]+]]
// CHECK7: omp.inner.for.end29:
// CHECK7-NEXT: br label [[OMP_IF_END]]
// CHECK7: omp_if.end:
@@ -7266,7 +7266,7 @@ int bar(int n){
// CHECK7-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
// CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
// CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META33]], !align [[META34]]
+// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META34]], !align [[META35]]
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK7-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
@@ -7297,7 +7297,7 @@ int bar(int n){
// CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
// CHECK7-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
// CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
-// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META33]], !align [[META34]]
+// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META34]], !align [[META35]]
// CHECK7-NEXT: ret void
//
//
@@ -7314,7 +7314,7 @@ int bar(int n){
// CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
// CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
// CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META33]], !align [[META34]]
+// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META34]], !align [[META35]]
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK7-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
@@ -7345,7 +7345,7 @@ int bar(int n){
// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
// CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
-// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META33]], !align [[META34]]
+// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META34]], !align [[META35]]
// CHECK7-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
// CHECK7-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8
// CHECK7-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
@@ -7368,35 +7368,35 @@ int bar(int n){
// CHECK7-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK7: omp.inner.for.cond:
-// CHECK7-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP54:![0-9]+]]
-// CHECK7-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP54]]
+// CHECK7-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP55:![0-9]+]]
+// CHECK7-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP55]]
// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK7: omp.inner.for.body:
-// CHECK7-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP54]]
+// CHECK7-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP55]]
// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
// CHECK7-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
-// CHECK7-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP54]]
-// CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP54]]
+// CHECK7-NEXT: store i64 [[ADD]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP55]]
+// CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP55]]
// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK7-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP54]]
-// CHECK7-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP54]]
+// CHECK7-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP55]]
+// CHECK7-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP55]]
// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32
// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
// CHECK7-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK7-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP54]]
+// CHECK7-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP55]]
// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2
-// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP54]]
+// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP55]]
// CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK7-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP54]]
+// CHECK7-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP55]]
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK7: omp.body.continue:
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK7: omp.inner.for.inc:
-// CHECK7-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP54]]
+// CHECK7-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP55]]
// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1
-// CHECK7-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP54]]
-// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP55:![0-9]+]]
+// CHECK7-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP55]]
+// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP56:![0-9]+]]
// CHECK7: omp.inner.for.end:
// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK7: omp.loop.exit:
@@ -9422,8 +9422,9 @@ int bar(int n){
// CHECK17-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK17-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP1]], align 8
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined)
// CHECK17-NEXT: ret void
@@ -9509,28 +9510,32 @@ int bar(int n){
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK17-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 8
-// CHECK17-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
-// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
-// CHECK17-NEXT: store i32 [[TMP4]], ptr [[LIN]], align 4
-// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
+// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 8
+// CHECK17-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
+// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK17-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 8
-// CHECK17-NEXT: store i32 [[TMP6]], ptr [[A]], align 4
-// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: store i32 [[TMP6]], ptr [[LIN]], align 4
+// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK17-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8
+// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 8
+// CHECK17-NEXT: store i32 [[TMP9]], ptr [[A]], align 4
+// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP10]], align 8
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK17-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK17-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
-// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[LIN]], align 4
-// CHECK17-NEXT: store i32 [[TMP9]], ptr [[LIN_CASTED]], align 4
-// CHECK17-NEXT: [[TMP10:%.*]] = load i64, ptr [[LIN_CASTED]], align 8
-// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[A]], align 4
-// CHECK17-NEXT: store i32 [[TMP11]], ptr [[A_CASTED]], align 4
-// CHECK17-NEXT: [[TMP12:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]])
+// CHECK17-NEXT: [[TMP11:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK17-NEXT: store i16 [[TMP11]], ptr [[AA_CASTED]], align 2
+// CHECK17-NEXT: [[TMP12:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[LIN]], align 4
+// CHECK17-NEXT: store i32 [[TMP13]], ptr [[LIN_CASTED]], align 4
+// CHECK17-NEXT: [[TMP14:%.*]] = load i64, ptr [[LIN_CASTED]], align 8
+// CHECK17-NEXT: [[TMP15:%.*]] = load i32, ptr [[A]], align 4
+// CHECK17-NEXT: store i32 [[TMP15]], ptr [[A_CASTED]], align 4
+// CHECK17-NEXT: [[TMP16:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i64 [[TMP12]], i64 [[TMP14]], i64 [[TMP16]])
// CHECK17-NEXT: ret void
//
//
@@ -9667,22 +9672,25 @@ int bar(int n){
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK17-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK17-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
-// CHECK17-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK17-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK17-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK17-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 8
+// CHECK17-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK17-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 8
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
-// CHECK17-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4
-// CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK17-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK17-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
-// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i64 [[TMP6]], i64 [[TMP8]])
+// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
+// CHECK17-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
+// CHECK17-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK17-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK17-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
+// CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i64 [[TMP9]], i64 [[TMP11]])
// CHECK17-NEXT: ret void
//
//
@@ -9777,38 +9785,49 @@ int bar(int n){
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK17-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK17-NEXT: [[B:%.*]] = load ptr, ptr [[TMP3]], align 8
-// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8
-// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK17-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP6]], align 8
-// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK17-NEXT: [[C:%.*]] = load ptr, ptr [[TMP7]], align 8
-// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
-// CHECK17-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8
-// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 6
-// CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
-// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 7
-// CHECK17-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP12]], align 8
-// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 8
-// CHECK17-NEXT: [[D:%.*]] = load ptr, ptr [[TMP13]], align 8
-// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 9
-// CHECK17-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 8
-// CHECK17-NEXT: store i32 [[TMP15]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 10
-// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK17-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK17-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK17-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 8
+// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK17-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
+// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP7]], align 8
+// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8
+// CHECK17-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP10]], align 8
+// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK17-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8
+// CHECK17-NEXT: [[C:%.*]] = load ptr, ptr [[TMP12]], align 8
+// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK17-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8
+// CHECK17-NEXT: [[TMP15:%.*]] = load i64, ptr [[TMP14]], align 8
+// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 6
+// CHECK17-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8
+// CHECK17-NEXT: [[TMP18:%.*]] = load i64, ptr [[TMP17]], align 8
+// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 7
+// CHECK17-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8
+// CHECK17-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP20]], align 8
+// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 8
+// CHECK17-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 8
+// CHECK17-NEXT: [[D:%.*]] = load ptr, ptr [[TMP22]], align 8
+// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 9
+// CHECK17-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 8
+// CHECK17-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 8
+// CHECK17-NEXT: store i32 [[TMP25]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 10
+// CHECK17-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP26]], align 8
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[A]], align 4
-// CHECK17-NEXT: store i32 [[TMP16]], ptr [[A_CASTED]], align 4
-// CHECK17-NEXT: [[TMP17:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK17-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK17-NEXT: store i32 [[TMP18]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
-// CHECK17-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
-// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i64 [[TMP17]], ptr [[B]], i64 [[TMP5]], ptr [[BN]], ptr [[C]], i64 [[TMP9]], i64 [[TMP11]], ptr [[CN]], ptr [[D]], i64 [[TMP19]])
+// CHECK17-NEXT: [[TMP27:%.*]] = load i32, ptr [[A]], align 4
+// CHECK17-NEXT: store i32 [[TMP27]], ptr [[A_CASTED]], align 4
+// CHECK17-NEXT: [[TMP28:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK17-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK17-NEXT: store i32 [[TMP29]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
+// CHECK17-NEXT: [[TMP30:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
+// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i64 [[TMP28]], ptr [[B]], i64 [[TMP8]], ptr [[BN]], ptr [[C]], i64 [[TMP15]], i64 [[TMP18]], ptr [[CN]], ptr [[D]], i64 [[TMP30]])
// CHECK17-NEXT: ret void
//
//
@@ -9975,30 +9994,35 @@ int bar(int n){
// CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK17-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK17-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
-// CHECK17-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK17-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 8
-// CHECK17-NEXT: store i8 [[TMP6]], ptr [[AAA]], align 1
-// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK17-NEXT: [[B:%.*]] = load ptr, ptr [[TMP7]], align 8
-// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK17-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK17-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK17-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 8
+// CHECK17-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK17-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8
+// CHECK17-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 8
+// CHECK17-NEXT: store i8 [[TMP9]], ptr [[AAA]], align 1
+// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK17-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8
+// CHECK17-NEXT: [[B:%.*]] = load ptr, ptr [[TMP11]], align 8
+// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK17-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP12]], align 8
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
-// CHECK17-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
-// CHECK17-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK17-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK17-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
-// CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK17-NEXT: [[TMP12:%.*]] = load i8, ptr [[AAA]], align 1
-// CHECK17-NEXT: store i8 [[TMP12]], ptr [[AAA_CASTED]], align 1
-// CHECK17-NEXT: [[TMP13:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
-// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], ptr [[B]])
+// CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[A]], align 4
+// CHECK17-NEXT: store i32 [[TMP13]], ptr [[A_CASTED]], align 4
+// CHECK17-NEXT: [[TMP14:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK17-NEXT: [[TMP15:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK17-NEXT: store i16 [[TMP15]], ptr [[AA_CASTED]], align 2
+// CHECK17-NEXT: [[TMP16:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK17-NEXT: [[TMP17:%.*]] = load i8, ptr [[AAA]], align 1
+// CHECK17-NEXT: store i8 [[TMP17]], ptr [[AAA_CASTED]], align 1
+// CHECK17-NEXT: [[TMP18:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
+// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i64 [[TMP14]], i64 [[TMP16]], i64 [[TMP18]], ptr [[B]])
// CHECK17-NEXT: ret void
//
//
@@ -10032,24 +10056,30 @@ int bar(int n){
// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK17-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK17-NEXT: store i32 [[TMP3]], ptr [[B]], align 4
-// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8
-// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK17-NEXT: [[TMP7:%.*]] = load i64, ptr [[TMP6]], align 8
-// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK17-NEXT: [[C:%.*]] = load ptr, ptr [[TMP8]], align 8
-// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
-// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK17-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
+// CHECK17-NEXT: store i32 [[TMP5]], ptr [[B]], align 4
+// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK17-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
+// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP7]], align 8
+// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8
+// CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
+// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8
+// CHECK17-NEXT: [[C:%.*]] = load ptr, ptr [[TMP13]], align 8
+// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK17-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP14]], align 8
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4
-// CHECK17-NEXT: store i32 [[TMP9]], ptr [[B_CASTED]], align 4
-// CHECK17-NEXT: [[TMP10:%.*]] = load i64, ptr [[B_CASTED]], align 8
-// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[THIS]], i64 [[TMP10]], i64 [[TMP5]], i64 [[TMP7]], ptr [[C]])
+// CHECK17-NEXT: [[TMP15:%.*]] = load i32, ptr [[B]], align 4
+// CHECK17-NEXT: store i32 [[TMP15]], ptr [[B_CASTED]], align 4
+// CHECK17-NEXT: [[TMP16:%.*]] = load i64, ptr [[B_CASTED]], align 8
+// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[THIS]], i64 [[TMP16]], i64 [[TMP8]], i64 [[TMP11]], ptr [[C]])
// CHECK17-NEXT: ret void
//
//
@@ -10159,24 +10189,28 @@ int bar(int n){
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK17-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK17-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
-// CHECK17-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK17-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 8
-// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK17-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK17-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK17-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 8
+// CHECK17-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK17-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8
+// CHECK17-NEXT: [[B:%.*]] = load ptr, ptr [[TMP8]], align 8
+// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP9]], align 8
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// CHECK17-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4
-// CHECK17-NEXT: [[TMP7:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK17-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK17-NEXT: store i16 [[TMP8]], ptr [[AA_CASTED]], align 2
-// CHECK17-NEXT: [[TMP9:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i64 [[TMP7]], i64 [[TMP9]], ptr [[B]])
+// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
+// CHECK17-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
+// CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK17-NEXT: [[TMP12:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK17-NEXT: store i16 [[TMP12]], ptr [[AA_CASTED]], align 2
+// CHECK17-NEXT: [[TMP13:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i64 [[TMP11]], i64 [[TMP13]], ptr [[B]])
// CHECK17-NEXT: ret void
//
//
@@ -10273,8 +10307,9 @@ int bar(int n){
// CHECK19-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK19-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP1]], align 4
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined)
// CHECK19-NEXT: ret void
@@ -10360,28 +10395,32 @@ int bar(int n){
// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK19-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 4
-// CHECK19-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
-// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-// CHECK19-NEXT: store i32 [[TMP4]], ptr [[LIN]], align 4
-// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
+// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 4
+// CHECK19-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
+// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK19-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
-// CHECK19-NEXT: store i32 [[TMP6]], ptr [[A]], align 4
-// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: store i32 [[TMP6]], ptr [[LIN]], align 4
+// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK19-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4
+// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
+// CHECK19-NEXT: store i32 [[TMP9]], ptr [[A]], align 4
+// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK19-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP10]], align 4
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK19-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK19-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
-// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[LIN]], align 4
-// CHECK19-NEXT: store i32 [[TMP9]], ptr [[LIN_CASTED]], align 4
-// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[LIN_CASTED]], align 4
-// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[A]], align 4
-// CHECK19-NEXT: store i32 [[TMP11]], ptr [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i32 [[TMP8]], i32 [[TMP10]], i32 [[TMP12]])
+// CHECK19-NEXT: [[TMP11:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK19-NEXT: store i16 [[TMP11]], ptr [[AA_CASTED]], align 2
+// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[LIN]], align 4
+// CHECK19-NEXT: store i32 [[TMP13]], ptr [[LIN_CASTED]], align 4
+// CHECK19-NEXT: [[TMP14:%.*]] = load i32, ptr [[LIN_CASTED]], align 4
+// CHECK19-NEXT: [[TMP15:%.*]] = load i32, ptr [[A]], align 4
+// CHECK19-NEXT: store i32 [[TMP15]], ptr [[A_CASTED]], align 4
+// CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i32 [[TMP12]], i32 [[TMP14]], i32 [[TMP16]])
// CHECK19-NEXT: ret void
//
//
@@ -10518,22 +10557,25 @@ int bar(int n){
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK19-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK19-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
-// CHECK19-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK19-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK19-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK19-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 4
+// CHECK19-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 4
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
-// CHECK19-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK19-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
-// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i32 [[TMP6]], i32 [[TMP8]])
+// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
+// CHECK19-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
+// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK19-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK19-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
+// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i32 [[TMP9]], i32 [[TMP11]])
// CHECK19-NEXT: ret void
//
//
@@ -10628,38 +10670,49 @@ int bar(int n){
// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK19-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK19-NEXT: [[B:%.*]] = load ptr, ptr [[TMP3]], align 4
-// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK19-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP6]], align 4
-// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK19-NEXT: [[C:%.*]] = load ptr, ptr [[TMP7]], align 4
-// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
-// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
-// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 6
-// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
-// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 7
-// CHECK19-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP12]], align 4
-// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 8
-// CHECK19-NEXT: [[D:%.*]] = load ptr, ptr [[TMP13]], align 4
-// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 9
+// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK19-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK19-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK19-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 4
+// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
+// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
+// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK19-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4
+// CHECK19-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP10]], align 4
+// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK19-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 4
+// CHECK19-NEXT: [[C:%.*]] = load ptr, ptr [[TMP12]], align 4
+// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK19-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 4
// CHECK19-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4
-// CHECK19-NEXT: store i32 [[TMP15]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 10
-// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 6
+// CHECK19-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 4
+// CHECK19-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4
+// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 7
+// CHECK19-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 4
+// CHECK19-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP20]], align 4
+// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 8
+// CHECK19-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 4
+// CHECK19-NEXT: [[D:%.*]] = load ptr, ptr [[TMP22]], align 4
+// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 9
+// CHECK19-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 4
+// CHECK19-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 4
+// CHECK19-NEXT: store i32 [[TMP25]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 10
+// CHECK19-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP26]], align 4
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[A]], align 4
-// CHECK19-NEXT: store i32 [[TMP16]], ptr [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP17:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK19-NEXT: store i32 [[TMP18]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
-// CHECK19-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
-// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i32 [[TMP17]], ptr [[B]], i32 [[TMP5]], ptr [[BN]], ptr [[C]], i32 [[TMP9]], i32 [[TMP11]], ptr [[CN]], ptr [[D]], i32 [[TMP19]])
+// CHECK19-NEXT: [[TMP27:%.*]] = load i32, ptr [[A]], align 4
+// CHECK19-NEXT: store i32 [[TMP27]], ptr [[A_CASTED]], align 4
+// CHECK19-NEXT: [[TMP28:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK19-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK19-NEXT: store i32 [[TMP29]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
+// CHECK19-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
+// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i32 [[TMP28]], ptr [[B]], i32 [[TMP8]], ptr [[BN]], ptr [[C]], i32 [[TMP15]], i32 [[TMP18]], ptr [[CN]], ptr [[D]], i32 [[TMP30]])
// CHECK19-NEXT: ret void
//
//
@@ -10826,30 +10879,35 @@ int bar(int n){
// CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK19-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK19-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
-// CHECK19-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK19-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 4
-// CHECK19-NEXT: store i8 [[TMP6]], ptr [[AAA]], align 1
-// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK19-NEXT: [[B:%.*]] = load ptr, ptr [[TMP7]], align 4
-// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK19-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK19-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK19-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 4
+// CHECK19-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK19-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4
+// CHECK19-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 4
+// CHECK19-NEXT: store i8 [[TMP9]], ptr [[AAA]], align 1
+// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK19-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 4
+// CHECK19-NEXT: [[B:%.*]] = load ptr, ptr [[TMP11]], align 4
+// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK19-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP12]], align 4
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
-// CHECK19-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK19-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
-// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK19-NEXT: [[TMP12:%.*]] = load i8, ptr [[AAA]], align 1
-// CHECK19-NEXT: store i8 [[TMP12]], ptr [[AAA_CASTED]], align 1
-// CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
-// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i32 [[TMP9]], i32 [[TMP11]], i32 [[TMP13]], ptr [[B]])
+// CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[A]], align 4
+// CHECK19-NEXT: store i32 [[TMP13]], ptr [[A_CASTED]], align 4
+// CHECK19-NEXT: [[TMP14:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK19-NEXT: [[TMP15:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK19-NEXT: store i16 [[TMP15]], ptr [[AA_CASTED]], align 2
+// CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK19-NEXT: [[TMP17:%.*]] = load i8, ptr [[AAA]], align 1
+// CHECK19-NEXT: store i8 [[TMP17]], ptr [[AAA_CASTED]], align 1
+// CHECK19-NEXT: [[TMP18:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
+// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i32 [[TMP14]], i32 [[TMP16]], i32 [[TMP18]], ptr [[B]])
// CHECK19-NEXT: ret void
//
//
@@ -10883,24 +10941,30 @@ int bar(int n){
// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK19-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 4
-// CHECK19-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK19-NEXT: store i32 [[TMP3]], ptr [[B]], align 4
-// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
+// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK19-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
-// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK19-NEXT: [[C:%.*]] = load ptr, ptr [[TMP8]], align 4
-// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
-// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: store i32 [[TMP5]], ptr [[B]], align 4
+// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
+// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
+// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK19-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4
+// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
+// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK19-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 4
+// CHECK19-NEXT: [[C:%.*]] = load ptr, ptr [[TMP13]], align 4
+// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK19-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP14]], align 4
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4
-// CHECK19-NEXT: store i32 [[TMP9]], ptr [[B_CASTED]], align 4
-// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[B_CASTED]], align 4
-// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[THIS]], i32 [[TMP10]], i32 [[TMP5]], i32 [[TMP7]], ptr [[C]])
+// CHECK19-NEXT: [[TMP15:%.*]] = load i32, ptr [[B]], align 4
+// CHECK19-NEXT: store i32 [[TMP15]], ptr [[B_CASTED]], align 4
+// CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[B_CASTED]], align 4
+// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[THIS]], i32 [[TMP16]], i32 [[TMP8]], i32 [[TMP11]], ptr [[C]])
// CHECK19-NEXT: ret void
//
//
@@ -11010,24 +11074,28 @@ int bar(int n){
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK19-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK19-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
-// CHECK19-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK19-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 4
-// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK19-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK19-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK19-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 4
+// CHECK19-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK19-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4
+// CHECK19-NEXT: [[B:%.*]] = load ptr, ptr [[TMP8]], align 4
+// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK19-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP9]], align 4
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// CHECK19-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK19-NEXT: store i16 [[TMP8]], ptr [[AA_CASTED]], align 2
-// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i32 [[TMP7]], i32 [[TMP9]], ptr [[B]])
+// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
+// CHECK19-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
+// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK19-NEXT: [[TMP12:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK19-NEXT: store i16 [[TMP12]], ptr [[AA_CASTED]], align 2
+// CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i32 [[TMP11]], i32 [[TMP13]], ptr [[B]])
// CHECK19-NEXT: ret void
//
//
@@ -11124,8 +11192,9 @@ int bar(int n){
// CHECK21-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK21-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP1]], align 8
// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined)
// CHECK21-NEXT: ret void
@@ -11211,28 +11280,32 @@ int bar(int n){
// CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK21-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 8
-// CHECK21-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
-// CHECK21-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
-// CHECK21-NEXT: store i32 [[TMP4]], ptr [[LIN]], align 4
-// CHECK21-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
+// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK21-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 8
+// CHECK21-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
+// CHECK21-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK21-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
// CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 8
-// CHECK21-NEXT: store i32 [[TMP6]], ptr [[A]], align 4
-// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: store i32 [[TMP6]], ptr [[LIN]], align 4
+// CHECK21-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK21-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8
+// CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 8
+// CHECK21-NEXT: store i32 [[TMP9]], ptr [[A]], align 4
+// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK21-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP10]], align 8
// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK21-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK21-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
-// CHECK21-NEXT: [[TMP8:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[LIN]], align 4
-// CHECK21-NEXT: store i32 [[TMP9]], ptr [[LIN_CASTED]], align 4
-// CHECK21-NEXT: [[TMP10:%.*]] = load i64, ptr [[LIN_CASTED]], align 8
-// CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[A]], align 4
-// CHECK21-NEXT: store i32 [[TMP11]], ptr [[A_CASTED]], align 4
-// CHECK21-NEXT: [[TMP12:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]])
+// CHECK21-NEXT: [[TMP11:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK21-NEXT: store i16 [[TMP11]], ptr [[AA_CASTED]], align 2
+// CHECK21-NEXT: [[TMP12:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[LIN]], align 4
+// CHECK21-NEXT: store i32 [[TMP13]], ptr [[LIN_CASTED]], align 4
+// CHECK21-NEXT: [[TMP14:%.*]] = load i64, ptr [[LIN_CASTED]], align 8
+// CHECK21-NEXT: [[TMP15:%.*]] = load i32, ptr [[A]], align 4
+// CHECK21-NEXT: store i32 [[TMP15]], ptr [[A_CASTED]], align 4
+// CHECK21-NEXT: [[TMP16:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i64 [[TMP12]], i64 [[TMP14]], i64 [[TMP16]])
// CHECK21-NEXT: ret void
//
//
@@ -11369,22 +11442,25 @@ int bar(int n){
// CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK21-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK21-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK21-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
-// CHECK21-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK21-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK21-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK21-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK21-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 8
+// CHECK21-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK21-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 8
// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
-// CHECK21-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4
-// CHECK21-NEXT: [[TMP6:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK21-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK21-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
-// CHECK21-NEXT: [[TMP8:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i64 [[TMP6]], i64 [[TMP8]])
+// CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
+// CHECK21-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
+// CHECK21-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK21-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK21-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
+// CHECK21-NEXT: [[TMP11:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i64 [[TMP9]], i64 [[TMP11]])
// CHECK21-NEXT: ret void
//
//
@@ -11479,38 +11555,49 @@ int bar(int n){
// CHECK21-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK21-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK21-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK21-NEXT: [[B:%.*]] = load ptr, ptr [[TMP3]], align 8
-// CHECK21-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK21-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8
-// CHECK21-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK21-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP6]], align 8
-// CHECK21-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK21-NEXT: [[C:%.*]] = load ptr, ptr [[TMP7]], align 8
-// CHECK21-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
-// CHECK21-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8
-// CHECK21-NEXT: [[TMP10:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 6
-// CHECK21-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
-// CHECK21-NEXT: [[TMP12:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 7
-// CHECK21-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP12]], align 8
-// CHECK21-NEXT: [[TMP13:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 8
-// CHECK21-NEXT: [[D:%.*]] = load ptr, ptr [[TMP13]], align 8
-// CHECK21-NEXT: [[TMP14:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 9
-// CHECK21-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 8
-// CHECK21-NEXT: store i32 [[TMP15]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 10
-// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK21-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK21-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK21-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK21-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 8
+// CHECK21-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK21-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
+// CHECK21-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP7]], align 8
+// CHECK21-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK21-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8
+// CHECK21-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP10]], align 8
+// CHECK21-NEXT: [[TMP11:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK21-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8
+// CHECK21-NEXT: [[C:%.*]] = load ptr, ptr [[TMP12]], align 8
+// CHECK21-NEXT: [[TMP13:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK21-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8
+// CHECK21-NEXT: [[TMP15:%.*]] = load i64, ptr [[TMP14]], align 8
+// CHECK21-NEXT: [[TMP16:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 6
+// CHECK21-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8
+// CHECK21-NEXT: [[TMP18:%.*]] = load i64, ptr [[TMP17]], align 8
+// CHECK21-NEXT: [[TMP19:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 7
+// CHECK21-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8
+// CHECK21-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP20]], align 8
+// CHECK21-NEXT: [[TMP21:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 8
+// CHECK21-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 8
+// CHECK21-NEXT: [[D:%.*]] = load ptr, ptr [[TMP22]], align 8
+// CHECK21-NEXT: [[TMP23:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 9
+// CHECK21-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 8
+// CHECK21-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 8
+// CHECK21-NEXT: store i32 [[TMP25]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 10
+// CHECK21-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP26]], align 8
// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK21-NEXT: [[TMP16:%.*]] = load i32, ptr [[A]], align 4
-// CHECK21-NEXT: store i32 [[TMP16]], ptr [[A_CASTED]], align 4
-// CHECK21-NEXT: [[TMP17:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK21-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK21-NEXT: store i32 [[TMP18]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
-// CHECK21-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
-// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i64 [[TMP17]], ptr [[B]], i64 [[TMP5]], ptr [[BN]], ptr [[C]], i64 [[TMP9]], i64 [[TMP11]], ptr [[CN]], ptr [[D]], i64 [[TMP19]])
+// CHECK21-NEXT: [[TMP27:%.*]] = load i32, ptr [[A]], align 4
+// CHECK21-NEXT: store i32 [[TMP27]], ptr [[A_CASTED]], align 4
+// CHECK21-NEXT: [[TMP28:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK21-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK21-NEXT: store i32 [[TMP29]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
+// CHECK21-NEXT: [[TMP30:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
+// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i64 [[TMP28]], ptr [[B]], i64 [[TMP8]], ptr [[BN]], ptr [[C]], i64 [[TMP15]], i64 [[TMP18]], ptr [[CN]], ptr [[D]], i64 [[TMP30]])
// CHECK21-NEXT: ret void
//
//
@@ -11677,30 +11764,35 @@ int bar(int n){
// CHECK21-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK21-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK21-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK21-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
-// CHECK21-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK21-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK21-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 8
-// CHECK21-NEXT: store i8 [[TMP6]], ptr [[AAA]], align 1
-// CHECK21-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK21-NEXT: [[B:%.*]] = load ptr, ptr [[TMP7]], align 8
-// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK21-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK21-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK21-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK21-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 8
+// CHECK21-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK21-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK21-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8
+// CHECK21-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 8
+// CHECK21-NEXT: store i8 [[TMP9]], ptr [[AAA]], align 1
+// CHECK21-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK21-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8
+// CHECK21-NEXT: [[B:%.*]] = load ptr, ptr [[TMP11]], align 8
+// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK21-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP12]], align 8
// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
-// CHECK21-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
-// CHECK21-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK21-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK21-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
-// CHECK21-NEXT: [[TMP11:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK21-NEXT: [[TMP12:%.*]] = load i8, ptr [[AAA]], align 1
-// CHECK21-NEXT: store i8 [[TMP12]], ptr [[AAA_CASTED]], align 1
-// CHECK21-NEXT: [[TMP13:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
-// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], ptr [[B]])
+// CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[A]], align 4
+// CHECK21-NEXT: store i32 [[TMP13]], ptr [[A_CASTED]], align 4
+// CHECK21-NEXT: [[TMP14:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK21-NEXT: [[TMP15:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK21-NEXT: store i16 [[TMP15]], ptr [[AA_CASTED]], align 2
+// CHECK21-NEXT: [[TMP16:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK21-NEXT: [[TMP17:%.*]] = load i8, ptr [[AAA]], align 1
+// CHECK21-NEXT: store i8 [[TMP17]], ptr [[AAA_CASTED]], align 1
+// CHECK21-NEXT: [[TMP18:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
+// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i64 [[TMP14]], i64 [[TMP16]], i64 [[TMP18]], ptr [[B]])
// CHECK21-NEXT: ret void
//
//
@@ -11739,44 +11831,51 @@ int bar(int n){
// CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK21-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK21-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK21-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 8
-// CHECK21-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
-// CHECK21-NEXT: store i32 [[TMP4]], ptr [[B]], align 4
-// CHECK21-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
-// CHECK21-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP5]], align 8
-// CHECK21-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
-// CHECK21-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP7]], align 8
-// CHECK21-NEXT: [[TMP9:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 4
-// CHECK21-NEXT: [[C:%.*]] = load ptr, ptr [[TMP9]], align 8
-// CHECK21-NEXT: [[TMP10:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 5
-// CHECK21-NEXT: [[TMP11:%.*]] = load i8, ptr [[TMP10]], align 8
-// CHECK21-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP11]], 0
+// CHECK21-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK21-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK21-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK21-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK21-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 8
+// CHECK21-NEXT: store i32 [[TMP6]], ptr [[B]], align 4
+// CHECK21-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK21-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8
+// CHECK21-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8
+// CHECK21-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK21-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8
+// CHECK21-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8
+// CHECK21-NEXT: [[TMP13:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 4
+// CHECK21-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8
+// CHECK21-NEXT: [[C:%.*]] = load ptr, ptr [[TMP14]], align 8
+// CHECK21-NEXT: [[TMP15:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 5
+// CHECK21-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8
+// CHECK21-NEXT: [[TMP17:%.*]] = load i8, ptr [[TMP16]], align 8
+// CHECK21-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP17]], 0
// CHECK21-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i8
// CHECK21-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 1
-// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 6
-// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 6
+// CHECK21-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP18]], align 8
// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK21-NEXT: [[TMP12:%.*]] = load i32, ptr [[B]], align 4
-// CHECK21-NEXT: store i32 [[TMP12]], ptr [[B_CASTED]], align 4
-// CHECK21-NEXT: [[TMP13:%.*]] = load i64, ptr [[B_CASTED]], align 8
-// CHECK21-NEXT: [[TMP14:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
-// CHECK21-NEXT: [[LOADEDV2:%.*]] = icmp ne i8 [[TMP14]], 0
+// CHECK21-NEXT: [[TMP19:%.*]] = load i32, ptr [[B]], align 4
+// CHECK21-NEXT: store i32 [[TMP19]], ptr [[B_CASTED]], align 4
+// CHECK21-NEXT: [[TMP20:%.*]] = load i64, ptr [[B_CASTED]], align 8
+// CHECK21-NEXT: [[TMP21:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
+// CHECK21-NEXT: [[LOADEDV2:%.*]] = icmp ne i8 [[TMP21]], 0
// CHECK21-NEXT: [[STOREDV3:%.*]] = zext i1 [[LOADEDV2]] to i8
// CHECK21-NEXT: store i8 [[STOREDV3]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1
-// CHECK21-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
-// CHECK21-NEXT: [[TMP16:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
-// CHECK21-NEXT: [[LOADEDV4:%.*]] = icmp ne i8 [[TMP16]], 0
+// CHECK21-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
+// CHECK21-NEXT: [[TMP23:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
+// CHECK21-NEXT: [[LOADEDV4:%.*]] = icmp ne i8 [[TMP23]], 0
// CHECK21-NEXT: br i1 [[LOADEDV4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK21: omp_if.then:
-// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined, ptr [[THIS]], i64 [[TMP13]], i64 [[TMP6]], i64 [[TMP8]], ptr [[C]], i64 [[TMP15]])
+// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined, ptr [[THIS]], i64 [[TMP20]], i64 [[TMP9]], i64 [[TMP12]], ptr [[C]], i64 [[TMP22]])
// CHECK21-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK21: omp_if.else:
// CHECK21-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]])
// CHECK21-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4
// CHECK21-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4
-// CHECK21-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[THIS]], i64 [[TMP13]], i64 [[TMP6]], i64 [[TMP8]], ptr [[C]], i64 [[TMP15]]) #[[ATTR1:[0-9]+]]
+// CHECK21-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[THIS]], i64 [[TMP20]], i64 [[TMP9]], i64 [[TMP12]], ptr [[C]], i64 [[TMP22]]) #[[ATTR1:[0-9]+]]
// CHECK21-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]])
// CHECK21-NEXT: br label [[OMP_IF_END]]
// CHECK21: omp_if.end:
@@ -11951,24 +12050,28 @@ int bar(int n){
// CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK21-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK21-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK21-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
-// CHECK21-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK21-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK21-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 8
-// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK21-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK21-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK21-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK21-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 8
+// CHECK21-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK21-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK21-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8
+// CHECK21-NEXT: [[B:%.*]] = load ptr, ptr [[TMP8]], align 8
+// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK21-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP9]], align 8
// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// CHECK21-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4
-// CHECK21-NEXT: [[TMP7:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK21-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK21-NEXT: store i16 [[TMP8]], ptr [[AA_CASTED]], align 2
-// CHECK21-NEXT: [[TMP9:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i64 [[TMP7]], i64 [[TMP9]], ptr [[B]])
+// CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
+// CHECK21-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
+// CHECK21-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK21-NEXT: [[TMP12:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK21-NEXT: store i16 [[TMP12]], ptr [[AA_CASTED]], align 2
+// CHECK21-NEXT: [[TMP13:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i64 [[TMP11]], i64 [[TMP13]], ptr [[B]])
// CHECK21-NEXT: ret void
//
//
@@ -12065,8 +12168,9 @@ int bar(int n){
// CHECK23-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK23-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP1]], align 4
// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined)
// CHECK23-NEXT: ret void
@@ -12152,28 +12256,32 @@ int bar(int n){
// CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK23-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 4
-// CHECK23-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
-// CHECK23-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-// CHECK23-NEXT: store i32 [[TMP4]], ptr [[LIN]], align 4
-// CHECK23-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
+// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK23-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 4
+// CHECK23-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
+// CHECK23-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK23-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
-// CHECK23-NEXT: store i32 [[TMP6]], ptr [[A]], align 4
-// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: store i32 [[TMP6]], ptr [[LIN]], align 4
+// CHECK23-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK23-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4
+// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
+// CHECK23-NEXT: store i32 [[TMP9]], ptr [[A]], align 4
+// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK23-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP10]], align 4
// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK23-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK23-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
-// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[LIN]], align 4
-// CHECK23-NEXT: store i32 [[TMP9]], ptr [[LIN_CASTED]], align 4
-// CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[LIN_CASTED]], align 4
-// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[A]], align 4
-// CHECK23-NEXT: store i32 [[TMP11]], ptr [[A_CASTED]], align 4
-// CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i32 [[TMP8]], i32 [[TMP10]], i32 [[TMP12]])
+// CHECK23-NEXT: [[TMP11:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK23-NEXT: store i16 [[TMP11]], ptr [[AA_CASTED]], align 2
+// CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[LIN]], align 4
+// CHECK23-NEXT: store i32 [[TMP13]], ptr [[LIN_CASTED]], align 4
+// CHECK23-NEXT: [[TMP14:%.*]] = load i32, ptr [[LIN_CASTED]], align 4
+// CHECK23-NEXT: [[TMP15:%.*]] = load i32, ptr [[A]], align 4
+// CHECK23-NEXT: store i32 [[TMP15]], ptr [[A_CASTED]], align 4
+// CHECK23-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.omp_outlined, i32 [[TMP12]], i32 [[TMP14]], i32 [[TMP16]])
// CHECK23-NEXT: ret void
//
//
@@ -12310,22 +12418,25 @@ int bar(int n){
// CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK23-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK23-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK23-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
-// CHECK23-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK23-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK23-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK23-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK23-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 4
+// CHECK23-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK23-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 4
// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
-// CHECK23-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4
-// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK23-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK23-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
-// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i32 [[TMP6]], i32 [[TMP8]])
+// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
+// CHECK23-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
+// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK23-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK23-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
+// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.omp_outlined, i32 [[TMP9]], i32 [[TMP11]])
// CHECK23-NEXT: ret void
//
//
@@ -12420,38 +12531,49 @@ int bar(int n){
// CHECK23-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK23-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK23-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK23-NEXT: [[B:%.*]] = load ptr, ptr [[TMP3]], align 4
-// CHECK23-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK23-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK23-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP6]], align 4
-// CHECK23-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK23-NEXT: [[C:%.*]] = load ptr, ptr [[TMP7]], align 4
-// CHECK23-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
-// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
-// CHECK23-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 6
-// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
-// CHECK23-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 7
-// CHECK23-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP12]], align 4
-// CHECK23-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 8
-// CHECK23-NEXT: [[D:%.*]] = load ptr, ptr [[TMP13]], align 4
-// CHECK23-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 9
+// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK23-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK23-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK23-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK23-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 4
+// CHECK23-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK23-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
+// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
+// CHECK23-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK23-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4
+// CHECK23-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP10]], align 4
+// CHECK23-NEXT: [[TMP11:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK23-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 4
+// CHECK23-NEXT: [[C:%.*]] = load ptr, ptr [[TMP12]], align 4
+// CHECK23-NEXT: [[TMP13:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK23-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 4
// CHECK23-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4
-// CHECK23-NEXT: store i32 [[TMP15]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 10
-// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[TMP16:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 6
+// CHECK23-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 4
+// CHECK23-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4
+// CHECK23-NEXT: [[TMP19:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 7
+// CHECK23-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 4
+// CHECK23-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP20]], align 4
+// CHECK23-NEXT: [[TMP21:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 8
+// CHECK23-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 4
+// CHECK23-NEXT: [[D:%.*]] = load ptr, ptr [[TMP22]], align 4
+// CHECK23-NEXT: [[TMP23:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 9
+// CHECK23-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 4
+// CHECK23-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 4
+// CHECK23-NEXT: store i32 [[TMP25]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 10
+// CHECK23-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP26]], align 4
// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK23-NEXT: [[TMP16:%.*]] = load i32, ptr [[A]], align 4
-// CHECK23-NEXT: store i32 [[TMP16]], ptr [[A_CASTED]], align 4
-// CHECK23-NEXT: [[TMP17:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK23-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK23-NEXT: store i32 [[TMP18]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
-// CHECK23-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
-// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i32 [[TMP17]], ptr [[B]], i32 [[TMP5]], ptr [[BN]], ptr [[C]], i32 [[TMP9]], i32 [[TMP11]], ptr [[CN]], ptr [[D]], i32 [[TMP19]])
+// CHECK23-NEXT: [[TMP27:%.*]] = load i32, ptr [[A]], align 4
+// CHECK23-NEXT: store i32 [[TMP27]], ptr [[A_CASTED]], align 4
+// CHECK23-NEXT: [[TMP28:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK23-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK23-NEXT: store i32 [[TMP29]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
+// CHECK23-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
+// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.omp_outlined, i32 [[TMP28]], ptr [[B]], i32 [[TMP8]], ptr [[BN]], ptr [[C]], i32 [[TMP15]], i32 [[TMP18]], ptr [[CN]], ptr [[D]], i32 [[TMP30]])
// CHECK23-NEXT: ret void
//
//
@@ -12618,30 +12740,35 @@ int bar(int n){
// CHECK23-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK23-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK23-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK23-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
-// CHECK23-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK23-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK23-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 4
-// CHECK23-NEXT: store i8 [[TMP6]], ptr [[AAA]], align 1
-// CHECK23-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK23-NEXT: [[B:%.*]] = load ptr, ptr [[TMP7]], align 4
-// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK23-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK23-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK23-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK23-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 4
+// CHECK23-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK23-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK23-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4
+// CHECK23-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 4
+// CHECK23-NEXT: store i8 [[TMP9]], ptr [[AAA]], align 1
+// CHECK23-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK23-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 4
+// CHECK23-NEXT: [[B:%.*]] = load ptr, ptr [[TMP11]], align 4
+// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK23-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP12]], align 4
// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
-// CHECK23-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
-// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK23-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK23-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
-// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK23-NEXT: [[TMP12:%.*]] = load i8, ptr [[AAA]], align 1
-// CHECK23-NEXT: store i8 [[TMP12]], ptr [[AAA_CASTED]], align 1
-// CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
-// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i32 [[TMP9]], i32 [[TMP11]], i32 [[TMP13]], ptr [[B]])
+// CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[A]], align 4
+// CHECK23-NEXT: store i32 [[TMP13]], ptr [[A_CASTED]], align 4
+// CHECK23-NEXT: [[TMP14:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK23-NEXT: [[TMP15:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK23-NEXT: store i16 [[TMP15]], ptr [[AA_CASTED]], align 2
+// CHECK23-NEXT: [[TMP16:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK23-NEXT: [[TMP17:%.*]] = load i8, ptr [[AAA]], align 1
+// CHECK23-NEXT: store i8 [[TMP17]], ptr [[AAA_CASTED]], align 1
+// CHECK23-NEXT: [[TMP18:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
+// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.omp_outlined, i32 [[TMP14]], i32 [[TMP16]], i32 [[TMP18]], ptr [[B]])
// CHECK23-NEXT: ret void
//
//
@@ -12680,44 +12807,51 @@ int bar(int n){
// CHECK23-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK23-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK23-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK23-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 4
-// CHECK23-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-// CHECK23-NEXT: store i32 [[TMP4]], ptr [[B]], align 4
-// CHECK23-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
+// CHECK23-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK23-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK23-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP3]], align 4
+// CHECK23-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK23-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
-// CHECK23-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
-// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
-// CHECK23-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 4
-// CHECK23-NEXT: [[C:%.*]] = load ptr, ptr [[TMP9]], align 4
-// CHECK23-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 5
-// CHECK23-NEXT: [[TMP11:%.*]] = load i8, ptr [[TMP10]], align 4
-// CHECK23-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP11]], 0
+// CHECK23-NEXT: store i32 [[TMP6]], ptr [[B]], align 4
+// CHECK23-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK23-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4
+// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
+// CHECK23-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK23-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 4
+// CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4
+// CHECK23-NEXT: [[TMP13:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 4
+// CHECK23-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 4
+// CHECK23-NEXT: [[C:%.*]] = load ptr, ptr [[TMP14]], align 4
+// CHECK23-NEXT: [[TMP15:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 5
+// CHECK23-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 4
+// CHECK23-NEXT: [[TMP17:%.*]] = load i8, ptr [[TMP16]], align 4
+// CHECK23-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP17]], 0
// CHECK23-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i8
// CHECK23-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 1
-// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 6
-// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 6
+// CHECK23-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP18]], align 4
// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[B]], align 4
-// CHECK23-NEXT: store i32 [[TMP12]], ptr [[B_CASTED]], align 4
-// CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_CASTED]], align 4
-// CHECK23-NEXT: [[TMP14:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
-// CHECK23-NEXT: [[LOADEDV2:%.*]] = icmp ne i8 [[TMP14]], 0
+// CHECK23-NEXT: [[TMP19:%.*]] = load i32, ptr [[B]], align 4
+// CHECK23-NEXT: store i32 [[TMP19]], ptr [[B_CASTED]], align 4
+// CHECK23-NEXT: [[TMP20:%.*]] = load i32, ptr [[B_CASTED]], align 4
+// CHECK23-NEXT: [[TMP21:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
+// CHECK23-NEXT: [[LOADEDV2:%.*]] = icmp ne i8 [[TMP21]], 0
// CHECK23-NEXT: [[STOREDV3:%.*]] = zext i1 [[LOADEDV2]] to i8
// CHECK23-NEXT: store i8 [[STOREDV3]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1
-// CHECK23-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
-// CHECK23-NEXT: [[TMP16:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
-// CHECK23-NEXT: [[LOADEDV4:%.*]] = icmp ne i8 [[TMP16]], 0
+// CHECK23-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
+// CHECK23-NEXT: [[TMP23:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
+// CHECK23-NEXT: [[LOADEDV4:%.*]] = icmp ne i8 [[TMP23]], 0
// CHECK23-NEXT: br i1 [[LOADEDV4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK23: omp_if.then:
-// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined, ptr [[THIS]], i32 [[TMP13]], i32 [[TMP6]], i32 [[TMP8]], ptr [[C]], i32 [[TMP15]])
+// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined, ptr [[THIS]], i32 [[TMP20]], i32 [[TMP9]], i32 [[TMP12]], ptr [[C]], i32 [[TMP22]])
// CHECK23-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK23: omp_if.else:
// CHECK23-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]])
// CHECK23-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4
// CHECK23-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4
-// CHECK23-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[THIS]], i32 [[TMP13]], i32 [[TMP6]], i32 [[TMP8]], ptr [[C]], i32 [[TMP15]]) #[[ATTR1:[0-9]+]]
+// CHECK23-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[THIS]], i32 [[TMP20]], i32 [[TMP9]], i32 [[TMP12]], ptr [[C]], i32 [[TMP22]]) #[[ATTR1:[0-9]+]]
// CHECK23-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB2]], i32 [[TMP0]])
// CHECK23-NEXT: br label [[OMP_IF_END]]
// CHECK23: omp_if.end:
@@ -12892,24 +13026,28 @@ int bar(int n){
// CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK23-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK23-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK23-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
-// CHECK23-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK23-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK23-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 4
-// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK23-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK23-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK23-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK23-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 4
+// CHECK23-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK23-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK23-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4
+// CHECK23-NEXT: [[B:%.*]] = load ptr, ptr [[TMP8]], align 4
+// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK23-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP9]], align 4
// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// CHECK23-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4
-// CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK23-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK23-NEXT: store i16 [[TMP8]], ptr [[AA_CASTED]], align 2
-// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i32 [[TMP7]], i32 [[TMP9]], ptr [[B]])
+// CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
+// CHECK23-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
+// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK23-NEXT: [[TMP12:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK23-NEXT: store i16 [[TMP12]], ptr [[AA_CASTED]], align 2
+// CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.omp_outlined, i32 [[TMP11]], i32 [[TMP13]], ptr [[B]])
// CHECK23-NEXT: ret void
//
//
diff --git a/clang/test/OpenMP/target_parallel_generic_loop_codegen-2.cpp b/clang/test/OpenMP/target_parallel_generic_loop_codegen-2.cpp
index 30d5ae3089a6b..9bd1b23236dde 100644
--- a/clang/test/OpenMP/target_parallel_generic_loop_codegen-2.cpp
+++ b/clang/test/OpenMP/target_parallel_generic_loop_codegen-2.cpp
@@ -592,16 +592,18 @@ int nested(int a){
// TCHECK-TARGET-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// TCHECK-TARGET-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// TCHECK-TARGET-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// TCHECK-TARGET-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// TCHECK-TARGET-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// TCHECK-TARGET-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// TCHECK-TARGET-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// TCHECK-TARGET-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// TCHECK-TARGET-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// TCHECK-TARGET-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// TCHECK-TARGET-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// TCHECK-TARGET-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// TCHECK-TARGET-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// TCHECK-TARGET-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// TCHECK-TARGET-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 8
// TCHECK-TARGET-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// TCHECK-TARGET-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4
-// TCHECK-TARGET-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4
-// TCHECK-TARGET-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// TCHECK-TARGET-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42.omp_outlined, i64 [[TMP4]])
+// TCHECK-TARGET-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
+// TCHECK-TARGET-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4
+// TCHECK-TARGET-NEXT: [[TMP6:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// TCHECK-TARGET-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42.omp_outlined, i64 [[TMP6]])
// TCHECK-TARGET-NEXT: ret void
//
//
@@ -679,16 +681,18 @@ int nested(int a){
// TCHECK-TARGET-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// TCHECK-TARGET-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// TCHECK-TARGET-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// TCHECK-TARGET-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// TCHECK-TARGET-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// TCHECK-TARGET-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// TCHECK-TARGET-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// TCHECK-TARGET-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// TCHECK-TARGET-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// TCHECK-TARGET-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// TCHECK-TARGET-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// TCHECK-TARGET-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// TCHECK-TARGET-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// TCHECK-TARGET-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// TCHECK-TARGET-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 8
// TCHECK-TARGET-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// TCHECK-TARGET-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4
-// TCHECK-TARGET-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4
-// TCHECK-TARGET-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// TCHECK-TARGET-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49.omp_outlined, i64 [[TMP4]])
+// TCHECK-TARGET-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
+// TCHECK-TARGET-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4
+// TCHECK-TARGET-NEXT: [[TMP6:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// TCHECK-TARGET-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49.omp_outlined, i64 [[TMP6]])
// TCHECK-TARGET-NEXT: ret void
//
//
@@ -766,16 +770,18 @@ int nested(int a){
// TCHECK-TARGET-X86-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// TCHECK-TARGET-X86-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// TCHECK-TARGET-X86-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// TCHECK-TARGET-X86-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// TCHECK-TARGET-X86-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// TCHECK-TARGET-X86-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// TCHECK-TARGET-X86-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// TCHECK-TARGET-X86-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// TCHECK-TARGET-X86-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// TCHECK-TARGET-X86-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// TCHECK-TARGET-X86-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// TCHECK-TARGET-X86-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// TCHECK-TARGET-X86-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// TCHECK-TARGET-X86-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// TCHECK-TARGET-X86-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 4
// TCHECK-TARGET-X86-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// TCHECK-TARGET-X86-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4
-// TCHECK-TARGET-X86-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4
-// TCHECK-TARGET-X86-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// TCHECK-TARGET-X86-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42.omp_outlined, i32 [[TMP4]])
+// TCHECK-TARGET-X86-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
+// TCHECK-TARGET-X86-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4
+// TCHECK-TARGET-X86-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// TCHECK-TARGET-X86-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l42.omp_outlined, i32 [[TMP6]])
// TCHECK-TARGET-X86-NEXT: ret void
//
//
@@ -853,16 +859,18 @@ int nested(int a){
// TCHECK-TARGET-X86-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// TCHECK-TARGET-X86-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// TCHECK-TARGET-X86-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// TCHECK-TARGET-X86-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// TCHECK-TARGET-X86-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// TCHECK-TARGET-X86-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// TCHECK-TARGET-X86-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// TCHECK-TARGET-X86-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// TCHECK-TARGET-X86-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// TCHECK-TARGET-X86-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// TCHECK-TARGET-X86-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// TCHECK-TARGET-X86-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// TCHECK-TARGET-X86-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// TCHECK-TARGET-X86-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// TCHECK-TARGET-X86-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 4
// TCHECK-TARGET-X86-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// TCHECK-TARGET-X86-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4
-// TCHECK-TARGET-X86-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4
-// TCHECK-TARGET-X86-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// TCHECK-TARGET-X86-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49.omp_outlined, i32 [[TMP4]])
+// TCHECK-TARGET-X86-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
+// TCHECK-TARGET-X86-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4
+// TCHECK-TARGET-X86-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// TCHECK-TARGET-X86-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6nestedi_l49.omp_outlined, i32 [[TMP6]])
// TCHECK-TARGET-X86-NEXT: ret void
//
//
diff --git a/clang/test/OpenMP/target_parallel_if_codegen.cpp b/clang/test/OpenMP/target_parallel_if_codegen.cpp
index 0917f4289d5c3..7daa70ba3fe4b 100644
--- a/clang/test/OpenMP/target_parallel_if_codegen.cpp
+++ b/clang/test/OpenMP/target_parallel_if_codegen.cpp
@@ -1623,16 +1623,18 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[TMP3:%.*]] = load i8, ptr [[TMP2]], align 8
-// CHECK9-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP3]], 0
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 8
+// CHECK9-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP4]], 0
// CHECK9-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i8
// CHECK9-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 1
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
-// CHECK9-NEXT: [[LOADEDV2:%.*]] = icmp ne i8 [[TMP4]], 0
+// CHECK9-NEXT: [[TMP6:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
+// CHECK9-NEXT: [[LOADEDV2:%.*]] = icmp ne i8 [[TMP6]], 0
// CHECK9-NEXT: br i1 [[LOADEDV2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK9: omp_if.then:
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined)
@@ -1665,8 +1667,9 @@ int bar(int n){
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP1]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.omp_outlined)
// CHECK9-NEXT: ret void
@@ -1695,33 +1698,37 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
-// CHECK9-NEXT: store i32 [[TMP4]], ptr [[B]], align 4
-// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
-// CHECK9-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 8
-// CHECK9-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP6]], 0
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 8
+// CHECK9-NEXT: store i32 [[TMP6]], ptr [[B]], align 4
+// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8
+// CHECK9-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 8
+// CHECK9-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP9]], 0
// CHECK9-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i8
// CHECK9-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 1
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP10]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[B]], align 4
-// CHECK9-NEXT: store i32 [[TMP7]], ptr [[B_CASTED]], align 4
-// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[B_CASTED]], align 8
-// CHECK9-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
-// CHECK9-NEXT: [[LOADEDV2:%.*]] = icmp ne i8 [[TMP9]], 0
+// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[B]], align 4
+// CHECK9-NEXT: store i32 [[TMP11]], ptr [[B_CASTED]], align 4
+// CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[B_CASTED]], align 8
+// CHECK9-NEXT: [[TMP13:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
+// CHECK9-NEXT: [[LOADEDV2:%.*]] = icmp ne i8 [[TMP13]], 0
// CHECK9-NEXT: br i1 [[LOADEDV2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK9: omp_if.then:
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[THIS]], i64 [[TMP8]])
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[THIS]], i64 [[TMP12]])
// CHECK9-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK9: omp_if.else:
// CHECK9-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
// CHECK9-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4
// CHECK9-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4
-// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[THIS]], i64 [[TMP8]]) #[[ATTR1]]
+// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[THIS]], i64 [[TMP12]]) #[[ATTR1]]
// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
// CHECK9-NEXT: br label [[OMP_IF_END]]
// CHECK9: omp_if.end:
@@ -1759,18 +1766,21 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK9-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 8
-// CHECK9-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP4]], 0
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK9-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 8
+// CHECK9-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP6]], 0
// CHECK9-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i8
// CHECK9-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 1
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP5:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
-// CHECK9-NEXT: [[LOADEDV2:%.*]] = icmp ne i8 [[TMP5]], 0
+// CHECK9-NEXT: [[TMP8:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
+// CHECK9-NEXT: [[LOADEDV2:%.*]] = icmp ne i8 [[TMP8]], 0
// CHECK9-NEXT: br i1 [[LOADEDV2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK9: omp_if.then:
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[THIS]])
@@ -1813,19 +1823,21 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
+// CHECK9-NEXT: store i32 [[TMP4]], ptr [[A]], align 4
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4
-// CHECK9-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4
-// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
+// CHECK9-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4
+// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[A_CASTED]], align 8
// CHECK9-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
// CHECK9-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4
// CHECK9-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4
-// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], i64 [[TMP5]]) #[[ATTR1]]
+// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], i64 [[TMP7]]) #[[ATTR1]]
// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
// CHECK9-NEXT: ret void
//
@@ -1856,22 +1868,25 @@ int bar(int n){
// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
-// CHECK9-NEXT: store i16 [[TMP4]], ptr [[B]], align 2
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK9-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 8
+// CHECK9-NEXT: store i16 [[TMP6]], ptr [[B]], align 2
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
-// CHECK9-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4
-// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[B]], align 2
-// CHECK9-NEXT: store i16 [[TMP7]], ptr [[B_CASTED]], align 2
-// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[B_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i64 [[TMP6]], i64 [[TMP8]])
+// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
+// CHECK9-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
+// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK9-NEXT: [[TMP10:%.*]] = load i16, ptr [[B]], align 2
+// CHECK9-NEXT: store i16 [[TMP10]], ptr [[B_CASTED]], align 2
+// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[B_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i64 [[TMP9]], i64 [[TMP11]])
// CHECK9-NEXT: ret void
//
//
@@ -1905,16 +1920,18 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[TMP3:%.*]] = load i8, ptr [[TMP2]], align 4
-// CHECK11-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP3]], 0
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 4
+// CHECK11-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP4]], 0
// CHECK11-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i8
// CHECK11-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 1
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
-// CHECK11-NEXT: [[LOADEDV2:%.*]] = icmp ne i8 [[TMP4]], 0
+// CHECK11-NEXT: [[TMP6:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
+// CHECK11-NEXT: [[LOADEDV2:%.*]] = icmp ne i8 [[TMP6]], 0
// CHECK11-NEXT: br i1 [[LOADEDV2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK11: omp_if.then:
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined)
@@ -1947,8 +1964,9 @@ int bar(int n){
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP1]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.omp_outlined)
// CHECK11-NEXT: ret void
@@ -1977,33 +1995,37 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-// CHECK11-NEXT: store i32 [[TMP4]], ptr [[B]], align 4
-// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
-// CHECK11-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 4
-// CHECK11-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP6]], 0
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP3]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
+// CHECK11-NEXT: store i32 [[TMP6]], ptr [[B]], align 4
+// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4
+// CHECK11-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 4
+// CHECK11-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP9]], 0
// CHECK11-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i8
// CHECK11-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 1
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP10]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[B]], align 4
-// CHECK11-NEXT: store i32 [[TMP7]], ptr [[B_CASTED]], align 4
-// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_CASTED]], align 4
-// CHECK11-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
-// CHECK11-NEXT: [[LOADEDV2:%.*]] = icmp ne i8 [[TMP9]], 0
+// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[B]], align 4
+// CHECK11-NEXT: store i32 [[TMP11]], ptr [[B_CASTED]], align 4
+// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_CASTED]], align 4
+// CHECK11-NEXT: [[TMP13:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
+// CHECK11-NEXT: [[LOADEDV2:%.*]] = icmp ne i8 [[TMP13]], 0
// CHECK11-NEXT: br i1 [[LOADEDV2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK11: omp_if.then:
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[THIS]], i32 [[TMP8]])
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[THIS]], i32 [[TMP12]])
// CHECK11-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK11: omp_if.else:
// CHECK11-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4
// CHECK11-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4
-// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[THIS]], i32 [[TMP8]]) #[[ATTR1]]
+// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[THIS]], i32 [[TMP12]]) #[[ATTR1]]
// CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
// CHECK11-NEXT: br label [[OMP_IF_END]]
// CHECK11: omp_if.end:
@@ -2041,18 +2063,21 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK11-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 4
-// CHECK11-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP4]], 0
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP3]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 4
+// CHECK11-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP6]], 0
// CHECK11-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i8
// CHECK11-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 1
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP5:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
-// CHECK11-NEXT: [[LOADEDV2:%.*]] = icmp ne i8 [[TMP5]], 0
+// CHECK11-NEXT: [[TMP8:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
+// CHECK11-NEXT: [[LOADEDV2:%.*]] = icmp ne i8 [[TMP8]], 0
// CHECK11-NEXT: br i1 [[LOADEDV2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
// CHECK11: omp_if.then:
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[THIS]])
@@ -2095,19 +2120,21 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
+// CHECK11-NEXT: store i32 [[TMP4]], ptr [[A]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4
-// CHECK11-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
+// CHECK11-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[A_CASTED]], align 4
// CHECK11-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4
// CHECK11-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4
-// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], i32 [[TMP5]]) #[[ATTR1]]
+// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], i32 [[TMP7]]) #[[ATTR1]]
// CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
// CHECK11-NEXT: ret void
//
@@ -2138,22 +2165,25 @@ int bar(int n){
// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
-// CHECK11-NEXT: store i16 [[TMP4]], ptr [[B]], align 2
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 4
+// CHECK11-NEXT: store i16 [[TMP6]], ptr [[B]], align 2
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
-// CHECK11-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[B]], align 2
-// CHECK11-NEXT: store i16 [[TMP7]], ptr [[B_CASTED]], align 2
-// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i32 [[TMP6]], i32 [[TMP8]])
+// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
+// CHECK11-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP10:%.*]] = load i16, ptr [[B]], align 2
+// CHECK11-NEXT: store i16 [[TMP10]], ptr [[B_CASTED]], align 2
+// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[B_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i32 [[TMP9]], i32 [[TMP11]])
// CHECK11-NEXT: ret void
//
//
diff --git a/clang/test/OpenMP/target_parallel_num_threads_codegen.cpp b/clang/test/OpenMP/target_parallel_num_threads_codegen.cpp
index 2878e37e6eec3..7131f9bac93b5 100644
--- a/clang/test/OpenMP/target_parallel_num_threads_codegen.cpp
+++ b/clang/test/OpenMP/target_parallel_num_threads_codegen.cpp
@@ -1460,14 +1460,16 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK9-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
+// CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]])
+// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP6]])
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined)
// CHECK9-NEXT: ret void
//
@@ -1491,14 +1493,16 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK9-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
+// CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]])
+// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP6]])
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.omp_outlined)
// CHECK9-NEXT: ret void
//
@@ -1524,23 +1528,27 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
-// CHECK9-NEXT: store i32 [[TMP4]], ptr [[B]], align 4
-// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 8
-// CHECK9-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: store i32 [[TMP6]], ptr [[B]], align 4
+// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8
+// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 8
+// CHECK9-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP10]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP7]])
-// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 4
-// CHECK9-NEXT: store i32 [[TMP8]], ptr [[B_CASTED]], align 4
-// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[B_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[THIS]], i64 [[TMP9]])
+// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP11]])
+// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[B]], align 4
+// CHECK9-NEXT: store i32 [[TMP12]], ptr [[B_CASTED]], align 4
+// CHECK9-NEXT: [[TMP13:%.*]] = load i64, ptr [[B_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[THIS]], i64 [[TMP13]])
// CHECK9-NEXT: ret void
//
//
@@ -1572,10 +1580,12 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 8
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 1024)
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[THIS]])
@@ -1605,8 +1615,9 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP2]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 20)
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.omp_outlined)
@@ -1636,28 +1647,32 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
-// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 8
-// CHECK9-NEXT: store i16 [[TMP5]], ptr [[B]], align 2
-// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
+// CHECK9-NEXT: store i32 [[TMP4]], ptr [[A]], align 4
+// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 8
-// CHECK9-NEXT: store i16 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 2
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: store i16 [[TMP7]], ptr [[B]], align 2
+// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8
+// CHECK9-NEXT: [[TMP10:%.*]] = load i16, ptr [[TMP9]], align 8
+// CHECK9-NEXT: store i16 [[TMP10]], ptr [[DOTCAPTURE_EXPR_]], align 2
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP11]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP8:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2
-// CHECK9-NEXT: [[TMP9:%.*]] = sext i16 [[TMP8]] to i32
-// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP9]])
-// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
-// CHECK9-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
-// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP12:%.*]] = load i16, ptr [[B]], align 2
-// CHECK9-NEXT: store i16 [[TMP12]], ptr [[B_CASTED]], align 2
-// CHECK9-NEXT: [[TMP13:%.*]] = load i64, ptr [[B_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i64 [[TMP11]], i64 [[TMP13]])
+// CHECK9-NEXT: [[TMP12:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2
+// CHECK9-NEXT: [[TMP13:%.*]] = sext i16 [[TMP12]] to i32
+// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP13]])
+// CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4
+// CHECK9-NEXT: store i32 [[TMP14]], ptr [[A_CASTED]], align 4
+// CHECK9-NEXT: [[TMP15:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK9-NEXT: [[TMP16:%.*]] = load i16, ptr [[B]], align 2
+// CHECK9-NEXT: store i16 [[TMP16]], ptr [[B_CASTED]], align 2
+// CHECK9-NEXT: [[TMP17:%.*]] = load i64, ptr [[B_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i64 [[TMP15]], i64 [[TMP17]])
// CHECK9-NEXT: ret void
//
//
@@ -1689,14 +1704,16 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK11-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
+// CHECK11-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]])
+// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP6]])
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined)
// CHECK11-NEXT: ret void
//
@@ -1720,14 +1737,16 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK11-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
+// CHECK11-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]])
+// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP6]])
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.omp_outlined)
// CHECK11-NEXT: ret void
//
@@ -1753,23 +1772,27 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-// CHECK11-NEXT: store i32 [[TMP4]], ptr [[B]], align 4
-// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP3]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
-// CHECK11-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: store i32 [[TMP6]], ptr [[B]], align 4
+// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4
+// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
+// CHECK11-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP10]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP7]])
-// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 4
-// CHECK11-NEXT: store i32 [[TMP8]], ptr [[B_CASTED]], align 4
-// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[B_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[THIS]], i32 [[TMP9]])
+// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP11]])
+// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[B]], align 4
+// CHECK11-NEXT: store i32 [[TMP12]], ptr [[B_CASTED]], align 4
+// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[THIS]], i32 [[TMP13]])
// CHECK11-NEXT: ret void
//
//
@@ -1801,10 +1824,12 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP3]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK11-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 1024)
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[THIS]])
@@ -1834,8 +1859,9 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP2]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK11-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 20)
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.omp_outlined)
@@ -1865,28 +1891,32 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 4
-// CHECK11-NEXT: store i16 [[TMP5]], ptr [[B]], align 2
-// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
+// CHECK11-NEXT: store i32 [[TMP4]], ptr [[A]], align 4
+// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 4
-// CHECK11-NEXT: store i16 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 2
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: store i16 [[TMP7]], ptr [[B]], align 2
+// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 4
+// CHECK11-NEXT: [[TMP10:%.*]] = load i16, ptr [[TMP9]], align 4
+// CHECK11-NEXT: store i16 [[TMP10]], ptr [[DOTCAPTURE_EXPR_]], align 2
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK11-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP11]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP8:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2
-// CHECK11-NEXT: [[TMP9:%.*]] = sext i16 [[TMP8]] to i32
-// CHECK11-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP9]])
-// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
-// CHECK11-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP12:%.*]] = load i16, ptr [[B]], align 2
-// CHECK11-NEXT: store i16 [[TMP12]], ptr [[B_CASTED]], align 2
-// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i32 [[TMP11]], i32 [[TMP13]])
+// CHECK11-NEXT: [[TMP12:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2
+// CHECK11-NEXT: [[TMP13:%.*]] = sext i16 [[TMP12]] to i32
+// CHECK11-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP13]])
+// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4
+// CHECK11-NEXT: store i32 [[TMP14]], ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP16:%.*]] = load i16, ptr [[B]], align 2
+// CHECK11-NEXT: store i16 [[TMP16]], ptr [[B_CASTED]], align 2
+// CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[B_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i32 [[TMP15]], i32 [[TMP17]])
// CHECK11-NEXT: ret void
//
//
diff --git a/clang/test/OpenMP/target_parallel_num_threads_strict_codegen.cpp b/clang/test/OpenMP/target_parallel_num_threads_strict_codegen.cpp
index b5b44fd50a7dd..b72aa3d618c9e 100644
--- a/clang/test/OpenMP/target_parallel_num_threads_strict_codegen.cpp
+++ b/clang/test/OpenMP/target_parallel_num_threads_strict_codegen.cpp
@@ -1097,19 +1097,22 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK9-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = load ptr, ptr [[TMP4]], align 8
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
+// CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8
+// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = load ptr, ptr [[TMP6]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 8
// CHECK9-NEXT: store ptr [[DOTCAPTURE_EXPR_1]], ptr [[TMP]], align 8
-// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META11:![0-9]+]]
-// CHECK9-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP6]], i64 0, i64 0
-// CHECK9-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP5]], i32 2, ptr [[ARRAYDECAY]])
+// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META11:![0-9]+]]
+// CHECK9-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP9]], i64 0, i64 0
+// CHECK9-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP8]], i32 2, ptr [[ARRAYDECAY]])
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l61.omp_outlined)
// CHECK9-NEXT: ret void
//
@@ -1133,14 +1136,16 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK9-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
+// CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 1, ptr null)
+// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP6]], i32 1, ptr null)
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l65.omp_outlined)
// CHECK9-NEXT: ret void
//
@@ -1165,19 +1170,22 @@ int bar(int n){
// CHECK9-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
-// CHECK9-NEXT: store i32 [[TMP4]], ptr [[N]], align 4
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 8
+// CHECK9-NEXT: store i32 [[TMP6]], ptr [[N]], align 4
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[N]], align 4
-// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP5]])
-// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[CALL]]
+// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[N]], align 4
+// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP8]])
+// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4
+// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[CALL]]
// CHECK9-NEXT: store i32 [[ADD]], ptr [[A]], align 4
// CHECK9-NEXT: ret void
//
@@ -1215,19 +1223,22 @@ int bar(int n){
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
-// CHECK9-NEXT: store i32 [[TMP4]], ptr [[N]], align 4
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 8
+// CHECK9-NEXT: store i32 [[TMP6]], ptr [[N]], align 4
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[N]], align 4
-// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP5]])
-// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[CALL]]
+// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[N]], align 4
+// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP8]])
+// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4
+// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[CALL]]
// CHECK9-NEXT: store i32 [[ADD]], ptr [[A]], align 4
// CHECK9-NEXT: ret void
//
@@ -1329,19 +1340,22 @@ int bar(int n){
// CHECK10-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
// CHECK10-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK10-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK10-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK10-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
-// CHECK10-NEXT: store i32 [[TMP4]], ptr [[N]], align 4
-// CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK10-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK10-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK10-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK10-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK10-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 8
+// CHECK10-NEXT: store i32 [[TMP6]], ptr [[N]], align 4
+// CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK10-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK10-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 8
// CHECK10-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK10-NEXT: [[TMP5:%.*]] = load i32, ptr [[N]], align 4
-// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP5]])
-// CHECK10-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[CALL]]
+// CHECK10-NEXT: [[TMP8:%.*]] = load i32, ptr [[N]], align 4
+// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP8]])
+// CHECK10-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4
+// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[CALL]]
// CHECK10-NEXT: store i32 [[ADD]], ptr [[A]], align 4
// CHECK10-NEXT: ret void
//
@@ -1379,19 +1393,22 @@ int bar(int n){
// CHECK10-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK10-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK10-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK10-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK10-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
-// CHECK10-NEXT: store i32 [[TMP4]], ptr [[N]], align 4
-// CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK10-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK10-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK10-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK10-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK10-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 8
+// CHECK10-NEXT: store i32 [[TMP6]], ptr [[N]], align 4
+// CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK10-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK10-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 8
// CHECK10-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK10-NEXT: [[TMP5:%.*]] = load i32, ptr [[N]], align 4
-// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP5]])
-// CHECK10-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[CALL]]
+// CHECK10-NEXT: [[TMP8:%.*]] = load i32, ptr [[N]], align 4
+// CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP8]])
+// CHECK10-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4
+// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[CALL]]
// CHECK10-NEXT: store i32 [[ADD]], ptr [[A]], align 4
// CHECK10-NEXT: ret void
//
@@ -1426,19 +1443,22 @@ int bar(int n){
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK10-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK10-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK10-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = load ptr, ptr [[TMP4]], align 8
-// CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
-// CHECK10-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK10-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
+// CHECK10-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK10-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8
+// CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = load ptr, ptr [[TMP6]], align 8
+// CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK10-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK10-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 8
// CHECK10-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 8
// CHECK10-NEXT: store ptr [[DOTCAPTURE_EXPR_1]], ptr [[TMP]], align 8
-// CHECK10-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK10-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META11:![0-9]+]]
-// CHECK10-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP6]], i64 0, i64 0
-// CHECK10-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP5]], i32 2, ptr [[ARRAYDECAY]])
+// CHECK10-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK10-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META11:![0-9]+]]
+// CHECK10-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP9]], i64 0, i64 0
+// CHECK10-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP8]], i32 2, ptr [[ARRAYDECAY]])
// CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l61.omp_outlined)
// CHECK10-NEXT: ret void
//
@@ -1462,14 +1482,16 @@ int bar(int n){
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK10-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK10-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK10-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK10-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK10-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
+// CHECK10-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK10-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK10-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK10-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK10-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK10-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 1, ptr null)
+// CHECK10-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK10-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP6]], i32 1, ptr null)
// CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l65.omp_outlined)
// CHECK10-NEXT: ret void
//
@@ -1561,19 +1583,22 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK11-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = load ptr, ptr [[TMP4]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
+// CHECK11-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4
+// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = load ptr, ptr [[TMP6]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 4
// CHECK11-NEXT: store ptr [[DOTCAPTURE_EXPR_1]], ptr [[TMP]], align 4
-// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META12:![0-9]+]]
-// CHECK11-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP6]], i32 0, i32 0
-// CHECK11-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP5]], i32 2, ptr [[ARRAYDECAY]])
+// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META12:![0-9]+]]
+// CHECK11-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP9]], i32 0, i32 0
+// CHECK11-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP8]], i32 2, ptr [[ARRAYDECAY]])
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l61.omp_outlined)
// CHECK11-NEXT: ret void
//
@@ -1597,14 +1622,16 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK11-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
+// CHECK11-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 1, ptr null)
+// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP6]], i32 1, ptr null)
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l65.omp_outlined)
// CHECK11-NEXT: ret void
//
@@ -1629,19 +1656,22 @@ int bar(int n){
// CHECK11-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-// CHECK11-NEXT: store i32 [[TMP4]], ptr [[N]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
+// CHECK11-NEXT: store i32 [[TMP6]], ptr [[N]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[N]], align 4
-// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP5]])
-// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[CALL]]
+// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[N]], align 4
+// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP8]])
+// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4
+// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[CALL]]
// CHECK11-NEXT: store i32 [[ADD]], ptr [[A]], align 4
// CHECK11-NEXT: ret void
//
@@ -1679,19 +1709,22 @@ int bar(int n){
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-// CHECK11-NEXT: store i32 [[TMP4]], ptr [[N]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
+// CHECK11-NEXT: store i32 [[TMP6]], ptr [[N]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[N]], align 4
-// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP5]])
-// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[CALL]]
+// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[N]], align 4
+// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP8]])
+// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4
+// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[CALL]]
// CHECK11-NEXT: store i32 [[ADD]], ptr [[A]], align 4
// CHECK11-NEXT: ret void
//
@@ -1793,19 +1826,22 @@ int bar(int n){
// CHECK12-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
// CHECK12-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK12-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK12-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK12-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK12-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-// CHECK12-NEXT: store i32 [[TMP4]], ptr [[N]], align 4
-// CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK12-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK12-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK12-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK12-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK12-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK12-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK12-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
+// CHECK12-NEXT: store i32 [[TMP6]], ptr [[N]], align 4
+// CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK12-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK12-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 4
// CHECK12-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK12-NEXT: [[TMP5:%.*]] = load i32, ptr [[N]], align 4
-// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP5]])
-// CHECK12-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[CALL]]
+// CHECK12-NEXT: [[TMP8:%.*]] = load i32, ptr [[N]], align 4
+// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP8]])
+// CHECK12-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4
+// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[CALL]]
// CHECK12-NEXT: store i32 [[ADD]], ptr [[A]], align 4
// CHECK12-NEXT: ret void
//
@@ -1843,19 +1879,22 @@ int bar(int n){
// CHECK12-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK12-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK12-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK12-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK12-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK12-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-// CHECK12-NEXT: store i32 [[TMP4]], ptr [[N]], align 4
-// CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK12-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK12-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK12-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK12-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK12-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK12-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK12-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
+// CHECK12-NEXT: store i32 [[TMP6]], ptr [[N]], align 4
+// CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK12-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK12-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 4
// CHECK12-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK12-NEXT: [[TMP5:%.*]] = load i32, ptr [[N]], align 4
-// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP5]])
-// CHECK12-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[CALL]]
+// CHECK12-NEXT: [[TMP8:%.*]] = load i32, ptr [[N]], align 4
+// CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP8]])
+// CHECK12-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4
+// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[CALL]]
// CHECK12-NEXT: store i32 [[ADD]], ptr [[A]], align 4
// CHECK12-NEXT: ret void
//
@@ -1890,19 +1929,22 @@ int bar(int n){
// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK12-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK12-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK12-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = load ptr, ptr [[TMP4]], align 4
-// CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
-// CHECK12-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK12-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK12-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
+// CHECK12-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK12-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4
+// CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = load ptr, ptr [[TMP6]], align 4
+// CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK12-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK12-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 4
// CHECK12-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 4
// CHECK12-NEXT: store ptr [[DOTCAPTURE_EXPR_1]], ptr [[TMP]], align 4
-// CHECK12-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK12-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META12:![0-9]+]]
-// CHECK12-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP6]], i32 0, i32 0
-// CHECK12-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP5]], i32 2, ptr [[ARRAYDECAY]])
+// CHECK12-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK12-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META12:![0-9]+]]
+// CHECK12-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x i8], ptr [[TMP9]], i32 0, i32 0
+// CHECK12-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP8]], i32 2, ptr [[ARRAYDECAY]])
// CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l61.omp_outlined)
// CHECK12-NEXT: ret void
//
@@ -1926,14 +1968,16 @@ int bar(int n){
// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK12-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK12-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK12-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK12-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK12-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK12-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
+// CHECK12-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK12-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK12-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK12-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK12-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK12-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 1, ptr null)
+// CHECK12-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK12-NEXT: call void @__kmpc_push_num_threads_strict(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP6]], i32 1, ptr null)
// CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l65.omp_outlined)
// CHECK12-NEXT: ret void
//
diff --git a/clang/test/OpenMP/target_private_codegen.cpp b/clang/test/OpenMP/target_private_codegen.cpp
index 9f662083e7be2..32073298a8bad 100644
--- a/clang/test/OpenMP/target_private_codegen.cpp
+++ b/clang/test/OpenMP/target_private_codegen.cpp
@@ -210,8 +210,9 @@ struct S1 {
// TCHECK: [[DYN_PTR:%.+]] = alloca ptr
// TCHECK: [[B:%.+]] = alloca i{{[0-9]+}},
// TCHECK: [[SSTACK:%.+]] = alloca ptr,
- // TCHECK: getelementptr inbounds i{{[0-9]+}}, ptr {{%.+}}, i32 0
- // TCHECK: [[TH_ADDR_REF:%.+]] = load ptr, ptr {{%.+}},
+ // TCHECK: [[TH_SLOT:%.+]] = getelementptr inbounds ptr, ptr {{%.+}}, i32 0
+ // TCHECK: [[TH_PTR:%.+]] = load ptr, ptr [[TH_SLOT]],
+ // TCHECK: [[TH_ADDR_REF:%.+]] = load ptr, ptr [[TH_PTR]],
// TCHECK: [[VLA_ADDR_REF:%.+]] = load i{{[0-9]+}}, ptr {{%.+}},
// TCHECK: [[VLA_ADDR_REF2:%.+]] = load i{{[0-9]+}}, ptr {{%.+}},
// TCHECK: [[RET_STACK:%.+]] = call ptr @llvm.stacksave.p0()
diff --git a/clang/test/OpenMP/target_task_affinity_codegen.cpp b/clang/test/OpenMP/target_task_affinity_codegen.cpp
index 23e2962583250..28904c62b1b8c 100644
--- a/clang/test/OpenMP/target_task_affinity_codegen.cpp
+++ b/clang/test/OpenMP/target_task_affinity_codegen.cpp
@@ -297,7 +297,7 @@ int main() {
// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META13]]
// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META13]]
// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META13]]
-// CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR1]]
+// CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR1]], !inline_history [[META14:![0-9]+]]
// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META13]]
// CHECK1-NEXT: store i32 0, ptr [[I_I]], align 4, !noalias [[META13]]
// CHECK1-NEXT: br label [[FOR_COND_I:%.*]]
@@ -312,7 +312,7 @@ int main() {
// CHECK1-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds i32, ptr [[TMP14]], i64 [[IDXPROM_I]]
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[ARRAYIDX_I]], align 4
// CHECK1-NEXT: [[MUL_I:%.*]] = mul nsw i32 2, [[TMP16]]
-// CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP9]], align 8, !nonnull [[META14:![0-9]+]], !align [[META15:![0-9]+]]
+// CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP9]], align 8, !nonnull [[META15:![0-9]+]], !align [[META16:![0-9]+]]
// CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[I_I]], align 4, !noalias [[META13]]
// CHECK1-NEXT: [[IDXPROM1_I:%.*]] = sext i32 [[TMP19]] to i64
@@ -321,7 +321,7 @@ int main() {
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[I_I]], align 4, !noalias [[META13]]
// CHECK1-NEXT: [[INC_I:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK1-NEXT: store i32 [[INC_I]], ptr [[I_I]], align 4, !noalias [[META13]]
-// CHECK1-NEXT: br label [[FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]]
+// CHECK1-NEXT: br label [[FOR_COND_I]], !llvm.loop [[LOOP17:![0-9]+]]
// CHECK1: .omp_outlined..exit:
// CHECK1-NEXT: ret i32 0
//
@@ -540,7 +540,7 @@ int main() {
// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META14]]
// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META14]]
// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META14]]
-// CHECK3-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR1]]
+// CHECK3-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR1]], !inline_history [[META15:![0-9]+]]
// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias [[META14]]
// CHECK3-NEXT: store i32 0, ptr [[I_I]], align 4, !noalias [[META14]]
// CHECK3-NEXT: br label [[FOR_COND_I:%.*]]
@@ -554,7 +554,7 @@ int main() {
// CHECK3-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds i32, ptr [[TMP14]], i32 [[TMP15]]
// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[ARRAYIDX_I]], align 4
// CHECK3-NEXT: [[MUL_I:%.*]] = mul nsw i32 2, [[TMP16]]
-// CHECK3-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP9]], align 4, !nonnull [[META15:![0-9]+]], !align [[META16:![0-9]+]]
+// CHECK3-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP9]], align 4, !nonnull [[META16:![0-9]+]], !align [[META17:![0-9]+]]
// CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 4
// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[I_I]], align 4, !noalias [[META14]]
// CHECK3-NEXT: [[ARRAYIDX1_I:%.*]] = getelementptr inbounds i32, ptr [[TMP18]], i32 [[TMP19]]
@@ -562,7 +562,7 @@ int main() {
// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[I_I]], align 4, !noalias [[META14]]
// CHECK3-NEXT: [[INC_I:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK3-NEXT: store i32 [[INC_I]], ptr [[I_I]], align 4, !noalias [[META14]]
-// CHECK3-NEXT: br label [[FOR_COND_I]], !llvm.loop [[LOOP17:![0-9]+]]
+// CHECK3-NEXT: br label [[FOR_COND_I]], !llvm.loop [[LOOP18:![0-9]+]]
// CHECK3: .omp_outlined..exit:
// CHECK3-NEXT: ret i32 0
//
@@ -647,40 +647,43 @@ int main() {
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK9-NEXT: [[A:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
-// CHECK9-NEXT: store ptr [[B]], ptr [[TMP2]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i64 48, i64 8, ptr @.omp_task_entry.)
-// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x [[STRUCT_KMP_TASK_AFFINITY_INFO_T]]], ptr [[DOTAFFS_ARR_ADDR]], i64 0, i64 0
-// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[A]], align 8
-// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP5]], i64 0
-// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[A]], align 8
-// CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP6]], i64 1023
-// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[ARRAYIDX2]], i32 1
-// CHECK9-NEXT: [[TMP8:%.*]] = ptrtoaddr ptr [[TMP7]] to i64
-// CHECK9-NEXT: [[TMP9:%.*]] = ptrtoaddr ptr [[ARRAYIDX]] to i64
-// CHECK9-NEXT: [[TMP10:%.*]] = sub nuw i64 [[TMP8]], [[TMP9]]
-// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr [[STRUCT_KMP_TASK_AFFINITY_INFO_T]], ptr [[TMP4]], i64 0
-// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_AFFINITY_INFO_T]], ptr [[TMP11]], i32 0, i32 0
-// CHECK9-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i64
-// CHECK9-NEXT: store i64 [[TMP13]], ptr [[TMP12]], align 8
-// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_AFFINITY_INFO_T]], ptr [[TMP11]], i32 0, i32 1
-// CHECK9-NEXT: store i64 [[TMP10]], ptr [[TMP14]], align 8
-// CHECK9-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_omp_reg_task_with_affinity(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP3]], i32 1, ptr [[TMP4]])
-// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
-// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP16]], i32 0, i32 0
-// CHECK9-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8
-// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP18]], ptr align 8 [[AGG_CAPTURED]], i64 8, i1 false)
-// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
-// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP19]], i32 0, i32 0
-// CHECK9-NEXT: [[TMP21:%.*]] = load ptr, ptr [[A]], align 8
-// CHECK9-NEXT: store ptr [[TMP21]], ptr [[TMP20]], align 8
-// CHECK9-NEXT: [[TMP22:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP3]])
-// CHECK9-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_omp_taskwait(ptr @[[GLOB1]], i32 [[TMP0]])
+// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
+// CHECK9-NEXT: store ptr [[B]], ptr [[TMP5]], align 8
+// CHECK9-NEXT: [[TMP6:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i64 48, i64 8, ptr @.omp_task_entry.)
+// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x [[STRUCT_KMP_TASK_AFFINITY_INFO_T]]], ptr [[DOTAFFS_ARR_ADDR]], i64 0, i64 0
+// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[A]], align 8
+// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP8]], i64 0
+// CHECK9-NEXT: [[TMP9:%.*]] = load ptr, ptr [[A]], align 8
+// CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP9]], i64 1023
+// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[ARRAYIDX2]], i32 1
+// CHECK9-NEXT: [[TMP11:%.*]] = ptrtoaddr ptr [[TMP10]] to i64
+// CHECK9-NEXT: [[TMP12:%.*]] = ptrtoaddr ptr [[ARRAYIDX]] to i64
+// CHECK9-NEXT: [[TMP13:%.*]] = sub nuw i64 [[TMP11]], [[TMP12]]
+// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr [[STRUCT_KMP_TASK_AFFINITY_INFO_T]], ptr [[TMP7]], i64 0
+// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_AFFINITY_INFO_T]], ptr [[TMP14]], i32 0, i32 0
+// CHECK9-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i64
+// CHECK9-NEXT: store i64 [[TMP16]], ptr [[TMP15]], align 8
+// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_AFFINITY_INFO_T]], ptr [[TMP14]], i32 0, i32 1
+// CHECK9-NEXT: store i64 [[TMP13]], ptr [[TMP17]], align 8
+// CHECK9-NEXT: [[TMP18:%.*]] = call i32 @__kmpc_omp_reg_task_with_affinity(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP6]], i32 1, ptr [[TMP7]])
+// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP6]], i32 0, i32 0
+// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP19]], i32 0, i32 0
+// CHECK9-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP20]], align 8
+// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP21]], ptr align 8 [[AGG_CAPTURED]], i64 8, i1 false)
+// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP6]], i32 0, i32 1
+// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP22]], i32 0, i32 0
+// CHECK9-NEXT: [[TMP24:%.*]] = load ptr, ptr [[A]], align 8
+// CHECK9-NEXT: store ptr [[TMP24]], ptr [[TMP23]], align 8
+// CHECK9-NEXT: [[TMP25:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP6]])
+// CHECK9-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_omp_taskwait(ptr @[[GLOB1]], i32 [[TMP0]])
// CHECK9-NEXT: ret void
//
//
@@ -733,7 +736,7 @@ int main() {
// CHECK9-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]
// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]]
// CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]]
-// CHECK9-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR3:[0-9]+]]
+// CHECK9-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR3:[0-9]+]], !inline_history [[META15:![0-9]+]]
// CHECK9-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META14]]
// CHECK9-NEXT: store i32 0, ptr [[I_I]], align 4, !noalias [[META14]]
// CHECK9-NEXT: br label [[FOR_COND_I:%.*]]
@@ -748,7 +751,7 @@ int main() {
// CHECK9-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds i32, ptr [[TMP14]], i64 [[IDXPROM_I]]
// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[ARRAYIDX_I]], align 4
// CHECK9-NEXT: [[MUL_I:%.*]] = mul nsw i32 2, [[TMP16]]
-// CHECK9-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP9]], align 8, !nonnull [[META15:![0-9]+]], !align [[META16:![0-9]+]]
+// CHECK9-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP9]], align 8, !nonnull [[META16:![0-9]+]], !align [[META17:![0-9]+]]
// CHECK9-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8
// CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[I_I]], align 4, !noalias [[META14]]
// CHECK9-NEXT: [[IDXPROM1_I:%.*]] = sext i32 [[TMP19]] to i64
@@ -757,7 +760,7 @@ int main() {
// CHECK9-NEXT: [[TMP20:%.*]] = load i32, ptr [[I_I]], align 4, !noalias [[META14]]
// CHECK9-NEXT: [[INC_I:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK9-NEXT: store i32 [[INC_I]], ptr [[I_I]], align 4, !noalias [[META14]]
-// CHECK9-NEXT: br label [[FOR_COND_I]], !llvm.loop [[LOOP17:![0-9]+]]
+// CHECK9-NEXT: br label [[FOR_COND_I]], !llvm.loop [[LOOP18:![0-9]+]]
// CHECK9: .omp_outlined..exit:
// CHECK9-NEXT: ret i32 0
//
@@ -772,40 +775,43 @@ int main() {
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[B:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK11-NEXT: [[A:%.*]] = load ptr, ptr [[TMP3]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
-// CHECK11-NEXT: store ptr [[B]], ptr [[TMP2]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 24, i32 4, ptr @.omp_task_entry.)
-// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x [[STRUCT_KMP_TASK_AFFINITY_INFO_T]]], ptr [[DOTAFFS_ARR_ADDR]], i32 0, i32 0
-// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[A]], align 4
-// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP5]], i32 0
-// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[A]], align 4
-// CHECK11-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP6]], i32 1023
-// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[ARRAYIDX2]], i32 1
-// CHECK11-NEXT: [[TMP8:%.*]] = ptrtoaddr ptr [[TMP7]] to i32
-// CHECK11-NEXT: [[TMP9:%.*]] = ptrtoaddr ptr [[ARRAYIDX]] to i32
-// CHECK11-NEXT: [[TMP10:%.*]] = sub nuw i32 [[TMP8]], [[TMP9]]
-// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr [[STRUCT_KMP_TASK_AFFINITY_INFO_T]], ptr [[TMP4]], i32 0
-// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_AFFINITY_INFO_T]], ptr [[TMP11]], i32 0, i32 0
-// CHECK11-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i32
-// CHECK11-NEXT: store i32 [[TMP13]], ptr [[TMP12]], align 4
-// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_AFFINITY_INFO_T]], ptr [[TMP11]], i32 0, i32 1
-// CHECK11-NEXT: store i32 [[TMP10]], ptr [[TMP14]], align 4
-// CHECK11-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_omp_reg_task_with_affinity(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP3]], i32 1, ptr [[TMP4]])
-// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
-// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP16]], i32 0, i32 0
-// CHECK11-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 4
-// CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP18]], ptr align 4 [[AGG_CAPTURED]], i32 4, i1 false)
-// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
-// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP19]], i32 0, i32 0
-// CHECK11-NEXT: [[TMP21:%.*]] = load ptr, ptr [[A]], align 4
-// CHECK11-NEXT: store ptr [[TMP21]], ptr [[TMP20]], align 4
-// CHECK11-NEXT: [[TMP22:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP3]])
-// CHECK11-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_omp_taskwait(ptr @[[GLOB1]], i32 [[TMP0]])
+// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
+// CHECK11-NEXT: store ptr [[B]], ptr [[TMP5]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 24, i32 4, ptr @.omp_task_entry.)
+// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x [[STRUCT_KMP_TASK_AFFINITY_INFO_T]]], ptr [[DOTAFFS_ARR_ADDR]], i32 0, i32 0
+// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[A]], align 4
+// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP8]], i32 0
+// CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[A]], align 4
+// CHECK11-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP9]], i32 1023
+// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[ARRAYIDX2]], i32 1
+// CHECK11-NEXT: [[TMP11:%.*]] = ptrtoaddr ptr [[TMP10]] to i32
+// CHECK11-NEXT: [[TMP12:%.*]] = ptrtoaddr ptr [[ARRAYIDX]] to i32
+// CHECK11-NEXT: [[TMP13:%.*]] = sub nuw i32 [[TMP11]], [[TMP12]]
+// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr [[STRUCT_KMP_TASK_AFFINITY_INFO_T]], ptr [[TMP7]], i32 0
+// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_AFFINITY_INFO_T]], ptr [[TMP14]], i32 0, i32 0
+// CHECK11-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i32
+// CHECK11-NEXT: store i32 [[TMP16]], ptr [[TMP15]], align 4
+// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_AFFINITY_INFO_T]], ptr [[TMP14]], i32 0, i32 1
+// CHECK11-NEXT: store i32 [[TMP13]], ptr [[TMP17]], align 4
+// CHECK11-NEXT: [[TMP18:%.*]] = call i32 @__kmpc_omp_reg_task_with_affinity(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP6]], i32 1, ptr [[TMP7]])
+// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP6]], i32 0, i32 0
+// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP19]], i32 0, i32 0
+// CHECK11-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP20]], align 4
+// CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP21]], ptr align 4 [[AGG_CAPTURED]], i32 4, i1 false)
+// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP6]], i32 0, i32 1
+// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP22]], i32 0, i32 0
+// CHECK11-NEXT: [[TMP24:%.*]] = load ptr, ptr [[A]], align 4
+// CHECK11-NEXT: store ptr [[TMP24]], ptr [[TMP23]], align 4
+// CHECK11-NEXT: [[TMP25:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP6]])
+// CHECK11-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_omp_taskwait(ptr @[[GLOB1]], i32 [[TMP0]])
// CHECK11-NEXT: ret void
//
//
@@ -858,7 +864,7 @@ int main() {
// CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META15]]
// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META15]]
// CHECK11-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META15]]
-// CHECK11-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR3:[0-9]+]]
+// CHECK11-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR3:[0-9]+]], !inline_history [[META16:![0-9]+]]
// CHECK11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias [[META15]]
// CHECK11-NEXT: store i32 0, ptr [[I_I]], align 4, !noalias [[META15]]
// CHECK11-NEXT: br label [[FOR_COND_I:%.*]]
@@ -872,7 +878,7 @@ int main() {
// CHECK11-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds i32, ptr [[TMP14]], i32 [[TMP15]]
// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[ARRAYIDX_I]], align 4
// CHECK11-NEXT: [[MUL_I:%.*]] = mul nsw i32 2, [[TMP16]]
-// CHECK11-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP9]], align 4, !nonnull [[META16:![0-9]+]], !align [[META17:![0-9]+]]
+// CHECK11-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP9]], align 4, !nonnull [[META17:![0-9]+]], !align [[META18:![0-9]+]]
// CHECK11-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 4
// CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[I_I]], align 4, !noalias [[META15]]
// CHECK11-NEXT: [[ARRAYIDX1_I:%.*]] = getelementptr inbounds i32, ptr [[TMP18]], i32 [[TMP19]]
@@ -880,7 +886,7 @@ int main() {
// CHECK11-NEXT: [[TMP20:%.*]] = load i32, ptr [[I_I]], align 4, !noalias [[META15]]
// CHECK11-NEXT: [[INC_I:%.*]] = add nsw i32 [[TMP20]], 1
// CHECK11-NEXT: store i32 [[INC_I]], ptr [[I_I]], align 4, !noalias [[META15]]
-// CHECK11-NEXT: br label [[FOR_COND_I]], !llvm.loop [[LOOP18:![0-9]+]]
+// CHECK11-NEXT: br label [[FOR_COND_I]], !llvm.loop [[LOOP19:![0-9]+]]
// CHECK11: .omp_outlined..exit:
// CHECK11-NEXT: ret i32 0
//
diff --git a/clang/test/OpenMP/target_teams_codegen.cpp b/clang/test/OpenMP/target_teams_codegen.cpp
index 441e3634fe989..243f533ed3b7e 100644
--- a/clang/test/OpenMP/target_teams_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_codegen.cpp
@@ -4129,25 +4129,29 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 8
-// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
-// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
-// CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
+// CHECK9-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
+// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 8
-// CHECK9-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8
+// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 8
+// CHECK9-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP11]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 8
-// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP8]], i32 [[TMP9]])
-// CHECK9-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK9-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
-// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined, i64 [[TMP11]])
+// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP12]], i32 [[TMP13]])
+// CHECK9-NEXT: [[TMP14:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK9-NEXT: store i16 [[TMP14]], ptr [[AA_CASTED]], align 2
+// CHECK9-NEXT: [[TMP15:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined, i64 [[TMP15]])
// CHECK9-NEXT: ret void
//
//
@@ -4172,16 +4176,18 @@ int bar(int n){
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 8
-// CHECK9-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 8
+// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
-// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i64 [[TMP4]])
+// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK9-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 2
+// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i64 [[TMP6]])
// CHECK9-NEXT: ret void
//
//
@@ -4213,22 +4219,25 @@ int bar(int n){
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
-// CHECK9-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK9-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 8
+// CHECK9-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
-// CHECK9-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4
-// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK9-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
-// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i64 [[TMP6]], i64 [[TMP8]])
+// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
+// CHECK9-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
+// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK9-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK9-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
+// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i64 [[TMP9]], i64 [[TMP11]])
// CHECK9-NEXT: ret void
//
//
@@ -4266,23 +4275,26 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
-// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 8
-// CHECK9-NEXT: store i16 [[TMP5]], ptr [[AA]], align 2
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
+// CHECK9-NEXT: store i32 [[TMP4]], ptr [[A]], align 4
+// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8
+// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 8
+// CHECK9-NEXT: store i16 [[TMP7]], ptr [[AA]], align 2
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP8]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 1)
-// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// CHECK9-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4
-// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK9-NEXT: store i16 [[TMP8]], ptr [[AA_CASTED]], align 2
-// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.omp_outlined, i64 [[TMP7]], i64 [[TMP9]])
+// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4
+// CHECK9-NEXT: store i32 [[TMP9]], ptr [[A_CASTED]], align 4
+// CHECK9-NEXT: [[TMP10:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK9-NEXT: [[TMP11:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK9-NEXT: store i16 [[TMP11]], ptr [[AA_CASTED]], align 2
+// CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.omp_outlined, i64 [[TMP10]], i64 [[TMP12]])
// CHECK9-NEXT: ret void
//
//
@@ -4320,23 +4332,26 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
-// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 8
-// CHECK9-NEXT: store i16 [[TMP5]], ptr [[AA]], align 2
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
+// CHECK9-NEXT: store i32 [[TMP4]], ptr [[A]], align 4
+// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8
+// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 8
+// CHECK9-NEXT: store i16 [[TMP7]], ptr [[AA]], align 2
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP8]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 1)
-// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// CHECK9-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4
-// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK9-NEXT: store i16 [[TMP8]], ptr [[AA_CASTED]], align 2
-// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l130.omp_outlined, i64 [[TMP7]], i64 [[TMP9]])
+// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4
+// CHECK9-NEXT: store i32 [[TMP9]], ptr [[A_CASTED]], align 4
+// CHECK9-NEXT: [[TMP10:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK9-NEXT: [[TMP11:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK9-NEXT: store i16 [[TMP11]], ptr [[AA_CASTED]], align 2
+// CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l130.omp_outlined, i64 [[TMP10]], i64 [[TMP12]])
// CHECK9-NEXT: ret void
//
//
@@ -4374,23 +4389,26 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
-// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 8
-// CHECK9-NEXT: store i16 [[TMP5]], ptr [[AA]], align 2
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
+// CHECK9-NEXT: store i32 [[TMP4]], ptr [[A]], align 4
+// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8
+// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 8
+// CHECK9-NEXT: store i16 [[TMP7]], ptr [[AA]], align 2
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP8]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 1)
-// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// CHECK9-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4
-// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK9-NEXT: store i16 [[TMP8]], ptr [[AA_CASTED]], align 2
-// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i64 [[TMP7]], i64 [[TMP9]])
+// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4
+// CHECK9-NEXT: store i32 [[TMP9]], ptr [[A_CASTED]], align 4
+// CHECK9-NEXT: [[TMP10:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK9-NEXT: [[TMP11:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK9-NEXT: store i16 [[TMP11]], ptr [[AA_CASTED]], align 2
+// CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i64 [[TMP10]], i64 [[TMP12]])
// CHECK9-NEXT: ret void
//
//
@@ -4425,32 +4443,42 @@ int bar(int n){
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP3]], align 8
-// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8
-// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK9-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP6]], align 8
-// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK9-NEXT: [[C:%.*]] = load ptr, ptr [[TMP7]], align 8
-// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
-// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8
-// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 6
-// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
-// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 7
-// CHECK9-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP12]], align 8
-// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 8
-// CHECK9-NEXT: [[D:%.*]] = load ptr, ptr [[TMP13]], align 8
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 9
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 8
+// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
+// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP7]], align 8
+// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8
+// CHECK9-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP10]], align 8
+// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK9-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8
+// CHECK9-NEXT: [[C:%.*]] = load ptr, ptr [[TMP12]], align 8
+// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8
+// CHECK9-NEXT: [[TMP15:%.*]] = load i64, ptr [[TMP14]], align 8
+// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 6
+// CHECK9-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8
+// CHECK9-NEXT: [[TMP18:%.*]] = load i64, ptr [[TMP17]], align 8
+// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 7
+// CHECK9-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8
+// CHECK9-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP20]], align 8
+// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 8
+// CHECK9-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 8
+// CHECK9-NEXT: [[D:%.*]] = load ptr, ptr [[TMP22]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 9
+// CHECK9-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP23]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4
-// CHECK9-NEXT: store i32 [[TMP14]], ptr [[A_CASTED]], align 4
-// CHECK9-NEXT: [[TMP15:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i64 [[TMP15]], ptr [[B]], i64 [[TMP5]], ptr [[BN]], ptr [[C]], i64 [[TMP9]], i64 [[TMP11]], ptr [[CN]], ptr [[D]])
+// CHECK9-NEXT: [[TMP24:%.*]] = load i32, ptr [[A]], align 4
+// CHECK9-NEXT: store i32 [[TMP24]], ptr [[A_CASTED]], align 4
+// CHECK9-NEXT: [[TMP25:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i64 [[TMP25]], ptr [[B]], i64 [[TMP8]], ptr [[BN]], ptr [[C]], i64 [[TMP15]], i64 [[TMP18]], ptr [[CN]], ptr [[D]])
// CHECK9-NEXT: ret void
//
//
@@ -4535,16 +4563,18 @@ int bar(int n){
// CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK9-NEXT: store i32 [[TMP2]], ptr [[NN]], align 4
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK9-NEXT: store i32 [[TMP3]], ptr [[NN]], align 4
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[NN]], align 4
-// CHECK9-NEXT: store i32 [[TMP3]], ptr [[NN_CASTED]], align 4
-// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[NN_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined, i64 [[TMP4]])
+// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[NN]], align 4
+// CHECK9-NEXT: store i32 [[TMP5]], ptr [[NN_CASTED]], align 4
+// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[NN_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined, i64 [[TMP6]])
// CHECK9-NEXT: ret void
//
//
@@ -4586,16 +4616,18 @@ int bar(int n){
// CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK9-NEXT: store i32 [[TMP2]], ptr [[NN]], align 4
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK9-NEXT: store i32 [[TMP3]], ptr [[NN]], align 4
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[NN]], align 4
-// CHECK9-NEXT: store i32 [[TMP3]], ptr [[NN_CASTED]], align 4
-// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[NN_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined, i64 [[TMP4]])
+// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[NN]], align 4
+// CHECK9-NEXT: store i32 [[TMP5]], ptr [[NN_CASTED]], align 4
+// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[NN_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined, i64 [[TMP6]])
// CHECK9-NEXT: ret void
//
//
@@ -4632,12 +4664,14 @@ int bar(int n){
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[TMP1]], align 8
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l200.omp_outlined, i64 [[TMP2]])
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l200.omp_outlined, i64 [[TMP3]])
// CHECK9-NEXT: ret void
//
//
@@ -4668,30 +4702,35 @@ int bar(int n){
// CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
-// CHECK9-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK9-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 8
-// CHECK9-NEXT: store i8 [[TMP6]], ptr [[AAA]], align 1
-// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP7]], align 8
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK9-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 8
+// CHECK9-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8
+// CHECK9-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 8
+// CHECK9-NEXT: store i8 [[TMP9]], ptr [[AAA]], align 1
+// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8
+// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP11]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK9-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP12]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
-// CHECK9-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
-// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK9-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
-// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK9-NEXT: [[TMP12:%.*]] = load i8, ptr [[AAA]], align 1
-// CHECK9-NEXT: store i8 [[TMP12]], ptr [[AAA_CASTED]], align 1
-// CHECK9-NEXT: [[TMP13:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], ptr [[B]])
+// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[A]], align 4
+// CHECK9-NEXT: store i32 [[TMP13]], ptr [[A_CASTED]], align 4
+// CHECK9-NEXT: [[TMP14:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK9-NEXT: [[TMP15:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK9-NEXT: store i16 [[TMP15]], ptr [[AA_CASTED]], align 2
+// CHECK9-NEXT: [[TMP16:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK9-NEXT: [[TMP17:%.*]] = load i8, ptr [[AAA]], align 1
+// CHECK9-NEXT: store i8 [[TMP17]], ptr [[AAA_CASTED]], align 1
+// CHECK9-NEXT: [[TMP18:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227.omp_outlined, i64 [[TMP14]], i64 [[TMP16]], i64 [[TMP18]], ptr [[B]])
// CHECK9-NEXT: ret void
//
//
@@ -4740,24 +4779,30 @@ int bar(int n){
// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK9-NEXT: store i32 [[TMP3]], ptr [[B]], align 4
-// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8
-// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[TMP6]], align 8
-// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK9-NEXT: [[C:%.*]] = load ptr, ptr [[TMP8]], align 8
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
+// CHECK9-NEXT: store i32 [[TMP5]], ptr [[B]], align 4
+// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
+// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP7]], align 8
+// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8
+// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
+// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK9-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8
+// CHECK9-NEXT: [[C:%.*]] = load ptr, ptr [[TMP13]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP14]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4
-// CHECK9-NEXT: store i32 [[TMP9]], ptr [[B_CASTED]], align 4
-// CHECK9-NEXT: [[TMP10:%.*]] = load i64, ptr [[B_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245.omp_outlined, ptr [[THIS]], i64 [[TMP10]], i64 [[TMP5]], i64 [[TMP7]], ptr [[C]])
+// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[B]], align 4
+// CHECK9-NEXT: store i32 [[TMP15]], ptr [[B_CASTED]], align 4
+// CHECK9-NEXT: [[TMP16:%.*]] = load i64, ptr [[B_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245.omp_outlined, ptr [[THIS]], i64 [[TMP16]], i64 [[TMP8]], i64 [[TMP11]], ptr [[C]])
// CHECK9-NEXT: ret void
//
//
@@ -4810,24 +4855,28 @@ int bar(int n){
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
-// CHECK9-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 8
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK9-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 8
+// CHECK9-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8
+// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP8]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK9-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP9]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// CHECK9-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4
-// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK9-NEXT: store i16 [[TMP8]], ptr [[AA_CASTED]], align 2
-// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210.omp_outlined, i64 [[TMP7]], i64 [[TMP9]], ptr [[B]])
+// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
+// CHECK9-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
+// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK9-NEXT: [[TMP12:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK9-NEXT: store i16 [[TMP12]], ptr [[AA_CASTED]], align 2
+// CHECK9-NEXT: [[TMP13:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210.omp_outlined, i64 [[TMP11]], i64 [[TMP13]], ptr [[B]])
// CHECK9-NEXT: ret void
//
//
@@ -4872,25 +4921,29 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 4
-// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
-// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK11-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
+// CHECK11-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
+// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
-// CHECK11-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 4
+// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
+// CHECK11-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK11-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP11]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 4
-// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP8]], i32 [[TMP9]])
-// CHECK11-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK11-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
-// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined, i32 [[TMP11]])
+// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP12]], i32 [[TMP13]])
+// CHECK11-NEXT: [[TMP14:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK11-NEXT: store i16 [[TMP14]], ptr [[AA_CASTED]], align 2
+// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined, i32 [[TMP15]])
// CHECK11-NEXT: ret void
//
//
@@ -4915,16 +4968,18 @@ int bar(int n){
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 4
-// CHECK11-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 4
+// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
-// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i32 [[TMP4]])
+// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK11-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 2
+// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i32 [[TMP6]])
// CHECK11-NEXT: ret void
//
//
@@ -4956,22 +5011,25 @@ int bar(int n){
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
-// CHECK11-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 4
+// CHECK11-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
-// CHECK11-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK11-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
-// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i32 [[TMP6]], i32 [[TMP8]])
+// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
+// CHECK11-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK11-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
+// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i32 [[TMP9]], i32 [[TMP11]])
// CHECK11-NEXT: ret void
//
//
@@ -5009,23 +5067,26 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 4
-// CHECK11-NEXT: store i16 [[TMP5]], ptr [[AA]], align 2
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
+// CHECK11-NEXT: store i32 [[TMP4]], ptr [[A]], align 4
+// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4
+// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 4
+// CHECK11-NEXT: store i16 [[TMP7]], ptr [[AA]], align 2
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP8]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 1)
-// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// CHECK11-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK11-NEXT: store i16 [[TMP8]], ptr [[AA_CASTED]], align 2
-// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.omp_outlined, i32 [[TMP7]], i32 [[TMP9]])
+// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4
+// CHECK11-NEXT: store i32 [[TMP9]], ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP11:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK11-NEXT: store i16 [[TMP11]], ptr [[AA_CASTED]], align 2
+// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.omp_outlined, i32 [[TMP10]], i32 [[TMP12]])
// CHECK11-NEXT: ret void
//
//
@@ -5063,23 +5124,26 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 4
-// CHECK11-NEXT: store i16 [[TMP5]], ptr [[AA]], align 2
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
+// CHECK11-NEXT: store i32 [[TMP4]], ptr [[A]], align 4
+// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4
+// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 4
+// CHECK11-NEXT: store i16 [[TMP7]], ptr [[AA]], align 2
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP8]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 1)
-// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// CHECK11-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK11-NEXT: store i16 [[TMP8]], ptr [[AA_CASTED]], align 2
-// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l130.omp_outlined, i32 [[TMP7]], i32 [[TMP9]])
+// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4
+// CHECK11-NEXT: store i32 [[TMP9]], ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP11:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK11-NEXT: store i16 [[TMP11]], ptr [[AA_CASTED]], align 2
+// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l130.omp_outlined, i32 [[TMP10]], i32 [[TMP12]])
// CHECK11-NEXT: ret void
//
//
@@ -5117,23 +5181,26 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 4
-// CHECK11-NEXT: store i16 [[TMP5]], ptr [[AA]], align 2
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
+// CHECK11-NEXT: store i32 [[TMP4]], ptr [[A]], align 4
+// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4
+// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 4
+// CHECK11-NEXT: store i16 [[TMP7]], ptr [[AA]], align 2
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP8]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 1)
-// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// CHECK11-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK11-NEXT: store i16 [[TMP8]], ptr [[AA_CASTED]], align 2
-// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i32 [[TMP7]], i32 [[TMP9]])
+// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A]], align 4
+// CHECK11-NEXT: store i32 [[TMP9]], ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP11:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK11-NEXT: store i16 [[TMP11]], ptr [[AA_CASTED]], align 2
+// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i32 [[TMP10]], i32 [[TMP12]])
// CHECK11-NEXT: ret void
//
//
@@ -5168,32 +5235,42 @@ int bar(int n){
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP3]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK11-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP6]], align 4
-// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK11-NEXT: [[C:%.*]] = load ptr, ptr [[TMP7]], align 4
-// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
-// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
-// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 6
-// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
-// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 7
-// CHECK11-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP12]], align 4
-// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 8
-// CHECK11-NEXT: [[D:%.*]] = load ptr, ptr [[TMP13]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 9
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
+// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
+// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4
+// CHECK11-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP10]], align 4
+// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 4
+// CHECK11-NEXT: [[C:%.*]] = load ptr, ptr [[TMP12]], align 4
+// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK11-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 4
+// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4
+// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 6
+// CHECK11-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 4
+// CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4
+// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 7
+// CHECK11-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 4
+// CHECK11-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP20]], align 4
+// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 8
+// CHECK11-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 4
+// CHECK11-NEXT: [[D:%.*]] = load ptr, ptr [[TMP22]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 9
+// CHECK11-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP23]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4
-// CHECK11-NEXT: store i32 [[TMP14]], ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i32 [[TMP15]], ptr [[B]], i32 [[TMP5]], ptr [[BN]], ptr [[C]], i32 [[TMP9]], i32 [[TMP11]], ptr [[CN]], ptr [[D]])
+// CHECK11-NEXT: [[TMP24:%.*]] = load i32, ptr [[A]], align 4
+// CHECK11-NEXT: store i32 [[TMP24]], ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP25:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i32 [[TMP25]], ptr [[B]], i32 [[TMP8]], ptr [[BN]], ptr [[C]], i32 [[TMP15]], i32 [[TMP18]], ptr [[CN]], ptr [[D]])
// CHECK11-NEXT: ret void
//
//
@@ -5278,16 +5355,18 @@ int bar(int n){
// CHECK11-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK11-NEXT: store i32 [[TMP2]], ptr [[NN]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK11-NEXT: store i32 [[TMP3]], ptr [[NN]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[NN]], align 4
-// CHECK11-NEXT: store i32 [[TMP3]], ptr [[NN_CASTED]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[NN_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined, i32 [[TMP4]])
+// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[NN]], align 4
+// CHECK11-NEXT: store i32 [[TMP5]], ptr [[NN_CASTED]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[NN_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l172.omp_outlined, i32 [[TMP6]])
// CHECK11-NEXT: ret void
//
//
@@ -5329,16 +5408,18 @@ int bar(int n){
// CHECK11-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK11-NEXT: store i32 [[TMP2]], ptr [[NN]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK11-NEXT: store i32 [[TMP3]], ptr [[NN]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[NN]], align 4
-// CHECK11-NEXT: store i32 [[TMP3]], ptr [[NN_CASTED]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[NN_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined, i32 [[TMP4]])
+// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[NN]], align 4
+// CHECK11-NEXT: store i32 [[TMP5]], ptr [[NN_CASTED]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[NN_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l175.omp_outlined, i32 [[TMP6]])
// CHECK11-NEXT: ret void
//
//
@@ -5375,12 +5456,14 @@ int bar(int n){
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l200.omp_outlined, i32 [[TMP2]])
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l200.omp_outlined, i32 [[TMP3]])
// CHECK11-NEXT: ret void
//
//
@@ -5411,30 +5494,35 @@ int bar(int n){
// CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
-// CHECK11-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK11-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP5]], align 4
-// CHECK11-NEXT: store i8 [[TMP6]], ptr [[AAA]], align 1
-// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP7]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 4
+// CHECK11-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4
+// CHECK11-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 4
+// CHECK11-NEXT: store i8 [[TMP9]], ptr [[AAA]], align 1
+// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK11-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 4
+// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP11]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP12]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
-// CHECK11-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK11-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
-// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK11-NEXT: [[TMP12:%.*]] = load i8, ptr [[AAA]], align 1
-// CHECK11-NEXT: store i8 [[TMP12]], ptr [[AAA_CASTED]], align 1
-// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227.omp_outlined, i32 [[TMP9]], i32 [[TMP11]], i32 [[TMP13]], ptr [[B]])
+// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[A]], align 4
+// CHECK11-NEXT: store i32 [[TMP13]], ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP15:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK11-NEXT: store i16 [[TMP15]], ptr [[AA_CASTED]], align 2
+// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK11-NEXT: [[TMP17:%.*]] = load i8, ptr [[AAA]], align 1
+// CHECK11-NEXT: store i8 [[TMP17]], ptr [[AAA_CASTED]], align 1
+// CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l227.omp_outlined, i32 [[TMP14]], i32 [[TMP16]], i32 [[TMP18]], ptr [[B]])
// CHECK11-NEXT: ret void
//
//
@@ -5483,24 +5571,30 @@ int bar(int n){
// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK11-NEXT: store i32 [[TMP3]], ptr [[B]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
-// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK11-NEXT: [[C:%.*]] = load ptr, ptr [[TMP8]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: store i32 [[TMP5]], ptr [[B]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
+// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
+// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4
+// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
+// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK11-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 4
+// CHECK11-NEXT: [[C:%.*]] = load ptr, ptr [[TMP13]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK11-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP14]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4
-// CHECK11-NEXT: store i32 [[TMP9]], ptr [[B_CASTED]], align 4
-// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[B_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245.omp_outlined, ptr [[THIS]], i32 [[TMP10]], i32 [[TMP5]], i32 [[TMP7]], ptr [[C]])
+// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[B]], align 4
+// CHECK11-NEXT: store i32 [[TMP15]], ptr [[B_CASTED]], align 4
+// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[B_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l245.omp_outlined, ptr [[THIS]], i32 [[TMP16]], i32 [[TMP8]], i32 [[TMP11]], ptr [[C]])
// CHECK11-NEXT: ret void
//
//
@@ -5553,24 +5647,28 @@ int bar(int n){
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
-// CHECK11-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 4
+// CHECK11-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4
+// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP8]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP9]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// CHECK11-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK11-NEXT: store i16 [[TMP8]], ptr [[AA_CASTED]], align 2
-// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210.omp_outlined, i32 [[TMP7]], i32 [[TMP9]], ptr [[B]])
+// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
+// CHECK11-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP12:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK11-NEXT: store i16 [[TMP12]], ptr [[AA_CASTED]], align 2
+// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l210.omp_outlined, i32 [[TMP11]], i32 [[TMP13]], ptr [[B]])
// CHECK11-NEXT: ret void
//
//
diff --git a/clang/test/OpenMP/target_teams_distribute_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_codegen.cpp
index 41ce9b1ff4c35..233ddd53f489c 100644
--- a/clang/test/OpenMP/target_teams_distribute_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_codegen.cpp
@@ -827,7 +827,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META27]]
// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META27]]
// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META27]]
-// CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
+// CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]], !inline_history [[META28:![0-9]+]]
// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META27]]
// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META27]]
// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META27]]
@@ -1164,14 +1164,14 @@ int bar(int n){
// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META28:![0-9]+]], !align [[META29:![0-9]+]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META29:![0-9]+]], !align [[META30:![0-9]+]]
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META28]], !align [[META29]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META28]], !align [[META30:![0-9]+]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META29]], !align [[META30]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META29]], !align [[META31:![0-9]+]]
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META28]], !align [[META30]]
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META28]], !align [[META30]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META29]], !align [[META31]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META29]], !align [[META31]]
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
@@ -1216,14 +1216,14 @@ int bar(int n){
// CHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8
// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META28]], !align [[META29]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META29]], !align [[META30]]
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META28]], !align [[META29]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META28]], !align [[META30]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META29]], !align [[META30]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META29]], !align [[META31]]
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META28]], !align [[META30]]
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META28]], !align [[META30]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META29]], !align [[META31]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META29]], !align [[META31]]
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -1254,59 +1254,59 @@ int bar(int n){
// CHECK1: omp.dispatch.body:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31:![0-9]+]]
-// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP31]]
+// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32:![0-9]+]]
+// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP32]]
// CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]]
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP31]]
-// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP31]]
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]]
// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1
-// CHECK1-NEXT: store i32 [[ADD7]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP31]]
+// CHECK1-NEXT: store i32 [[ADD7]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]]
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2
-// CHECK1-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP31]]
+// CHECK1-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP32]]
// CHECK1-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double
// CHECK1-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00
// CHECK1-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
-// CHECK1-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP31]]
+// CHECK1-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP32]]
// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3
-// CHECK1-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP31]]
+// CHECK1-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP32]]
// CHECK1-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
// CHECK1-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
// CHECK1-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
-// CHECK1-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP31]]
+// CHECK1-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP32]]
// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1
// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2
-// CHECK1-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP31]]
+// CHECK1-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP32]]
// CHECK1-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
-// CHECK1-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP31]]
+// CHECK1-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP32]]
// CHECK1-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]]
// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 3
-// CHECK1-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP31]]
+// CHECK1-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP32]]
// CHECK1-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
-// CHECK1-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP31]]
+// CHECK1-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP32]]
// CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
-// CHECK1-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP31]]
+// CHECK1-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP32]]
// CHECK1-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
-// CHECK1-NEXT: store i64 [[ADD20]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP31]]
+// CHECK1-NEXT: store i64 [[ADD20]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP32]]
// CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
-// CHECK1-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP31]]
+// CHECK1-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP32]]
// CHECK1-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
// CHECK1-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
// CHECK1-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
-// CHECK1-NEXT: store i8 [[CONV23]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP31]]
+// CHECK1-NEXT: store i8 [[CONV23]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP32]]
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]]
+// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]
// CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
-// CHECK1-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]]
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]]
+// CHECK1-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
// CHECK1: omp.inner.for.end:
// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK1: omp.dispatch.inc:
@@ -1735,7 +1735,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META28]], !align [[META34:![0-9]+]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META29]], !align [[META35:![0-9]+]]
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8
@@ -1770,7 +1770,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META28]], !align [[META34]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META29]], !align [[META35]]
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -1850,7 +1850,7 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META28]], !align [[META29]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META29]], !align [[META30]]
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[N_CASTED]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[N_CASTED]], align 8
@@ -1895,7 +1895,7 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META28]], !align [[META29]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META29]], !align [[META30]]
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
@@ -2000,7 +2000,7 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META28]], !align [[META29]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META29]], !align [[META30]]
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
@@ -2031,7 +2031,7 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META28]], !align [[META29]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META29]], !align [[META30]]
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -2623,7 +2623,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META28]]
// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META28]]
// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META28]]
-// CHECK3-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
+// CHECK3-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]], !inline_history [[META29:![0-9]+]]
// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias [[META28]]
// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias [[META28]]
// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias [[META28]]
@@ -2960,14 +2960,14 @@ int bar(int n){
// CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META29:![0-9]+]], !align [[META30:![0-9]+]]
+// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META30:![0-9]+]], !align [[META31:![0-9]+]]
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
-// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4, !nonnull [[META29]], !align [[META30]]
-// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META29]], !align [[META30]]
+// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4, !nonnull [[META30]], !align [[META31]]
+// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META30]], !align [[META31]]
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
-// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4, !nonnull [[META29]], !align [[META30]]
-// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META29]], !align [[META30]]
+// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4, !nonnull [[META30]], !align [[META31]]
+// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META30]], !align [[META31]]
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
@@ -3012,14 +3012,14 @@ int bar(int n){
// CHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4
// CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
-// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META29]], !align [[META30]]
+// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META30]], !align [[META31]]
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
-// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4, !nonnull [[META29]], !align [[META30]]
-// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META29]], !align [[META30]]
+// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4, !nonnull [[META30]], !align [[META31]]
+// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META30]], !align [[META31]]
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
-// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4, !nonnull [[META29]], !align [[META30]]
-// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META29]], !align [[META30]]
+// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4, !nonnull [[META30]], !align [[META31]]
+// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META30]], !align [[META31]]
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -3050,59 +3050,59 @@ int bar(int n){
// CHECK3: omp.dispatch.body:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK3: omp.inner.for.cond:
-// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31:![0-9]+]]
-// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP31]]
+// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32:![0-9]+]]
+// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP32]]
// CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
// CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK3: omp.inner.for.body:
-// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]]
+// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP31]]
-// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP31]]
+// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]]
// CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1
-// CHECK3-NEXT: store i32 [[ADD7]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP31]]
+// CHECK3-NEXT: store i32 [[ADD7]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]]
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2
-// CHECK3-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP31]]
+// CHECK3-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP32]]
// CHECK3-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double
// CHECK3-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00
// CHECK3-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
-// CHECK3-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP31]]
+// CHECK3-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP32]]
// CHECK3-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3
-// CHECK3-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP31]]
+// CHECK3-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP32]]
// CHECK3-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
// CHECK3-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
// CHECK3-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
-// CHECK3-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP31]]
+// CHECK3-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP32]]
// CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1
// CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2
-// CHECK3-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP31]]
+// CHECK3-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP32]]
// CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
-// CHECK3-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP31]]
+// CHECK3-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP32]]
// CHECK3-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
// CHECK3-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]]
// CHECK3-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 3
-// CHECK3-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP31]]
+// CHECK3-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP32]]
// CHECK3-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
-// CHECK3-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP31]]
+// CHECK3-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP32]]
// CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
-// CHECK3-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP31]]
+// CHECK3-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP32]]
// CHECK3-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
-// CHECK3-NEXT: store i64 [[ADD20]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP31]]
+// CHECK3-NEXT: store i64 [[ADD20]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP32]]
// CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
-// CHECK3-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP31]]
+// CHECK3-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP32]]
// CHECK3-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
// CHECK3-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
// CHECK3-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
-// CHECK3-NEXT: store i8 [[CONV23]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP31]]
+// CHECK3-NEXT: store i8 [[CONV23]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP32]]
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK3: omp.inner.for.inc:
-// CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]]
+// CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]
// CHECK3-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
-// CHECK3-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]]
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]]
+// CHECK3-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
// CHECK3: omp.inner.for.end:
// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK3: omp.dispatch.inc:
@@ -3531,7 +3531,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
-// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META29]], !align [[META34:![0-9]+]]
+// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META30]], !align [[META35:![0-9]+]]
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
@@ -3566,7 +3566,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
-// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META29]], !align [[META34]]
+// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META30]], !align [[META35]]
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -3646,7 +3646,7 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META29]], !align [[META30]]
+// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META30]], !align [[META31]]
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[N_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_CASTED]], align 4
@@ -3691,7 +3691,7 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
// CHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
-// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META29]], !align [[META30]]
+// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META30]], !align [[META31]]
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
@@ -3796,7 +3796,7 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META29]], !align [[META30]]
+// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META30]], !align [[META31]]
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
@@ -3827,7 +3827,7 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
-// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META29]], !align [[META30]]
+// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META30]], !align [[META31]]
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -3898,25 +3898,29 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 8
-// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
-// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
-// CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
+// CHECK9-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
+// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 8
-// CHECK9-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8
+// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 8
+// CHECK9-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP11]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 8
-// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP8]], i32 [[TMP9]])
-// CHECK9-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK9-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
-// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined, i64 [[TMP11]])
+// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP12]], i32 [[TMP13]])
+// CHECK9-NEXT: [[TMP14:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK9-NEXT: store i16 [[TMP14]], ptr [[AA_CASTED]], align 2
+// CHECK9-NEXT: [[TMP15:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined, i64 [[TMP15]])
// CHECK9-NEXT: ret void
//
//
@@ -3991,16 +3995,18 @@ int bar(int n){
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 8
-// CHECK9-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 8
+// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
-// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.omp_outlined, i64 [[TMP4]])
+// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK9-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 2
+// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.omp_outlined, i64 [[TMP6]])
// CHECK9-NEXT: ret void
//
//
@@ -4082,22 +4088,25 @@ int bar(int n){
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
-// CHECK9-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK9-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 8
+// CHECK9-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
-// CHECK9-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4
-// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK9-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
-// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.omp_outlined, i64 [[TMP6]], i64 [[TMP8]])
+// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
+// CHECK9-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
+// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK9-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK9-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
+// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.omp_outlined, i64 [[TMP9]], i64 [[TMP11]])
// CHECK9-NEXT: ret void
//
//
@@ -4184,38 +4193,49 @@ int bar(int n){
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP3]], align 8
-// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8
-// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK9-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP6]], align 8
-// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK9-NEXT: [[C:%.*]] = load ptr, ptr [[TMP7]], align 8
-// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
-// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8
-// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 6
-// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
-// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 7
-// CHECK9-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP12]], align 8
-// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 8
-// CHECK9-NEXT: [[D:%.*]] = load ptr, ptr [[TMP13]], align 8
-// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 9
-// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 8
-// CHECK9-NEXT: store i32 [[TMP15]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 10
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 8
+// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
+// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP7]], align 8
+// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8
+// CHECK9-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP10]], align 8
+// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK9-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8
+// CHECK9-NEXT: [[C:%.*]] = load ptr, ptr [[TMP12]], align 8
+// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8
+// CHECK9-NEXT: [[TMP15:%.*]] = load i64, ptr [[TMP14]], align 8
+// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 6
+// CHECK9-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8
+// CHECK9-NEXT: [[TMP18:%.*]] = load i64, ptr [[TMP17]], align 8
+// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 7
+// CHECK9-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8
+// CHECK9-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP20]], align 8
+// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 8
+// CHECK9-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 8
+// CHECK9-NEXT: [[D:%.*]] = load ptr, ptr [[TMP22]], align 8
+// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 9
+// CHECK9-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 8
+// CHECK9-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 8
+// CHECK9-NEXT: store i32 [[TMP25]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 10
+// CHECK9-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP26]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[A]], align 4
-// CHECK9-NEXT: store i32 [[TMP16]], ptr [[A_CASTED]], align 4
-// CHECK9-NEXT: [[TMP17:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: store i32 [[TMP18]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
-// CHECK9-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.omp_outlined, i64 [[TMP17]], ptr [[B]], i64 [[TMP5]], ptr [[BN]], ptr [[C]], i64 [[TMP9]], i64 [[TMP11]], ptr [[CN]], ptr [[D]], i64 [[TMP19]])
+// CHECK9-NEXT: [[TMP27:%.*]] = load i32, ptr [[A]], align 4
+// CHECK9-NEXT: store i32 [[TMP27]], ptr [[A_CASTED]], align 4
+// CHECK9-NEXT: [[TMP28:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK9-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: store i32 [[TMP29]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
+// CHECK9-NEXT: [[TMP30:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.omp_outlined, i64 [[TMP28]], ptr [[B]], i64 [[TMP8]], ptr [[BN]], ptr [[C]], i64 [[TMP15]], i64 [[TMP18]], ptr [[CN]], ptr [[D]], i64 [[TMP30]])
// CHECK9-NEXT: ret void
//
//
@@ -4376,36 +4396,42 @@ int bar(int n){
// CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK9-NEXT: store i32 [[TMP2]], ptr [[N]], align 4
-// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
-// CHECK9-NEXT: store i32 [[TMP4]], ptr [[A]], align 4
-// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK9-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 8
-// CHECK9-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
-// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK9-NEXT: [[TMP8:%.*]] = load i8, ptr [[TMP7]], align 8
-// CHECK9-NEXT: store i8 [[TMP8]], ptr [[AAA]], align 1
-// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP9]], align 8
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK9-NEXT: store i32 [[TMP3]], ptr [[N]], align 4
+// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 8
+// CHECK9-NEXT: store i32 [[TMP6]], ptr [[A]], align 4
+// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8
+// CHECK9-NEXT: [[TMP9:%.*]] = load i16, ptr [[TMP8]], align 8
+// CHECK9-NEXT: store i16 [[TMP9]], ptr [[AA]], align 2
+// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8
+// CHECK9-NEXT: [[TMP12:%.*]] = load i8, ptr [[TMP11]], align 8
+// CHECK9-NEXT: store i8 [[TMP12]], ptr [[AAA]], align 1
+// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8
+// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP14]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK9-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP15]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[N]], align 4
-// CHECK9-NEXT: store i32 [[TMP10]], ptr [[N_CASTED]], align 4
-// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[N_CASTED]], align 8
-// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[A]], align 4
-// CHECK9-NEXT: store i32 [[TMP12]], ptr [[A_CASTED]], align 4
-// CHECK9-NEXT: [[TMP13:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP14:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK9-NEXT: store i16 [[TMP14]], ptr [[AA_CASTED]], align 2
-// CHECK9-NEXT: [[TMP15:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK9-NEXT: [[TMP16:%.*]] = load i8, ptr [[AAA]], align 1
-// CHECK9-NEXT: store i8 [[TMP16]], ptr [[AAA_CASTED]], align 1
-// CHECK9-NEXT: [[TMP17:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.omp_outlined, i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]], ptr [[B]])
+// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[N]], align 4
+// CHECK9-NEXT: store i32 [[TMP16]], ptr [[N_CASTED]], align 4
+// CHECK9-NEXT: [[TMP17:%.*]] = load i64, ptr [[N_CASTED]], align 8
+// CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[A]], align 4
+// CHECK9-NEXT: store i32 [[TMP18]], ptr [[A_CASTED]], align 4
+// CHECK9-NEXT: [[TMP19:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK9-NEXT: [[TMP20:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK9-NEXT: store i16 [[TMP20]], ptr [[AA_CASTED]], align 2
+// CHECK9-NEXT: [[TMP21:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK9-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA]], align 1
+// CHECK9-NEXT: store i8 [[TMP22]], ptr [[AAA_CASTED]], align 1
+// CHECK9-NEXT: [[TMP23:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.omp_outlined, i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP23]], ptr [[B]])
// CHECK9-NEXT: ret void
//
//
@@ -4538,24 +4564,30 @@ int bar(int n){
// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK9-NEXT: store i32 [[TMP3]], ptr [[B]], align 4
-// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8
-// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[TMP6]], align 8
-// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK9-NEXT: [[C:%.*]] = load ptr, ptr [[TMP8]], align 8
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
+// CHECK9-NEXT: store i32 [[TMP5]], ptr [[B]], align 4
+// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
+// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP7]], align 8
+// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8
+// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
+// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK9-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8
+// CHECK9-NEXT: [[C:%.*]] = load ptr, ptr [[TMP13]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP14]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4
-// CHECK9-NEXT: store i32 [[TMP9]], ptr [[B_CASTED]], align 4
-// CHECK9-NEXT: [[TMP10:%.*]] = load i64, ptr [[B_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.omp_outlined, ptr [[THIS]], i64 [[TMP10]], i64 [[TMP5]], i64 [[TMP7]], ptr [[C]])
+// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[B]], align 4
+// CHECK9-NEXT: store i32 [[TMP15]], ptr [[B_CASTED]], align 4
+// CHECK9-NEXT: [[TMP16:%.*]] = load i64, ptr [[B_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.omp_outlined, ptr [[THIS]], i64 [[TMP16]], i64 [[TMP8]], i64 [[TMP11]], ptr [[C]])
// CHECK9-NEXT: ret void
//
//
@@ -4658,24 +4690,28 @@ int bar(int n){
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK9-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
-// CHECK9-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 8
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK9-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 8
+// CHECK9-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8
+// CHECK9-NEXT: [[B:%.*]] = load ptr, ptr [[TMP8]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK9-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP9]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// CHECK9-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4
-// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK9-NEXT: store i16 [[TMP8]], ptr [[AA_CASTED]], align 2
-// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.omp_outlined, i64 [[TMP7]], i64 [[TMP9]], ptr [[B]])
+// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
+// CHECK9-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
+// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK9-NEXT: [[TMP12:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK9-NEXT: store i16 [[TMP12]], ptr [[AA_CASTED]], align 2
+// CHECK9-NEXT: [[TMP13:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.omp_outlined, i64 [[TMP11]], i64 [[TMP13]], ptr [[B]])
// CHECK9-NEXT: ret void
//
//
@@ -4770,25 +4806,29 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 4
-// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
-// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK11-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
+// CHECK11-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
+// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
-// CHECK11-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 4
+// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
+// CHECK11-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK11-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP11]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 4
-// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP8]], i32 [[TMP9]])
-// CHECK11-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK11-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
-// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined, i32 [[TMP11]])
+// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP12]], i32 [[TMP13]])
+// CHECK11-NEXT: [[TMP14:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK11-NEXT: store i16 [[TMP14]], ptr [[AA_CASTED]], align 2
+// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined, i32 [[TMP15]])
// CHECK11-NEXT: ret void
//
//
@@ -4863,16 +4903,18 @@ int bar(int n){
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 4
-// CHECK11-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 4
+// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
-// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.omp_outlined, i32 [[TMP4]])
+// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK11-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 2
+// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.omp_outlined, i32 [[TMP6]])
// CHECK11-NEXT: ret void
//
//
@@ -4954,22 +4996,25 @@ int bar(int n){
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
-// CHECK11-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 4
+// CHECK11-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
-// CHECK11-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK11-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
-// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.omp_outlined, i32 [[TMP6]], i32 [[TMP8]])
+// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
+// CHECK11-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK11-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
+// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.omp_outlined, i32 [[TMP9]], i32 [[TMP11]])
// CHECK11-NEXT: ret void
//
//
@@ -5056,38 +5101,49 @@ int bar(int n){
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP3]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK11-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP6]], align 4
-// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK11-NEXT: [[C:%.*]] = load ptr, ptr [[TMP7]], align 4
-// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
-// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
-// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 6
-// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
-// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 7
-// CHECK11-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP12]], align 4
-// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 8
-// CHECK11-NEXT: [[D:%.*]] = load ptr, ptr [[TMP13]], align 4
-// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 9
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
+// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
+// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4
+// CHECK11-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP10]], align 4
+// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 4
+// CHECK11-NEXT: [[C:%.*]] = load ptr, ptr [[TMP12]], align 4
+// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK11-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 4
// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4
-// CHECK11-NEXT: store i32 [[TMP15]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 10
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 6
+// CHECK11-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 4
+// CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4
+// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 7
+// CHECK11-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 4
+// CHECK11-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP20]], align 4
+// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 8
+// CHECK11-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 4
+// CHECK11-NEXT: [[D:%.*]] = load ptr, ptr [[TMP22]], align 4
+// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 9
+// CHECK11-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 4
+// CHECK11-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 4
+// CHECK11-NEXT: store i32 [[TMP25]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 10
+// CHECK11-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP26]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[A]], align 4
-// CHECK11-NEXT: store i32 [[TMP16]], ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: store i32 [[TMP18]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
-// CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.omp_outlined, i32 [[TMP17]], ptr [[B]], i32 [[TMP5]], ptr [[BN]], ptr [[C]], i32 [[TMP9]], i32 [[TMP11]], ptr [[CN]], ptr [[D]], i32 [[TMP19]])
+// CHECK11-NEXT: [[TMP27:%.*]] = load i32, ptr [[A]], align 4
+// CHECK11-NEXT: store i32 [[TMP27]], ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP28:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: store i32 [[TMP29]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
+// CHECK11-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.omp_outlined, i32 [[TMP28]], ptr [[B]], i32 [[TMP8]], ptr [[BN]], ptr [[C]], i32 [[TMP15]], i32 [[TMP18]], ptr [[CN]], ptr [[D]], i32 [[TMP30]])
// CHECK11-NEXT: ret void
//
//
@@ -5248,36 +5304,42 @@ int bar(int n){
// CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK11-NEXT: store i32 [[TMP2]], ptr [[N]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-// CHECK11-NEXT: store i32 [[TMP4]], ptr [[A]], align 4
-// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK11-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 4
-// CHECK11-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
-// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK11-NEXT: [[TMP8:%.*]] = load i8, ptr [[TMP7]], align 4
-// CHECK11-NEXT: store i8 [[TMP8]], ptr [[AAA]], align 1
-// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP9]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK11-NEXT: store i32 [[TMP3]], ptr [[N]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
+// CHECK11-NEXT: store i32 [[TMP6]], ptr [[A]], align 4
+// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4
+// CHECK11-NEXT: [[TMP9:%.*]] = load i16, ptr [[TMP8]], align 4
+// CHECK11-NEXT: store i16 [[TMP9]], ptr [[AA]], align 2
+// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK11-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 4
+// CHECK11-NEXT: [[TMP12:%.*]] = load i8, ptr [[TMP11]], align 4
+// CHECK11-NEXT: store i8 [[TMP12]], ptr [[AAA]], align 1
+// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK11-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 4
+// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP14]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK11-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP15]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[N]], align 4
-// CHECK11-NEXT: store i32 [[TMP10]], ptr [[N_CASTED]], align 4
-// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[N_CASTED]], align 4
-// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[A]], align 4
-// CHECK11-NEXT: store i32 [[TMP12]], ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP14:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK11-NEXT: store i16 [[TMP14]], ptr [[AA_CASTED]], align 2
-// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK11-NEXT: [[TMP16:%.*]] = load i8, ptr [[AAA]], align 1
-// CHECK11-NEXT: store i8 [[TMP16]], ptr [[AAA_CASTED]], align 1
-// CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.omp_outlined, i32 [[TMP11]], i32 [[TMP13]], i32 [[TMP15]], i32 [[TMP17]], ptr [[B]])
+// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[N]], align 4
+// CHECK11-NEXT: store i32 [[TMP16]], ptr [[N_CASTED]], align 4
+// CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[N_CASTED]], align 4
+// CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[A]], align 4
+// CHECK11-NEXT: store i32 [[TMP18]], ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP20:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK11-NEXT: store i16 [[TMP20]], ptr [[AA_CASTED]], align 2
+// CHECK11-NEXT: [[TMP21:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK11-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA]], align 1
+// CHECK11-NEXT: store i8 [[TMP22]], ptr [[AAA_CASTED]], align 1
+// CHECK11-NEXT: [[TMP23:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.omp_outlined, i32 [[TMP17]], i32 [[TMP19]], i32 [[TMP21]], i32 [[TMP23]], ptr [[B]])
// CHECK11-NEXT: ret void
//
//
@@ -5410,24 +5472,30 @@ int bar(int n){
// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK11-NEXT: store i32 [[TMP3]], ptr [[B]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
-// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK11-NEXT: [[C:%.*]] = load ptr, ptr [[TMP8]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: store i32 [[TMP5]], ptr [[B]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
+// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
+// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4
+// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
+// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK11-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 4
+// CHECK11-NEXT: [[C:%.*]] = load ptr, ptr [[TMP13]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK11-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP14]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4
-// CHECK11-NEXT: store i32 [[TMP9]], ptr [[B_CASTED]], align 4
-// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[B_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.omp_outlined, ptr [[THIS]], i32 [[TMP10]], i32 [[TMP5]], i32 [[TMP7]], ptr [[C]])
+// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[B]], align 4
+// CHECK11-NEXT: store i32 [[TMP15]], ptr [[B_CASTED]], align 4
+// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[B_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.omp_outlined, ptr [[THIS]], i32 [[TMP16]], i32 [[TMP8]], i32 [[TMP11]], ptr [[C]])
// CHECK11-NEXT: ret void
//
//
@@ -5530,24 +5598,28 @@ int bar(int n){
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK11-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
-// CHECK11-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 4
+// CHECK11-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4
+// CHECK11-NEXT: [[B:%.*]] = load ptr, ptr [[TMP8]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP9]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// CHECK11-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK11-NEXT: store i16 [[TMP8]], ptr [[AA_CASTED]], align 2
-// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.omp_outlined, i32 [[TMP7]], i32 [[TMP9]], ptr [[B]])
+// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
+// CHECK11-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP12:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK11-NEXT: store i16 [[TMP12]], ptr [[AA_CASTED]], align 2
+// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.omp_outlined, i32 [[TMP11]], i32 [[TMP13]], ptr [[B]])
// CHECK11-NEXT: ret void
//
//
diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp
index 6f239e97533fb..a1c76dff16e3d 100644
--- a/clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp
@@ -1887,27 +1887,32 @@ int target_teams_fun(int *g){
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]])
// CHECK10-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK10-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK10-NEXT: store i32 [[TMP3]], ptr [[N]], align 4
-// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK10-NEXT: [[A:%.*]] = load ptr, ptr [[TMP4]], align 8
-// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
-// CHECK10-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 8
-// CHECK10-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
-// CHECK10-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 8
-// CHECK10-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 4
-// CHECK10-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK10-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
+// CHECK10-NEXT: store i32 [[TMP4]], ptr [[N]], align 4
+// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK10-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8
+// CHECK10-NEXT: [[A:%.*]] = load ptr, ptr [[TMP6]], align 8
+// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK10-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8
+// CHECK10-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 8
+// CHECK10-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK10-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8
+// CHECK10-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 8
+// CHECK10-NEXT: store i32 [[TMP12]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 4
+// CHECK10-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK10-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP13]], align 8
// CHECK10-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 8
-// CHECK10-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK10-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK10-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP9]], i32 [[TMP10]])
-// CHECK10-NEXT: [[TMP11:%.*]] = load i32, ptr [[N]], align 4
-// CHECK10-NEXT: store i32 [[TMP11]], ptr [[N_CASTED]], align 4
-// CHECK10-NEXT: [[TMP12:%.*]] = load i64, ptr [[N_CASTED]], align 8
-// CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51.omp_outlined, i64 [[TMP12]], ptr [[A]])
+// CHECK10-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK10-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK10-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP14]], i32 [[TMP15]])
+// CHECK10-NEXT: [[TMP16:%.*]] = load i32, ptr [[N]], align 4
+// CHECK10-NEXT: store i32 [[TMP16]], ptr [[N_CASTED]], align 4
+// CHECK10-NEXT: [[TMP17:%.*]] = load i64, ptr [[N_CASTED]], align 8
+// CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51.omp_outlined, i64 [[TMP17]], ptr [[A]])
// CHECK10-NEXT: ret void
//
//
@@ -2127,20 +2132,24 @@ int target_teams_fun(int *g){
// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK10-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK10-NEXT: store i32 [[TMP2]], ptr [[N]], align 4
-// CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK10-NEXT: [[A:%.*]] = load ptr, ptr [[TMP3]], align 8
-// CHECK10-NEXT: [[G:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK10-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK10-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK10-NEXT: store i32 [[TMP3]], ptr [[N]], align 4
+// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK10-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK10-NEXT: [[A:%.*]] = load ptr, ptr [[TMP5]], align 8
+// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK10-NEXT: [[G:%.*]] = load ptr, ptr [[TMP6]], align 8
+// CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK10-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK10-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 8
// CHECK10-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK10-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4
-// CHECK10-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4
-// CHECK10-NEXT: [[TMP5:%.*]] = load i64, ptr [[N_CASTED]], align 8
-// CHECK10-NEXT: [[TMP6:%.*]] = load ptr, ptr [[G]], align 8
-// CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58.omp_outlined, i64 [[TMP5]], ptr [[A]], ptr [[TMP6]])
+// CHECK10-NEXT: [[TMP8:%.*]] = load i32, ptr [[N]], align 4
+// CHECK10-NEXT: store i32 [[TMP8]], ptr [[N_CASTED]], align 4
+// CHECK10-NEXT: [[TMP9:%.*]] = load i64, ptr [[N_CASTED]], align 8
+// CHECK10-NEXT: [[TMP10:%.*]] = load ptr, ptr [[G]], align 8
+// CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58.omp_outlined, i64 [[TMP9]], ptr [[A]], ptr [[TMP10]])
// CHECK10-NEXT: ret void
//
//
@@ -2356,27 +2365,32 @@ int target_teams_fun(int *g){
// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]])
// CHECK12-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK12-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK12-NEXT: store i32 [[TMP3]], ptr [[N]], align 4
-// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK12-NEXT: [[A:%.*]] = load ptr, ptr [[TMP4]], align 4
-// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
-// CHECK12-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
-// CHECK12-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
-// CHECK12-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
-// CHECK12-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 4
-// CHECK12-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK12-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK12-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
+// CHECK12-NEXT: store i32 [[TMP4]], ptr [[N]], align 4
+// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK12-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4
+// CHECK12-NEXT: [[A:%.*]] = load ptr, ptr [[TMP6]], align 4
+// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK12-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4
+// CHECK12-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
+// CHECK12-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK12-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 4
+// CHECK12-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4
+// CHECK12-NEXT: store i32 [[TMP12]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 4
+// CHECK12-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK12-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP13]], align 4
// CHECK12-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 4
-// CHECK12-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK12-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK12-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP9]], i32 [[TMP10]])
-// CHECK12-NEXT: [[TMP11:%.*]] = load i32, ptr [[N]], align 4
-// CHECK12-NEXT: store i32 [[TMP11]], ptr [[N_CASTED]], align 4
-// CHECK12-NEXT: [[TMP12:%.*]] = load i32, ptr [[N_CASTED]], align 4
-// CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51.omp_outlined, i32 [[TMP12]], ptr [[A]])
+// CHECK12-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK12-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK12-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP14]], i32 [[TMP15]])
+// CHECK12-NEXT: [[TMP16:%.*]] = load i32, ptr [[N]], align 4
+// CHECK12-NEXT: store i32 [[TMP16]], ptr [[N_CASTED]], align 4
+// CHECK12-NEXT: [[TMP17:%.*]] = load i32, ptr [[N_CASTED]], align 4
+// CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51.omp_outlined, i32 [[TMP17]], ptr [[A]])
// CHECK12-NEXT: ret void
//
//
@@ -2591,20 +2605,24 @@ int target_teams_fun(int *g){
// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
// CHECK12-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK12-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK12-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK12-NEXT: store i32 [[TMP2]], ptr [[N]], align 4
-// CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK12-NEXT: [[A:%.*]] = load ptr, ptr [[TMP3]], align 4
-// CHECK12-NEXT: [[G:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK12-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK12-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK12-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK12-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK12-NEXT: store i32 [[TMP3]], ptr [[N]], align 4
+// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK12-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK12-NEXT: [[A:%.*]] = load ptr, ptr [[TMP5]], align 4
+// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK12-NEXT: [[G:%.*]] = load ptr, ptr [[TMP6]], align 4
+// CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK12-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK12-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 4
// CHECK12-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK12-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4
-// CHECK12-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4
-// CHECK12-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4
-// CHECK12-NEXT: [[TMP6:%.*]] = load ptr, ptr [[G]], align 4
-// CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58.omp_outlined, i32 [[TMP5]], ptr [[A]], ptr [[TMP6]])
+// CHECK12-NEXT: [[TMP8:%.*]] = load i32, ptr [[N]], align 4
+// CHECK12-NEXT: store i32 [[TMP8]], ptr [[N_CASTED]], align 4
+// CHECK12-NEXT: [[TMP9:%.*]] = load i32, ptr [[N_CASTED]], align 4
+// CHECK12-NEXT: [[TMP10:%.*]] = load ptr, ptr [[G]], align 4
+// CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58.omp_outlined, i32 [[TMP9]], ptr [[A]], ptr [[TMP10]])
// CHECK12-NEXT: ret void
//
//
diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp
index 29941c9458feb..1048608dfba6a 100644
--- a/clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp
@@ -2687,28 +2687,34 @@ int main() {
// CHECK13-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
// CHECK13-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK13-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK13-NEXT: [[VEC:%.*]] = load ptr, ptr [[TMP1]], align 8
-// CHECK13-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK13-NEXT: store i32 [[TMP3]], ptr [[T_VAR]], align 4
-// CHECK13-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK13-NEXT: [[S_ARR:%.*]] = load ptr, ptr [[TMP4]], align 8
-// CHECK13-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK13-NEXT: [[VAR:%.*]] = load ptr, ptr [[TMP5]], align 8
-// CHECK13-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 8
-// CHECK13-NEXT: store i32 [[TMP7]], ptr [[SIVAR]], align 4
-// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
-// CHECK13-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK13-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK13-NEXT: [[VEC:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK13-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK13-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
+// CHECK13-NEXT: store i32 [[TMP5]], ptr [[T_VAR]], align 4
+// CHECK13-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK13-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
+// CHECK13-NEXT: [[S_ARR:%.*]] = load ptr, ptr [[TMP7]], align 8
+// CHECK13-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK13-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8
+// CHECK13-NEXT: [[VAR:%.*]] = load ptr, ptr [[TMP9]], align 8
+// CHECK13-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK13-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8
+// CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 8
+// CHECK13-NEXT: store i32 [[TMP12]], ptr [[SIVAR]], align 4
+// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK13-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK13-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP13]], align 8
// CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4
-// CHECK13-NEXT: store i32 [[TMP8]], ptr [[T_VAR_CASTED]], align 4
-// CHECK13-NEXT: [[TMP9:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
-// CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[SIVAR]], align 4
-// CHECK13-NEXT: store i32 [[TMP10]], ptr [[SIVAR_CASTED]], align 4
-// CHECK13-NEXT: [[TMP11:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8
-// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined, ptr [[VEC]], i64 [[TMP9]], ptr [[S_ARR]], ptr [[VAR]], i64 [[TMP11]])
+// CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR]], align 4
+// CHECK13-NEXT: store i32 [[TMP14]], ptr [[T_VAR_CASTED]], align 4
+// CHECK13-NEXT: [[TMP15:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
+// CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR]], align 4
+// CHECK13-NEXT: store i32 [[TMP16]], ptr [[SIVAR_CASTED]], align 4
+// CHECK13-NEXT: [[TMP17:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8
+// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined, ptr [[VEC]], i64 [[TMP15]], ptr [[S_ARR]], ptr [[VAR]], i64 [[TMP17]])
// CHECK13-NEXT: ret void
//
//
@@ -3022,24 +3028,29 @@ int main() {
// CHECK13-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
// CHECK13-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK13-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK13-NEXT: [[VEC:%.*]] = load ptr, ptr [[TMP1]], align 8
-// CHECK13-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK13-NEXT: store i32 [[TMP3]], ptr [[T_VAR]], align 4
-// CHECK13-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK13-NEXT: [[S_ARR:%.*]] = load ptr, ptr [[TMP4]], align 8
-// CHECK13-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK13-NEXT: [[VAR:%.*]] = load ptr, ptr [[TMP5]], align 8
-// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK13-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK13-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK13-NEXT: [[VEC:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK13-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK13-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
+// CHECK13-NEXT: store i32 [[TMP5]], ptr [[T_VAR]], align 4
+// CHECK13-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK13-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
+// CHECK13-NEXT: [[S_ARR:%.*]] = load ptr, ptr [[TMP7]], align 8
+// CHECK13-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK13-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8
+// CHECK13-NEXT: [[VAR:%.*]] = load ptr, ptr [[TMP9]], align 8
+// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK13-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK13-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP10]], align 8
// CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK13-NEXT: store ptr [[VAR]], ptr [[TMP]], align 8
-// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[T_VAR]], align 4
-// CHECK13-NEXT: store i32 [[TMP6]], ptr [[T_VAR_CASTED]], align 4
-// CHECK13-NEXT: [[TMP7:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
-// CHECK13-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]
-// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, ptr [[VEC]], i64 [[TMP7]], ptr [[S_ARR]], ptr [[TMP8]])
+// CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[T_VAR]], align 4
+// CHECK13-NEXT: store i32 [[TMP11]], ptr [[T_VAR_CASTED]], align 4
+// CHECK13-NEXT: [[TMP12:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
+// CHECK13-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]
+// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, ptr [[VEC]], i64 [[TMP12]], ptr [[S_ARR]], ptr [[TMP13]])
// CHECK13-NEXT: ret void
//
//
@@ -3417,28 +3428,34 @@ int main() {
// CHECK15-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
// CHECK15-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK15-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK15-NEXT: [[VEC:%.*]] = load ptr, ptr [[TMP1]], align 4
-// CHECK15-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK15-NEXT: store i32 [[TMP3]], ptr [[T_VAR]], align 4
-// CHECK15-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK15-NEXT: [[S_ARR:%.*]] = load ptr, ptr [[TMP4]], align 4
-// CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK15-NEXT: [[VAR:%.*]] = load ptr, ptr [[TMP5]], align 4
-// CHECK15-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
-// CHECK15-NEXT: store i32 [[TMP7]], ptr [[SIVAR]], align 4
-// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
-// CHECK15-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK15-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK15-NEXT: [[VEC:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK15-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK15-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4
+// CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
+// CHECK15-NEXT: store i32 [[TMP5]], ptr [[T_VAR]], align 4
+// CHECK15-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK15-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
+// CHECK15-NEXT: [[S_ARR:%.*]] = load ptr, ptr [[TMP7]], align 4
+// CHECK15-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK15-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 4
+// CHECK15-NEXT: [[VAR:%.*]] = load ptr, ptr [[TMP9]], align 4
+// CHECK15-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK15-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 4
+// CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4
+// CHECK15-NEXT: store i32 [[TMP12]], ptr [[SIVAR]], align 4
+// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK15-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK15-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP13]], align 4
// CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4
-// CHECK15-NEXT: store i32 [[TMP8]], ptr [[T_VAR_CASTED]], align 4
-// CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
-// CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[SIVAR]], align 4
-// CHECK15-NEXT: store i32 [[TMP10]], ptr [[SIVAR_CASTED]], align 4
-// CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4
-// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined, ptr [[VEC]], i32 [[TMP9]], ptr [[S_ARR]], ptr [[VAR]], i32 [[TMP11]])
+// CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR]], align 4
+// CHECK15-NEXT: store i32 [[TMP14]], ptr [[T_VAR_CASTED]], align 4
+// CHECK15-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
+// CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR]], align 4
+// CHECK15-NEXT: store i32 [[TMP16]], ptr [[SIVAR_CASTED]], align 4
+// CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4
+// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined, ptr [[VEC]], i32 [[TMP15]], ptr [[S_ARR]], ptr [[VAR]], i32 [[TMP17]])
// CHECK15-NEXT: ret void
//
//
@@ -3746,24 +3763,29 @@ int main() {
// CHECK15-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
// CHECK15-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK15-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK15-NEXT: [[VEC:%.*]] = load ptr, ptr [[TMP1]], align 4
-// CHECK15-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK15-NEXT: store i32 [[TMP3]], ptr [[T_VAR]], align 4
-// CHECK15-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK15-NEXT: [[S_ARR:%.*]] = load ptr, ptr [[TMP4]], align 4
-// CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK15-NEXT: [[VAR:%.*]] = load ptr, ptr [[TMP5]], align 4
-// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK15-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK15-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK15-NEXT: [[VEC:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK15-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK15-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4
+// CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
+// CHECK15-NEXT: store i32 [[TMP5]], ptr [[T_VAR]], align 4
+// CHECK15-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK15-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
+// CHECK15-NEXT: [[S_ARR:%.*]] = load ptr, ptr [[TMP7]], align 4
+// CHECK15-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK15-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 4
+// CHECK15-NEXT: [[VAR:%.*]] = load ptr, ptr [[TMP9]], align 4
+// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK15-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK15-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP10]], align 4
// CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK15-NEXT: store ptr [[VAR]], ptr [[TMP]], align 4
-// CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[T_VAR]], align 4
-// CHECK15-NEXT: store i32 [[TMP6]], ptr [[T_VAR_CASTED]], align 4
-// CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
-// CHECK15-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]
-// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, ptr [[VEC]], i32 [[TMP7]], ptr [[S_ARR]], ptr [[TMP8]])
+// CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[T_VAR]], align 4
+// CHECK15-NEXT: store i32 [[TMP11]], ptr [[T_VAR_CASTED]], align 4
+// CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
+// CHECK15-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]
+// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, ptr [[VEC]], i32 [[TMP12]], ptr [[S_ARR]], ptr [[TMP13]])
// CHECK15-NEXT: ret void
//
//
@@ -4138,30 +4160,34 @@ int main() {
// CHECK17-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK17-NEXT: store i32 [[TMP2]], ptr [[G]], align 4
-// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
-// CHECK17-NEXT: store i32 [[TMP4]], ptr [[G1]], align 4
-// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
+// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK17-NEXT: store i32 [[TMP3]], ptr [[G]], align 4
+// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK17-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 8
-// CHECK17-NEXT: store i32 [[TMP6]], ptr [[SIVAR]], align 4
-// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: store i32 [[TMP6]], ptr [[G1]], align 4
+// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK17-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8
+// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 8
+// CHECK17-NEXT: store i32 [[TMP9]], ptr [[SIVAR]], align 4
+// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP10]], align 8
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK17-NEXT: store ptr [[G1]], ptr [[TMP]], align 8
-// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[G]], align 4
-// CHECK17-NEXT: store i32 [[TMP7]], ptr [[G_CASTED]], align 4
-// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[G_CASTED]], align 8
-// CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]
-// CHECK17-NEXT: [[TMP10:%.*]] = load volatile i32, ptr [[TMP9]], align 4
-// CHECK17-NEXT: store i32 [[TMP10]], ptr [[G1_CASTED]], align 4
-// CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[G1_CASTED]], align 8
-// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4
-// CHECK17-NEXT: store i32 [[TMP12]], ptr [[SIVAR_CASTED]], align 4
-// CHECK17-NEXT: [[TMP13:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8
-// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined, i64 [[TMP8]], i64 [[TMP11]], i64 [[TMP13]])
+// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[G]], align 4
+// CHECK17-NEXT: store i32 [[TMP11]], ptr [[G_CASTED]], align 4
+// CHECK17-NEXT: [[TMP12:%.*]] = load i64, ptr [[G_CASTED]], align 8
+// CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]
+// CHECK17-NEXT: [[TMP14:%.*]] = load volatile i32, ptr [[TMP13]], align 4
+// CHECK17-NEXT: store i32 [[TMP14]], ptr [[G1_CASTED]], align 4
+// CHECK17-NEXT: [[TMP15:%.*]] = load i64, ptr [[G1_CASTED]], align 8
+// CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR]], align 4
+// CHECK17-NEXT: store i32 [[TMP16]], ptr [[SIVAR_CASTED]], align 4
+// CHECK17-NEXT: [[TMP17:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8
+// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined, i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]])
// CHECK17-NEXT: ret void
//
//
diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp
index 1a3a09b0deac0..d3c617d564de9 100644
--- a/clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp
@@ -1989,8 +1989,9 @@ int main() {
// CHECK13-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK13-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK13-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP1]], align 8
// CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined)
// CHECK13-NEXT: ret void
@@ -2228,8 +2229,9 @@ int main() {
// CHECK13-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK13-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK13-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP1]], align 8
// CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined)
// CHECK13-NEXT: ret void
@@ -2513,8 +2515,9 @@ int main() {
// CHECK15-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK15-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK15-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK15-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP1]], align 4
// CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined)
// CHECK15-NEXT: ret void
@@ -2746,8 +2749,9 @@ int main() {
// CHECK15-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK15-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK15-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK15-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP1]], align 4
// CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined)
// CHECK15-NEXT: ret void
@@ -3025,8 +3029,9 @@ int main() {
// CHECK17-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK17-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP1]], align 8
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined)
// CHECK17-NEXT: ret void
diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_codegen.cpp
index 24218a15b23a2..c73ef0dac7fd0 100644
--- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_codegen.cpp
@@ -2384,33 +2384,39 @@ void test_target_teams_atomic() {
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB4:[0-9]+]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK9-NEXT: store i32 [[TMP3]], ptr [[I]], align 4
-// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
-// CHECK9-NEXT: store i32 [[TMP5]], ptr [[N]], align 4
-// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
-// CHECK9-NEXT: [[A:%.*]] = load ptr, ptr [[TMP6]], align 8
-// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
-// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 8
-// CHECK9-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 4
-// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 8
-// CHECK9-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 5
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
+// CHECK9-NEXT: store i32 [[TMP4]], ptr [[I]], align 4
+// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8
+// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 8
+// CHECK9-NEXT: store i32 [[TMP7]], ptr [[N]], align 4
+// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8
+// CHECK9-NEXT: [[A:%.*]] = load ptr, ptr [[TMP9]], align 8
+// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8
+// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 8
+// CHECK9-NEXT: store i32 [[TMP12]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 4
+// CHECK9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8
+// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 8
+// CHECK9-NEXT: store i32 [[TMP15]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 5
+// CHECK9-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP16]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 8
-// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB4]], i32 [[TMP0]], i32 [[TMP11]], i32 [[TMP12]])
-// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4
-// CHECK9-NEXT: store i32 [[TMP13]], ptr [[I_CASTED]], align 4
-// CHECK9-NEXT: [[TMP14:%.*]] = load i64, ptr [[I_CASTED]], align 8
-// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[N]], align 4
-// CHECK9-NEXT: store i32 [[TMP15]], ptr [[N_CASTED]], align 4
-// CHECK9-NEXT: [[TMP16:%.*]] = load i64, ptr [[N_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l50.omp_outlined, i64 [[TMP14]], i64 [[TMP16]], ptr [[A]])
+// CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB4]], i32 [[TMP0]], i32 [[TMP17]], i32 [[TMP18]])
+// CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4
+// CHECK9-NEXT: store i32 [[TMP19]], ptr [[I_CASTED]], align 4
+// CHECK9-NEXT: [[TMP20:%.*]] = load i64, ptr [[I_CASTED]], align 8
+// CHECK9-NEXT: [[TMP21:%.*]] = load i32, ptr [[N]], align 4
+// CHECK9-NEXT: store i32 [[TMP21]], ptr [[N_CASTED]], align 4
+// CHECK9-NEXT: [[TMP22:%.*]] = load i64, ptr [[N_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l50.omp_outlined, i64 [[TMP20]], i64 [[TMP22]], ptr [[A]])
// CHECK9-NEXT: ret void
//
//
@@ -2667,20 +2673,24 @@ void test_target_teams_atomic() {
// CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK9-NEXT: store i32 [[TMP2]], ptr [[N]], align 4
-// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[A:%.*]] = load ptr, ptr [[TMP3]], align 8
-// CHECK9-NEXT: [[G:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK9-NEXT: store i32 [[TMP3]], ptr [[N]], align 4
+// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK9-NEXT: [[A:%.*]] = load ptr, ptr [[TMP5]], align 8
+// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK9-NEXT: [[G:%.*]] = load ptr, ptr [[TMP6]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4
-// CHECK9-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4
-// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[N_CASTED]], align 8
-// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[G]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l56.omp_outlined, i64 [[TMP5]], ptr [[A]], ptr [[TMP6]])
+// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[N]], align 4
+// CHECK9-NEXT: store i32 [[TMP8]], ptr [[N_CASTED]], align 4
+// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[N_CASTED]], align 8
+// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[G]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l56.omp_outlined, i64 [[TMP9]], ptr [[A]], ptr [[TMP10]])
// CHECK9-NEXT: ret void
//
//
@@ -2915,10 +2925,12 @@ void test_target_teams_atomic() {
// CHECK9-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK9-NEXT: [[X:%.*]] = load ptr, ptr [[TMP1]], align 8
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK9-NEXT: [[X:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP3]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z24test_target_teams_atomicv_l72.omp_outlined, ptr [[X]])
// CHECK9-NEXT: ret void
@@ -3089,33 +3101,39 @@ void test_target_teams_atomic() {
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB4:[0-9]+]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK11-NEXT: store i32 [[TMP3]], ptr [[I]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK11-NEXT: store i32 [[TMP5]], ptr [[N]], align 4
-// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
-// CHECK11-NEXT: [[A:%.*]] = load ptr, ptr [[TMP6]], align 4
-// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
-// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
-// CHECK11-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 4
-// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
-// CHECK11-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 5
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
+// CHECK11-NEXT: store i32 [[TMP4]], ptr [[I]], align 4
+// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4
+// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+// CHECK11-NEXT: store i32 [[TMP7]], ptr [[N]], align 4
+// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 4
+// CHECK11-NEXT: [[A:%.*]] = load ptr, ptr [[TMP9]], align 4
+// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK11-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 4
+// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4
+// CHECK11-NEXT: store i32 [[TMP12]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 4
+// CHECK11-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 4
+// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4
+// CHECK11-NEXT: store i32 [[TMP15]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 5
+// CHECK11-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP16]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 4
-// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB4]], i32 [[TMP0]], i32 [[TMP11]], i32 [[TMP12]])
-// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4
-// CHECK11-NEXT: store i32 [[TMP13]], ptr [[I_CASTED]], align 4
-// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[I_CASTED]], align 4
-// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[N]], align 4
-// CHECK11-NEXT: store i32 [[TMP15]], ptr [[N_CASTED]], align 4
-// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[N_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l50.omp_outlined, i32 [[TMP14]], i32 [[TMP16]], ptr [[A]])
+// CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB4]], i32 [[TMP0]], i32 [[TMP17]], i32 [[TMP18]])
+// CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4
+// CHECK11-NEXT: store i32 [[TMP19]], ptr [[I_CASTED]], align 4
+// CHECK11-NEXT: [[TMP20:%.*]] = load i32, ptr [[I_CASTED]], align 4
+// CHECK11-NEXT: [[TMP21:%.*]] = load i32, ptr [[N]], align 4
+// CHECK11-NEXT: store i32 [[TMP21]], ptr [[N_CASTED]], align 4
+// CHECK11-NEXT: [[TMP22:%.*]] = load i32, ptr [[N_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l50.omp_outlined, i32 [[TMP20]], i32 [[TMP22]], ptr [[A]])
// CHECK11-NEXT: ret void
//
//
@@ -3367,20 +3385,24 @@ void test_target_teams_atomic() {
// CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK11-NEXT: store i32 [[TMP2]], ptr [[N]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[A:%.*]] = load ptr, ptr [[TMP3]], align 4
-// CHECK11-NEXT: [[G:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK11-NEXT: store i32 [[TMP3]], ptr [[N]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK11-NEXT: [[A:%.*]] = load ptr, ptr [[TMP5]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK11-NEXT: [[G:%.*]] = load ptr, ptr [[TMP6]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4
-// CHECK11-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4
-// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4
-// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[G]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l56.omp_outlined, i32 [[TMP5]], ptr [[A]], ptr [[TMP6]])
+// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[N]], align 4
+// CHECK11-NEXT: store i32 [[TMP8]], ptr [[N_CASTED]], align 4
+// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[N_CASTED]], align 4
+// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[G]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l56.omp_outlined, i32 [[TMP9]], ptr [[A]], ptr [[TMP10]])
// CHECK11-NEXT: ret void
//
//
@@ -3610,10 +3632,12 @@ void test_target_teams_atomic() {
// CHECK11-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK11-NEXT: [[X:%.*]] = load ptr, ptr [[TMP1]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK11-NEXT: [[X:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP3]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z24test_target_teams_atomicv_l72.omp_outlined, ptr [[X]])
// CHECK11-NEXT: ret void
diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
index 4bd2f911aa476..e652eee72d01d 100644
--- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
@@ -3527,28 +3527,34 @@ int main() {
// CHECK13-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
// CHECK13-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK13-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK13-NEXT: [[VEC:%.*]] = load ptr, ptr [[TMP1]], align 8
-// CHECK13-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK13-NEXT: store i32 [[TMP3]], ptr [[T_VAR]], align 4
-// CHECK13-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK13-NEXT: [[S_ARR:%.*]] = load ptr, ptr [[TMP4]], align 8
-// CHECK13-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK13-NEXT: [[VAR:%.*]] = load ptr, ptr [[TMP5]], align 8
-// CHECK13-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 8
-// CHECK13-NEXT: store i32 [[TMP7]], ptr [[SIVAR]], align 4
-// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
-// CHECK13-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK13-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK13-NEXT: [[VEC:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK13-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK13-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
+// CHECK13-NEXT: store i32 [[TMP5]], ptr [[T_VAR]], align 4
+// CHECK13-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK13-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
+// CHECK13-NEXT: [[S_ARR:%.*]] = load ptr, ptr [[TMP7]], align 8
+// CHECK13-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK13-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8
+// CHECK13-NEXT: [[VAR:%.*]] = load ptr, ptr [[TMP9]], align 8
+// CHECK13-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK13-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8
+// CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 8
+// CHECK13-NEXT: store i32 [[TMP12]], ptr [[SIVAR]], align 4
+// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK13-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK13-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP13]], align 8
// CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4
-// CHECK13-NEXT: store i32 [[TMP8]], ptr [[T_VAR_CASTED]], align 4
-// CHECK13-NEXT: [[TMP9:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
-// CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[SIVAR]], align 4
-// CHECK13-NEXT: store i32 [[TMP10]], ptr [[SIVAR_CASTED]], align 4
-// CHECK13-NEXT: [[TMP11:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8
-// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined, ptr [[VEC]], i64 [[TMP9]], ptr [[S_ARR]], ptr [[VAR]], i64 [[TMP11]])
+// CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR]], align 4
+// CHECK13-NEXT: store i32 [[TMP14]], ptr [[T_VAR_CASTED]], align 4
+// CHECK13-NEXT: [[TMP15:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
+// CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR]], align 4
+// CHECK13-NEXT: store i32 [[TMP16]], ptr [[SIVAR_CASTED]], align 4
+// CHECK13-NEXT: [[TMP17:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8
+// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined, ptr [[VEC]], i64 [[TMP15]], ptr [[S_ARR]], ptr [[VAR]], i64 [[TMP17]])
// CHECK13-NEXT: ret void
//
//
@@ -3876,24 +3882,29 @@ int main() {
// CHECK13-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
// CHECK13-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK13-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK13-NEXT: [[VEC:%.*]] = load ptr, ptr [[TMP1]], align 8
-// CHECK13-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK13-NEXT: store i32 [[TMP3]], ptr [[T_VAR]], align 4
-// CHECK13-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK13-NEXT: [[S_ARR:%.*]] = load ptr, ptr [[TMP4]], align 8
-// CHECK13-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK13-NEXT: [[VAR:%.*]] = load ptr, ptr [[TMP5]], align 8
-// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK13-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK13-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK13-NEXT: [[VEC:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK13-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK13-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
+// CHECK13-NEXT: store i32 [[TMP5]], ptr [[T_VAR]], align 4
+// CHECK13-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK13-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
+// CHECK13-NEXT: [[S_ARR:%.*]] = load ptr, ptr [[TMP7]], align 8
+// CHECK13-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK13-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8
+// CHECK13-NEXT: [[VAR:%.*]] = load ptr, ptr [[TMP9]], align 8
+// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK13-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK13-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP10]], align 8
// CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK13-NEXT: store ptr [[VAR]], ptr [[TMP]], align 8
-// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[T_VAR]], align 4
-// CHECK13-NEXT: store i32 [[TMP6]], ptr [[T_VAR_CASTED]], align 4
-// CHECK13-NEXT: [[TMP7:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
-// CHECK13-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]
-// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, ptr [[VEC]], i64 [[TMP7]], ptr [[S_ARR]], ptr [[TMP8]])
+// CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[T_VAR]], align 4
+// CHECK13-NEXT: store i32 [[TMP11]], ptr [[T_VAR_CASTED]], align 4
+// CHECK13-NEXT: [[TMP12:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
+// CHECK13-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]]
+// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, ptr [[VEC]], i64 [[TMP12]], ptr [[S_ARR]], ptr [[TMP13]])
// CHECK13-NEXT: ret void
//
//
@@ -4285,28 +4296,34 @@ int main() {
// CHECK15-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
// CHECK15-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK15-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK15-NEXT: [[VEC:%.*]] = load ptr, ptr [[TMP1]], align 4
-// CHECK15-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK15-NEXT: store i32 [[TMP3]], ptr [[T_VAR]], align 4
-// CHECK15-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK15-NEXT: [[S_ARR:%.*]] = load ptr, ptr [[TMP4]], align 4
-// CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK15-NEXT: [[VAR:%.*]] = load ptr, ptr [[TMP5]], align 4
-// CHECK15-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
-// CHECK15-NEXT: store i32 [[TMP7]], ptr [[SIVAR]], align 4
-// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
-// CHECK15-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK15-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK15-NEXT: [[VEC:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK15-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK15-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4
+// CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
+// CHECK15-NEXT: store i32 [[TMP5]], ptr [[T_VAR]], align 4
+// CHECK15-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK15-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
+// CHECK15-NEXT: [[S_ARR:%.*]] = load ptr, ptr [[TMP7]], align 4
+// CHECK15-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK15-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 4
+// CHECK15-NEXT: [[VAR:%.*]] = load ptr, ptr [[TMP9]], align 4
+// CHECK15-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK15-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 4
+// CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4
+// CHECK15-NEXT: store i32 [[TMP12]], ptr [[SIVAR]], align 4
+// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK15-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK15-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP13]], align 4
// CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4
-// CHECK15-NEXT: store i32 [[TMP8]], ptr [[T_VAR_CASTED]], align 4
-// CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
-// CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[SIVAR]], align 4
-// CHECK15-NEXT: store i32 [[TMP10]], ptr [[SIVAR_CASTED]], align 4
-// CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4
-// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined, ptr [[VEC]], i32 [[TMP9]], ptr [[S_ARR]], ptr [[VAR]], i32 [[TMP11]])
+// CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR]], align 4
+// CHECK15-NEXT: store i32 [[TMP14]], ptr [[T_VAR_CASTED]], align 4
+// CHECK15-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
+// CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR]], align 4
+// CHECK15-NEXT: store i32 [[TMP16]], ptr [[SIVAR_CASTED]], align 4
+// CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4
+// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l122.omp_outlined, ptr [[VEC]], i32 [[TMP15]], ptr [[S_ARR]], ptr [[VAR]], i32 [[TMP17]])
// CHECK15-NEXT: ret void
//
//
@@ -4628,24 +4645,29 @@ int main() {
// CHECK15-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
// CHECK15-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK15-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK15-NEXT: [[VEC:%.*]] = load ptr, ptr [[TMP1]], align 4
-// CHECK15-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK15-NEXT: store i32 [[TMP3]], ptr [[T_VAR]], align 4
-// CHECK15-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK15-NEXT: [[S_ARR:%.*]] = load ptr, ptr [[TMP4]], align 4
-// CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK15-NEXT: [[VAR:%.*]] = load ptr, ptr [[TMP5]], align 4
-// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK15-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK15-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK15-NEXT: [[VEC:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK15-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK15-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4
+// CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
+// CHECK15-NEXT: store i32 [[TMP5]], ptr [[T_VAR]], align 4
+// CHECK15-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK15-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
+// CHECK15-NEXT: [[S_ARR:%.*]] = load ptr, ptr [[TMP7]], align 4
+// CHECK15-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK15-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 4
+// CHECK15-NEXT: [[VAR:%.*]] = load ptr, ptr [[TMP9]], align 4
+// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK15-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK15-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP10]], align 4
// CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK15-NEXT: store ptr [[VAR]], ptr [[TMP]], align 4
-// CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[T_VAR]], align 4
-// CHECK15-NEXT: store i32 [[TMP6]], ptr [[T_VAR_CASTED]], align 4
-// CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
-// CHECK15-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]
-// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, ptr [[VEC]], i32 [[TMP7]], ptr [[S_ARR]], ptr [[TMP8]])
+// CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[T_VAR]], align 4
+// CHECK15-NEXT: store i32 [[TMP11]], ptr [[T_VAR_CASTED]], align 4
+// CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
+// CHECK15-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]]
+// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, ptr [[VEC]], i32 [[TMP12]], ptr [[S_ARR]], ptr [[TMP13]])
// CHECK15-NEXT: ret void
//
//
@@ -5034,30 +5056,34 @@ int main() {
// CHECK17-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK17-NEXT: store i32 [[TMP2]], ptr [[G]], align 4
-// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
-// CHECK17-NEXT: store i32 [[TMP4]], ptr [[G1]], align 4
-// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
+// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK17-NEXT: store i32 [[TMP3]], ptr [[G]], align 4
+// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK17-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 8
-// CHECK17-NEXT: store i32 [[TMP6]], ptr [[SIVAR]], align 4
-// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: store i32 [[TMP6]], ptr [[G1]], align 4
+// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK17-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8
+// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 8
+// CHECK17-NEXT: store i32 [[TMP9]], ptr [[SIVAR]], align 4
+// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP10]], align 8
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK17-NEXT: store ptr [[G1]], ptr [[TMP]], align 8
-// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[G]], align 4
-// CHECK17-NEXT: store i32 [[TMP7]], ptr [[G_CASTED]], align 4
-// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[G_CASTED]], align 8
-// CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]
-// CHECK17-NEXT: [[TMP10:%.*]] = load volatile i32, ptr [[TMP9]], align 4
-// CHECK17-NEXT: store i32 [[TMP10]], ptr [[G1_CASTED]], align 4
-// CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[G1_CASTED]], align 8
-// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4
-// CHECK17-NEXT: store i32 [[TMP12]], ptr [[SIVAR_CASTED]], align 4
-// CHECK17-NEXT: [[TMP13:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8
-// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined, i64 [[TMP8]], i64 [[TMP11]], i64 [[TMP13]])
+// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[G]], align 4
+// CHECK17-NEXT: store i32 [[TMP11]], ptr [[G_CASTED]], align 4
+// CHECK17-NEXT: [[TMP12:%.*]] = load i64, ptr [[G_CASTED]], align 8
+// CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]]
+// CHECK17-NEXT: [[TMP14:%.*]] = load volatile i32, ptr [[TMP13]], align 4
+// CHECK17-NEXT: store i32 [[TMP14]], ptr [[G1_CASTED]], align 4
+// CHECK17-NEXT: [[TMP15:%.*]] = load i64, ptr [[G1_CASTED]], align 8
+// CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR]], align 4
+// CHECK17-NEXT: store i32 [[TMP16]], ptr [[SIVAR_CASTED]], align 4
+// CHECK17-NEXT: [[TMP17:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8
+// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l99.omp_outlined, i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]])
// CHECK17-NEXT: ret void
//
//
diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp
index b975f393e3666..6d9d437979044 100644
--- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp
@@ -2941,8 +2941,9 @@ int main() {
// CHECK13-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK13-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK13-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP1]], align 8
// CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined)
// CHECK13-NEXT: ret void
@@ -3194,8 +3195,9 @@ int main() {
// CHECK13-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK13-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK13-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP1]], align 8
// CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined)
// CHECK13-NEXT: ret void
@@ -3493,8 +3495,9 @@ int main() {
// CHECK15-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK15-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK15-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK15-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP1]], align 4
// CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined)
// CHECK15-NEXT: ret void
@@ -3740,8 +3743,9 @@ int main() {
// CHECK15-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK15-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK15-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK15-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP1]], align 4
// CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined)
// CHECK15-NEXT: ret void
@@ -4033,8 +4037,9 @@ int main() {
// CHECK17-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK17-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP1]], align 8
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined)
// CHECK17-NEXT: ret void
diff --git a/clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp
index 038abb4fe564e..5c7c798512c55 100644
--- a/clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp
@@ -820,7 +820,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META32]]
// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META32]]
// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META32]]
-// CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
+// CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]], !inline_history [[META33:![0-9]+]]
// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META32]]
// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META32]]
// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META32]]
@@ -945,7 +945,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
// CHECK1: omp.inner.for.end:
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK1: omp.loop.exit:
@@ -1013,28 +1013,28 @@ int bar(int n){
// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35:![0-9]+]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP35]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP36]]
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP35]]
-// CHECK1-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP35]]
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP36]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP36]]
// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i32
// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
// CHECK1-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK1-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP35]]
+// CHECK1-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP36]]
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]]
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]]
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]]
+// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
// CHECK1: omp.inner.for.end:
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK1: omp.loop.exit:
@@ -1110,31 +1110,31 @@ int bar(int n){
// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38:![0-9]+]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP38]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39:![0-9]+]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP39]]
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]]
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP38]]
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP38]]
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP39]]
// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP38]]
-// CHECK1-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP38]]
+// CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP39]]
+// CHECK1-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP39]]
// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
// CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK1-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP38]]
+// CHECK1-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP39]]
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]]
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]]
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]]
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]]
+// CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]
// CHECK1: omp.inner.for.end:
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK1: omp.loop.exit:
@@ -1173,14 +1173,14 @@ int bar(int n){
// CHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8
// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META41:![0-9]+]], !align [[META42:![0-9]+]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META42:![0-9]+]], !align [[META43:![0-9]+]]
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META41]], !align [[META42]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META41]], !align [[META43:![0-9]+]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META42]], !align [[META43]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META42]], !align [[META44:![0-9]+]]
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META41]], !align [[META43]]
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META41]], !align [[META43]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META42]], !align [[META44]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META42]], !align [[META44]]
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
@@ -1220,14 +1220,14 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
// CHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8
// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META41]], !align [[META42]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META42]], !align [[META43]]
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META41]], !align [[META42]]
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META41]], !align [[META43]]
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META42]], !align [[META43]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META42]], !align [[META44]]
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
-// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META41]], !align [[META43]]
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META41]], !align [[META43]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META42]], !align [[META44]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META42]], !align [[META44]]
// CHECK1-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 0
// CHECK1-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[ARRAYDECAY]], i64 16) ]
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
@@ -1252,59 +1252,59 @@ int bar(int n){
// CHECK1-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44:![0-9]+]]
-// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45:![0-9]+]]
+// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP44]]
-// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP45]]
+// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
-// CHECK1-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2
-// CHECK1-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double
// CHECK1-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00
// CHECK1-NEXT: [[CONV8:%.*]] = fptrunc double [[ADD7]] to float
-// CHECK1-NEXT: store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3
-// CHECK1-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: [[CONV10:%.*]] = fpext float [[TMP18]] to double
// CHECK1-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00
// CHECK1-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float
-// CHECK1-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1
// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i64 0, i64 2
-// CHECK1-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00
-// CHECK1-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP5]]
// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP20]]
// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX16]], i64 3
-// CHECK1-NEXT: [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00
-// CHECK1-NEXT: store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
-// CHECK1-NEXT: [[TMP22:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: [[TMP22:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1
-// CHECK1-NEXT: store i64 [[ADD19]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: store i64 [[ADD19]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
-// CHECK1-NEXT: [[TMP23:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: [[TMP23:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: [[CONV20:%.*]] = sext i8 [[TMP23]] to i32
// CHECK1-NEXT: [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1
// CHECK1-NEXT: [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8
-// CHECK1-NEXT: store i8 [[CONV22]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: store i8 [[CONV22]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK1-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1
-// CHECK1-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]]
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]]
+// CHECK1-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]]
// CHECK1: omp.inner.for.end:
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK1: omp.loop.exit:
@@ -1730,7 +1730,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META41]], !align [[META47:![0-9]+]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META42]], !align [[META48:![0-9]+]]
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8
@@ -1765,7 +1765,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META41]], !align [[META47]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META42]], !align [[META48]]
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -1788,37 +1788,37 @@ int bar(int n){
// CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP48:![0-9]+]]
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP48]]
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP49:![0-9]+]]
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP49]]
// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP48]]
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP49]]
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP48]]
-// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP48]]
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP49]]
+// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP49]]
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK1-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
-// CHECK1-NEXT: store double [[ADD4]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP48]]
+// CHECK1-NEXT: store double [[ADD4]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP49]]
// CHECK1-NEXT: [[A5:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
-// CHECK1-NEXT: [[TMP13:%.*]] = load double, ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP48]]
+// CHECK1-NEXT: [[TMP13:%.*]] = load double, ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP49]]
// CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
-// CHECK1-NEXT: store double [[INC]], ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP48]]
+// CHECK1-NEXT: store double [[INC]], ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP49]]
// CHECK1-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
// CHECK1-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP14]]
// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
-// CHECK1-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP48]]
+// CHECK1-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP49]]
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP48]]
+// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP49]]
// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1
-// CHECK1-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP48]]
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP49:![0-9]+]]
+// CHECK1-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP49]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP50:![0-9]+]]
// CHECK1: omp.inner.for.end:
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK1: omp.loop.exit:
@@ -1852,7 +1852,7 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META41]], !align [[META42]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META42]], !align [[META43]]
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
@@ -1897,7 +1897,7 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META41]], !align [[META42]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META42]], !align [[META43]]
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
@@ -1942,42 +1942,42 @@ int bar(int n){
// CHECK1-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 4
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP51:![0-9]+]]
-// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP51]]
+// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP52:![0-9]+]]
+// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP52]]
// CHECK1-NEXT: [[ADD7:%.*]] = add i32 [[TMP17]], 1
// CHECK1-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]]
// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP51]]
-// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP51]]
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP52]]
+// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP52]]
// CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK1-NEXT: [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]]
-// CHECK1-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP51]]
-// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP51]]
+// CHECK1-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP52]]
+// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP52]]
// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1
-// CHECK1-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP51]]
-// CHECK1-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP51]]
+// CHECK1-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP52]]
+// CHECK1-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP52]]
// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP21]] to i32
// CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV]], 1
// CHECK1-NEXT: [[CONV12:%.*]] = trunc i32 [[ADD11]] to i16
-// CHECK1-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP51]]
-// CHECK1-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP51]]
+// CHECK1-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP52]]
+// CHECK1-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP52]]
// CHECK1-NEXT: [[CONV13:%.*]] = sext i8 [[TMP22]] to i32
// CHECK1-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1
// CHECK1-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8
-// CHECK1-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP51]]
+// CHECK1-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP52]]
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2
-// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP51]]
+// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP52]]
// CHECK1-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1
-// CHECK1-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP51]]
+// CHECK1-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP52]]
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP51]]
+// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP52]]
// CHECK1-NEXT: [[ADD17:%.*]] = add i32 [[TMP24]], 1
-// CHECK1-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP51]]
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP52:![0-9]+]]
+// CHECK1-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP52]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP53:![0-9]+]]
// CHECK1: omp.inner.for.end:
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK1: omp.loop.exit:
@@ -2018,7 +2018,7 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META41]], !align [[META42]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META42]], !align [[META43]]
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
@@ -2049,7 +2049,7 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META41]], !align [[META42]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META42]], !align [[META43]]
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -2072,35 +2072,35 @@ int bar(int n){
// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP54:![0-9]+]]
-// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP54]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP55:![0-9]+]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP55]]
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP54]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP55]]
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP54]]
-// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP54]]
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP55]]
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP55]]
// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP54]]
-// CHECK1-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP54]]
+// CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP55]]
+// CHECK1-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP55]]
// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
// CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK1-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP54]]
+// CHECK1-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP55]]
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2
-// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP54]]
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP55]]
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK1-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP54]]
+// CHECK1-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP55]]
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP54]]
+// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP55]]
// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1
-// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP54]]
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP55:![0-9]+]]
+// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP55]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP56:![0-9]+]]
// CHECK1: omp.inner.for.end:
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK1: omp.loop.exit:
@@ -2642,7 +2642,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META33]]
// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META33]]
// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META33]]
-// CHECK3-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
+// CHECK3-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]], !inline_history [[META34:![0-9]+]]
// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias [[META33]]
// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias [[META33]]
// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias [[META33]]
@@ -2767,7 +2767,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
+// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]]
// CHECK3: omp.inner.for.end:
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK3: omp.loop.exit:
@@ -2835,28 +2835,28 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK3: omp.inner.for.cond:
-// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]]
-// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP36]]
+// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37:![0-9]+]]
+// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP37]]
// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK3: omp.inner.for.body:
-// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]
+// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]]
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP36]]
-// CHECK3-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP36]]
+// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP37]]
+// CHECK3-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP37]]
// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i32
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
// CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK3-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP36]]
+// CHECK3-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP37]]
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK3: omp.inner.for.inc:
-// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]
+// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]]
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
+// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]]
+// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]]
// CHECK3: omp.inner.for.end:
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK3: omp.loop.exit:
@@ -2932,31 +2932,31 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK3: omp.inner.for.cond:
-// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39:![0-9]+]]
-// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP39]]
+// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40:![0-9]+]]
+// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP40]]
// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK3: omp.inner.for.body:
-// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]]
+// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]]
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]]
-// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP39]]
+// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP40]]
+// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP40]]
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP39]]
-// CHECK3-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP39]]
+// CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP40]]
+// CHECK3-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP40]]
// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
// CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK3-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP39]]
+// CHECK3-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP40]]
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK3: omp.inner.for.inc:
-// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]]
+// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]]
// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]]
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]
+// CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]]
+// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]]
// CHECK3: omp.inner.for.end:
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK3: omp.loop.exit:
@@ -2995,14 +2995,14 @@ int bar(int n){
// CHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4
// CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META42:![0-9]+]], !align [[META43:![0-9]+]]
+// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META43:![0-9]+]], !align [[META44:![0-9]+]]
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
-// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4, !nonnull [[META42]], !align [[META43]]
-// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META42]], !align [[META43]]
+// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4, !nonnull [[META43]], !align [[META44]]
+// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META43]], !align [[META44]]
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
-// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4, !nonnull [[META42]], !align [[META43]]
-// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META42]], !align [[META43]]
+// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4, !nonnull [[META43]], !align [[META44]]
+// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META43]], !align [[META44]]
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
@@ -3042,14 +3042,14 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
// CHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4
// CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
-// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META42]], !align [[META43]]
+// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META43]], !align [[META44]]
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
-// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4, !nonnull [[META42]], !align [[META43]]
-// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META42]], !align [[META43]]
+// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4, !nonnull [[META43]], !align [[META44]]
+// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META43]], !align [[META44]]
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
-// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4, !nonnull [[META42]], !align [[META43]]
-// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META42]], !align [[META43]]
+// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4, !nonnull [[META43]], !align [[META44]]
+// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META43]], !align [[META44]]
// CHECK3-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 0
// CHECK3-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[ARRAYDECAY]], i32 16) ]
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
@@ -3074,59 +3074,59 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK3: omp.inner.for.cond:
-// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44:![0-9]+]]
-// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45:![0-9]+]]
+// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK3: omp.inner.for.body:
-// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP44]]
-// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP45]]
+// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
-// CHECK3-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2
-// CHECK3-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double
// CHECK3-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00
// CHECK3-NEXT: [[CONV8:%.*]] = fptrunc double [[ADD7]] to float
-// CHECK3-NEXT: store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3
-// CHECK3-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: [[CONV10:%.*]] = fpext float [[TMP18]] to double
// CHECK3-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00
// CHECK3-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float
-// CHECK3-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1
// CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i32 0, i32 2
-// CHECK3-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00
-// CHECK3-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: [[TMP20:%.*]] = mul nsw i32 1, [[TMP5]]
// CHECK3-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP20]]
// CHECK3-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX16]], i32 3
-// CHECK3-NEXT: [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00
-// CHECK3-NEXT: store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
-// CHECK3-NEXT: [[TMP22:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: [[TMP22:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1
-// CHECK3-NEXT: store i64 [[ADD19]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: store i64 [[ADD19]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
-// CHECK3-NEXT: [[TMP23:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: [[TMP23:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: [[CONV20:%.*]] = sext i8 [[TMP23]] to i32
// CHECK3-NEXT: [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1
// CHECK3-NEXT: [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8
-// CHECK3-NEXT: store i8 [[CONV22]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: store i8 [[CONV22]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK3: omp.inner.for.inc:
-// CHECK3-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]]
+// CHECK3-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]
// CHECK3-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1
-// CHECK3-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]]
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]]
+// CHECK3-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]
+// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]]
// CHECK3: omp.inner.for.end:
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK3: omp.loop.exit:
@@ -3552,7 +3552,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
-// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META42]], !align [[META47:![0-9]+]]
+// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META43]], !align [[META48:![0-9]+]]
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
@@ -3587,7 +3587,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
-// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META42]], !align [[META47]]
+// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META43]], !align [[META48]]
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -3610,37 +3610,37 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK3: omp.inner.for.cond:
-// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP48:![0-9]+]]
-// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP48]]
+// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP49:![0-9]+]]
+// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP49]]
// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK3: omp.inner.for.body:
-// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP48]]
+// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP49]]
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP48]]
-// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP48]]
+// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP49]]
+// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP49]]
// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
// CHECK3-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
-// CHECK3-NEXT: store double [[ADD4]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP48]]
+// CHECK3-NEXT: store double [[ADD4]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP49]]
// CHECK3-NEXT: [[A5:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
-// CHECK3-NEXT: [[TMP13:%.*]] = load double, ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP48]]
+// CHECK3-NEXT: [[TMP13:%.*]] = load double, ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP49]]
// CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
-// CHECK3-NEXT: store double [[INC]], ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP48]]
+// CHECK3-NEXT: store double [[INC]], ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP49]]
// CHECK3-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
// CHECK3-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP14]]
// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
-// CHECK3-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP48]]
+// CHECK3-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP49]]
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK3: omp.inner.for.inc:
-// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP48]]
+// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP49]]
// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1
-// CHECK3-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP48]]
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP49:![0-9]+]]
+// CHECK3-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP49]]
+// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP50:![0-9]+]]
// CHECK3: omp.inner.for.end:
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK3: omp.loop.exit:
@@ -3674,7 +3674,7 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META42]], !align [[META43]]
+// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META43]], !align [[META44]]
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
@@ -3719,7 +3719,7 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
// CHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
-// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META42]], !align [[META43]]
+// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META43]], !align [[META44]]
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
@@ -3764,42 +3764,42 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 4
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK3: omp.inner.for.cond:
-// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP51:![0-9]+]]
-// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP51]]
+// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP52:![0-9]+]]
+// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP52]]
// CHECK3-NEXT: [[ADD7:%.*]] = add i32 [[TMP17]], 1
// CHECK3-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]]
// CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK3: omp.inner.for.body:
-// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP51]]
-// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP51]]
+// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP52]]
+// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP52]]
// CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK3-NEXT: [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]]
-// CHECK3-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP51]]
-// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP51]]
+// CHECK3-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP52]]
+// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP52]]
// CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1
-// CHECK3-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP51]]
-// CHECK3-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP51]]
+// CHECK3-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP52]]
+// CHECK3-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP52]]
// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP21]] to i32
// CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV]], 1
// CHECK3-NEXT: [[CONV12:%.*]] = trunc i32 [[ADD11]] to i16
-// CHECK3-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP51]]
-// CHECK3-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP51]]
+// CHECK3-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP52]]
+// CHECK3-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP52]]
// CHECK3-NEXT: [[CONV13:%.*]] = sext i8 [[TMP22]] to i32
// CHECK3-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1
// CHECK3-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8
-// CHECK3-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP51]]
+// CHECK3-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP52]]
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2
-// CHECK3-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP51]]
+// CHECK3-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP52]]
// CHECK3-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1
-// CHECK3-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP51]]
+// CHECK3-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP52]]
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK3: omp.inner.for.inc:
-// CHECK3-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP51]]
+// CHECK3-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP52]]
// CHECK3-NEXT: [[ADD17:%.*]] = add i32 [[TMP24]], 1
-// CHECK3-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP51]]
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP52:![0-9]+]]
+// CHECK3-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP52]]
+// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP53:![0-9]+]]
// CHECK3: omp.inner.for.end:
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK3: omp.loop.exit:
@@ -3840,7 +3840,7 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META42]], !align [[META43]]
+// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META43]], !align [[META44]]
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
@@ -3871,7 +3871,7 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
-// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META42]], !align [[META43]]
+// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META43]], !align [[META44]]
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -3894,35 +3894,35 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK3: omp.inner.for.cond:
-// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP54:![0-9]+]]
-// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP54]]
+// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP55:![0-9]+]]
+// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP55]]
// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK3: omp.inner.for.body:
-// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP54]]
+// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP55]]
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP54]]
-// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP54]]
+// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP55]]
+// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP55]]
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP54]]
-// CHECK3-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP54]]
+// CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP55]]
+// CHECK3-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP55]]
// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
// CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK3-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP54]]
+// CHECK3-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP55]]
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2
-// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP54]]
+// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP55]]
// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK3-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP54]]
+// CHECK3-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP55]]
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue:
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK3: omp.inner.for.inc:
-// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP54]]
+// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP55]]
// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1
-// CHECK3-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP54]]
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP55:![0-9]+]]
+// CHECK3-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP55]]
+// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP56:![0-9]+]]
// CHECK3: omp.inner.for.end:
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK3: omp.loop.exit:
@@ -4464,7 +4464,7 @@ int bar(int n){
// CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META32]]
// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META32]]
// CHECK5-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META32]]
-// CHECK5-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
+// CHECK5-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]], !inline_history [[META33:![0-9]+]]
// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META32]]
// CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META32]]
// CHECK5-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META32]]
@@ -4578,10 +4578,10 @@ int bar(int n){
// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK5-NEXT: store i32 [[ADD]], ptr [[A1]], align 4, !nontemporal [[META33:![0-9]+]]
-// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A1]], align 4, !nontemporal [[META33]]
+// CHECK5-NEXT: store i32 [[ADD]], ptr [[A1]], align 4, !nontemporal [[META34:![0-9]+]]
+// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A1]], align 4, !nontemporal [[META34]]
// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK5-NEXT: store i32 [[ADD3]], ptr [[A1]], align 4, !nontemporal [[META33]]
+// CHECK5-NEXT: store i32 [[ADD3]], ptr [[A1]], align 4, !nontemporal [[META34]]
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK5: omp.body.continue:
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -4589,7 +4589,7 @@ int bar(int n){
// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK5-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]]
// CHECK5: omp.inner.for.end:
// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK5: omp.loop.exit:
@@ -4657,28 +4657,28 @@ int bar(int n){
// CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK5: omp.inner.for.cond:
-// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]]
-// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP36]]
+// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37:![0-9]+]]
+// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP37]]
// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body:
-// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]
+// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]]
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP36]]
-// CHECK5-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP36]]
+// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP37]]
+// CHECK5-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP37]]
// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i32
// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
// CHECK5-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK5-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP36]]
+// CHECK5-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP37]]
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK5: omp.body.continue:
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK5: omp.inner.for.inc:
-// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]
+// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]]
// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK5-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
+// CHECK5-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]]
// CHECK5: omp.inner.for.end:
// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK5: omp.loop.exit:
@@ -4754,31 +4754,31 @@ int bar(int n){
// CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK5: omp.inner.for.cond:
-// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39:![0-9]+]]
-// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP39]]
+// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40:![0-9]+]]
+// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP40]]
// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body:
-// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]]
+// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]]
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]]
-// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP39]]
+// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP40]]
+// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP40]]
// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK5-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP39]]
-// CHECK5-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP39]]
+// CHECK5-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP40]]
+// CHECK5-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP40]]
// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32
// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
// CHECK5-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK5-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP39]]
+// CHECK5-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP40]]
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK5: omp.body.continue:
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK5: omp.inner.for.inc:
-// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]]
+// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]]
// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK5-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]]
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]
+// CHECK5-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]]
// CHECK5: omp.inner.for.end:
// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK5: omp.loop.exit:
@@ -4817,14 +4817,14 @@ int bar(int n){
// CHECK5-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8
// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META42:![0-9]+]], !align [[META43:![0-9]+]]
+// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META43:![0-9]+]], !align [[META44:![0-9]+]]
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
-// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META42]], !align [[META43]]
-// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META42]], !align [[META44:![0-9]+]]
+// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META43]], !align [[META44]]
+// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META43]], !align [[META45:![0-9]+]]
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
// CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
-// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META42]], !align [[META44]]
-// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META42]], !align [[META44]]
+// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META43]], !align [[META45]]
+// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META43]], !align [[META45]]
// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
// CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
@@ -4864,14 +4864,14 @@ int bar(int n){
// CHECK5-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
// CHECK5-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8
// CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
-// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META42]], !align [[META43]]
+// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META43]], !align [[META44]]
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
-// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META42]], !align [[META43]]
-// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META42]], !align [[META44]]
+// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8, !nonnull [[META43]], !align [[META44]]
+// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META43]], !align [[META45]]
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
// CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
-// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META42]], !align [[META44]]
-// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META42]], !align [[META44]]
+// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8, !nonnull [[META43]], !align [[META45]]
+// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META43]], !align [[META45]]
// CHECK5-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 0
// CHECK5-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[ARRAYDECAY]], i64 16) ]
// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
@@ -4896,59 +4896,59 @@ int bar(int n){
// CHECK5-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK5: omp.inner.for.cond:
-// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45:![0-9]+]]
-// CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP45]]
+// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP46:![0-9]+]]
+// CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP46]]
// CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body:
-// CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]
+// CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP46]]
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP45]]
-// CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]]
+// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP46]]
+// CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP46]]
// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
-// CHECK5-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]]
+// CHECK5-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP46]]
// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2
-// CHECK5-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]]
+// CHECK5-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP46]]
// CHECK5-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double
// CHECK5-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00
// CHECK5-NEXT: [[CONV8:%.*]] = fptrunc double [[ADD7]] to float
-// CHECK5-NEXT: store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]]
+// CHECK5-NEXT: store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP46]]
// CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3
-// CHECK5-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP45]]
+// CHECK5-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP46]]
// CHECK5-NEXT: [[CONV10:%.*]] = fpext float [[TMP18]] to double
// CHECK5-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00
// CHECK5-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float
-// CHECK5-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP45]]
+// CHECK5-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP46]]
// CHECK5-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1
// CHECK5-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i64 0, i64 2
-// CHECK5-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP45]]
+// CHECK5-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP46]]
// CHECK5-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00
-// CHECK5-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP45]]
+// CHECK5-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP46]]
// CHECK5-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP5]]
// CHECK5-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP20]]
// CHECK5-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX16]], i64 3
-// CHECK5-NEXT: [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP45]]
+// CHECK5-NEXT: [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP46]]
// CHECK5-NEXT: [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00
-// CHECK5-NEXT: store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP45]]
+// CHECK5-NEXT: store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP46]]
// CHECK5-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
-// CHECK5-NEXT: [[TMP22:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP45]]
+// CHECK5-NEXT: [[TMP22:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP46]]
// CHECK5-NEXT: [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1
-// CHECK5-NEXT: store i64 [[ADD19]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP45]]
+// CHECK5-NEXT: store i64 [[ADD19]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP46]]
// CHECK5-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
-// CHECK5-NEXT: [[TMP23:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP45]]
+// CHECK5-NEXT: [[TMP23:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP46]]
// CHECK5-NEXT: [[CONV20:%.*]] = sext i8 [[TMP23]] to i32
// CHECK5-NEXT: [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1
// CHECK5-NEXT: [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8
-// CHECK5-NEXT: store i8 [[CONV22]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP45]]
+// CHECK5-NEXT: store i8 [[CONV22]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP46]]
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK5: omp.body.continue:
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK5: omp.inner.for.inc:
-// CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]
+// CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP46]]
// CHECK5-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1
-// CHECK5-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]]
+// CHECK5-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP46]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP47:![0-9]+]]
// CHECK5: omp.inner.for.end:
// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK5: omp.loop.exit:
@@ -5394,7 +5394,7 @@ int bar(int n){
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
-// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META42]], !align [[META48:![0-9]+]]
+// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META43]], !align [[META49:![0-9]+]]
// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
// CHECK5-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
// CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8
@@ -5436,7 +5436,7 @@ int bar(int n){
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
-// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META42]], !align [[META48]]
+// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META43]], !align [[META49]]
// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK5-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -5463,37 +5463,37 @@ int bar(int n){
// CHECK5: omp_if.then:
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK5: omp.inner.for.cond:
-// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP49:![0-9]+]]
-// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP49]]
+// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP50:![0-9]+]]
+// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP50]]
// CHECK5-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
// CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body:
-// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP49]]
+// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP50]]
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP49]]
-// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP49]]
+// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP50]]
+// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP50]]
// CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP13]] to double
// CHECK5-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
-// CHECK5-NEXT: store double [[ADD4]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP49]]
+// CHECK5-NEXT: store double [[ADD4]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP50]]
// CHECK5-NEXT: [[A5:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
-// CHECK5-NEXT: [[TMP14:%.*]] = load double, ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP49]]
+// CHECK5-NEXT: [[TMP14:%.*]] = load double, ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP50]]
// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
-// CHECK5-NEXT: store double [[INC]], ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP49]]
+// CHECK5-NEXT: store double [[INC]], ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP50]]
// CHECK5-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
// CHECK5-NEXT: [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]]
// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP15]]
// CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
-// CHECK5-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP49]]
+// CHECK5-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP50]]
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK5: omp.body.continue:
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK5: omp.inner.for.inc:
-// CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP49]]
+// CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP50]]
// CHECK5-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP16]], 1
-// CHECK5-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP49]]
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP50:![0-9]+]]
+// CHECK5-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP50]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP51:![0-9]+]]
// CHECK5: omp.inner.for.end:
// CHECK5-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK5: omp_if.else:
@@ -5529,7 +5529,7 @@ int bar(int n){
// CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// CHECK5-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK5-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP52:![0-9]+]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP53:![0-9]+]]
// CHECK5: omp.inner.for.end25:
// CHECK5-NEXT: br label [[OMP_IF_END]]
// CHECK5: omp_if.end:
@@ -5565,7 +5565,7 @@ int bar(int n){
// CHECK5-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META42]], !align [[META43]]
+// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META43]], !align [[META44]]
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
// CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
@@ -5610,7 +5610,7 @@ int bar(int n){
// CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
// CHECK5-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
-// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META42]], !align [[META43]]
+// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META43]], !align [[META44]]
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
@@ -5655,42 +5655,42 @@ int bar(int n){
// CHECK5-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 4
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK5: omp.inner.for.cond:
-// CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP54:![0-9]+]]
-// CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP54]]
+// CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP55:![0-9]+]]
+// CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP55]]
// CHECK5-NEXT: [[ADD7:%.*]] = add i32 [[TMP17]], 1
// CHECK5-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]]
// CHECK5-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body:
-// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP54]]
-// CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP54]]
+// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP55]]
+// CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP55]]
// CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK5-NEXT: [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]]
-// CHECK5-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP54]]
-// CHECK5-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP54]]
+// CHECK5-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP55]]
+// CHECK5-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP55]]
// CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1
-// CHECK5-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP54]]
-// CHECK5-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP54]]
+// CHECK5-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP55]]
+// CHECK5-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP55]]
// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP21]] to i32
// CHECK5-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV]], 1
// CHECK5-NEXT: [[CONV12:%.*]] = trunc i32 [[ADD11]] to i16
-// CHECK5-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP54]]
-// CHECK5-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP54]]
+// CHECK5-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP55]]
+// CHECK5-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP55]]
// CHECK5-NEXT: [[CONV13:%.*]] = sext i8 [[TMP22]] to i32
// CHECK5-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1
// CHECK5-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8
-// CHECK5-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP54]]
+// CHECK5-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP55]]
// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2
-// CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP54]]
+// CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP55]]
// CHECK5-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1
-// CHECK5-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP54]]
+// CHECK5-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP55]]
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK5: omp.body.continue:
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK5: omp.inner.for.inc:
-// CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP54]]
+// CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP55]]
// CHECK5-NEXT: [[ADD17:%.*]] = add i32 [[TMP24]], 1
-// CHECK5-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP54]]
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP55:![0-9]+]]
+// CHECK5-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP55]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP56:![0-9]+]]
// CHECK5: omp.inner.for.end:
// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK5: omp.loop.exit:
@@ -5731,7 +5731,7 @@ int bar(int n){
// CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META42]], !align [[META43]]
+// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META43]], !align [[META44]]
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK5-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
// CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
@@ -5762,7 +5762,7 @@ int bar(int n){
// CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
// CHECK5-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
// CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
-// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META42]], !align [[META43]]
+// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META43]], !align [[META44]]
// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK5-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -5785,35 +5785,35 @@ int bar(int n){
// CHECK5-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK5: omp.inner.for.cond:
-// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP57:![0-9]+]]
-// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP57]]
+// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP58:![0-9]+]]
+// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP58]]
// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK5: omp.inner.for.body:
-// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP57]]
+// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP58]]
// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP57]]
-// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP57]]
+// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP58]]
+// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP58]]
// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK5-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP57]]
-// CHECK5-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP57]]
+// CHECK5-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP58]]
+// CHECK5-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP58]]
// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32
// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
// CHECK5-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK5-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP57]]
+// CHECK5-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP58]]
// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2
-// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP57]]
+// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP58]]
// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK5-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP57]]
+// CHECK5-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP58]]
// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK5: omp.body.continue:
// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK5: omp.inner.for.inc:
-// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP57]]
+// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP58]]
// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1
-// CHECK5-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP57]]
-// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP58:![0-9]+]]
+// CHECK5-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP58]]
+// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP59:![0-9]+]]
// CHECK5: omp.inner.for.end:
// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK5: omp.loop.exit:
@@ -6355,7 +6355,7 @@ int bar(int n){
// CHECK7-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias [[META33]]
// CHECK7-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias [[META33]]
// CHECK7-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias [[META33]]
-// CHECK7-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
+// CHECK7-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]], !inline_history [[META34:![0-9]+]]
// CHECK7-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias [[META33]]
// CHECK7-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias [[META33]]
// CHECK7-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias [[META33]]
@@ -6469,10 +6469,10 @@ int bar(int n){
// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK7-NEXT: store i32 [[ADD]], ptr [[A1]], align 4, !nontemporal [[META34:![0-9]+]]
-// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A1]], align 4, !nontemporal [[META34]]
+// CHECK7-NEXT: store i32 [[ADD]], ptr [[A1]], align 4, !nontemporal [[META35:![0-9]+]]
+// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A1]], align 4, !nontemporal [[META35]]
// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK7-NEXT: store i32 [[ADD3]], ptr [[A1]], align 4, !nontemporal [[META34]]
+// CHECK7-NEXT: store i32 [[ADD3]], ptr [[A1]], align 4, !nontemporal [[META35]]
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK7: omp.body.continue:
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
@@ -6480,7 +6480,7 @@ int bar(int n){
// CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
// CHECK7-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
-// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]]
+// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]]
// CHECK7: omp.inner.for.end:
// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK7: omp.loop.exit:
@@ -6548,28 +6548,28 @@ int bar(int n){
// CHECK7-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK7: omp.inner.for.cond:
-// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37:![0-9]+]]
-// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP37]]
+// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38:![0-9]+]]
+// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP38]]
// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK7: omp.inner.for.body:
-// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]]
+// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]]
// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP37]]
-// CHECK7-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP37]]
+// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP38]]
+// CHECK7-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP38]]
// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i32
// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
// CHECK7-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
-// CHECK7-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP37]]
+// CHECK7-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP38]]
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK7: omp.body.continue:
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK7: omp.inner.for.inc:
-// CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]]
+// CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]]
// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK7-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]]
-// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]]
+// CHECK7-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]]
+// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]]
// CHECK7: omp.inner.for.end:
// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK7: omp.loop.exit:
@@ -6645,31 +6645,31 @@ int bar(int n){
// CHECK7-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK7: omp.inner.for.cond:
-// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40:![0-9]+]]
-// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP40]]
+// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP41:![0-9]+]]
+// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP41]]
// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK7: omp.inner.for.body:
-// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]]
+// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP41]]
// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP40]]
-// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP40]]
+// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP41]]
+// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP41]]
// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK7-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP40]]
-// CHECK7-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP40]]
+// CHECK7-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP41]]
+// CHECK7-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP41]]
// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32
// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
// CHECK7-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK7-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP40]]
+// CHECK7-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP41]]
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK7: omp.body.continue:
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK7: omp.inner.for.inc:
-// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]]
+// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP41]]
// CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK7-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]]
-// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]]
+// CHECK7-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP41]]
+// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP42:![0-9]+]]
// CHECK7: omp.inner.for.end:
// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK7: omp.loop.exit:
@@ -6708,14 +6708,14 @@ int bar(int n){
// CHECK7-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4
// CHECK7-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
// CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META43:![0-9]+]], !align [[META44:![0-9]+]]
+// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META44:![0-9]+]], !align [[META45:![0-9]+]]
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
-// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4, !nonnull [[META43]], !align [[META44]]
-// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META43]], !align [[META44]]
+// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4, !nonnull [[META44]], !align [[META45]]
+// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META44]], !align [[META45]]
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
-// CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4, !nonnull [[META43]], !align [[META44]]
-// CHECK7-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META43]], !align [[META44]]
+// CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4, !nonnull [[META44]], !align [[META45]]
+// CHECK7-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META44]], !align [[META45]]
// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK7-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
// CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
@@ -6755,14 +6755,14 @@ int bar(int n){
// CHECK7-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
// CHECK7-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4
// CHECK7-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
-// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META43]], !align [[META44]]
+// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META44]], !align [[META45]]
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
-// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4, !nonnull [[META43]], !align [[META44]]
-// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META43]], !align [[META44]]
+// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4, !nonnull [[META44]], !align [[META45]]
+// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META44]], !align [[META45]]
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
-// CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4, !nonnull [[META43]], !align [[META44]]
-// CHECK7-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META43]], !align [[META44]]
+// CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4, !nonnull [[META44]], !align [[META45]]
+// CHECK7-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META44]], !align [[META45]]
// CHECK7-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 0
// CHECK7-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[ARRAYDECAY]], i32 16) ]
// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
@@ -6787,59 +6787,59 @@ int bar(int n){
// CHECK7-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK7: omp.inner.for.cond:
-// CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45:![0-9]+]]
-// CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP45]]
+// CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP46:![0-9]+]]
+// CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP46]]
// CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
// CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK7: omp.inner.for.body:
-// CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]
+// CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP46]]
// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP45]]
-// CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]]
+// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP46]]
+// CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP46]]
// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
-// CHECK7-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]]
+// CHECK7-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP46]]
// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2
-// CHECK7-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]]
+// CHECK7-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP46]]
// CHECK7-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double
// CHECK7-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00
// CHECK7-NEXT: [[CONV8:%.*]] = fptrunc double [[ADD7]] to float
-// CHECK7-NEXT: store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]]
+// CHECK7-NEXT: store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP46]]
// CHECK7-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3
-// CHECK7-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP45]]
+// CHECK7-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP46]]
// CHECK7-NEXT: [[CONV10:%.*]] = fpext float [[TMP18]] to double
// CHECK7-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00
// CHECK7-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float
-// CHECK7-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP45]]
+// CHECK7-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP46]]
// CHECK7-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1
// CHECK7-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i32 0, i32 2
-// CHECK7-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP45]]
+// CHECK7-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP46]]
// CHECK7-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00
-// CHECK7-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP45]]
+// CHECK7-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP46]]
// CHECK7-NEXT: [[TMP20:%.*]] = mul nsw i32 1, [[TMP5]]
// CHECK7-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP20]]
// CHECK7-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX16]], i32 3
-// CHECK7-NEXT: [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP45]]
+// CHECK7-NEXT: [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP46]]
// CHECK7-NEXT: [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00
-// CHECK7-NEXT: store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP45]]
+// CHECK7-NEXT: store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP46]]
// CHECK7-NEXT: [[X:%.*]] = getelementptr inbounds nuw [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
-// CHECK7-NEXT: [[TMP22:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP45]]
+// CHECK7-NEXT: [[TMP22:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP46]]
// CHECK7-NEXT: [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1
-// CHECK7-NEXT: store i64 [[ADD19]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP45]]
+// CHECK7-NEXT: store i64 [[ADD19]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP46]]
// CHECK7-NEXT: [[Y:%.*]] = getelementptr inbounds nuw [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
-// CHECK7-NEXT: [[TMP23:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP45]]
+// CHECK7-NEXT: [[TMP23:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP46]]
// CHECK7-NEXT: [[CONV20:%.*]] = sext i8 [[TMP23]] to i32
// CHECK7-NEXT: [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1
// CHECK7-NEXT: [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8
-// CHECK7-NEXT: store i8 [[CONV22]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP45]]
+// CHECK7-NEXT: store i8 [[CONV22]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP46]]
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK7: omp.body.continue:
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK7: omp.inner.for.inc:
-// CHECK7-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]
+// CHECK7-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP46]]
// CHECK7-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1
-// CHECK7-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]
-// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]]
+// CHECK7-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP46]]
+// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP47:![0-9]+]]
// CHECK7: omp.inner.for.end:
// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK7: omp.loop.exit:
@@ -7285,7 +7285,7 @@ int bar(int n){
// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
-// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META43]], !align [[META48:![0-9]+]]
+// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META44]], !align [[META49:![0-9]+]]
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
// CHECK7-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
@@ -7327,7 +7327,7 @@ int bar(int n){
// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
-// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META43]], !align [[META48]]
+// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4, !nonnull [[META44]], !align [[META49]]
// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK7-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
// CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -7354,37 +7354,37 @@ int bar(int n){
// CHECK7: omp_if.then:
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK7: omp.inner.for.cond:
-// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP49:![0-9]+]]
-// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP49]]
+// CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP50:![0-9]+]]
+// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP50]]
// CHECK7-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
// CHECK7-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK7: omp.inner.for.body:
-// CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP49]]
+// CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP50]]
// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP49]]
-// CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP49]]
+// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP50]]
+// CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP50]]
// CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP13]] to double
// CHECK7-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
// CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
-// CHECK7-NEXT: store double [[ADD4]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP49]]
+// CHECK7-NEXT: store double [[ADD4]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP50]]
// CHECK7-NEXT: [[A5:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
-// CHECK7-NEXT: [[TMP14:%.*]] = load double, ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP49]]
+// CHECK7-NEXT: [[TMP14:%.*]] = load double, ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP50]]
// CHECK7-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
-// CHECK7-NEXT: store double [[INC]], ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP49]]
+// CHECK7-NEXT: store double [[INC]], ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP50]]
// CHECK7-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
// CHECK7-NEXT: [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]]
// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP15]]
// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
-// CHECK7-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP49]]
+// CHECK7-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP50]]
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK7: omp.body.continue:
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK7: omp.inner.for.inc:
-// CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP49]]
+// CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP50]]
// CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP16]], 1
-// CHECK7-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP49]]
-// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP50:![0-9]+]]
+// CHECK7-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP50]]
+// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP51:![0-9]+]]
// CHECK7: omp.inner.for.end:
// CHECK7-NEXT: br label [[OMP_IF_END:%.*]]
// CHECK7: omp_if.else:
@@ -7420,7 +7420,7 @@ int bar(int n){
// CHECK7-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// CHECK7-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP23]], 1
// CHECK7-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4
-// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP52:![0-9]+]]
+// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP53:![0-9]+]]
// CHECK7: omp.inner.for.end25:
// CHECK7-NEXT: br label [[OMP_IF_END]]
// CHECK7: omp_if.end:
@@ -7456,7 +7456,7 @@ int bar(int n){
// CHECK7-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
// CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
// CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META43]], !align [[META44]]
+// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META44]], !align [[META45]]
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK7-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
@@ -7501,7 +7501,7 @@ int bar(int n){
// CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
// CHECK7-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
// CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
-// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META43]], !align [[META44]]
+// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META44]], !align [[META45]]
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK7-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
@@ -7546,42 +7546,42 @@ int bar(int n){
// CHECK7-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 4
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK7: omp.inner.for.cond:
-// CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP54:![0-9]+]]
-// CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP54]]
+// CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP55:![0-9]+]]
+// CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP55]]
// CHECK7-NEXT: [[ADD7:%.*]] = add i32 [[TMP17]], 1
// CHECK7-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]]
// CHECK7-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK7: omp.inner.for.body:
-// CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP54]]
-// CHECK7-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP54]]
+// CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP55]]
+// CHECK7-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP55]]
// CHECK7-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
// CHECK7-NEXT: [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]]
-// CHECK7-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP54]]
-// CHECK7-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP54]]
+// CHECK7-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP55]]
+// CHECK7-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP55]]
// CHECK7-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1
-// CHECK7-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP54]]
-// CHECK7-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP54]]
+// CHECK7-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP55]]
+// CHECK7-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP55]]
// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP21]] to i32
// CHECK7-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV]], 1
// CHECK7-NEXT: [[CONV12:%.*]] = trunc i32 [[ADD11]] to i16
-// CHECK7-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP54]]
-// CHECK7-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP54]]
+// CHECK7-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP55]]
+// CHECK7-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP55]]
// CHECK7-NEXT: [[CONV13:%.*]] = sext i8 [[TMP22]] to i32
// CHECK7-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1
// CHECK7-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8
-// CHECK7-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP54]]
+// CHECK7-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP55]]
// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2
-// CHECK7-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP54]]
+// CHECK7-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP55]]
// CHECK7-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1
-// CHECK7-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP54]]
+// CHECK7-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP55]]
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK7: omp.body.continue:
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK7: omp.inner.for.inc:
-// CHECK7-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP54]]
+// CHECK7-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP55]]
// CHECK7-NEXT: [[ADD17:%.*]] = add i32 [[TMP24]], 1
-// CHECK7-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP54]]
-// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP55:![0-9]+]]
+// CHECK7-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP55]]
+// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP56:![0-9]+]]
// CHECK7: omp.inner.for.end:
// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK7: omp.loop.exit:
@@ -7622,7 +7622,7 @@ int bar(int n){
// CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
// CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
// CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META43]], !align [[META44]]
+// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META44]], !align [[META45]]
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK7-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
@@ -7653,7 +7653,7 @@ int bar(int n){
// CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK7-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
// CHECK7-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
-// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META43]], !align [[META44]]
+// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META44]], !align [[META45]]
// CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK7-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
// CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -7676,35 +7676,35 @@ int bar(int n){
// CHECK7-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK7: omp.inner.for.cond:
-// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP57:![0-9]+]]
-// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP57]]
+// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP58:![0-9]+]]
+// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP58]]
// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK7: omp.inner.for.body:
-// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP57]]
+// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP58]]
// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP57]]
-// CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP57]]
+// CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP58]]
+// CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP58]]
// CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
-// CHECK7-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP57]]
-// CHECK7-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP57]]
+// CHECK7-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP58]]
+// CHECK7-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP58]]
// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32
// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
// CHECK7-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
-// CHECK7-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP57]]
+// CHECK7-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP58]]
// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2
-// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP57]]
+// CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP58]]
// CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK7-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP57]]
+// CHECK7-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP58]]
// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK7: omp.body.continue:
// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK7: omp.inner.for.inc:
-// CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP57]]
+// CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP58]]
// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1
-// CHECK7-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP57]]
-// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP58:![0-9]+]]
+// CHECK7-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP58]]
+// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP59:![0-9]+]]
// CHECK7: omp.inner.for.end:
// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK7: omp.loop.exit:
@@ -9863,25 +9863,29 @@ int bar(int n){
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK17-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 8
-// CHECK17-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
-// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
-// CHECK17-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
+// CHECK17-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK17-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
+// CHECK17-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
+// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK17-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 8
-// CHECK17-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
-// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8
+// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 8
+// CHECK17-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK17-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP11]], align 8
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 8
-// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK17-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP8]], i32 [[TMP9]])
-// CHECK17-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK17-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
-// CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined, i64 [[TMP11]])
+// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK17-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP12]], i32 [[TMP13]])
+// CHECK17-NEXT: [[TMP14:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK17-NEXT: store i16 [[TMP14]], ptr [[AA_CASTED]], align 2
+// CHECK17-NEXT: [[TMP15:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined, i64 [[TMP15]])
// CHECK17-NEXT: ret void
//
//
@@ -9963,16 +9967,18 @@ int bar(int n){
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK17-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 8
-// CHECK17-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
-// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 8
+// CHECK17-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
+// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 8
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK17-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK17-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
-// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i64 [[TMP4]])
+// CHECK17-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK17-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 2
+// CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i64 [[TMP6]])
// CHECK17-NEXT: ret void
//
//
@@ -10061,22 +10067,25 @@ int bar(int n){
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK17-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK17-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
-// CHECK17-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK17-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK17-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK17-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 8
+// CHECK17-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK17-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 8
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
-// CHECK17-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4
-// CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK17-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK17-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
-// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i64 [[TMP6]], i64 [[TMP8]])
+// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
+// CHECK17-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
+// CHECK17-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK17-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK17-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
+// CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i64 [[TMP9]], i64 [[TMP11]])
// CHECK17-NEXT: ret void
//
//
@@ -10168,32 +10177,42 @@ int bar(int n){
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK17-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK17-NEXT: [[B:%.*]] = load ptr, ptr [[TMP3]], align 8
-// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8
-// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK17-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP6]], align 8
-// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK17-NEXT: [[C:%.*]] = load ptr, ptr [[TMP7]], align 8
-// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
-// CHECK17-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8
-// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 6
-// CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
-// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 7
-// CHECK17-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP12]], align 8
-// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 8
-// CHECK17-NEXT: [[D:%.*]] = load ptr, ptr [[TMP13]], align 8
-// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 9
-// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK17-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK17-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK17-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 8
+// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK17-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
+// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP7]], align 8
+// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8
+// CHECK17-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP10]], align 8
+// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK17-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8
+// CHECK17-NEXT: [[C:%.*]] = load ptr, ptr [[TMP12]], align 8
+// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK17-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8
+// CHECK17-NEXT: [[TMP15:%.*]] = load i64, ptr [[TMP14]], align 8
+// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 6
+// CHECK17-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8
+// CHECK17-NEXT: [[TMP18:%.*]] = load i64, ptr [[TMP17]], align 8
+// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 7
+// CHECK17-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8
+// CHECK17-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP20]], align 8
+// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 8
+// CHECK17-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 8
+// CHECK17-NEXT: [[D:%.*]] = load ptr, ptr [[TMP22]], align 8
+// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 9
+// CHECK17-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP23]], align 8
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK17-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4
-// CHECK17-NEXT: store i32 [[TMP14]], ptr [[A_CASTED]], align 4
-// CHECK17-NEXT: [[TMP15:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined, i64 [[TMP15]], ptr [[B]], i64 [[TMP5]], ptr [[BN]], ptr [[C]], i64 [[TMP9]], i64 [[TMP11]], ptr [[CN]], ptr [[D]])
+// CHECK17-NEXT: [[TMP24:%.*]] = load i32, ptr [[A]], align 4
+// CHECK17-NEXT: store i32 [[TMP24]], ptr [[A_CASTED]], align 4
+// CHECK17-NEXT: [[TMP25:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined, i64 [[TMP25]], ptr [[B]], i64 [[TMP8]], ptr [[BN]], ptr [[C]], i64 [[TMP15]], i64 [[TMP18]], ptr [[CN]], ptr [[D]])
// CHECK17-NEXT: ret void
//
//
@@ -10343,36 +10362,42 @@ int bar(int n){
// CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK17-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
-// CHECK17-NEXT: store i32 [[TMP4]], ptr [[N]], align 4
-// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK17-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 8
-// CHECK17-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
-// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK17-NEXT: [[TMP8:%.*]] = load i8, ptr [[TMP7]], align 8
-// CHECK17-NEXT: store i8 [[TMP8]], ptr [[AAA]], align 1
-// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK17-NEXT: [[B:%.*]] = load ptr, ptr [[TMP9]], align 8
-// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
-// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK17-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK17-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 8
+// CHECK17-NEXT: store i32 [[TMP6]], ptr [[N]], align 4
+// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK17-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8
+// CHECK17-NEXT: [[TMP9:%.*]] = load i16, ptr [[TMP8]], align 8
+// CHECK17-NEXT: store i16 [[TMP9]], ptr [[AA]], align 2
+// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK17-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8
+// CHECK17-NEXT: [[TMP12:%.*]] = load i8, ptr [[TMP11]], align 8
+// CHECK17-NEXT: store i8 [[TMP12]], ptr [[AAA]], align 1
+// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK17-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8
+// CHECK17-NEXT: [[B:%.*]] = load ptr, ptr [[TMP14]], align 8
+// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK17-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP15]], align 8
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
-// CHECK17-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
-// CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[N]], align 4
-// CHECK17-NEXT: store i32 [[TMP12]], ptr [[N_CASTED]], align 4
-// CHECK17-NEXT: [[TMP13:%.*]] = load i64, ptr [[N_CASTED]], align 8
-// CHECK17-NEXT: [[TMP14:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK17-NEXT: store i16 [[TMP14]], ptr [[AA_CASTED]], align 2
-// CHECK17-NEXT: [[TMP15:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK17-NEXT: [[TMP16:%.*]] = load i8, ptr [[AAA]], align 1
-// CHECK17-NEXT: store i8 [[TMP16]], ptr [[AAA_CASTED]], align 1
-// CHECK17-NEXT: [[TMP17:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
-// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined, i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]], ptr [[B]])
+// CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[A]], align 4
+// CHECK17-NEXT: store i32 [[TMP16]], ptr [[A_CASTED]], align 4
+// CHECK17-NEXT: [[TMP17:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK17-NEXT: [[TMP18:%.*]] = load i32, ptr [[N]], align 4
+// CHECK17-NEXT: store i32 [[TMP18]], ptr [[N_CASTED]], align 4
+// CHECK17-NEXT: [[TMP19:%.*]] = load i64, ptr [[N_CASTED]], align 8
+// CHECK17-NEXT: [[TMP20:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK17-NEXT: store i16 [[TMP20]], ptr [[AA_CASTED]], align 2
+// CHECK17-NEXT: [[TMP21:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK17-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA]], align 1
+// CHECK17-NEXT: store i8 [[TMP22]], ptr [[AAA_CASTED]], align 1
+// CHECK17-NEXT: [[TMP23:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
+// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined, i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP23]], ptr [[B]])
// CHECK17-NEXT: ret void
//
//
@@ -10521,24 +10546,30 @@ int bar(int n){
// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK17-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 8
-// CHECK17-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK17-NEXT: store i32 [[TMP3]], ptr [[B]], align 4
-// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8
-// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK17-NEXT: [[TMP7:%.*]] = load i64, ptr [[TMP6]], align 8
-// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK17-NEXT: [[C:%.*]] = load ptr, ptr [[TMP8]], align 8
-// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
-// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK17-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
+// CHECK17-NEXT: store i32 [[TMP5]], ptr [[B]], align 4
+// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK17-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
+// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP7]], align 8
+// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8
+// CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
+// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8
+// CHECK17-NEXT: [[C:%.*]] = load ptr, ptr [[TMP13]], align 8
+// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK17-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP14]], align 8
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4
-// CHECK17-NEXT: store i32 [[TMP9]], ptr [[B_CASTED]], align 4
-// CHECK17-NEXT: [[TMP10:%.*]] = load i64, ptr [[B_CASTED]], align 8
-// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined, ptr [[THIS]], i64 [[TMP10]], i64 [[TMP5]], i64 [[TMP7]], ptr [[C]])
+// CHECK17-NEXT: [[TMP15:%.*]] = load i32, ptr [[B]], align 4
+// CHECK17-NEXT: store i32 [[TMP15]], ptr [[B_CASTED]], align 4
+// CHECK17-NEXT: [[TMP16:%.*]] = load i64, ptr [[B_CASTED]], align 8
+// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined, ptr [[THIS]], i64 [[TMP16]], i64 [[TMP8]], i64 [[TMP11]], ptr [[C]])
// CHECK17-NEXT: ret void
//
//
@@ -10648,24 +10679,28 @@ int bar(int n){
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK17-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK17-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
-// CHECK17-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK17-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 8
-// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK17-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK17-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK17-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 8
+// CHECK17-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK17-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8
+// CHECK17-NEXT: [[B:%.*]] = load ptr, ptr [[TMP8]], align 8
+// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP9]], align 8
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// CHECK17-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4
-// CHECK17-NEXT: [[TMP7:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK17-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK17-NEXT: store i16 [[TMP8]], ptr [[AA_CASTED]], align 2
-// CHECK17-NEXT: [[TMP9:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined, i64 [[TMP7]], i64 [[TMP9]], ptr [[B]])
+// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
+// CHECK17-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
+// CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK17-NEXT: [[TMP12:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK17-NEXT: store i16 [[TMP12]], ptr [[AA_CASTED]], align 2
+// CHECK17-NEXT: [[TMP13:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined, i64 [[TMP11]], i64 [[TMP13]], ptr [[B]])
// CHECK17-NEXT: ret void
//
//
@@ -10767,25 +10802,29 @@ int bar(int n){
// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK19-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK19-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 4
-// CHECK19-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
-// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK19-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
+// CHECK19-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK19-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
+// CHECK19-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
+// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK19-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
-// CHECK19-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
-// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK19-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 4
+// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
+// CHECK19-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK19-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP11]], align 4
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 4
-// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK19-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP8]], i32 [[TMP9]])
-// CHECK19-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK19-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
-// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined, i32 [[TMP11]])
+// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK19-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP12]], i32 [[TMP13]])
+// CHECK19-NEXT: [[TMP14:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK19-NEXT: store i16 [[TMP14]], ptr [[AA_CASTED]], align 2
+// CHECK19-NEXT: [[TMP15:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined, i32 [[TMP15]])
// CHECK19-NEXT: ret void
//
//
@@ -10867,16 +10906,18 @@ int bar(int n){
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK19-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 4
-// CHECK19-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
-// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 4
+// CHECK19-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
+// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 4
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK19-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK19-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
-// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i32 [[TMP4]])
+// CHECK19-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK19-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 2
+// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i32 [[TMP6]])
// CHECK19-NEXT: ret void
//
//
@@ -10965,22 +11006,25 @@ int bar(int n){
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK19-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK19-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
-// CHECK19-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK19-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK19-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK19-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 4
+// CHECK19-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 4
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
-// CHECK19-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK19-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
-// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i32 [[TMP6]], i32 [[TMP8]])
+// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
+// CHECK19-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
+// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK19-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK19-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
+// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i32 [[TMP9]], i32 [[TMP11]])
// CHECK19-NEXT: ret void
//
//
@@ -11072,32 +11116,42 @@ int bar(int n){
// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK19-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK19-NEXT: [[B:%.*]] = load ptr, ptr [[TMP3]], align 4
-// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK19-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP6]], align 4
-// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK19-NEXT: [[C:%.*]] = load ptr, ptr [[TMP7]], align 4
-// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
-// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
-// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 6
-// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
-// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 7
-// CHECK19-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP12]], align 4
-// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 8
-// CHECK19-NEXT: [[D:%.*]] = load ptr, ptr [[TMP13]], align 4
-// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 9
-// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK19-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK19-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK19-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 4
+// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
+// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
+// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK19-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4
+// CHECK19-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP10]], align 4
+// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK19-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 4
+// CHECK19-NEXT: [[C:%.*]] = load ptr, ptr [[TMP12]], align 4
+// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK19-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 4
+// CHECK19-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4
+// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 6
+// CHECK19-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 4
+// CHECK19-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4
+// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 7
+// CHECK19-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 4
+// CHECK19-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP20]], align 4
+// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 8
+// CHECK19-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 4
+// CHECK19-NEXT: [[D:%.*]] = load ptr, ptr [[TMP22]], align 4
+// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 9
+// CHECK19-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP23]], align 4
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK19-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4
-// CHECK19-NEXT: store i32 [[TMP14]], ptr [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP15:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined, i32 [[TMP15]], ptr [[B]], i32 [[TMP5]], ptr [[BN]], ptr [[C]], i32 [[TMP9]], i32 [[TMP11]], ptr [[CN]], ptr [[D]])
+// CHECK19-NEXT: [[TMP24:%.*]] = load i32, ptr [[A]], align 4
+// CHECK19-NEXT: store i32 [[TMP24]], ptr [[A_CASTED]], align 4
+// CHECK19-NEXT: [[TMP25:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined, i32 [[TMP25]], ptr [[B]], i32 [[TMP8]], ptr [[BN]], ptr [[C]], i32 [[TMP15]], i32 [[TMP18]], ptr [[CN]], ptr [[D]])
// CHECK19-NEXT: ret void
//
//
@@ -11247,36 +11301,42 @@ int bar(int n){
// CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK19-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-// CHECK19-NEXT: store i32 [[TMP4]], ptr [[N]], align 4
-// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK19-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 4
-// CHECK19-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
-// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK19-NEXT: [[TMP8:%.*]] = load i8, ptr [[TMP7]], align 4
-// CHECK19-NEXT: store i8 [[TMP8]], ptr [[AAA]], align 1
-// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK19-NEXT: [[B:%.*]] = load ptr, ptr [[TMP9]], align 4
-// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
-// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK19-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK19-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
+// CHECK19-NEXT: store i32 [[TMP6]], ptr [[N]], align 4
+// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK19-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4
+// CHECK19-NEXT: [[TMP9:%.*]] = load i16, ptr [[TMP8]], align 4
+// CHECK19-NEXT: store i16 [[TMP9]], ptr [[AA]], align 2
+// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK19-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 4
+// CHECK19-NEXT: [[TMP12:%.*]] = load i8, ptr [[TMP11]], align 4
+// CHECK19-NEXT: store i8 [[TMP12]], ptr [[AAA]], align 1
+// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK19-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 4
+// CHECK19-NEXT: [[B:%.*]] = load ptr, ptr [[TMP14]], align 4
+// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK19-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP15]], align 4
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
-// CHECK19-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[N]], align 4
-// CHECK19-NEXT: store i32 [[TMP12]], ptr [[N_CASTED]], align 4
-// CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[N_CASTED]], align 4
-// CHECK19-NEXT: [[TMP14:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK19-NEXT: store i16 [[TMP14]], ptr [[AA_CASTED]], align 2
-// CHECK19-NEXT: [[TMP15:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK19-NEXT: [[TMP16:%.*]] = load i8, ptr [[AAA]], align 1
-// CHECK19-NEXT: store i8 [[TMP16]], ptr [[AAA_CASTED]], align 1
-// CHECK19-NEXT: [[TMP17:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
-// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined, i32 [[TMP11]], i32 [[TMP13]], i32 [[TMP15]], i32 [[TMP17]], ptr [[B]])
+// CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[A]], align 4
+// CHECK19-NEXT: store i32 [[TMP16]], ptr [[A_CASTED]], align 4
+// CHECK19-NEXT: [[TMP17:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK19-NEXT: [[TMP18:%.*]] = load i32, ptr [[N]], align 4
+// CHECK19-NEXT: store i32 [[TMP18]], ptr [[N_CASTED]], align 4
+// CHECK19-NEXT: [[TMP19:%.*]] = load i32, ptr [[N_CASTED]], align 4
+// CHECK19-NEXT: [[TMP20:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK19-NEXT: store i16 [[TMP20]], ptr [[AA_CASTED]], align 2
+// CHECK19-NEXT: [[TMP21:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK19-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA]], align 1
+// CHECK19-NEXT: store i8 [[TMP22]], ptr [[AAA_CASTED]], align 1
+// CHECK19-NEXT: [[TMP23:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
+// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined, i32 [[TMP17]], i32 [[TMP19]], i32 [[TMP21]], i32 [[TMP23]], ptr [[B]])
// CHECK19-NEXT: ret void
//
//
@@ -11425,24 +11485,30 @@ int bar(int n){
// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK19-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 4
-// CHECK19-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK19-NEXT: store i32 [[TMP3]], ptr [[B]], align 4
-// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
+// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK19-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
-// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK19-NEXT: [[C:%.*]] = load ptr, ptr [[TMP8]], align 4
-// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
-// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: store i32 [[TMP5]], ptr [[B]], align 4
+// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
+// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
+// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK19-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4
+// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
+// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK19-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 4
+// CHECK19-NEXT: [[C:%.*]] = load ptr, ptr [[TMP13]], align 4
+// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK19-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP14]], align 4
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4
-// CHECK19-NEXT: store i32 [[TMP9]], ptr [[B_CASTED]], align 4
-// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[B_CASTED]], align 4
-// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined, ptr [[THIS]], i32 [[TMP10]], i32 [[TMP5]], i32 [[TMP7]], ptr [[C]])
+// CHECK19-NEXT: [[TMP15:%.*]] = load i32, ptr [[B]], align 4
+// CHECK19-NEXT: store i32 [[TMP15]], ptr [[B_CASTED]], align 4
+// CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[B_CASTED]], align 4
+// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined, ptr [[THIS]], i32 [[TMP16]], i32 [[TMP8]], i32 [[TMP11]], ptr [[C]])
// CHECK19-NEXT: ret void
//
//
@@ -11552,24 +11618,28 @@ int bar(int n){
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK19-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK19-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK19-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
-// CHECK19-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK19-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 4
-// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK19-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK19-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK19-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 4
+// CHECK19-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK19-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4
+// CHECK19-NEXT: [[B:%.*]] = load ptr, ptr [[TMP8]], align 4
+// CHECK19-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK19-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK19-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP9]], align 4
// CHECK19-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// CHECK19-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK19-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK19-NEXT: store i16 [[TMP8]], ptr [[AA_CASTED]], align 2
-// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined, i32 [[TMP7]], i32 [[TMP9]], ptr [[B]])
+// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
+// CHECK19-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
+// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK19-NEXT: [[TMP12:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK19-NEXT: store i16 [[TMP12]], ptr [[AA_CASTED]], align 2
+// CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined, i32 [[TMP11]], i32 [[TMP13]], ptr [[B]])
// CHECK19-NEXT: ret void
//
//
@@ -11671,25 +11741,29 @@ int bar(int n){
// CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK21-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK21-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK21-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 8
-// CHECK21-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
-// CHECK21-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
-// CHECK21-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK21-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
+// CHECK21-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK21-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK21-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
+// CHECK21-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
+// CHECK21-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK21-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 8
-// CHECK21-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
-// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK21-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK21-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8
+// CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 8
+// CHECK21-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK21-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP11]], align 8
// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 8
-// CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK21-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP8]], i32 [[TMP9]])
-// CHECK21-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK21-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
-// CHECK21-NEXT: [[TMP11:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined, i64 [[TMP11]])
+// CHECK21-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK21-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK21-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP12]], i32 [[TMP13]])
+// CHECK21-NEXT: [[TMP14:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK21-NEXT: store i16 [[TMP14]], ptr [[AA_CASTED]], align 2
+// CHECK21-NEXT: [[TMP15:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined, i64 [[TMP15]])
// CHECK21-NEXT: ret void
//
//
@@ -11771,16 +11845,18 @@ int bar(int n){
// CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK21-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 8
-// CHECK21-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
-// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK21-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 8
+// CHECK21-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
+// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK21-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 8
// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK21-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK21-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
-// CHECK21-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i64 [[TMP4]])
+// CHECK21-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK21-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 2
+// CHECK21-NEXT: [[TMP6:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i64 [[TMP6]])
// CHECK21-NEXT: ret void
//
//
@@ -11869,22 +11945,25 @@ int bar(int n){
// CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK21-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK21-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK21-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
-// CHECK21-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK21-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK21-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK21-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK21-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 8
+// CHECK21-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK21-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 8
// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
-// CHECK21-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4
-// CHECK21-NEXT: [[TMP6:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK21-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK21-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
-// CHECK21-NEXT: [[TMP8:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i64 [[TMP6]], i64 [[TMP8]])
+// CHECK21-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
+// CHECK21-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
+// CHECK21-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK21-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK21-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
+// CHECK21-NEXT: [[TMP11:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i64 [[TMP9]], i64 [[TMP11]])
// CHECK21-NEXT: ret void
//
//
@@ -11976,32 +12055,42 @@ int bar(int n){
// CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK21-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK21-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK21-NEXT: [[B:%.*]] = load ptr, ptr [[TMP3]], align 8
-// CHECK21-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK21-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8
-// CHECK21-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK21-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP6]], align 8
-// CHECK21-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK21-NEXT: [[C:%.*]] = load ptr, ptr [[TMP7]], align 8
-// CHECK21-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
-// CHECK21-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8
-// CHECK21-NEXT: [[TMP10:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 6
-// CHECK21-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
-// CHECK21-NEXT: [[TMP12:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 7
-// CHECK21-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP12]], align 8
-// CHECK21-NEXT: [[TMP13:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 8
-// CHECK21-NEXT: [[D:%.*]] = load ptr, ptr [[TMP13]], align 8
-// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 9
-// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK21-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK21-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK21-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK21-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 8
+// CHECK21-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK21-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
+// CHECK21-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP7]], align 8
+// CHECK21-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK21-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8
+// CHECK21-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP10]], align 8
+// CHECK21-NEXT: [[TMP11:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK21-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8
+// CHECK21-NEXT: [[C:%.*]] = load ptr, ptr [[TMP12]], align 8
+// CHECK21-NEXT: [[TMP13:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK21-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8
+// CHECK21-NEXT: [[TMP15:%.*]] = load i64, ptr [[TMP14]], align 8
+// CHECK21-NEXT: [[TMP16:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 6
+// CHECK21-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8
+// CHECK21-NEXT: [[TMP18:%.*]] = load i64, ptr [[TMP17]], align 8
+// CHECK21-NEXT: [[TMP19:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 7
+// CHECK21-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8
+// CHECK21-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP20]], align 8
+// CHECK21-NEXT: [[TMP21:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 8
+// CHECK21-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 8
+// CHECK21-NEXT: [[D:%.*]] = load ptr, ptr [[TMP22]], align 8
+// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 9
+// CHECK21-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP23]], align 8
// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK21-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4
-// CHECK21-NEXT: store i32 [[TMP14]], ptr [[A_CASTED]], align 4
-// CHECK21-NEXT: [[TMP15:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined, i64 [[TMP15]], ptr [[B]], i64 [[TMP5]], ptr [[BN]], ptr [[C]], i64 [[TMP9]], i64 [[TMP11]], ptr [[CN]], ptr [[D]])
+// CHECK21-NEXT: [[TMP24:%.*]] = load i32, ptr [[A]], align 4
+// CHECK21-NEXT: store i32 [[TMP24]], ptr [[A_CASTED]], align 4
+// CHECK21-NEXT: [[TMP25:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined, i64 [[TMP25]], ptr [[B]], i64 [[TMP8]], ptr [[BN]], ptr [[C]], i64 [[TMP15]], i64 [[TMP18]], ptr [[CN]], ptr [[D]])
// CHECK21-NEXT: ret void
//
//
@@ -12151,36 +12240,42 @@ int bar(int n){
// CHECK21-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK21-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK21-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
-// CHECK21-NEXT: store i32 [[TMP4]], ptr [[N]], align 4
-// CHECK21-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK21-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 8
-// CHECK21-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
-// CHECK21-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK21-NEXT: [[TMP8:%.*]] = load i8, ptr [[TMP7]], align 8
-// CHECK21-NEXT: store i8 [[TMP8]], ptr [[AAA]], align 1
-// CHECK21-NEXT: [[TMP9:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK21-NEXT: [[B:%.*]] = load ptr, ptr [[TMP9]], align 8
-// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
-// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK21-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK21-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK21-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 8
+// CHECK21-NEXT: store i32 [[TMP6]], ptr [[N]], align 4
+// CHECK21-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK21-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8
+// CHECK21-NEXT: [[TMP9:%.*]] = load i16, ptr [[TMP8]], align 8
+// CHECK21-NEXT: store i16 [[TMP9]], ptr [[AA]], align 2
+// CHECK21-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK21-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8
+// CHECK21-NEXT: [[TMP12:%.*]] = load i8, ptr [[TMP11]], align 8
+// CHECK21-NEXT: store i8 [[TMP12]], ptr [[AAA]], align 1
+// CHECK21-NEXT: [[TMP13:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK21-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8
+// CHECK21-NEXT: [[B:%.*]] = load ptr, ptr [[TMP14]], align 8
+// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK21-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP15]], align 8
// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
-// CHECK21-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
-// CHECK21-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK21-NEXT: [[TMP12:%.*]] = load i32, ptr [[N]], align 4
-// CHECK21-NEXT: store i32 [[TMP12]], ptr [[N_CASTED]], align 4
-// CHECK21-NEXT: [[TMP13:%.*]] = load i64, ptr [[N_CASTED]], align 8
-// CHECK21-NEXT: [[TMP14:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK21-NEXT: store i16 [[TMP14]], ptr [[AA_CASTED]], align 2
-// CHECK21-NEXT: [[TMP15:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK21-NEXT: [[TMP16:%.*]] = load i8, ptr [[AAA]], align 1
-// CHECK21-NEXT: store i8 [[TMP16]], ptr [[AAA_CASTED]], align 1
-// CHECK21-NEXT: [[TMP17:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
-// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined, i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]], ptr [[B]])
+// CHECK21-NEXT: [[TMP16:%.*]] = load i32, ptr [[A]], align 4
+// CHECK21-NEXT: store i32 [[TMP16]], ptr [[A_CASTED]], align 4
+// CHECK21-NEXT: [[TMP17:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK21-NEXT: [[TMP18:%.*]] = load i32, ptr [[N]], align 4
+// CHECK21-NEXT: store i32 [[TMP18]], ptr [[N_CASTED]], align 4
+// CHECK21-NEXT: [[TMP19:%.*]] = load i64, ptr [[N_CASTED]], align 8
+// CHECK21-NEXT: [[TMP20:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK21-NEXT: store i16 [[TMP20]], ptr [[AA_CASTED]], align 2
+// CHECK21-NEXT: [[TMP21:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK21-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA]], align 1
+// CHECK21-NEXT: store i8 [[TMP22]], ptr [[AAA_CASTED]], align 1
+// CHECK21-NEXT: [[TMP23:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
+// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined, i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]], i64 [[TMP23]], ptr [[B]])
// CHECK21-NEXT: ret void
//
//
@@ -12331,34 +12426,41 @@ int bar(int n){
// CHECK21-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK21-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 8
-// CHECK21-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK21-NEXT: store i32 [[TMP3]], ptr [[B]], align 4
-// CHECK21-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK21-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 8
-// CHECK21-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK21-NEXT: [[TMP7:%.*]] = load i64, ptr [[TMP6]], align 8
-// CHECK21-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 4
-// CHECK21-NEXT: [[C:%.*]] = load ptr, ptr [[TMP8]], align 8
-// CHECK21-NEXT: [[TMP9:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 5
-// CHECK21-NEXT: [[TMP10:%.*]] = load i8, ptr [[TMP9]], align 8
-// CHECK21-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP10]], 0
+// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK21-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK21-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK21-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
+// CHECK21-NEXT: store i32 [[TMP5]], ptr [[B]], align 4
+// CHECK21-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK21-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
+// CHECK21-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP7]], align 8
+// CHECK21-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK21-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8
+// CHECK21-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
+// CHECK21-NEXT: [[TMP12:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK21-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8
+// CHECK21-NEXT: [[C:%.*]] = load ptr, ptr [[TMP13]], align 8
+// CHECK21-NEXT: [[TMP14:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK21-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 8
+// CHECK21-NEXT: [[TMP16:%.*]] = load i8, ptr [[TMP15]], align 8
+// CHECK21-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP16]], 0
// CHECK21-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i8
// CHECK21-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 1
-// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 6
-// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 6
+// CHECK21-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP17]], align 8
// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[B]], align 4
-// CHECK21-NEXT: store i32 [[TMP11]], ptr [[B_CASTED]], align 4
-// CHECK21-NEXT: [[TMP12:%.*]] = load i64, ptr [[B_CASTED]], align 8
-// CHECK21-NEXT: [[TMP13:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
-// CHECK21-NEXT: [[LOADEDV2:%.*]] = icmp ne i8 [[TMP13]], 0
+// CHECK21-NEXT: [[TMP18:%.*]] = load i32, ptr [[B]], align 4
+// CHECK21-NEXT: store i32 [[TMP18]], ptr [[B_CASTED]], align 4
+// CHECK21-NEXT: [[TMP19:%.*]] = load i64, ptr [[B_CASTED]], align 8
+// CHECK21-NEXT: [[TMP20:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
+// CHECK21-NEXT: [[LOADEDV2:%.*]] = icmp ne i8 [[TMP20]], 0
// CHECK21-NEXT: [[STOREDV3:%.*]] = zext i1 [[LOADEDV2]] to i8
// CHECK21-NEXT: store i8 [[STOREDV3]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1
-// CHECK21-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
-// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined, ptr [[THIS]], i64 [[TMP12]], i64 [[TMP5]], i64 [[TMP7]], ptr [[C]], i64 [[TMP14]])
+// CHECK21-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
+// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined, ptr [[THIS]], i64 [[TMP19]], i64 [[TMP8]], i64 [[TMP11]], ptr [[C]], i64 [[TMP21]])
// CHECK21-NEXT: ret void
//
//
@@ -12512,24 +12614,28 @@ int bar(int n){
// CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
// CHECK21-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK21-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK21-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK21-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK21-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 8
-// CHECK21-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK21-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK21-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 8
-// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK21-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK21-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK21-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK21-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 8
+// CHECK21-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK21-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK21-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8
+// CHECK21-NEXT: [[B:%.*]] = load ptr, ptr [[TMP8]], align 8
+// CHECK21-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK21-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK21-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP9]], align 8
// CHECK21-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK21-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// CHECK21-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4
-// CHECK21-NEXT: [[TMP7:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK21-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK21-NEXT: store i16 [[TMP8]], ptr [[AA_CASTED]], align 2
-// CHECK21-NEXT: [[TMP9:%.*]] = load i64, ptr [[AA_CASTED]], align 8
-// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined, i64 [[TMP7]], i64 [[TMP9]], ptr [[B]])
+// CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
+// CHECK21-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
+// CHECK21-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK21-NEXT: [[TMP12:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK21-NEXT: store i16 [[TMP12]], ptr [[AA_CASTED]], align 2
+// CHECK21-NEXT: [[TMP13:%.*]] = load i64, ptr [[AA_CASTED]], align 8
+// CHECK21-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined, i64 [[TMP11]], i64 [[TMP13]], ptr [[B]])
// CHECK21-NEXT: ret void
//
//
@@ -12631,25 +12737,29 @@ int bar(int n){
// CHECK23-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK23-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK23-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK23-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 4
-// CHECK23-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
-// CHECK23-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK23-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK23-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
+// CHECK23-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK23-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK23-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
+// CHECK23-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
+// CHECK23-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK23-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
-// CHECK23-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
-// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK23-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK23-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 4
+// CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
+// CHECK23-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK23-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP11]], align 4
// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 4
-// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK23-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP8]], i32 [[TMP9]])
-// CHECK23-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK23-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
-// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined, i32 [[TMP11]])
+// CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK23-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP12]], i32 [[TMP13]])
+// CHECK23-NEXT: [[TMP14:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK23-NEXT: store i16 [[TMP14]], ptr [[AA_CASTED]], align 2
+// CHECK23-NEXT: [[TMP15:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined, i32 [[TMP15]])
// CHECK23-NEXT: ret void
//
//
@@ -12731,16 +12841,18 @@ int bar(int n){
// CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK23-NEXT: [[TMP2:%.*]] = load i16, ptr [[TMP1]], align 4
-// CHECK23-NEXT: store i16 [[TMP2]], ptr [[AA]], align 2
-// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK23-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP2]], align 4
+// CHECK23-NEXT: store i16 [[TMP3]], ptr [[AA]], align 2
+// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK23-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 4
// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK23-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK23-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
-// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i32 [[TMP4]])
+// CHECK23-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK23-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 2
+// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i32 [[TMP6]])
// CHECK23-NEXT: ret void
//
//
@@ -12829,22 +12941,25 @@ int bar(int n){
// CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK23-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK23-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK23-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
-// CHECK23-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK23-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK23-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK23-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK23-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 4
+// CHECK23-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK23-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 4
// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
-// CHECK23-NEXT: store i32 [[TMP5]], ptr [[A_CASTED]], align 4
-// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK23-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK23-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
-// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i32 [[TMP6]], i32 [[TMP8]])
+// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
+// CHECK23-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
+// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK23-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK23-NEXT: store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
+// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i32 [[TMP9]], i32 [[TMP11]])
// CHECK23-NEXT: ret void
//
//
@@ -12936,32 +13051,42 @@ int bar(int n){
// CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK23-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK23-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK23-NEXT: [[B:%.*]] = load ptr, ptr [[TMP3]], align 4
-// CHECK23-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK23-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK23-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP6]], align 4
-// CHECK23-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK23-NEXT: [[C:%.*]] = load ptr, ptr [[TMP7]], align 4
-// CHECK23-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
-// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
-// CHECK23-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 6
-// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
-// CHECK23-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 7
-// CHECK23-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP12]], align 4
-// CHECK23-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 8
-// CHECK23-NEXT: [[D:%.*]] = load ptr, ptr [[TMP13]], align 4
-// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 9
-// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK23-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK23-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK23-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK23-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 4
+// CHECK23-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK23-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
+// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
+// CHECK23-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK23-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4
+// CHECK23-NEXT: [[BN:%.*]] = load ptr, ptr [[TMP10]], align 4
+// CHECK23-NEXT: [[TMP11:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK23-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 4
+// CHECK23-NEXT: [[C:%.*]] = load ptr, ptr [[TMP12]], align 4
+// CHECK23-NEXT: [[TMP13:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK23-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 4
+// CHECK23-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4
+// CHECK23-NEXT: [[TMP16:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 6
+// CHECK23-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 4
+// CHECK23-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4
+// CHECK23-NEXT: [[TMP19:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 7
+// CHECK23-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 4
+// CHECK23-NEXT: [[CN:%.*]] = load ptr, ptr [[TMP20]], align 4
+// CHECK23-NEXT: [[TMP21:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 8
+// CHECK23-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 4
+// CHECK23-NEXT: [[D:%.*]] = load ptr, ptr [[TMP22]], align 4
+// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 9
+// CHECK23-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP23]], align 4
// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK23-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4
-// CHECK23-NEXT: store i32 [[TMP14]], ptr [[A_CASTED]], align 4
-// CHECK23-NEXT: [[TMP15:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined, i32 [[TMP15]], ptr [[B]], i32 [[TMP5]], ptr [[BN]], ptr [[C]], i32 [[TMP9]], i32 [[TMP11]], ptr [[CN]], ptr [[D]])
+// CHECK23-NEXT: [[TMP24:%.*]] = load i32, ptr [[A]], align 4
+// CHECK23-NEXT: store i32 [[TMP24]], ptr [[A_CASTED]], align 4
+// CHECK23-NEXT: [[TMP25:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined, i32 [[TMP25]], ptr [[B]], i32 [[TMP8]], ptr [[BN]], ptr [[C]], i32 [[TMP15]], i32 [[TMP18]], ptr [[CN]], ptr [[D]])
// CHECK23-NEXT: ret void
//
//
@@ -13111,36 +13236,42 @@ int bar(int n){
// CHECK23-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK23-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK23-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-// CHECK23-NEXT: store i32 [[TMP4]], ptr [[N]], align 4
-// CHECK23-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK23-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 4
-// CHECK23-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
-// CHECK23-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK23-NEXT: [[TMP8:%.*]] = load i8, ptr [[TMP7]], align 4
-// CHECK23-NEXT: store i8 [[TMP8]], ptr [[AAA]], align 1
-// CHECK23-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK23-NEXT: [[B:%.*]] = load ptr, ptr [[TMP9]], align 4
-// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
-// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK23-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK23-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK23-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
+// CHECK23-NEXT: store i32 [[TMP6]], ptr [[N]], align 4
+// CHECK23-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK23-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4
+// CHECK23-NEXT: [[TMP9:%.*]] = load i16, ptr [[TMP8]], align 4
+// CHECK23-NEXT: store i16 [[TMP9]], ptr [[AA]], align 2
+// CHECK23-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK23-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 4
+// CHECK23-NEXT: [[TMP12:%.*]] = load i8, ptr [[TMP11]], align 4
+// CHECK23-NEXT: store i8 [[TMP12]], ptr [[AAA]], align 1
+// CHECK23-NEXT: [[TMP13:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK23-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 4
+// CHECK23-NEXT: [[B:%.*]] = load ptr, ptr [[TMP14]], align 4
+// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK23-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP15]], align 4
// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
-// CHECK23-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
-// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[N]], align 4
-// CHECK23-NEXT: store i32 [[TMP12]], ptr [[N_CASTED]], align 4
-// CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[N_CASTED]], align 4
-// CHECK23-NEXT: [[TMP14:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK23-NEXT: store i16 [[TMP14]], ptr [[AA_CASTED]], align 2
-// CHECK23-NEXT: [[TMP15:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK23-NEXT: [[TMP16:%.*]] = load i8, ptr [[AAA]], align 1
-// CHECK23-NEXT: store i8 [[TMP16]], ptr [[AAA_CASTED]], align 1
-// CHECK23-NEXT: [[TMP17:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
-// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined, i32 [[TMP11]], i32 [[TMP13]], i32 [[TMP15]], i32 [[TMP17]], ptr [[B]])
+// CHECK23-NEXT: [[TMP16:%.*]] = load i32, ptr [[A]], align 4
+// CHECK23-NEXT: store i32 [[TMP16]], ptr [[A_CASTED]], align 4
+// CHECK23-NEXT: [[TMP17:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK23-NEXT: [[TMP18:%.*]] = load i32, ptr [[N]], align 4
+// CHECK23-NEXT: store i32 [[TMP18]], ptr [[N_CASTED]], align 4
+// CHECK23-NEXT: [[TMP19:%.*]] = load i32, ptr [[N_CASTED]], align 4
+// CHECK23-NEXT: [[TMP20:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK23-NEXT: store i16 [[TMP20]], ptr [[AA_CASTED]], align 2
+// CHECK23-NEXT: [[TMP21:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK23-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA]], align 1
+// CHECK23-NEXT: store i8 [[TMP22]], ptr [[AAA_CASTED]], align 1
+// CHECK23-NEXT: [[TMP23:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
+// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined, i32 [[TMP17]], i32 [[TMP19]], i32 [[TMP21]], i32 [[TMP23]], ptr [[B]])
// CHECK23-NEXT: ret void
//
//
@@ -13291,34 +13422,41 @@ int bar(int n){
// CHECK23-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK23-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP1]], align 4
-// CHECK23-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK23-NEXT: store i32 [[TMP3]], ptr [[B]], align 4
-// CHECK23-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
+// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK23-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK23-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK23-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4
// CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK23-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
-// CHECK23-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 4
-// CHECK23-NEXT: [[C:%.*]] = load ptr, ptr [[TMP8]], align 4
-// CHECK23-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 5
-// CHECK23-NEXT: [[TMP10:%.*]] = load i8, ptr [[TMP9]], align 4
-// CHECK23-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP10]], 0
+// CHECK23-NEXT: store i32 [[TMP5]], ptr [[B]], align 4
+// CHECK23-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK23-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
+// CHECK23-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
+// CHECK23-NEXT: [[TMP9:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK23-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4
+// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
+// CHECK23-NEXT: [[TMP12:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 4
+// CHECK23-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 4
+// CHECK23-NEXT: [[C:%.*]] = load ptr, ptr [[TMP13]], align 4
+// CHECK23-NEXT: [[TMP14:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 5
+// CHECK23-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 4
+// CHECK23-NEXT: [[TMP16:%.*]] = load i8, ptr [[TMP15]], align 4
+// CHECK23-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP16]], 0
// CHECK23-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i8
// CHECK23-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 1
-// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 6
-// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 6
+// CHECK23-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP17]], align 4
// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[B]], align 4
-// CHECK23-NEXT: store i32 [[TMP11]], ptr [[B_CASTED]], align 4
-// CHECK23-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_CASTED]], align 4
-// CHECK23-NEXT: [[TMP13:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
-// CHECK23-NEXT: [[LOADEDV2:%.*]] = icmp ne i8 [[TMP13]], 0
+// CHECK23-NEXT: [[TMP18:%.*]] = load i32, ptr [[B]], align 4
+// CHECK23-NEXT: store i32 [[TMP18]], ptr [[B_CASTED]], align 4
+// CHECK23-NEXT: [[TMP19:%.*]] = load i32, ptr [[B_CASTED]], align 4
+// CHECK23-NEXT: [[TMP20:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
+// CHECK23-NEXT: [[LOADEDV2:%.*]] = icmp ne i8 [[TMP20]], 0
// CHECK23-NEXT: [[STOREDV3:%.*]] = zext i1 [[LOADEDV2]] to i8
// CHECK23-NEXT: store i8 [[STOREDV3]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1
-// CHECK23-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
-// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined, ptr [[THIS]], i32 [[TMP12]], i32 [[TMP5]], i32 [[TMP7]], ptr [[C]], i32 [[TMP14]])
+// CHECK23-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
+// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined, ptr [[THIS]], i32 [[TMP19]], i32 [[TMP8]], i32 [[TMP11]], ptr [[C]], i32 [[TMP21]])
// CHECK23-NEXT: ret void
//
//
@@ -13472,24 +13610,28 @@ int bar(int n){
// CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
// CHECK23-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK23-NEXT: store i32 [[TMP2]], ptr [[A]], align 4
-// CHECK23-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK23-NEXT: [[TMP4:%.*]] = load i16, ptr [[TMP3]], align 4
-// CHECK23-NEXT: store i16 [[TMP4]], ptr [[AA]], align 2
-// CHECK23-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK23-NEXT: [[B:%.*]] = load ptr, ptr [[TMP5]], align 4
-// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK23-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
+// CHECK23-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK23-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK23-NEXT: [[TMP6:%.*]] = load i16, ptr [[TMP5]], align 4
+// CHECK23-NEXT: store i16 [[TMP6]], ptr [[AA]], align 2
+// CHECK23-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK23-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4
+// CHECK23-NEXT: [[B:%.*]] = load ptr, ptr [[TMP8]], align 4
+// CHECK23-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK23-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK23-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP9]], align 4
// CHECK23-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK23-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// CHECK23-NEXT: store i32 [[TMP6]], ptr [[A_CASTED]], align 4
-// CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK23-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA]], align 2
-// CHECK23-NEXT: store i16 [[TMP8]], ptr [[AA_CASTED]], align 2
-// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[AA_CASTED]], align 4
-// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined, i32 [[TMP7]], i32 [[TMP9]], ptr [[B]])
+// CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
+// CHECK23-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
+// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK23-NEXT: [[TMP12:%.*]] = load i16, ptr [[AA]], align 2
+// CHECK23-NEXT: store i16 [[TMP12]], ptr [[AA_CASTED]], align 2
+// CHECK23-NEXT: [[TMP13:%.*]] = load i32, ptr [[AA_CASTED]], align 4
+// CHECK23-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined, i32 [[TMP11]], i32 [[TMP13]], ptr [[B]])
// CHECK23-NEXT: ret void
//
//
diff --git a/clang/test/OpenMP/target_teams_generic_loop_codegen-1.cpp b/clang/test/OpenMP/target_teams_generic_loop_codegen-1.cpp
index f897879abd4d7..c343cf0b681b8 100644
--- a/clang/test/OpenMP/target_teams_generic_loop_codegen-1.cpp
+++ b/clang/test/OpenMP/target_teams_generic_loop_codegen-1.cpp
@@ -1837,27 +1837,32 @@ int target_teams_fun(int *g){
// CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]])
// CHECK10-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK10-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK10-NEXT: store i32 [[TMP3]], ptr [[N]], align 4
-// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK10-NEXT: [[A:%.*]] = load ptr, ptr [[TMP4]], align 8
-// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
-// CHECK10-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 8
-// CHECK10-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
-// CHECK10-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 8
-// CHECK10-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 4
-// CHECK10-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK10-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
+// CHECK10-NEXT: store i32 [[TMP4]], ptr [[N]], align 4
+// CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK10-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8
+// CHECK10-NEXT: [[A:%.*]] = load ptr, ptr [[TMP6]], align 8
+// CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK10-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8
+// CHECK10-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 8
+// CHECK10-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK10-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8
+// CHECK10-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 8
+// CHECK10-NEXT: store i32 [[TMP12]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 4
+// CHECK10-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK10-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP13]], align 8
// CHECK10-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 8
-// CHECK10-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK10-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK10-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP9]], i32 [[TMP10]])
-// CHECK10-NEXT: [[TMP11:%.*]] = load i32, ptr [[N]], align 4
-// CHECK10-NEXT: store i32 [[TMP11]], ptr [[N_CASTED]], align 4
-// CHECK10-NEXT: [[TMP12:%.*]] = load i64, ptr [[N_CASTED]], align 8
-// CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51.omp_outlined, i64 [[TMP12]], ptr [[A]])
+// CHECK10-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK10-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK10-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP14]], i32 [[TMP15]])
+// CHECK10-NEXT: [[TMP16:%.*]] = load i32, ptr [[N]], align 4
+// CHECK10-NEXT: store i32 [[TMP16]], ptr [[N_CASTED]], align 4
+// CHECK10-NEXT: [[TMP17:%.*]] = load i64, ptr [[N_CASTED]], align 8
+// CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51.omp_outlined, i64 [[TMP17]], ptr [[A]])
// CHECK10-NEXT: ret void
//
//
@@ -2062,20 +2067,24 @@ int target_teams_fun(int *g){
// CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK10-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK10-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK10-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK10-NEXT: store i32 [[TMP2]], ptr [[N]], align 4
-// CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK10-NEXT: [[A:%.*]] = load ptr, ptr [[TMP3]], align 8
-// CHECK10-NEXT: [[G:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 3
-// CHECK10-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK10-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK10-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK10-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK10-NEXT: store i32 [[TMP3]], ptr [[N]], align 4
+// CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK10-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK10-NEXT: [[A:%.*]] = load ptr, ptr [[TMP5]], align 8
+// CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK10-NEXT: [[G:%.*]] = load ptr, ptr [[TMP6]], align 8
+// CHECK10-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK10-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK10-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 8
// CHECK10-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK10-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4
-// CHECK10-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4
-// CHECK10-NEXT: [[TMP5:%.*]] = load i64, ptr [[N_CASTED]], align 8
-// CHECK10-NEXT: [[TMP6:%.*]] = load ptr, ptr [[G]], align 8
-// CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l57.omp_outlined, i64 [[TMP5]], ptr [[A]], ptr [[TMP6]])
+// CHECK10-NEXT: [[TMP8:%.*]] = load i32, ptr [[N]], align 4
+// CHECK10-NEXT: store i32 [[TMP8]], ptr [[N_CASTED]], align 4
+// CHECK10-NEXT: [[TMP9:%.*]] = load i64, ptr [[N_CASTED]], align 8
+// CHECK10-NEXT: [[TMP10:%.*]] = load ptr, ptr [[G]], align 8
+// CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l57.omp_outlined, i64 [[TMP9]], ptr [[A]], ptr [[TMP10]])
// CHECK10-NEXT: ret void
//
//
@@ -2291,27 +2300,32 @@ int target_teams_fun(int *g){
// CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]])
// CHECK12-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK12-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK12-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK12-NEXT: store i32 [[TMP3]], ptr [[N]], align 4
-// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK12-NEXT: [[A:%.*]] = load ptr, ptr [[TMP4]], align 4
-// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
-// CHECK12-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
-// CHECK12-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
-// CHECK12-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
-// CHECK12-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 4
-// CHECK12-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK12-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK12-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
+// CHECK12-NEXT: store i32 [[TMP4]], ptr [[N]], align 4
+// CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK12-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4
+// CHECK12-NEXT: [[A:%.*]] = load ptr, ptr [[TMP6]], align 4
+// CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK12-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4
+// CHECK12-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
+// CHECK12-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK12-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 4
+// CHECK12-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4
+// CHECK12-NEXT: store i32 [[TMP12]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 4
+// CHECK12-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK12-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP13]], align 4
// CHECK12-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 4
-// CHECK12-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK12-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK12-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP9]], i32 [[TMP10]])
-// CHECK12-NEXT: [[TMP11:%.*]] = load i32, ptr [[N]], align 4
-// CHECK12-NEXT: store i32 [[TMP11]], ptr [[N_CASTED]], align 4
-// CHECK12-NEXT: [[TMP12:%.*]] = load i32, ptr [[N_CASTED]], align 4
-// CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51.omp_outlined, i32 [[TMP12]], ptr [[A]])
+// CHECK12-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK12-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK12-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP14]], i32 [[TMP15]])
+// CHECK12-NEXT: [[TMP16:%.*]] = load i32, ptr [[N]], align 4
+// CHECK12-NEXT: store i32 [[TMP16]], ptr [[N_CASTED]], align 4
+// CHECK12-NEXT: [[TMP17:%.*]] = load i32, ptr [[N_CASTED]], align 4
+// CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51.omp_outlined, i32 [[TMP17]], ptr [[A]])
// CHECK12-NEXT: ret void
//
//
@@ -2511,20 +2525,24 @@ int target_teams_fun(int *g){
// CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
// CHECK12-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK12-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK12-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK12-NEXT: store i32 [[TMP2]], ptr [[N]], align 4
-// CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK12-NEXT: [[A:%.*]] = load ptr, ptr [[TMP3]], align 4
-// CHECK12-NEXT: [[G:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 3
-// CHECK12-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK12-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK12-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK12-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK12-NEXT: store i32 [[TMP3]], ptr [[N]], align 4
+// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK12-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK12-NEXT: [[A:%.*]] = load ptr, ptr [[TMP5]], align 4
+// CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK12-NEXT: [[G:%.*]] = load ptr, ptr [[TMP6]], align 4
+// CHECK12-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 3
+// CHECK12-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK12-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP7]], align 4
// CHECK12-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK12-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4
-// CHECK12-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4
-// CHECK12-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4
-// CHECK12-NEXT: [[TMP6:%.*]] = load ptr, ptr [[G]], align 4
-// CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l57.omp_outlined, i32 [[TMP5]], ptr [[A]], ptr [[TMP6]])
+// CHECK12-NEXT: [[TMP8:%.*]] = load i32, ptr [[N]], align 4
+// CHECK12-NEXT: store i32 [[TMP8]], ptr [[N_CASTED]], align 4
+// CHECK12-NEXT: [[TMP9:%.*]] = load i32, ptr [[N_CASTED]], align 4
+// CHECK12-NEXT: [[TMP10:%.*]] = load ptr, ptr [[G]], align 4
+// CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l57.omp_outlined, i32 [[TMP9]], ptr [[A]], ptr [[TMP10]])
// CHECK12-NEXT: ret void
//
//
diff --git a/clang/test/OpenMP/target_teams_generic_loop_private_codegen.cpp b/clang/test/OpenMP/target_teams_generic_loop_private_codegen.cpp
index efc5fc6680d99..b3cf6526ffa0a 100644
--- a/clang/test/OpenMP/target_teams_generic_loop_private_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_generic_loop_private_codegen.cpp
@@ -1510,8 +1510,9 @@ int main() {
// CHECK13-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK13-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK13-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP1]], align 8
// CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined)
// CHECK13-NEXT: ret void
@@ -1648,8 +1649,9 @@ int main() {
// CHECK13-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK13-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK13-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP1]], align 8
// CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined)
// CHECK13-NEXT: ret void
@@ -1829,8 +1831,9 @@ int main() {
// CHECK15-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK15-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK15-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK15-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP1]], align 4
// CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined)
// CHECK15-NEXT: ret void
@@ -1965,8 +1968,9 @@ int main() {
// CHECK15-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK15-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK15-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK15-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP1]], align 4
// CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined)
// CHECK15-NEXT: ret void
@@ -2144,8 +2148,9 @@ int main() {
// CHECK17-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK17-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK17-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP1]], align 8
// CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined)
// CHECK17-NEXT: ret void
diff --git a/clang/test/OpenMP/target_teams_map_codegen.cpp b/clang/test/OpenMP/target_teams_map_codegen.cpp
index f08e75cf6f9d7..98ad25fa32fb6 100644
--- a/clang/test/OpenMP/target_teams_map_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_map_codegen.cpp
@@ -2374,8 +2374,9 @@ void mapInt128() {
// CHECK5-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK5-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK5-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP1]], align 8
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14mapWithPrivatev_l27.omp_outlined)
// CHECK5-NEXT: ret void
@@ -2402,20 +2403,23 @@ void mapInt128() {
// CHECK5-NEXT: [[Y_CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK5-NEXT: [[X:%.*]] = load ptr, ptr [[TMP1]], align 8
-// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK5-NEXT: [[Y:%.*]] = load ptr, ptr [[TMP2]], align 8
-// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK5-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK5-NEXT: [[X:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK5-NEXT: [[Y:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK5-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[X]], align 4
-// CHECK5-NEXT: store i32 [[TMP3]], ptr [[X_CASTED]], align 4
-// CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[X_CASTED]], align 8
-// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[Y]], align 4
-// CHECK5-NEXT: store i32 [[TMP5]], ptr [[Y_CASTED]], align 4
-// CHECK5-NEXT: [[TMP6:%.*]] = load i64, ptr [[Y_CASTED]], align 8
-// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33.omp_outlined, i64 [[TMP4]], i64 [[TMP6]])
+// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[X]], align 4
+// CHECK5-NEXT: store i32 [[TMP6]], ptr [[X_CASTED]], align 4
+// CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[X_CASTED]], align 8
+// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[Y]], align 4
+// CHECK5-NEXT: store i32 [[TMP8]], ptr [[Y_CASTED]], align 4
+// CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[Y_CASTED]], align 8
+// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33.omp_outlined, i64 [[TMP7]], i64 [[TMP9]])
// CHECK5-NEXT: ret void
//
//
@@ -2440,12 +2444,15 @@ void mapInt128() {
// CHECK5-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK5-NEXT: [[X:%.*]] = load ptr, ptr [[TMP1]], align 8
-// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK5-NEXT: [[Y:%.*]] = load ptr, ptr [[TMP2]], align 8
-// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK5-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK5-NEXT: [[X:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK5-NEXT: [[Y:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK5-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39.omp_outlined, ptr [[X]], ptr [[Y]])
// CHECK5-NEXT: ret void
@@ -2538,15 +2545,17 @@ void mapInt128() {
// CHECK5-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK5-NEXT: [[X:%.*]] = load ptr, ptr [[TMP1]], align 8
-// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK5-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK5-NEXT: [[X:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK5-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP3]], align 8
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[X]], align 4
-// CHECK5-NEXT: store i32 [[TMP2]], ptr [[X_CASTED]], align 4
-// CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[X_CASTED]], align 8
-// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45.omp_outlined, i64 [[TMP3]])
+// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[X]], align 4
+// CHECK5-NEXT: store i32 [[TMP4]], ptr [[X_CASTED]], align 4
+// CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[X_CASTED]], align 8
+// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45.omp_outlined, i64 [[TMP5]])
// CHECK5-NEXT: ret void
//
//
@@ -2570,15 +2579,17 @@ void mapInt128() {
// CHECK5-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK5-NEXT: [[X:%.*]] = load ptr, ptr [[TMP1]], align 8
-// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK5-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK5-NEXT: [[X:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK5-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP3]], align 8
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[X]], align 4
-// CHECK5-NEXT: store i32 [[TMP2]], ptr [[X_CASTED]], align 4
-// CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[X_CASTED]], align 8
-// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51.omp_outlined, i64 [[TMP3]])
+// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[X]], align 4
+// CHECK5-NEXT: store i32 [[TMP4]], ptr [[X_CASTED]], align 4
+// CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[X_CASTED]], align 8
+// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51.omp_outlined, i64 [[TMP5]])
// CHECK5-NEXT: ret void
//
//
@@ -2602,15 +2613,17 @@ void mapInt128() {
// CHECK5-NEXT: [[X_CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK5-NEXT: [[X:%.*]] = load ptr, ptr [[TMP1]], align 8
-// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK5-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK5-NEXT: [[X:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK5-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP3]], align 8
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[X]], align 4
-// CHECK5-NEXT: store i32 [[TMP2]], ptr [[X_CASTED]], align 4
-// CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[X_CASTED]], align 8
-// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57.omp_outlined, i64 [[TMP3]])
+// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[X]], align 4
+// CHECK5-NEXT: store i32 [[TMP4]], ptr [[X_CASTED]], align 4
+// CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[X_CASTED]], align 8
+// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57.omp_outlined, i64 [[TMP5]])
// CHECK5-NEXT: ret void
//
//
@@ -2633,12 +2646,15 @@ void mapInt128() {
// CHECK5-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK5-NEXT: [[Y:%.*]] = load ptr, ptr [[TMP1]], align 8
-// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK5-NEXT: [[Z:%.*]] = load ptr, ptr [[TMP2]], align 8
-// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK5-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK5-NEXT: [[Y:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK5-NEXT: [[Z:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK5-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63.omp_outlined, ptr [[Y]], ptr [[Z]])
// CHECK5-NEXT: ret void
@@ -2758,12 +2774,15 @@ void mapInt128() {
// CHECK5-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK5-NEXT: [[Y:%.*]] = load ptr, ptr [[TMP1]], align 8
-// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK5-NEXT: [[Z:%.*]] = load ptr, ptr [[TMP2]], align 8
-// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK5-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK5-NEXT: [[Y:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK5-NEXT: [[Z:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK5-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65.omp_outlined, ptr [[Y]], ptr [[Z]])
// CHECK5-NEXT: ret void
@@ -2883,12 +2902,15 @@ void mapInt128() {
// CHECK5-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK5-NEXT: [[Y:%.*]] = load ptr, ptr [[TMP1]], align 8
-// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK5-NEXT: [[Z:%.*]] = load ptr, ptr [[TMP2]], align 8
-// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK5-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK5-NEXT: [[Y:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK5-NEXT: [[Z:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK5-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l72.omp_outlined, ptr [[Y]], ptr [[Z]])
// CHECK5-NEXT: ret void
@@ -2980,12 +3002,15 @@ void mapInt128() {
// CHECK5-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK5-NEXT: [[Y:%.*]] = load ptr, ptr [[TMP1]], align 8
-// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK5-NEXT: [[Z:%.*]] = load ptr, ptr [[TMP2]], align 8
-// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 2
-// CHECK5-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK5-NEXT: [[Y:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK5-NEXT: [[Z:%.*]] = load ptr, ptr [[TMP4]], align 8
+// CHECK5-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK5-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK5-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9mapInt128v_l74.omp_outlined, ptr [[Y]], ptr [[Z]])
// CHECK5-NEXT: ret void
@@ -3077,8 +3102,9 @@ void mapInt128() {
// CHECK7-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK7-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK7-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK7-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP1]], align 4
// CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z14mapWithPrivatev_l27.omp_outlined)
// CHECK7-NEXT: ret void
@@ -3105,20 +3131,23 @@ void mapInt128() {
// CHECK7-NEXT: [[Y_CASTED:%.*]] = alloca i32, align 4
// CHECK7-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK7-NEXT: [[X:%.*]] = load ptr, ptr [[TMP1]], align 4
-// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK7-NEXT: [[Y:%.*]] = load ptr, ptr [[TMP2]], align 4
-// CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK7-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK7-NEXT: [[X:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK7-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK7-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4
+// CHECK7-NEXT: [[Y:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK7-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK7-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[X]], align 4
-// CHECK7-NEXT: store i32 [[TMP3]], ptr [[X_CASTED]], align 4
-// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[X_CASTED]], align 4
-// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[Y]], align 4
-// CHECK7-NEXT: store i32 [[TMP5]], ptr [[Y_CASTED]], align 4
-// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[Y_CASTED]], align 4
-// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33.omp_outlined, i32 [[TMP4]], i32 [[TMP6]])
+// CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[X]], align 4
+// CHECK7-NEXT: store i32 [[TMP6]], ptr [[X_CASTED]], align 4
+// CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[X_CASTED]], align 4
+// CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[Y]], align 4
+// CHECK7-NEXT: store i32 [[TMP8]], ptr [[Y_CASTED]], align 4
+// CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[Y_CASTED]], align 4
+// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z19mapWithFirstprivatev_l33.omp_outlined, i32 [[TMP7]], i32 [[TMP9]])
// CHECK7-NEXT: ret void
//
//
@@ -3143,12 +3172,15 @@ void mapInt128() {
// CHECK7-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK7-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK7-NEXT: [[X:%.*]] = load ptr, ptr [[TMP1]], align 4
-// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK7-NEXT: [[Y:%.*]] = load ptr, ptr [[TMP2]], align 4
-// CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK7-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK7-NEXT: [[X:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK7-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK7-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4
+// CHECK7-NEXT: [[Y:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK7-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK7-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16mapWithReductionv_l39.omp_outlined, ptr [[X]], ptr [[Y]])
// CHECK7-NEXT: ret void
@@ -3241,15 +3273,17 @@ void mapInt128() {
// CHECK7-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4
// CHECK7-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK7-NEXT: [[X:%.*]] = load ptr, ptr [[TMP1]], align 4
-// CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK7-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK7-NEXT: [[X:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK7-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP3]], align 4
// CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[X]], align 4
-// CHECK7-NEXT: store i32 [[TMP2]], ptr [[X_CASTED]], align 4
-// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[X_CASTED]], align 4
-// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45.omp_outlined, i32 [[TMP3]])
+// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[X]], align 4
+// CHECK7-NEXT: store i32 [[TMP4]], ptr [[X_CASTED]], align 4
+// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[X_CASTED]], align 4
+// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z7mapFromv_l45.omp_outlined, i32 [[TMP5]])
// CHECK7-NEXT: ret void
//
//
@@ -3273,15 +3307,17 @@ void mapInt128() {
// CHECK7-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4
// CHECK7-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK7-NEXT: [[X:%.*]] = load ptr, ptr [[TMP1]], align 4
-// CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK7-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK7-NEXT: [[X:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK7-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP3]], align 4
// CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[X]], align 4
-// CHECK7-NEXT: store i32 [[TMP2]], ptr [[X_CASTED]], align 4
-// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[X_CASTED]], align 4
-// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51.omp_outlined, i32 [[TMP3]])
+// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[X]], align 4
+// CHECK7-NEXT: store i32 [[TMP4]], ptr [[X_CASTED]], align 4
+// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[X_CASTED]], align 4
+// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5mapTov_l51.omp_outlined, i32 [[TMP5]])
// CHECK7-NEXT: ret void
//
//
@@ -3305,15 +3341,17 @@ void mapInt128() {
// CHECK7-NEXT: [[X_CASTED:%.*]] = alloca i32, align 4
// CHECK7-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK7-NEXT: [[X:%.*]] = load ptr, ptr [[TMP1]], align 4
-// CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK7-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK7-NEXT: [[X:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK7-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP3]], align 4
// CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[X]], align 4
-// CHECK7-NEXT: store i32 [[TMP2]], ptr [[X_CASTED]], align 4
-// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[X_CASTED]], align 4
-// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57.omp_outlined, i32 [[TMP3]])
+// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[X]], align 4
+// CHECK7-NEXT: store i32 [[TMP4]], ptr [[X_CASTED]], align 4
+// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[X_CASTED]], align 4
+// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapAllocv_l57.omp_outlined, i32 [[TMP5]])
// CHECK7-NEXT: ret void
//
//
@@ -3336,12 +3374,15 @@ void mapInt128() {
// CHECK7-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK7-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK7-NEXT: [[Y:%.*]] = load ptr, ptr [[TMP1]], align 4
-// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK7-NEXT: [[Z:%.*]] = load ptr, ptr [[TMP2]], align 4
-// CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK7-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK7-NEXT: [[Y:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK7-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK7-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4
+// CHECK7-NEXT: [[Z:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK7-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK7-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l63.omp_outlined, ptr [[Y]], ptr [[Z]])
// CHECK7-NEXT: ret void
@@ -3461,12 +3502,15 @@ void mapInt128() {
// CHECK7-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK7-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK7-NEXT: [[Y:%.*]] = load ptr, ptr [[TMP1]], align 4
-// CHECK7-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK7-NEXT: [[Z:%.*]] = load ptr, ptr [[TMP2]], align 4
-// CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 2
-// CHECK7-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK7-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK7-NEXT: [[Y:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK7-NEXT: [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK7-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 4
+// CHECK7-NEXT: [[Z:%.*]] = load ptr, ptr [[TMP4]], align 4
+// CHECK7-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 2
+// CHECK7-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK7-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK7-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z8mapArrayv_l65.omp_outlined, ptr [[Y]], ptr [[Z]])
// CHECK7-NEXT: ret void
diff --git a/clang/test/OpenMP/target_teams_num_teams_codegen.cpp b/clang/test/OpenMP/target_teams_num_teams_codegen.cpp
index 24b4027f41e95..9f45af4dc5f2d 100644
--- a/clang/test/OpenMP/target_teams_num_teams_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_num_teams_codegen.cpp
@@ -1445,14 +1445,16 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK9-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
+// CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 0)
+// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP6]], i32 0)
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined)
// CHECK9-NEXT: ret void
//
@@ -1476,14 +1478,16 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK9-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
+// CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 0)
+// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP6]], i32 0)
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.omp_outlined)
// CHECK9-NEXT: ret void
//
@@ -1509,23 +1513,27 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
-// CHECK9-NEXT: store i32 [[TMP4]], ptr [[B]], align 4
-// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 8
-// CHECK9-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: store i32 [[TMP6]], ptr [[B]], align 4
+// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8
+// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 8
+// CHECK9-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP10]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP7]], i32 0)
-// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 4
-// CHECK9-NEXT: store i32 [[TMP8]], ptr [[B_CASTED]], align 4
-// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[B_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[THIS]], i64 [[TMP9]])
+// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP11]], i32 0)
+// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[B]], align 4
+// CHECK9-NEXT: store i32 [[TMP12]], ptr [[B_CASTED]], align 4
+// CHECK9-NEXT: [[TMP13:%.*]] = load i64, ptr [[B_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[THIS]], i64 [[TMP13]])
// CHECK9-NEXT: ret void
//
//
@@ -1557,10 +1565,12 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 8
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0)
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[THIS]])
@@ -1590,8 +1600,9 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP2]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0)
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.omp_outlined)
@@ -1621,28 +1632,32 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
-// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 8
-// CHECK9-NEXT: store i16 [[TMP5]], ptr [[B]], align 2
-// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
+// CHECK9-NEXT: store i32 [[TMP4]], ptr [[A]], align 4
+// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 8
-// CHECK9-NEXT: store i16 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 2
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: store i16 [[TMP7]], ptr [[B]], align 2
+// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8
+// CHECK9-NEXT: [[TMP10:%.*]] = load i16, ptr [[TMP9]], align 8
+// CHECK9-NEXT: store i16 [[TMP10]], ptr [[DOTCAPTURE_EXPR_]], align 2
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP11]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP8:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2
-// CHECK9-NEXT: [[TMP9:%.*]] = sext i16 [[TMP8]] to i32
-// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP9]], i32 0)
-// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
-// CHECK9-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
-// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP12:%.*]] = load i16, ptr [[B]], align 2
-// CHECK9-NEXT: store i16 [[TMP12]], ptr [[B_CASTED]], align 2
-// CHECK9-NEXT: [[TMP13:%.*]] = load i64, ptr [[B_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i64 [[TMP11]], i64 [[TMP13]])
+// CHECK9-NEXT: [[TMP12:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2
+// CHECK9-NEXT: [[TMP13:%.*]] = sext i16 [[TMP12]] to i32
+// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP13]], i32 0)
+// CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4
+// CHECK9-NEXT: store i32 [[TMP14]], ptr [[A_CASTED]], align 4
+// CHECK9-NEXT: [[TMP15:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK9-NEXT: [[TMP16:%.*]] = load i16, ptr [[B]], align 2
+// CHECK9-NEXT: store i16 [[TMP16]], ptr [[B_CASTED]], align 2
+// CHECK9-NEXT: [[TMP17:%.*]] = load i64, ptr [[B_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i64 [[TMP15]], i64 [[TMP17]])
// CHECK9-NEXT: ret void
//
//
@@ -1674,14 +1689,16 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK11-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
+// CHECK11-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 0)
+// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP6]], i32 0)
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined)
// CHECK11-NEXT: ret void
//
@@ -1705,14 +1722,16 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK11-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
+// CHECK11-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 0)
+// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP6]], i32 0)
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.omp_outlined)
// CHECK11-NEXT: ret void
//
@@ -1738,23 +1757,27 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-// CHECK11-NEXT: store i32 [[TMP4]], ptr [[B]], align 4
-// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP3]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
-// CHECK11-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: store i32 [[TMP6]], ptr [[B]], align 4
+// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4
+// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
+// CHECK11-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP10]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP7]], i32 0)
-// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 4
-// CHECK11-NEXT: store i32 [[TMP8]], ptr [[B_CASTED]], align 4
-// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[B_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[THIS]], i32 [[TMP9]])
+// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP11]], i32 0)
+// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[B]], align 4
+// CHECK11-NEXT: store i32 [[TMP12]], ptr [[B_CASTED]], align 4
+// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[THIS]], i32 [[TMP13]])
// CHECK11-NEXT: ret void
//
//
@@ -1786,10 +1809,12 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP3]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0)
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[THIS]])
@@ -1819,8 +1844,9 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP2]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0)
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.omp_outlined)
@@ -1850,28 +1876,32 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 4
-// CHECK11-NEXT: store i16 [[TMP5]], ptr [[B]], align 2
-// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
+// CHECK11-NEXT: store i32 [[TMP4]], ptr [[A]], align 4
+// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 4
-// CHECK11-NEXT: store i16 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 2
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: store i16 [[TMP7]], ptr [[B]], align 2
+// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 4
+// CHECK11-NEXT: [[TMP10:%.*]] = load i16, ptr [[TMP9]], align 4
+// CHECK11-NEXT: store i16 [[TMP10]], ptr [[DOTCAPTURE_EXPR_]], align 2
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK11-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP11]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP8:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2
-// CHECK11-NEXT: [[TMP9:%.*]] = sext i16 [[TMP8]] to i32
-// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP9]], i32 0)
-// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
-// CHECK11-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP12:%.*]] = load i16, ptr [[B]], align 2
-// CHECK11-NEXT: store i16 [[TMP12]], ptr [[B_CASTED]], align 2
-// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i32 [[TMP11]], i32 [[TMP13]])
+// CHECK11-NEXT: [[TMP12:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2
+// CHECK11-NEXT: [[TMP13:%.*]] = sext i16 [[TMP12]] to i32
+// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP13]], i32 0)
+// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4
+// CHECK11-NEXT: store i32 [[TMP14]], ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP16:%.*]] = load i16, ptr [[B]], align 2
+// CHECK11-NEXT: store i16 [[TMP16]], ptr [[B_CASTED]], align 2
+// CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[B_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i32 [[TMP15]], i32 [[TMP17]])
// CHECK11-NEXT: ret void
//
//
diff --git a/clang/test/OpenMP/target_teams_thread_limit_codegen.cpp b/clang/test/OpenMP/target_teams_thread_limit_codegen.cpp
index 5c97b05c60be4..eddfc7fcc6976 100644
--- a/clang/test/OpenMP/target_teams_thread_limit_codegen.cpp
+++ b/clang/test/OpenMP/target_teams_thread_limit_codegen.cpp
@@ -1484,18 +1484,21 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK9-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
-// CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
+// CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8
+// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 8
+// CHECK9-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP8]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 8
-// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP6]], i32 [[TMP7]])
+// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP9]], i32 [[TMP10]])
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined)
// CHECK9-NEXT: ret void
//
@@ -1519,14 +1522,16 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK9-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
+// CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP4]])
+// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP6]])
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.omp_outlined)
// CHECK9-NEXT: ret void
//
@@ -1552,23 +1557,27 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
-// CHECK9-NEXT: store i32 [[TMP4]], ptr [[B]], align 4
-// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 8
-// CHECK9-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: store i32 [[TMP6]], ptr [[B]], align 4
+// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8
+// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 8
+// CHECK9-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP10]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP7]])
-// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 4
-// CHECK9-NEXT: store i32 [[TMP8]], ptr [[B_CASTED]], align 4
-// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[B_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[THIS]], i64 [[TMP9]])
+// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP11]])
+// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[B]], align 4
+// CHECK9-NEXT: store i32 [[TMP12]], ptr [[B_CASTED]], align 4
+// CHECK9-NEXT: [[TMP13:%.*]] = load i64, ptr [[B_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[THIS]], i64 [[TMP13]])
// CHECK9-NEXT: ret void
//
//
@@ -1600,10 +1609,12 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 8
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP3]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024)
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[THIS]])
@@ -1633,8 +1644,9 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP2]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20)
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.omp_outlined)
@@ -1664,28 +1676,32 @@ int bar(int n){
// CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK9-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK9-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
-// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 8
-// CHECK9-NEXT: store i16 [[TMP5]], ptr [[B]], align 2
-// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
+// CHECK9-NEXT: store i32 [[TMP4]], ptr [[A]], align 4
+// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK9-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 8
-// CHECK9-NEXT: store i16 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 2
-// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
-// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: store i16 [[TMP7]], ptr [[B]], align 2
+// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK9-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8
+// CHECK9-NEXT: [[TMP10:%.*]] = load i16, ptr [[TMP9]], align 8
+// CHECK9-NEXT: store i16 [[TMP10]], ptr [[DOTCAPTURE_EXPR_]], align 2
+// CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK9-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP11]], align 8
// CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK9-NEXT: [[TMP8:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2
-// CHECK9-NEXT: [[TMP9:%.*]] = sext i16 [[TMP8]] to i32
-// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP9]], i32 1024)
-// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
-// CHECK9-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
-// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK9-NEXT: [[TMP12:%.*]] = load i16, ptr [[B]], align 2
-// CHECK9-NEXT: store i16 [[TMP12]], ptr [[B_CASTED]], align 2
-// CHECK9-NEXT: [[TMP13:%.*]] = load i64, ptr [[B_CASTED]], align 8
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i64 [[TMP11]], i64 [[TMP13]])
+// CHECK9-NEXT: [[TMP12:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2
+// CHECK9-NEXT: [[TMP13:%.*]] = sext i16 [[TMP12]] to i32
+// CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP13]], i32 1024)
+// CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4
+// CHECK9-NEXT: store i32 [[TMP14]], ptr [[A_CASTED]], align 4
+// CHECK9-NEXT: [[TMP15:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK9-NEXT: [[TMP16:%.*]] = load i16, ptr [[B]], align 2
+// CHECK9-NEXT: store i16 [[TMP16]], ptr [[B_CASTED]], align 2
+// CHECK9-NEXT: [[TMP17:%.*]] = load i64, ptr [[B_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i64 [[TMP15]], i64 [[TMP17]])
// CHECK9-NEXT: ret void
//
//
@@ -1718,18 +1734,21 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK11-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK11-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
+// CHECK11-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4
+// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+// CHECK11-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP8]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR2]], align 4
-// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP6]], i32 [[TMP7]])
+// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP9]], i32 [[TMP10]])
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.omp_outlined)
// CHECK11-NEXT: ret void
//
@@ -1753,14 +1772,16 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK11-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
+// CHECK11-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP4]])
+// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP6]])
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.omp_outlined)
// CHECK11-NEXT: ret void
//
@@ -1786,23 +1807,27 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-// CHECK11-NEXT: store i32 [[TMP4]], ptr [[B]], align 4
-// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP3]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
-// CHECK11-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: store i32 [[TMP6]], ptr [[B]], align 4
+// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 4
+// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
+// CHECK11-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP10]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP7]])
-// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 4
-// CHECK11-NEXT: store i32 [[TMP8]], ptr [[B_CASTED]], align 4
-// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[B_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[THIS]], i32 [[TMP9]])
+// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP11]])
+// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[B]], align 4
+// CHECK11-NEXT: store i32 [[TMP12]], ptr [[B_CASTED]], align 4
+// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.omp_outlined, ptr [[THIS]], i32 [[TMP13]])
// CHECK11-NEXT: ret void
//
//
@@ -1834,10 +1859,12 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP2]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[THIS:%.*]] = load ptr, ptr [[TMP3]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 1024)
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.omp_outlined, ptr [[THIS]])
@@ -1867,8 +1894,9 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP2]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i32 20)
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.omp_outlined)
@@ -1898,28 +1926,32 @@ int bar(int n){
// CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK11-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK11-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 4
-// CHECK11-NEXT: store i16 [[TMP5]], ptr [[B]], align 2
-// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
+// CHECK11-NEXT: store i32 [[TMP4]], ptr [[A]], align 4
+// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK11-NEXT: [[TMP7:%.*]] = load i16, ptr [[TMP6]], align 4
-// CHECK11-NEXT: store i16 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 2
-// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
-// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: store i16 [[TMP7]], ptr [[B]], align 2
+// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 4
+// CHECK11-NEXT: [[TMP10:%.*]] = load i16, ptr [[TMP9]], align 4
+// CHECK11-NEXT: store i16 [[TMP10]], ptr [[DOTCAPTURE_EXPR_]], align 2
+// CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK11-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK11-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP11]], align 4
// CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK11-NEXT: [[TMP8:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2
-// CHECK11-NEXT: [[TMP9:%.*]] = sext i16 [[TMP8]] to i32
-// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP9]], i32 1024)
-// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
-// CHECK11-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK11-NEXT: [[TMP12:%.*]] = load i16, ptr [[B]], align 2
-// CHECK11-NEXT: store i16 [[TMP12]], ptr [[B_CASTED]], align 2
-// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[B_CASTED]], align 4
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i32 [[TMP11]], i32 [[TMP13]])
+// CHECK11-NEXT: [[TMP12:%.*]] = load i16, ptr [[DOTCAPTURE_EXPR_]], align 2
+// CHECK11-NEXT: [[TMP13:%.*]] = sext i16 [[TMP12]] to i32
+// CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP13]], i32 1024)
+// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4
+// CHECK11-NEXT: store i32 [[TMP14]], ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK11-NEXT: [[TMP16:%.*]] = load i16, ptr [[B]], align 2
+// CHECK11-NEXT: store i16 [[TMP16]], ptr [[B_CASTED]], align 2
+// CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[B_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.omp_outlined, i32 [[TMP15]], i32 [[TMP17]])
// CHECK11-NEXT: ret void
//
//
diff --git a/clang/test/OpenMP/teams_codegen.cpp b/clang/test/OpenMP/teams_codegen.cpp
index 3d3f2754276d5..c4f5edd9137b8 100644
--- a/clang/test/OpenMP/teams_codegen.cpp
+++ b/clang/test/OpenMP/teams_codegen.cpp
@@ -2538,11 +2538,13 @@ void foo() {
// CHECK25-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK25-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK25-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK25-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK25-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
-// CHECK25-NEXT: store i32 [[TMP2]], ptr [[ARGC]], align 4
-// CHECK25-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK25-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK25-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK25-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
+// CHECK25-NEXT: store i32 [[TMP3]], ptr [[ARGC]], align 4
+// CHECK25-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK25-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK25-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 8
// CHECK25-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK25-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216.omp_outlined, ptr [[ARGC]])
// CHECK25-NEXT: ret void
@@ -2569,9 +2571,11 @@ void foo() {
// CHECK25-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 8
// CHECK25-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK25-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK25-NEXT: [[ARGC:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 0
-// CHECK25-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i32 1
-// CHECK25-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK25-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK25-NEXT: [[ARGC:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CHECK25-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK25-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK25-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP2]], align 8
// CHECK25-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
// CHECK25-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209.omp_outlined, ptr [[ARGC]])
// CHECK25-NEXT: ret void
@@ -2599,11 +2603,13 @@ void foo() {
// CHECK27-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK27-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK27-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK27-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK27-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK27-NEXT: store i32 [[TMP2]], ptr [[ARGC]], align 4
-// CHECK27-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK27-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK27-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK27-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK27-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK27-NEXT: store i32 [[TMP3]], ptr [[ARGC]], align 4
+// CHECK27-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK27-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK27-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP4]], align 4
// CHECK27-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK27-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216.omp_outlined, ptr [[ARGC]])
// CHECK27-NEXT: ret void
@@ -2630,9 +2636,11 @@ void foo() {
// CHECK27-NEXT: [[DYN_PTR1:%.*]] = alloca ptr, align 4
// CHECK27-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK27-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK27-NEXT: [[ARGC:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 0
-// CHECK27-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
-// CHECK27-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK27-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 0
+// CHECK27-NEXT: [[ARGC:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CHECK27-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP0]], i32 1
+// CHECK27-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK27-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP2]], align 4
// CHECK27-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
// CHECK27-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209.omp_outlined, ptr [[ARGC]])
// CHECK27-NEXT: ret void
@@ -2663,21 +2671,25 @@ void foo() {
// CHECK33-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
// CHECK33-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK33-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK33-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK33-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK33-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
-// CHECK33-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK33-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
-// CHECK33-NEXT: store i32 [[TMP5]], ptr [[B]], align 4
-// CHECK33-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
+// CHECK33-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK33-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK33-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
+// CHECK33-NEXT: store i32 [[TMP4]], ptr [[A]], align 4
+// CHECK33-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK33-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8
// CHECK33-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 8
-// CHECK33-NEXT: store i32 [[TMP7]], ptr [[ARGC]], align 4
-// CHECK33-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
-// CHECK33-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK33-NEXT: store i32 [[TMP7]], ptr [[B]], align 4
+// CHECK33-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK33-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8
+// CHECK33-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 8
+// CHECK33-NEXT: store i32 [[TMP10]], ptr [[ARGC]], align 4
+// CHECK33-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK33-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK33-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP11]], align 8
// CHECK33-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK33-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
-// CHECK33-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4
-// CHECK33-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP8]], i32 [[TMP9]])
+// CHECK33-NEXT: [[TMP12:%.*]] = load i32, ptr [[A]], align 4
+// CHECK33-NEXT: [[TMP13:%.*]] = load i32, ptr [[B]], align 4
+// CHECK33-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP12]], i32 [[TMP13]])
// CHECK33-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265.omp_outlined, ptr [[ARGC]])
// CHECK33-NEXT: ret void
//
@@ -2706,19 +2718,23 @@ void foo() {
// CHECK33-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK33-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
// CHECK33-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
-// CHECK33-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0
-// CHECK33-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 8
-// CHECK33-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
-// CHECK33-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 1
-// CHECK33-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 8
-// CHECK33-NEXT: store i32 [[TMP5]], ptr [[B]], align 4
-// CHECK33-NEXT: [[ARGC:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 2
-// CHECK33-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 3
-// CHECK33-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK33-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK33-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK33-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
+// CHECK33-NEXT: store i32 [[TMP4]], ptr [[A]], align 4
+// CHECK33-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK33-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8
+// CHECK33-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 8
+// CHECK33-NEXT: store i32 [[TMP7]], ptr [[B]], align 4
+// CHECK33-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK33-NEXT: [[ARGC:%.*]] = load ptr, ptr [[TMP8]], align 8
+// CHECK33-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK33-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 8
+// CHECK33-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP9]], align 8
// CHECK33-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 8
-// CHECK33-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// CHECK33-NEXT: [[TMP7:%.*]] = load i32, ptr [[B]], align 4
-// CHECK33-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP6]], i32 [[TMP7]])
+// CHECK33-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
+// CHECK33-NEXT: [[TMP11:%.*]] = load i32, ptr [[B]], align 4
+// CHECK33-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP10]], i32 [[TMP11]])
// CHECK33-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254.omp_outlined, ptr [[ARGC]])
// CHECK33-NEXT: ret void
//
@@ -2748,21 +2764,25 @@ void foo() {
// CHECK35-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
// CHECK35-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK35-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK35-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK35-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK35-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
-// CHECK35-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK35-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK35-NEXT: store i32 [[TMP5]], ptr [[B]], align 4
-// CHECK35-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
+// CHECK35-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK35-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK35-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
+// CHECK35-NEXT: store i32 [[TMP4]], ptr [[A]], align 4
+// CHECK35-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK35-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4
// CHECK35-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
-// CHECK35-NEXT: store i32 [[TMP7]], ptr [[ARGC]], align 4
-// CHECK35-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
-// CHECK35-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK35-NEXT: store i32 [[TMP7]], ptr [[B]], align 4
+// CHECK35-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK35-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 4
+// CHECK35-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
+// CHECK35-NEXT: store i32 [[TMP10]], ptr [[ARGC]], align 4
+// CHECK35-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK35-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK35-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP11]], align 4
// CHECK35-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK35-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
-// CHECK35-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4
-// CHECK35-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP8]], i32 [[TMP9]])
+// CHECK35-NEXT: [[TMP12:%.*]] = load i32, ptr [[A]], align 4
+// CHECK35-NEXT: [[TMP13:%.*]] = load i32, ptr [[B]], align 4
+// CHECK35-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP12]], i32 [[TMP13]])
// CHECK35-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265.omp_outlined, ptr [[ARGC]])
// CHECK35-NEXT: ret void
//
@@ -2791,19 +2811,23 @@ void foo() {
// CHECK35-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK35-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 4
// CHECK35-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 4
-// CHECK35-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
-// CHECK35-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK35-NEXT: store i32 [[TMP3]], ptr [[A]], align 4
-// CHECK35-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
-// CHECK35-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK35-NEXT: store i32 [[TMP5]], ptr [[B]], align 4
-// CHECK35-NEXT: [[ARGC:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 2
-// CHECK35-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 3
-// CHECK35-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK35-NEXT: [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 0
+// CHECK35-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK35-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
+// CHECK35-NEXT: store i32 [[TMP4]], ptr [[A]], align 4
+// CHECK35-NEXT: [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 1
+// CHECK35-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4
+// CHECK35-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+// CHECK35-NEXT: store i32 [[TMP7]], ptr [[B]], align 4
+// CHECK35-NEXT: [[TMP8:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 2
+// CHECK35-NEXT: [[ARGC:%.*]] = load ptr, ptr [[TMP8]], align 4
+// CHECK35-NEXT: [[DYN_PTR_ADDR:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i32 3
+// CHECK35-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DYN_PTR_ADDR]], align 4
+// CHECK35-NEXT: [[DYN_PTR:%.*]] = load ptr, ptr [[TMP9]], align 4
// CHECK35-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR1]], align 4
-// CHECK35-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
-// CHECK35-NEXT: [[TMP7:%.*]] = load i32, ptr [[B]], align 4
-// CHECK35-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP6]], i32 [[TMP7]])
+// CHECK35-NEXT: [[TMP10:%.*]] = load i32, ptr [[A]], align 4
+// CHECK35-NEXT: [[TMP11:%.*]] = load i32, ptr [[B]], align 4
+// CHECK35-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP10]], i32 [[TMP11]])
// CHECK35-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254.omp_outlined, ptr [[ARGC]])
// CHECK35-NEXT: ret void
//
diff --git a/offload/plugins-nextgen/host/src/rtl.cpp b/offload/plugins-nextgen/host/src/rtl.cpp
index 7c676bd82c801..765887c616daf 100644
--- a/offload/plugins-nextgen/host/src/rtl.cpp
+++ b/offload/plugins-nextgen/host/src/rtl.cpp
@@ -99,7 +99,7 @@ struct GenELF64KernelTy : public GenericKernelTy {
"cooperative kernel launch not supported for host");
// TODO: The data will need to be copied locally if we ever support
// asynchronous kernel launches in the host interface.
- Func(LaunchParams.Data);
+ Func(LaunchParams.Ptrs);
return Plugin::success();
}
@@ -112,8 +112,9 @@ struct GenELF64KernelTy : public GenericKernelTy {
}
private:
- /// Host kernel arguments are defined as a single, contiguous buffer.
- using KernelTy = void(void *);
+ /// Host kernel arguments are defined as an array of pointers, one per
+ /// argument, each pointing to that argument's storage.
+ using KernelTy = void(void **);
/// The kernel function to execute.
KernelTy *Func;
};
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