[clang] [llvm] [Clang][RISCV] Add CORE-V (XCV) builtins for CV32E40P (PR #204881)

[via cfe-commits]

VittorioBurani wrote:

Update: reworked per @lenary's point on intrinsics vs IR types.

The element-wise XCVsimd builtins that map to plain vector ops are removed: min/minu/max/maxu/and/or/xor/abs (and add_b/sub_b). These are now expressed as native operations on `4 x i8` / `2 x i16` vector types and lowered by the backend (#204880). The scalar-broadcast (sc) builtins are kept. The shift/avg/compare builtins remain for now, pending the matching backend change.

Depends on #204880.


https://github.com/llvm/llvm-project/pull/204881