[clang] [compiler-rt] [llvm] [X86] Add AVX512BMM support for AMD Zen 6 (znver6) (PR #182556)

[via cfe-commits]

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+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx512bmm,+avx512vl,+avx512bw --show-mc-encoding | FileCheck %s --check-prefixes=CHECK,VLX
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx512bmm,+avx512bw --show-mc-encoding | FileCheck %s --check-prefixes=CHECK,NOVLX
+
+; Test vbitrevb instruction generation from bitreverse intrinsic
+; This test verifies that the bitreverse intrinsic generates vbitrevb instructions
+; when AVX512BMM is available.
+; Without VLX, 128/256-bit operations are widened to 512-bit zmm registers.
+
+; Test 512-bit vector bit reversal with aligned memory load
+define <64 x i8> @bitrev_zmm_aligned_load(ptr %ptr) {
+; CHECK-LABEL: bitrev_zmm_aligned_load:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vbitrevb (%rdi), %zmm0 # encoding: [0x62,0xf6,0x7c,0x48,0x81,0x07]
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ganeshgit wrote:

Both versions of the tests added.

https://github.com/llvm/llvm-project/pull/182556