[clang] [CIR][AArch64] Upstream widening-addition and vector-shift-left-and-widen NEON builtins (PR #204285)

[Jiahao Guo via cfe-commits]

================
@@ -959,7 +959,20 @@ static mlir::Value emitCommonNeonBuiltinExpr(
   case NEON::BI__builtin_neon_vshlq_n_v:
     return emitCommonNeonShift(cgf.getBuilder(), loc, vTy, ops[0], ops[1],
                                /*shiftLeft=*/true);
-  case NEON::BI__builtin_neon_vshll_n_v:
+  case NEON::BI__builtin_neon_vshll_n_v: {
+    CIRGenBuilderTy &builder = cgf.getBuilder();
+    auto wideEltTy = mlir::cast<cir::IntType>(vTy.getElementType());
+    cir::VectorType narrowVecTy = cir::VectorType::get(
----------------
E00N777 wrote:

Maybe we could simply implement it like this:
```
case NEON::BI__builtin_neon_vshll_n_v: {
    CIRGenBuilderTy &builder = cgf.getBuilder();
    cir::VectorType narrowVecTy = builder.getExtendedOrTruncatedElementVectorType(
        vTy, /*isExtended=*/false, /*isSigned=*/!usgn);
    mlir::Value src = builder.createBitcast(ops[0], narrowVecTy);
    mlir::Value extended = builder.createIntCast(src, vTy);
    return emitCommonNeonShift(builder, loc, vTy, extended, ops[1],
                               /*shiftLeft=*/true);
  }
```

https://github.com/llvm/llvm-project/pull/204285