[clang] [Clang][CIR] Move AArch64 Add tests (nfc) (PR #203543)
Andrzej Warzyński via cfe-commits
cfe-commits at lists.llvm.org
Fri Jun 12 07:21:25 PDT 2026
https://github.com/banach-space created https://github.com/llvm/llvm-project/pull/203543
Follow-up for https://github.com/llvm/llvm-project/pull/202005
>From 55bc9e2549d154a34fe8d3623572cb092a6a4eba Mon Sep 17 00:00:00 2001
From: Andrzej Warzynski <andrzej.warzynski at arm.com>
Date: Fri, 12 Jun 2026 14:20:45 +0000
Subject: [PATCH] [Clang][CIR] Move AArch64 Add tests (nfc)
Follow-up for https://github.com/llvm/llvm-project/pull/202005
---
clang/test/CodeGen/AArch64/neon/add.c | 248 ++++++++++++++++++-
clang/test/CodeGen/AArch64/neon/intrinsics.c | 247 ------------------
2 files changed, 247 insertions(+), 248 deletions(-)
diff --git a/clang/test/CodeGen/AArch64/neon/add.c b/clang/test/CodeGen/AArch64/neon/add.c
index 916f4af59363e..ff2cb23c772dd 100644
--- a/clang/test/CodeGen/AArch64/neon/add.c
+++ b/clang/test/CodeGen/AArch64/neon/add.c
@@ -6,6 +6,253 @@
#include <arm_neon.h>
+//===------------------------------------------------------===//
+// 2.1.1.1.1 Addition
+// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#addition
+//===------------------------------------------------------===//
+
+// LLVM-LABEL: @test_vadd_s8(
+// CIR-LABEL: @vadd_s8(
+int8x8_t test_vadd_s8(int8x8_t a, int8x8_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: <8 x i8> {{.*}}[[A:%.*]], <8 x i8> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = add <8 x i8> [[A]], [[B]]
+// LLVM: ret <8 x i8> [[ADD_I]]
+ return vadd_s8(a, b);
+}
+
+// LLVM-LABEL: @test_vadd_s16(
+// CIR-LABEL: @vadd_s16(
+int16x4_t test_vadd_s16(int16x4_t a, int16x4_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: <4 x i16> {{.*}}[[A:%.*]], <4 x i16> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = add <4 x i16> [[A]], [[B]]
+// LLVM: ret <4 x i16> [[ADD_I]]
+ return vadd_s16(a, b);
+}
+
+// LLVM-LABEL: @test_vadd_s32(
+// CIR-LABEL: @vadd_s32(
+int32x2_t test_vadd_s32(int32x2_t a, int32x2_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]], <2 x i32> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = add <2 x i32> [[A]], [[B]]
+// LLVM: ret <2 x i32> [[ADD_I]]
+ return vadd_s32(a, b);
+}
+
+// LLVM-LABEL: @test_vadd_s64(
+// CIR-LABEL: @vadd_s64(
+int64x1_t test_vadd_s64(int64x1_t a, int64x1_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: <1 x i64> {{.*}}[[A:%.*]], <1 x i64> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = add <1 x i64> [[A]], [[B]]
+// LLVM: ret <1 x i64> [[ADD_I]]
+ return vadd_s64(a, b);
+}
+
+// LLVM-LABEL: @test_vadd_f32(
+// CIR-LABEL: @vadd_f32(
+float32x2_t test_vadd_f32(float32x2_t a, float32x2_t b) {
+// CIR: cir.fadd
+
+// LLVM-SAME: <2 x float> {{.*}}[[A:%.*]], <2 x float> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = fadd <2 x float> [[A]], [[B]]
+// LLVM: ret <2 x float> [[ADD_I]]
+ return vadd_f32(a, b);
+}
+
+// LLVM-LABEL: @test_vadd_u8(
+// CIR-LABEL: @vadd_u8(
+uint8x8_t test_vadd_u8(uint8x8_t a, uint8x8_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: <8 x i8> {{.*}}[[A:%.*]], <8 x i8> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = add <8 x i8> [[A]], [[B]]
+// LLVM: ret <8 x i8> [[ADD_I]]
+ return vadd_u8(a, b);
+}
+
+// LLVM-LABEL: @test_vadd_u16(
+// CIR-LABEL: @vadd_u16(
+uint16x4_t test_vadd_u16(uint16x4_t a, uint16x4_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: <4 x i16> {{.*}}[[A:%.*]], <4 x i16> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = add <4 x i16> [[A]], [[B]]
+// LLVM: ret <4 x i16> [[ADD_I]]
+ return vadd_u16(a, b);
+}
+
+// LLVM-LABEL: @test_vadd_u32(
+// CIR-LABEL: @vadd_u32(
+uint32x2_t test_vadd_u32(uint32x2_t a, uint32x2_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]], <2 x i32> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = add <2 x i32> [[A]], [[B]]
+// LLVM: ret <2 x i32> [[ADD_I]]
+ return vadd_u32(a, b);
+}
+
+// LLVM-LABEL: @test_vadd_u64(
+// CIR-LABEL: @vadd_u64(
+uint64x1_t test_vadd_u64(uint64x1_t a, uint64x1_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: <1 x i64> {{.*}}[[A:%.*]], <1 x i64> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = add <1 x i64> [[A]], [[B]]
+// LLVM: ret <1 x i64> [[ADD_I]]
+ return vadd_u64(a, b);
+}
+
+// LLVM-LABEL: @test_vaddq_s8(
+// CIR-LABEL: @vaddq_s8(
+int8x16_t test_vaddq_s8(int8x16_t a, int8x16_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]], <16 x i8> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = add <16 x i8> [[A]], [[B]]
+// LLVM: ret <16 x i8> [[ADD_I]]
+ return vaddq_s8(a, b);
+}
+
+// LLVM-LABEL: @test_vaddq_s16(
+// CIR-LABEL: @vaddq_s16(
+int16x8_t test_vaddq_s16(int16x8_t a, int16x8_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]], <8 x i16> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = add <8 x i16> [[A]], [[B]]
+// LLVM: ret <8 x i16> [[ADD_I]]
+ return vaddq_s16(a, b);
+}
+
+// LLVM-LABEL: @test_vaddq_s32(
+// CIR-LABEL: @vaddq_s32(
+int32x4_t test_vaddq_s32(int32x4_t a, int32x4_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: <4 x i32> {{.*}}[[A:%.*]], <4 x i32> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = add <4 x i32> [[A]], [[B]]
+// LLVM: ret <4 x i32> [[ADD_I]]
+ return vaddq_s32(a, b);
+}
+
+// LLVM-LABEL: @test_vaddq_s64(
+// CIR-LABEL: @vaddq_s64(
+int64x2_t test_vaddq_s64(int64x2_t a, int64x2_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: <2 x i64> {{.*}}[[A:%.*]], <2 x i64> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = add <2 x i64> [[A]], [[B]]
+// LLVM: ret <2 x i64> [[ADD_I]]
+ return vaddq_s64(a, b);
+}
+
+// LLVM-LABEL: @test_vaddq_f32(
+// CIR-LABEL: @vaddq_f32(
+float32x4_t test_vaddq_f32(float32x4_t a, float32x4_t b) {
+// CIR: cir.fadd
+
+// LLVM-SAME: <4 x float> {{.*}}[[A:%.*]], <4 x float> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = fadd <4 x float> [[A]], [[B]]
+// LLVM: ret <4 x float> [[ADD_I]]
+ return vaddq_f32(a, b);
+}
+
+// LLVM-LABEL: @test_vaddq_f64(
+// CIR-LABEL: @vaddq_f64(
+float64x2_t test_vaddq_f64(float64x2_t a, float64x2_t b) {
+// CIR: cir.fadd
+
+// LLVM-SAME: <2 x double> {{.*}}[[A:%.*]], <2 x double> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = fadd <2 x double> [[A]], [[B]]
+// LLVM: ret <2 x double> [[ADD_I]]
+ return vaddq_f64(a, b);
+}
+
+// LLVM-LABEL: @test_vaddq_u8(
+// CIR-LABEL: @vaddq_u8(
+uint8x16_t test_vaddq_u8(uint8x16_t a, uint8x16_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]], <16 x i8> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = add <16 x i8> [[A]], [[B]]
+// LLVM: ret <16 x i8> [[ADD_I]]
+ return vaddq_u8(a, b);
+}
+
+// LLVM-LABEL: @test_vaddq_u16(
+// CIR-LABEL: @vaddq_u16(
+uint16x8_t test_vaddq_u16(uint16x8_t a, uint16x8_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]], <8 x i16> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = add <8 x i16> [[A]], [[B]]
+// LLVM: ret <8 x i16> [[ADD_I]]
+ return vaddq_u16(a, b);
+}
+
+// LLVM-LABEL: @test_vaddq_u32(
+// CIR-LABEL: @vaddq_u32(
+uint32x4_t test_vaddq_u32(uint32x4_t a, uint32x4_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: <4 x i32> {{.*}}[[A:%.*]], <4 x i32> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = add <4 x i32> [[A]], [[B]]
+// LLVM: ret <4 x i32> [[ADD_I]]
+ return vaddq_u32(a, b);
+}
+
+// LLVM-LABEL: @test_vaddq_u64(
+// CIR-LABEL: @vaddq_u64(
+uint64x2_t test_vaddq_u64(uint64x2_t a, uint64x2_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: <2 x i64> {{.*}}[[A:%.*]], <2 x i64> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = add <2 x i64> [[A]], [[B]]
+// LLVM: ret <2 x i64> [[ADD_I]]
+ return vaddq_u64(a, b);
+}
+
+// LLVM-LABEL: @test_vadd_f64(
+// CIR-LABEL: @vadd_f64(
+float64x1_t test_vadd_f64(float64x1_t a, float64x1_t b) {
+// CIR: cir.fadd
+
+// LLVM-SAME: <1 x double> {{.*}}[[A:%.*]], <1 x double> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = fadd <1 x double> [[A]], [[B]]
+// LLVM: ret <1 x double> [[ADD_I]]
+ return vadd_f64(a, b);
+}
+
+// LLVM-LABEL: @test_vaddd_s64(
+// CIR-LABEL: @vaddd_s64(
+int64_t test_vaddd_s64(int64_t a, int64_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: i64 {{.*}}[[A:%.*]], i64 {{.*}}[[B:%.*]])
+// LLVM: [[VADDD_I:%.*]] = add i64 [[A]], [[B]]
+// LLVM: ret i64 [[VADDD_I]]
+ return vaddd_s64(a, b);
+}
+
+// LLVM-LABEL: @test_vaddd_u64(
+// CIR-LABEL: @vaddd_u64(
+uint64_t test_vaddd_u64(uint64_t a, uint64_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: i64 {{.*}}[[A:%.*]], i64 {{.*}}[[B:%.*]])
+// LLVM: [[VADDD_I:%.*]] = add i64 [[A]], [[B]]
+// LLVM: ret i64 [[VADDD_I]]
+ return vaddd_u64(a, b);
+}
+
//===----------------------------------------------------------------------===//
// 2.2.2.1.2. Polynomial addition
// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#polynomial-addition
@@ -102,4 +349,3 @@ poly128_t test_vaddq_p128(poly128_t a, poly128_t b) {
// LLVM-NEXT: ret i128 [[TMP3]]
return vaddq_p128(a, b);
}
-
diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c
index a74e7842b2c4a..ca3ae478d6546 100644
--- a/clang/test/CodeGen/AArch64/neon/intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c
@@ -6881,250 +6881,3 @@ float64_t test_vpmaxnmqd_f64(float64x2_t a) {
// LLVM-NEXT: ret double [[VPMAXNMQD_F64_I]]
return vpmaxnmqd_f64(a);
}
-
-//===------------------------------------------------------===//
-// 2.1.1.1.1 Addition
-// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#addition
-//===------------------------------------------------------===//
-
-// LLVM-LABEL: @test_vadd_s8(
-// CIR-LABEL: @vadd_s8(
-int8x8_t test_vadd_s8(int8x8_t a, int8x8_t b) {
-// CIR: cir.add
-
-// LLVM-SAME: <8 x i8> {{.*}}[[A:%.*]], <8 x i8> {{.*}}[[B:%.*]])
-// LLVM: [[ADD_I:%.*]] = add <8 x i8> [[A]], [[B]]
-// LLVM: ret <8 x i8> [[ADD_I]]
- return vadd_s8(a, b);
-}
-
-// LLVM-LABEL: @test_vadd_s16(
-// CIR-LABEL: @vadd_s16(
-int16x4_t test_vadd_s16(int16x4_t a, int16x4_t b) {
-// CIR: cir.add
-
-// LLVM-SAME: <4 x i16> {{.*}}[[A:%.*]], <4 x i16> {{.*}}[[B:%.*]])
-// LLVM: [[ADD_I:%.*]] = add <4 x i16> [[A]], [[B]]
-// LLVM: ret <4 x i16> [[ADD_I]]
- return vadd_s16(a, b);
-}
-
-// LLVM-LABEL: @test_vadd_s32(
-// CIR-LABEL: @vadd_s32(
-int32x2_t test_vadd_s32(int32x2_t a, int32x2_t b) {
-// CIR: cir.add
-
-// LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]], <2 x i32> {{.*}}[[B:%.*]])
-// LLVM: [[ADD_I:%.*]] = add <2 x i32> [[A]], [[B]]
-// LLVM: ret <2 x i32> [[ADD_I]]
- return vadd_s32(a, b);
-}
-
-// LLVM-LABEL: @test_vadd_s64(
-// CIR-LABEL: @vadd_s64(
-int64x1_t test_vadd_s64(int64x1_t a, int64x1_t b) {
-// CIR: cir.add
-
-// LLVM-SAME: <1 x i64> {{.*}}[[A:%.*]], <1 x i64> {{.*}}[[B:%.*]])
-// LLVM: [[ADD_I:%.*]] = add <1 x i64> [[A]], [[B]]
-// LLVM: ret <1 x i64> [[ADD_I]]
- return vadd_s64(a, b);
-}
-
-// LLVM-LABEL: @test_vadd_f32(
-// CIR-LABEL: @vadd_f32(
-float32x2_t test_vadd_f32(float32x2_t a, float32x2_t b) {
-// CIR: cir.fadd
-
-// LLVM-SAME: <2 x float> {{.*}}[[A:%.*]], <2 x float> {{.*}}[[B:%.*]])
-// LLVM: [[ADD_I:%.*]] = fadd <2 x float> [[A]], [[B]]
-// LLVM: ret <2 x float> [[ADD_I]]
- return vadd_f32(a, b);
-}
-
-// LLVM-LABEL: @test_vadd_u8(
-// CIR-LABEL: @vadd_u8(
-uint8x8_t test_vadd_u8(uint8x8_t a, uint8x8_t b) {
-// CIR: cir.add
-
-// LLVM-SAME: <8 x i8> {{.*}}[[A:%.*]], <8 x i8> {{.*}}[[B:%.*]])
-// LLVM: [[ADD_I:%.*]] = add <8 x i8> [[A]], [[B]]
-// LLVM: ret <8 x i8> [[ADD_I]]
- return vadd_u8(a, b);
-}
-
-// LLVM-LABEL: @test_vadd_u16(
-// CIR-LABEL: @vadd_u16(
-uint16x4_t test_vadd_u16(uint16x4_t a, uint16x4_t b) {
-// CIR: cir.add
-
-// LLVM-SAME: <4 x i16> {{.*}}[[A:%.*]], <4 x i16> {{.*}}[[B:%.*]])
-// LLVM: [[ADD_I:%.*]] = add <4 x i16> [[A]], [[B]]
-// LLVM: ret <4 x i16> [[ADD_I]]
- return vadd_u16(a, b);
-}
-
-// LLVM-LABEL: @test_vadd_u32(
-// CIR-LABEL: @vadd_u32(
-uint32x2_t test_vadd_u32(uint32x2_t a, uint32x2_t b) {
-// CIR: cir.add
-
-// LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]], <2 x i32> {{.*}}[[B:%.*]])
-// LLVM: [[ADD_I:%.*]] = add <2 x i32> [[A]], [[B]]
-// LLVM: ret <2 x i32> [[ADD_I]]
- return vadd_u32(a, b);
-}
-
-// LLVM-LABEL: @test_vadd_u64(
-// CIR-LABEL: @vadd_u64(
-uint64x1_t test_vadd_u64(uint64x1_t a, uint64x1_t b) {
-// CIR: cir.add
-
-// LLVM-SAME: <1 x i64> {{.*}}[[A:%.*]], <1 x i64> {{.*}}[[B:%.*]])
-// LLVM: [[ADD_I:%.*]] = add <1 x i64> [[A]], [[B]]
-// LLVM: ret <1 x i64> [[ADD_I]]
- return vadd_u64(a, b);
-}
-
-// LLVM-LABEL: @test_vaddq_s8(
-// CIR-LABEL: @vaddq_s8(
-int8x16_t test_vaddq_s8(int8x16_t a, int8x16_t b) {
-// CIR: cir.add
-
-// LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]], <16 x i8> {{.*}}[[B:%.*]])
-// LLVM: [[ADD_I:%.*]] = add <16 x i8> [[A]], [[B]]
-// LLVM: ret <16 x i8> [[ADD_I]]
- return vaddq_s8(a, b);
-}
-
-// LLVM-LABEL: @test_vaddq_s16(
-// CIR-LABEL: @vaddq_s16(
-int16x8_t test_vaddq_s16(int16x8_t a, int16x8_t b) {
-// CIR: cir.add
-
-// LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]], <8 x i16> {{.*}}[[B:%.*]])
-// LLVM: [[ADD_I:%.*]] = add <8 x i16> [[A]], [[B]]
-// LLVM: ret <8 x i16> [[ADD_I]]
- return vaddq_s16(a, b);
-}
-
-// LLVM-LABEL: @test_vaddq_s32(
-// CIR-LABEL: @vaddq_s32(
-int32x4_t test_vaddq_s32(int32x4_t a, int32x4_t b) {
-// CIR: cir.add
-
-// LLVM-SAME: <4 x i32> {{.*}}[[A:%.*]], <4 x i32> {{.*}}[[B:%.*]])
-// LLVM: [[ADD_I:%.*]] = add <4 x i32> [[A]], [[B]]
-// LLVM: ret <4 x i32> [[ADD_I]]
- return vaddq_s32(a, b);
-}
-
-// LLVM-LABEL: @test_vaddq_s64(
-// CIR-LABEL: @vaddq_s64(
-int64x2_t test_vaddq_s64(int64x2_t a, int64x2_t b) {
-// CIR: cir.add
-
-// LLVM-SAME: <2 x i64> {{.*}}[[A:%.*]], <2 x i64> {{.*}}[[B:%.*]])
-// LLVM: [[ADD_I:%.*]] = add <2 x i64> [[A]], [[B]]
-// LLVM: ret <2 x i64> [[ADD_I]]
- return vaddq_s64(a, b);
-}
-
-// LLVM-LABEL: @test_vaddq_f32(
-// CIR-LABEL: @vaddq_f32(
-float32x4_t test_vaddq_f32(float32x4_t a, float32x4_t b) {
-// CIR: cir.fadd
-
-// LLVM-SAME: <4 x float> {{.*}}[[A:%.*]], <4 x float> {{.*}}[[B:%.*]])
-// LLVM: [[ADD_I:%.*]] = fadd <4 x float> [[A]], [[B]]
-// LLVM: ret <4 x float> [[ADD_I]]
- return vaddq_f32(a, b);
-}
-
-// LLVM-LABEL: @test_vaddq_f64(
-// CIR-LABEL: @vaddq_f64(
-float64x2_t test_vaddq_f64(float64x2_t a, float64x2_t b) {
-// CIR: cir.fadd
-
-// LLVM-SAME: <2 x double> {{.*}}[[A:%.*]], <2 x double> {{.*}}[[B:%.*]])
-// LLVM: [[ADD_I:%.*]] = fadd <2 x double> [[A]], [[B]]
-// LLVM: ret <2 x double> [[ADD_I]]
- return vaddq_f64(a, b);
-}
-
-// LLVM-LABEL: @test_vaddq_u8(
-// CIR-LABEL: @vaddq_u8(
-uint8x16_t test_vaddq_u8(uint8x16_t a, uint8x16_t b) {
-// CIR: cir.add
-
-// LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]], <16 x i8> {{.*}}[[B:%.*]])
-// LLVM: [[ADD_I:%.*]] = add <16 x i8> [[A]], [[B]]
-// LLVM: ret <16 x i8> [[ADD_I]]
- return vaddq_u8(a, b);
-}
-
-// LLVM-LABEL: @test_vaddq_u16(
-// CIR-LABEL: @vaddq_u16(
-uint16x8_t test_vaddq_u16(uint16x8_t a, uint16x8_t b) {
-// CIR: cir.add
-
-// LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]], <8 x i16> {{.*}}[[B:%.*]])
-// LLVM: [[ADD_I:%.*]] = add <8 x i16> [[A]], [[B]]
-// LLVM: ret <8 x i16> [[ADD_I]]
- return vaddq_u16(a, b);
-}
-
-// LLVM-LABEL: @test_vaddq_u32(
-// CIR-LABEL: @vaddq_u32(
-uint32x4_t test_vaddq_u32(uint32x4_t a, uint32x4_t b) {
-// CIR: cir.add
-
-// LLVM-SAME: <4 x i32> {{.*}}[[A:%.*]], <4 x i32> {{.*}}[[B:%.*]])
-// LLVM: [[ADD_I:%.*]] = add <4 x i32> [[A]], [[B]]
-// LLVM: ret <4 x i32> [[ADD_I]]
- return vaddq_u32(a, b);
-}
-
-// LLVM-LABEL: @test_vaddq_u64(
-// CIR-LABEL: @vaddq_u64(
-uint64x2_t test_vaddq_u64(uint64x2_t a, uint64x2_t b) {
-// CIR: cir.add
-
-// LLVM-SAME: <2 x i64> {{.*}}[[A:%.*]], <2 x i64> {{.*}}[[B:%.*]])
-// LLVM: [[ADD_I:%.*]] = add <2 x i64> [[A]], [[B]]
-// LLVM: ret <2 x i64> [[ADD_I]]
- return vaddq_u64(a, b);
-}
-
-// LLVM-LABEL: @test_vadd_f64(
-// CIR-LABEL: @vadd_f64(
-float64x1_t test_vadd_f64(float64x1_t a, float64x1_t b) {
-// CIR: cir.fadd
-
-// LLVM-SAME: <1 x double> {{.*}}[[A:%.*]], <1 x double> {{.*}}[[B:%.*]])
-// LLVM: [[ADD_I:%.*]] = fadd <1 x double> [[A]], [[B]]
-// LLVM: ret <1 x double> [[ADD_I]]
- return vadd_f64(a, b);
-}
-
-// LLVM-LABEL: @test_vaddd_s64(
-// CIR-LABEL: @vaddd_s64(
-int64_t test_vaddd_s64(int64_t a, int64_t b) {
-// CIR: cir.add
-
-// LLVM-SAME: i64 {{.*}}[[A:%.*]], i64 {{.*}}[[B:%.*]])
-// LLVM: [[VADDD_I:%.*]] = add i64 [[A]], [[B]]
-// LLVM: ret i64 [[VADDD_I]]
- return vaddd_s64(a, b);
-}
-
-// LLVM-LABEL: @test_vaddd_u64(
-// CIR-LABEL: @vaddd_u64(
-uint64_t test_vaddd_u64(uint64_t a, uint64_t b) {
-// CIR: cir.add
-
-// LLVM-SAME: i64 {{.*}}[[A:%.*]], i64 {{.*}}[[B:%.*]])
-// LLVM: [[VADDD_I:%.*]] = add i64 [[A]], [[B]]
-// LLVM: ret i64 [[VADDD_I]]
- return vaddd_u64(a, b);
-}
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