[clang] [CIR][AArch64] Lower NEON subtraction intrinsics (PR #202857)
Jiahao Guo via cfe-commits
cfe-commits at lists.llvm.org
Thu Jun 11 06:13:54 PDT 2026
https://github.com/E00N777 updated https://github.com/llvm/llvm-project/pull/202857
>From 5839db1f346e3d2db4c0119e9dcd6b655961727c Mon Sep 17 00:00:00 2001
From: E0N777 <E0N_gjh at 163.com>
Date: Wed, 10 Jun 2026 13:21:43 +0800
Subject: [PATCH] [CIR][AArch64] Lower NEON subtraction intrinsics
---
.../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 5 +
clang/test/CodeGen/AArch64/neon-intrinsics.c | 220 ---------------
clang/test/CodeGen/AArch64/neon/subtraction.c | 266 ++++++++++++++++++
3 files changed, 271 insertions(+), 220 deletions(-)
create mode 100644 clang/test/CodeGen/AArch64/neon/subtraction.c
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index 4111df26d241d..0a35ada0db2f8 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -2528,8 +2528,13 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
convertType(expr->getType()), ops);
case NEON::BI__builtin_neon_vaddd_s64:
case NEON::BI__builtin_neon_vaddd_u64:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
case NEON::BI__builtin_neon_vsubd_s64:
case NEON::BI__builtin_neon_vsubd_u64:
+ return builder.createSub(loc, ops[0], ops[1]);
case NEON::BI__builtin_neon_vqdmlalh_s16:
case NEON::BI__builtin_neon_vqdmlslh_s16:
cgm.errorNYI(expr->getSourceRange(),
diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c
index 5865c4cf61b50..e204b311fa292 100644
--- a/clang/test/CodeGen/AArch64/neon-intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c
@@ -195,196 +195,6 @@ uint64x2_t test_vaddq_u64(uint64x2_t v1, uint64x2_t v2) {
return vaddq_u64(v1, v2);
}
-// CHECK-LABEL: define dso_local <8 x i8> @test_vsub_s8(
-// CHECK-SAME: <8 x i8> noundef [[V1:%.*]], <8 x i8> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[SUB_I:%.*]] = sub <8 x i8> [[V1]], [[V2]]
-// CHECK-NEXT: ret <8 x i8> [[SUB_I]]
-//
-int8x8_t test_vsub_s8(int8x8_t v1, int8x8_t v2) {
- return vsub_s8(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <4 x i16> @test_vsub_s16(
-// CHECK-SAME: <4 x i16> noundef [[V1:%.*]], <4 x i16> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[SUB_I:%.*]] = sub <4 x i16> [[V1]], [[V2]]
-// CHECK-NEXT: ret <4 x i16> [[SUB_I]]
-//
-int16x4_t test_vsub_s16(int16x4_t v1, int16x4_t v2) {
- return vsub_s16(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <2 x i32> @test_vsub_s32(
-// CHECK-SAME: <2 x i32> noundef [[V1:%.*]], <2 x i32> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[SUB_I:%.*]] = sub <2 x i32> [[V1]], [[V2]]
-// CHECK-NEXT: ret <2 x i32> [[SUB_I]]
-//
-int32x2_t test_vsub_s32(int32x2_t v1, int32x2_t v2) {
- return vsub_s32(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <1 x i64> @test_vsub_s64(
-// CHECK-SAME: <1 x i64> noundef [[V1:%.*]], <1 x i64> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[SUB_I:%.*]] = sub <1 x i64> [[V1]], [[V2]]
-// CHECK-NEXT: ret <1 x i64> [[SUB_I]]
-//
-int64x1_t test_vsub_s64(int64x1_t v1, int64x1_t v2) {
- return vsub_s64(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <2 x float> @test_vsub_f32(
-// CHECK-SAME: <2 x float> noundef [[V1:%.*]], <2 x float> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[SUB_I:%.*]] = fsub <2 x float> [[V1]], [[V2]]
-// CHECK-NEXT: ret <2 x float> [[SUB_I]]
-//
-float32x2_t test_vsub_f32(float32x2_t v1, float32x2_t v2) {
- return vsub_f32(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <8 x i8> @test_vsub_u8(
-// CHECK-SAME: <8 x i8> noundef [[V1:%.*]], <8 x i8> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[SUB_I:%.*]] = sub <8 x i8> [[V1]], [[V2]]
-// CHECK-NEXT: ret <8 x i8> [[SUB_I]]
-//
-uint8x8_t test_vsub_u8(uint8x8_t v1, uint8x8_t v2) {
- return vsub_u8(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <4 x i16> @test_vsub_u16(
-// CHECK-SAME: <4 x i16> noundef [[V1:%.*]], <4 x i16> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[SUB_I:%.*]] = sub <4 x i16> [[V1]], [[V2]]
-// CHECK-NEXT: ret <4 x i16> [[SUB_I]]
-//
-uint16x4_t test_vsub_u16(uint16x4_t v1, uint16x4_t v2) {
- return vsub_u16(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <2 x i32> @test_vsub_u32(
-// CHECK-SAME: <2 x i32> noundef [[V1:%.*]], <2 x i32> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[SUB_I:%.*]] = sub <2 x i32> [[V1]], [[V2]]
-// CHECK-NEXT: ret <2 x i32> [[SUB_I]]
-//
-uint32x2_t test_vsub_u32(uint32x2_t v1, uint32x2_t v2) {
- return vsub_u32(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <1 x i64> @test_vsub_u64(
-// CHECK-SAME: <1 x i64> noundef [[V1:%.*]], <1 x i64> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[SUB_I:%.*]] = sub <1 x i64> [[V1]], [[V2]]
-// CHECK-NEXT: ret <1 x i64> [[SUB_I]]
-//
-uint64x1_t test_vsub_u64(uint64x1_t v1, uint64x1_t v2) {
- return vsub_u64(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <16 x i8> @test_vsubq_s8(
-// CHECK-SAME: <16 x i8> noundef [[V1:%.*]], <16 x i8> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[SUB_I:%.*]] = sub <16 x i8> [[V1]], [[V2]]
-// CHECK-NEXT: ret <16 x i8> [[SUB_I]]
-//
-int8x16_t test_vsubq_s8(int8x16_t v1, int8x16_t v2) {
- return vsubq_s8(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <8 x i16> @test_vsubq_s16(
-// CHECK-SAME: <8 x i16> noundef [[V1:%.*]], <8 x i16> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[SUB_I:%.*]] = sub <8 x i16> [[V1]], [[V2]]
-// CHECK-NEXT: ret <8 x i16> [[SUB_I]]
-//
-int16x8_t test_vsubq_s16(int16x8_t v1, int16x8_t v2) {
- return vsubq_s16(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <4 x i32> @test_vsubq_s32(
-// CHECK-SAME: <4 x i32> noundef [[V1:%.*]], <4 x i32> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[SUB_I:%.*]] = sub <4 x i32> [[V1]], [[V2]]
-// CHECK-NEXT: ret <4 x i32> [[SUB_I]]
-//
-int32x4_t test_vsubq_s32(int32x4_t v1, int32x4_t v2) {
- return vsubq_s32(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <2 x i64> @test_vsubq_s64(
-// CHECK-SAME: <2 x i64> noundef [[V1:%.*]], <2 x i64> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[SUB_I:%.*]] = sub <2 x i64> [[V1]], [[V2]]
-// CHECK-NEXT: ret <2 x i64> [[SUB_I]]
-//
-int64x2_t test_vsubq_s64(int64x2_t v1, int64x2_t v2) {
- return vsubq_s64(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <4 x float> @test_vsubq_f32(
-// CHECK-SAME: <4 x float> noundef [[V1:%.*]], <4 x float> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[SUB_I:%.*]] = fsub <4 x float> [[V1]], [[V2]]
-// CHECK-NEXT: ret <4 x float> [[SUB_I]]
-//
-float32x4_t test_vsubq_f32(float32x4_t v1, float32x4_t v2) {
- return vsubq_f32(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <2 x double> @test_vsubq_f64(
-// CHECK-SAME: <2 x double> noundef [[V1:%.*]], <2 x double> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[SUB_I:%.*]] = fsub <2 x double> [[V1]], [[V2]]
-// CHECK-NEXT: ret <2 x double> [[SUB_I]]
-//
-float64x2_t test_vsubq_f64(float64x2_t v1, float64x2_t v2) {
- return vsubq_f64(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <16 x i8> @test_vsubq_u8(
-// CHECK-SAME: <16 x i8> noundef [[V1:%.*]], <16 x i8> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[SUB_I:%.*]] = sub <16 x i8> [[V1]], [[V2]]
-// CHECK-NEXT: ret <16 x i8> [[SUB_I]]
-//
-uint8x16_t test_vsubq_u8(uint8x16_t v1, uint8x16_t v2) {
- return vsubq_u8(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <8 x i16> @test_vsubq_u16(
-// CHECK-SAME: <8 x i16> noundef [[V1:%.*]], <8 x i16> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[SUB_I:%.*]] = sub <8 x i16> [[V1]], [[V2]]
-// CHECK-NEXT: ret <8 x i16> [[SUB_I]]
-//
-uint16x8_t test_vsubq_u16(uint16x8_t v1, uint16x8_t v2) {
- return vsubq_u16(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <4 x i32> @test_vsubq_u32(
-// CHECK-SAME: <4 x i32> noundef [[V1:%.*]], <4 x i32> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[SUB_I:%.*]] = sub <4 x i32> [[V1]], [[V2]]
-// CHECK-NEXT: ret <4 x i32> [[SUB_I]]
-//
-uint32x4_t test_vsubq_u32(uint32x4_t v1, uint32x4_t v2) {
- return vsubq_u32(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <2 x i64> @test_vsubq_u64(
-// CHECK-SAME: <2 x i64> noundef [[V1:%.*]], <2 x i64> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[SUB_I:%.*]] = sub <2 x i64> [[V1]], [[V2]]
-// CHECK-NEXT: ret <2 x i64> [[SUB_I]]
-//
-uint64x2_t test_vsubq_u64(uint64x2_t v1, uint64x2_t v2) {
- return vsubq_u64(v1, v2);
-}
-
// CHECK-LABEL: define dso_local <8 x i8> @test_vmul_s8(
// CHECK-SAME: <8 x i8> noundef [[V1:%.*]], <8 x i8> noundef [[V2:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
@@ -8260,26 +8070,6 @@ uint64_t test_vaddd_u64(uint64_t a, uint64_t b) {
return vaddd_u64(a, b);
}
-// CHECK-LABEL: define dso_local i64 @test_vsubd_s64(
-// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VSUBD_I:%.*]] = sub i64 [[A]], [[B]]
-// CHECK-NEXT: ret i64 [[VSUBD_I]]
-//
-int64_t test_vsubd_s64(int64_t a, int64_t b) {
- return vsubd_s64(a, b);
-}
-
-// CHECK-LABEL: define dso_local i64 @test_vsubd_u64(
-// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VSUBD_I:%.*]] = sub i64 [[A]], [[B]]
-// CHECK-NEXT: ret i64 [[VSUBD_I]]
-//
-uint64_t test_vsubd_u64(uint64_t a, uint64_t b) {
- return vsubd_u64(a, b);
-}
-
// CHECK-LABEL: define dso_local i8 @test_vqaddb_s8(
// CHECK-SAME: i8 noundef [[A:%.*]], i8 noundef [[B:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
@@ -18593,16 +18383,6 @@ float64x1_t test_vfms_f64(float64x1_t a, float64x1_t b, float64x1_t c) {
return vfms_f64(a, b, c);
}
-// CHECK-LABEL: define dso_local <1 x double> @test_vsub_f64(
-// CHECK-SAME: <1 x double> noundef [[A:%.*]], <1 x double> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[SUB_I:%.*]] = fsub <1 x double> [[A]], [[B]]
-// CHECK-NEXT: ret <1 x double> [[SUB_I]]
-//
-float64x1_t test_vsub_f64(float64x1_t a, float64x1_t b) {
- return vsub_f64(a, b);
-}
-
// CHECK-LABEL: define dso_local <1 x double> @test_vabd_f64(
// CHECK-SAME: <1 x double> noundef [[A:%.*]], <1 x double> noundef [[B:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
diff --git a/clang/test/CodeGen/AArch64/neon/subtraction.c b/clang/test/CodeGen/AArch64/neon/subtraction.c
new file mode 100644
index 0000000000000..3811850a27c2e
--- /dev/null
+++ b/clang/test/CodeGen/AArch64/neon/subtraction.c
@@ -0,0 +1,266 @@
+// REQUIRES: aarch64-registered-target || arm-registered-target
+
+// RUN: %clang_cc1_cg_arm64_neon -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=LLVM
+// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon -fclangir -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=LLVM %}
+// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon -fclangir -emit-cir %s -disable-O0-optnone | FileCheck %s --check-prefixes=CIR %}
+
+//=============================================================================
+// NOTES
+//
+// Tests for vector subtraction intrinsics: Subtraction, Widening subtraction, Narrowing subtraction and Saturating subtract elements.
+//
+// ACLE section headings based on v2025Q2 of the ACLE specification:
+// * https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#subtract
+//
+// TODO: Migrate Widening subtraction, Narrowing subtraction and Saturating subtract test cases.
+//
+//=============================================================================
+
+#include <arm_neon.h>
+
+//===------------------------------------------------------===//
+// 2.1.1.5.1. Subtraction
+// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#subtraction
+//===------------------------------------------------------===//
+
+// LLVM-LABEL: @test_vsub_s8(
+// CIR-LABEL: @vsub_s8(
+int8x8_t test_vsub_s8(int8x8_t v1, int8x8_t v2) {
+// CIR: [[SUB_I:%.*]] = cir.sub [[V1:%.*]], [[V2:%.*]] : !cir.vector<8 x !s8i>
+
+// LLVM-SAME: <8 x i8> {{.*}} [[V1:%.*]], <8 x i8> {{.*}} [[V2:%.*]])
+// LLVM: [[SUB_I:%.*]] = sub <8 x i8> [[V1]], [[V2]]
+// LLVM: ret <8 x i8> [[SUB_I]]
+ return vsub_s8(v1, v2);
+}
+
+// LLVM-LABEL: @test_vsubq_s8(
+// CIR-LABEL: @vsubq_s8(
+int8x16_t test_vsubq_s8(int8x16_t v1, int8x16_t v2) {
+// CIR: [[SUB_I:%.*]] = cir.sub [[V1:%.*]], [[V2:%.*]] : !cir.vector<16 x !s8i>
+
+// LLVM-SAME: <16 x i8> {{.*}} [[V1:%.*]], <16 x i8> {{.*}} [[V2:%.*]])
+// LLVM: [[SUB_I:%.*]] = sub <16 x i8> [[V1]], [[V2]]
+// LLVM: ret <16 x i8> [[SUB_I]]
+ return vsubq_s8(v1, v2);
+}
+
+// LLVM-LABEL: @test_vsub_s16(
+// CIR-LABEL: @vsub_s16(
+int16x4_t test_vsub_s16(int16x4_t v1, int16x4_t v2) {
+// CIR: [[SUB_I:%.*]] = cir.sub [[V1:%.*]], [[V2:%.*]] : !cir.vector<4 x !s16i>
+
+// LLVM-SAME: <4 x i16> {{.*}} [[V1:%.*]], <4 x i16> {{.*}} [[V2:%.*]])
+// LLVM: [[SUB_I:%.*]] = sub <4 x i16> [[V1]], [[V2]]
+// LLVM: ret <4 x i16> [[SUB_I]]
+ return vsub_s16(v1, v2);
+}
+
+// LLVM-LABEL: @test_vsubq_s16(
+// CIR-LABEL: @vsubq_s16(
+int16x8_t test_vsubq_s16(int16x8_t v1, int16x8_t v2) {
+// CIR: [[SUB_I:%.*]] = cir.sub [[V1:%.*]], [[V2:%.*]] : !cir.vector<8 x !s16i>
+
+// LLVM-SAME: <8 x i16> {{.*}} [[V1:%.*]], <8 x i16> {{.*}} [[V2:%.*]])
+// LLVM: [[SUB_I:%.*]] = sub <8 x i16> [[V1]], [[V2]]
+// LLVM: ret <8 x i16> [[SUB_I]]
+ return vsubq_s16(v1, v2);
+}
+
+// LLVM-LABEL: @test_vsub_s32(
+// CIR-LABEL: @vsub_s32(
+int32x2_t test_vsub_s32(int32x2_t v1, int32x2_t v2) {
+// CIR: [[SUB_I:%.*]] = cir.sub [[V1:%.*]], [[V2:%.*]] : !cir.vector<2 x !s32i>
+
+// LLVM-SAME: <2 x i32> {{.*}} [[V1:%.*]], <2 x i32> {{.*}} [[V2:%.*]])
+// LLVM: [[SUB_I:%.*]] = sub <2 x i32> [[V1]], [[V2]]
+// LLVM: ret <2 x i32> [[SUB_I]]
+ return vsub_s32(v1, v2);
+}
+
+// LLVM-LABEL: @test_vsubq_s32(
+// CIR-LABEL: @vsubq_s32(
+int32x4_t test_vsubq_s32(int32x4_t v1, int32x4_t v2) {
+// CIR: [[SUB_I:%.*]] = cir.sub [[V1:%.*]], [[V2:%.*]] : !cir.vector<4 x !s32i>
+
+// LLVM-SAME: <4 x i32> {{.*}} [[V1:%.*]], <4 x i32> {{.*}} [[V2:%.*]])
+// LLVM: [[SUB_I:%.*]] = sub <4 x i32> [[V1]], [[V2]]
+// LLVM: ret <4 x i32> [[SUB_I]]
+ return vsubq_s32(v1, v2);
+}
+
+// LLVM-LABEL: @test_vsub_s64(
+// CIR-LABEL: @vsub_s64(
+int64x1_t test_vsub_s64(int64x1_t v1, int64x1_t v2) {
+// CIR: [[SUB_I:%.*]] = cir.sub [[V1:%.*]], [[V2:%.*]] : !cir.vector<1 x !s64i>
+
+// LLVM-SAME: <1 x i64> {{.*}} [[V1:%.*]], <1 x i64> {{.*}} [[V2:%.*]])
+// LLVM: [[SUB_I:%.*]] = sub <1 x i64> [[V1]], [[V2]]
+// LLVM: ret <1 x i64> [[SUB_I]]
+ return vsub_s64(v1, v2);
+}
+
+// LLVM-LABEL: @test_vsubq_s64(
+// CIR-LABEL: @vsubq_s64(
+int64x2_t test_vsubq_s64(int64x2_t v1, int64x2_t v2) {
+// CIR: [[SUB_I:%.*]] = cir.sub [[V1:%.*]], [[V2:%.*]] : !cir.vector<2 x !s64i>
+
+// LLVM-SAME: <2 x i64> {{.*}} [[V1:%.*]], <2 x i64> {{.*}} [[V2:%.*]])
+// LLVM: [[SUB_I:%.*]] = sub <2 x i64> [[V1]], [[V2]]
+// LLVM: ret <2 x i64> [[SUB_I]]
+ return vsubq_s64(v1, v2);
+}
+
+// LLVM-LABEL: @test_vsub_u8(
+// CIR-LABEL: @vsub_u8(
+uint8x8_t test_vsub_u8(uint8x8_t v1, uint8x8_t v2) {
+// CIR: [[SUB_I:%.*]] = cir.sub [[V1:%.*]], [[V2:%.*]] : !cir.vector<8 x !u8i>
+
+// LLVM-SAME: <8 x i8> {{.*}} [[V1:%.*]], <8 x i8> {{.*}} [[V2:%.*]])
+// LLVM: [[SUB_I:%.*]] = sub <8 x i8> [[V1]], [[V2]]
+// LLVM: ret <8 x i8> [[SUB_I]]
+ return vsub_u8(v1, v2);
+}
+
+// LLVM-LABEL: @test_vsub_u16(
+// CIR-LABEL: @vsub_u16(
+uint16x4_t test_vsub_u16(uint16x4_t v1, uint16x4_t v2) {
+// CIR: [[SUB_I:%.*]] = cir.sub [[V1:%.*]], [[V2:%.*]] : !cir.vector<4 x !u16i>
+
+// LLVM-SAME: <4 x i16> {{.*}} [[V1:%.*]], <4 x i16> {{.*}} [[V2:%.*]])
+// LLVM: [[SUB_I:%.*]] = sub <4 x i16> [[V1]], [[V2]]
+// LLVM: ret <4 x i16> [[SUB_I]]
+ return vsub_u16(v1, v2);
+}
+
+// LLVM-LABEL: @test_vsub_u32(
+// CIR-LABEL: @vsub_u32(
+uint32x2_t test_vsub_u32(uint32x2_t v1, uint32x2_t v2) {
+// CIR: [[SUB_I:%.*]] = cir.sub [[V1:%.*]], [[V2:%.*]] : !cir.vector<2 x !u32i>
+
+// LLVM-SAME: <2 x i32> {{.*}} [[V1:%.*]], <2 x i32> {{.*}} [[V2:%.*]])
+// LLVM: [[SUB_I:%.*]] = sub <2 x i32> [[V1]], [[V2]]
+// LLVM: ret <2 x i32> [[SUB_I]]
+ return vsub_u32(v1, v2);
+}
+
+// LLVM-LABEL: @test_vsub_u64(
+// CIR-LABEL: @vsub_u64(
+uint64x1_t test_vsub_u64(uint64x1_t v1, uint64x1_t v2) {
+// CIR: [[SUB_I:%.*]] = cir.sub [[V1:%.*]], [[V2:%.*]] : !cir.vector<1 x !u64i>
+
+// LLVM-SAME: <1 x i64> {{.*}} [[V1:%.*]], <1 x i64> {{.*}} [[V2:%.*]])
+// LLVM: [[SUB_I:%.*]] = sub <1 x i64> [[V1]], [[V2]]
+// LLVM: ret <1 x i64> [[SUB_I]]
+ return vsub_u64(v1, v2);
+}
+
+// LLVM-LABEL: @test_vsubq_u8(
+// CIR-LABEL: @vsubq_u8(
+uint8x16_t test_vsubq_u8(uint8x16_t v1, uint8x16_t v2) {
+// CIR: [[SUB_I:%.*]] = cir.sub [[V1:%.*]], [[V2:%.*]] : !cir.vector<16 x !u8i>
+
+// LLVM-SAME: <16 x i8> {{.*}} [[V1:%.*]], <16 x i8> {{.*}} [[V2:%.*]])
+// LLVM: [[SUB_I:%.*]] = sub <16 x i8> [[V1]], [[V2]]
+// LLVM: ret <16 x i8> [[SUB_I]]
+ return vsubq_u8(v1, v2);
+}
+
+// LLVM-LABEL: @test_vsubq_u16(
+// CIR-LABEL: @vsubq_u16(
+uint16x8_t test_vsubq_u16(uint16x8_t v1, uint16x8_t v2) {
+// CIR: [[SUB_I:%.*]] = cir.sub [[V1:%.*]], [[V2:%.*]] : !cir.vector<8 x !u16i>
+
+// LLVM-SAME: <8 x i16> {{.*}} [[V1:%.*]], <8 x i16> {{.*}} [[V2:%.*]])
+// LLVM: [[SUB_I:%.*]] = sub <8 x i16> [[V1]], [[V2]]
+// LLVM: ret <8 x i16> [[SUB_I]]
+ return vsubq_u16(v1, v2);
+}
+
+// LLVM-LABEL: @test_vsubq_u32(
+// CIR-LABEL: @vsubq_u32(
+uint32x4_t test_vsubq_u32(uint32x4_t v1, uint32x4_t v2) {
+// CIR: [[SUB_I:%.*]] = cir.sub [[V1:%.*]], [[V2:%.*]] : !cir.vector<4 x !u32i>
+
+// LLVM-SAME: <4 x i32> {{.*}} [[V1:%.*]], <4 x i32> {{.*}} [[V2:%.*]])
+// LLVM: [[SUB_I:%.*]] = sub <4 x i32> [[V1]], [[V2]]
+// LLVM: ret <4 x i32> [[SUB_I]]
+ return vsubq_u32(v1, v2);
+}
+
+// LLVM-LABEL: @test_vsubq_u64(
+// CIR-LABEL: @vsubq_u64(
+uint64x2_t test_vsubq_u64(uint64x2_t v1, uint64x2_t v2) {
+// CIR: [[SUB_I:%.*]] = cir.sub [[V1:%.*]], [[V2:%.*]] : !cir.vector<2 x !u64i>
+
+// LLVM-SAME: <2 x i64> {{.*}} [[V1:%.*]], <2 x i64> {{.*}} [[V2:%.*]])
+// LLVM: [[SUB_I:%.*]] = sub <2 x i64> [[V1]], [[V2]]
+// LLVM: ret <2 x i64> [[SUB_I]]
+ return vsubq_u64(v1, v2);
+}
+
+// LLVM-LABEL: @test_vsub_f32(
+// CIR-LABEL: @vsub_f32(
+float32x2_t test_vsub_f32(float32x2_t v1, float32x2_t v2) {
+// CIR: [[SUB_I:%.*]] = cir.fsub [[V1:%.*]], [[V2:%.*]] : !cir.vector<2 x !cir.float>
+
+// LLVM-SAME: <2 x float> {{.*}} [[V1:%.*]], <2 x float> {{.*}} [[V2:%.*]])
+// LLVM: [[SUB_I:%.*]] = fsub <2 x float> [[V1]], [[V2]]
+// LLVM: ret <2 x float> [[SUB_I]]
+ return vsub_f32(v1, v2);
+}
+
+// LLVM-LABEL: @test_vsubq_f32(
+// CIR-LABEL: @vsubq_f32(
+float32x4_t test_vsubq_f32(float32x4_t v1, float32x4_t v2) {
+// CIR: [[SUB_I:%.*]] = cir.fsub [[V1:%.*]], [[V2:%.*]] : !cir.vector<4 x !cir.float>
+
+// LLVM-SAME: <4 x float> {{.*}} [[V1:%.*]], <4 x float> {{.*}} [[V2:%.*]])
+// LLVM: [[SUB_I:%.*]] = fsub <4 x float> [[V1]], [[V2]]
+// LLVM: ret <4 x float> [[SUB_I]]
+ return vsubq_f32(v1, v2);
+}
+
+// LLVM-LABEL: @test_vsub_f64(
+// CIR-LABEL: @vsub_f64(
+float64x1_t test_vsub_f64(float64x1_t a, float64x1_t b) {
+// CIR: [[SUB_I:%.*]] = cir.fsub [[A:%.*]], [[B:%.*]] : !cir.vector<1 x !cir.double>
+
+// LLVM-SAME: <1 x double> {{.*}} [[A:%.*]], <1 x double> {{.*}} [[B:%.*]])
+// LLVM: [[SUB_I:%.*]] = fsub <1 x double> [[A]], [[B]]
+// LLVM: ret <1 x double> [[SUB_I]]
+ return vsub_f64(a, b);
+}
+
+// LLVM-LABEL: @test_vsubq_f64(
+// CIR-LABEL: @vsubq_f64(
+float64x2_t test_vsubq_f64(float64x2_t v1, float64x2_t v2) {
+// CIR: [[SUB_I:%.*]] = cir.fsub [[V1:%.*]], [[V2:%.*]] : !cir.vector<2 x !cir.double>
+
+// LLVM-SAME: <2 x double> {{.*}} [[V1:%.*]], <2 x double> {{.*}} [[V2:%.*]])
+// LLVM: [[SUB_I:%.*]] = fsub <2 x double> [[V1]], [[V2]]
+// LLVM: ret <2 x double> [[SUB_I]]
+ return vsubq_f64(v1, v2);
+}
+
+// LLVM-LABEL: @test_vsubd_s64(
+// CIR-LABEL: @vsubd_s64(
+int64_t test_vsubd_s64(int64_t a, int64_t b) {
+// CIR: [[VSUBD_I:%.*]] = cir.sub [[A:%.*]], [[B:%.*]] : !s64i
+
+// LLVM-SAME: i64 {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]])
+// LLVM: [[VSUBD_I:%.*]] = sub i64 [[A]], [[B]]
+// LLVM: ret i64 [[VSUBD_I]]
+ return vsubd_s64(a, b);
+}
+
+// LLVM-LABEL: @test_vsubd_u64(
+// CIR-LABEL: @vsubd_u64(
+uint64_t test_vsubd_u64(uint64_t a, uint64_t b) {
+// CIR: [[VSUBD_I:%.*]] = cir.sub [[A:%.*]], [[B:%.*]] : !u64i
+
+// LLVM-SAME: i64 {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]])
+// LLVM: [[VSUBD_I:%.*]] = sub i64 [[A]], [[B]]
+// LLVM: ret i64 [[VSUBD_I]]
+ return vsubd_u64(a, b);
+}
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