[clang] [llvm] [AArch64][TableGen] Define ZA, ZT0 and FPMR memory defvars (PR #154144)

[via cfe-commits]

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@@ -3179,9 +3217,9 @@ let TargetPrefix = "aarch64" in {
                               [IntrNoMem, IntrHasSideEffects]>;
 
   def int_aarch64_sme_za_enable
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Lukacma wrote:

I agree that side effects is an overkill here. I suggested it as that's how tpidr2 intrinsics were modelled above. But just marking it as read and write should be good enough to avoid incorrect reordering.

https://github.com/llvm/llvm-project/pull/154144