[clang] [CIR][AArch64] Lower NEON laneq FMA builtins (PR #202337)

[Yair Ben Avraham via cfe-commits]

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@@ -2742,17 +2742,38 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
     llvm::SmallVector<mlir::Value> fmaOps = {laneSource, multiplicand, addend};
     return emitCallMaybeConstrainedBuiltin(builder, loc, "fma", ty, fmaOps);
   }
-  case NEON::BI__builtin_neon_vfmaq_laneq_v:
+  case NEON::BI__builtin_neon_vfmaq_laneq_v: {
+    mlir::Value addend = builder.createBitcast(ops[0], ty);
+    mlir::Value multiplicand = builder.createBitcast(ops[1], ty);
+    mlir::Value laneSource = builder.createBitcast(ops[2], ty);
+    laneSource = emitNeonSplat(builder, loc, laneSource, ops[3], ty.getSize());
+
+    llvm::SmallVector<mlir::Value> fmaOps = {laneSource, multiplicand, addend};
+    return emitCallMaybeConstrainedBuiltin(builder, loc, "fma", ty, fmaOps);
+  }
   case NEON::BI__builtin_neon_vfmah_lane_f16:
   case NEON::BI__builtin_neon_vfmas_lane_f32:
   case NEON::BI__builtin_neon_vfmah_laneq_f16:
   case NEON::BI__builtin_neon_vfmas_laneq_f32:
   case NEON::BI__builtin_neon_vfmad_lane_f64:
-  case NEON::BI__builtin_neon_vfmad_laneq_f64:
     cgm.errorNYI(expr->getSourceRange(),
                  std::string("unimplemented AArch64 builtin call: ") +
                      getContext().BuiltinInfo.getName(builtinID));
     return mlir::Value{};
+  case NEON::BI__builtin_neon_vfmad_laneq_f64: {
+    mlir::Value addend = builder.createBitcast(ops[0], cgm.doubleTy);
+    mlir::Value multiplicand = builder.createBitcast(ops[1], cgm.doubleTy);
+    // The laneq source operand is float64x2_t, so the source vector has two
+    // double lanes.
+    cir::VectorType sourceTy = cir::VectorType::get(cgm.doubleTy, 2);
+    mlir::Value laneSource = builder.createBitcast(ops[2], sourceTy);
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yairbenavraham wrote:

Apparently no, I was trying to be too defensive/consistent with nearby code. Anyway, fixed.

https://github.com/llvm/llvm-project/pull/202337