[clang] [llvm] [AArch64][TableGen] Define ZA, ZT0 and FPMR memory defvars (PR #154144)

[via cfe-commits]

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@@ -3179,9 +3217,9 @@ let TargetPrefix = "aarch64" in {
                               [IntrNoMem, IntrHasSideEffects]>;
 
   def int_aarch64_sme_za_enable
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CarolineConcatto wrote:

Hi Paul,
I think you are correct Paul ZA is linked with ZT0 according to the ACLE.

> ZT0 is architecturally linked to ZA such that changing PSTATE.ZA enables or
> disables both ZA and ZT0 simultaneously.

So if we are adding ZA we should also add ZT0.

However, AFAIU enable/disable za only tell about the availability of ZA, it does not write/read to ZA vector like the other instructions
https://developer.arm.com/documentation/ddi0602/2023-06/Base-Instructions/SMSTART--Enables-access-to-Streaming-SVE-mode-and-SME-architectural-state--an-alias-of-MSR--immediate--?lang=en
So I am not sure we should model them as IntrReadMem/IntrWriteMem, I kind of agree with Marian.

However, again, as we may not agree on that  I will add ZT0 to the list of IntrReadMem/IntrWriteMem.

https://github.com/llvm/llvm-project/pull/154144