[clang] 5868847 - [RISCV] Add Zvfbfa to RISCVABIInfo::coerceVLSVector checks. (#202812)

[via cfe-commits]

Author: Craig Topper
Date: 2026-06-09T22:23:38-07:00
New Revision: 5868847241e2d761843a3a9bed9f4c3703e2ac2c

URL: https://github.com/llvm/llvm-project/commit/5868847241e2d761843a3a9bed9f4c3703e2ac2c
DIFF: https://github.com/llvm/llvm-project/commit/5868847241e2d761843a3a9bed9f4c3703e2ac2c.diff

LOG: [RISCV] Add Zvfbfa to RISCVABIInfo::coerceVLSVector checks. (#202812)

Added: 
    

Modified: 
    clang/lib/CodeGen/Targets/RISCV.cpp
    clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c
    clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.cpp

Removed: 
    


################################################################################
diff  --git a/clang/lib/CodeGen/Targets/RISCV.cpp b/clang/lib/CodeGen/Targets/RISCV.cpp
index bcf2ee6de4293..11e9f8d6a12cb 100644
--- a/clang/lib/CodeGen/Targets/RISCV.cpp
+++ b/clang/lib/CodeGen/Targets/RISCV.cpp
@@ -580,7 +580,8 @@ ABIArgInfo RISCVABIInfo::coerceVLSVector(QualType Ty, unsigned ABIVLen) const {
     // vector with same LMUL.
     const TargetInfo &TI = getContext().getTargetInfo();
     if ((EltType->isHalfTy() && !TI.hasFeature("zvfhmin")) ||
-        (EltType->isBFloatTy() && !TI.hasFeature("zvfbfmin")) ||
+        (EltType->isBFloatTy() && !(TI.hasFeature("zvfbfmin") ||
+                                    TI.hasFeature("experimental-zvfbfa"))) ||
         (EltType->isFloatTy() && !TI.hasFeature("zve32f")) ||
         (EltType->isDoubleTy() && !TI.hasFeature("zve64d")) ||
         (EltType->isIntegerTy(64) && !TI.hasFeature("zve64x")) ||

diff  --git a/clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c b/clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c
index 701df94cb3e10..0e5b76e7d024d 100644
--- a/clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c
+++ b/clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c
@@ -5,6 +5,8 @@
 // RUN:   -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM-ZVE32X %s
 // RUN: %clang_cc1 -std=c23 -triple riscv64 -target-feature +v \
 // RUN:   -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zvfbfa \
+// RUN:   -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM-ZVFBFA %s
 
 #include <riscv_vector.h>
 
@@ -50,15 +52,27 @@ void __attribute__((riscv_vls_cc)) test_vls_default_abi_vlen_unsupported_feature
 // CHECK-LLVM: define dso_local riscv_vls_cc(128) void @test_vls_default_abi_vlen_c23_unsupported_feature(<vscale x 8 x i8> noundef %arg.coerce)
 [[riscv::vls_cc]] void test_vls_default_abi_vlen_c23_unsupported_feature(__attribute__((vector_size(16))) _Float16 arg) {}
 
+// CHECK-LLVM: define dso_local riscv_vls_cc(128) void @test_vls_default_abi_vlen_bfloat(<vscale x 8 x i8> noundef %arg.coerce)
+// CHECK-LLVM-ZVFBFA: define dso_local riscv_vls_cc(128) void @test_vls_default_abi_vlen_bfloat(<vscale x 4 x bfloat> noundef %arg.coerce)
+void __attribute__((riscv_vls_cc)) test_vls_default_abi_vlen_bfloat(__attribute__((vector_size(16))) __bf16 arg) {}
+
+// CHECK-LLVM: define dso_local riscv_vls_cc(128) void @test_vls_default_abi_vlen_c23_bfloat(<vscale x 8 x i8> noundef %arg.coerce)
+// CHECK-LLVM-ZVFBFA: define dso_local riscv_vls_cc(128) void @test_vls_default_abi_vlen_c23_bfloat(<vscale x 4 x bfloat> noundef %arg.coerce)
+[[riscv::vls_cc]] void test_vls_default_abi_vlen_c23_bfloat(__attribute__((vector_size(16))) __bf16 arg) {}
+
+// CHECK-LLVM: define dso_local riscv_vls_cc(128) void @test_vls_default_abi_vlen_unsupported_feature_zve32x(<vscale x 2 x float> noundef %arg.coerce)
 // CHECK-LLVM-ZVE32X: define dso_local riscv_vls_cc(128) void @test_vls_default_abi_vlen_unsupported_feature_zve32x(<vscale x 8 x i8> noundef %arg.coerce)
 void __attribute__((riscv_vls_cc)) test_vls_default_abi_vlen_unsupported_feature_zve32x(__attribute__((vector_size(16))) float arg) {}
 
+// CHECK-LLVM: define dso_local riscv_vls_cc(128) void @test_vls_default_abi_vlen_c23_unsupported_feature_zve32x(<vscale x 2 x float> noundef %arg.coerce)
 // CHECK-LLVM-ZVE32X: define dso_local riscv_vls_cc(128) void @test_vls_default_abi_vlen_c23_unsupported_feature_zve32x(<vscale x 8 x i8> noundef %arg.coerce)
 [[riscv::vls_cc]] void test_vls_default_abi_vlen_c23_unsupported_feature_zve32x(__attribute__((vector_size(16))) float arg) {}
 
+// CHECK-LLVM: define dso_local riscv_vls_cc(128) void @test_vls_default_abi_vlen_unsupported_feature_no_zve64x(<vscale x 1 x i64> noundef %arg.coerce)
 // CHECK-LLVM-ZVE32X: define dso_local riscv_vls_cc(128) void @test_vls_default_abi_vlen_unsupported_feature_no_zve64x(<vscale x 8 x i8> noundef %arg.coerce)
 void __attribute__((riscv_vls_cc)) test_vls_default_abi_vlen_unsupported_feature_no_zve64x(__attribute__((vector_size(16))) uint64_t arg) {}
 
+// CHECK-LLVM: define dso_local riscv_vls_cc(128) void @test_vls_default_abi_vlen_c23_unsupported_feature_no_zve64x(<vscale x 1 x i64> noundef %arg.coerce)
 // CHECK-LLVM-ZVE32X: define dso_local riscv_vls_cc(128) void @test_vls_default_abi_vlen_c23_unsupported_feature_no_zve64x(<vscale x 8 x i8> noundef %arg.coerce)
 [[riscv::vls_cc]] void test_vls_default_abi_vlen_c23_unsupported_feature_no_zve64x(__attribute__((vector_size(16))) uint64_t arg) {}
 

diff  --git a/clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.cpp b/clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.cpp
index e0562034cd5d6..96a4c9741f738 100644
--- a/clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.cpp
+++ b/clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.cpp
@@ -3,6 +3,8 @@
 // RUN:   -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM %s
 // RUN: %clang_cc1 -std=c++11 -triple riscv64 -target-feature +zve32x \
 // RUN:   -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM-ZVE32X %s
+// RUN: %clang_cc1 -std=c++11 -triple riscv64 -target-feature +experimental-zvfbfa \
+// RUN:   -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM-ZVFBFA %s
 
 #include <riscv_vector.h>
 
@@ -42,9 +44,15 @@ void test_vls_no_cc(__attribute__((vector_size(16))) int arg) {}
 // CHECK-LLVM: define dso_local riscv_vls_cc(128) void @_Z45test_vls_default_abi_vlen_unsupported_featureDv8_DF16_(<vscale x 8 x i8> noundef %arg.coerce)
 [[riscv::vls_cc]] void test_vls_default_abi_vlen_unsupported_feature(__attribute__((vector_size(16))) _Float16 arg) {}
 
+// CHECK-LLVM: define dso_local riscv_vls_cc(128) void @_Z32test_vls_default_abi_vlen_bfloatDv8_DF16b(<vscale x 8 x i8> noundef %arg.coerce)
+// CHECK-LLVM-ZVFBFA: define dso_local riscv_vls_cc(128) void @_Z32test_vls_default_abi_vlen_bfloatDv8_DF16b(<vscale x 4 x bfloat> noundef %arg.coerce)
+[[riscv::vls_cc]] void test_vls_default_abi_vlen_bfloat(__attribute__((vector_size(16))) __bf16 arg) {}
+
+// CHECK-LLVM: define dso_local riscv_vls_cc(128) void @_Z52test_vls_default_abi_vlen_unsupported_feature_zve32xDv4_f(<vscale x 2 x float> noundef %arg.coerce)
 // CHECK-LLVM-ZVE32X: define dso_local riscv_vls_cc(128) void @_Z52test_vls_default_abi_vlen_unsupported_feature_zve32xDv4_f(<vscale x 8 x i8> noundef %arg.coerce)
 [[riscv::vls_cc]] void test_vls_default_abi_vlen_unsupported_feature_zve32x(__attribute__((vector_size(16))) float arg) {}
 
+// CHECK-LLVM: define dso_local riscv_vls_cc(128) void @_Z55test_vls_default_abi_vlen_unsupported_feature_no_zve64xDv2_m(<vscale x 1 x i64> noundef %arg.coerce)
 // CHECK-LLVM-ZVE32X: define dso_local riscv_vls_cc(128) void @_Z55test_vls_default_abi_vlen_unsupported_feature_no_zve64xDv2_m(<vscale x 8 x i8> noundef %arg.coerce)
 [[riscv::vls_cc]] void test_vls_default_abi_vlen_unsupported_feature_no_zve64x(__attribute__((vector_size(16))) uint64_t arg) {}