[clang] [llvm] [AArch64] Add MS atomic and exclusive-access intrinsics (PR #202416)

Eli Friedman via cfe-commits cfe-commits at lists.llvm.org
Tue Jun 9 12:00:38 PDT 2026


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@@ -32,7 +32,140 @@ def int_aarch64_stlxp : Intrinsic<[llvm_i32_ty],
                                   [llvm_i64_ty, llvm_i64_ty, llvm_ptr_ty],
                                   [IntrNoFree, IntrWillReturn]>;
 
-def int_aarch64_clrex : Intrinsic<[]>;
+def int_aarch64_clrex : Intrinsic<[], [llvm_i32_ty]>;
+
+// CAS intrinsics — emit CAS* (no acquire/release) directly, regardless of the
+// LSE target feature. CAS{H,b} comparand/value use i32; CAS{X}uses i64.
+def int_aarch64_cas8  : Intrinsic<[llvm_i32_ty],
+                                  [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
+                                  [IntrNoFree, IntrWillReturn]>;
----------------
efriedma-quic wrote:

I'm not sure IntrWillReturn is correct; these instructions can trap.

More generally, the reason we don't want to do this sort of thing is that all the intrinsics defined this way are possibly-trapping.  Which means we need two versions of every intrinsic that isn't part of the base architecture.

These particular intrinsics are less messy than some of the others; they involve registers which are defined in the base architecture, and they have side-effects anyway.  But I'm not sure we want to go down this path, in general, unless we have a compelling reason.

Maybe worth a Discourse thread to discuss this.

https://github.com/llvm/llvm-project/pull/202416


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