[clang] [compiler-rt] [llvm] [X86] Hygon Processors Initial enablement (PR #187622)
Simon Pilgrim via cfe-commits
cfe-commits at lists.llvm.org
Tue Jun 9 03:07:45 PDT 2026
https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/187622
>From 8f803462d19fc97f4cb552aa6c79899e934b7a57 Mon Sep 17 00:00:00 2001
From: zhangxiaomeng <zhangxiaomeng at hygon.cn>
Date: Thu, 19 Mar 2026 15:49:38 +0800
Subject: [PATCH 01/11] [X86] Hygon Processors Initial enablement
This patch adds initial support for several Hygon architectures.
The Hygon architectures include:
c86-4g-m4
c86-4g-m6
c86-4g-m7
This patch includes:
Added Hygon architectures CPU targets recognition in Clang and LLVM
Added Hygon architectures to target parser and host CPU detection
Updated compiler-rt CPU model detection for Hygon architectures
Added Hygon architectures to various optimizer tests
---
clang/lib/Basic/Targets/X86.cpp | 13 +
clang/test/CodeGen/target-builtin-noerror.c | 3 +
clang/test/Driver/x86-march.c | 12 +
clang/test/Frontend/x86-target-cpu.c | 3 +
clang/test/Misc/target-invalid-cpu-note/x86.c | 12 +
.../Preprocessor/predefined-arch-macros.c | 298 ++++++++++++++++++
compiler-rt/lib/builtins/cpu_model/x86.c | 50 +++
llvm/include/llvm/TargetParser/Host.h | 1 +
.../llvm/TargetParser/X86TargetParser.def | 4 +
.../llvm/TargetParser/X86TargetParser.h | 3 +
llvm/lib/Target/X86/X86.td | 84 +++++
llvm/lib/TargetParser/Host.cpp | 40 +++
llvm/lib/TargetParser/X86TargetParser.cpp | 25 ++
.../CodeGen/X86/bypass-slow-division-64.ll | 3 +
llvm/test/CodeGen/X86/cmp16.ll | 3 +
llvm/test/CodeGen/X86/cpus-hygon.ll | 10 +
llvm/test/CodeGen/X86/rdpru.ll | 3 +
llvm/test/CodeGen/X86/slow-unaligned-mem.ll | 6 +
llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll | 3 +
.../X86/vector-shuffle-fast-per-lane.ll | 3 +
.../CodeGen/X86/x86-64-double-shifts-var.ll | 3 +
llvm/test/MC/X86/x86_long_nop.s | 6 +
22 files changed, 588 insertions(+)
create mode 100644 llvm/test/CodeGen/X86/cpus-hygon.ll
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index cb941c94c84a7..fd30c7f8d61b9 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -729,6 +729,15 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
case CK_Geode:
defineCPUMacros(Builder, "geode");
break;
+ case CK_C86_4G_M4:
+ defineCPUMacros(Builder, "c86-4g-m4");
+ break;
+ case CK_C86_4G_M6:
+ defineCPUMacros(Builder, "c86-4g-m6");
+ break;
+ case CK_C86_4G_M7:
+ defineCPUMacros(Builder, "c86-4g-m7");
+ break;
}
// Target properties.
@@ -1657,6 +1666,10 @@ std::optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
case CK_ZNVER4:
case CK_ZNVER5:
case CK_ZNVER6:
+ // Hygon
+ case CK_C86_4G_M4:
+ case CK_C86_4G_M6:
+ case CK_C86_4G_M7:
// Deprecated
case CK_x86_64:
case CK_x86_64_v2:
diff --git a/clang/test/CodeGen/target-builtin-noerror.c b/clang/test/CodeGen/target-builtin-noerror.c
index a65a07d81b8c0..bb4c65991ab50 100644
--- a/clang/test/CodeGen/target-builtin-noerror.c
+++ b/clang/test/CodeGen/target-builtin-noerror.c
@@ -211,4 +211,7 @@ void verifycpustrings(void) {
(void)__builtin_cpu_is("znver5");
(void)__builtin_cpu_is("znver6");
(void)__builtin_cpu_is("diamondrapids");
+ (void)__builtin_cpu_is("c86-4g-m4");
+ (void)__builtin_cpu_is("c86-4g-m6");
+ (void)__builtin_cpu_is("c86-4g-m7");
}
diff --git a/clang/test/Driver/x86-march.c b/clang/test/Driver/x86-march.c
index 6a3ef5be67d8a..b05e025fca81c 100644
--- a/clang/test/Driver/x86-march.c
+++ b/clang/test/Driver/x86-march.c
@@ -263,6 +263,18 @@
// RUN: | FileCheck %s -check-prefix=znver6
// znver6: "-target-cpu" "znver6"
+// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=c86-4g-m4 2>&1 \
+// RUN: | FileCheck %s -check-prefix=c86-4g-m4
+// c86-4g-m4: "-target-cpu" "c86-4g-m4"
+
+// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=c86-4g-m6 2>&1 \
+// RUN: | FileCheck %s -check-prefix=c86-4g-m6
+// c86-4g-m6: "-target-cpu" "c86-4g-m6"
+
+// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=c86-4g-m7 2>&1 \
+// RUN: | FileCheck %s -check-prefix=c86-4g-m7
+// c86-4g-m7: "-target-cpu" "c86-4g-m7"
+
// RUN: %clang -target x86_64 -c -### %s -march=x86-64 2>&1 | FileCheck %s --check-prefix=x86-64
// x86-64: "-target-cpu" "x86-64"
// RUN: %clang -target x86_64 -c -### %s -march=x86-64-v2 2>&1 | FileCheck %s --check-prefix=x86-64-v2
diff --git a/clang/test/Frontend/x86-target-cpu.c b/clang/test/Frontend/x86-target-cpu.c
index 7dc7f5474687e..281e41c03c4d0 100644
--- a/clang/test/Frontend/x86-target-cpu.c
+++ b/clang/test/Frontend/x86-target-cpu.c
@@ -40,5 +40,8 @@
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver4 -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver5 -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver6 -verify %s
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu c86-4g-m4 -verify %s
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu c86-4g-m6 -verify %s
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu c86-4g-m7 -verify %s
//
// expected-no-diagnostics
diff --git a/clang/test/Misc/target-invalid-cpu-note/x86.c b/clang/test/Misc/target-invalid-cpu-note/x86.c
index 766bd679796f5..921c4b7c5cab0 100644
--- a/clang/test/Misc/target-invalid-cpu-note/x86.c
+++ b/clang/test/Misc/target-invalid-cpu-note/x86.c
@@ -104,6 +104,9 @@
// X86-SAME: {{^}}, znver4
// X86-SAME: {{^}}, znver5
// X86-SAME: {{^}}, znver6
+// X86-SAME: {{^}}, c86-4g-m4
+// X86-SAME: {{^}}, c86-4g-m6
+// X86-SAME: {{^}}, c86-4g-m7
// X86-SAME: {{^}}, x86-64
// X86-SAME: {{^}}, x86-64-v2
// X86-SAME: {{^}}, x86-64-v3
@@ -185,6 +188,9 @@
// X86_64-SAME: {{^}}, znver4
// X86_64-SAME: {{^}}, znver5
// X86_64-SAME: {{^}}, znver6
+// X86_64-SAME: {{^}}, c86-4g-m4
+// X86_64-SAME: {{^}}, c86-4g-m6
+// X86_64-SAME: {{^}}, c86-4g-m7
// X86_64-SAME: {{^}}, x86-64
// X86_64-SAME: {{^}}, x86-64-v2
// X86_64-SAME: {{^}}, x86-64-v3
@@ -293,6 +299,9 @@
// TUNE_X86-SAME: {{^}}, znver4
// TUNE_X86-SAME: {{^}}, znver5
// TUNE_X86-SAME: {{^}}, znver6
+// TUNE_X86-SAME: {{^}}, c86-4g-m4
+// TUNE_X86-SAME: {{^}}, c86-4g-m6
+// TUNE_X86-SAME: {{^}}, c86-4g-m7
// TUNE_X86-SAME: {{^}}, x86-64
// TUNE_X86-SAME: {{^}}, geode
// TUNE_X86-SAME: {{$}}
@@ -399,6 +408,9 @@
// TUNE_X86_64-SAME: {{^}}, znver4
// TUNE_X86_64-SAME: {{^}}, znver5
// TUNE_X86_64-SAME: {{^}}, znver6
+// TUNE_X86_64-SAME: {{^}}, c86-4g-m4
+// TUNE_X86_64-SAME: {{^}}, c86-4g-m6
+// TUNE_X86_64-SAME: {{^}}, c86-4g-m7
// TUNE_X86_64-SAME: {{^}}, x86-64
// TUNE_X86_64-SAME: {{^}}, geode
// TUNE_X86_64-SAME: {{$}}
diff --git a/clang/test/Preprocessor/predefined-arch-macros.c b/clang/test/Preprocessor/predefined-arch-macros.c
index cb2d13d59d8bf..bc950f5ecee9c 100644
--- a/clang/test/Preprocessor/predefined-arch-macros.c
+++ b/clang/test/Preprocessor/predefined-arch-macros.c
@@ -4287,6 +4287,304 @@
// CHECK_ZNVER6_M64: #define __znver6 1
// CHECK_ZNVER6_M64: #define __znver6__ 1
+// RUN: %clang -march=c86-4g-m4 -m32 -E -dM %s -o - 2>&1 \
+// RUN: -target i386-unknown-linux \
+// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_C864GM4_M32
+// CHECK_C864GM4_M32: #define __ADX__ 1
+// CHECK_C864GM4_M32: #define __AES__ 1
+// CHECK_C864GM4_M32: #define __AVX2__ 1
+// CHECK_C864GM4_M32: #define __AVX__ 1
+// CHECK_C864GM4_M32: #define __BMI2__ 1
+// CHECK_C864GM4_M32: #define __BMI__ 1
+// CHECK_C864GM4_M32: #define __CLFLUSHOPT__ 1
+// CHECK_C864GM4_M32: #define __CLZERO__ 1
+// CHECK_C864GM4_M32: #define __CRC32__ 1
+// CHECK_C864GM4_M32: #define __F16C__ 1
+// CHECK_C864GM4_M32: #define __FMA__ 1
+// CHECK_C864GM4_M32: #define __FSGSBASE__ 1
+// CHECK_C864GM4_M32: #define __FXSR__ 1
+// CHECK_C864GM4_M32: #define __LZCNT__ 1
+// CHECK_C864GM4_M32: #define __MMX__ 1
+// CHECK_C864GM4_M32: #define __MOVBE__ 1
+// CHECK_C864GM4_M32: #define __MWAITX__ 1
+// CHECK_C864GM4_M32: #define __PCLMUL__ 1
+// CHECK_C864GM4_M32: #define __POPCNT__ 1
+// CHECK_C864GM4_M32: #define __PRFCHW__ 1
+// CHECK_C864GM4_M32: #define __RDRND__ 1
+// CHECK_C864GM4_M32: #define __RDSEED__ 1
+// CHECK_C864GM4_M32: #define __SHA__ 1
+// CHECK_C864GM4_M32: #define __SSE2_MATH__ 1
+// CHECK_C864GM4_M32: #define __SSE2__ 1
+// CHECK_C864GM4_M32: #define __SSE3__ 1
+// CHECK_C864GM4_M32: #define __SSE4A__ 1
+// CHECK_C864GM4_M32: #define __SSE4_1__ 1
+// CHECK_C864GM4_M32: #define __SSE4_2__ 1
+// CHECK_C864GM4_M32: #define __SSE_MATH__ 1
+// CHECK_C864GM4_M32: #define __SSE__ 1
+// CHECK_C864GM4_M32: #define __SSSE3__ 1
+// CHECK_C864GM4_M32: #define __XSAVEC__ 1
+// CHECK_C864GM4_M32: #define __XSAVEOPT__ 1
+// CHECK_C864GM4_M32: #define __XSAVES__ 1
+// CHECK_C864GM4_M32: #define __XSAVE__ 1
+// CHECK_C864GM4_M32: #define __c86 -4g-m4__ 1
+// CHECK_C864GM4_M32: #define __i386 1
+// CHECK_C864GM4_M32: #define __i386__ 1
+// CHECK_C864GM4_M32: #define __tune_c86 -4g-m4__ 1
+
+// RUN: %clang -march=c86-4g-m4 -m64 -E -dM %s -o - 2>&1 \
+// RUN: -target i386-unknown-linux \
+// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_C864GM4_M64
+// CHECK_C864GM4_M64: #define __ADX__ 1
+// CHECK_C864GM4_M64: #define __AES__ 1
+// CHECK_C864GM4_M64: #define __AVX2__ 1
+// CHECK_C864GM4_M64: #define __AVX__ 1
+// CHECK_C864GM4_M64: #define __BMI2__ 1
+// CHECK_C864GM4_M64: #define __BMI__ 1
+// CHECK_C864GM4_M64: #define __CLFLUSHOPT__ 1
+// CHECK_C864GM4_M64: #define __CLZERO__ 1
+// CHECK_C864GM4_M64: #define __CRC32__ 1
+// CHECK_C864GM4_M64: #define __F16C__ 1
+// CHECK_C864GM4_M64: #define __FMA__ 1
+// CHECK_C864GM4_M64: #define __FSGSBASE__ 1
+// CHECK_C864GM4_M64: #define __FXSR__ 1
+// CHECK_C864GM4_M64: #define __LZCNT__ 1
+// CHECK_C864GM4_M64: #define __MMX__ 1
+// CHECK_C864GM4_M64: #define __MOVBE__ 1
+// CHECK_C864GM4_M64: #define __MWAITX__ 1
+// CHECK_C864GM4_M64: #define __PCLMUL__ 1
+// CHECK_C864GM4_M64: #define __POPCNT__ 1
+// CHECK_C864GM4_M64: #define __PRFCHW__ 1
+// CHECK_C864GM4_M64: #define __RDRND__ 1
+// CHECK_C864GM4_M64: #define __RDSEED__ 1
+// CHECK_C864GM4_M64: #define __SHA__ 1
+// CHECK_C864GM4_M64: #define __SSE2_MATH__ 1
+// CHECK_C864GM4_M64: #define __SSE2__ 1
+// CHECK_C864GM4_M64: #define __SSE3__ 1
+// CHECK_C864GM4_M64: #define __SSE4A__ 1
+// CHECK_C864GM4_M64: #define __SSE4_1__ 1
+// CHECK_C864GM4_M64: #define __SSE4_2__ 1
+// CHECK_C864GM4_M64: #define __SSE_MATH__ 1
+// CHECK_C864GM4_M64: #define __SSE__ 1
+// CHECK_C864GM4_M64: #define __SSSE3__ 1
+// CHECK_C864GM4_M64: #define __XSAVEC__ 1
+// CHECK_C864GM4_M64: #define __XSAVEOPT__ 1
+// CHECK_C864GM4_M64: #define __XSAVES__ 1
+// CHECK_C864GM4_M64: #define __XSAVE__ 1
+// CHECK_C864GM4_M64: #define __c86 -4g-m4__ 1
+// CHECK_C864GM4_M64: #define __tune_c86 -4g-m4__ 1
+// CHECK_C864GM4_M64: #define __x86_64 1
+// CHECK_C864GM4_M64: #define __x86_64__ 1
+
+// RUN: %clang -march=c86-4g-m6 -m32 -E -dM %s -o - 2>&1 \
+// RUN: -target i386-unknown-linux \
+// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_C864GM6_M32
+// CHECK_C864GM6_M32: #define __ADX__ 1
+// CHECK_C864GM6_M32: #define __AES__ 1
+// CHECK_C864GM6_M32: #define __AVX2__ 1
+// CHECK_C864GM6_M32: #define __AVX__ 1
+// CHECK_C864GM6_M32: #define __BMI2__ 1
+// CHECK_C864GM6_M32: #define __BMI__ 1
+// CHECK_C864GM6_M32: #define __CLFLUSHOPT__ 1
+// CHECK_C864GM6_M32: #define __CLZERO__ 1
+// CHECK_C864GM6_M32: #define __CRC32__ 1
+// CHECK_C864GM6_M32: #define __F16C__ 1
+// CHECK_C864GM6_M32: #define __FMA__ 1
+// CHECK_C864GM6_M32: #define __FSGSBASE__ 1
+// CHECK_C864GM6_M32: #define __FXSR__ 1
+// CHECK_C864GM6_M32: #define __LZCNT__ 1
+// CHECK_C864GM6_M32: #define __MMX__ 1
+// CHECK_C864GM6_M32: #define __MOVBE__ 1
+// CHECK_C864GM6_M32: #define __MWAITX__ 1
+// CHECK_C864GM6_M32: #define __PCLMUL__ 1
+// CHECK_C864GM6_M32: #define __POPCNT__ 1
+// CHECK_C864GM6_M32: #define __PRFCHW__ 1
+// CHECK_C864GM6_M32: #define __RDRND__ 1
+// CHECK_C864GM6_M32: #define __RDSEED__ 1
+// CHECK_C864GM6_M32: #define __SHA__ 1
+// CHECK_C864GM6_M32: #define __SSE2_MATH__ 1
+// CHECK_C864GM6_M32: #define __SSE2__ 1
+// CHECK_C864GM6_M32: #define __SSE3__ 1
+// CHECK_C864GM6_M32: #define __SSE4A__ 1
+// CHECK_C864GM6_M32: #define __SSE4_1__ 1
+// CHECK_C864GM6_M32: #define __SSE4_2__ 1
+// CHECK_C864GM6_M32: #define __SSE_MATH__ 1
+// CHECK_C864GM6_M32: #define __SSE__ 1
+// CHECK_C864GM6_M32: #define __SSSE3__ 1
+// CHECK_C864GM6_M32: #define __XSAVEC__ 1
+// CHECK_C864GM6_M32: #define __XSAVEOPT__ 1
+// CHECK_C864GM6_M32: #define __XSAVES__ 1
+// CHECK_C864GM6_M32: #define __XSAVE__ 1
+// CHECK_C864GM6_M32: #define __c86 -4g-m6__ 1
+// CHECK_C864GM6_M32: #define __i386 1
+// CHECK_C864GM6_M32: #define __i386__ 1
+// CHECK_C864GM6_M32: #define __tune_c86 -4g-m6__ 1
+
+// RUN: %clang -march=c86-4g-m6 -m64 -E -dM %s -o - 2>&1 \
+// RUN: -target i386-unknown-linux \
+// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_C864GM6_M64
+// CHECK_C864GM6_M64: #define __ADX__ 1
+// CHECK_C864GM6_M64: #define __AES__ 1
+// CHECK_C864GM6_M64: #define __AVX2__ 1
+// CHECK_C864GM6_M64: #define __AVX__ 1
+// CHECK_C864GM6_M64: #define __BMI2__ 1
+// CHECK_C864GM6_M64: #define __BMI__ 1
+// CHECK_C864GM6_M64: #define __CLFLUSHOPT__ 1
+// CHECK_C864GM6_M64: #define __CLZERO__ 1
+// CHECK_C864GM6_M64: #define __CRC32__ 1
+// CHECK_C864GM6_M64: #define __F16C__ 1
+// CHECK_C864GM6_M64: #define __FMA__ 1
+// CHECK_C864GM6_M64: #define __FSGSBASE__ 1
+// CHECK_C864GM6_M64: #define __FXSR__ 1
+// CHECK_C864GM6_M64: #define __LZCNT__ 1
+// CHECK_C864GM6_M64: #define __MMX__ 1
+// CHECK_C864GM6_M64: #define __MOVBE__ 1
+// CHECK_C864GM6_M64: #define __MWAITX__ 1
+// CHECK_C864GM6_M64: #define __PCLMUL__ 1
+// CHECK_C864GM6_M64: #define __POPCNT__ 1
+// CHECK_C864GM6_M64: #define __PRFCHW__ 1
+// CHECK_C864GM6_M64: #define __RDRND__ 1
+// CHECK_C864GM6_M64: #define __RDSEED__ 1
+// CHECK_C864GM6_M64: #define __SHA__ 1
+// CHECK_C864GM6_M64: #define __SSE2_MATH__ 1
+// CHECK_C864GM6_M64: #define __SSE2__ 1
+// CHECK_C864GM6_M64: #define __SSE3__ 1
+// CHECK_C864GM6_M64: #define __SSE4A__ 1
+// CHECK_C864GM6_M64: #define __SSE4_1__ 1
+// CHECK_C864GM6_M64: #define __SSE4_2__ 1
+// CHECK_C864GM6_M64: #define __SSE_MATH__ 1
+// CHECK_C864GM6_M64: #define __SSE__ 1
+// CHECK_C864GM6_M64: #define __SSSE3__ 1
+// CHECK_C864GM6_M64: #define __XSAVEC__ 1
+// CHECK_C864GM6_M64: #define __XSAVEOPT__ 1
+// CHECK_C864GM6_M64: #define __XSAVES__ 1
+// CHECK_C864GM6_M64: #define __XSAVE__ 1
+// CHECK_C864GM6_M64: #define __c86 -4g-m6__ 1
+// CHECK_C864GM6_M64: #define __tune_c86 -4g-m6__ 1
+// CHECK_C864GM6_M64: #define __x86_64 1
+// CHECK_C864GM6_M64: #define __x86_64__ 1
+
+// RUN: %clang -march=c86-4g-m7 -m32 -E -dM %s -o - 2>&1 \
+// RUN: -target i386-unknown-linux \
+// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_C864GM7_M32
+// CHECK_C864GM7_M32: #define __ADX__ 1
+// CHECK_C864GM7_M32: #define __AES__ 1
+// CHECK_C864GM7_M32: #define __AVX2__ 1
+// CHECK_C864GM7_M32: #define __AVX512BF16__ 1
+// CHECK_C864GM7_M32: #define __AVX512BITALG__ 1
+// CHECK_C864GM7_M32: #define __AVX512BW__ 1
+// CHECK_C864GM7_M32: #define __AVX512CD__ 1
+// CHECK_C864GM7_M32: #define __AVX512DQ__ 1
+// CHECK_C864GM7_M32: #define __AVX512F__ 1
+// CHECK_C864GM7_M32: #define __AVX512IFMA__ 1
+// CHECK_C864GM7_M32: #define __AVX512VBMI2__ 1
+// CHECK_C864GM7_M32: #define __AVX512VBMI__ 1
+// CHECK_C864GM7_M32: #define __AVX512VL__ 1
+// CHECK_C864GM7_M32: #define __AVX512VNNI__ 1
+// CHECK_C864GM7_M32: #define __AVX512VPOPCNTDQ__ 1
+// CHECK_C864GM7_M32: #define __AVX__ 1
+// CHECK_C864GM7_M32: #define __BMI2__ 1
+// CHECK_C864GM7_M32: #define __BMI__ 1
+// CHECK_C864GM7_M32: #define __CLFLUSHOPT__ 1
+// CHECK_C864GM7_M32: #define __CLWB__ 1
+// CHECK_C864GM7_M32: #define __CLZERO__ 1
+// CHECK_C864GM7_M32: #define __CRC32__ 1
+// CHECK_C864GM7_M32: #define __F16C__ 1
+// CHECK_C864GM7_M32: #define __FMA__ 1
+// CHECK_C864GM7_M32: #define __FSGSBASE__ 1
+// CHECK_C864GM7_M32: #define __FXSR__ 1
+// CHECK_C864GM7_M32: #define __GFNI__ 1
+// CHECK_C864GM7_M32: #define __LZCNT__ 1
+// CHECK_C864GM7_M32: #define __MMX__ 1
+// CHECK_C864GM7_M32: #define __MOVBE__ 1
+// CHECK_C864GM7_M32: #define __MWAITX__ 1
+// CHECK_C864GM7_M32: #define __PCLMUL__ 1
+// CHECK_C864GM7_M32: #define __POPCNT__ 1
+// CHECK_C864GM7_M32: #define __PRFCHW__ 1
+// CHECK_C864GM7_M32: #define __RDRND__ 1
+// CHECK_C864GM7_M32: #define __RDSEED__ 1
+// CHECK_C864GM7_M32: #define __SHA__ 1
+// CHECK_C864GM7_M32: #define __SSE2_MATH__ 1
+// CHECK_C864GM7_M32: #define __SSE2__ 1
+// CHECK_C864GM7_M32: #define __SSE3__ 1
+// CHECK_C864GM7_M32: #define __SSE4A__ 1
+// CHECK_C864GM7_M32: #define __SSE4_1__ 1
+// CHECK_C864GM7_M32: #define __SSE4_2__ 1
+// CHECK_C864GM7_M32: #define __SSE_MATH__ 1
+// CHECK_C864GM7_M32: #define __SSE__ 1
+// CHECK_C864GM7_M32: #define __SSSE3__ 1
+// CHECK_C864GM7_M32: #define __VAES__ 1
+// CHECK_C864GM7_M32: #define __VPCLMULQDQ__ 1
+// CHECK_C864GM7_M32: #define __WBNOINVD__ 1
+// CHECK_C864GM7_M32: #define __XSAVEC__ 1
+// CHECK_C864GM7_M32: #define __XSAVEOPT__ 1
+// CHECK_C864GM7_M32: #define __XSAVES__ 1
+// CHECK_C864GM7_M32: #define __XSAVE__ 1
+// CHECK_C864GM7_M32: #define __c86 -4g-m7__ 1
+// CHECK_C864GM7_M32: #define __i386 1
+// CHECK_C864GM7_M32: #define __i386__ 1
+// CHECK_C864GM7_M32: #define __tune_c86 -4g-m7__ 1
+
+// RUN: %clang -march=c86-4g-m7 -m64 -E -dM %s -o - 2>&1 \
+// RUN: -target i386-unknown-linux \
+// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_C864GM7_M64
+// CHECK_C864GM7_M64: #define __ADX__ 1
+// CHECK_C864GM7_M64: #define __AES__ 1
+// CHECK_C864GM7_M64: #define __AVX2__ 1
+// CHECK_C864GM7_M64: #define __AVX512BF16__ 1
+// CHECK_C864GM7_M64: #define __AVX512BITALG__ 1
+// CHECK_C864GM7_M64: #define __AVX512BW__ 1
+// CHECK_C864GM7_M64: #define __AVX512CD__ 1
+// CHECK_C864GM7_M64: #define __AVX512DQ__ 1
+// CHECK_C864GM7_M64: #define __AVX512F__ 1
+// CHECK_C864GM7_M64: #define __AVX512IFMA__ 1
+// CHECK_C864GM7_M64: #define __AVX512VBMI2__ 1
+// CHECK_C864GM7_M64: #define __AVX512VBMI__ 1
+// CHECK_C864GM7_M64: #define __AVX512VL__ 1
+// CHECK_C864GM7_M64: #define __AVX512VNNI__ 1
+// CHECK_C864GM7_M64: #define __AVX512VPOPCNTDQ__ 1
+// CHECK_C864GM7_M64: #define __AVX__ 1
+// CHECK_C864GM7_M64: #define __BMI2__ 1
+// CHECK_C864GM7_M64: #define __BMI__ 1
+// CHECK_C864GM7_M64: #define __CLFLUSHOPT__ 1
+// CHECK_C864GM7_M64: #define __CLWB__ 1
+// CHECK_C864GM7_M64: #define __CLZERO__ 1
+// CHECK_C864GM7_M64: #define __CRC32__ 1
+// CHECK_C864GM7_M64: #define __F16C__ 1
+// CHECK_C864GM7_M64: #define __FMA__ 1
+// CHECK_C864GM7_M64: #define __FSGSBASE__ 1
+// CHECK_C864GM7_M64: #define __FXSR__ 1
+// CHECK_C864GM7_M64: #define __GFNI__ 1
+// CHECK_C864GM7_M64: #define __LZCNT__ 1
+// CHECK_C864GM7_M64: #define __MMX__ 1
+// CHECK_C864GM7_M64: #define __MOVBE__ 1
+// CHECK_C864GM7_M64: #define __MWAITX__ 1
+// CHECK_C864GM7_M64: #define __PCLMUL__ 1
+// CHECK_C864GM7_M64: #define __POPCNT__ 1
+// CHECK_C864GM7_M64: #define __PRFCHW__ 1
+// CHECK_C864GM7_M64: #define __RDRND__ 1
+// CHECK_C864GM7_M64: #define __RDSEED__ 1
+// CHECK_C864GM7_M64: #define __SHA__ 1
+// CHECK_C864GM7_M64: #define __SSE2_MATH__ 1
+// CHECK_C864GM7_M64: #define __SSE2__ 1
+// CHECK_C864GM7_M64: #define __SSE3__ 1
+// CHECK_C864GM7_M64: #define __SSE4A__ 1
+// CHECK_C864GM7_M64: #define __SSE4_1__ 1
+// CHECK_C864GM7_M64: #define __SSE4_2__ 1
+// CHECK_C864GM7_M64: #define __SSE_MATH__ 1
+// CHECK_C864GM7_M64: #define __SSE__ 1
+// CHECK_C864GM7_M64: #define __SSSE3__ 1
+// CHECK_C864GM7_M64: #define __VAES__ 1
+// CHECK_C864GM7_M64: #define __VPCLMULQDQ__ 1
+// CHECK_C864GM7_M64: #define __WBNOINVD__ 1
+// CHECK_C864GM7_M64: #define __XSAVEC__ 1
+// CHECK_C864GM7_M64: #define __XSAVEOPT__ 1
+// CHECK_C864GM7_M64: #define __XSAVES__ 1
+// CHECK_C864GM7_M64: #define __XSAVE__ 1
+// CHECK_C864GM7_M64: #define __c86 -4g-m7__ 1
+// CHECK_C864GM7_M64: #define __tune_c86 -4g-m7__ 1
+// CHECK_C864GM7_M64: #define __x86_64 1
+// CHECK_C864GM7_M64: #define __x86_64__ 1
+
// End X86/GCC/Linux tests ------------------
diff --git a/compiler-rt/lib/builtins/cpu_model/x86.c b/compiler-rt/lib/builtins/cpu_model/x86.c
index a71078e9064d5..44e0560391966 100644
--- a/compiler-rt/lib/builtins/cpu_model/x86.c
+++ b/compiler-rt/lib/builtins/cpu_model/x86.c
@@ -36,11 +36,13 @@
enum VendorSignatures {
SIG_INTEL = 0x756e6547, // Genu
SIG_AMD = 0x68747541, // Auth
+ SIG_HYGON = 0x6f677948, // Hygo
};
enum ProcessorVendors {
VENDOR_INTEL = 1,
VENDOR_AMD,
+ VENDOR_HYGON,
VENDOR_OTHER,
VENDOR_MAX
};
@@ -66,6 +68,7 @@ enum ProcessorTypes {
INTEL_GRANDRIDGE,
INTEL_CLEARWATERFOREST,
AMDFAM1AH,
+ HYGONFAM18H,
CPU_TYPE_MAX
};
@@ -108,6 +111,9 @@ enum ProcessorSubtypes {
AMDFAM1AH_ZNVER6,
INTEL_COREI7_DIAMONDRAPIDS,
INTEL_COREI7_NOVALAKE,
+ HYGONFAM18H_C86_4G_M4,
+ HYGONFAM18H_C86_4G_M6,
+ HYGONFAM18H_C86_4G_M7,
CPU_SUBTYPE_MAX
};
@@ -872,6 +878,47 @@ getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model,
return CPU;
}
+static const char *
+getHygonProcessorTypeAndSubtype(unsigned Family, unsigned Model,
+ const unsigned *Features,
+ struct __processor_model *CpuModel) {
+ const char *CPU = 0;
+
+ enum ProcessorTypes Type = CPU_TYPE_MAX;
+ enum ProcessorSubtypes Subtype = CPU_SUBTYPE_MAX;
+
+ switch (Family) {
+ case 24:
+ switch (Model) {
+ case 4:
+ CPU = "c86-4g-m4";
+ Type = HYGONFAM18H;
+ Subtype = HYGONFAM18H_C86_4G_M4;
+ break; // c86-4g-m4
+ case 6:
+ CPU = "c86-4g-m6";
+ Type = HYGONFAM18H;
+ Subtype = HYGONFAM18H_C86_4G_M6;
+ break; // c86-4g-m6
+ case 7:
+ CPU = "c86-4g-m7";
+ Type = HYGONFAM18H;
+ Subtype = HYGONFAM18H_C86_4G_M7;
+ break; // c86-4g-m7
+ }
+ break; // Hygon Family 18H
+ default:
+ break; // Unknown Hygon CPU.
+ }
+
+ if (Type != CPU_TYPE_MAX)
+ CpuModel->__cpu_type = Type;
+ if (Subtype != CPU_SUBTYPE_MAX)
+ CpuModel->__cpu_subtype = Subtype;
+
+ return CPU;
+}
+
#undef testFeature
static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
@@ -1235,6 +1282,9 @@ int CONSTRUCTOR_ATTRIBUTE __cpu_indicator_init(void) {
// Get CPU type.
getAMDProcessorTypeAndSubtype(Family, Model, &Features[0], &__cpu_model);
__cpu_model.__cpu_vendor = VENDOR_AMD;
+ } else if (Vendor == SIG_HYGON) {
+ getHygonProcessorTypeAndSubtype(Family, Model, &Features[0], &__cpu_model);
+ __cpu_model.__cpu_vendor = VENDOR_HYGON;
} else
__cpu_model.__cpu_vendor = VENDOR_OTHER;
diff --git a/llvm/include/llvm/TargetParser/Host.h b/llvm/include/llvm/TargetParser/Host.h
index b44b9b9a4d069..27749eef9cd41 100644
--- a/llvm/include/llvm/TargetParser/Host.h
+++ b/llvm/include/llvm/TargetParser/Host.h
@@ -77,6 +77,7 @@ enum class VendorSignatures {
UNKNOWN,
GENUINE_INTEL,
AUTHENTIC_AMD,
+ HYGON_GENUINE,
};
/// Returns the host CPU's vendor.
diff --git a/llvm/include/llvm/TargetParser/X86TargetParser.def b/llvm/include/llvm/TargetParser/X86TargetParser.def
index db03fc855df5a..0194941bb70e0 100644
--- a/llvm/include/llvm/TargetParser/X86TargetParser.def
+++ b/llvm/include/llvm/TargetParser/X86TargetParser.def
@@ -50,6 +50,7 @@ X86_CPU_TYPE(INTEL_SIERRAFOREST, "sierraforest")
X86_CPU_TYPE(INTEL_GRANDRIDGE, "grandridge")
X86_CPU_TYPE(INTEL_CLEARWATERFOREST, "clearwaterforest")
X86_CPU_TYPE(AMDFAM1AH, "amdfam1ah")
+X86_CPU_TYPE(HYGONFAM18H, "hygonfam18h")
// Alternate names supported by __builtin_cpu_is and target multiversioning.
X86_CPU_TYPE_ALIAS(INTEL_BONNELL, "atom")
@@ -110,6 +111,9 @@ X86_CPU_SUBTYPE(AMDFAM1AH_ZNVER5, "znver5")
X86_CPU_SUBTYPE(AMDFAM1AH_ZNVER6, "znver6")
X86_CPU_SUBTYPE(INTEL_COREI7_DIAMONDRAPIDS, "diamondrapids")
X86_CPU_SUBTYPE(INTEL_COREI7_NOVALAKE, "novalake")
+X86_CPU_SUBTYPE(HYGONFAM18H_C86_4G_M4, "c86-4g-m4")
+X86_CPU_SUBTYPE(HYGONFAM18H_C86_4G_M6, "c86-4g-m6")
+X86_CPU_SUBTYPE(HYGONFAM18H_C86_4G_M7, "c86-4g-m7")
// Alternate names supported by __builtin_cpu_is and target multiversioning.
X86_CPU_SUBTYPE_ALIAS(INTEL_COREI7_ALDERLAKE, "raptorlake")
diff --git a/llvm/include/llvm/TargetParser/X86TargetParser.h b/llvm/include/llvm/TargetParser/X86TargetParser.h
index 31d13ce29f7fc..85b10d500f0a4 100644
--- a/llvm/include/llvm/TargetParser/X86TargetParser.h
+++ b/llvm/include/llvm/TargetParser/X86TargetParser.h
@@ -147,6 +147,9 @@ enum CPUKind {
CK_ZNVER4,
CK_ZNVER5,
CK_ZNVER6,
+ CK_C86_4G_M4,
+ CK_C86_4G_M6,
+ CK_C86_4G_M7,
CK_x86_64,
CK_x86_64_v2,
CK_x86_64_v3,
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index c42d3453e0729..0080732ec198a 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -1661,6 +1661,81 @@ def ProcessorFeatures {
];
list<SubtargetFeature> ZN6Features =
!listconcat(ZN5Features, ZN6AdditionalFeatures);
+
+ list<SubtargetFeature> C864GM4Features = [FeatureADX,
+ FeatureAES,
+ FeatureAVX2,
+ FeatureBMI,
+ FeatureBMI2,
+ FeatureCLFLUSHOPT,
+ FeatureCLZERO,
+ FeatureCMOV,
+ FeatureCRC32,
+ FeatureCX16,
+ FeatureF16C,
+ FeatureFMA,
+ FeatureFSGSBase,
+ FeatureFXSR,
+ FeatureLAHFSAHF64,
+ FeatureLZCNT,
+ FeatureMMX,
+ FeatureMOVBE,
+ FeatureMWAITX,
+ FeatureNOPL,
+ FeaturePCLMUL,
+ FeaturePOPCNT,
+ FeaturePRFCHW,
+ FeatureRDRAND,
+ FeatureRDSEED,
+ FeatureSHA,
+ FeatureSSE4A,
+ FeatureX86_64,
+ FeatureX87,
+ FeatureXSAVE,
+ FeatureXSAVEC,
+ FeatureXSAVEOPT,
+ FeatureXSAVES];
+ list<SubtargetFeature> C864GM4Tuning = [TuningFastLZCNT,
+ TuningFastBEXTR,
+ TuningFast15ByteNOP,
+ TuningFastScalarFSQRT,
+ TuningFastVectorFSQRT,
+ TuningFastScalarShiftMasks,
+ TuningFastVariablePerLaneShuffle,
+ TuningFastMOVBE,
+ TuningFastImm16,
+ TuningSlowDivide64,
+ TuningSlowSHLD,
+ TuningSBBDepBreaking,
+ TuningInsertVZEROUPPER,
+ TuningAllowLight256Bit];
+
+ list<SubtargetFeature> C864GM6Features = C864GM4Features;
+ list<SubtargetFeature> C864GM6Tuning = C864GM4Tuning;
+
+ list<SubtargetFeature> C864GM7AdditionalFeatures = [FeatureAVX512,
+ FeatureBF16,
+ FeatureBITALG,
+ FeatureBWI,
+ FeatureCDI,
+ FeatureCLWB,
+ FeatureDQI,
+ FeatureGFNI,
+ FeatureIFMA,
+ FeatureVAES,
+ FeatureVBMI,
+ FeatureVBMI2,
+ FeatureVLX,
+ FeatureVNNI,
+ FeatureVPCLMULQDQ,
+ FeatureVPOPCNTDQ,
+ FeatureWBNOINVD];
+ list<SubtargetFeature> C864GM7Features =
+ !listconcat(C864GM4Features, C864GM7AdditionalFeatures);
+
+ list<SubtargetFeature> C864GM7AdditionalTuning = [TuningBranchFusion];
+ list<SubtargetFeature> C864GM7Tuning =
+ !listconcat(C864GM4Tuning, C864GM7AdditionalTuning);
}
//===----------------------------------------------------------------------===//
@@ -2026,6 +2101,15 @@ def : ProcModel<"znver5", Znver4Model, ProcessorFeatures.ZN5Features,
def : ProcModel<"znver6", Znver4Model, ProcessorFeatures.ZN6Features,
ProcessorFeatures.ZN6Tuning>;
+// Hygon CPUs.
+
+def : Proc<"c86-4g-m4", ProcessorFeatures.C864GM4Features,
+ ProcessorFeatures.C864GM4Tuning>;
+def : Proc<"c86-4g-m6", ProcessorFeatures.C864GM6Features,
+ ProcessorFeatures.C864GM6Tuning>;
+def : Proc<"c86-4g-m7", ProcessorFeatures.C864GM7Features,
+ ProcessorFeatures.C864GM7Tuning>;
+
def : Proc<"geode", [FeatureX87, FeatureCX8, FeatureMMX, FeaturePRFCHW],
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp
index dfe97f178bd46..ef164bed8c5af 100644
--- a/llvm/lib/TargetParser/Host.cpp
+++ b/llvm/lib/TargetParser/Host.cpp
@@ -682,6 +682,10 @@ VendorSignatures getVendorSignature(unsigned *MaxLeaf) {
if (EBX == 0x68747541 && EDX == 0x69746e65 && ECX == 0x444d4163)
return VendorSignatures::AUTHENTIC_AMD;
+ // "Hygo nGen uien"
+ if (EBX == 0x6f677948 && EDX == 0x6e65476e && ECX == 0x656e6975)
+ return VendorSignatures::HYGON_GENUINE;
+
return VendorSignatures::UNKNOWN;
}
@@ -1355,6 +1359,39 @@ static const char *getAMDProcessorTypeAndSubtype(unsigned Family,
return CPU;
}
+static StringRef
+getHygonProcessorTypeAndSubtype(unsigned Family, unsigned Model,
+ const unsigned *Features,
+ unsigned *Type, unsigned *Subtype) {
+ StringRef CPU;
+
+ switch (Family) {
+ case 24:
+ switch (Model) {
+ case 4:
+ CPU = "c86-4g-m4";
+ *Type = X86::HYGONFAM18H;
+ *Subtype = X86::HYGONFAM18H_C86_4G_M4;
+ break; // c86-4g-m4
+ case 6:
+ CPU = "c86-4g-m6";
+ *Type = X86::HYGONFAM18H;
+ *Subtype = X86::HYGONFAM18H_C86_4G_M6;
+ break; // c86-4g-m6
+ case 7:
+ CPU = "c86-4g-m7";
+ *Type = X86::HYGONFAM18H;
+ *Subtype = X86::HYGONFAM18H_C86_4G_M7;
+ break; // c86-4g-m7
+ }
+ break; // Hygon Family 18H
+ default:
+ break; // Unknown Hygon CPU.
+ }
+
+ return CPU;
+}
+
#undef testFeature
static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
@@ -1517,6 +1554,9 @@ StringRef sys::getHostCPUName() {
} else if (Vendor == VendorSignatures::AUTHENTIC_AMD) {
CPU = getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type,
&Subtype);
+ } else if (Vendor == VendorSignatures::HYGON_GENUINE) {
+ CPU = getHygonProcessorTypeAndSubtype(Family, Model, Features, &Type,
+ &Subtype);
}
if (!CPU.empty())
diff --git a/llvm/lib/TargetParser/X86TargetParser.cpp b/llvm/lib/TargetParser/X86TargetParser.cpp
index b3859eb4ff2fd..f2e18b8b8d967 100644
--- a/llvm/lib/TargetParser/X86TargetParser.cpp
+++ b/llvm/lib/TargetParser/X86TargetParser.cpp
@@ -259,6 +259,27 @@ static constexpr FeatureBitset FeaturesZNVER6 =
FeaturesZNVER5 | FeatureAVXVNNIINT8 | FeatureAVX512FP16 | FeatureAVXIFMA |
FeatureAVXNECONVERT;
+// Hygon architecture processors.
+constexpr FeatureBitset FeaturesC86_4G_M4 =
+ FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 |
+ FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO |
+ FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT |
+ FeatureF16C | FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT |
+ FeatureMMX | FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT |
+ FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA |
+ FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 |
+ FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC |
+ FeatureXSAVEOPT | FeatureXSAVES;
+
+static constexpr FeatureBitset FeaturesC86_4G_M6 = FeaturesC86_4G_M4;
+
+static constexpr FeatureBitset FeaturesC86_4G_M7 = FeaturesC86_4G_M4 |
+ FeatureAVX512BF16 | FeatureAVX512BITALG | FeatureAVX512BW | FeatureAVX512CD |
+ FeatureAVX512DQ | FeatureAVX512F | FeatureAVX512IFMA | FeatureAVX512VBMI |
+ FeatureAVX512VBMI2 | FeatureAVX512VL | FeatureAVX512VNNI |
+ FeatureAVX512VPOPCNTDQ | FeatureCLWB | FeatureCMOV | FeatureGFNI |
+ FeatureVAES | FeatureVPCLMULQDQ | FeatureWBNOINVD;
+
// D151696 tranplanted Mangling and OnlyForCPUDispatchSpecific from
// X86TargetParser.def to here. They are assigned by following ways:
// 1. Copy the mangling from the original CPU_SPEICIFC MACROs. If no, assign
@@ -445,6 +466,10 @@ constexpr ProcInfo Processors[] = {
{ {"znver4"}, CK_ZNVER4, FEATURE_AVX512VBMI2, FeaturesZNVER4, '\0', false },
{ {"znver5"}, CK_ZNVER5, FEATURE_AVX512VP2INTERSECT, FeaturesZNVER5, '\0', false },
{ {"znver6"}, CK_ZNVER6, FEATURE_AVX512FP16, FeaturesZNVER6, '\0', false },
+ // Hygon precessors.
+ { {"c86-4g-m4"}, CK_C86_4G_M4, FEATURE_AVX2, FeaturesC86_4G_M4 , '\0', false },
+ { {"c86-4g-m6"}, CK_C86_4G_M6, FEATURE_AVX512VBMI2, FeaturesC86_4G_M6 , '\0', false },
+ { {"c86-4g-m7"}, CK_C86_4G_M7, FEATURE_AVX512VBMI2, FeaturesC86_4G_M7 , '\0', false },
// Generic 64-bit processor.
{ {"x86-64"}, CK_x86_64, FEATURE_SSE2 , FeaturesX86_64, '\0', false },
{ {"x86-64-v2"}, CK_x86_64_v2, FEATURE_SSE4_2 , FeaturesX86_64_V2, '\0', false },
diff --git a/llvm/test/CodeGen/X86/bypass-slow-division-64.ll b/llvm/test/CodeGen/X86/bypass-slow-division-64.ll
index 821b7b8e4144f..f60d7f011c7d5 100644
--- a/llvm/test/CodeGen/X86/bypass-slow-division-64.ll
+++ b/llvm/test/CodeGen/X86/bypass-slow-division-64.ll
@@ -25,6 +25,9 @@
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver5 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver6 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m4 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m6 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m7 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
; Additional tests for 64-bit divide bypass
diff --git a/llvm/test/CodeGen/X86/cmp16.ll b/llvm/test/CodeGen/X86/cmp16.ll
index ff6ee68074088..8d441424dabec 100644
--- a/llvm/test/CodeGen/X86/cmp16.ll
+++ b/llvm/test/CodeGen/X86/cmp16.ll
@@ -15,6 +15,9 @@
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 | FileCheck %s --check-prefixes=X64,X64-FAST
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver5 | FileCheck %s --check-prefixes=X64,X64-FAST
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver6 | FileCheck %s --check-prefixes=X64,X64-FAST
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m4 | FileCheck %s --check-prefixes=X64,X64-FAST
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m6 | FileCheck %s --check-prefixes=X64,X64-FAST
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m7 | FileCheck %s --check-prefixes=X64,X64-FAST
define i1 @cmp16_reg_eq_reg(i16 %a0, i16 %a1) {
; X86-GENERIC-LABEL: cmp16_reg_eq_reg:
diff --git a/llvm/test/CodeGen/X86/cpus-hygon.ll b/llvm/test/CodeGen/X86/cpus-hygon.ll
new file mode 100644
index 0000000000000..94895e32c4d72
--- /dev/null
+++ b/llvm/test/CodeGen/X86/cpus-hygon.ll
@@ -0,0 +1,10 @@
+; Test that the CPU names work.
+; CHECK-NO-ERROR-NOT: not a recognized processor for this target
+
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m6 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+
+define void @foo() {
+ ret void
+}
diff --git a/llvm/test/CodeGen/X86/rdpru.ll b/llvm/test/CodeGen/X86/rdpru.ll
index 067ae31142c39..b811bba23c329 100644
--- a/llvm/test/CodeGen/X86/rdpru.ll
+++ b/llvm/test/CodeGen/X86/rdpru.ll
@@ -8,6 +8,9 @@
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 -fast-isel | FileCheck %s --check-prefix=X64
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver5 -fast-isel | FileCheck %s --check-prefix=X64
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver6 -fast-isel | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m4 -fast-isel | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m6 -fast-isel | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m7 -fast-isel | FileCheck %s --check-prefix=X64
define void @rdpru_asm() {
; X86-LABEL: rdpru_asm:
diff --git a/llvm/test/CodeGen/X86/slow-unaligned-mem.ll b/llvm/test/CodeGen/X86/slow-unaligned-mem.ll
index a215b60055dd5..ec2a61c548fd1 100644
--- a/llvm/test/CodeGen/X86/slow-unaligned-mem.ll
+++ b/llvm/test/CodeGen/X86/slow-unaligned-mem.ll
@@ -53,6 +53,12 @@
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver5 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX512
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver6 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX512
+; Hygon chips with fast unaligned memory accesses
+
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=c86-4g-m4 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX256
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=c86-4g-m6 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX256
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=c86-4g-m7 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX512
+
; Other chips with slow unaligned memory accesses
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=c3-2 2>&1 | FileCheck %s --check-prefixes=SLOW
diff --git a/llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll b/llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll
index 416ff1d41af72..ab527e3a0bc63 100644
--- a/llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll
+++ b/llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll
@@ -8,6 +8,9 @@
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 | FileCheck %s --check-prefixes=FAST-SCALAR,FAST-VECTOR
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver5 | FileCheck %s --check-prefixes=FAST-SCALAR,FAST-VECTOR
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver6 | FileCheck %s --check-prefixes=FAST-SCALAR,FAST-VECTOR
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m4 | FileCheck %s --check-prefixes=FAST-SCALAR,FAST-VECTOR
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m6 | FileCheck %s --check-prefixes=FAST-SCALAR,FAST-VECTOR
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m7 | FileCheck %s --check-prefixes=FAST-SCALAR,FAST-VECTOR
; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s --check-prefixes=X86-64
define float @f32_no_daz(float %f) #0 {
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-fast-per-lane.ll b/llvm/test/CodeGen/X86/vector-shuffle-fast-per-lane.ll
index 5bf936c6e5cec..eb0751d01182a 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-fast-per-lane.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-fast-per-lane.ll
@@ -10,6 +10,9 @@
; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=znver4 | FileCheck %s --check-prefixes=FAST
; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=znver5 | FileCheck %s --check-prefixes=FAST
; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=znver6 | FileCheck %s --check-prefixes=FAST
+; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m4 | FileCheck %s --check-prefixes=FAST
+; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m6 | FileCheck %s --check-prefixes=FAST
+; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 | FileCheck %s --check-prefixes=FAST
; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=haswell | FileCheck %s --check-prefixes=FAST
; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=skx | FileCheck %s --check-prefixes=FAST
diff --git a/llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll b/llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll
index bb1a4e5fcb75b..1d3feb0b7802d 100644
--- a/llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll
+++ b/llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll
@@ -19,6 +19,9 @@
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 | FileCheck %s --check-prefixes=BMI2-FAST
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver5 | FileCheck %s --check-prefixes=BMI2-FAST
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver6 | FileCheck %s --check-prefixes=BMI2-FAST
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m4 | FileCheck %s --check-prefixes=BMI2-SLOW
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m6 | FileCheck %s --check-prefixes=BMI2-SLOW
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m7 | FileCheck %s --check-prefixes=BMI2-SLOW
; Verify that for the X86_64 processors that are known to have poor latency
; double precision shift instructions we do not generate 'shld' or 'shrd'
diff --git a/llvm/test/MC/X86/x86_long_nop.s b/llvm/test/MC/X86/x86_long_nop.s
index 2c5fe3acde26c..9a1826c8748ab 100644
--- a/llvm/test/MC/X86/x86_long_nop.s
+++ b/llvm/test/MC/X86/x86_long_nop.s
@@ -23,6 +23,12 @@
# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=znver5 | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu -mcpu=znver6 %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=znver6 | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu -mcpu=c86-4g-m4 %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=c86-4g-m4 | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu -mcpu=c86-4g-m6 %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=c86-4g-m6 | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu -mcpu=c86-4g-m7 %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=c86-4g-m7 | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=nehalem %s | llvm-objdump -d --no-show-raw-insn - | FileCheck --check-prefix=LNOP10 %s
# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=westmere %s | llvm-objdump -d --no-show-raw-insn - | FileCheck --check-prefix=LNOP10 %s
# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=sandybridge %s | llvm-objdump -d --no-show-raw-insn - | FileCheck --check-prefix=LNOP15 %s
>From 29588a49746a8e226ee8cd1e377750b3f258fd32 Mon Sep 17 00:00:00 2001
From: Xiaomeng Zhang <zhangxiaomeng at hygon.cn>
Date: Fri, 20 Mar 2026 14:21:04 +0800
Subject: [PATCH 02/11] Update Host.cpp
---
llvm/lib/TargetParser/Host.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp
index ef164bed8c5af..2124b0e3783ac 100644
--- a/llvm/lib/TargetParser/Host.cpp
+++ b/llvm/lib/TargetParser/Host.cpp
@@ -682,7 +682,7 @@ VendorSignatures getVendorSignature(unsigned *MaxLeaf) {
if (EBX == 0x68747541 && EDX == 0x69746e65 && ECX == 0x444d4163)
return VendorSignatures::AUTHENTIC_AMD;
- // "Hygo nGen uien"
+ // "Hygo nGen uine"
if (EBX == 0x6f677948 && EDX == 0x6e65476e && ECX == 0x656e6975)
return VendorSignatures::HYGON_GENUINE;
>From 41c2607ef5114cc8c3ce45317b4957d88100648c Mon Sep 17 00:00:00 2001
From: zhangxiaomeng <zhangxiaomeng at hygon.cn>
Date: Fri, 20 Mar 2026 16:50:45 +0800
Subject: [PATCH 03/11] fix some clang-format errors
---
compiler-rt/lib/builtins/cpu_model/x86.c | 4 ++--
llvm/lib/TargetParser/Host.cpp | 11 ++++++-----
llvm/lib/TargetParser/X86TargetParser.cpp | 13 +++++++------
3 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/compiler-rt/lib/builtins/cpu_model/x86.c b/compiler-rt/lib/builtins/cpu_model/x86.c
index 44e0560391966..b0e1f0bdcc5c4 100644
--- a/compiler-rt/lib/builtins/cpu_model/x86.c
+++ b/compiler-rt/lib/builtins/cpu_model/x86.c
@@ -880,8 +880,8 @@ getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model,
static const char *
getHygonProcessorTypeAndSubtype(unsigned Family, unsigned Model,
- const unsigned *Features,
- struct __processor_model *CpuModel) {
+ const unsigned *Features,
+ struct __processor_model *CpuModel) {
const char *CPU = 0;
enum ProcessorTypes Type = CPU_TYPE_MAX;
diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp
index 2124b0e3783ac..881c963585e75 100644
--- a/llvm/lib/TargetParser/Host.cpp
+++ b/llvm/lib/TargetParser/Host.cpp
@@ -1359,10 +1359,11 @@ static const char *getAMDProcessorTypeAndSubtype(unsigned Family,
return CPU;
}
-static StringRef
-getHygonProcessorTypeAndSubtype(unsigned Family, unsigned Model,
- const unsigned *Features,
- unsigned *Type, unsigned *Subtype) {
+static StringRef getHygonProcessorTypeAndSubtype(unsigned Family,
+ unsigned Model,
+ const unsigned *Features,
+ unsigned *Type,
+ unsigned *Subtype) {
StringRef CPU;
switch (Family) {
@@ -1556,7 +1557,7 @@ StringRef sys::getHostCPUName() {
&Subtype);
} else if (Vendor == VendorSignatures::HYGON_GENUINE) {
CPU = getHygonProcessorTypeAndSubtype(Family, Model, Features, &Type,
- &Subtype);
+ &Subtype);
}
if (!CPU.empty())
diff --git a/llvm/lib/TargetParser/X86TargetParser.cpp b/llvm/lib/TargetParser/X86TargetParser.cpp
index f2e18b8b8d967..676a989977f3a 100644
--- a/llvm/lib/TargetParser/X86TargetParser.cpp
+++ b/llvm/lib/TargetParser/X86TargetParser.cpp
@@ -273,12 +273,13 @@ constexpr FeatureBitset FeaturesC86_4G_M4 =
static constexpr FeatureBitset FeaturesC86_4G_M6 = FeaturesC86_4G_M4;
-static constexpr FeatureBitset FeaturesC86_4G_M7 = FeaturesC86_4G_M4 |
- FeatureAVX512BF16 | FeatureAVX512BITALG | FeatureAVX512BW | FeatureAVX512CD |
- FeatureAVX512DQ | FeatureAVX512F | FeatureAVX512IFMA | FeatureAVX512VBMI |
- FeatureAVX512VBMI2 | FeatureAVX512VL | FeatureAVX512VNNI |
- FeatureAVX512VPOPCNTDQ | FeatureCLWB | FeatureCMOV | FeatureGFNI |
- FeatureVAES | FeatureVPCLMULQDQ | FeatureWBNOINVD;
+static constexpr FeatureBitset FeaturesC86_4G_M7 =
+ FeaturesC86_4G_M4 | FeatureAVX512BF16 | FeatureAVX512BITALG |
+ FeatureAVX512BW | FeatureAVX512CD | FeatureAVX512DQ | FeatureAVX512F |
+ FeatureAVX512IFMA | FeatureAVX512VBMI | FeatureAVX512VBMI2 |
+ FeatureAVX512VL | FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureCLWB |
+ FeatureCMOV | FeatureGFNI | FeatureVAES | FeatureVPCLMULQDQ |
+ FeatureWBNOINVD;
// D151696 tranplanted Mangling and OnlyForCPUDispatchSpecific from
// X86TargetParser.def to here. They are assigned by following ways:
>From 31d214f7ac165931f934edfae90a371251e0dbb5 Mon Sep 17 00:00:00 2001
From: zhangxiaomeng <zhangxiaomeng at hygon.cn>
Date: Sun, 22 Mar 2026 12:33:20 +0800
Subject: [PATCH 04/11] Change c86-4g-m6 KeyFeature to right.
---
llvm/lib/TargetParser/X86TargetParser.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/TargetParser/X86TargetParser.cpp b/llvm/lib/TargetParser/X86TargetParser.cpp
index 676a989977f3a..012cdabfb85e6 100644
--- a/llvm/lib/TargetParser/X86TargetParser.cpp
+++ b/llvm/lib/TargetParser/X86TargetParser.cpp
@@ -469,7 +469,7 @@ constexpr ProcInfo Processors[] = {
{ {"znver6"}, CK_ZNVER6, FEATURE_AVX512FP16, FeaturesZNVER6, '\0', false },
// Hygon precessors.
{ {"c86-4g-m4"}, CK_C86_4G_M4, FEATURE_AVX2, FeaturesC86_4G_M4 , '\0', false },
- { {"c86-4g-m6"}, CK_C86_4G_M6, FEATURE_AVX512VBMI2, FeaturesC86_4G_M6 , '\0', false },
+ { {"c86-4g-m6"}, CK_C86_4G_M6, FEATURE_AVX2, FeaturesC86_4G_M6 , '\0', false },
{ {"c86-4g-m7"}, CK_C86_4G_M7, FEATURE_AVX512VBMI2, FeaturesC86_4G_M7 , '\0', false },
// Generic 64-bit processor.
{ {"x86-64"}, CK_x86_64, FEATURE_SSE2 , FeaturesX86_64, '\0', false },
>From 21da8f14665c0c4d6b2abfa64470cdf75f003412 Mon Sep 17 00:00:00 2001
From: zhangxiaomeng <zhangxiaomeng at hygon.cn>
Date: Sun, 22 Mar 2026 14:16:57 +0800
Subject: [PATCH 05/11] Add and update some comments.
---
llvm/lib/Target/X86/X86.td | 5 ++++-
llvm/lib/TargetParser/X86TargetParser.cpp | 2 +-
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 0080732ec198a..61e863bf46431 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -1662,6 +1662,7 @@ def ProcessorFeatures {
list<SubtargetFeature> ZN6Features =
!listconcat(ZN5Features, ZN6AdditionalFeatures);
+ // Hygon Processors common ISAs
list<SubtargetFeature> C864GM4Features = [FeatureADX,
FeatureAES,
FeatureAVX2,
@@ -1710,9 +1711,11 @@ def ProcessorFeatures {
TuningInsertVZEROUPPER,
TuningAllowLight256Bit];
+ // C86-4G-M6
list<SubtargetFeature> C864GM6Features = C864GM4Features;
list<SubtargetFeature> C864GM6Tuning = C864GM4Tuning;
-
+
+ // C86-4G-M7
list<SubtargetFeature> C864GM7AdditionalFeatures = [FeatureAVX512,
FeatureBF16,
FeatureBITALG,
diff --git a/llvm/lib/TargetParser/X86TargetParser.cpp b/llvm/lib/TargetParser/X86TargetParser.cpp
index 012cdabfb85e6..b924851cd0c53 100644
--- a/llvm/lib/TargetParser/X86TargetParser.cpp
+++ b/llvm/lib/TargetParser/X86TargetParser.cpp
@@ -467,7 +467,7 @@ constexpr ProcInfo Processors[] = {
{ {"znver4"}, CK_ZNVER4, FEATURE_AVX512VBMI2, FeaturesZNVER4, '\0', false },
{ {"znver5"}, CK_ZNVER5, FEATURE_AVX512VP2INTERSECT, FeaturesZNVER5, '\0', false },
{ {"znver6"}, CK_ZNVER6, FEATURE_AVX512FP16, FeaturesZNVER6, '\0', false },
- // Hygon precessors.
+ // Hygon processors.
{ {"c86-4g-m4"}, CK_C86_4G_M4, FEATURE_AVX2, FeaturesC86_4G_M4 , '\0', false },
{ {"c86-4g-m6"}, CK_C86_4G_M6, FEATURE_AVX2, FeaturesC86_4G_M6 , '\0', false },
{ {"c86-4g-m7"}, CK_C86_4G_M7, FEATURE_AVX512VBMI2, FeaturesC86_4G_M7 , '\0', false },
>From e7c93df8ab25f329fe8d0d9f3722867762514669 Mon Sep 17 00:00:00 2001
From: zhangxiaomeng <zhangxiaomeng at hygon.cn>
Date: Thu, 26 Mar 2026 14:31:05 +0800
Subject: [PATCH 06/11] Change the macro names from hyphens to underscores.
---
clang/lib/Basic/Targets/X86.cpp | 6 ++---
.../Preprocessor/predefined-arch-macros.c | 24 +++++++++----------
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index fd30c7f8d61b9..becae6e9526a6 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -730,13 +730,13 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
defineCPUMacros(Builder, "geode");
break;
case CK_C86_4G_M4:
- defineCPUMacros(Builder, "c86-4g-m4");
+ defineCPUMacros(Builder, "c86_4g_m4");
break;
case CK_C86_4G_M6:
- defineCPUMacros(Builder, "c86-4g-m6");
+ defineCPUMacros(Builder, "c86_4g_m6");
break;
case CK_C86_4G_M7:
- defineCPUMacros(Builder, "c86-4g-m7");
+ defineCPUMacros(Builder, "c86_4g_m7");
break;
}
diff --git a/clang/test/Preprocessor/predefined-arch-macros.c b/clang/test/Preprocessor/predefined-arch-macros.c
index bc950f5ecee9c..79e3b282c7058 100644
--- a/clang/test/Preprocessor/predefined-arch-macros.c
+++ b/clang/test/Preprocessor/predefined-arch-macros.c
@@ -4326,10 +4326,10 @@
// CHECK_C864GM4_M32: #define __XSAVEOPT__ 1
// CHECK_C864GM4_M32: #define __XSAVES__ 1
// CHECK_C864GM4_M32: #define __XSAVE__ 1
-// CHECK_C864GM4_M32: #define __c86 -4g-m4__ 1
+// CHECK_C864GM4_M32: #define __c86_4g_m4__ 1
// CHECK_C864GM4_M32: #define __i386 1
// CHECK_C864GM4_M32: #define __i386__ 1
-// CHECK_C864GM4_M32: #define __tune_c86 -4g-m4__ 1
+// CHECK_C864GM4_M32: #define __tune_c86_4g_m4__ 1
// RUN: %clang -march=c86-4g-m4 -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
@@ -4370,8 +4370,8 @@
// CHECK_C864GM4_M64: #define __XSAVEOPT__ 1
// CHECK_C864GM4_M64: #define __XSAVES__ 1
// CHECK_C864GM4_M64: #define __XSAVE__ 1
-// CHECK_C864GM4_M64: #define __c86 -4g-m4__ 1
-// CHECK_C864GM4_M64: #define __tune_c86 -4g-m4__ 1
+// CHECK_C864GM4_M64: #define __c86_4g_m4__ 1
+// CHECK_C864GM4_M64: #define __tune_c86_4g_m4__ 1
// CHECK_C864GM4_M64: #define __x86_64 1
// CHECK_C864GM4_M64: #define __x86_64__ 1
@@ -4414,10 +4414,10 @@
// CHECK_C864GM6_M32: #define __XSAVEOPT__ 1
// CHECK_C864GM6_M32: #define __XSAVES__ 1
// CHECK_C864GM6_M32: #define __XSAVE__ 1
-// CHECK_C864GM6_M32: #define __c86 -4g-m6__ 1
+// CHECK_C864GM6_M32: #define __c86_4g_m6__ 1
// CHECK_C864GM6_M32: #define __i386 1
// CHECK_C864GM6_M32: #define __i386__ 1
-// CHECK_C864GM6_M32: #define __tune_c86 -4g-m6__ 1
+// CHECK_C864GM6_M32: #define __tune_c86_4g_m6__ 1
// RUN: %clang -march=c86-4g-m6 -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
@@ -4458,8 +4458,8 @@
// CHECK_C864GM6_M64: #define __XSAVEOPT__ 1
// CHECK_C864GM6_M64: #define __XSAVES__ 1
// CHECK_C864GM6_M64: #define __XSAVE__ 1
-// CHECK_C864GM6_M64: #define __c86 -4g-m6__ 1
-// CHECK_C864GM6_M64: #define __tune_c86 -4g-m6__ 1
+// CHECK_C864GM6_M64: #define __c86_4g_m6__ 1
+// CHECK_C864GM6_M64: #define __tune_c86_4g_m6__ 1
// CHECK_C864GM6_M64: #define __x86_64 1
// CHECK_C864GM6_M64: #define __x86_64__ 1
@@ -4519,10 +4519,10 @@
// CHECK_C864GM7_M32: #define __XSAVEOPT__ 1
// CHECK_C864GM7_M32: #define __XSAVES__ 1
// CHECK_C864GM7_M32: #define __XSAVE__ 1
-// CHECK_C864GM7_M32: #define __c86 -4g-m7__ 1
+// CHECK_C864GM7_M32: #define __c86_4g_m7__ 1
// CHECK_C864GM7_M32: #define __i386 1
// CHECK_C864GM7_M32: #define __i386__ 1
-// CHECK_C864GM7_M32: #define __tune_c86 -4g-m7__ 1
+// CHECK_C864GM7_M32: #define __tune_c86_4g_m7__ 1
// RUN: %clang -march=c86-4g-m7 -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
@@ -4580,8 +4580,8 @@
// CHECK_C864GM7_M64: #define __XSAVEOPT__ 1
// CHECK_C864GM7_M64: #define __XSAVES__ 1
// CHECK_C864GM7_M64: #define __XSAVE__ 1
-// CHECK_C864GM7_M64: #define __c86 -4g-m7__ 1
-// CHECK_C864GM7_M64: #define __tune_c86 -4g-m7__ 1
+// CHECK_C864GM7_M64: #define __c86_4g_m7__ 1
+// CHECK_C864GM7_M64: #define __tune_c86_4g_m7__ 1
// CHECK_C864GM7_M64: #define __x86_64 1
// CHECK_C864GM7_M64: #define __x86_64__ 1
>From 196317d28e2c53f38928e738f7b0548d15137086 Mon Sep 17 00:00:00 2001
From: Xiaomeng Zhang <zhangxiaomeng at hygon.cn>
Date: Thu, 26 Mar 2026 14:49:10 +0800
Subject: [PATCH 07/11] Update llvm/lib/Target/X86/X86.td
Co-authored-by: Carlo Cabrera <github at carlo.cab>
---
llvm/lib/Target/X86/X86.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 61e863bf46431..0adab58f9eff7 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -1711,7 +1711,7 @@ def ProcessorFeatures {
TuningInsertVZEROUPPER,
TuningAllowLight256Bit];
- // C86-4G-M6
+ // C86-4G-M6: same features as M4; kept separate for future differentiation
list<SubtargetFeature> C864GM6Features = C864GM4Features;
list<SubtargetFeature> C864GM6Tuning = C864GM4Tuning;
>From c31f14a00bbcbb412438044931d69527ca1126af Mon Sep 17 00:00:00 2001
From: zhangxiaomeng <zhangxiaomeng at hygon.cn>
Date: Thu, 14 May 2026 15:43:53 +0800
Subject: [PATCH 08/11] Add C864GM4 and C864GM7 Schedule Model
---
llvm/lib/Target/X86/X86.td | 11 +-
llvm/lib/Target/X86/X86ScheduleC864GM4.td | 1014 ++++
llvm/lib/Target/X86/X86ScheduleC864GM7.td | 3721 ++++++++++++
.../CodeGen/X86/bypass-slow-division-64.ll | 1 +
.../tools/llvm-mca/X86/4GM4/resources-adx.s | 66 +
.../tools/llvm-mca/X86/4GM4/resources-aes.s | 82 +
.../tools/llvm-mca/X86/4GM4/resources-avx1.s | 2442 ++++++++
.../tools/llvm-mca/X86/4GM4/resources-avx2.s | 1092 ++++
.../tools/llvm-mca/X86/4GM4/resources-bmi1.s | 131 +
.../tools/llvm-mca/X86/4GM4/resources-bmi2.s | 152 +
.../llvm-mca/X86/4GM4/resources-clflushopt.s | 44 +
.../llvm-mca/X86/4GM4/resources-clzero.s | 44 +
.../tools/llvm-mca/X86/4GM4/resources-cmov.s | 334 ++
.../llvm-mca/X86/4GM4/resources-cmpxchg.s | 53 +
.../tools/llvm-mca/X86/4GM4/resources-f16c.s | 68 +
.../tools/llvm-mca/X86/4GM4/resources-fma.s | 712 +++
.../llvm-mca/X86/4GM4/resources-fsgsbase.s | 68 +
.../tools/llvm-mca/X86/4GM4/resources-lea.s | 448 ++
.../tools/llvm-mca/X86/4GM4/resources-lzcnt.s | 61 +
.../tools/llvm-mca/X86/4GM4/resources-mmx.s | 404 ++
.../tools/llvm-mca/X86/4GM4/resources-movbe.s | 61 +
.../llvm-mca/X86/4GM4/resources-mwaitx.s | 47 +
.../llvm-mca/X86/4GM4/resources-pclmul.s | 47 +
.../llvm-mca/X86/4GM4/resources-popcnt.s | 61 +
.../llvm-mca/X86/4GM4/resources-prefetchw.s | 47 +
.../llvm-mca/X86/4GM4/resources-rdrand.s | 50 +
.../llvm-mca/X86/4GM4/resources-rdseed.s | 50 +
.../tools/llvm-mca/X86/4GM4/resources-sha.s | 89 +
.../tools/llvm-mca/X86/4GM4/resources-sse1.s | 472 ++
.../tools/llvm-mca/X86/4GM4/resources-sse2.s | 971 +++
.../tools/llvm-mca/X86/4GM4/resources-sse3.s | 115 +
.../tools/llvm-mca/X86/4GM4/resources-sse41.s | 377 ++
.../tools/llvm-mca/X86/4GM4/resources-sse42.s | 110 +
.../tools/llvm-mca/X86/4GM4/resources-sse4a.s | 61 +
.../tools/llvm-mca/X86/4GM4/resources-ssse3.s | 264 +
.../llvm-mca/X86/4GM4/resources-x86_32.s | 89 +
.../llvm-mca/X86/4GM4/resources-x86_64.s | 2890 +++++++++
.../tools/llvm-mca/X86/4GM4/resources-x87.s | 532 ++
.../tools/llvm-mca/X86/4GM4/resources-xsave.s | 60 +
.../tools/llvm-mca/X86/4GM4/zero-idioms.s | 507 ++
.../X86/4GM7/independent-load-stores.s | 155 +
.../partially-overlapping-group-resources.s | 91 +
.../tools/llvm-mca/X86/4GM7/resources-adx.s | 70 +
.../tools/llvm-mca/X86/4GM7/resources-aes.s | 86 +
.../tools/llvm-mca/X86/4GM7/resources-avx1.s | 2446 ++++++++
.../tools/llvm-mca/X86/4GM7/resources-avx2.s | 1096 ++++
.../llvm-mca/X86/4GM7/resources-avx512.s | 3264 ++++++++++
.../X86/4GM7/resources-avx512bitalg.s | 95 +
.../X86/4GM7/resources-avx512bitalgvl.s | 146 +
.../llvm-mca/X86/4GM7/resources-avx512bw.s | 1654 +++++
.../llvm-mca/X86/4GM7/resources-avx512bwvl.s | 2976 +++++++++
.../llvm-mca/X86/4GM7/resources-avx512cd.s | 164 +
.../llvm-mca/X86/4GM7/resources-avx512cdvl.s | 282 +
.../llvm-mca/X86/4GM7/resources-avx512dq.s | 1277 ++++
.../llvm-mca/X86/4GM7/resources-avx512dqvl.s | 1677 ++++++
.../llvm-mca/X86/4GM7/resources-avx512gfni.s | 119 +
.../X86/4GM7/resources-avx512gfnivl.s | 194 +
.../llvm-mca/X86/4GM7/resources-avx512ifma.s | 100 +
.../X86/4GM7/resources-avx512ifmavl.s | 156 +
.../llvm-mca/X86/4GM7/resources-avx512vaes.s | 72 +
.../X86/4GM7/resources-avx512vaesvl.s | 100 +
.../llvm-mca/X86/4GM7/resources-avx512vbmi.s | 129 +
.../llvm-mca/X86/4GM7/resources-avx512vbmi2.s | 408 ++
.../X86/4GM7/resources-avx512vbmi2vl.s | 772 +++
.../X86/4GM7/resources-avx512vbmivl.s | 214 +
.../llvm-mca/X86/4GM7/resources-avx512vl.s | 5294 +++++++++++++++++
.../llvm-mca/X86/4GM7/resources-avx512vnni.s | 156 +
.../X86/4GM7/resources-avx512vnnivl.s | 268 +
.../X86/4GM7/resources-avx512vp2intersect.s | 53 +
.../X86/4GM7/resources-avx512vp2intersectvl.s | 73 +
.../X86/4GM7/resources-avx512vpclmulqdq.s | 51 +
.../X86/4GM7/resources-avx512vpclmulqdqvl.s | 58 +
.../X86/4GM7/resources-avx512vpopcntdq.s | 104 +
.../X86/4GM7/resources-avx512vpopcntdqvl.s | 164 +
.../llvm-mca/X86/4GM7/resources-avxgfni.s | 86 +
.../llvm-mca/X86/4GM7/resources-avxvnni.s | 100 +
.../tools/llvm-mca/X86/4GM7/resources-bmi1.s | 135 +
.../tools/llvm-mca/X86/4GM7/resources-bmi2.s | 156 +
.../llvm-mca/X86/4GM7/resources-clflushopt.s | 48 +
.../tools/llvm-mca/X86/4GM7/resources-clwb.s | 48 +
.../tools/llvm-mca/X86/4GM7/resources-cmov.s | 338 ++
.../llvm-mca/X86/4GM7/resources-cmpxchg.s | 57 +
.../tools/llvm-mca/X86/4GM7/resources-f16c.s | 72 +
.../tools/llvm-mca/X86/4GM7/resources-fma.s | 716 +++
.../llvm-mca/X86/4GM7/resources-fsgsbase.s | 72 +
.../tools/llvm-mca/X86/4GM7/resources-gfni.s | 65 +
.../tools/llvm-mca/X86/4GM7/resources-lea.s | 452 ++
.../tools/llvm-mca/X86/4GM7/resources-lzcnt.s | 65 +
.../tools/llvm-mca/X86/4GM7/resources-mmx.s | 408 ++
.../tools/llvm-mca/X86/4GM7/resources-movbe.s | 65 +
.../llvm-mca/X86/4GM7/resources-mwaitx.s | 51 +
.../llvm-mca/X86/4GM7/resources-pclmul.s | 51 +
.../llvm-mca/X86/4GM7/resources-popcnt.s | 65 +
.../llvm-mca/X86/4GM7/resources-prefetchw.s | 51 +
.../llvm-mca/X86/4GM7/resources-rdrand.s | 54 +
.../llvm-mca/X86/4GM7/resources-rdseed.s | 54 +
.../tools/llvm-mca/X86/4GM7/resources-sha.s | 93 +
.../tools/llvm-mca/X86/4GM7/resources-sse1.s | 476 ++
.../tools/llvm-mca/X86/4GM7/resources-sse2.s | 975 +++
.../tools/llvm-mca/X86/4GM7/resources-sse3.s | 119 +
.../tools/llvm-mca/X86/4GM7/resources-sse41.s | 381 ++
.../tools/llvm-mca/X86/4GM7/resources-sse42.s | 114 +
.../tools/llvm-mca/X86/4GM7/resources-sse4a.s | 65 +
.../tools/llvm-mca/X86/4GM7/resources-ssse3.s | 268 +
.../tools/llvm-mca/X86/4GM7/resources-vaes.s | 72 +
.../llvm-mca/X86/4GM7/resources-vpclmulqdq.s | 51 +
.../llvm-mca/X86/4GM7/resources-x86_32.s | 93 +
.../llvm-mca/X86/4GM7/resources-x86_64.s | 2894 +++++++++
.../tools/llvm-mca/X86/4GM7/resources-x87.s | 536 ++
.../tools/llvm-mca/X86/4GM7/resources-xsave.s | 64 +
.../tools/llvm-mca/X86/4GM7/zero-idioms.s | 796 +++
111 files changed, 52014 insertions(+), 4 deletions(-)
create mode 100644 llvm/lib/Target/X86/X86ScheduleC864GM4.td
create mode 100644 llvm/lib/Target/X86/X86ScheduleC864GM7.td
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-adx.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-aes.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-avx1.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-avx2.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-bmi1.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-bmi2.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-clflushopt.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-clzero.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-cmov.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-cmpxchg.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-f16c.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-fma.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-fsgsbase.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-lea.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-lzcnt.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-mmx.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-movbe.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-mwaitx.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-pclmul.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-popcnt.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-prefetchw.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-rdrand.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-rdseed.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-sha.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-sse1.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-sse2.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-sse3.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-sse41.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-sse42.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-sse4a.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-ssse3.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-x86_32.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-x86_64.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-x87.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/resources-xsave.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM4/zero-idioms.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/independent-load-stores.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/partially-overlapping-group-resources.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-adx.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-aes.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-avx1.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-avx2.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bitalg.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bitalgvl.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bw.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bwvl.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512cd.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512cdvl.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512dq.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512dqvl.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512gfni.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512gfnivl.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512ifma.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512ifmavl.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vaes.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vaesvl.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmi.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmi2.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmi2vl.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmivl.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vl.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vnni.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vnnivl.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vp2intersect.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vp2intersectvl.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpclmulqdq.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpclmulqdqvl.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpopcntdq.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpopcntdqvl.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-avxgfni.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-avxvnni.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-bmi1.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-bmi2.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-clflushopt.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-clwb.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-cmov.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-cmpxchg.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-f16c.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-fma.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-fsgsbase.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-gfni.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-lea.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-lzcnt.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-mmx.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-movbe.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-mwaitx.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-pclmul.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-popcnt.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-prefetchw.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-rdrand.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-rdseed.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-sha.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-sse1.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-sse2.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-sse3.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-sse41.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-sse42.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-sse4a.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-ssse3.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-vaes.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-vpclmulqdq.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-x86_32.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-x86_64.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-x87.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/resources-xsave.s
create mode 100644 llvm/test/tools/llvm-mca/X86/4GM7/zero-idioms.s
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 0adab58f9eff7..ef2e23445c947 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -846,6 +846,9 @@ include "X86SchedIceLake.td"
include "X86SchedAlderlakeP.td"
include "X86SchedLunarlakeP.td"
include "X86SchedSapphireRapids.td"
+include "X86ScheduleC864GM4.td"
+include "X86ScheduleC864GM7.td"
+
//===----------------------------------------------------------------------===//
// X86 Processor Feature Lists
@@ -2106,11 +2109,11 @@ def : ProcModel<"znver6", Znver4Model, ProcessorFeatures.ZN6Features,
// Hygon CPUs.
-def : Proc<"c86-4g-m4", ProcessorFeatures.C864GM4Features,
+foreach P = ["c86-4g-m4", "c86-4g-m6"] in {
+def : ProcModel<P, C864GM4Model, ProcessorFeatures.C864GM4Features,
ProcessorFeatures.C864GM4Tuning>;
-def : Proc<"c86-4g-m6", ProcessorFeatures.C864GM6Features,
- ProcessorFeatures.C864GM6Tuning>;
-def : Proc<"c86-4g-m7", ProcessorFeatures.C864GM7Features,
+}
+def : ProcModel<"c86-4g-m7", C864GM7Model, ProcessorFeatures.C864GM7Features,
ProcessorFeatures.C864GM7Tuning>;
def : Proc<"geode", [FeatureX87, FeatureCX8, FeatureMMX, FeaturePRFCHW],
diff --git a/llvm/lib/Target/X86/X86ScheduleC864GM4.td b/llvm/lib/Target/X86/X86ScheduleC864GM4.td
new file mode 100644
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+++ b/llvm/lib/Target/X86/X86ScheduleC864GM4.td
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+//=- X86ScheduleC864GM4.td - X86 C86-4G-M4 Scheduling --------*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the machine model for C86-4G-M4 to support instruction
+// scheduling and other instruction cost heuristics.
+//
+//===----------------------------------------------------------------------===//
+
+def C864GM4Model : SchedMachineModel {
+ let IssueWidth = 4;
+ let MicroOpBufferSize = 224;
+ // The maximum dispatch is 6 ops/cycle, and a mispredict cost is 16 cycle from
+ // the op-cache, so the loop buffer is limited to 6*16 = 96.
+ let LoopMicroOpBufferSize = 96;
+ // The common case of branch misprediction penalty is 16 cycles.
+ let MispredictPenalty = 16;
+
+ let LoadLatency = 4;
+ int VecLoadLatency = 7;
+ int StoreLatency = 1;
+ let HighLatency = 25;
+
+ let PostRAScheduler = 1;
+
+ let CompleteModel = 1;
+}
+
+let SchedModel = C864GM4Model in {
+
+//===----------------------------------------------------------------------===//
+// Integer Execution Unit
+//===----------------------------------------------------------------------===//
+
+// The C864GM4 has 4 ALUs.
+def 4GM4ALU0 : ProcResource<1>;
+def 4GM4ALU1 : ProcResource<1>;
+def 4GM4ALU2 : ProcResource<1>;
+def 4GM4ALU3 : ProcResource<1>;
+
+def 4GM4ALU23 : ProcResGroup<[4GM4ALU2, 4GM4ALU3]>;
+
+// BRU on ALU0 and ALU3.
+defvar 4GM4BRU0 = 4GM4ALU0;
+defvar 4GM4BRU1 = 4GM4ALU3;
+
+def 4GM4BRU01 : ProcResGroup<[4GM4BRU0, 4GM4BRU1]>;
+
+// 72 Entry (4x18 entries) integer Scheduler.
+def 4GM4ALU : ProcResGroup<[4GM4ALU0, 4GM4BRU0,
+ 4GM4ALU1,
+ 4GM4ALU2,
+ 4GM4ALU3, 4GM4BRU1]> {
+ let BufferSize = 72;
+}
+
+// The integer physical register file consists of 192 registers.
+def 4GM4IntegerPRF : RegisterFile<192,
+ [GR64, CCR],
+ [1, 1],
+ [1, 0],
+ 6, // Max moves that can be eliminated per cycle.
+ 0>; // Restrict move elimination to zero regs.
+
+// AGU
+// The C864GM4 has 3 AGUs.
+def 4GM4AGU0 : ProcResource<1>;
+def 4GM4AGU1 : ProcResource<1>;
+def 4GM4AGU2 : ProcResource<1>;
+// 28 Entry (1x28 entries) AGU group.
+def 4GM4AGU : ProcResGroup<[4GM4AGU0, 4GM4AGU1, 4GM4AGU2]> {
+ let BufferSize = 28;
+}
+
+//===----------------------------------------------------------------------===//
+// Floating-Point Unit
+//===----------------------------------------------------------------------===//
+
+// The C864GM4 has 4 FPUs.
+def 4GM4FPU0 : ProcResource<1>;
+def 4GM4FPU1 : ProcResource<1>;
+def 4GM4FPU2 : ProcResource<1>;
+def 4GM4FPU3 : ProcResource<1>;
+
+def 4GM4FPU01 : ProcResGroup<[4GM4FPU0, 4GM4FPU1]>;
+def 4GM4FPU13 : ProcResGroup<[4GM4FPU1, 4GM4FPU3]>;
+def 4GM4FPU23 : ProcResGroup<[4GM4FPU2, 4GM4FPU3]>;
+def 4GM4FPU02 : ProcResGroup<[4GM4FPU0, 4GM4FPU2]>;
+
+// 48 Entry (4x12 entries) floating-point Scheduler.
+def 4GM4FPU : ProcResGroup<[4GM4FPU0, 4GM4FPU1, 4GM4FPU2, 4GM4FPU3]> {
+ let BufferSize = 48;
+}
+
+// The floating point physical register file consists of 176 registers.
+def 4GM4FpuPRF : RegisterFile<176,
+ [VR64, VR128, VR256],
+ [1, 1, 1],
+ [0, 1, 1],
+ 6, // Max moves that can be eliminated per cycle.
+ 0>; // Restrict move elimination to zero regs.
+
+//===----------------------------------------------------------------------===//
+// Load-Store Unit
+//===----------------------------------------------------------------------===//
+
+// Load/Store Units and Memory Queues
+// The C864GM4 has 3 LS Units.
+def 4GM4LSU : ProcResource<3>;
+
+// The two of LSU can be loads.
+let Super = 4GM4LSU in
+def 4GM4Load : ProcResource<2> {
+ // The LDQ is 50.
+ let BufferSize = 50;
+}
+def 4GM4LoadQueue : LoadQueue<4GM4Load>;
+
+// All three of LSU can be loads.
+let Super = 4GM4LSU in
+def 4GM4Store : ProcResource<3> {
+ // The STQ is 52.
+ let BufferSize = 52;
+}
+def 4GM4StoreQueue : StoreQueue<4GM4Store>;
+
+def : ReadAdvance<ReadAfterLd, C864GM4Model.LoadLatency>;
+def : ReadAdvance<ReadAfterVecLd, C864GM4Model.VecLoadLatency>;
+def : ReadAdvance<ReadAfterVecXLd, C864GM4Model.VecLoadLatency>;
+def : ReadAdvance<ReadAfterVecYLd, C864GM4Model.VecLoadLatency>;
+def : ReadAdvance<ReadInt2Fpu, 0>;
+
+//===----------------------------------------------------------------------===//
+// Retire Control Unit
+//===----------------------------------------------------------------------===//
+
+def 4GM4RCU : RetireControlUnit<C864GM4Model.MicroOpBufferSize, 8>;
+
+//===----------------------------------------------------------------------===//
+// Basic helper classes.
+//===----------------------------------------------------------------------===//
+
+// Many SchedWrites are defined in pairs with and without a folded load.
+// Instructions with folded loads are usually micro-fused, so they only appear
+// as two micro-ops when dispatched by the schedulers.
+// This multiclass defines the resource usage for variants with and without
+// folded loads.
+
+
+multiclass __4GM4WriteRes<SchedWrite SchedRW, list<ProcResourceKind> ExePorts,
+ int Lat = 1, list<int> Res = [], int UOps = 1> {
+ def : WriteRes<SchedRW, ExePorts> {
+ let Latency = Lat;
+ let ReleaseAtCycles = Res;
+ let NumMicroOps = UOps;
+ }
+}
+
+multiclass __4GM4WriteResPair<X86FoldableSchedWrite SchedRW,
+ list<ProcResourceKind> ExePorts, int Lat,
+ list<int> Res, int UOps, int LoadLat, int LoadUOps,
+ ProcResourceKind AGU, int LoadRes> {
+ defm : __4GM4WriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
+
+ defm : __4GM4WriteRes<SchedRW.Folded,
+ !listconcat([AGU, 4GM4Load], ExePorts),
+ !add(LoadLat, Lat),
+ !if(!and(!empty(Res), !eq(LoadRes, 1)),
+ [],
+ !listconcat([1, LoadRes],
+ !if(!empty(Res),
+ !listsplat(1, !size(ExePorts)),
+ Res))),
+ !add(UOps, LoadUOps)>;
+}
+
+// For classes without folded loads.
+multiclass 4GM4WriteRes<SchedWrite SchedRW,
+ list<ProcResourceKind> ExePorts, int Lat = 1,
+ list<int> Res = [], int UOps = 1> {
+ defm : __4GM4WriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
+}
+
+// For classes with folded loads.
+multiclass 4GM4WriteResIntPair<X86FoldableSchedWrite SchedRW,
+ list<ProcResourceKind> ExePorts, int Lat = 1,
+ list<int> Res = [], int UOps = 1,
+ int LoadUOps = 0, int LoadRes = 1> {
+ defm : __4GM4WriteResPair<SchedRW, ExePorts, Lat, Res, UOps,
+ C864GM4Model.LoadLatency,
+ LoadUOps, 4GM4AGU, LoadRes>;
+}
+
+multiclass 4GM4WriteResFPPair<X86FoldableSchedWrite SchedRW,
+ list<ProcResourceKind> ExePorts, int Lat = 1,
+ list<int> Res = [], int UOps = 1,
+ int LoadUOps = 0, int LoadRes = 1> {
+ defm : __4GM4WriteResPair<SchedRW, ExePorts, Lat, Res, UOps,
+ C864GM4Model.VecLoadLatency,
+ LoadUOps, 4GM4AGU, LoadRes>;
+}
+
+// Microcoded Instructions
+def 4GM4WriteMicrocoded : SchedWriteRes<[]> {
+ let Latency = 100;
+}
+
+def : SchedAlias<WriteMicrocoded, 4GM4WriteMicrocoded>;
+def : SchedAlias<WriteSystem, 4GM4WriteMicrocoded>;
+def : SchedAlias<WriteFCMOV, 4GM4WriteMicrocoded>;
+def : SchedAlias<WriteLDMXCSR, 4GM4WriteMicrocoded>;
+def : SchedAlias<WriteSTMXCSR, 4GM4WriteMicrocoded>;
+def : SchedAlias<WriteDPPS, 4GM4WriteMicrocoded>;
+def : SchedAlias<WriteDPPSY, 4GM4WriteMicrocoded>;
+def : SchedAlias<WriteDPPSLd, 4GM4WriteMicrocoded>;
+def : SchedAlias<WriteDPPSYLd,4GM4WriteMicrocoded>;
+
+def 4GM4WritePDEP_PEXT : SchedWriteRes<[]>;
+def : InstRW<[4GM4WritePDEP_PEXT], (instregex "PDEP(32|64)rr",
+ "PEXT(32|64)rr")>;
+def : SchedAlias<4GM4WritePDEP_PEXT, 4GM4WriteMicrocoded>;
+def 4GM4WritePDEP_PEXTLd : SchedWriteRes<[]>;
+def : InstRW<[4GM4WritePDEP_PEXTLd], (instregex "PDEP(32|64)rm",
+ "PEXT(32|64)rm")>;
+def : SchedAlias<4GM4WritePDEP_PEXTLd, 4GM4WriteMicrocoded>;
+
+// Integer Instructions
+
+defm : 4GM4WriteRes<WriteRMW, [4GM4AGU, 4GM4Store]>;
+
+defm : 4GM4WriteRes<WriteStore, [4GM4AGU, 4GM4Store]>;
+defm : 4GM4WriteRes<WriteStoreNT, [4GM4AGU, 4GM4Store]>;
+defm : 4GM4WriteRes<WriteMove, [4GM4ALU]>;
+defm : 4GM4WriteRes<WriteLoad, [4GM4AGU, 4GM4Load], !add(1, C864GM4Model.LoadLatency)>;
+
+defm : 4GM4WriteRes<WriteVecMaskedGatherWriteback, [], !add(1, C864GM4Model.VecLoadLatency)>;
+
+defm : 4GM4WriteRes<WriteZero, [], 0, [], 1>;
+defm : 4GM4WriteRes<WriteLEA, [4GM4ALU]>;
+defm : 4GM4WriteResIntPair<WriteALU, [4GM4ALU], 1>;
+defm : 4GM4WriteResIntPair<WriteADC, [4GM4ALU], 1>;
+
+// This write is used for slow LEA instructions.
+def 4GM4Write3OpsLEA : SchedWriteRes<[4GM4ALU23]> {
+ let Latency = 2;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 2;
+}
+// a slow LEA is either a 3Ops LEA (base, index, offset),
+// or an LEA with a `Scale` value different than 1.
+def 4GM4SlowLEAPredicate : MCSchedPredicate<
+ CheckAny<[
+ IsThreeOperandsLEAFn,
+ CheckAll<[
+ CheckIsImmOperand<2>,
+ CheckNot<CheckImmOperand<2, 1>>
+ ]>
+ ]>
+>;
+
+def 4GM4WriteLEA : SchedWriteVariant<[
+ SchedVar<4GM4SlowLEAPredicate, [4GM4Write3OpsLEA]>,
+ SchedVar<NoSchedPred, [WriteLEA]>
+]>;
+
+def : InstRW<[4GM4WriteLEA], (instrs LEA64r, LEA64_32r)>;
+
+// MUL IMUL MULX
+defm : 4GM4WriteResIntPair<WriteIMul8, [4GM4ALU1], 3, [3], 1>;
+defm : 4GM4WriteResIntPair<WriteIMul16, [4GM4ALU1], 3, [3], 1>;
+defm : 4GM4WriteResIntPair<WriteIMul16Imm, [4GM4ALU1], 4, [4], 2>;
+defm : 4GM4WriteResIntPair<WriteIMul16Reg, [4GM4ALU1], 3>;
+defm : 4GM4WriteResIntPair<WriteIMul32, [4GM4ALU1], 3, [3], 1>;
+defm : 4GM4WriteResIntPair<WriteIMul32Imm, [4GM4ALU1], 3, [3], 2>;
+defm : 4GM4WriteResIntPair<WriteIMul32Reg, [4GM4ALU1], 3>;
+defm : 4GM4WriteResIntPair<WriteIMul64, [4GM4ALU1], 3, [3], 1>;
+defm : 4GM4WriteResIntPair<WriteIMul64Imm, [4GM4ALU1], 3, [3], 2>;
+defm : 4GM4WriteResIntPair<WriteIMul64Reg, [4GM4ALU1], 3>;
+
+defm : 4GM4WriteResIntPair<WriteMULX32, [4GM4ALU1], 3>;
+defm : 4GM4WriteResIntPair<WriteMULX64, [4GM4ALU1], 3>;
+defm : 4GM4WriteRes<WriteIMulHLd, [4GM4ALU1], !add(3, C864GM4Model.LoadLatency), [], 0>;
+defm : 4GM4WriteRes<WriteIMulH, [4GM4ALU1], 3, [], 0>;
+
+def 4GM4WriteMULX:SchedWriteRes<[4GM4ALU1]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM4WriteMULX], (instregex "MULX(32|64)rr")>;
+
+def 4GM4WriteMULXLd:SchedWriteRes<[4GM4AGU, 4GM4Load, 4GM4ALU1]> {
+ let Latency = !add(C864GM4Model.VecLoadLatency, 4GM4WriteMULX.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM4WriteMULXLd], (instregex "MULX(32|64)rm")>;
+
+// DIV IDIV
+defm : 4GM4WriteResIntPair<WriteDiv8, [4GM4ALU2], 12, [12], 2>;
+defm : 4GM4WriteResIntPair<WriteDiv16, [4GM4ALU2], 17, [17], 2>;
+defm : 4GM4WriteResIntPair<WriteDiv32, [4GM4ALU2], 25, [25], 2>;
+defm : 4GM4WriteResIntPair<WriteDiv64, [4GM4ALU2], 41, [41], 1>;
+defm : 4GM4WriteResIntPair<WriteIDiv8, [4GM4ALU2], 12, [12], 2>;
+defm : 4GM4WriteResIntPair<WriteIDiv16, [4GM4ALU2], 17, [17], 2>;
+defm : 4GM4WriteResIntPair<WriteIDiv32, [4GM4ALU2], 25, [25], 2>;
+defm : 4GM4WriteResIntPair<WriteIDiv64, [4GM4ALU2], 41, [41], 1>;
+
+defm : 4GM4WriteRes<WriteBSWAP32, [4GM4ALU], 1, [4], 1>;
+defm : 4GM4WriteRes<WriteBSWAP64, [4GM4ALU], 1, [4], 1>;
+defm : 4GM4WriteRes<WriteCMPXCHG, [4GM4ALU], 3>;
+defm : 4GM4WriteRes<WriteCMPXCHGRMW,[4GM4ALU, 4GM4AGU], 5, [1,1], 3>;
+
+def 4GM4WriteXCHGrm : SchedWriteRes<[4GM4AGU, 4GM4Load, 4GM4ALU]> {
+ let Latency = !add(C864GM4Model.LoadLatency, 1);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM4WriteXCHGrm], (instregex "XCHG(8|16|32|64)rm")>;
+
+defm : 4GM4WriteResIntPair<WriteShift, [4GM4ALU], 1>;
+defm : 4GM4WriteResIntPair<WriteShiftCL, [4GM4ALU], 1>;
+defm : 4GM4WriteResIntPair<WriteRotate, [4GM4ALU], 1>;
+defm : 4GM4WriteResIntPair<WriteRotateCL, [4GM4ALU], 1>;
+
+def 4GM4WriteRCR:SchedWriteRes<[4GM4ALU]> {
+ let Latency = 3;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM4WriteRCR], (instregex "RCR(8|16|32|64)rCL")>;
+
+def 4GM4WriteRCRLd:SchedWriteRes<[4GM4AGU, 4GM4Load, 4GM4ALU]> {
+ let Latency = !add(C864GM4Model.VecLoadLatency, 4GM4WriteRCR.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM4WriteRCRLd], (instregex "RCR(8|16|32|64)mCL")>;
+
+def 4GM4WriteRCL:SchedWriteRes<[4GM4ALU]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM4WriteRCL], (instregex "RCL(8|16|32|64)rCL")>;
+
+def 4GM4WriteRCLLd:SchedWriteRes<[4GM4AGU, 4GM4Load, 4GM4ALU]> {
+ let Latency = !add(C864GM4Model.VecLoadLatency, 4GM4WriteRCL.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM4WriteRCLLd], (instregex "RCL(8|16|32|64)mCL")>;
+
+
+defm : 4GM4WriteRes<WriteSHDrri, [4GM4ALU], 3, [3], 6>;
+defm : 4GM4WriteRes<WriteSHDrrcl, [4GM4ALU], 3, [5], 7>;
+defm : 4GM4WriteRes<WriteSHDmri, [4GM4ALU], 5, [5], 8>;
+defm : 4GM4WriteRes<WriteSHDmrcl, [4GM4ALU], 5, [5], 8>;
+
+defm : 4GM4WriteResIntPair<WriteJump, [4GM4ALU], 1>;
+defm : 4GM4WriteResIntPair<WriteCRC32, [4GM4ALU3], 3, [3], 3>;
+
+defm : 4GM4WriteResIntPair<WriteCMOV, [4GM4ALU], 1>;
+defm : 4GM4WriteRes<WriteSETCC, [4GM4ALU]>;
+defm : 4GM4WriteRes<WriteSETCCStore, [4GM4ALU, 4GM4AGU, 4GM4Store]>;
+defm : 4GM4WriteRes<WriteLAHFSAHF, [4GM4ALU], 2, [1], 2>;
+
+defm : 4GM4WriteRes<WriteBitTest, [4GM4ALU], 1>;
+defm : 4GM4WriteRes<WriteBitTestImmLd, [4GM4AGU, 4GM4Load, 4GM4ALU], !add(C864GM4Model.LoadLatency, 1), [1,1,1], 2>;
+defm : 4GM4WriteRes<WriteBitTestRegLd, [4GM4AGU, 4GM4Load, 4GM4ALU], !add(C864GM4Model.LoadLatency, 1), [1,1,1], 7>;
+defm : 4GM4WriteRes<WriteBitTestSet, [4GM4ALU], 2, [1], 2>;
+defm : 4GM4WriteRes<WriteBitTestSetImmLd, [4GM4AGU, 4GM4Load, 4GM4ALU], !add(C864GM4Model.LoadLatency, 2), [1, 1, 1], 2>;
+defm : 4GM4WriteRes<WriteBitTestSetRegLd, [4GM4AGU, 4GM4Load, 4GM4ALU], !add(C864GM4Model.LoadLatency, 2), [1, 1, 1], 7>;
+
+// Bit counts.
+defm : 4GM4WriteResIntPair<WriteBSF, [4GM4ALU], 3, [12], 6, 4, 2>;
+defm : 4GM4WriteResIntPair<WriteBSR, [4GM4ALU], 4, [16], 6, 4, 2>;
+defm : 4GM4WriteResIntPair<WriteLZCNT, [4GM4ALU], 1>;
+defm : 4GM4WriteResIntPair<WriteTZCNT, [4GM4ALU], 2, [2], 2, 4, 0>;
+defm : 4GM4WriteResIntPair<WritePOPCNT, [4GM4ALU], 1, [1], 1, 4, 0>;
+
+// Treat misc copies as a move.
+def : InstRW<[WriteMove], (instrs COPY)>;
+
+// BMI1 BEXTR, BMI2 BZHI
+defm : 4GM4WriteResIntPair<WriteBEXTR, [4GM4ALU], 1, [1], 1, 4, 1>;
+defm : 4GM4WriteResIntPair<WriteBLS, [4GM4ALU], 2, [2], 2, 4, 1>;
+defm : 4GM4WriteResIntPair<WriteBZHI, [4GM4ALU], 1>;
+
+// Floating Point Instructions
+
+defm : 4GM4WriteRes<WriteFLD0, [4GM4AGU, 4GM4AGU, 4GM4FPU1], !add(C864GM4Model.LoadLatency, 4), [1, 1, 1], 1>;
+defm : 4GM4WriteRes<WriteFLD1, [4GM4AGU, 4GM4AGU, 4GM4FPU1], !add(C864GM4Model.LoadLatency, 4), [1, 1, 1], 1>;
+defm : 4GM4WriteRes<WriteFLDC, [4GM4AGU, 4GM4AGU, 4GM4FPU1], !add(C864GM4Model.LoadLatency, 4), [1, 1, 1], 1>;
+defm : 4GM4WriteRes<WriteFLoad, [4GM4AGU, 4GM4Load], !add(C864GM4Model.VecLoadLatency, 1)>;
+defm : 4GM4WriteRes<WriteFLoadX, [4GM4AGU, 4GM4Load], !add(C864GM4Model.VecLoadLatency, 1)>;
+defm : 4GM4WriteRes<WriteFLoadY, [4GM4AGU, 4GM4Load], !add(C864GM4Model.VecLoadLatency, 1)>;
+defm : 4GM4WriteRes<WriteFMaskedLoad, [4GM4AGU, 4GM4Load, 4GM4FPU02], !add(C864GM4Model.VecLoadLatency, 1)>;
+defm : 4GM4WriteRes<WriteFMaskedLoadY, [4GM4AGU, 4GM4Load, 4GM4FPU02], !add(C864GM4Model.VecLoadLatency, 1), [1, 1, 1], 2>;
+
+defm : 4GM4WriteRes<WriteFStore, [4GM4AGU, 4GM4Store], C864GM4Model.StoreLatency>;
+defm : 4GM4WriteRes<WriteFStoreX, [4GM4AGU, 4GM4Store], C864GM4Model.StoreLatency>;
+defm : 4GM4WriteRes<WriteFStoreY, [4GM4AGU, 4GM4Store], C864GM4Model.StoreLatency>;
+defm : 4GM4WriteRes<WriteFStoreNT, [4GM4FPU1, 4GM4AGU, 4GM4Store], !add(C864GM4Model.StoreLatency, 4)>;
+defm : 4GM4WriteRes<WriteFStoreNTX, [4GM4FPU1, 4GM4AGU, 4GM4Store], !add(C864GM4Model.StoreLatency, 4)>;
+defm : 4GM4WriteRes<WriteFStoreNTY, [4GM4FPU1, 4GM4AGU, 4GM4Store], !add(C864GM4Model.StoreLatency, 4)>;
+defm : 4GM4WriteRes<WriteFMaskedStore32, [4GM4FPU02, 4GM4AGU, 4GM4Store], C864GM4Model.StoreLatency>;
+defm : 4GM4WriteRes<WriteFMaskedStore32Y, [4GM4FPU02, 4GM4AGU, 4GM4Store], C864GM4Model.StoreLatency>;
+defm : 4GM4WriteRes<WriteFMaskedStore64, [4GM4FPU02, 4GM4AGU, 4GM4Store], C864GM4Model.StoreLatency>;
+defm : 4GM4WriteRes<WriteFMaskedStore64Y, [4GM4FPU02, 4GM4AGU, 4GM4Store], C864GM4Model.StoreLatency>;
+
+defm : 4GM4WriteResFPPair<WriteFAdd, [4GM4FPU13], 3>;
+defm : 4GM4WriteResFPPair<WriteFAddX, [4GM4FPU13], 3>;
+defm : 4GM4WriteResFPPair<WriteFAddY, [4GM4FPU13], 3>;
+defm : X86WriteResPairUnsupported<WriteFAddZ>;
+defm : 4GM4WriteResFPPair<WriteFAdd64, [4GM4FPU13], 3>;
+defm : 4GM4WriteResFPPair<WriteFAdd64X, [4GM4FPU13], 3>;
+defm : 4GM4WriteResFPPair<WriteFAdd64Y, [4GM4FPU13], 3>;
+defm : X86WriteResPairUnsupported<WriteFAdd64Z>;
+defm : 4GM4WriteResFPPair<WriteFHAdd, [4GM4FPU13], 7, [8], 4, 3>;
+defm : 4GM4WriteResFPPair<WriteFHAddY, [4GM4FPU13], 7, [8], 4, 3>;
+defm : X86WriteResPairUnsupported<WriteFHAddZ>;
+defm : 4GM4WriteResFPPair<WritePHAdd, [4GM4FPU13], 3, [8], 4, 3>;
+defm : 4GM4WriteResFPPair<WritePHAddX, [4GM4FPU13], 3, [8], 4, 3>;
+defm : 4GM4WriteResFPPair<WritePHAddY, [4GM4FPU13], 3, [8], 4, 3>;
+defm : X86WriteResPairUnsupported<WritePHAddZ>;
+defm : 4GM4WriteResFPPair<WriteFCmp, [4GM4FPU02], 1>;
+defm : 4GM4WriteResFPPair<WriteFCmpX, [4GM4FPU02], 1>;
+defm : 4GM4WriteResFPPair<WriteFCmpY, [4GM4FPU02], 1>;
+defm : X86WriteResPairUnsupported<WriteFCmpZ>;
+defm : 4GM4WriteResFPPair<WriteFCmp64, [4GM4FPU02], 1>;
+defm : 4GM4WriteResFPPair<WriteFCmp64X, [4GM4FPU02], 1>;
+defm : 4GM4WriteResFPPair<WriteFCmp64Y, [4GM4FPU02], 1>;
+defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
+defm : 4GM4WriteResFPPair<WriteFCom, [4GM4FPU02,4GM4FPU1], 5>;
+defm : 4GM4WriteResFPPair<WriteFComX, [4GM4FPU02,4GM4FPU1], 5>;
+defm : 4GM4WriteResFPPair<WriteFBlend, [4GM4FPU02], 1>;
+defm : 4GM4WriteResFPPair<WriteFBlendY, [4GM4FPU02], 1>;
+defm : X86WriteResPairUnsupported<WriteFBlendZ>;
+defm : 4GM4WriteResFPPair<WriteFVarBlend, [4GM4FPU02], 1>;
+defm : 4GM4WriteResFPPair<WriteFVarBlendY,[4GM4FPU02], 1>;
+defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
+defm : 4GM4WriteResFPPair<WriteCvtSS2I, [4GM4FPU1, 4GM4FPU1], 2, [1, 1], 2>;
+defm : 4GM4WriteResFPPair<WriteCvtPS2I, [4GM4FPU1], 4, [1], 2>;
+defm : 4GM4WriteResFPPair<WriteCvtPS2IY, [4GM4FPU1], 4, [1], 2>;
+defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
+defm : 4GM4WriteResFPPair<WriteCvtSD2I, [4GM4FPU1, 4GM4FPU1], 2, [1, 2], 2>;
+defm : 4GM4WriteResFPPair<WriteCvtPD2I, [4GM4FPU01, 4GM4FPU1], 7, [1, 2], 2>;
+defm : 4GM4WriteResFPPair<WriteCvtPD2IY, [4GM4FPU01, 4GM4FPU1], 9, [1, 2], 2>;
+defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
+defm : 4GM4WriteResFPPair<WriteCvtSS2SD, [4GM4FPU1], 4, [1], 1>;
+defm : 4GM4WriteResFPPair<WriteCvtPS2PD, [4GM4FPU13], 3, [1], 1>;
+defm : 4GM4WriteResFPPair<WriteCvtPS2PDY, [4GM4FPU13], 3, [1], 1>;
+defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;
+defm : 4GM4WriteResFPPair<WriteCvtSD2SS, [4GM4FPU1], 4, [1], 1>;
+defm : 4GM4WriteResFPPair<WriteCvtPD2PS, [4GM4FPU1, 4GM4FPU13], 3, [1, 1], 2>;
+defm : 4GM4WriteResFPPair<WriteCvtPD2PSY, [4GM4FPU1, 4GM4FPU13], 3, [1, 1], 2>;
+defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;
+defm : 4GM4WriteResFPPair<WriteCvtI2SS, [4GM4ALU2, 4GM4FPU1], 4, [1, 1], 2>;
+defm : 4GM4WriteResFPPair<WriteCvtI2PS, [4GM4FPU1], 4>;
+defm : 4GM4WriteResFPPair<WriteCvtI2PSY, [4GM4FPU1], 4>;
+defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
+defm : 4GM4WriteResFPPair<WriteCvtI2SD, [4GM4ALU2, 4GM4FPU1], 4, [1, 2], 2>;
+defm : 4GM4WriteResFPPair<WriteCvtI2PD, [4GM4FPU01, 4GM4FPU1], 7, [1, 2], 2>;
+defm : 4GM4WriteResFPPair<WriteCvtI2PDY, [4GM4FPU01, 4GM4FPU1], 9, [1, 2], 2>;
+defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
+defm : 4GM4WriteResFPPair<WriteCvtPH2PS, [4GM4FPU1], 7, [2], 1>;
+defm : 4GM4WriteResFPPair<WriteCvtPH2PSY, [4GM4FPU0], 9, [1], 1>;
+defm : X86WriteResPairUnsupported<WriteCvtPH2PSZ>;
+defm : 4GM4WriteRes<WriteCvtPS2PH, [4GM4FPU0], 7, [1], 1>;
+defm : 4GM4WriteRes<WriteCvtPS2PHY, [4GM4FPU1], 9, [2], 1>;
+defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;
+defm : 4GM4WriteRes<WriteCvtPS2PHSt, [4GM4FPU0, 4GM4AGU, 4GM4Store], !add(7, C864GM4Model.StoreLatency), [1, 1, 1], 2>;
+defm : 4GM4WriteRes<WriteCvtPS2PHYSt, [4GM4FPU1, 4GM4AGU, 4GM4Store], !add(9, C864GM4Model.StoreLatency), [2, 1, 1], 3>;
+defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;
+
+defm : 4GM4WriteResFPPair<WriteFDiv, [4GM4FPU1], 10, [5], 1>;
+defm : 4GM4WriteResFPPair<WriteFDivX, [4GM4FPU1], 10, [5], 1>;
+defm : 4GM4WriteResFPPair<WriteFDivY, [4GM4FPU1], 10, [5], 1>;
+defm : X86WriteResPairUnsupported<WriteFDivZ>;
+defm : 4GM4WriteResFPPair<WriteFDiv64, [4GM4FPU1], 8, [6], 1>;
+defm : 4GM4WriteResFPPair<WriteFDiv64X, [4GM4FPU1], 8, [6], 1>;
+defm : 4GM4WriteResFPPair<WriteFDiv64Y, [4GM4FPU1], 8, [6], 1>;
+defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
+defm : 4GM4WriteResFPPair<WriteFSign, [4GM4FPU13], 1>;
+defm : 4GM4WriteResFPPair<WriteFRnd, [4GM4FPU1], 4, [1], 1, C864GM4Model.VecLoadLatency, 0>;
+defm : 4GM4WriteResFPPair<WriteFRndY, [4GM4FPU1], 4, [1], 1, C864GM4Model.VecLoadLatency, 0>;
+defm : X86WriteResPairUnsupported<WriteFRndZ>;
+defm : 4GM4WriteResFPPair<WriteFLogic, [4GM4FPU], 1>;
+defm : 4GM4WriteResFPPair<WriteFLogicY, [4GM4FPU], 1>;
+defm : X86WriteResPairUnsupported<WriteFLogicZ>;
+defm : 4GM4WriteResFPPair<WriteFTest, [4GM4FPU01, 4GM4FPU1], 4, [1, 2], 1, C864GM4Model.VecLoadLatency, 1>;
+defm : 4GM4WriteResFPPair<WriteFTestY, [4GM4FPU01, 4GM4FPU1], 8, [1, 2], 1, C864GM4Model.VecLoadLatency, 1>;
+defm : X86WriteResPairUnsupported<WriteFTestZ>;
+defm : 4GM4WriteResFPPair<WriteFShuffle, [4GM4FPU01], 1>;
+defm : 4GM4WriteResFPPair<WriteFShuffleY, [4GM4FPU01], 1>;
+defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
+defm : 4GM4WriteResFPPair<WriteFVarShuffle, [4GM4FPU01], 3>;
+defm : 4GM4WriteResFPPair<WriteFVarShuffleY,[4GM4FPU01], 3>;
+defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
+defm : 4GM4WriteResFPPair<WriteFMul, [4GM4FPU02], 3>;
+defm : 4GM4WriteResFPPair<WriteFMulX, [4GM4FPU02], 3>;
+defm : 4GM4WriteResFPPair<WriteFMulY, [4GM4FPU02], 3>;
+defm : X86WriteResPairUnsupported<WriteFMulZ>;
+defm : 4GM4WriteResFPPair<WriteFMul64, [4GM4FPU02], 4>;
+defm : 4GM4WriteResFPPair<WriteFMul64X, [4GM4FPU02], 4>;
+defm : 4GM4WriteResFPPair<WriteFMul64Y, [4GM4FPU02], 4>;
+defm : X86WriteResPairUnsupported<WriteFMul64Z>;
+defm : 4GM4WriteResFPPair<WriteFMA, [4GM4FPU02], 5>;
+defm : 4GM4WriteResFPPair<WriteFMAX, [4GM4FPU02], 5>;
+defm : 4GM4WriteResFPPair<WriteFMAY, [4GM4FPU02], 5>;
+defm : X86WriteResPairUnsupported<WriteFMAZ>;
+defm : 4GM4WriteResFPPair<WriteFRcp, [4GM4FPU02], 5>;
+defm : 4GM4WriteResFPPair<WriteFRcpX, [4GM4FPU02], 5>;
+defm : 4GM4WriteResFPPair<WriteFRcpY, [4GM4FPU02], 5>;
+defm : X86WriteResPairUnsupported<WriteFRcpZ>;
+defm : 4GM4WriteResFPPair<WriteFRsqrt, [4GM4FPU02], 5>;
+defm : 4GM4WriteResFPPair<WriteFRsqrtX, [4GM4FPU02], 5>;
+defm : 4GM4WriteResFPPair<WriteFRsqrtY, [4GM4FPU02], 5>;
+defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
+defm : 4GM4WriteResFPPair<WriteFSqrt, [4GM4FPU1], 8, [7]>;
+defm : 4GM4WriteResFPPair<WriteFSqrtX, [4GM4FPU1], 8, [7]>;
+defm : 4GM4WriteResFPPair<WriteFSqrtY, [4GM4FPU1], 8, [7]>;
+defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
+defm : 4GM4WriteResFPPair<WriteFSqrt64, [4GM4FPU1], 8, [10]>;
+defm : 4GM4WriteResFPPair<WriteFSqrt64X, [4GM4FPU1], 8, [10]>;
+defm : 4GM4WriteResFPPair<WriteFSqrt64Y, [4GM4FPU1], 8, [10]>;
+defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
+defm : 4GM4WriteResFPPair<WriteFSqrt80, [4GM4FPU1], 22, [22]>;
+defm : 4GM4WriteResFPPair<WriteFShuffle256, [4GM4FPU0], 3>;
+defm : 4GM4WriteResFPPair<WriteFVarShuffle256, [4GM4FPU0], 3>;
+defm : 4GM4WriteResFPPair<WriteDPPD, [4GM4FPU1], 10, [8], 4>;
+
+def 4GM4WriteVPERM:SchedWriteRes<[4GM4FPU01]> {
+ let Latency = 7;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 3;
+}
+def : InstRW<[4GM4WriteVPERM], (instrs VPERM2I128rri, VPERM2F128rri)>;
+
+def 4GM4WriteVPERMLd:SchedWriteRes<[4GM4AGU, 4GM4Load, 4GM4FPU01]> {
+ let Latency = !add(C864GM4Model.VecLoadLatency, 4GM4WriteVPERM.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 3;
+}
+def : InstRW<[4GM4WriteVPERMLd], (instrs VPERM2I128rmi, VPERM2F128rmi)>;
+
+def 4GM4WriteVPERMDY:SchedWriteRes<[4GM4FPU0]> {
+ let Latency = 3;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 3;
+}
+def : InstRW<[4GM4WriteVPERMDY], (instrs VPERMDYrr)>;
+
+def 4GM4WriteVPERMDYLd:SchedWriteRes<[4GM4AGU, 4GM4Load, 4GM4FPU0]> {
+ let Latency = !add(C864GM4Model.VecLoadLatency, 4GM4WriteVPERMDY.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM4WriteVPERMDYLd], (instrs VPERMDYrm)>;
+
+defm : 4GM4WriteRes<WriteVecLoad, [4GM4AGU, 4GM4Load], !add(C864GM4Model.VecLoadLatency, 1), [1, 1], 1>;
+defm : 4GM4WriteRes<WriteVecLoadX, [4GM4AGU, 4GM4Load], !add(C864GM4Model.VecLoadLatency, 1), [1, 1], 1>;
+defm : 4GM4WriteRes<WriteVecLoadY, [4GM4AGU, 4GM4Load], !add(C864GM4Model.VecLoadLatency, 1), [1, 1], 1>;
+defm : 4GM4WriteRes<WriteVecLoadNT, [4GM4AGU, 4GM4Load], !add(C864GM4Model.VecLoadLatency, 1), [1, 1], 1>;
+defm : 4GM4WriteRes<WriteVecLoadNTY, [4GM4AGU, 4GM4Load], !add(C864GM4Model.VecLoadLatency, 1), [1, 1], 1>;
+defm : 4GM4WriteRes<WriteVecMaskedLoad, [4GM4AGU, 4GM4Load, 4GM4FPU02], !add(C864GM4Model.VecLoadLatency, 1), [1, 1, 2], 1>;
+defm : 4GM4WriteRes<WriteVecMaskedLoadY, [4GM4AGU, 4GM4Load, 4GM4FPU02], !add(C864GM4Model.VecLoadLatency, 1), [1, 1, 2], 1>;
+defm : 4GM4WriteRes<WriteVecStore, [4GM4AGU, 4GM4Store], C864GM4Model.StoreLatency>;
+defm : 4GM4WriteRes<WriteVecStoreX, [4GM4AGU, 4GM4Store], C864GM4Model.StoreLatency>;
+defm : 4GM4WriteRes<WriteVecStoreY, [4GM4AGU, 4GM4Store], C864GM4Model.StoreLatency>;
+defm : 4GM4WriteRes<WriteVecStoreNT, [4GM4FPU1, 4GM4AGU, 4GM4Store], !add(C864GM4Model.StoreLatency, 4)>;
+defm : 4GM4WriteRes<WriteVecStoreNTY, [4GM4FPU1, 4GM4AGU, 4GM4Store], !add(C864GM4Model.StoreLatency, 4)>;
+defm : 4GM4WriteRes<WriteVecMaskedStore32, [4GM4FPU02, 4GM4AGU, 4GM4Store], !add(C864GM4Model.StoreLatency, 1)>;
+defm : 4GM4WriteRes<WriteVecMaskedStore32Y, [4GM4FPU02, 4GM4AGU, 4GM4Store], !add(C864GM4Model.StoreLatency, 1)>;
+defm : 4GM4WriteRes<WriteVecMaskedStore64, [4GM4FPU02, 4GM4AGU, 4GM4Store], !add(C864GM4Model.StoreLatency, 1)>;
+defm : 4GM4WriteRes<WriteVecMaskedStore64Y, [4GM4FPU02, 4GM4AGU, 4GM4Store], !add(C864GM4Model.StoreLatency, 1)>;
+defm : 4GM4WriteRes<WriteVecMoveToGpr, [4GM4FPU1], 1>;
+defm : 4GM4WriteRes<WriteVecMoveFromGpr, [4GM4FPU1], 1>;
+defm : 4GM4WriteRes<WriteEMMS, [4GM4FPU], 0>;
+
+defm : 4GM4WriteResFPPair<WriteVecShift, [4GM4FPU1], 1>;
+defm : 4GM4WriteResFPPair<WriteVecShiftX, [4GM4FPU1], 1>;
+defm : 4GM4WriteResFPPair<WriteVecShiftY, [4GM4FPU1], 1>;
+defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
+defm : 4GM4WriteResFPPair<WriteVecShiftImm, [4GM4FPU1], 1>;
+defm : 4GM4WriteResFPPair<WriteVecShiftImmX, [4GM4FPU1], 1>;
+defm : 4GM4WriteResFPPair<WriteVecShiftImmY, [4GM4FPU1], 1>;
+defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
+defm : 4GM4WriteResFPPair<WriteVarVecShift, [4GM4FPU0], 3, [2], 1>;
+defm : 4GM4WriteResFPPair<WriteVarVecShiftY, [4GM4FPU0], 3, [2], 1>;
+defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
+defm : 4GM4WriteResFPPair<WriteVecLogic, [4GM4FPU], 1>;
+defm : 4GM4WriteResFPPair<WriteVecLogicX, [4GM4FPU], 1>;
+defm : 4GM4WriteResFPPair<WriteVecLogicY, [4GM4FPU], 1>;
+defm : X86WriteResPairUnsupported<WriteVecLogicZ>;
+defm : 4GM4WriteResFPPair<WriteVecTest, [4GM4FPU01, 4GM4FPU1], 4, [1, 2], 1, 7, 1>;
+defm : 4GM4WriteResFPPair<WriteVecTestY, [4GM4FPU01, 4GM4FPU1], 8, [1, 2], 1, 7, 1>;
+defm : X86WriteResPairUnsupported<WriteVecTestZ>;
+defm : 4GM4WriteResFPPair<WriteVecALU, [4GM4FPU], 1>;
+defm : 4GM4WriteResFPPair<WriteVecALUX, [4GM4FPU], 1>;
+defm : 4GM4WriteResFPPair<WriteVecALUY, [4GM4FPU], 1>;
+defm : X86WriteResPairUnsupported<WriteVecALUZ>;
+defm : 4GM4WriteResFPPair<WriteVecIMul, [4GM4FPU0], 3>;
+defm : 4GM4WriteResFPPair<WriteVecIMulX, [4GM4FPU0], 3>;
+defm : 4GM4WriteResFPPair<WriteVecIMulY, [4GM4FPU0], 3>;
+defm : 4GM4WriteRes<WriteCLMul, [4GM4FPU3], 3>;
+defm : 4GM4WriteRes<WriteCLMulLd, [4GM4AGU, 4GM4Load, 4GM4FPU3], !add(C864GM4Model.VecLoadLatency, 3)>;
+defm : X86WriteResPairUnsupported<WriteVecIMulZ>;
+defm : 4GM4WriteResFPPair<WritePMULLD, [4GM4FPU0], 4, [2]>;
+defm : 4GM4WriteResFPPair<WritePMULLDY, [4GM4FPU0], 4, [2]>;
+defm : X86WriteResPairUnsupported<WritePMULLDZ>;
+defm : 4GM4WriteResFPPair<WriteShuffle, [4GM4FPU01], 1>;
+defm : 4GM4WriteResFPPair<WriteShuffleX, [4GM4FPU01], 1>;
+defm : 4GM4WriteResFPPair<WriteShuffleY, [4GM4FPU01], 1>;
+defm : X86WriteResPairUnsupported<WriteShuffleZ>;
+defm : 4GM4WriteResFPPair<WriteVarShuffle, [4GM4FPU01], 1>;
+defm : 4GM4WriteResFPPair<WriteVarShuffleX,[4GM4FPU01], 1>;
+defm : 4GM4WriteResFPPair<WriteVarShuffleY,[4GM4FPU01], 1>;
+defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
+defm : 4GM4WriteResFPPair<WriteBlend, [4GM4FPU], 1>;
+defm : 4GM4WriteResFPPair<WriteBlendY, [4GM4FPU], 1>;
+defm : X86WriteResPairUnsupported<WriteBlendZ>;
+defm : 4GM4WriteResFPPair<WriteVarBlend, [4GM4FPU0], 1>;
+defm : 4GM4WriteResFPPair<WriteVarBlendY, [4GM4FPU0], 1>;
+defm : X86WriteResPairUnsupported<WriteVarBlendZ>;
+defm : 4GM4WriteResFPPair<WriteShuffle256, [4GM4FPU01], 3>;
+defm : 4GM4WriteResFPPair<WriteVPMOV256, [4GM4FPU01], 1>;
+defm : 4GM4WriteResFPPair<WriteVarShuffle256, [4GM4FPU01], 2>;
+defm : 4GM4WriteResFPPair<WritePSADBW, [4GM4FPU0], 3>;
+defm : 4GM4WriteResFPPair<WritePSADBWX, [4GM4FPU0], 3>;
+defm : 4GM4WriteResFPPair<WritePSADBWY, [4GM4FPU0], 3>;
+defm : X86WriteResPairUnsupported<WritePSADBWZ>;
+defm : 4GM4WriteResFPPair<WriteMPSAD, [4GM4FPU], 4, [8], 1>;
+defm : 4GM4WriteResFPPair<WriteMPSADY, [4GM4FPU], 4, [8], 1>;
+defm : 4GM4WriteResFPPair<WriteMPSADZ, [4GM4FPU], 4, [16], 1>;
+defm : 4GM4WriteResFPPair<WritePHMINPOS, [4GM4FPU0], 3>;
+
+// EXTRQ INSERTQ
+def 4GM4WriteEXTRQ_INSERTQ:SchedWriteRes<[4GM4FPU]> {
+ let Latency = 3;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM4WriteEXTRQ_INSERTQ], (instrs EXTRQ, EXTRQI, INSERTQ, INSERTQI)>;
+
+def 4GM4WriteVPMOVY:SchedWriteRes<[4GM4FPU01]> {
+ let Latency = 3;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM4WriteVPMOVY], (instregex "VPMOV(S|Z)X(BD|BQ|BW|DQ|WD|WQ)Yrr")>;
+
+def 4GM4WriteVPMOVYLd:SchedWriteRes<[4GM4AGU, 4GM4Load, 4GM4FPU01]> {
+ let Latency = !add(C864GM4Model.VecLoadLatency, 4GM4WriteVPMOVY.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM4WriteVPMOVYLd], (instregex "VPMOV(S|Z)X(BD|BQ|BW|DQ|WD|WQ)Yrm")>;
+
+def 4GM4WriteVPS:SchedWriteRes<[4GM4FPU1]> {
+ let Latency = 3;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM4WriteVPS], (instregex "VPS(LL|RA|RL)(D|Q|W)Yrr")>;
+
+def 4GM4WriteVPSLd:SchedWriteRes<[4GM4AGU, 4GM4Load, 4GM4FPU1]> {
+ let Latency = !add(C864GM4Model.VecLoadLatency, 4GM4WriteVPS.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM4WriteVPSLd], (instregex "VPS(LL|RA|RL)(D|Q|W)Yrm")>;
+
+def 4GM4WritePMADDUBSW_PMULHRSW:SchedWriteRes<[4GM4FPU0]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM4WritePMADDUBSW_PMULHRSW], (instregex "(V?)PMADDUBSW(Y)?rr",
+ "(V?)PMULHRSW(Y)?rr")>;
+
+def 4GM4WritePMADDUBSW_PMULHRSWLd:SchedWriteRes<[4GM4AGU, 4GM4Load, 4GM4FPU0]> {
+ let Latency = !add(C864GM4Model.VecLoadLatency, 4GM4WritePMADDUBSW_PMULHRSW.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM4WritePMADDUBSW_PMULHRSWLd], (instregex "(V?)PMADDUBSW(Y)?rm",
+ "(V?)PMULHRSW(Y)?rm")>;
+
+// Vector insert/extract operations.
+defm : 4GM4WriteResFPPair<WriteVecInsert, [4GM4FPU01], 1>;
+defm : 4GM4WriteRes<WriteVecExtract, [4GM4FPU01, 4GM4FPU1], 2, [1, 2], 2>;
+defm : 4GM4WriteRes<WriteVecExtractSt, [4GM4FPU01, 4GM4FPU1, 4GM4AGU, 4GM4Store], 2, [1, 1, 1, 2], 2>;
+
+def 4GM4WritePINSR:SchedWriteRes<[4GM4FPU01]> {
+ let Latency = 2;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM4WritePINSR], (instregex "(V?)PINSR(B|D|Q|W)rri")>;
+
+def 4GM4WritePINSRLd:SchedWriteRes<[4GM4AGU, 4GM4Load, 4GM4FPU01]> {
+ let Latency = !add(C864GM4Model.VecLoadLatency, 4GM4WritePINSR.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM4WritePINSRLd], (instregex "(V?)PINSR(B|D|Q|W)rmi")>;
+
+
+// MOVMSK Instructions.
+defm : 4GM4WriteRes<WriteFMOVMSK, [4GM4FPU1], 1>;
+defm : 4GM4WriteRes<WriteMMXMOVMSK, [4GM4FPU1], 1>;
+defm : 4GM4WriteRes<WriteVecMOVMSK, [4GM4FPU1], 1>;
+defm : 4GM4WriteRes<WriteVecMOVMSKY, [4GM4FPU1], 1>;
+
+// Strings instructions.
+defm : 4GM4WriteResFPPair<WritePCmpIStrM, [4GM4FPU], 7, [25], 3>;
+defm : 4GM4WriteResFPPair<WritePCmpEStrM, [4GM4FPU], 8, [25], 8>;
+defm : 4GM4WriteResFPPair<WritePCmpIStrI, [4GM4FPU], 1, [8], 2>;
+defm : 4GM4WriteResFPPair<WritePCmpEStrI, [4GM4FPU], 2, [13], 8>;
+
+// AES Instructions.
+defm : 4GM4WriteResFPPair<WriteAESDecEnc, [4GM4FPU23], 4>;
+defm : 4GM4WriteResFPPair<WriteAESIMC, [4GM4FPU23], 4>;
+defm : 4GM4WriteResFPPair<WriteAESKeyGen, [4GM4FPU23], 4>;
+
+defm : 4GM4WriteRes<WriteFence, [4GM4AGU]>;
+defm : 4GM4WriteRes<WriteNop, []>;
+
+// SHA Instructions.
+
+def 4GM4WriteSHA1:SchedWriteRes<[4GM4FPU2]> {
+ let Latency = 1;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM4WriteSHA1], (instrs SHA1MSG1rr, SHA1MSG2rr, SHA1NEXTErr)>;
+
+def 4GM4WriteSHA1Ld:SchedWriteRes<[4GM4AGU, 4GM4Load, 4GM4FPU2]> {
+ let Latency = !add(C864GM4Model.VecLoadLatency, 4GM4WriteSHA1.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM4WriteSHA1Ld], (instrs SHA1MSG1rm, SHA1MSG2rm, SHA1NEXTErm)>;
+
+def 4GM4WriteSHA1RNDS4rri:SchedWriteRes<[4GM4FPU2]> {
+ let Latency = 6;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM4WriteSHA1RNDS4rri], (instrs SHA1RNDS4rri)>;
+
+def 4GM4WriteSHA1RNDS4rmi:SchedWriteRes<[4GM4AGU, 4GM4Load, 4GM4FPU2]> {
+ let Latency = !add(C864GM4Model.VecLoadLatency, 4GM4WriteSHA1RNDS4rri.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM4WriteSHA1RNDS4rmi], (instrs SHA1RNDS4rmi)>;
+
+def 4GM4WriteSHA256MSG1rr:SchedWriteRes<[4GM4FPU2]> {
+ let Latency = 2;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM4WriteSHA256MSG1rr], (instrs SHA256MSG1rr)>;
+
+def 4GM4WriteSHA256MSG1rm:SchedWriteRes<[4GM4AGU, 4GM4Load, 4GM4FPU2]> {
+ let Latency = !add(C864GM4Model.VecLoadLatency, 4GM4WriteSHA256MSG1rr.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM4WriteSHA256MSG1rm], (instrs SHA256MSG1rm)>;
+
+def 4GM4WriteSHA256:SchedWriteRes<[4GM4FPU2]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM4WriteSHA256], (instrs SHA256MSG2rr, SHA256RNDS2rr)>;
+
+def 4GM4WriteSHA256Ld:SchedWriteRes<[4GM4AGU, 4GM4Load, 4GM4FPU2]> {
+ let Latency = !add(C864GM4Model.VecLoadLatency, 4GM4WriteSHA256.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM4WriteSHA256Ld], (instrs SHA256MSG2rm, SHA256RNDS2rm)>;
+
+//===----------------------------------------------------------------------===//
+// Zero Cycle Move
+//===----------------------------------------------------------------------===//
+
+def 4GM4WriteZeroLatency : SchedWriteRes<[]> {
+ let Latency = 0;
+ let ReleaseAtCycles = [];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM4WriteZeroLatency], (instrs MOV32rr, MOV32rr_REV,
+ MOV64rr, MOV64rr_REV,
+ MOVSX32rr32)>;
+
+def 4GM4WriteSwapRenameable : SchedWriteRes<[]> {
+ let Latency = 0;
+ let ReleaseAtCycles = [];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM4WriteSwapRenameable], (instrs XCHG32rr, XCHG32ar,
+ XCHG64rr, XCHG64ar)>;
+
+defm : 4GM4WriteRes<WriteXCHG, [4GM4ALU], 1, [2], 1>;
+
+defm : 4GM4WriteRes<WriteFMoveX, [], 0, [], 1>;
+defm : 4GM4WriteRes<WriteFMoveY, [], 0, [], 1>;
+defm : X86WriteResUnsupported<WriteFMoveZ>;
+
+defm : 4GM4WriteRes<WriteVecMove, [], 0, [], 1>;
+defm : 4GM4WriteRes<WriteVecMoveX, [], 0, [], 1>;
+defm : 4GM4WriteRes<WriteVecMoveY, [], 0, [], 1>;
+defm : X86WriteResUnsupported<WriteVecMoveZ>;
+
+def : IsOptimizableRegisterMove<[
+ InstructionEquivalenceClass<[
+ // GPR variants.
+ MOV32rr, MOV32rr_REV,
+ MOV64rr, MOV64rr_REV,
+ MOVSX32rr32,
+ XCHG32rr, XCHG32ar,
+ XCHG64rr, XCHG64ar,
+
+ // MMX variants.
+ // MMX moves are *NOT* eliminated.
+
+ // SSE variants.
+ MOVAPSrr, MOVAPSrr_REV,
+ MOVUPSrr, MOVUPSrr_REV,
+ MOVAPDrr, MOVAPDrr_REV,
+ MOVUPDrr, MOVUPDrr_REV,
+ MOVDQArr, MOVDQArr_REV,
+ MOVDQUrr, MOVDQUrr_REV,
+
+ // AVX variants.
+ VMOVAPSrr, VMOVAPSrr_REV,
+ VMOVUPSrr, VMOVUPSrr_REV,
+ VMOVAPDrr, VMOVAPDrr_REV,
+ VMOVUPDrr, VMOVUPDrr_REV,
+ VMOVDQArr, VMOVDQArr_REV,
+ VMOVDQUrr, VMOVDQUrr_REV,
+
+ // AVX YMM variants.
+ VMOVAPSYrr, VMOVAPSYrr_REV,
+ VMOVUPSYrr, VMOVUPSYrr_REV,
+ VMOVAPDYrr, VMOVAPDYrr_REV,
+ VMOVUPDYrr, VMOVUPDYrr_REV,
+ VMOVDQAYrr, VMOVDQAYrr_REV,
+ VMOVDQUYrr, VMOVDQUYrr_REV,
+ ], TruePred >
+]>;
+
+//===----------------------------------------------------------------------===//
+// Dependency breaking instructions.
+//===----------------------------------------------------------------------===//
+
+def 4GM4WriteZeroIdiom : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM4WriteZeroLatency]>,
+ SchedVar<NoSchedPred, [WriteALU]>
+]>;
+def : InstRW<[4GM4WriteZeroIdiom], (instrs XOR32rr, XOR32rr_REV,
+ XOR64rr, XOR64rr_REV,
+ SUB32rr, SUB32rr_REV,
+ SUB64rr, SUB64rr_REV)>;
+
+def 4GM4WriteZeroIdiomEFLAGS : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<CheckSameRegOperand<0, 1>>, [4GM4WriteZeroLatency]>,
+ SchedVar<NoSchedPred, [WriteALU]>
+]>;
+def : InstRW<[4GM4WriteZeroIdiomEFLAGS], (instrs CMP8rr, CMP8rr_REV,
+ CMP16rr, CMP16rr_REV,
+ CMP32rr, CMP32rr_REV,
+ CMP64rr, CMP64rr_REV)>;
+
+def 4GM4WriteFZeroIdiom : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM4WriteZeroLatency]>,
+ SchedVar<NoSchedPred, [WriteFLogic]>
+]>;
+
+def : InstRW<[4GM4WriteFZeroIdiom], (instrs VXORPSrr, VXORPDrr,
+ VANDNPSrr, VANDNPDrr)>;
+
+def 4GM4WriteFZeroIdiomY : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM4WriteZeroLatency]>,
+ SchedVar<NoSchedPred, [WriteFLogicY]>
+]>;
+def : InstRW<[4GM4WriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr,
+ VANDNPSYrr, VANDNPDYrr)>;
+
+def 4GM4WriteVZeroIdiomLogicX : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM4WriteZeroLatency]>,
+ SchedVar<NoSchedPred, [WriteVecLogicX]>
+]>;
+
+def : InstRW<[4GM4WriteVZeroIdiomLogicX], (instrs VPXORrr, VPANDNrr)>;
+
+def 4GM4WriteVZeroIdiomLogicY : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM4WriteZeroLatency]>,
+ SchedVar<NoSchedPred, [WriteVecLogicY]>
+]>;
+def : InstRW<[4GM4WriteVZeroIdiomLogicY], (instrs VPXORYrr, VPANDNYrr)>;
+
+def 4GM4WriteVZeroIdiomALUX : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM4WriteZeroLatency]>,
+ SchedVar<NoSchedPred, [WriteVecALUX]>
+]>;
+
+
+def : InstRW<[4GM4WriteVZeroIdiomALUX],
+ (instrs VPSUBBrr, VPSUBWrr, VPSUBDrr, VPSUBQrr,
+ VPCMPGTBrr, VPCMPGTWrr, VPCMPGTDrr, VPCMPGTQrr)>;
+
+def 4GM4WriteVZeroIdiomALUY : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM4WriteZeroLatency]>,
+ SchedVar<NoSchedPred, [WriteVecALUY]>
+]>;
+def : InstRW<[4GM4WriteVZeroIdiomALUY],
+ (instrs VPSUBBYrr, VPSUBWYrr, VPSUBDYrr, VPSUBQYrr,
+ VPCMPGTBYrr, VPCMPGTWYrr, VPCMPGTDYrr, VPCMPGTQYrr)>;
+
+def : IsZeroIdiomFunction<[
+ // GPR Zero-idioms.
+ DepBreakingClass<[ XOR32rr, XOR32rr_REV,
+ XOR64rr, XOR64rr_REV,
+ SUB32rr, SUB32rr_REV,
+ SUB64rr, SUB64rr_REV ], ZeroIdiomPredicate>,
+
+ // SSE XMM Zero-idioms.
+ DepBreakingClass<[
+ // fp variants.
+ XORPSrr, XORPDrr,
+ ANDNPSrr, ANDNPDrr,
+
+ // int variants.
+ PXORrr,
+ PANDNrr,
+ PSUBBrr, PSUBWrr, PSUBDrr, PSUBQrr,
+ PSUBSBrr, PSUBSWrr,
+ PSUBUSBrr, PSUBUSWrr,
+ PCMPGTBrr, PCMPGTWrr, PCMPGTDrr, PCMPGTQrr
+ ], ZeroIdiomPredicate>,
+
+ // AVX XMM Zero-idioms.
+ DepBreakingClass<[
+ // fp variants.
+ VXORPSrr, VXORPDrr,
+ VANDNPSrr, VANDNPDrr,
+
+ // int variants.
+ VPXORrr,
+ VPANDNrr,
+ VPSUBBrr, VPSUBWrr, VPSUBDrr, VPSUBQrr,
+ VPSUBSBrr, VPSUBSWrr,
+ VPSUBUSBrr, VPSUBUSWrr,
+ VPCMPGTBrr, VPCMPGTWrr, VPCMPGTDrr, VPCMPGTQrr,
+ ], ZeroIdiomPredicate>,
+
+ // AVX YMM Zero-idioms.
+ DepBreakingClass<[
+ // fp variants.
+ VXORPSYrr, VXORPDYrr,
+ VANDNPSYrr, VANDNPDYrr,
+
+ // int variants.
+ VPXORYrr,
+ VPANDNYrr,
+ VPSUBBYrr, VPSUBWYrr, VPSUBDYrr, VPSUBQYrr,
+ VPSUBSBYrr, VPSUBSWYrr,
+ VPSUBUSBYrr, VPSUBUSWYrr,
+ VPCMPGTBYrr, VPCMPGTWYrr, VPCMPGTDYrr, VPCMPGTQYrr
+ ], ZeroIdiomPredicate>,
+]>;
+
+def : IsDepBreakingFunction<[
+ // GPR
+ DepBreakingClass<[ SBB32rr, SBB32rr_REV,
+ SBB64rr, SBB64rr_REV ], ZeroIdiomPredicate>,
+ DepBreakingClass<[ CMP8rr, CMP8rr_REV,
+ CMP16rr, CMP16rr_REV,
+ CMP32rr, CMP32rr_REV,
+ CMP64rr, CMP64rr_REV ], CheckSameRegOperand<0, 1> >,
+
+ // MMX
+ DepBreakingClass<[
+ MMX_PCMPEQBrr, MMX_PCMPEQWrr, MMX_PCMPEQDrr
+ ], ZeroIdiomPredicate>,
+
+ // SSE
+ DepBreakingClass<[
+ PCMPEQBrr, PCMPEQWrr, PCMPEQDrr, PCMPEQQrr
+ ], ZeroIdiomPredicate>,
+
+ // AVX XMM
+ DepBreakingClass<[
+ VPCMPEQBrr, VPCMPEQWrr, VPCMPEQDrr, VPCMPEQQrr
+ ], ZeroIdiomPredicate>,
+
+ // AVX YMM
+ DepBreakingClass<[
+ VPCMPEQBYrr, VPCMPEQWYrr, VPCMPEQDYrr, VPCMPEQQYrr
+ ], ZeroIdiomPredicate>,
+]>;
+
+} // SchedModel
\ No newline at end of file
diff --git a/llvm/lib/Target/X86/X86ScheduleC864GM7.td b/llvm/lib/Target/X86/X86ScheduleC864GM7.td
new file mode 100644
index 0000000000000..4d6270373cb62
--- /dev/null
+++ b/llvm/lib/Target/X86/X86ScheduleC864GM7.td
@@ -0,0 +1,3721 @@
+//=- X86ScheduleC864GM7.td - X86 C86-4G-M7 Scheduling --------*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the machine model for C86-4G-M7 to support instruction
+// scheduling and other instruction cost heuristics.
+//
+//===----------------------------------------------------------------------===//
+
+def C864GM7Model : SchedMachineModel {
+ let IssueWidth = 4;
+ let MicroOpBufferSize = 256;
+ // The maximum dispatch is 6 ops/cycle, and a mispredict cost is 16 cycle from
+ // the op-cache, so the loop buffer is limited to 6*16 = 96.
+ let LoopMicroOpBufferSize = 96;
+ // The common case of branch misprediction penalty is 16 cycles.
+ let MispredictPenalty = 16;
+
+ let LoadLatency = 4;
+ int VecLoadLatency = 7;
+ int StoreLatency = 1;
+ let HighLatency = 25;
+
+ let PostRAScheduler = 1;
+
+ let CompleteModel = 1;
+}
+
+let SchedModel = C864GM7Model in {
+
+//===----------------------------------------------------------------------===//
+// Integer Execution Unit
+//===----------------------------------------------------------------------===//
+
+// The C864GM7 has 4 ALUs.
+def 4GM7ALU0 : ProcResource<1>;
+def 4GM7ALU1 : ProcResource<1>;
+def 4GM7ALU2 : ProcResource<1>;
+def 4GM7ALU3 : ProcResource<1>;
+
+def 4GM7ALU : ProcResGroup<[4GM7ALU0, 4GM7ALU1, 4GM7ALU2, 4GM7ALU3]>;
+def 4GM7ALU12 : ProcResGroup<[4GM7ALU1, 4GM7ALU2]>;
+def 4GM7ALU03 : ProcResGroup<[4GM7ALU0, 4GM7ALU3]>;
+
+// BRU0 on ALU0.
+defvar 4GM7BRU0 = 4GM7ALU0;
+// BRU1 is a separate branch execution unit.
+def 4GM7BRU1 : ProcResource<1>;
+
+def 4GM7BRU : ProcResGroup<[4GM7BRU0, 4GM7BRU1]>;
+
+// The C864GM7 has 3 AGUs.
+def 4GM7AGU0 : ProcResource<1>;
+def 4GM7AGU1 : ProcResource<1>;
+def 4GM7AGU2 : ProcResource<1>;
+
+def 4GM7AGU : ProcResGroup<[4GM7AGU0, 4GM7AGU1, 4GM7AGU2]>;
+
+// 96 Entry (4x24 entries) integer Scheduler.
+def 4GM7Int : ProcResGroup<[4GM7ALU0, 4GM7AGU0, 4GM7BRU0,
+ 4GM7ALU1, 4GM7AGU1,
+ 4GM7ALU2, 4GM7AGU2,
+ 4GM7ALU3, 4GM7BRU1]> {
+ let BufferSize = 96;
+}
+
+// The integer physical register file consists of 224 registers.
+def 4GM7IntegerPRF : RegisterFile<224,
+ [GR64, CCR],
+ [1, 1],
+ [1, 0],
+ 6, // Max moves that can be eliminated per cycle.
+ 0>; // Restrict move elimination to zero regs.
+
+//===----------------------------------------------------------------------===//
+// Floating-Point Unit
+//===----------------------------------------------------------------------===//
+
+// The C864GM7 has 4 FPUs.
+def 4GM7FPU0 : ProcResource<1>;
+def 4GM7FPU1 : ProcResource<1>;
+def 4GM7FPU2 : ProcResource<1>;
+def 4GM7FPU3 : ProcResource<1>;
+
+def 4GM7FPU013 : ProcResGroup<[4GM7FPU0, 4GM7FPU1, 4GM7FPU3]>;
+def 4GM7FPU01 : ProcResGroup<[4GM7FPU0, 4GM7FPU1]>;
+def 4GM7FPU12 : ProcResGroup<[4GM7FPU1, 4GM7FPU2]>;
+def 4GM7FPU13 : ProcResGroup<[4GM7FPU1, 4GM7FPU3]>;
+def 4GM7FPU23 : ProcResGroup<[4GM7FPU2, 4GM7FPU3]>;
+def 4GM7FPU02 : ProcResGroup<[4GM7FPU0, 4GM7FPU2]>;
+def 4GM7FPU03 : ProcResGroup<[4GM7FPU0, 4GM7FPU3]>;
+
+// 48 Entry (4x12 entries) floating-point Scheduler.
+def 4GM7FPU : ProcResGroup<[4GM7FPU0, 4GM7FPU1, 4GM7FPU2, 4GM7FPU3]> {
+ let BufferSize = 48;
+}
+
+// The floating point physical register file consists of 256 bits x 208 registers.
+def 4GM7FpuPRF : RegisterFile<208,
+ [VR64, VR128, VR256, VR512],
+ [1, 1, 1, 2],
+ [0, 1, 1, 0],
+ 6, // Max moves that can be eliminated per cycle.
+ 0>; // Restrict move elimination to zero regs.
+
+
+//===----------------------------------------------------------------------===//
+// Load-Store Unit
+//===----------------------------------------------------------------------===//
+
+// Load/Store Units and Memory Queues
+// The C864GM7 has 4 LS Units.
+def 4GM7LSU : ProcResource<4>;
+
+// The three of LSU can be loads.
+let Super = 4GM7LSU in
+def 4GM7Load : ProcResource<3> {
+ // The LDQ is 54.
+ let BufferSize = 54;
+}
+def 4GM7LoadQueue : LoadQueue<4GM7Load>;
+
+// All four of LSU can be loads.
+let Super = 4GM7LSU in
+def 4GM7Store : ProcResource<4> {
+ // The STQ is 52.
+ let BufferSize = 52;
+}
+def 4GM7StoreQueue : StoreQueue<4GM7Store>;
+
+def : ReadAdvance<ReadAfterLd, C864GM7Model.LoadLatency>;
+def : ReadAdvance<ReadAfterVecLd, C864GM7Model.VecLoadLatency>;
+def : ReadAdvance<ReadAfterVecXLd, C864GM7Model.VecLoadLatency>;
+def : ReadAdvance<ReadAfterVecYLd, C864GM7Model.VecLoadLatency>;
+def : ReadAdvance<ReadInt2Fpu, 0>;
+
+
+//===----------------------------------------------------------------------===//
+// Retire Control Unit
+//===----------------------------------------------------------------------===//
+def 4GM7RCU : RetireControlUnit<C864GM7Model.MicroOpBufferSize, 8>;
+
+//===----------------------------------------------------------------------===//
+// Basic helper classes.
+//===----------------------------------------------------------------------===//
+
+// Many SchedWrites are defined in pairs with and without a folded load.
+// Instructions with folded loads are usually micro-fused, so they only appear
+// as two micro-ops when dispatched by the schedulers.
+// This multiclass defines the resource usage for variants with and without
+// folded loads.
+
+
+multiclass __4GM7WriteRes<SchedWrite SchedRW, list<ProcResourceKind> ExePorts,
+ int Lat = 1, list<int> Res = [], int UOps = 1> {
+ def : WriteRes<SchedRW, ExePorts> {
+ let Latency = Lat;
+ let ReleaseAtCycles = Res;
+ let NumMicroOps = UOps;
+ }
+}
+
+multiclass __4GM7WriteResPair<X86FoldableSchedWrite SchedRW,
+ list<ProcResourceKind> ExePorts, int Lat,
+ list<int> Res, int UOps, int LoadLat, int LoadUOps,
+ ProcResourceKind AGU, int LoadRes> {
+ defm : __4GM7WriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
+
+ defm : __4GM7WriteRes<SchedRW.Folded,
+ !listconcat([AGU, 4GM7Load], ExePorts),
+ !add(LoadLat, Lat),
+ !if(!and(!empty(Res), !eq(LoadRes, 1)),
+ [],
+ !listconcat([1, LoadRes],
+ !if(!empty(Res),
+ !listsplat(1, !size(ExePorts)),
+ Res))),
+ !add(UOps, LoadUOps)>;
+}
+
+// For classes without folded loads.
+multiclass 4GM7WriteRes<SchedWrite SchedRW,
+ list<ProcResourceKind> ExePorts, int Lat = 1,
+ list<int> Res = [], int UOps = 1> {
+ defm : __4GM7WriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
+}
+
+// For classes with folded loads.
+multiclass 4GM7WriteResIntPair<X86FoldableSchedWrite SchedRW,
+ list<ProcResourceKind> ExePorts, int Lat = 1,
+ list<int> Res = [], int UOps = 1,
+ int LoadUOps = 0, int LoadRes = 1> {
+ defm : __4GM7WriteResPair<SchedRW, ExePorts, Lat, Res, UOps,
+ C864GM7Model.LoadLatency,
+ LoadUOps, 4GM7AGU, LoadRes>;
+}
+
+multiclass 4GM7WriteResFPPair<X86FoldableSchedWrite SchedRW,
+ list<ProcResourceKind> ExePorts, int Lat = 1,
+ list<int> Res = [], int UOps = 1,
+ int LoadUOps = 0, int LoadRes = 1> {
+ defm : __4GM7WriteResPair<SchedRW, ExePorts, Lat, Res, UOps,
+ C864GM7Model.VecLoadLatency,
+ LoadUOps, 4GM7AGU, LoadRes>;
+}
+
+// Microcoded Instructions
+def 4GM7WriteMicrocoded : SchedWriteRes<[]> {
+ let Latency = 100;
+}
+
+def : SchedAlias<WriteMicrocoded, 4GM7WriteMicrocoded>;
+def : SchedAlias<WriteSystem, 4GM7WriteMicrocoded>;
+def : SchedAlias<WriteFCMOV, 4GM7WriteMicrocoded>;
+def : SchedAlias<WriteLDMXCSR, 4GM7WriteMicrocoded>;
+def : SchedAlias<WriteSTMXCSR, 4GM7WriteMicrocoded>;
+
+// Integer Instructions
+
+defm : 4GM7WriteRes<WriteRMW, [4GM7AGU, 4GM7Store], C864GM7Model.StoreLatency, [1, 1], 0>;
+
+defm : 4GM7WriteRes<WriteStore, [4GM7AGU, 4GM7Store], C864GM7Model.StoreLatency, [1, 2], 1>;
+defm : 4GM7WriteRes<WriteStoreNT, [4GM7AGU, 4GM7Store], C864GM7Model.StoreLatency, [1, 2], 1>;
+defm : 4GM7WriteRes<WriteLoad, [4GM7AGU, 4GM7Load], !add(C864GM7Model.LoadLatency, 1), [1, 1], 1>;
+defm : 4GM7WriteRes<WriteMove, [4GM7ALU], 1, [4], 1>;
+
+def : InstRW<[WriteMove], (instrs COPY, MOVSX16rr16, MOVSX16rr32,
+ MOVZX16rr16, MOVSX16rr8, MOVZX16rr8)>;
+
+defm : 4GM7WriteRes<WriteVecMaskedGatherWriteback, [], !add(1, C864GM7Model.VecLoadLatency)>;
+
+defm : 4GM7WriteRes<WriteZero, [], 0, [], 1>;
+defm : 4GM7WriteRes<WriteLEA, [4GM7AGU]>;
+defm : 4GM7WriteResIntPair<WriteALU, [4GM7ALU], 1>;
+defm : 4GM7WriteResIntPair<WriteADC, [4GM7ALU], 1>;
+
+// This write is used for slow LEA instructions.
+def 4GM7Write3OpsLEA : SchedWriteRes<[4GM7ALU]> {
+ let Latency = 2;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 2;
+}
+// a slow LEA is either a 3Ops LEA (base, index, offset),
+// or an LEA with a `Scale` value different than 1.
+def 4GM7SlowLEAPredicate : MCSchedPredicate<
+ CheckAny<[
+ IsThreeOperandsLEAFn,
+ CheckAll<[
+ CheckIsImmOperand<2>,
+ CheckNot<CheckImmOperand<2, 1>>
+ ]>
+ ]>
+>;
+
+def 4GM7WriteLEA : SchedWriteVariant<[
+ SchedVar<4GM7SlowLEAPredicate, [4GM7Write3OpsLEA]>,
+ SchedVar<NoSchedPred, [WriteLEA]>
+]>;
+
+def : InstRW<[4GM7WriteLEA], (instrs LEA64r, LEA64_32r)>;
+
+// MUL IMUL MULX
+defm : 4GM7WriteResIntPair<WriteIMul8, [4GM7ALU1], 3, [3], 1>;
+defm : 4GM7WriteResIntPair<WriteIMul16, [4GM7ALU1], 3, [3], 1>;
+defm : 4GM7WriteResIntPair<WriteIMul16Imm, [4GM7ALU1], 4, [3], 2>;
+defm : 4GM7WriteResIntPair<WriteIMul16Reg, [4GM7ALU1], 3>;
+defm : 4GM7WriteResIntPair<WriteIMul32, [4GM7ALU1], 3, [3], 1>;
+defm : 4GM7WriteResIntPair<WriteIMul32Imm, [4GM7ALU1], 3, [3], 2>;
+defm : 4GM7WriteResIntPair<WriteIMul32Reg, [4GM7ALU1], 3>;
+defm : 4GM7WriteResIntPair<WriteIMul64, [4GM7ALU1], 3, [4], 1>;
+defm : 4GM7WriteResIntPair<WriteIMul64Imm, [4GM7ALU1], 3, [4], 2>;
+defm : 4GM7WriteResIntPair<WriteIMul64Reg, [4GM7ALU1], 3>;
+
+defm : 4GM7WriteResIntPair<WriteMULX32, [4GM7ALU1], 3, [2], 2>;
+defm : 4GM7WriteResIntPair<WriteMULX64, [4GM7ALU1], 4, [2], 2>;
+defm : 4GM7WriteRes<WriteIMulHLd, [4GM7ALU1], !add(3, C864GM7Model.LoadLatency), [], 0>;
+defm : 4GM7WriteRes<WriteIMulH, [4GM7ALU1], 3, [], 0>;
+
+// IDIV
+defm : 4GM7WriteResIntPair<WriteDiv8, [4GM7ALU3], 9, [4], 2>;
+defm : 4GM7WriteResIntPair<WriteDiv16, [4GM7ALU3], 10, [4], 2>;
+defm : 4GM7WriteResIntPair<WriteDiv32, [4GM7ALU3], 12, [7], 2>;
+defm : 4GM7WriteResIntPair<WriteDiv64, [4GM7ALU3], 18, [10], 2>;
+defm : 4GM7WriteResIntPair<WriteIDiv8, [4GM7ALU3], 9, [4], 2>;
+defm : 4GM7WriteResIntPair<WriteIDiv16, [4GM7ALU3], 10, [4], 2>;
+defm : 4GM7WriteResIntPair<WriteIDiv32, [4GM7ALU3], 12, [7], 2>;
+defm : 4GM7WriteResIntPair<WriteIDiv64, [4GM7ALU3], 18, [10], 2>;
+
+defm : 4GM7WriteRes<WriteBSWAP32, [4GM7ALU], 1, [1], 1>;
+defm : 4GM7WriteRes<WriteBSWAP64, [4GM7ALU], 1, [1], 1>;
+defm : 4GM7WriteRes<WriteCMPXCHG, [4GM7ALU], 3, [12], 5>;
+defm : 4GM7WriteRes<WriteCMPXCHGRMW,[4GM7ALU], 3, [12], 6>;
+
+def 4GM7WriteXADD : SchedWriteRes<[4GM7ALU]> {
+ let Latency = 1;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteXADD], (instrs XADD8rr, XADD16rr, XADD32rr, XADD64rr)>;
+
+def 4GM7WriteXADDLd : SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7ALU]> {
+ let Latency = !add(C864GM7Model.LoadLatency, 4GM7WriteXADD.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteXADDLd], (instrs XADD8rm, XADD16rm, XADD32rm, XADD64rm)>;
+
+def 4GM7WriteCMPXCHG8rr : SchedWriteRes<[4GM7ALU]> {
+ let Latency = 3;
+ let ReleaseAtCycles = [12];
+ let NumMicroOps = 3;
+}
+def : InstRW<[4GM7WriteCMPXCHG8rr], (instrs CMPXCHG8rr)>;
+
+def 4GM7WriteCMPXCHG8mr : SchedWriteRes<[4GM7ALU, 4GM7AGU, 4GM7Store]> {
+ let Latency = !add(4GM7WriteCMPXCHG8rr.Latency, C864GM7Model.StoreLatency);
+ let ReleaseAtCycles = [12, 1, 1];
+ let NumMicroOps = 5;
+}
+def : InstRW<[4GM7WriteCMPXCHG8mr], (instrs CMPXCHG8rm, LCMPXCHG8)>;
+
+def 4GM7WriteXCHG : SchedWriteRes<[4GM7ALU]> {
+ let Latency = 1;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteXCHG], (instrs XCHG8rr, XCHG16ar, XCHG16rr)>;
+
+def 4GM7WriteXCHGLd : SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7ALU]> {
+ let Latency = !add(C864GM7Model.LoadLatency, 4GM7WriteXCHG.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteXCHGLd], (instrs XCHG8rm, XCHG16rm)>;
+
+defm : 4GM7WriteResIntPair<WriteShift, [4GM7ALU], 1>;
+defm : 4GM7WriteResIntPair<WriteShiftCL, [4GM7ALU], 1>;
+defm : 4GM7WriteResIntPair<WriteRotate, [4GM7ALU], 1>;
+defm : 4GM7WriteResIntPair<WriteRotateCL, [4GM7ALU], 1>;
+
+def 4GM7WriteRCR:SchedWriteRes<[4GM7ALU]> {
+ let Latency = 3;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteRCR], (instregex "RCR(8|16|32|64)rCL")>;
+
+def 4GM7WriteRCRLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7ALU]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteRCR.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteRCRLd], (instregex "RCR(8|16|32|64)mCL")>;
+
+def 4GM7WriteRCL:SchedWriteRes<[4GM7ALU]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteRCL], (instregex "RCL(8|16|32|64)rCL")>;
+
+def 4GM7WriteRCLLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7ALU]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteRCL.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteRCLLd], (instregex "RCL(8|16|32|64)mCL")>;
+
+defm : 4GM7WriteRes<WriteSHDrri, [4GM7ALU], 3, [4], 6>;
+defm : 4GM7WriteRes<WriteSHDrrcl, [4GM7ALU], 3, [4], 7>;
+defm : 4GM7WriteRes<WriteSHDmri, [4GM7ALU, 4GM7AGU, 4GM7Store], !add(3, C864GM7Model.StoreLatency), [4, 1, 1], 8>;
+defm : 4GM7WriteRes<WriteSHDmrcl, [4GM7ALU, 4GM7AGU, 4GM7Store], !add(3, C864GM7Model.StoreLatency), [4, 1, 1], 8>;
+
+defm : 4GM7WriteResIntPair<WriteJump, [4GM7ALU], 1>;
+defm : 4GM7WriteResIntPair<WriteCRC32, [4GM7ALU], 3, [12], 3>;
+
+defm : 4GM7WriteResIntPair<WriteCMOV, [4GM7ALU], 1>;
+defm : 4GM7WriteRes<WriteSETCC, [4GM7ALU], 1, [1], 1>;
+defm : 4GM7WriteRes<WriteSETCCStore, [4GM7ALU, 4GM7AGU, 4GM7Store], 1, [2, 1, 1], 2>;
+defm : 4GM7WriteRes<WriteLAHFSAHF, [4GM7ALU], 2, [2], 4>;
+
+defm : 4GM7WriteRes<WriteBitTest, [4GM7ALU], 1, [1], 1>;
+defm : 4GM7WriteRes<WriteBitTestImmLd, [4GM7AGU, 4GM7Load, 4GM7ALU], !add(C864GM7Model.LoadLatency, 1), [1,1,1], 2>;
+defm : 4GM7WriteRes<WriteBitTestRegLd, [4GM7AGU, 4GM7Load, 4GM7ALU], !add(C864GM7Model.LoadLatency, 1), [1,1,1], 6>;
+defm : 4GM7WriteRes<WriteBitTestSet, [4GM7ALU], 2, [1], 2>;
+defm : 4GM7WriteRes<WriteBitTestSetImmLd, [4GM7AGU, 4GM7Load, 4GM7ALU], !add(C864GM7Model.LoadLatency, 2), [1, 1, 1], 4>;
+defm : 4GM7WriteRes<WriteBitTestSetRegLd, [4GM7AGU, 4GM7Load, 4GM7ALU], !add(C864GM7Model.LoadLatency, 2), [1, 1, 1], 8>;
+
+// Bit counts.
+defm : 4GM7WriteResIntPair<WriteBSF, [4GM7ALU], 3, [12], 6, -2>;
+defm : 4GM7WriteResIntPair<WriteBSR, [4GM7ALU], 4, [16], 6, -3>;
+defm : 4GM7WriteResIntPair<WriteLZCNT, [4GM7ALU], 1>;
+defm : 4GM7WriteResIntPair<WriteTZCNT, [4GM7ALU], 2, [2], 2>;
+defm : 4GM7WriteResIntPair<WritePOPCNT, [4GM7ALU], 1>;
+
+// PLZCNT
+def 4GM7WritePLZCNTXY:SchedWriteRes<[4GM7FPU]> {
+ let Latency = 1;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WritePLZCNTXY], (instregex "VPLZCNT(D|Q)(Z128|Z256)rr(k|kz)")>;
+
+def 4GM7WritePLZCNTXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WritePLZCNTXY.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WritePLZCNTXYLd], (instregex "VPLZCNT(D|Q)(Z128|Z256)rm(k|kz)")>;
+
+def 4GM7WritePLZCNTZ:SchedWriteRes<[4GM7FPU]> {
+ let Latency = 1;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WritePLZCNTZ], (instregex "VPLZCNT(D|Q)Zrr(k|kz)")>;
+
+def 4GM7WritePLZCNTZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WritePLZCNTZ.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WritePLZCNTZLd], (instregex "VPLZCNT(D|Q)Zrm(k|kz)")>;
+
+// BMI1 BEXTR, BMI2 BZHI
+defm : 4GM7WriteResIntPair<WriteBEXTR, [4GM7ALU], 1, [1], 1>;
+defm : 4GM7WriteResIntPair<WriteBLS, [4GM7ALU], 2, [2], 3>;
+defm : 4GM7WriteResIntPair<WriteBZHI, [4GM7ALU], 1>;
+
+
+// Floating Point Instructions
+defm : 4GM7WriteRes<WriteFLD0, [4GM7AGU, 4GM7Load, 4GM7FPU1], !add(C864GM7Model.LoadLatency, 4), [1, 1, 1], 1>;
+defm : 4GM7WriteRes<WriteFLD1, [4GM7AGU, 4GM7Load, 4GM7FPU1], !add(C864GM7Model.LoadLatency, 4), [1, 1, 1], 1>;
+defm : 4GM7WriteRes<WriteFLDC, [4GM7AGU, 4GM7Load, 4GM7FPU1], !add(C864GM7Model.LoadLatency, 4), [1, 1, 1], 1>;
+defm : 4GM7WriteRes<WriteFLoad, [4GM7AGU, 4GM7Load], !add(C864GM7Model.VecLoadLatency, 1)>;
+defm : 4GM7WriteRes<WriteFLoadX, [4GM7AGU, 4GM7Load], !add(C864GM7Model.VecLoadLatency, 1)>;
+defm : 4GM7WriteRes<WriteFLoadY, [4GM7AGU, 4GM7Load], !add(C864GM7Model.VecLoadLatency, 1)>;
+defm : 4GM7WriteRes<WriteFMaskedLoad, [4GM7AGU, 4GM7Load, 4GM7FPU01], !add(C864GM7Model.VecLoadLatency, 1)>;
+defm : 4GM7WriteRes<WriteFMaskedLoadY, [4GM7AGU, 4GM7Load, 4GM7FPU01], !add(C864GM7Model.VecLoadLatency, 1), [1, 1, 1], 2>;
+
+defm : 4GM7WriteRes<WriteFStore, [4GM7AGU, 4GM7Store], C864GM7Model.StoreLatency>;
+defm : 4GM7WriteRes<WriteFStoreX, [4GM7AGU, 4GM7Store], C864GM7Model.StoreLatency>;
+defm : 4GM7WriteRes<WriteFStoreY, [4GM7AGU, 4GM7Store], C864GM7Model.StoreLatency>;
+defm : 4GM7WriteRes<WriteFStoreNT, [4GM7FPU1, 4GM7AGU, 4GM7Store], !add(1, C864GM7Model.StoreLatency)>;
+defm : 4GM7WriteRes<WriteFStoreNTX, [4GM7FPU1, 4GM7AGU, 4GM7Store], !add(1, C864GM7Model.StoreLatency)>;
+defm : 4GM7WriteRes<WriteFStoreNTY, [4GM7FPU1, 4GM7AGU, 4GM7Store], !add(1, C864GM7Model.StoreLatency)>;
+defm : 4GM7WriteRes<WriteFMaskedStore32, [4GM7FPU01, 4GM7AGU, 4GM7Store], C864GM7Model.StoreLatency>;
+defm : 4GM7WriteRes<WriteFMaskedStore32Y, [4GM7FPU01, 4GM7AGU, 4GM7Store], C864GM7Model.StoreLatency>;
+defm : 4GM7WriteRes<WriteFMaskedStore64, [4GM7FPU01, 4GM7AGU, 4GM7Store], C864GM7Model.StoreLatency>;
+defm : 4GM7WriteRes<WriteFMaskedStore64Y, [4GM7FPU01, 4GM7AGU, 4GM7Store], C864GM7Model.StoreLatency>;
+
+defm : 4GM7WriteResFPPair<WriteFAdd, [4GM7FPU13], 3>;
+defm : 4GM7WriteResFPPair<WriteFAddX, [4GM7FPU13], 3>;
+defm : 4GM7WriteResFPPair<WriteFAddY, [4GM7FPU13], 3>;
+defm : 4GM7WriteResFPPair<WriteFAddZ, [4GM7FPU13], 3, [2], 1>;
+defm : 4GM7WriteResFPPair<WriteFAdd64, [4GM7FPU13], 3>;
+defm : 4GM7WriteResFPPair<WriteFAdd64X, [4GM7FPU13], 3>;
+defm : 4GM7WriteResFPPair<WriteFAdd64Y, [4GM7FPU13], 3>;
+defm : 4GM7WriteResFPPair<WriteFAdd64Z, [4GM7FPU13], 3, [2], 1>;
+defm : 4GM7WriteResFPPair<WriteFHAdd, [4GM7FPU13], 7, [8], 4, 3>;
+defm : 4GM7WriteResFPPair<WriteFHAddY, [4GM7FPU13], 7, [8], 4, 3>;
+defm : X86WriteResPairUnsupported<WriteFHAddZ>;
+defm : 4GM7WriteResFPPair<WritePHAdd, [4GM7FPU13], 3, [8], 4, 3>;
+defm : 4GM7WriteResFPPair<WritePHAddX, [4GM7FPU13], 3, [8], 4, 3>;
+defm : 4GM7WriteResFPPair<WritePHAddY, [4GM7FPU13], 3, [8], 4, 3>;
+defm : X86WriteResPairUnsupported<WritePHAddZ>;
+defm : 4GM7WriteResFPPair<WriteFMul, [4GM7FPU02], 3>;
+defm : 4GM7WriteResFPPair<WriteFMulX, [4GM7FPU02], 3>;
+defm : 4GM7WriteResFPPair<WriteFMulY, [4GM7FPU02], 3>;
+defm : 4GM7WriteResFPPair<WriteFMulZ, [4GM7FPU02], 3, [2], 1>;
+defm : 4GM7WriteResFPPair<WriteFMul64, [4GM7FPU02], 3>;
+defm : 4GM7WriteResFPPair<WriteFMul64X, [4GM7FPU02], 3>;
+defm : 4GM7WriteResFPPair<WriteFMul64Y, [4GM7FPU02], 3>;
+defm : 4GM7WriteResFPPair<WriteFMul64Z, [4GM7FPU02], 3, [2], 1>;
+defm : 4GM7WriteResFPPair<WriteFMA, [4GM7FPU02], 4>;
+defm : 4GM7WriteResFPPair<WriteFMAX, [4GM7FPU02], 4>;
+defm : 4GM7WriteResFPPair<WriteFMAY, [4GM7FPU02], 4>;
+defm : 4GM7WriteResFPPair<WriteFMAZ, [4GM7FPU02], 4, [2], 2>;
+defm : 4GM7WriteResFPPair<WriteFRcp, [4GM7FPU02], 5, [2], 1>;
+defm : 4GM7WriteResFPPair<WriteFRcpX, [4GM7FPU02], 5, [2], 1>;
+defm : 4GM7WriteResFPPair<WriteFRcpY, [4GM7FPU02], 5, [2], 1>;
+defm : 4GM7WriteResFPPair<WriteFRcpZ, [4GM7FPU02], 5, [2], 1>;
+defm : 4GM7WriteResFPPair<WriteFRsqrt, [4GM7FPU02], 5, [2], 1>;
+defm : 4GM7WriteResFPPair<WriteFRsqrtX, [4GM7FPU02], 5, [2], 1>;
+defm : 4GM7WriteResFPPair<WriteFRsqrtY, [4GM7FPU02], 5, [2], 1>;
+defm : 4GM7WriteResFPPair<WriteFRsqrtZ, [4GM7FPU02], 5, [2], 1>;
+defm : 4GM7WriteResFPPair<WriteFSqrt, [4GM7FPU13], 8, [13]>;
+defm : 4GM7WriteResFPPair<WriteFSqrtX, [4GM7FPU13], 8, [13]>;
+defm : 4GM7WriteResFPPair<WriteFSqrtY, [4GM7FPU13], 8, [13]>;
+defm : 4GM7WriteResFPPair<WriteFSqrtZ, [4GM7FPU13], 16, [13]>;
+defm : 4GM7WriteResFPPair<WriteFSqrt64, [4GM7FPU13], 8, [19]>;
+defm : 4GM7WriteResFPPair<WriteFSqrt64X, [4GM7FPU13], 8, [19]>;
+defm : 4GM7WriteResFPPair<WriteFSqrt64Y, [4GM7FPU13], 8, [19]>;
+defm : 4GM7WriteResFPPair<WriteFSqrt64Z, [4GM7FPU13], 16, [19]>;
+defm : 4GM7WriteResFPPair<WriteFSqrt80, [4GM7FPU13], 22, [23]>;
+defm : 4GM7WriteResFPPair<WriteFDiv, [4GM7FPU13], 10, [9], 1>;
+defm : 4GM7WriteResFPPair<WriteFDivX, [4GM7FPU13], 10, [9], 1>;
+defm : 4GM7WriteResFPPair<WriteFDivY, [4GM7FPU13], 10, [9], 1>;
+defm : 4GM7WriteResFPPair<WriteFDivZ, [4GM7FPU13], 18, [18], 2>;
+defm : 4GM7WriteResFPPair<WriteFDiv64, [4GM7FPU13], 8, [12], 1>;
+defm : 4GM7WriteResFPPair<WriteFDiv64X, [4GM7FPU13], 8, [12], 1>;
+defm : 4GM7WriteResFPPair<WriteFDiv64Y, [4GM7FPU13], 8, [12], 1>;
+defm : 4GM7WriteResFPPair<WriteFDiv64Z, [4GM7FPU13], 16, [24], 2>;
+defm : 4GM7WriteResFPPair<WriteDPPD, [4GM7FPU13], 9, [8], 4>;
+defm : 4GM7WriteResFPPair<WriteDPPS, [4GM7FPU13], 14, [8], 8>;
+defm : 4GM7WriteResFPPair<WriteDPPSY, [4GM7FPU13], 14, [8], 8>;
+
+// PMADD
+def 4GM7WriteVPMADDXYrrk:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPMADDXYrrk], (instrs VPMADDWDZ128rrk, VPMADDWDZ256rrk)>;
+
+def 4GM7WriteVPMADDXYrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPMADDXYrrk.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPMADDXYrmk], (instrs VPMADDWDZ128rmk, VPMADDWDZ256rmk)>;
+
+def 4GM7WriteVPMADDZrrk:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPMADDZrrk], (instrs VPMADDWDZrrk)>;
+
+def 4GM7WriteVPMADDZrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPMADDZrrk.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPMADDZrmk], (instrs VPMADDWDZrmk)>;
+
+
+// PMADD52
+def 4GM7WriteVPMADD52XY:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPMADD52XY], (instregex "VPMADD52(L|H)UQ(Z128|Z256)(r|rkz)$")>;
+
+def 4GM7WriteVPMADD52XYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPMADD52XY.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPMADD52XYLd], (instregex "VPMADD52(L|H)UQ(Z128|Z256)(m|mkz)$")>;
+
+def 4GM7WriteVPMADD52XYrk:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 5;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPMADD52XYrk], (instregex "VPMADD52(L|H)UQ(Z128|Z256)rk$")>;
+
+def 4GM7WriteVPMADD52XYmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPMADD52XYrk.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPMADD52XYmk], (instregex "VPMADD52(L|H)UQ(Z128|Z256)mk$")>;
+
+
+def 4GM7WriteVPMADD52Z:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPMADD52Z], (instregex "VPMADD52(L|H)UQZ(r|rkz)$")>;
+
+def 4GM7WriteVPMADD52ZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPMADD52Z.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPMADD52ZLd], (instregex "VPMADD52(L|H)UQZ(m|mkz)$")>;
+
+def 4GM7WriteVPMADD52Zrk:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 5;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPMADD52Zrk], (instregex "VPMADD52(L|H)UQZrk$")>;
+
+def 4GM7WriteVPMADD52Zmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPMADD52Zrk.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPMADD52Zmk], (instregex "VPMADD52(L|H)UQZmk$")>;
+
+
+// VMULZ VPMULZ
+def 4GM7WriteVMULZ_VPMULZ:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVMULZ_VPMULZ], (instrs VMULPSZ128rrk, VMULPDZ128rrk,
+ VMULPSZ256rrk, VMULPDZ256rrk,
+ VMULPSZrrbk, VMULPSZrrk,
+ VMULPDZrrbk, VMULPDZrrk,
+ VMULSSZrrbk_Int, VMULSSZrrk_Int,
+ VMULSDZrrbk_Int, VMULSDZrrk_Int,
+ VPMULDQZrrk, VPMULDQZ128rrk, VPMULDQZ256rrk,
+ VPMULHRSWZrrk, VPMULHRSWZ128rrk, VPMULHRSWZ256rrk,
+ VPMULHUWZrrk, VPMULHUWZ128rrk, VPMULHUWZ256rrk,
+ VPMULHWZrrk, VPMULHWZ128rrk, VPMULHWZ256rrk,
+ VPMULLDZrrk, VPMULLDZ128rrk, VPMULLDZ256rrk,
+ VPMULLQZrr, VPMULLQZrrkz,
+ VPMULLQZ128rr, VPMULLQZ128rrkz,
+ VPMULLQZ256rr, VPMULLQZ256rrkz,
+ VPMULLWZrrk, VPMULLWZ128rrk, VPMULLWZ256rrk,
+ VPMULUDQZrrk, VPMULUDQZ128rrk, VPMULUDQZ256rrk)>;
+
+def 4GM7WriteVMULZ_VPMULZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVMULZ_VPMULZ.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVMULZ_VPMULZLd], (instrs VMULPSZ128rmk, VMULPDZ128rmk,
+ VMULPSZ256rmk, VMULPDZ256rmk,
+ VMULPSZrmbk, VMULPSZrmk,
+ VMULPDZrmbk, VMULPDZrmk,
+ VPMULDQZrmk, VPMULDQZ128rmk, VPMULDQZ256rmk,
+ VPMULHRSWZrmk, VPMULHRSWZ128rmk, VPMULHRSWZ256rmk,
+ VPMULHUWZrmk, VPMULHUWZ128rmk, VPMULHUWZ256rmk,
+ VPMULHWZrmk, VPMULHWZ128rmk, VPMULHWZ256rmk,
+ VPMULLDZrmk, VPMULLDZ128rmk, VPMULLDZ256rmk,
+ VPMULLQZrm, VPMULLQZrmkz,
+ VPMULLQZ128rm, VPMULLQZ128rmkz,
+ VPMULLQZ256rm, VPMULLQZ256rmkz,
+ VPMULLWZrmk, VPMULLWZ128rmk, VPMULLWZ256rmk,
+ VPMULUDQZrmk, VPMULUDQZ128rmk, VPMULUDQZ256rmk)>;
+
+def 4GM7WriteVPMULLQZrrk:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 5;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPMULLQZrrk], (instrs VPMULLQZrrk, VPMULLQZ128rrk, VPMULLQZ256rrk)>;
+
+def 4GM7WriteVPMULLQZrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPMULLQZrrk.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPMULLQZrmk], (instrs VPMULLQZrmk, VPMULLQZ128rmk, VPMULLQZ256rmk)>;
+
+
+// VPMULTISHIFTQB
+def 4GM7WriteVPMULTISHIFTQBZ:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 3;
+ let ReleaseAtCycles = [8];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPMULTISHIFTQBZ], (instrs VPMULTISHIFTQBZ128rr, VPMULTISHIFTQBZ128rrkz,
+ VPMULTISHIFTQBZ256rr, VPMULTISHIFTQBZ256rrkz)>;
+
+def 4GM7WriteVPMULTISHIFTQBZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPMULTISHIFTQBZ.Latency);
+ let ReleaseAtCycles = [1, 1, 8];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPMULTISHIFTQBZLd], (instrs VPMULTISHIFTQBZ128rm, VPMULTISHIFTQBZ128rmkz,
+ VPMULTISHIFTQBZ256rm, VPMULTISHIFTQBZ256rmkz)>;
+
+def 4GM7WriteVPMULTISHIFTQBZrrk:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [8];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPMULTISHIFTQBZrrk], (instrs VPMULTISHIFTQBZ128rrk, VPMULTISHIFTQBZ256rrk,
+ VPMULTISHIFTQBZrr, VPMULTISHIFTQBZrrk, VPMULTISHIFTQBZrrkz)>;
+
+def 4GM7WriteVPMULTISHIFTQBZrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPMULTISHIFTQBZrrk.Latency);
+ let ReleaseAtCycles = [1, 1, 8];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPMULTISHIFTQBZrmk], (instrs VPMULTISHIFTQBZ128rmk, VPMULTISHIFTQBZ256rmk,
+ VPMULTISHIFTQBZrm, VPMULTISHIFTQBZrmk, VPMULTISHIFTQBZrmkz)>;
+
+// VPMADDUBSWZ
+def 4GM7WriteVPMADDUBSWZrrk:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPMADDUBSWZrrk], (instrs VPMADDUBSWZrrk, VPMADDUBSWZ128rrk, VPMADDUBSWZ256rrk)>;
+
+def 4GM7WriteVPMADDUBSWZrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPMADDUBSWZrrk.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPMADDUBSWZrmk], (instrs VPMADDUBSWZrmk, VPMADDUBSWZ128rmk, VPMADDUBSWZ256rmk)>;
+
+// FADD rrb rrbk
+def 4GM7WriteFADD:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteFADD], (instregex "VADD(S|P)(S|D)(Z|Z128|Z256)rr(bk|k)$",
+ "VSUB(S|P)(S|D)(Z|Z128|Z256)rr(bk|k)$")>;
+
+def 4GM7WriteFADDLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteFADD.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteFADDLd], (instregex "VADD(S|P)(S|D)(Z|Z128|Z256)rm(bk|k)$",
+ "VSUB(S|P)(S|D)(Z|Z128|Z256)rm(bk|k)$")>;
+
+// FADD rrb rrbk Int
+def 4GM7WriteFADD_Int:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteFADD_Int], (instregex "VADD(SD|SS)Zrr(bk|k)_Int",
+ "VSUB(SD|SS)Zrr(bk|k)_Int")>;
+
+def 4GM7WriteFADDLd_Int:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteFADD_Int.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteFADDLd_Int], (instregex "VADD(SD|SS)Zrm(bk|k)_Int",
+ "VSUB(SD|SS)Zrm(bk|k)_Int")>;
+
+// RCP14
+def 4GM7WriteVRCP14:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVRCP14], (instrs VRCP14SSZrr, VRCP14SSZrrk, VRCP14SSZrrkz,
+ VRCP14SDZrr, VRCP14SDZrrk, VRCP14SDZrrkz)>;
+
+def 4GM7WriteVRCP14Ld:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVRCP14.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVRCP14Ld], (instrs VRCP14SDZrm, VRCP14SDZrmk, VRCP14SDZrmkz,
+ VRCP14SSZrm, VRCP14SSZrmk, VRCP14SSZrmkz)>;
+
+def 4GM7WriteVRCP14X:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVRCP14X], (instrs VRCP14PSZ128r, VRCP14PSZ128rk, VRCP14PSZ128rkz,
+ VRCP14PDZ128r, VRCP14PDZ128rk, VRCP14PDZ128rkz)>;
+
+def 4GM7WriteVRCP14XLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVRCP14X.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVRCP14XLd], (instrs VRCP14PDZ128m, VRCP14PDZ128mb, VRCP14PDZ128mbk,
+ VRCP14PDZ128mbkz, VRCP14PDZ128mk, VRCP14PDZ128mkz,
+ VRCP14PSZ128m, VRCP14PSZ128mb, VRCP14PSZ128mbk,
+ VRCP14PSZ128mbkz, VRCP14PSZ128mk, VRCP14PSZ128mkz)>;
+
+def 4GM7WriteVRCP14Y:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVRCP14Y], (instrs VRCP14PSZ256r, VRCP14PSZ256rk, VRCP14PSZ256rkz,
+ VRCP14PDZ256r, VRCP14PDZ256rk, VRCP14PDZ256rkz)>;
+
+def 4GM7WriteVRCP14YLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVRCP14Y.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVRCP14YLd], (instrs VRCP14PDZ256m, VRCP14PDZ256mb, VRCP14PDZ256mbk,
+ VRCP14PDZ256mbkz, VRCP14PDZ256mk, VRCP14PDZ256mkz,
+ VRCP14PSZ256m, VRCP14PSZ256mb, VRCP14PSZ256mbk,
+ VRCP14PSZ256mbkz, VRCP14PSZ256mk, VRCP14PSZ256mkz)>;
+
+def 4GM7WriteVRCP14Z:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVRCP14Z], (instrs VRCP14PDZr, VRCP14PDZrk, VRCP14PDZrkz,
+ VRCP14PSZr, VRCP14PSZrk, VRCP14PSZrkz)>;
+
+def 4GM7WriteVRCP14ZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVRCP14Z.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVRCP14ZLd], (instrs VRCP14PDZm, VRCP14PDZmb, VRCP14PDZmbk,
+ VRCP14PDZmbkz, VRCP14PDZmk, VRCP14PDZmkz,
+ VRCP14PSZm, VRCP14PSZmb, VRCP14PSZmbk,
+ VRCP14PSZmbkz, VRCP14PSZmk, VRCP14PSZmkz)>;
+
+// RSQRT14
+def 4GM7WriteRSQRT14:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteRSQRT14], (instrs VRSQRT14SDZrr, VRSQRT14SDZrrk, VRSQRT14SDZrrkz,
+ VRSQRT14SSZrr, VRSQRT14SSZrrk, VRSQRT14SSZrrkz)>;
+
+def 4GM7WriteRSQRT14Ld:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteRSQRT14.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteRSQRT14Ld], (instrs VRSQRT14SDZrm, VRSQRT14SDZrmk, VRSQRT14SDZrmkz,
+ VRSQRT14SSZrm, VRSQRT14SSZrmk, VRSQRT14SSZrmkz)>;
+
+def 4GM7WriteRSQRT14X:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteRSQRT14X], (instrs VRSQRT14PDZ128r, VRSQRT14PDZ128rk, VRSQRT14PDZ128rkz,
+ VRSQRT14PSZ128r, VRSQRT14PSZ128rk, VRSQRT14PSZ128rkz)>;
+
+def 4GM7WriteRSQRT14XLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteRSQRT14X.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteRSQRT14XLd], (instrs VRSQRT14PDZ128m, VRSQRT14PDZ128mb, VRSQRT14PDZ128mbk,
+ VRSQRT14PDZ128mbkz, VRSQRT14PDZ128mk, VRSQRT14PDZ128mkz,
+ VRSQRT14PSZ128m, VRSQRT14PSZ128mb, VRSQRT14PSZ128mbk,
+ VRSQRT14PSZ128mbkz, VRSQRT14PSZ128mk, VRSQRT14PSZ128mkz)>;
+
+def 4GM7WriteRSQRT14Y:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteRSQRT14Y], (instrs VRSQRT14PDZ256r, VRSQRT14PDZ256rk, VRSQRT14PDZ256rkz,
+ VRSQRT14PSZ256r, VRSQRT14PSZ256rk, VRSQRT14PSZ256rkz)>;
+
+def 4GM7WriteRSQRT14YLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteRSQRT14Y.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteRSQRT14YLd], (instrs VRSQRT14PDZ256m, VRSQRT14PDZ256mb, VRSQRT14PDZ256mbk,
+ VRSQRT14PDZ256mbkz, VRSQRT14PDZ256mk, VRSQRT14PDZ256mkz,
+ VRSQRT14PSZ256m, VRSQRT14PSZ256mb, VRSQRT14PSZ256mbk,
+ VRSQRT14PSZ256mbkz, VRSQRT14PSZ256mk, VRSQRT14PSZ256mkz)>;
+
+def 4GM7WriteRSQRT14Z:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteRSQRT14Z], (instrs VRSQRT14PDZr, VRSQRT14PDZrk, VRSQRT14PDZrkz,
+ VRSQRT14PSZr, VRSQRT14PSZrk, VRSQRT14PSZrkz)>;
+
+def 4GM7WriteRSQRT14ZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteRSQRT14Z.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteRSQRT14ZLd], (instrs VRSQRT14PDZm, VRSQRT14PDZmb, VRSQRT14PDZmbk,
+ VRSQRT14PDZmbkz, VRSQRT14PDZmk, VRSQRT14PDZmkz,
+ VRSQRT14PSZm, VRSQRT14PSZmb, VRSQRT14PSZmbk,
+ VRSQRT14PSZmbkz, VRSQRT14PSZmk, VRSQRT14PSZmkz)>;
+
+defm : 4GM7WriteResFPPair<WriteFCmp, [4GM7FPU02], 1>;
+defm : 4GM7WriteResFPPair<WriteFCmpX, [4GM7FPU02], 1>;
+defm : 4GM7WriteResFPPair<WriteFCmpY, [4GM7FPU02], 1>;
+defm : 4GM7WriteResFPPair<WriteFCmpZ, [4GM7FPU02], 1>;
+defm : 4GM7WriteResFPPair<WriteFCmp64, [4GM7FPU02], 1>;
+defm : 4GM7WriteResFPPair<WriteFCmp64X, [4GM7FPU02], 1>;
+defm : 4GM7WriteResFPPair<WriteFCmp64Y, [4GM7FPU02], 1>;
+defm : 4GM7WriteResFPPair<WriteFCmp64Z, [4GM7FPU02], 1>;
+defm : 4GM7WriteResFPPair<WriteFCom, [4GM7FPU02], 1>;
+defm : 4GM7WriteResFPPair<WriteFComX, [4GM7FPU], 1, [2], 2>;
+defm : 4GM7WriteResFPPair<WriteFBlend, [4GM7FPU], 1>;
+defm : 4GM7WriteResFPPair<WriteFBlendY, [4GM7FPU], 1>;
+defm : 4GM7WriteResFPPair<WriteFBlendZ, [4GM7FPU], 1>;
+defm : 4GM7WriteResFPPair<WriteFVarBlend, [4GM7FPU], 1>;
+defm : 4GM7WriteResFPPair<WriteFVarBlendY, [4GM7FPU], 1>;
+defm : 4GM7WriteResFPPair<WriteFVarBlendZ, [4GM7FPU], 1>;
+
+def 4GM7WriteFCOMI_FCOMIP:SchedWriteRes<[4GM7FPU02, 4GM7FPU13]> {
+ let Latency = 2;
+ let ReleaseAtCycles = [1, 1];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteFCOMI_FCOMIP], (instrs COM_FIPr, COM_FIr)>;
+
+// VMAX VMIN
+def 4GM7WriteVMAXXY_VMINXY:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 2;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVMAXXY_VMINXY], (instrs VMAXPSZ128rrk, VMAXPDZ128rrk,
+ VMINPSZ128rrk, VMINPDZ128rrk,
+ VMAXCPSZ128rrk, VMAXCPDZ128rrk,
+ VMINCPSZ128rrk, VMINCPDZ128rrk,
+ VMAXPSZ256rrk, VMAXPDZ256rrk,
+ VMINPSZ256rrk, VMINPDZ256rrk,
+ VMAXCPSZ256rrk, VMAXCPDZ256rrk,
+ VMINCPSZ256rrk, VMINCPDZ256rrk)>;
+
+def 4GM7WriteVMAXXY_VMINXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVMAXXY_VMINXY.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVMAXXY_VMINXYLd], (instrs VMAXPSZ128rmk, VMAXPDZ128rmk,
+ VMINPSZ128rmk, VMINPDZ128rmk,
+ VMAXCPSZ128rmk, VMAXCPDZ128rmk,
+ VMINCPSZ128rmk, VMINCPDZ128rmk,
+ VMAXPSZ256rmk, VMAXPDZ256rmk,
+ VMINPSZ256rmk, VMINPDZ256rmk,
+ VMAXCPSZ256rmk, VMAXCPDZ256rmk,
+ VMINCPSZ256rmk, VMINCPDZ256rmk)>;
+
+def 4GM7WriteVMAXZ_VMINZ:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 2;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVMAXZ_VMINZ], (instrs VMAXPSZrrk, VMAXPSZrrbk,
+ VMAXPDZrrk, VMAXPDZrrbk,
+ VMINPSZrrk, VMINPSZrrbk,
+ VMINPDZrrk, VMINPDZrrbk,
+ VMAXCPSZrrk, VMAXCPDZrrk,
+ VMINCPSZrrk, VMINCPDZrrk,
+ VMAXSSZrrk_Int, VMAXSSZrrbk_Int,
+ VMAXSDZrrk_Int, VMAXSDZrrbk_Int,
+ VMINSSZrrk_Int, VMINSSZrrbk_Int,
+ VMINSDZrrk_Int, VMINSDZrrbk_Int)>;
+
+def 4GM7WriteVMAXZ_VMINZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVMAXZ_VMINZ.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVMAXZ_VMINZLd], (instrs VMAXPSZrmk, VMAXPSZrmbk,
+ VMAXPDZrmk, VMAXPDZrmbk,
+ VMINPSZrmk, VMINPSZrmbk,
+ VMINPDZrmk, VMINPDZrmbk,
+ VMAXCPSZrmk, VMAXCPDZrmk,
+ VMINCPSZrmk, VMINCPDZrmk,
+ VMAXSSZrmk_Int, VMAXSDZrmk_Int,
+ VMINSSZrmk_Int, VMINSDZrmk_Int)>;
+
+// VBLEND
+def 4GM7WriteVBLENDrrk:SchedWriteRes<[4GM7FPU]> {
+ let Latency = 2;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVBLENDrrk], (instregex "VPBLENDM(B|D|W|Q)Z(128|256)?rrk$",
+ "VBLENDM(PS|PD)Zrrk$")>;
+
+def 4GM7WriteVBLENDrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVBLENDrrk.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVBLENDrmk], (instregex "VPBLENDM(B|D|W|Q)Z(128|256)?rmk$",
+ "VBLENDM(PS|PD)Zrmk$")>;
+
+defm : 4GM7WriteResFPPair<WriteCvtSS2I, [4GM7FPU13], 2, [2], 2>;
+defm : 4GM7WriteResFPPair<WriteCvtPS2I, [4GM7FPU13], 4, [1], 1>;
+defm : 4GM7WriteResFPPair<WriteCvtPS2IY, [4GM7FPU13], 4, [1], 1>;
+defm : 4GM7WriteResFPPair<WriteCvtPS2IZ, [4GM7FPU13], 4, [2], 2>;
+defm : 4GM7WriteResFPPair<WriteCvtSD2I, [4GM7FPU13], 2, [2], 2>;
+defm : 4GM7WriteResFPPair<WriteCvtPD2I, [4GM7FPU13], 4, [1], 1>;
+defm : 4GM7WriteResFPPair<WriteCvtPD2IY, [4GM7FPU13], 4, [1], 1>;
+defm : 4GM7WriteResFPPair<WriteCvtPD2IZ, [4GM7FPU13], 8, [2], 2>;
+defm : 4GM7WriteResFPPair<WriteCvtSS2SD, [4GM7FPU13], 4, [1], 1>;
+defm : 4GM7WriteResFPPair<WriteCvtPS2PD, [4GM7FPU13], 4, [1], 1>;
+defm : 4GM7WriteResFPPair<WriteCvtPS2PDY, [4GM7FPU13], 4, [1], 1>;
+defm : 4GM7WriteResFPPair<WriteCvtPS2PDZ, [4GM7FPU13], 5, [2], 2>;
+defm : 4GM7WriteResFPPair<WriteCvtSD2SS, [4GM7FPU13], 4, [1], 1>;
+defm : 4GM7WriteResFPPair<WriteCvtPD2PS, [4GM7FPU13], 4, [1], 1>;
+defm : 4GM7WriteResFPPair<WriteCvtPD2PSY, [4GM7FPU13], 4, [1], 1>;
+defm : 4GM7WriteResFPPair<WriteCvtPD2PSZ, [4GM7FPU13], 8, [2], 2>;
+defm : 4GM7WriteResFPPair<WriteCvtI2SS, [4GM7FPU13], 4, [3], 2>;
+defm : 4GM7WriteResFPPair<WriteCvtI2PS, [4GM7FPU13], 4>;
+defm : 4GM7WriteResFPPair<WriteCvtI2PSY, [4GM7FPU13], 4>;
+defm : 4GM7WriteResFPPair<WriteCvtI2PSZ, [4GM7FPU13], 4, [2], 2>;
+defm : 4GM7WriteResFPPair<WriteCvtI2SD, [4GM7FPU13], 4, [3], 2>;
+defm : 4GM7WriteResFPPair<WriteCvtI2PD, [4GM7FPU13], 4>;
+defm : 4GM7WriteResFPPair<WriteCvtI2PDY, [4GM7FPU13], 4>;
+defm : 4GM7WriteResFPPair<WriteCvtI2PDZ, [4GM7FPU13], 5, [2], 2>;
+defm : 4GM7WriteResFPPair<WriteCvtPH2PS, [4GM7FPU13], 4, [1], 1>;
+defm : 4GM7WriteResFPPair<WriteCvtPH2PSY, [4GM7FPU13], 4, [1], 1>;
+defm : 4GM7WriteResFPPair<WriteCvtPH2PSZ, [4GM7FPU13], 5, [2], 2>;
+defm : 4GM7WriteRes<WriteCvtPS2PH, [4GM7FPU13], 4, [1], 1>;
+defm : 4GM7WriteRes<WriteCvtPS2PHY, [4GM7FPU13], 4, [1], 1>;
+defm : 4GM7WriteRes<WriteCvtPS2PHZ, [4GM7FPU13], 8, [2], 2>;
+defm : 4GM7WriteRes<WriteCvtPS2PHSt, [4GM7FPU13, 4GM7AGU, 4GM7Store], !add(4, C864GM7Model.StoreLatency), [1, 1, 1], 2>;
+defm : 4GM7WriteRes<WriteCvtPS2PHYSt, [4GM7FPU13, 4GM7AGU, 4GM7Store], !add(4, C864GM7Model.StoreLatency), [1, 1, 1], 2>;
+defm : 4GM7WriteRes<WriteCvtPS2PHZSt, [4GM7FPU13, 4GM7AGU, 4GM7Store], !add(8, C864GM7Model.StoreLatency), [2, 1, 1], 3>;
+
+// CVTPD2QQ
+def 4GM7WritePD2QQ:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WritePD2QQ], (instregex "VCVT(T?)PD2(U?)QQ(Z|Z128|Z256)(rr$|rrkz)")>;
+
+def 4GM7WritePD2QQLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WritePD2QQ.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WritePD2QQLd], (instregex "VCVT(T?)PD2(U?)QQ(Z|Z128|Z256)(rm$|rmkz)")>;
+
+// CVTSI2SS
+def 4GM7WriteSI2SSrr:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteSI2SSrr], (instregex "VCVT(U?)SI2SS(Z?)rr")>;
+
+def 4GM7WriteSI2SSrm:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteSI2SSrr.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteSI2SSrm], (instregex "VCVT(U?)SI2SS(Z?)rm")>;
+
+// SI2SD
+def 4GM7WriteSI2SD:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteSI2SD], (instregex "VCVT(U?)SI2SD(Z?)rr")>;
+
+def 4GM7WriteSI2SDLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteSI2SD.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteSI2SDLd], (instregex "VCVT(U?)SI2SD(Z?)rm")>;
+
+// CVT BF16
+def 4GM7WriteCVTBF16:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [6];
+ let NumMicroOps = 7;
+}
+def : InstRW<[4GM7WriteCVTBF16], (instrs VCVTNE2PS2BF16Z256rr, VCVTNE2PS2BF16Z256rrkz,
+ VCVTNE2PS2BF16Zrrkz)>;
+
+def 4GM7WriteCVTBF16Ld:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteCVTBF16.Latency);
+ let ReleaseAtCycles = [1, 1, 6];
+ let NumMicroOps = 7;
+}
+def : InstRW<[4GM7WriteCVTBF16Ld], (instrs VCVTNE2PS2BF16Z256rm, VCVTNE2PS2BF16Z256rmkz,
+ VCVTNE2PS2BF16Zrmkz)>;
+
+// CVT BF16
+def 4GM7WriteCVTBF16rrk:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 5;
+ let ReleaseAtCycles = [6];
+ let NumMicroOps = 7;
+}
+def : InstRW<[4GM7WriteCVTBF16rrk], (instrs VCVTNE2PS2BF16Z128rrk, VCVTNEPS2BF16Zrrk,
+ VCVTNE2PS2BF16Zrrk)>;
+
+def 4GM7WriteCVTBF16rmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteCVTBF16rrk.Latency);
+ let ReleaseAtCycles = [1, 1, 6];
+ let NumMicroOps = 7;
+}
+def : InstRW<[4GM7WriteCVTBF16rmk], (instrs VCVTNE2PS2BF16Z128rmk, VCVTNEPS2BF16Zrmk)>;
+
+// CVT BF16
+def 4GM7WriteCVTBF16rr:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 8;
+ let ReleaseAtCycles = [6];
+ let NumMicroOps = 7;
+}
+def : InstRW<[4GM7WriteCVTBF16rr], (instrs VCVTNE2PS2BF16Zrr)>;
+
+def 4GM7WriteCVTBF16rm:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteCVTBF16rr.Latency);
+ let ReleaseAtCycles = [1, 1, 6];
+ let NumMicroOps = 7;
+}
+def : InstRW<[4GM7WriteCVTBF16rm], (instrs VCVTNE2PS2BF16Zrm)>;
+
+// VDPBF16
+def 4GM7WriteVDPBF16:SchedWriteRes<[4GM7FPU02, 4GM7FPU02]> {
+ let Latency = 8;
+ let ReleaseAtCycles = [4, 4];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVDPBF16], (instrs VDPBF16PSZr, VDPBF16PSZrkz,
+ VDPBF16PSZ128r, VDPBF16PSZ128rkz,
+ VDPBF16PSZ256r, VDPBF16PSZ256rkz)>;
+
+def 4GM7WriteVDPBF16Ld:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVDPBF16.Latency);
+ let ReleaseAtCycles = [1, 1, 4, 4];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVDPBF16Ld], (instrs VDPBF16PSZm, VDPBF16PSZmkz,
+ VDPBF16PSZ128m, VDPBF16PSZ128mkz,
+ VDPBF16PSZ256m, VDPBF16PSZ256mkz)>;
+
+// VDPBF16
+def 4GM7WriteVDPBF16rk:SchedWriteRes<[4GM7FPU02, 4GM7FPU02]> {
+ let Latency = 10;
+ let ReleaseAtCycles = [4, 4];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVDPBF16rk], (instrs VDPBF16PSZrk, VDPBF16PSZ128rk, VDPBF16PSZ256rk)>;
+
+def 4GM7WriteVDPBF16mk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVDPBF16rk.Latency);
+ let ReleaseAtCycles = [1, 1, 4, 4];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVDPBF16mk], (instrs VDPBF16PSZmk, VDPBF16PSZ128mk, VDPBF16PSZ256mk)>;
+
+// VCVT rrk
+def 4GM7WriteVCVTrrk:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 5;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVCVTrrk], (instrs VCVTPD2PSZ128rrk, VCVTPD2PSZ128rrk, VCVTSD2SSZrrbk_Int,
+ VCVTSD2SSZrrk_Int, VCVTSS2SDZrrbk_Int, VCVTSS2SDZrrk_Int,
+ VCVTDQ2PDZ128rrk, VCVTUDQ2PDZ128rrk, VCVTDQ2PDZ256rrk,
+ VCVTUDQ2PDZ256rrk, VCVTDQ2PSZ128rrk, VCVTUDQ2PSZ128rrk,
+ VCVTDQ2PSZ256rrk, VCVTUDQ2PSZ256rrk, VCVTDQ2PSZrrbk,
+ VCVTDQ2PSZrrk, VCVTUDQ2PSZrrbk, VCVTUDQ2PSZrrk,
+ VCVTPD2DQZ128rrk, VCVTPD2UDQZ128rrk, VCVTTPD2DQZ128rrk,
+ VCVTTPD2UDQZ128rrk, VCVTPD2DQZ256rrk, VCVTPD2UDQZ256rrk,
+ VCVTTPD2DQZ256rrk, VCVTTPD2UDQZ256rrk, VCVTPD2DQZrrbk,
+ VCVTPD2DQZrrk, VCVTPD2UDQZrrbk, VCVTPD2UDQZrrk,
+ VCVTTPD2DQZrrbk, VCVTTPD2DQZrrk, VCVTTPD2UDQZrrbk,
+ VCVTTPD2UDQZrrk, VCVTPD2PSZ256rrk, VCVTPD2PSZrrbk,
+ VCVTPD2PSZrrk, VCVTPD2QQZ128rrk, VCVTPD2UQQZ128rrk,
+ VCVTTPD2QQZ128rrk, VCVTTPD2UQQZ128rrk, VCVTPD2QQZ256rrk,
+ VCVTPD2UQQZ256rrk, VCVTTPD2QQZ256rrk, VCVTTPD2UQQZ256rrk,
+ VCVTPD2QQZrrbk, VCVTPD2QQZrrk, VCVTPD2UQQZrrbk,
+ VCVTPD2UQQZrrk, VCVTTPD2QQZrrbk, VCVTTPD2QQZrrk,
+ VCVTTPD2UQQZrrbk, VCVTTPD2UQQZrrk, VCVTPH2PSZ128rrk,
+ VCVTPH2PSZ256rrk, VCVTPS2DQZ256rrk, VCVTPS2UDQZ256rrk,
+ VCVTTPS2DQZ256rrk, VCVTTPS2UDQZ256rrk, VCVTPS2DQZ128rrk,
+ VCVTPS2UDQZ128rrk, VCVTTPS2DQZ128rrk, VCVTTPS2UDQZ128rrk,
+ VCVTPS2DQZrrbk, VCVTPS2DQZrrk, VCVTPS2UDQZrrbk,
+ VCVTPS2UDQZrrk, VCVTTPS2DQZrrbk, VCVTTPS2DQZrrk,
+ VCVTTPS2UDQZrrbk, VCVTTPS2UDQZrrk, VCVTPS2PDZ256rrk,
+ VCVTPS2PHZ128rrk, VCVTPS2PHZ256rrk, VCVTPS2PHZrrbk,
+ VCVTPS2PHZrrk, VCVTPS2QQZ128rrk, VCVTPS2UQQZ128rrk,
+ VCVTTPS2QQZ128rrk, VCVTTPS2UQQZ128rrk, VCVTPS2QQZ256rrk,
+ VCVTPS2UQQZ256rrk, VCVTTPS2QQZ256rrk, VCVTTPS2UQQZ256rrk,
+ VCVTQQ2PDZ128rrk, VCVTUQQ2PDZ128rrk, VCVTQQ2PDZ256rrk,
+ VCVTUQQ2PDZ256rrk, VCVTQQ2PDZrrbk, VCVTQQ2PDZrrk,
+ VCVTUQQ2PDZrrbk, VCVTUQQ2PDZrrk, VCVTQQ2PSZ128rrk,
+ VCVTUQQ2PSZ128rrk, VCVTQQ2PSZ256rrk, VCVTUQQ2PSZ256rrk,
+ VCVTQQ2PSZrrbk, VCVTQQ2PSZrrk, VCVTUQQ2PSZrrbk,
+ VCVTUQQ2PSZrrk, VCVTPS2PDZ128rrk, VCVTPS2QQZrr,
+ VCVTPS2UQQZrr, VCVTTPS2QQZrr, VCVTTPS2UQQZrr,
+ VCVTPS2QQZrrb, VCVTPS2QQZrrbkz, VCVTPS2QQZrrkz,
+ VCVTPS2UQQZrrb, VCVTPS2UQQZrrbkz, VCVTPS2UQQZrrkz,
+ VCVTTPS2QQZrrb, VCVTTPS2QQZrrbkz, VCVTTPS2QQZrrkz,
+ VCVTTPS2UQQZrrb, VCVTTPS2UQQZrrbkz, VCVTTPS2UQQZrrkz,
+ VCVTPS2QQZrrbk, VCVTPS2QQZrrk, VCVTPS2UQQZrrbk,
+ VCVTPS2UQQZrrk, VCVTTPS2QQZrrbk, VCVTTPS2QQZrrk,
+ VCVTTPS2UQQZrrbk, VCVTTPS2UQQZrrk)>;
+
+def 4GM7WriteVCVTrrkLD:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVCVTrrk.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVCVTrrkLD], (instrs VCVTPD2PSZ128rmk, VCVTPD2PSZ128rmk,
+ VCVTSD2SSZrmk_Int, VCVTSS2SDZrmk_Int,
+ VCVTDQ2PDZ128rmk, VCVTUDQ2PDZ128rmk, VCVTDQ2PDZ256rmk,
+ VCVTUDQ2PDZ256rmk, VCVTDQ2PSZ128rmk, VCVTUDQ2PSZ128rmk,
+ VCVTDQ2PSZ256rmk, VCVTUDQ2PSZ256rmk, VCVTDQ2PSZrmbk,
+ VCVTDQ2PSZrmk, VCVTUDQ2PSZrmbk, VCVTUDQ2PSZrmk,
+ VCVTPD2DQZ128rmk, VCVTPD2UDQZ128rmk, VCVTTPD2DQZ128rmk,
+ VCVTTPD2UDQZ128rmk, VCVTPD2DQZ256rmk, VCVTPD2UDQZ256rmk,
+ VCVTTPD2DQZ256rmk, VCVTTPD2UDQZ256rmk, VCVTPD2DQZrmbk,
+ VCVTPD2DQZrmk, VCVTPD2UDQZrmbk, VCVTPD2UDQZrmk,
+ VCVTTPD2DQZrmbk, VCVTTPD2DQZrmk, VCVTTPD2UDQZrmbk,
+ VCVTTPD2UDQZrmk, VCVTPD2PSZ256rmk, VCVTPD2PSZrmbk,
+ VCVTPD2PSZrmk, VCVTPD2QQZ128rmk, VCVTPD2UQQZ128rmk,
+ VCVTTPD2QQZ128rmk, VCVTTPD2UQQZ128rmk, VCVTPD2QQZ256rmk,
+ VCVTPD2UQQZ256rmk, VCVTTPD2QQZ256rmk, VCVTTPD2UQQZ256rmk,
+ VCVTPD2QQZrmbk, VCVTPD2QQZrmk, VCVTPD2UQQZrmbk,
+ VCVTPD2UQQZrmk, VCVTTPD2QQZrmbk, VCVTTPD2QQZrmk,
+ VCVTTPD2UQQZrmbk, VCVTTPD2UQQZrmk, VCVTPH2PSZ128rmk,
+ VCVTPH2PSZ256rmk, VCVTPS2DQZ256rmk, VCVTPS2UDQZ256rmk,
+ VCVTTPS2DQZ256rmk, VCVTTPS2UDQZ256rmk, VCVTPS2DQZ128rmk,
+ VCVTPS2UDQZ128rmk, VCVTTPS2DQZ128rmk, VCVTTPS2UDQZ128rmk,
+ VCVTPS2DQZrmbk, VCVTPS2DQZrmk, VCVTPS2UDQZrmbk,
+ VCVTPS2UDQZrmk, VCVTTPS2DQZrmbk, VCVTTPS2DQZrmk,
+ VCVTTPS2UDQZrmbk, VCVTTPS2UDQZrmk, VCVTPS2PDZ256rmk,
+ VCVTPS2QQZ128rmk, VCVTPS2UQQZ128rmk,
+ VCVTTPS2QQZ128rmk, VCVTTPS2UQQZ128rmk, VCVTPS2QQZ256rmk,
+ VCVTPS2UQQZ256rmk, VCVTTPS2QQZ256rmk, VCVTTPS2UQQZ256rmk,
+ VCVTQQ2PDZ128rmk, VCVTUQQ2PDZ128rmk, VCVTQQ2PDZ256rmk,
+ VCVTUQQ2PDZ256rmk, VCVTQQ2PDZrmbk, VCVTQQ2PDZrmk,
+ VCVTUQQ2PDZrmbk, VCVTUQQ2PDZrmk, VCVTQQ2PSZ128rmk,
+ VCVTUQQ2PSZ128rmk, VCVTQQ2PSZ256rmk, VCVTUQQ2PSZ256rmk,
+ VCVTQQ2PSZrmbk, VCVTQQ2PSZrmk, VCVTUQQ2PSZrmbk,
+ VCVTUQQ2PSZrmk, VCVTPS2PDZ128rmk, VCVTPS2QQZrm,
+ VCVTPS2UQQZrm, VCVTTPS2QQZrm, VCVTTPS2UQQZrm,
+ VCVTPS2QQZrmb, VCVTPS2QQZrmbkz, VCVTPS2QQZrmkz,
+ VCVTPS2UQQZrmb, VCVTPS2UQQZrmbkz, VCVTPS2UQQZrmkz,
+ VCVTTPS2QQZrmb, VCVTTPS2QQZrmbkz, VCVTTPS2QQZrmkz,
+ VCVTTPS2UQQZrmb, VCVTTPS2UQQZrmbkz, VCVTTPS2UQQZrmkz,
+ VCVTPS2QQZrmbk, VCVTPS2QQZrmk, VCVTPS2UQQZrmbk,
+ VCVTPS2UQQZrmk, VCVTTPS2QQZrmbk, VCVTTPS2QQZrmk,
+ VCVTTPS2UQQZrmbk, VCVTTPS2UQQZrmk)>;
+
+// VCVT
+def 4GM7WriteVCVTrr:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVCVTrr], (instrs VCVTPD2QQZrrb, VCVTPD2QQZrrbkz, VCVTPD2UQQZrrb,
+ VCVTPD2UQQZrrbkz, VCVTTPD2QQZrrb, VCVTTPD2QQZrrbkz,
+ VCVTTPD2UQQZrrb, VCVTTPD2UQQZrrbkz, VCVTQQ2PDZrr,
+ VCVTQQ2PDZrrb, VCVTQQ2PDZrrbkz, VCVTQQ2PDZrrkz,
+ VCVTUQQ2PDZrr, VCVTUQQ2PDZrrb, VCVTUQQ2PDZrrbkz,
+ VCVTUQQ2PDZrrkz)>;
+
+def 4GM7WriteVCVTrm:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVCVTrr.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVCVTrm], (instrs VCVTPD2QQZrmb, VCVTPD2QQZrmbkz, VCVTPD2UQQZrmb,
+ VCVTPD2UQQZrmbkz, VCVTTPD2QQZrmb, VCVTTPD2QQZrmbkz,
+ VCVTTPD2UQQZrmb, VCVTTPD2UQQZrmbkz, VCVTQQ2PDZrm,
+ VCVTQQ2PDZrmb, VCVTQQ2PDZrmbkz, VCVTQQ2PDZrmkz,
+ VCVTUQQ2PDZrm, VCVTUQQ2PDZrmb, VCVTUQQ2PDZrmbkz,
+ VCVTUQQ2PDZrmkz)>;
+
+// VCVTQQ2PS
+def 4GM7WriteVCVTQQ2PS:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 8;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVCVTQQ2PS], (instrs VCVTQQ2PSZrr, VCVTQQ2PSZrrb, VCVTQQ2PSZrrbkz, VCVTQQ2PSZrrkz,
+ VCVTUQQ2PSZrr, VCVTUQQ2PSZrrb, VCVTUQQ2PSZrrbkz, VCVTUQQ2PSZrrkz)>;
+
+def 4GM7WriteVCVTQQ2PSLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVCVTQQ2PS.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVCVTQQ2PSLd], (instrs VCVTQQ2PSZrm, VCVTQQ2PSZrmb, VCVTQQ2PSZrmbkz, VCVTQQ2PSZrmkz,
+ VCVTUQQ2PSZrm, VCVTUQQ2PSZrmb, VCVTUQQ2PSZrmbkz, VCVTUQQ2PSZrmkz)>;
+
+
+// VCVTNE2PS2BF16Z128
+def 4GM7WriteVCVTNE2PS2BF16Z128:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 9;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVCVTNE2PS2BF16Z128], (instrs VCVTNE2PS2BF16Z128rr,
+ VCVTNE2PS2BF16Z128rrkz)>;
+
+def 4GM7WriteVCVTNE2PS2BF16Z128Ld:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVCVTNE2PS2BF16Z128.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVCVTNE2PS2BF16Z128Ld], (instrs VCVTNE2PS2BF16Z128rm,
+ VCVTNE2PS2BF16Z128rmkz)>;
+
+// VCVTNE2PS2BF16Z VCVTNE2PS2BF16Z256 VCVTNEPS2BF16
+def 4GM7WriteVCVTNEPS2BF16:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 5;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVCVTNEPS2BF16], (instrs VCVTNE2PS2BF16Z256rrk,
+ VCVTNEPS2BF16Z128rrk, VCVTNEPS2BF16Z256rrk)>;
+
+def 4GM7WriteVCVTNEPS2BF16Ld:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVCVTNEPS2BF16.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVCVTNEPS2BF16Ld], (instrs VCVTNE2PS2BF16Z256rmk,
+ VCVTNEPS2BF16Z128rmk, VCVTNEPS2BF16Z256rmk)>;
+
+
+defm : 4GM7WriteResFPPair<WriteFSign, [4GM7FPU1], 1>;
+defm : 4GM7WriteResFPPair<WriteFRnd, [4GM7FPU13], 4, [1], 1>;
+defm : 4GM7WriteResFPPair<WriteFRndY, [4GM7FPU13], 4, [1], 1>;
+defm : 4GM7WriteResFPPair<WriteFRndZ, [4GM7FPU13], 4, [2], 2>;
+defm : 4GM7WriteResFPPair<WriteFLogic, [4GM7FPU], 1>;
+defm : 4GM7WriteResFPPair<WriteFLogicY, [4GM7FPU], 1>;
+defm : 4GM7WriteResFPPair<WriteFLogicZ, [4GM7FPU], 1>;
+defm : 4GM7WriteResFPPair<WriteFTest, [4GM7FPU13], 1, [1], 1>;
+defm : 4GM7WriteResFPPair<WriteFTestY, [4GM7FPU13], 1, [1], 1>;
+defm : 4GM7WriteResFPPair<WriteFTestZ, [4GM7FPU13], 1, [2], 2>;
+defm : 4GM7WriteResFPPair<WriteFShuffle, [4GM7FPU13], 1, [1], 1>;
+defm : 4GM7WriteResFPPair<WriteFShuffleY, [4GM7FPU13], 1, [1], 1>;
+defm : 4GM7WriteResFPPair<WriteFShuffleZ, [4GM7FPU13], 1, [2], 1>;
+defm : 4GM7WriteResFPPair<WriteFVarShuffle, [4GM7FPU02], 3, [4], 1>;
+defm : 4GM7WriteResFPPair<WriteFVarShuffleY,[4GM7FPU02], 3, [4], 1>;
+defm : 4GM7WriteResFPPair<WriteFVarShuffleZ,[4GM7FPU02], 5, [8], 1>;
+defm : 4GM7WriteResFPPair<WriteFShuffle256, [4GM7FPU02], 3>;
+defm : 4GM7WriteResFPPair<WriteFVarShuffle256, [4GM7FPU02], 3>;
+
+defm : 4GM7WriteRes<WriteVecLoad, [4GM7AGU, 4GM7Load], !add(C864GM7Model.VecLoadLatency, 1), [1, 1], 1>;
+defm : 4GM7WriteRes<WriteVecLoadX, [4GM7AGU, 4GM7Load], !add(C864GM7Model.VecLoadLatency, 1), [1, 1], 1>;
+defm : 4GM7WriteRes<WriteVecLoadY, [4GM7AGU, 4GM7Load], !add(C864GM7Model.VecLoadLatency, 1), [1, 1], 1>;
+defm : 4GM7WriteRes<WriteVecLoadNT, [4GM7AGU, 4GM7Load], !add(C864GM7Model.VecLoadLatency, 1), [1, 1], 1>;
+defm : 4GM7WriteRes<WriteVecLoadNTY, [4GM7AGU, 4GM7Load], !add(C864GM7Model.VecLoadLatency, 1), [1, 1], 1>;
+defm : 4GM7WriteRes<WriteVecMaskedLoad, [4GM7AGU, 4GM7Load, 4GM7FPU01], !add(C864GM7Model.VecLoadLatency, 1), [1, 1, 2], 1>;
+defm : 4GM7WriteRes<WriteVecMaskedLoadY, [4GM7AGU, 4GM7Load, 4GM7FPU01], !add(C864GM7Model.VecLoadLatency, 1), [1, 1, 2], 1>;
+defm : 4GM7WriteRes<WriteVecStore, [4GM7AGU, 4GM7Store], C864GM7Model.StoreLatency>;
+defm : 4GM7WriteRes<WriteVecStoreX, [4GM7AGU, 4GM7Store], C864GM7Model.StoreLatency>;
+defm : 4GM7WriteRes<WriteVecStoreY, [4GM7AGU, 4GM7Store], C864GM7Model.StoreLatency>;
+defm : 4GM7WriteRes<WriteVecStoreNT, [4GM7FPU1, 4GM7AGU, 4GM7Store], !add(1, C864GM7Model.StoreLatency)>;
+defm : 4GM7WriteRes<WriteVecStoreNTY, [4GM7FPU1, 4GM7AGU, 4GM7Store], !add(1, C864GM7Model.StoreLatency)>;
+defm : 4GM7WriteRes<WriteVecMaskedStore32, [4GM7FPU01, 4GM7AGU, 4GM7Store], !add(1, C864GM7Model.StoreLatency)>;
+defm : 4GM7WriteRes<WriteVecMaskedStore32Y, [4GM7FPU01, 4GM7AGU, 4GM7Store], !add(1, C864GM7Model.StoreLatency)>;
+defm : 4GM7WriteRes<WriteVecMaskedStore64, [4GM7FPU01, 4GM7AGU, 4GM7Store], !add(1, C864GM7Model.StoreLatency)>;
+defm : 4GM7WriteRes<WriteVecMaskedStore64Y, [4GM7FPU01, 4GM7AGU, 4GM7Store], !add(1, C864GM7Model.StoreLatency)>;
+defm : 4GM7WriteRes<WriteVecMoveToGpr, [4GM7FPU13], 1, [2], 1>;
+defm : 4GM7WriteRes<WriteVecMoveFromGpr, [4GM7FPU], 1, [4], 2>;
+defm : 4GM7WriteRes<WriteEMMS, [], 0, [], 1>;
+
+defm : 4GM7WriteResFPPair<WriteVecShift, [4GM7FPU02], 1>; // from llvm-exegesis
+defm : 4GM7WriteResFPPair<WriteVecShiftX, [4GM7FPU02], 3>;
+defm : 4GM7WriteResFPPair<WriteVecShiftY, [4GM7FPU02], 3>;
+defm : 4GM7WriteResFPPair<WriteVecShiftZ, [4GM7FPU02], 3, [2], 1>;
+defm : 4GM7WriteResFPPair<WriteVecShiftImm, [4GM7FPU02], 1>;
+defm : 4GM7WriteResFPPair<WriteVecShiftImmX, [4GM7FPU02], 1>;
+defm : 4GM7WriteResFPPair<WriteVecShiftImmY, [4GM7FPU02], 1>;
+defm : 4GM7WriteResFPPair<WriteVecShiftImmZ, [4GM7FPU02], 1, [2], 1>;
+defm : 4GM7WriteResFPPair<WriteVarVecShift, [4GM7FPU02], 1, [4], 1>;
+defm : 4GM7WriteResFPPair<WriteVarVecShiftY, [4GM7FPU02], 1, [4], 1>;
+defm : 4GM7WriteResFPPair<WriteVarVecShiftZ, [4GM7FPU02], 1, [8], 1>;
+defm : 4GM7WriteResFPPair<WriteVecLogic, [4GM7FPU], 1>;
+defm : 4GM7WriteResFPPair<WriteVecLogicX, [4GM7FPU], 1>;
+defm : 4GM7WriteResFPPair<WriteVecLogicY, [4GM7FPU], 1>;
+defm : 4GM7WriteResFPPair<WriteVecLogicZ, [4GM7FPU], 1>;
+defm : 4GM7WriteResFPPair<WriteVecTest, [4GM7FPU13], 1>;
+defm : 4GM7WriteResFPPair<WriteVecTestY, [4GM7FPU13], 1>;
+defm : 4GM7WriteResFPPair<WriteVecTestZ, [4GM7FPU13], 1, [2], 1>;
+defm : 4GM7WriteResFPPair<WriteVecALU, [4GM7FPU], 1>;
+defm : 4GM7WriteResFPPair<WriteVecALUX, [4GM7FPU], 1>;
+defm : 4GM7WriteResFPPair<WriteVecALUY, [4GM7FPU], 1>;
+defm : 4GM7WriteResFPPair<WriteVecALUZ, [4GM7FPU], 1, [2], 1>;
+defm : 4GM7WriteResFPPair<WriteVecIMul, [4GM7FPU02], 3>;
+defm : 4GM7WriteResFPPair<WriteVecIMulX, [4GM7FPU02], 3>;
+defm : 4GM7WriteResFPPair<WriteVecIMulY, [4GM7FPU02], 3>;
+defm : 4GM7WriteResFPPair<WriteVecIMulZ, [4GM7FPU02], 3, [2], 1>;
+defm : 4GM7WriteRes<WriteCLMul, [4GM7FPU02], 3>;
+defm : 4GM7WriteRes<WriteCLMulLd, [4GM7AGU, 4GM7Load, 4GM7FPU02], !add(C864GM7Model.VecLoadLatency, 3)>;
+defm : 4GM7WriteResFPPair<WritePMULLD, [4GM7FPU02], 3>;
+defm : 4GM7WriteResFPPair<WritePMULLDY, [4GM7FPU02], 3>;
+defm : 4GM7WriteResFPPair<WritePMULLDZ, [4GM7FPU02], 3, [2], 1>;
+defm : 4GM7WriteResFPPair<WriteShuffle, [4GM7FPU13], 1>;
+defm : 4GM7WriteResFPPair<WriteShuffleX, [4GM7FPU13], 1>;
+defm : 4GM7WriteResFPPair<WriteShuffleY, [4GM7FPU13], 1>;
+defm : 4GM7WriteResFPPair<WriteShuffleZ, [4GM7FPU13], 1, [2], 1>;
+defm : 4GM7WriteResFPPair<WriteVarShuffle, [4GM7FPU13], 1>;
+defm : 4GM7WriteResFPPair<WriteVarShuffleX,[4GM7FPU13], 1>;
+defm : 4GM7WriteResFPPair<WriteVarShuffleY,[4GM7FPU13], 1>;
+defm : 4GM7WriteResFPPair<WriteVarShuffleZ,[4GM7FPU13], 1, [2], 1>;
+defm : 4GM7WriteResFPPair<WriteBlend, [4GM7FPU], 1>;
+defm : 4GM7WriteResFPPair<WriteBlendY, [4GM7FPU], 1>;
+defm : 4GM7WriteResFPPair<WriteBlendZ, [4GM7FPU], 1, [2], 1>;
+defm : 4GM7WriteResFPPair<WriteVarBlend, [4GM7FPU], 1>;
+defm : 4GM7WriteResFPPair<WriteVarBlendY, [4GM7FPU], 1>;
+defm : 4GM7WriteResFPPair<WriteVarBlendZ, [4GM7FPU], 1, [2], 1>;
+defm : 4GM7WriteResFPPair<WriteShuffle256, [4GM7FPU01], 3>;
+defm : 4GM7WriteResFPPair<WriteVPMOV256, [4GM7FPU02], 3>;
+defm : 4GM7WriteResFPPair<WriteVarShuffle256, [4GM7FPU3, 4GM7FPU02], 2, [2, 2], 2>;
+defm : 4GM7WriteResFPPair<WritePSADBW, [4GM7FPU02], 3, [2], 1>;
+defm : 4GM7WriteResFPPair<WritePSADBWX, [4GM7FPU02], 3, [2], 1>;
+defm : 4GM7WriteResFPPair<WritePSADBWY, [4GM7FPU02], 3, [2], 1>;
+defm : 4GM7WriteResFPPair<WritePSADBWZ, [4GM7FPU02], 3, [4], 1>;
+defm : 4GM7WriteResFPPair<WriteMPSAD, [4GM7FPU], 4, [8], 1>;
+defm : 4GM7WriteResFPPair<WriteMPSADY, [4GM7FPU], 4, [8], 1>;
+defm : 4GM7WriteResFPPair<WriteMPSADZ, [4GM7FPU], 4, [16], 1>;
+defm : 4GM7WriteResFPPair<WritePHMINPOS, [4GM7FPU02], 3, [2], 1>;
+
+// EXTRQ INSERTQ
+def 4GM7WriteEXTRQ_INSERTQ:SchedWriteRes<[4GM7FPU]> {
+ let Latency = 3;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteEXTRQ_INSERTQ], (instrs EXTRQ, EXTRQI, INSERTQ, INSERTQI)>;
+
+// VPCMP
+def 4GM7WriteVPCMPXY:SchedWriteRes<[4GM7FPU, 4GM7FPU13]> {
+ let Latency = 6;
+ let ReleaseAtCycles = [2, 1];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVPCMPXY], (instregex "VPCMPEQ(B|D|Q|W)(Z128|Z256)rrk$",
+ "VPCMPGT(B|D|Q|W)(Z128|Z256)rrk$",
+ "VPCMP(U)?(B|D|Q|W)(Z128|Z256)rrik$")>;
+
+def 4GM7WriteVPCMPXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPCMPXY.Latency);
+ let ReleaseAtCycles = [1, 1, 2, 1];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVPCMPXYLd], (instregex "VPCMPEQ(B|D|Q|W)(Z128|Z256)rmk$",
+ "VPCMPGT(B|D|Q|W)(Z128|Z256)rmk$",
+ "VPCMP(U)?(B|D|Q|W)(Z128|Z256)rmik$")>;
+
+def 4GM7WriteVPCMPZ:SchedWriteRes<[4GM7FPU, 4GM7FPU13]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [12, 6];
+ let NumMicroOps = 4;
+}
+def : InstRW<[4GM7WriteVPCMPZ], (instregex "VPCMPEQ(B|D|Q|W)Zrrk$",
+ "VPCMPGT(B|D|Q|W)Zrrk$",
+ "VPCMP(U)?(B|D|Q|W)Zrrik$")>;
+
+def 4GM7WriteVPCMPZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPCMPZ.Latency);
+ let ReleaseAtCycles = [1, 1, 12, 6];
+ let NumMicroOps = 4;
+}
+def : InstRW<[4GM7WriteVPCMPZLd], (instregex "VPCMPEQ(B|D|Q|W)Zrmk$",
+ "VPCMPGT(B|D|Q|W)Zrmk$",
+ "VPCMP(U)?(B|D|Q|W)Zrmik$")>;
+
+// VPSHUFBIT
+def 4GM7WriteVPSHUFBIT:SchedWriteRes<[4GM7FPU02, 4GM7FPU13]> {
+ let Latency = 8;
+ let ReleaseAtCycles = [4, 4];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVPSHUFBIT], (instrs VPSHUFBITQMBZ128rrk, VPSHUFBITQMBZ256rrk)>;
+
+def 4GM7WriteVPSHUFBITLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPSHUFBIT.Latency);
+ let ReleaseAtCycles = [1, 1, 4, 4];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVPSHUFBITLd], (instrs VPSHUFBITQMBZ128rmk, VPSHUFBITQMBZ256rmk)>;
+
+def 4GM7WriteVPSHUFBITZ:SchedWriteRes<[4GM7FPU02, 4GM7FPU13]> {
+ let Latency = 10;
+ let ReleaseAtCycles = [8, 8];
+ let NumMicroOps = 4;
+}
+def : InstRW<[4GM7WriteVPSHUFBITZ], (instrs VPSHUFBITQMBZrrk)>;
+
+def 4GM7WriteVPSHUFBITZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPSHUFBITZ.Latency);
+ let ReleaseAtCycles = [1, 1, 8, 8];
+ let NumMicroOps = 3;
+}
+def : InstRW<[4GM7WriteVPSHUFBITZLd], (instrs VPSHUFBITQMBZrmk)>;
+
+// VSHUF VPSHUFB VPSHUFLW VPSHUFHW
+def 4GM7WriteVPSHUFXY:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 2;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPSHUFXY], (instrs VSHUFPSZ128rrik, VSHUFPDZ128rrik,
+ VSHUFPSZ256rrik, VSHUFPDZ256rrik,
+ VPSHUFBZ128rrk, VPSHUFBZ128rrkz,
+ VPSHUFHWZ128rik, VPSHUFHWZ128rikz,
+ VPSHUFLWZ128rik, VPSHUFLWZ128rikz,
+ VPSHUFBZ256rrk, VPSHUFBZ256rrkz,
+ VPSHUFHWZ256rik, VPSHUFHWZ256rikz,
+ VPSHUFLWZ256rik, VPSHUFLWZ256rikz)>;
+
+def 4GM7WriteVPSHUFXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPSHUFXY.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPSHUFXYLd], (instrs VSHUFPSZ128rmik, VSHUFPDZ128rmik,
+ VSHUFPSZ256rmik, VSHUFPDZ256rmik,
+ VPSHUFBZ128rmk, VPSHUFBZ128rmkz,
+ VPSHUFHWZ128mik, VPSHUFHWZ128mikz,
+ VPSHUFLWZ128mik, VPSHUFLWZ128mikz,
+ VPSHUFBZ256rmk, VPSHUFBZ256rmkz,
+ VPSHUFHWZ256mik, VPSHUFHWZ256mikz,
+ VPSHUFLWZ256mik, VPSHUFLWZ256mikz)>;
+
+def 4GM7WriteVPSHUFZ:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 2;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPSHUFZ], (instrs VSHUFPSZrrik, VSHUFPDZrrik,
+ VPSHUFBZrrk, VPSHUFBZrrkz,
+ VPSHUFHWZrik, VPSHUFHWZrikz,
+ VPSHUFLWZrik, VPSHUFLWZrikz)>;
+
+def 4GM7WriteVPSHUFZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPSHUFZ.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPSHUFZLd], (instrs VSHUFPSZrmik, VSHUFPDZrmik,
+ VPSHUFBZrmk, VPSHUFBZrmkz,
+ VPSHUFHWZmik, VPSHUFHWZmikz,
+ VPSHUFLWZmik, VPSHUFLWZmikz)>;
+
+// VSHUFF VSHUFI
+def 4GM7WriteVSHUFFY_VSHUFIY:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 3;
+ let ReleaseAtCycles = [4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVSHUFFY_VSHUFIY], (instrs VSHUFF32X4Z256rrik, VSHUFF64X2Z256rrik,
+ VSHUFI32X4Z256rrik, VSHUFI64X2Z256rrik)>;
+
+def 4GM7WriteVSHUFFY_VSHUFIYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVSHUFFY_VSHUFIY.Latency);
+ let ReleaseAtCycles = [1, 1, 4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVSHUFFY_VSHUFIYLd], (instrs VSHUFF32X4Z256rmik, VSHUFF64X2Z256rmik,
+ VSHUFI32X4Z256rmik, VSHUFI64X2Z256rmik)>;
+
+def 4GM7WriteVSHUFFZ_VSHUFIZ:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 3;
+ let ReleaseAtCycles = [8];
+ let NumMicroOps = 4;
+}
+def : InstRW<[4GM7WriteVSHUFFZ_VSHUFIZ], (instrs VSHUFF32X4Zrri, VSHUFF32X4Zrrik, VSHUFF32X4Zrrikz,
+ VSHUFF64X2Zrri, VSHUFF64X2Zrrik, VSHUFF64X2Zrrikz,
+ VSHUFI32X4Zrri, VSHUFI32X4Zrrik, VSHUFI32X4Zrrikz,
+ VSHUFI64X2Zrri, VSHUFI64X2Zrrik, VSHUFI64X2Zrrikz)>;
+
+def 4GM7WriteVSHUFFZ_VSHUFIZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVSHUFFZ_VSHUFIZ.Latency);
+ let ReleaseAtCycles = [1, 1, 8];
+ let NumMicroOps = 4;
+}
+def : InstRW<[4GM7WriteVSHUFFZ_VSHUFIZLd], (instrs VSHUFF32X4Zrmi, VSHUFF32X4Zrmik, VSHUFF32X4Zrmikz,
+ VSHUFF64X2Zrmi, VSHUFF64X2Zrmik, VSHUFF64X2Zrmikz,
+ VSHUFI32X4Zrmi, VSHUFI32X4Zrmik, VSHUFI32X4Zrmikz,
+ VSHUFI64X2Zrmi, VSHUFI64X2Zrmik, VSHUFI64X2Zrmikz)>;
+
+// UNPCK
+def 4GM7WriteUNPCKXY:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 2;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteUNPCKXY], (instrs VUNPCKLPSZ128rrk, VUNPCKLPDZ128rrk,
+ VUNPCKHPSZ128rrk, VUNPCKHPDZ128rrk,
+ VUNPCKLPSZ256rrk, VUNPCKLPDZ256rrk,
+ VUNPCKHPSZ256rrk, VUNPCKHPDZ256rrk,
+ VPUNPCKHBWZ128rrk, VPUNPCKHBWZ128rrkz,
+ VPUNPCKHWDZ128rrk, VPUNPCKHWDZ128rrkz,
+ VPUNPCKLBWZ128rrk, VPUNPCKLBWZ128rrkz,
+ VPUNPCKLWDZ128rrk, VPUNPCKLWDZ128rrkz,
+ VPUNPCKHBWZ256rrk, VPUNPCKHBWZ256rrkz,
+ VPUNPCKHWDZ256rrk, VPUNPCKHWDZ256rrkz,
+ VPUNPCKLBWZ256rrk, VPUNPCKLBWZ256rrkz,
+ VPUNPCKLWDZ256rrk, VPUNPCKLWDZ256rrkz)>;
+
+def 4GM7WriteUNPCKXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteUNPCKXY.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteUNPCKXYLd], (instrs VUNPCKLPSZ128rmk, VUNPCKLPDZ128rmk,
+ VUNPCKHPSZ128rmk, VUNPCKHPDZ128rmk,
+ VUNPCKLPSZ256rmk, VUNPCKLPDZ256rmk,
+ VUNPCKHPSZ256rmk, VUNPCKHPDZ256rmk,
+ VPUNPCKHBWZ128rmk, VPUNPCKHBWZ128rmkz,
+ VPUNPCKHWDZ128rmk, VPUNPCKHWDZ128rmkz,
+ VPUNPCKLBWZ128rmk, VPUNPCKLBWZ128rmkz,
+ VPUNPCKLWDZ128rmk, VPUNPCKLWDZ128rmkz,
+ VPUNPCKHBWZ256rmk, VPUNPCKHBWZ256rmkz,
+ VPUNPCKHWDZ256rmk, VPUNPCKHWDZ256rmkz,
+ VPUNPCKLBWZ256rmk, VPUNPCKLBWZ256rmkz,
+ VPUNPCKLWDZ256rmk, VPUNPCKLWDZ256rmkz)>;
+
+
+def 4GM7WriteUNPCKZ:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 2;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteUNPCKZ], (instrs VUNPCKLPSZrrk, VUNPCKLPDZrrk,
+ VUNPCKHPSZrrk, VUNPCKHPDZrrk,
+ VPUNPCKHBWZrrk, VPUNPCKHBWZrrkz,
+ VPUNPCKHWDZrrk, VPUNPCKHWDZrrkz,
+ VPUNPCKLBWZrrk, VPUNPCKLBWZrrkz,
+ VPUNPCKLWDZrrk, VPUNPCKLWDZrrkz)>;
+
+def 4GM7WriteUNPCKZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteUNPCKZ.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteUNPCKZLd], (instrs VUNPCKLPSZrmk, VUNPCKLPDZrmk,
+ VUNPCKHPSZrmk, VUNPCKHPDZrmk,
+ VPUNPCKHBWZrmk, VPUNPCKHBWZrmkz,
+ VPUNPCKHWDZrmk, VPUNPCKHWDZrmkz,
+ VPUNPCKLBWZrmk, VPUNPCKLBWZrmkz,
+ VPUNPCKLWDZrmk, VPUNPCKLWDZrmkz)>;
+
+// POPCNT
+def 4GM7WritePOPCNTZ:SchedWriteRes<[4GM7FPU]> {
+ let Latency = 2;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WritePOPCNTZ], (instrs VPOPCNTBZrrk, VPOPCNTBZrrkz,
+ VPOPCNTWZrrk, VPOPCNTWZrrkz,
+ VPOPCNTBZ128rrk, VPOPCNTBZ128rrkz,
+ VPOPCNTWZ128rrk, VPOPCNTWZ128rrkz,
+ VPOPCNTBZ256rrk, VPOPCNTBZ256rrkz,
+ VPOPCNTWZ256rrk, VPOPCNTWZ256rrkz)>;
+
+def 4GM7WritePOPCNTZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WritePOPCNTZ.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WritePOPCNTZLd], (instrs VPOPCNTBZrmk, VPOPCNTBZrmkz,
+ VPOPCNTWZrmk, VPOPCNTWZrmkz,
+ VPOPCNTBZ128rmk, VPOPCNTBZ128rmkz,
+ VPOPCNTWZ128rmk, VPOPCNTWZ128rmkz,
+ VPOPCNTBZ256rmk, VPOPCNTBZ256rmkz,
+ VPOPCNTWZ256rmk, VPOPCNTWZ256rmkz)>;
+
+// VPABS VPADDS VPADDUS VPAVG VPMAX VPMIN VPADD VPSUB VPTERNLOG
+def 4GM7WriteVecALUZ:SchedWriteRes<[4GM7FPU]> {
+ let Latency = 2;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVecALUZ], (instregex "VPABS(B|W)Z(128|256)?rrk$",
+ "VPADD(U)?S(B|W)Z(128|256)?rrk$",
+ "VPAVG(B|W)Z(128|256)?rrk$",
+ "VPSUB(U)?S(B|W)Z(128|256)?rrk$",
+ "VPMAX(SD|UD|SB|SW|UB|UW)Z(256)?rrk$",
+ "VPMIN(SD|UD|SB|SW|UB|UW)Z(256)?rrk$",
+ "VPADD(B|W)Z(128)?rrk$",
+ "VPADD(D|Q)Zrr(k)?",
+ "VPSUB(B|W)Z(128)?rrk$",
+ "VPSUB(D|Q)Zrrk$",
+ "VPTERNLOG(D|Q)Zrri(k)?")>;
+
+def 4GM7WriteVecALUZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVecALUZ.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVecALUZLd], (instregex "VPABS(B|W)Z(128|256)?rmk$",
+ "VPADD(U)?S(B|W)Z(128|256)?rmk$",
+ "VPAVG(B|W)Z(128|256)?rmk$",
+ "VPSUB(U)?S(B|W)Z(128|256)?rmk$",
+ "VPMAX(SD|UD|SB|SW|UB|UW)Z(256)?rmk$",
+ "VPMIN(SD|UD|SB|SW|UB|UW)Z(256)?rmk$",
+ "VPADD(B|W)Z(128)?rmk$",
+ "VPADD(D|Q)Zrm(k)?$",
+ "VPSUB(B|W)Z(128)?rmk$",
+ "VPSUB(D|Q)Zrmk$",
+ "VPTERNLOG(D|Q)Zrmi(k)?")>;
+
+// WriteVecShift WriteVecShiftImm
+def 4GM7WriteVecShiftZ:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 2;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVecShiftZ], (instrs VPSHLDDZ128rrik, VPSHLDDZ128rrikz, VPSHLDDZ256rrik,
+ VPSHLDDZ256rrikz, VPSHLDDZrrik, VPSHLDDZrrikz,
+ VPSHLDQZ128rrik, VPSHLDQZ128rrikz, VPSHLDQZ256rrik,
+ VPSHLDQZ256rrikz, VPSHLDQZrrik, VPSHLDQZrrikz,
+ VPSHLDVWZ128rk, VPSHLDVWZ128rkz, VPSHLDVWZ256rk,
+ VPSHLDVWZ256rkz, VPSHLDVWZrk, VPSHLDVWZrkz,
+ VPSHLDWZ128rrik, VPSHLDWZ128rrikz, VPSHLDWZ256rrik,
+ VPSHLDWZ256rrikz, VPSHLDWZrrik, VPSHLDWZrrikz,
+ VPSHRDDZ128rrik, VPSHRDDZ128rrikz, VPSHRDDZ256rrik,
+ VPSHRDDZ256rrikz, VPSHRDDZrrik, VPSHRDDZrrikz,
+ VPSHRDQZ128rrik, VPSHRDQZ128rrikz, VPSHRDQZ256rrik,
+ VPSHRDQZ256rrikz, VPSHRDQZrrik, VPSHRDQZrrikz,
+ VPSHRDVWZ128rk, VPSHRDVWZ128rkz, VPSHRDVWZ256rk,
+ VPSHRDVWZ256rkz, VPSHRDVWZrk, VPSHRDVWZrkz,
+ VPSHRDWZ128rrik, VPSHRDWZ128rrikz, VPSHRDWZ256rrik,
+ VPSHRDWZ256rrikz, VPSHRDWZrrik, VPSHRDWZrrikz,
+ VPSLLVWZ128rrk, VPSLLVWZ128rrkz, VPSLLVWZ256rrk,
+ VPSLLVWZ256rrkz, VPSLLVWZrrk, VPSLLVWZrrkz,
+ VPSLLWZ128rik, VPSLLWZ128rikz, VPSLLWZ128rrk,
+ VPSLLWZ128rrkz, VPSLLWZ256rik, VPSLLWZ256rikz,
+ VPSLLWZrik, VPSLLWZrikz, VPSRAVWZ128rrk,
+ VPSRAVWZ128rrkz, VPSRAVWZ256rrk, VPSRAVWZ256rrkz,
+ VPSRAVWZrrk, VPSRAVWZrrkz, VPSRAWZ128rik,
+ VPSRAWZ128rikz, VPSRAWZ128rrk, VPSRAWZ128rrkz,
+ VPSRAWZ256rik, VPSRAWZ256rikz, VPSRAWZrik,
+ VPSRAWZrikz, VPSRLVWZ128rrk, VPSRLVWZ128rrkz,
+ VPSRLVWZ256rrk, VPSRLVWZ256rrkz, VPSRLVWZrrk,
+ VPSRLVWZrrkz, VPSRLWZ128rik, VPSRLWZ128rikz,
+ VPSRLWZ128rrk, VPSRLWZ128rrkz, VPSRLWZ256rik,
+ VPSRLWZ256rikz, VPSRLWZrik, VPSRLWZrikz)>;
+
+def 4GM7WriteVecShiftZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVecShiftZ.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVecShiftZLd], (instrs VPSHLDDZ128rmik, VPSHLDDZ128rmikz, VPSHLDDZ256rmik,
+ VPSHLDDZ256rmikz, VPSHLDDZrmik, VPSHLDDZrmikz,
+ VPSHLDQZ128rmik, VPSHLDQZ128rmikz, VPSHLDQZ256rmik,
+ VPSHLDQZ256rmikz, VPSHLDQZrmik, VPSHLDQZrmikz,
+ VPSHLDVWZ128mk, VPSHLDVWZ128mkz, VPSHLDVWZ256mk,
+ VPSHLDVWZ256mkz, VPSHLDVWZmk, VPSHLDVWZmkz,
+ VPSHLDWZ128rmik, VPSHLDWZ128rmikz, VPSHLDWZ256rmik,
+ VPSHLDWZ256rmikz, VPSHLDWZrmik, VPSHLDWZrmikz,
+ VPSHRDDZ128rmik, VPSHRDDZ128rmikz, VPSHRDDZ256rmik,
+ VPSHRDDZ256rmikz, VPSHRDDZrmik, VPSHRDDZrmikz,
+ VPSHRDQZ128rmik, VPSHRDQZ128rmikz, VPSHRDQZ256rmik,
+ VPSHRDQZ256rmikz, VPSHRDQZrmik, VPSHRDQZrmikz,
+ VPSHRDVWZ128mk, VPSHRDVWZ128mkz, VPSHRDVWZ256mk,
+ VPSHRDVWZ256mkz, VPSHRDVWZmk, VPSHRDVWZmkz,
+ VPSHRDWZ128rmik, VPSHRDWZ128rmikz, VPSHRDWZ256rmik,
+ VPSHRDWZ256rmikz, VPSHRDWZrmik, VPSHRDWZrmikz,
+ VPSLLVWZ128rmk, VPSLLVWZ128rmkz, VPSLLVWZ256rmk,
+ VPSLLVWZ256rmkz, VPSLLVWZrmk, VPSLLVWZrmkz,
+ VPSLLWZ128mik, VPSLLWZ128mikz, VPSLLWZ128rmk,
+ VPSLLWZ128rmkz, VPSLLWZ256mik, VPSLLWZ256mikz,
+ VPSLLWZmik, VPSLLWZmikz, VPSRAVWZ128rmk,
+ VPSRAVWZ128rmkz, VPSRAVWZ256rmk, VPSRAVWZ256rmkz,
+ VPSRAVWZrmk, VPSRAVWZrmkz, VPSRAWZ128mik,
+ VPSRAWZ128mikz, VPSRAWZ128rmk, VPSRAWZ128rmkz,
+ VPSRAWZ256mik, VPSRAWZ256mikz, VPSRAWZmik,
+ VPSRAWZmikz, VPSRLVWZ128rmk, VPSRLVWZ128rmkz,
+ VPSRLVWZ256rmk, VPSRLVWZ256rmkz, VPSRLVWZrmk,
+ VPSRLVWZrmkz, VPSRLWZ128mik, VPSRLWZ128mikz,
+ VPSRLWZ128rmk, VPSRLWZ128rmkz, VPSRLWZ256mik,
+ VPSRLWZ256mikz, VPSRLWZmik, VPSRLWZmikz)>;
+
+def 4GM7WriteVecShiftZrrk:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVecShiftZrrk], (instrs VPSLLDZrrk, VPSLLQZrrk, VPSRADZrrk,
+ VPSRAQZrrk, VPSRLDZrrk, VPSRLQZrrk,
+ VPSLLWZrrk, VPSRAWZrrk, VPSRLWZrrk,
+ VPSLLDZ256rrk, VPSLLQZ256rrk, VPSRADZ256rrk,
+ VPSRAQZ256rrk, VPSRLDZ256rrk, VPSRLQZ256rrk,
+ VPSLLWZ256rrk, VPSRAWZ256rrk, VPSRLWZ256rrk)>;
+
+def 4GM7WriteVecShiftZrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVecShiftZrrk.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVecShiftZrmk], (instrs VPSLLDZrmk, VPSLLQZrmk, VPSRADZrmk,
+ VPSRAQZrmk, VPSRLDZrmk, VPSRLQZrmk,
+ VPSLLWZrmk, VPSRAWZrmk, VPSRLWZrmk,
+ VPSLLDZ256rmk, VPSLLQZ256rmk, VPSRADZ256rmk,
+ VPSRAQZ256rmk, VPSRLDZ256rmk, VPSRLQZ256rmk,
+ VPSLLWZ256rmk, VPSRAWZ256rmk, VPSRLWZ256rmk)>;
+
+def 4GM7WriteVecShift:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 1;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVecShift], (instrs PSLLDrr, PSLLQrr, PSLLWrr, PSRADrr,
+ PSRAWrr, PSRLDrr,PSRLQrr, PSRLWrr,
+ VPSHLDDZ128rri, VPSHLDDZ256rri, VPSHLDDZrri,
+ VPSHLDQZ128rri, VPSHLDQZ256rri, VPSHLDQZrri,
+ VPSHLDVDZ128r, VPSHLDVDZ128rk, VPSHLDVDZ128rkz,
+ VPSHLDVDZ256r, VPSHLDVDZ256rk, VPSHLDVDZ256rkz,
+ VPSHLDVDZr, VPSHLDVDZrk, VPSHLDVDZrkz,
+ VPSHLDVQZ128r, VPSHLDVQZ128rk, VPSHLDVQZ128rkz,
+ VPSHLDVQZ256r, VPSHLDVQZ256rk, VPSHLDVQZ256rkz,
+ VPSHLDVQZr, VPSHLDVQZrk, VPSHLDVQZrkz,
+ VPSHLDVWZ128r, VPSHLDVWZ256r, VPSHLDVWZr,
+ VPSHLDWZ128rri, VPSHLDWZ256rri, VPSHLDWZrri,
+ VPSHRDDZ128rri, VPSHRDDZ256rri, VPSHRDDZrri,
+ VPSHRDQZ128rri, VPSHRDQZ256rri, VPSHRDQZrri,
+ VPSHRDVDZ128r, VPSHRDVDZ128rk, VPSHRDVDZ128rkz,
+ VPSHRDVDZ256r, VPSHRDVDZ256rk, VPSHRDVDZ256rkz,
+ VPSHRDVDZr, VPSHRDVDZrk, VPSHRDVDZrkz,
+ VPSHRDVQZ128r, VPSHRDVQZ128rk, VPSHRDVQZ128rkz,
+ VPSHRDVQZ256r, VPSHRDVQZ256rk, VPSHRDVQZ256rkz,
+ VPSHRDVQZr, VPSHRDVQZrk, VPSHRDVQZrkz,
+ VPSHRDVWZ128r, VPSHRDVWZ256r, VPSHRDVWZr,
+ VPSHRDWZ128rri, VPSHRDWZ256rri, VPSHRDWZrri,
+ VPSLLDrr, VPSLLDZ128rr, VPSLLDZ128rrk,
+ VPSLLDZ128rrkz, VPSLLQrr, VPSLLQZ128rr,
+ VPSLLQZ128rrk, VPSLLQZ128rrkz, VPSLLWrr,
+ VPSLLWZ128rr, VPSRADrr, VPSRADZ128rr,
+ VPSRADZ128rrk, VPSRADZ128rrkz, VPSRAQZ128rr,
+ VPSRAQZ128rrk, VPSRAQZ128rrkz, VPSRAWrr,
+ VPSRAWZ128rr, VPSRLDrr, VPSRLDZ128rr,
+ VPSRLDZ128rrk, VPSRLDZ128rrkz, VPSRLQrr,
+ VPSRLQZ128rr, VPSRLQZ128rrk, VPSRLQZ128rrkz,
+ VPSRLWrr, VPSRLWZ128rr)>;
+
+def 4GM7WriteVecShiftLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVecShift.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVecShiftLd], (instrs PSLLDrm, PSLLQrm, PSLLWrm, PSRADrm,
+ PSRAWrm, PSRLDrm,PSRLQrm, PSRLWrm,
+ VPSHLDDZ128rmi, VPSHLDDZ256rmi, VPSHLDDZrmi,
+ VPSHLDQZ128rmi, VPSHLDQZ256rmi, VPSHLDQZrmi,
+ VPSHLDVDZ128m, VPSHLDVDZ128mk, VPSHLDVDZ128mkz,
+ VPSHLDVDZ256m, VPSHLDVDZ256mk, VPSHLDVDZ256mkz,
+ VPSHLDVDZm, VPSHLDVDZmk, VPSHLDVDZmkz,
+ VPSHLDVQZ128m, VPSHLDVQZ128mk, VPSHLDVQZ128mkz,
+ VPSHLDVQZ256m, VPSHLDVQZ256mk, VPSHLDVQZ256mkz,
+ VPSHLDVQZm, VPSHLDVQZmk, VPSHLDVQZmkz,
+ VPSHLDVWZ128m, VPSHLDVWZ256m, VPSHLDVWZm,
+ VPSHLDWZ128rmi, VPSHLDWZ256rmi, VPSHLDWZrmi,
+ VPSHRDDZ128rmi, VPSHRDDZ256rmi, VPSHRDDZrmi,
+ VPSHRDQZ128rmi, VPSHRDQZ256rmi, VPSHRDQZrmi,
+ VPSHRDVDZ128m, VPSHRDVDZ128mk, VPSHRDVDZ128mkz,
+ VPSHRDVDZ256m, VPSHRDVDZ256mk, VPSHRDVDZ256mkz,
+ VPSHRDVDZm, VPSHRDVDZmk, VPSHRDVDZmkz,
+ VPSHRDVQZ128m, VPSHRDVQZ128mk, VPSHRDVQZ128mkz,
+ VPSHRDVQZ256m, VPSHRDVQZ256mk, VPSHRDVQZ256mkz,
+ VPSHRDVQZm, VPSHRDVQZmk, VPSHRDVQZmkz,
+ VPSHRDVWZ128m, VPSHRDVWZ256m, VPSHRDVWZm,
+ VPSHRDWZ128rmi, VPSHRDWZ256rmi, VPSHRDWZrmi,
+ VPSLLDrm, VPSLLDZ128rm, VPSLLDZ128rmk,
+ VPSLLDZ128rmkz, VPSLLQrm, VPSLLQZ128rm,
+ VPSLLQZ128rmk, VPSLLQZ128rmkz, VPSLLWrm,
+ VPSLLWZ128rm, VPSRADrm, VPSRADZ128rm,
+ VPSRADZ128rmk, VPSRADZ128rmkz, VPSRAQZ128rm,
+ VPSRAQZ128rmk, VPSRAQZ128rmkz, VPSRAWrm,
+ VPSRAWZ128rm, VPSRLDrm, VPSRLDZ128rm,
+ VPSRLDZ128rmk, VPSRLDZ128rmkz, VPSRLQrm,
+ VPSRLQZ128rm, VPSRLQZ128rmk, VPSRLQZ128rmkz,
+ VPSRLWrm, VPSRLWZ128rm)>;
+
+// VCMP
+def 4GM7WriteVCMPXY:SchedWriteRes<[4GM7FPU02, 4GM7FPU13]> {
+ let Latency = 5;
+ let ReleaseAtCycles = [1, 1];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVCMPXY], (instrs VCMPPDZ128rrik, VCMPPSZ128rrik,
+ VCMPPDZ256rrik, VCMPPSZ256rrik)>;
+
+def 4GM7WriteVCMPXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVCMPXY.Latency);
+ let ReleaseAtCycles = [1, 1, 1, 1];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVCMPXYLd], (instrs VCMPPDZ128rmik, VCMPPSZ128rmik,
+ VCMPPDZ256rmik, VCMPPSZ256rmik)>;
+
+def 4GM7WriteVCMPZ:SchedWriteRes<[4GM7FPU02, 4GM7FPU13]> {
+ let Latency = 5;
+ let ReleaseAtCycles = [10, 10];
+ let NumMicroOps = 4;
+}
+def : InstRW<[4GM7WriteVCMPZ], (instrs VCMPPSZrribk, VCMPPSZrrik,
+ VCMPPDZrribk, VCMPPDZrrik,
+ VCMPSSZrrik_Int, VCMPSSZrribk_Int,
+ VCMPSDZrribk_Int, VCMPSDZrrik_Int)>;
+
+def 4GM7WriteVCMPZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVCMPZ.Latency);
+ let ReleaseAtCycles = [1, 1, 10, 10];
+ let NumMicroOps = 4;
+}
+def : InstRW<[4GM7WriteVCMPZLd], (instrs VCMPPSZrmik, VCMPPDZrmik,
+ VCMPSSZrmik_Int, VCMPSDZrmik_Int)>;
+
+// VFPCLASS
+def 4GM7WriteVFPCLASSXY:SchedWriteRes<[4GM7FPU13, 4GM7FPU13]> {
+ let Latency = 5;
+ let ReleaseAtCycles = [2, 2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVFPCLASSXY], (instrs VFPCLASSPDZ128rik, VFPCLASSPSZ128rik,
+ VFPCLASSPDZ256rik, VFPCLASSPSZ256rik)>;
+
+def 4GM7WriteVFPCLASSXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVFPCLASSXY.Latency);
+ let ReleaseAtCycles = [1, 1, 2, 2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVFPCLASSXYLd], (instrs VFPCLASSPDZ128mik, VFPCLASSPSZ128mik,
+ VFPCLASSPDZ256mik, VFPCLASSPSZ256mik)>;
+
+def 4GM7WriteVFPCLASSZ:SchedWriteRes<[4GM7FPU13, 4GM7FPU13]> {
+ let Latency = 5;
+ let ReleaseAtCycles = [4, 4];
+ let NumMicroOps = 4;
+}
+def : InstRW<[4GM7WriteVFPCLASSZ], (instrs VFPCLASSSDZrik, VFPCLASSSSZrik)>;
+
+def 4GM7WriteVFPCLASSZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVFPCLASSZ.Latency);
+ let ReleaseAtCycles = [1, 1, 4, 4];
+ let NumMicroOps = 4;
+}
+def : InstRW<[4GM7WriteVFPCLASSZLd], (instrs VFPCLASSSDZmik, VFPCLASSSSZmik)>;
+
+def 4GM7WriteVFPCLASSZrik:SchedWriteRes<[4GM7FPU13, 4GM7FPU13]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [4, 4];
+ let NumMicroOps = 4;
+}
+def : InstRW<[4GM7WriteVFPCLASSZrik], (instrs VFPCLASSPDZrik, VFPCLASSPSZrik)>;
+
+def 4GM7WriteVFPCLASSZrikLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVFPCLASSZrik.Latency);
+ let ReleaseAtCycles = [1, 1, 4, 4];
+ let NumMicroOps = 4;
+}
+def : InstRW<[4GM7WriteVFPCLASSZrikLd], (instrs VFPCLASSPDZmik, VFPCLASSPSZmik)>;
+
+// VRNDSCALE
+def 4GM7WriteVRNDSCALEXY:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 5;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVRNDSCALEXY], (instrs VRNDSCALEPDZ128rrik, VRNDSCALEPSZ128rrik,
+ VRNDSCALEPDZ256rrik, VRNDSCALEPSZ256rrik)>;
+
+def 4GM7WriteVRNDSCALEXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVRNDSCALEXY.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVRNDSCALEXYLd], (instrs VRNDSCALEPDZ128rmik, VRNDSCALEPSZ128rmik,
+ VRNDSCALEPDZ256rmik, VRNDSCALEPSZ256rmik)>;
+
+def 4GM7WriteVRNDSCALEZ:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 5;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVRNDSCALEZ], (instrs VRNDSCALESDZrribk_Int, VRNDSCALESDZrrik_Int,
+ VRNDSCALESSZrribk_Int, VRNDSCALESSZrrik_Int,
+ VRNDSCALEPDZrribk, VRNDSCALEPDZrrik,
+ VRNDSCALEPSZrribk, VRNDSCALEPSZrrik)>;
+
+def 4GM7WriteVRNDSCALEZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVRNDSCALEZ.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVRNDSCALEZLd], (instrs VRNDSCALESDZrmik_Int, VRNDSCALESSZrmik_Int,
+ VRNDSCALEPDZrmik, VRNDSCALEPSZrmik)>;
+
+// VREDUCE
+def 4GM7WriteVREDUCEXY:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 5;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVREDUCEXY], (instrs VREDUCEPDZ128rrik, VREDUCEPSZ128rrik,
+ VREDUCEPDZ256rrik, VREDUCEPSZ256rrik)>;
+
+def 4GM7WriteVREDUCEXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVREDUCEXY.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVREDUCEXYLd], (instrs VREDUCEPDZ128rmik, VREDUCEPSZ128rmik,
+ VREDUCEPDZ256rmik, VREDUCEPSZ256rmik)>;
+
+def 4GM7WriteVREDUCEZ:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 5;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVREDUCEZ], (instrs VREDUCESDZrribk, VREDUCESDZrrik,
+ VREDUCESSZrribk, VREDUCESSZrrik,
+ VREDUCEPDZrribk, VREDUCEPDZrrik,
+ VREDUCEPSZrribk, VREDUCEPSZrrik)>;
+
+def 4GM7WriteVREDUCEZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVREDUCEZ.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVREDUCEZLd], (instrs VREDUCESSZrmik, VREDUCESDZrmik,
+ VREDUCEPSZrmik, VREDUCEPDZrmik)>;
+
+// VGETEXP VGETMANT
+def 4GM7WriteVGETEXPXY_VGETMANTXY:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 5;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVGETEXPXY_VGETMANTXY], (instrs VGETEXPPSZ128rk, VGETEXPPDZ128rk,
+ VGETEXPPSZ256rk, VGETEXPPDZ256rk,
+ VGETMANTPSZ128rrik, VGETMANTPDZ128rrik,
+ VGETMANTPSZ256rrik, VGETMANTPDZ256rrik)>;
+
+def 4GM7WriteVGETEXPXY_VGETMANTXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVGETEXPXY_VGETMANTXY.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVGETEXPXY_VGETMANTXYLd], (instrs VGETEXPPSZ128mk, VGETEXPPDZ128mk,
+ VGETEXPPSZ256mk, VGETEXPPDZ256mk,
+ VGETMANTPSZ128rmik, VGETMANTPDZ128rmik,
+ VGETMANTPSZ256rmik, VGETMANTPDZ256rmik)>;
+
+def 4GM7WriteVGETEXPZ_VGETMANTZ:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 5;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVGETEXPZ_VGETMANTZ], (instrs VGETEXPSSZrbk, VGETEXPSSZrk,
+ VGETEXPSDZrbk, VGETEXPSDZrk,
+ VGETEXPPSZrbk, VGETEXPPSZrk,
+ VGETEXPPDZrbk, VGETEXPPDZrk,
+ VGETMANTSSZrribk, VGETMANTSSZrrik,
+ VGETMANTSDZrribk, VGETMANTSDZrrik,
+ VGETMANTPSZrribk, VGETMANTPSZrrik,
+ VGETMANTPDZrribk, VGETMANTPDZrrik)>;
+
+def 4GM7WriteVGETEXPZ_VGETMANTZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVGETEXPZ_VGETMANTZ.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVGETEXPZ_VGETMANTZLd], (instrs VGETEXPSSZmk, VGETEXPSDZmk,
+ VGETEXPPSZmbk, VGETEXPPSZmk,
+ VGETEXPPDZmbk, VGETEXPPDZmk,
+ VGETMANTSSZrmik, VGETMANTSDZrmik,
+ VGETMANTPSZrmik, VGETMANTPDZrmik)>;
+
+// VSCALEF
+def 4GM7WriteVSCALEFXY:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVSCALEFXY], (instrs VSCALEFPSZ128rr, VSCALEFPSZ128rrkz,
+ VSCALEFPSZ256rr, VSCALEFPSZ256rrkz,
+ VSCALEFPDZ128rr, VSCALEFPDZ128rrkz,
+ VSCALEFPDZ256rr, VSCALEFPDZ256rrkz)>;
+
+def 4GM7WriteVSCALEFXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVSCALEFXY.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVSCALEFXYLd], (instrs VSCALEFPSZ128rm, VSCALEFPSZ128rmkz,
+ VSCALEFPSZ256rm, VSCALEFPSZ256rmkz,
+ VSCALEFPDZ128rm, VSCALEFPDZ128rmkz,
+ VSCALEFPDZ256rm, VSCALEFPDZ256rmkz)>;
+
+def 4GM7WriteVSCALEFZ:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVSCALEFZ], (instrs VSCALEFSSZrr, VSCALEFSSZrrkz,
+ VSCALEFSSZrrb_Int, VSCALEFSSZrrbkz_Int,
+ VSCALEFSDZrr, VSCALEFSDZrrkz,
+ VSCALEFSDZrrb_Int, VSCALEFSDZrrbkz_Int,
+ VSCALEFPSZrr, VSCALEFPSZrrkz,
+ VSCALEFPSZrrb, VSCALEFPSZrrbkz,
+ VSCALEFPDZrr, VSCALEFPDZrrkz,
+ VSCALEFPDZrrb, VSCALEFPDZrrbkz)>;
+
+def 4GM7WriteVSCALEFZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVSCALEFZ.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVSCALEFZLd], (instrs VSCALEFSSZrm, VSCALEFSSZrmkz,
+ VSCALEFSDZrm,
+ VSCALEFPSZrm, VSCALEFPSZrmkz,
+ VSCALEFPSZrmb, VSCALEFPSZrmbkz,
+ VSCALEFPDZrm, VSCALEFPDZrmkz,
+ VSCALEFPDZrmb, VSCALEFPDZrmbkz)>;
+
+def 4GM7WriteVSCALEFXYrrk:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 5;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVSCALEFXYrrk], (instrs VSCALEFPSZ128rrk, VSCALEFPDZ128rrk,
+ VSCALEFPSZ256rrk, VSCALEFPDZ256rrk)>;
+
+def 4GM7WriteVSCALEFXYrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVSCALEFXYrrk.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVSCALEFXYrmk], (instrs VSCALEFPSZ128rmk, VSCALEFPDZ128rmk,
+ VSCALEFPSZ256rmk, VSCALEFPDZ256rmk)>;
+
+def 4GM7WriteVSCALEFZrrk:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 5;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVSCALEFZrrk], (instrs VSCALEFSSZrrk, VSCALEFSSZrrbk_Int,
+ VSCALEFSDZrrk, VSCALEFSDZrrbk_Int,
+ VSCALEFPSZrrk, VSCALEFPSZrrbk,
+ VSCALEFPDZrrk, VSCALEFPDZrrbk)>;
+
+def 4GM7WriteVSCALEFZrmkLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVSCALEFZrrk.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVSCALEFZrmkLd], (instrs VSCALEFSSZrmk, VSCALEFSDZrmk,
+ VSCALEFPSZrmk, VSCALEFPSZrmbk,
+ VSCALEFPDZrmk, VSCALEFPDZrmbk)>;
+
+// VFMA
+def 4GM7WriteVFMAXY:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 5;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVFMAXY], (instregex "VF(MADD|MSUB|MADDSUB|MSUBADD|NMADD|NMSUB)(132|213|231)(PD|PS)(Z128|Z256)r(bk|k)$")>;
+
+def 4GM7WriteVFMAXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVFMAXY.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVFMAXYLd], (instregex "VF(MADD|MSUB|MADDSUB|MSUBADD|NMADD|NMSUB)(132|213|231)(PD|PS)(Z128|Z256)m(bk|k)$")>;
+
+def 4GM7WriteVFMAZ:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 5;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVFMAZ], (instregex "VF(MADD|MSUB|MADDSUB|MSUBADD|NMADD|NMSUB)(132|213|231)(PD|PS)Zr(bk|k)$",
+ "VF(MADD|MSUB|NMADD|NMSUB)(132|213|231)(SD|SS)Zr(bk|k)_Int")>;
+
+def 4GM7WriteVFMAZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVFMAZ.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVFMAZLd], (instregex "VF(MADD|MSUB|MADDSUB|MSUBADD|NMADD|NMSUB)(132|213|231)(PD|PS)Zm(bk|k)$",
+ "VF(MADD|MSUB|NMADD|NMSUB)(132|213|231)(SD|SS)Zm(bk|k)_Int")>;
+
+// VPROL VPROR
+def 4GM7WriteVPROLXY_VPRORXY:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 3;
+ let ReleaseAtCycles = [4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPROLXY_VPRORXY], (instregex "VPRO(L|R)V(D|Q)(Z128|Z256)(rr|rrkz)$")>;
+
+def 4GM7WriteVPROLXY_VPRORXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPROLXY_VPRORXY.Latency);
+ let ReleaseAtCycles = [1, 1, 4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPROLXY_VPRORXYLd], (instregex "VPRO(L|R)V(D|Q)(Z128|Z256)(rm|rmkz)$")>;
+
+def 4GM7WriteVPROLXY_VPRORXYrrk:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPROLXY_VPRORXYrrk], (instregex "VPRO(L|R)V(D|Q)(Z128|Z256)rrk$")>;
+
+def 4GM7WriteVPROLXY_VPRORXYrmkLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPROLXY_VPRORXYrrk.Latency);
+ let ReleaseAtCycles = [1, 1, 4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPROLXY_VPRORXYrmkLd], (instregex "VPRO(L|R)V(D|Q)(Z128|Z256)rmk$")>;
+
+def 4GM7WriteVPROLZ_VPRORZ:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [8];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPROLZ_VPRORZ], (instregex "VPRO(L|R)V(D|Q)Z(rr|rrk|rrkz)")>;
+
+def 4GM7WriteVPROLZ_VPRORZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPROLZ_VPRORZ.Latency);
+ let ReleaseAtCycles = [1, 1, 8];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPROLZ_VPRORZLd], (instregex "VPRO(L|R)V(D|Q)Z(rm|rmk|rmkz)")>;
+
+def 4GM7WriteVPROLImmZ_VPRORImmZ:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 2;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPROLImmZ_VPRORImmZ], (instregex "VPRO(L|R)(D|Q)Z(ri|rik|rikz)")>;
+
+def 4GM7WriteVPROLImmZ_VPRORImmZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPROLImmZ_VPRORImmZ.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPROLImmZ_VPRORImmZLd], (instregex "VPRO(L|R)(D|Q)Z(mi|mik|mikz)")>;
+
+// VPTEST
+def 4GM7WriteVPTESTXY:SchedWriteRes<[4GM7FPU, 4GM7FPU13]> {
+ let Latency = 6;
+ let ReleaseAtCycles = [3, 1];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVPTESTXY], (instregex "VPTEST(N)?M(B|D|Q|W)(Z128|Z256)rrk")>;
+
+def 4GM7WriteVPTESTXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPTESTXY.Latency);
+ let ReleaseAtCycles = [1, 1, 3, 1];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVPTESTXYLd], (instregex "VPTEST(N)?M(B|D|Q|W)(Z128|Z256)rmk")>;
+
+def 4GM7WriteVPTESTZ:SchedWriteRes<[4GM7FPU, 4GM7FPU13]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [8, 4];
+ let NumMicroOps = 4;
+}
+def : InstRW<[4GM7WriteVPTESTZ], (instregex "VPTEST(N)?M(B|D|Q|W)Zrrk")>;
+
+def 4GM7WriteVPTESTZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPTESTZ.Latency);
+ let ReleaseAtCycles = [1, 1, 12, 6];
+ let NumMicroOps = 3;
+}
+def : InstRW<[4GM7WriteVPTESTZLd], (instregex "VPTEST(N)?M(B|D|Q|W)Zrmk")>;
+
+// VPACK
+def 4GM7WriteVPACKXY:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 2;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPACKXY], (instrs VPACKSSDWZ128rrk, VPACKSSWBZ128rrk,
+ VPACKUSDWZ128rrk, VPACKUSWBZ128rrk,
+ VPACKSSDWZ256rrk, VPACKSSWBZ256rrk,
+ VPACKUSDWZ256rrk, VPACKUSWBZ256rrk)>;
+
+def 4GM7WriteVPACKXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPACKXY.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPACKXYLd], (instrs VPACKSSDWZ128rmk, VPACKSSWBZ128rmk,
+ VPACKUSDWZ128rmk, VPACKUSWBZ128rmk,
+ VPACKSSDWZ256rmk, VPACKSSWBZ256rmk,
+ VPACKUSDWZ256rmk, VPACKUSWBZ256rmk)>;
+
+def 4GM7WriteVPACKZ:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 2;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPACKZ], (instrs VPACKSSDWZrrk, VPACKSSWBZrrk,
+ VPACKUSDWZrrk, VPACKUSWBZrrk)>;
+
+def 4GM7WriteVPACKZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPACKZ.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPACKZLd], (instrs VPACKSSDWZrmk, VPACKSSWBZrmk,
+ VPACKUSDWZrmk, VPACKUSWBZrmk)>;
+
+// VRANGE
+def 4GM7WriteVRANGEXY:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 1;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVRANGEXY], (instregex "VRANGE(PS|PD)(Z128|Z256)(rri|rrikz)$",
+ "VRANGE(SS|SD)Z(rri|rrib|rribkz|rrikz)$")>;
+
+def 4GM7WriteVRANGEXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVRANGEXY.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVRANGEXYLd], (instregex "VRANGE(PS|PD)(Z128|Z256)(rmi|rmikz)$",
+ "VRANGE(SS|SD)Z(rmi|rmib|rmibkz|rmikz)$")>;
+
+def 4GM7WriteVRANGEZ:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 1;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVRANGEZ], (instregex "VRANGE(PS|PD)Z(rri|rrib|rribkz|rrikz)$")>;
+
+def 4GM7WriteVRANGEZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVRANGEZ.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVRANGEZLd], (instregex "VRANGE(PS|PD)Z(rmi|rmib|rmibkz|rmikz)$")>;
+
+def 4GM7WriteVRANGEXYrrik:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 2;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVRANGEXYrrik], (instregex "VRANGE(PS|PD)(Z128|Z256)rrik$",
+ "VRANGE(SS|SD)Z(rrik|rribk)$")>;
+
+def 4GM7WriteVRANGEXYrmikLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVRANGEXYrrik.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVRANGEXYrmikLd], (instregex "VRANGE(PS|PD)(Z128|Z256)rmik$",
+ "VRANGE(SS|SD)Z(rmik|rmibk)$")>;
+
+def 4GM7WriteVRANGEZrrik:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 2;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVRANGEZrrik], (instregex "VRANGE(PS|PD)Z(rrik|rribk)$")>;
+
+def 4GM7WriteVRANGEZrmikLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVRANGEZrrik.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVRANGEZrmikLd], (instregex "VRANGE(PS|PD)Z(rmik|rmibk)$")>;
+
+// VFIXUPIMM
+def 4GM7WriteVFIXUPIMMXY:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVFIXUPIMMXY], (instregex "VFIXUPIMM(PS|PD)(Z128|Z256)rrik$")>;
+
+def 4GM7WriteVFIXUPIMMXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVFIXUPIMMXY.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVFIXUPIMMXYLd], (instregex "VFIXUPIMM(PS|PD)(Z128|Z256)rmik$")>;
+
+def 4GM7WriteVFIXUPIMMZ:SchedWriteRes<[4GM7FPU02, 4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [2, 2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVFIXUPIMMZ], (instregex "VFIXUPIMM(SS|SD|PS|PD)Z(rrik|rribk)$",
+ "VFIXUPIMM(SS|SD)Z(rrik|rribk)$")>;
+
+def 4GM7WriteVFIXUPIMMZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVFIXUPIMMZ.Latency);
+ let ReleaseAtCycles = [1, 1, 2, 2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVFIXUPIMMZLd], (instregex "VFIXUPIMM(SS|SD|PS|PD)Z(rmik|rmibk)$",
+ "VFIXUPIMM(SS|SD)Z(rmik|rmibk)$")>;
+
+def 4GM7WriteVFIXUPIMMZrribkz:SchedWriteRes<[4GM7FPU02, 4GM7FPU02]> {
+ let Latency = 3;
+ let ReleaseAtCycles = [2, 2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVFIXUPIMMZrribkz], (instregex "VFIXUPIMM(SS|SD)Z(rrib|rribkz)$")>;
+
+// VCOMPRESS VPCOMPRESS
+def 4GM7WriteCOMPRESSXYrrkz:SchedWriteRes<[4GM7FPU3, 4GM7FPU02]> {
+ let Latency = 3;
+ let ReleaseAtCycles = [2, 4];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteCOMPRESSXYrrkz], (instrs VCOMPRESSPSZ128rrkz, VCOMPRESSPDZ128rrkz,
+ VPCOMPRESSBZ128rrkz, VPCOMPRESSWZ128rrkz,
+ VPCOMPRESSDZ128rrkz, VPCOMPRESSQZ128rrkz,
+ VCOMPRESSPSZ256rrkz, VCOMPRESSPDZ256rrkz,
+ VPCOMPRESSBZ256rrkz, VPCOMPRESSWZ256rrkz,
+ VPCOMPRESSDZ256rrkz, VPCOMPRESSQZ256rrkz)>;
+
+def 4GM7WriteCOMPRESSXYrrk:SchedWriteRes<[4GM7FPU3, 4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [2, 4];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteCOMPRESSXYrrk], (instrs VCOMPRESSPSZ128rrk, VCOMPRESSPDZ128rrk,
+ VPCOMPRESSBZ128rrk, VPCOMPRESSWZ128rrk,
+ VPCOMPRESSDZ128rrk, VPCOMPRESSQZ128rrk,
+ VCOMPRESSPSZ256rrk, VCOMPRESSPDZ256rrk,
+ VPCOMPRESSBZ256rrk, VPCOMPRESSWZ256rrk,
+ VPCOMPRESSDZ256rrk, VPCOMPRESSQZ256rrk)>;
+
+def 4GM7WriteCOMPRESSXYmrk:SchedWriteRes<[4GM7FPU3, 4GM7FPU02, 4GM7AGU, 4GM7Store]> {
+ let Latency = !add(4GM7WriteCOMPRESSXYrrk.Latency, C864GM7Model.StoreLatency);
+ let ReleaseAtCycles = [2, 4, 1, 1];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteCOMPRESSXYmrk], (instrs VCOMPRESSPSZ128mrk, VCOMPRESSPDZ128mrk,
+ VPCOMPRESSBZ128mrk, VPCOMPRESSWZ128mrk,
+ VPCOMPRESSDZ128mrk, VPCOMPRESSQZ128mrk,
+ VCOMPRESSPSZ256mrk, VCOMPRESSPDZ256mrk,
+ VPCOMPRESSBZ256mrk, VPCOMPRESSWZ256mrk,
+ VPCOMPRESSDZ256mrk, VPCOMPRESSQZ256mrk)>;
+
+def 4GM7WriteCOMPRESSXY:SchedWriteRes<[4GM7FPU3, 4GM7FPU02]> {
+ let Latency = 1;
+ let ReleaseAtCycles = [2, 4];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteCOMPRESSXY], (instrs VCOMPRESSPSZ128rr, VCOMPRESSPDZ128rr,
+ VPCOMPRESSBZ128rr, VPCOMPRESSWZ128rr,
+ VPCOMPRESSDZ128rr, VPCOMPRESSQZ128rr,
+ VCOMPRESSPSZ256rr, VCOMPRESSPDZ256rr,
+ VPCOMPRESSBZ256rr, VPCOMPRESSWZ256rr,
+ VPCOMPRESSDZ256rr, VPCOMPRESSQZ256rr)>;
+
+def 4GM7WriteCOMPRESSXYLd:SchedWriteRes<[4GM7FPU3, 4GM7FPU02, 4GM7AGU, 4GM7Store]> {
+ let Latency = !add(4GM7WriteCOMPRESSXY.Latency, C864GM7Model.StoreLatency);
+ let ReleaseAtCycles = [2, 4, 1, 1];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteCOMPRESSXYLd], (instrs VCOMPRESSPSZ128mr, VCOMPRESSPDZ128mr,
+ VPCOMPRESSBZ128mr, VPCOMPRESSWZ128mr,
+ VPCOMPRESSDZ128mr, VPCOMPRESSQZ128mr,
+ VCOMPRESSPSZ256mr, VCOMPRESSPDZ256mr,
+ VPCOMPRESSBZ256mr, VPCOMPRESSWZ256mr,
+ VPCOMPRESSDZ256mr, VPCOMPRESSQZ256mr)>;
+
+def 4GM7WriteCOMPRESSZrrkz:SchedWriteRes<[4GM7FPU3, 4GM7FPU02]> {
+ let Latency = 10;
+ let ReleaseAtCycles = [6, 12];
+ let NumMicroOps = 4;
+}
+def : InstRW<[4GM7WriteCOMPRESSZrrkz], (instrs VCOMPRESSPSZrrkz, VCOMPRESSPDZrrkz,
+ VPCOMPRESSBZrrkz, VPCOMPRESSWZrrkz,
+ VPCOMPRESSDZrrkz, VPCOMPRESSQZrrkz)>;
+
+def 4GM7WriteCOMPRESSZrrk:SchedWriteRes<[4GM7FPU3, 4GM7FPU02]> {
+ let Latency = 7;
+ let ReleaseAtCycles = [6, 12];
+ let NumMicroOps = 4;
+}
+def : InstRW<[4GM7WriteCOMPRESSZrrk], (instrs VCOMPRESSPSZrrk, VCOMPRESSPDZrrk,
+ VPCOMPRESSBZrrk, VPCOMPRESSDZrrk,
+ VPCOMPRESSWZrrk, VPCOMPRESSQZrrk)>;
+
+def 4GM7WriteCOMPRESSZmrk:SchedWriteRes<[4GM7FPU3, 4GM7FPU02, 4GM7AGU, 4GM7Store]> {
+ let Latency = !add(4GM7WriteCOMPRESSZrrk.Latency, C864GM7Model.StoreLatency);
+ let ReleaseAtCycles = [6, 12, 1, 1];
+ let NumMicroOps = 4;
+}
+def : InstRW<[4GM7WriteCOMPRESSZmrk], (instrs VCOMPRESSPSZmrk, VCOMPRESSPDZmrk,
+ VPCOMPRESSBZmrk, VPCOMPRESSDZmrk,
+ VPCOMPRESSWZmrk, VPCOMPRESSQZmrk)>;
+
+def 4GM7WriteCOMPRESSZ:SchedWriteRes<[4GM7FPU3, 4GM7FPU02]> {
+ let Latency = 1;
+ let ReleaseAtCycles = [6, 12];
+ let NumMicroOps = 4;
+}
+def : InstRW<[4GM7WriteCOMPRESSZ], (instrs VCOMPRESSPSZrr, VCOMPRESSPDZrr,
+ VPCOMPRESSBZrr, VPCOMPRESSWZrr,
+ VPCOMPRESSDZrr, VPCOMPRESSQZrr)>;
+
+def 4GM7WriteCOMPRESSZLd:SchedWriteRes<[4GM7FPU3, 4GM7FPU02, 4GM7AGU, 4GM7Store]> {
+ let Latency = !add(4GM7WriteCOMPRESSZ.Latency, C864GM7Model.StoreLatency);
+ let ReleaseAtCycles = [6, 12, 1, 1];
+ let NumMicroOps = 4;
+}
+def : InstRW<[4GM7WriteCOMPRESSZLd], (instrs VCOMPRESSPSZmr, VCOMPRESSPDZmr,
+ VPCOMPRESSBZmr, VPCOMPRESSWZmr,
+ VPCOMPRESSDZmr, VPCOMPRESSQZmr)>;
+
+// EXPAND
+def 4GM7WriteEXPANDXYrrkz:SchedWriteRes<[4GM7FPU3, 4GM7FPU02]> {
+ let Latency = 3;
+ let ReleaseAtCycles = [2, 4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteEXPANDXYrrkz], (instrs VEXPANDPSZ128rrkz, VEXPANDPDZ128rrkz,
+ VPEXPANDBZ128rrkz, VPEXPANDWZ128rrkz,
+ VPEXPANDDZ128rrkz, VPEXPANDQZ128rrkz,
+ VEXPANDPSZ256rrkz, VEXPANDPDZ256rrkz,
+ VPEXPANDBZ256rrkz, VPEXPANDWZ256rrkz,
+ VPEXPANDDZ256rrkz, VPEXPANDQZ256rrkz)>;
+
+def 4GM7WriteEXPANDXYrmkz:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU3, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteEXPANDXYrrkz.Latency);
+ let ReleaseAtCycles = [1, 1, 2, 4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteEXPANDXYrmkz], (instrs VEXPANDPSZ128rmkz, VEXPANDPDZ128rmkz,
+ VPEXPANDBZ128rmkz, VPEXPANDWZ128rmkz,
+ VPEXPANDDZ128rmkz, VPEXPANDQZ128rmkz,
+ VEXPANDPSZ256rmkz, VEXPANDPDZ256rmkz,
+ VPEXPANDBZ256rmkz, VPEXPANDWZ256rmkz,
+ VPEXPANDDZ256rmkz, VPEXPANDQZ256rmkz)>;
+
+def 4GM7WriteEXPANDXYrrk:SchedWriteRes<[4GM7FPU3, 4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [2, 4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteEXPANDXYrrk], (instrs VEXPANDPSZ128rrk, VEXPANDPDZ128rrk,
+ VPEXPANDBZ128rrk, VPEXPANDWZ128rrk,
+ VPEXPANDDZ128rrk, VPEXPANDQZ128rrk,
+ VEXPANDPSZ256rrk, VEXPANDPDZ256rrk,
+ VPEXPANDBZ256rrk, VPEXPANDWZ256rrk,
+ VPEXPANDDZ256rrk, VPEXPANDQZ256rrk)>;
+
+def 4GM7WriteEXPANDXYrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU3, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteEXPANDXYrrk.Latency);
+ let ReleaseAtCycles = [1, 1, 2, 4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteEXPANDXYrmk], (instrs VEXPANDPSZ128rmk, VEXPANDPDZ128rmk,
+ VPEXPANDBZ128rmk, VPEXPANDWZ128rmk,
+ VPEXPANDDZ128rmk, VPEXPANDQZ128rmk,
+ VEXPANDPSZ256rmk, VEXPANDPDZ256rmk,
+ VPEXPANDBZ256rmk, VPEXPANDWZ256rmk,
+ VPEXPANDDZ256rmk, VPEXPANDQZ256rmk)>;
+
+def 4GM7WriteEXPANDXY:SchedWriteRes<[4GM7FPU3, 4GM7FPU02]> {
+ let Latency = 1;
+ let ReleaseAtCycles = [2, 4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteEXPANDXY], (instrs VEXPANDPSZ128rr, VEXPANDPDZ128rr,
+ VPEXPANDBZ128rr, VPEXPANDWZ128rr,
+ VPEXPANDDZ128rr, VPEXPANDQZ128rr,
+ VEXPANDPSZ256rr, VEXPANDPDZ256rr,
+ VPEXPANDBZ256rr, VPEXPANDWZ256rr,
+ VPEXPANDDZ256rr, VPEXPANDQZ256rr)>;
+
+def 4GM7WriteEXPANDXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU3, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteEXPANDXY.Latency);
+ let ReleaseAtCycles = [1, 1, 2, 4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteEXPANDXYLd], (instrs VEXPANDPSZ128rm, VEXPANDPDZ128rm,
+ VPEXPANDBZ128rm, VPEXPANDWZ128rm,
+ VPEXPANDDZ128rm, VPEXPANDQZ128rm,
+ VEXPANDPSZ256rm, VEXPANDPDZ256rm,
+ VPEXPANDBZ256rm, VPEXPANDWZ256rm,
+ VPEXPANDDZ256rm, VPEXPANDQZ256rm)>;
+
+def 4GM7WriteEXPANDZrrkz:SchedWriteRes<[4GM7FPU3, 4GM7FPU02]> {
+ let Latency = 10;
+ let ReleaseAtCycles = [8, 16];
+ let NumMicroOps = 10;
+}
+def : InstRW<[4GM7WriteEXPANDZrrkz], (instrs VEXPANDPSZrrkz, VEXPANDPDZrrkz,
+ VPEXPANDBZrrkz, VPEXPANDWZrrkz,
+ VPEXPANDDZrrkz, VPEXPANDQZrrkz)>;
+
+def 4GM7WriteEXPANDZrmkz:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU3, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteEXPANDZrrkz.Latency);
+ let ReleaseAtCycles = [1, 1, 8, 16];
+ let NumMicroOps = 10;
+}
+def : InstRW<[4GM7WriteEXPANDZrmkz], (instrs VEXPANDPSZrmkz, VEXPANDPDZrmkz,
+ VPEXPANDBZrmkz, VPEXPANDWZrmkz,
+ VPEXPANDDZrmkz, VPEXPANDQZrmkz)>;
+
+def 4GM7WriteEXPANDZrrk:SchedWriteRes<[4GM7FPU3, 4GM7FPU02]> {
+ let Latency = 8;
+ let ReleaseAtCycles = [8, 16];
+ let NumMicroOps = 10;
+}
+def : InstRW<[4GM7WriteEXPANDZrrk], (instrs VEXPANDPSZrrk, VEXPANDPDZrrk,
+ VPEXPANDBZrrk, VPEXPANDDZrrk,
+ VPEXPANDWZrrk, VPEXPANDQZrrk)>;
+
+def 4GM7WriteEXPANDZrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU3, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteEXPANDZrrk.Latency);
+ let ReleaseAtCycles = [1, 1, 8, 16];
+ let NumMicroOps = 10;
+}
+def : InstRW<[4GM7WriteEXPANDZrmk], (instrs VEXPANDPSZrmk, VEXPANDPDZrmk,
+ VPEXPANDBZrmk, VPEXPANDDZrmk,
+ VPEXPANDWZrmk, VPEXPANDQZrmk)>;
+
+def 4GM7WriteEXPANDZ:SchedWriteRes<[4GM7FPU3, 4GM7FPU02]> {
+ let Latency = 1;
+ let ReleaseAtCycles = [8, 16];
+ let NumMicroOps = 10;
+}
+def : InstRW<[4GM7WriteEXPANDZ], (instrs VEXPANDPSZrr, VEXPANDPDZrr,
+ VPEXPANDBZrr, VPEXPANDWZrr,
+ VPEXPANDDZrr, VPEXPANDQZrr)>;
+
+def 4GM7WriteEXPANDZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU3, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteEXPANDZ.Latency);
+ let ReleaseAtCycles = [1, 1, 8, 16];
+ let NumMicroOps = 10;
+}
+def : InstRW<[4GM7WriteEXPANDZLd], (instrs VEXPANDPSZrm, VEXPANDPDZrm,
+ VPEXPANDBZrm, VPEXPANDWZrm,
+ VPEXPANDDZrm, VPEXPANDQZrm)>;
+
+// VINSERT
+def 4GM7WriteVINSERT256Z:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 2;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVINSERT256Z], (instregex "VINSERT(F|I)(32X8|64X4)Zrri(k|kz)?")>;
+
+def 4GM7WriteVINSERT256ZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVINSERT256Z.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVINSERT256ZLd], (instregex "VINSERT(F|I)(32X8|64X4)Zrmi(k|kz)?")>;
+
+def 4GM7WriteVINSERTY:SchedWriteRes<[4GM7FPU02, 4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [4, 4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVINSERTY], (instregex "VINSERT(F|I)(32X4|64X2)Z256rrik")>;
+
+def 4GM7WriteVINSERTYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVINSERTY.Latency);
+ let ReleaseAtCycles = [1, 1, 4, 4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVINSERTYLd], (instregex "VINSERT(F|I)(32X4|64X2)Z256rmik")>;
+
+def 4GM7WriteVINSERTZ:SchedWriteRes<[4GM7FPU02, 4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [8, 8];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVINSERTZ], (instregex "VINSERT(F|I)(32X4|64X2)Zrrik")>;
+
+def 4GM7WriteVINSERTZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVINSERTZ.Latency);
+ let ReleaseAtCycles = [1, 1, 8, 8];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVINSERTZLd], (instregex "VINSERT(F|I)(32X4|64X2)Zrmik")>;
+
+def 4GM7WriteVINSERTZrri:SchedWriteRes<[4GM7FPU02, 4GM7FPU02]> {
+ let Latency = 5;
+ let ReleaseAtCycles = [8, 8];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVINSERTZrri], (instregex "VINSERT(F|I)(32X4|64X2)Zrri$")>;
+
+def 4GM7WriteVINSERTZrmi:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVINSERTZrri.Latency);
+ let ReleaseAtCycles = [1, 1, 8, 8];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVINSERTZrmi], (instregex "VINSERT(F|I)(32X4|64X2)Zrmi$")>;
+
+// VEXTRACT
+def 4GM7WriteVEXTRACTZ:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 1;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVEXTRACTZ], (instregex "VEXTRACT(F|I)(32X8|64X4)Z(rri|rrikz)$")>;
+
+def 4GM7WriteVEXTRACTZLd:SchedWriteRes<[4GM7FPU13, 4GM7AGU, 4GM7Store]> {
+ let Latency = !add(4GM7WriteVEXTRACTZ.Latency, C864GM7Model.StoreLatency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVEXTRACTZLd], (instregex "VEXTRACT(F|I)(32X8|64X4)Z(mri|mrikz)$")>;
+
+def 4GM7WriteVEXTRACTZrrik:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 2;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVEXTRACTZrrik], (instregex "VEXTRACT(F|I)(32X8|64X4)Zrrik$")>;
+
+def 4GM7WriteVEXTRACTZmrik:SchedWriteRes<[4GM7FPU13, 4GM7AGU, 4GM7Store]> {
+ let Latency = !add(4GM7WriteVEXTRACTZrrik.Latency, C864GM7Model.StoreLatency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVEXTRACTZmrik], (instregex "VEXTRACT(F|I)(32X8|64X4)Zmrik$")>;
+
+def 4GM7WriteVEXTRACTY:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVEXTRACTY], (instregex "VEXTRACT(F|I)(32X4|64X2)(Z|Z256)rrik$")>;
+
+def 4GM7WriteVEXTRACTYLd:SchedWriteRes<[4GM7FPU02, 4GM7AGU, 4GM7Store]> {
+ let Latency = !add(4GM7WriteVEXTRACTY.Latency, C864GM7Model.StoreLatency);
+ let ReleaseAtCycles = [4, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVEXTRACTYLd], (instregex "VEXTRACT(F|I)(32X4|64X2)(Z|Z256)mrik$")>;
+
+// VPCONFLIC
+def 4GM7WriteVPCONFLICX:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 2;
+ let ReleaseAtCycles = [4];
+ let NumMicroOps = 4;
+}
+def : InstRW<[4GM7WriteVPCONFLICX], (instregex "VPCONFLICT(D|Q)Z128(rr|rrk|rrkz)")>;
+
+def 4GM7WriteVPCONFLICXLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPCONFLICX.Latency);
+ let ReleaseAtCycles = [1, 1, 4];
+ let NumMicroOps = 4;
+}
+def : InstRW<[4GM7WriteVPCONFLICXLd], (instregex "VPCONFLICT(D|Q)Z128(rm|rmk|rmkz)")>;
+
+def 4GM7WriteVPCONFLICY:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 5;
+ let ReleaseAtCycles = [6];
+ let NumMicroOps = 5;
+}
+def : InstRW<[4GM7WriteVPCONFLICY], (instregex "VPCONFLICT(D|Q)Z256(rr|rrkz)$")>;
+
+def 4GM7WriteVPCONFLICYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPCONFLICY.Latency);
+ let ReleaseAtCycles = [1, 1, 6];
+ let NumMicroOps = 8;
+}
+def : InstRW<[4GM7WriteVPCONFLICYLd], (instregex "VPCONFLICT(D|Q)Z256(rm|rmkz)$")>;
+
+def 4GM7WriteVPCONFLICYrrk:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 3;
+ let ReleaseAtCycles = [6];
+ let NumMicroOps = 4;
+}
+def : InstRW<[4GM7WriteVPCONFLICYrrk], (instregex "VPCONFLICT(D|Q)Z256rrk$")>;
+
+def 4GM7WriteVPCONFLICYrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPCONFLICYrrk.Latency);
+ let ReleaseAtCycles = [1, 1, 6];
+ let NumMicroOps = 4;
+}
+def : InstRW<[4GM7WriteVPCONFLICYrmk], (instregex "VPCONFLICT(D|Q)Z256rmk$")>;
+
+def 4GM7WriteVPCONFLICZ:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 7;
+ let ReleaseAtCycles = [12];
+ let NumMicroOps = 16;
+}
+def : InstRW<[4GM7WriteVPCONFLICZ], (instregex "VPCONFLICT(D|Q)Z(rr|rrkz)$")>;
+
+def 4GM7WriteVPCONFLICZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPCONFLICZ.Latency);
+ let ReleaseAtCycles = [1, 1, 12];
+ let NumMicroOps = 16;
+}
+def : InstRW<[4GM7WriteVPCONFLICZLd], (instregex "VPCONFLICT(D|Q)Z(rm|rmkz)$")>;
+
+def 4GM7WriteVPCONFLICZrrk:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 6;
+ let ReleaseAtCycles = [12];
+ let NumMicroOps = 16;
+}
+def : InstRW<[4GM7WriteVPCONFLICZrrk], (instregex "VPCONFLICT(D|Q)Zrrk$")>;
+
+def 4GM7WriteVPCONFLICZrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPCONFLICZrrk.Latency);
+ let ReleaseAtCycles = [1, 1, 12];
+ let NumMicroOps = 16;
+}
+def : InstRW<[4GM7WriteVPCONFLICZrmk], (instregex "VPCONFLICT(D|Q)Zrmk$")>;
+
+// VPDP
+def 4GM7WriteVPDPXY:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPDPXY], (instregex "VPDP(BUSDS|BUSD|WSSDS|WSSD)(Z128|Z256)rrk$")>;
+
+def 4GM7WriteVPDPXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPDPXY.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPDPXYLd], (instregex "VPDP(BUSDS|BUSD|WSSDS|WSSD)(Z128|Z256)rmk$")>;
+
+def 4GM7WriteVPDPZ:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPDPZ], (instregex "VPDP(BUSDS|BUSD|WSSDS|WSSD)Zrrk$")>;
+
+def 4GM7WriteVPDPZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPDPZ.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPDPZLd], (instregex "VPDP(BUSDS|BUSD|WSSDS|WSSD)Zrmk$")>;
+
+// VBROADCAST VPBROADCAST
+def 4GM7WriteVBROADCASTX:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 1;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVBROADCASTX], (instregex "V(P)?BROADCAST(SS|B|W)Z128(rr|rrkz)$")>;
+
+def 4GM7WriteVBROADCASTXLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVBROADCASTX.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVBROADCASTXLd], (instregex "V(P)?BROADCAST(SS|B|W)Z128(rm|rmkz)$")>;
+
+def 4GM7WriteVBROADCASTXrrk:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 2;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVBROADCASTXrrk], (instregex "V(P)?BROADCAST(SS|SD|I32X2|B|W|D|Q)(r)?Z128rrk$")>;
+
+def 4GM7WriteVBROADCASTXrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVBROADCASTXrrk.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVBROADCASTXrmk], (instregex "V(P)?BROADCAST(SS|SD|I32X2|B|W|D|Q)(r)?Z128rmk$")>;
+
+def 4GM7WriteVBROADCASTY:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVBROADCASTY], (instregex "V(P)?BROADCAST(SS|SD|F32X2|I32X2|B|W|D|Q)(r)?Z256rrk$")>;
+
+def 4GM7WriteVBROADCASTYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVBROADCASTY.Latency);
+ let ReleaseAtCycles = [1, 1, 4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVBROADCASTYLd], (instregex "V(P)?BROADCAST(SS|SD|F32X2|I32X2|B|W|D|Q)(r)?Z256rmk$")>;
+
+def 4GM7WriteVBROADCASTZ:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 5;
+ let ReleaseAtCycles = [8];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVBROADCASTZ], (instregex "V(P)?BROADCAST(SS|SD|F32X2|I32X2|B|W|D|Q)Z(rr|rrkz)$")>;
+
+def 4GM7WriteVBROADCASTZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVBROADCASTZ.Latency);
+ let ReleaseAtCycles = [1, 1, 8];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVBROADCASTZLd], (instregex "V(P)?BROADCAST(SS|SD|F32X2|I32X2|B|W|D|Q)Z(rm|rmkz)$")>;
+
+def 4GM7WriteVBROADCASTZrrk:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [8];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVBROADCASTZrrk], (instregex "V(P)?BROADCAST(SS|SD|F32X2|I32X2|B|W|D|Q)(r)?Zrrk$")>;
+
+def 4GM7WriteVBROADCASTZrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVBROADCASTZrrk.Latency);
+ let ReleaseAtCycles = [1, 1, 8];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVBROADCASTZrmk], (instregex "V(P)?BROADCAST(SS|SD|F32X2|I32X2|B|W|D|Q)(r)?Zrmk$")>;
+
+// VPERM
+def 4GM7WriteVPERMXY:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 3;
+ let ReleaseAtCycles = [4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPERMXY], (instregex "VPERM(PS|PD|B|W|D|Q)(Z128|Z256)(rr|rrkz)$")>;
+
+def 4GM7WriteVPERMXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPERMXY.Latency);
+ let ReleaseAtCycles = [1, 1, 4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPERMXYLd], (instregex "VPERM(PS|PD|B|W|D|Q)(Z128|Z256)(rm|rmkz)$")>;
+
+
+def 4GM7WriteVPERMXYrrk:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPERMXYrrk], (instregex "VPERM(PS|PD|B|W|D|Q)(Z128|Z256)rrk$")>;
+
+def 4GM7WriteVPERMXYrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPERMXYrrk.Latency);
+ let ReleaseAtCycles = [1, 1, 4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPERMXYrmk], (instregex "VPERM(PS|PD|B|W|D|Q)(Z128|Z256)rmk$")>;
+
+
+def 4GM7WriteVPERMZ:SchedWriteRes<[4GM7FPU]> {
+ let Latency = 8;
+ let ReleaseAtCycles = [32];
+ let NumMicroOps = 8;
+}
+def : InstRW<[4GM7WriteVPERMZ], (instregex "VPERM(PS|PD|B|W|D|Q)Zrr(k|kz)?",
+ "VPERM2(F|I)128rri")>;
+
+def 4GM7WriteVPERMZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPERMZ.Latency);
+ let ReleaseAtCycles = [1, 1, 32];
+ let NumMicroOps = 8;
+}
+def : InstRW<[4GM7WriteVPERMZLd], (instregex "VPERM(PS|PD|B|W|D|Q)Zrm(k|kz)?",
+ "VPERM2(F|I)128rmi")>;
+
+def 4GM7WriteVPERMImmY:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 3;
+ let ReleaseAtCycles = [4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPERMImmY], (instregex "VPERM(PD|Q)Z256(ri|rikz)$")>;
+
+def 4GM7WriteVPERMImmYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPERMImmY.Latency);
+ let ReleaseAtCycles = [1, 1, 4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPERMImmYLd], (instregex "VPERM(PD|Q)Z256(mi|mikz)$")>;
+
+def 4GM7WriteVPERMImmYrik:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPERMImmYrik], (instregex "VPERM(PD|Q)Z256rik$")>;
+
+def 4GM7WriteVPERMImmYmik:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPERMImmYrik.Latency);
+ let ReleaseAtCycles = [1, 1, 4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPERMImmYmik], (instregex "VPERM(PD|Q)Z256mik$")>;
+
+def 4GM7WriteVPERMImmZ:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [8];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPERMImmZ], (instregex "VPERM(PD|Q)Zri(k|kz)?")>;
+
+def 4GM7WriteVPERMImmZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPERMImmZ.Latency);
+ let ReleaseAtCycles = [1, 1, 8];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPERMImmZLd], (instregex "VPERM(PD|Q)Zmi(k|kz)?")>;
+
+// VPERMI2 VPERMT2
+def 4GM7WriteVPERMI2X_VPERMT2X:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 3;
+ let ReleaseAtCycles = [4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPERMI2X_VPERMT2X], (instregex "VPERM(I|T)2(PS|PD|B|W|D|Q)Z128(rr|rrkz)$")>;
+
+def 4GM7WriteVPERMI2X_VPERMT2XLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPERMI2X_VPERMT2X.Latency);
+ let ReleaseAtCycles = [1, 1, 4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPERMI2X_VPERMT2XLd], (instregex "VPERM(I|T)2(PS|PD|B|W|D|Q)Z128(rm|rmkz)$")>;
+
+def 4GM7WriteVPERMI2X_VPERMT2Xrrk:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPERMI2X_VPERMT2Xrrk], (instregex "VPERM(I|T)2(PS|PD|B|D|W|Q)Z128rrk$")>;
+
+def 4GM7WriteVPERMI2X_VPERMT2Xrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPERMI2X_VPERMT2Xrrk.Latency);
+ let ReleaseAtCycles = [1, 1, 4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPERMI2X_VPERMT2Xrmk], (instregex "VPERM(I|T)2(PS|PD|B|D|W|Q)Z128rmk$")>;
+
+def 4GM7WriteVPERMT2Y:SchedWriteRes<[4GM7FPU]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [16];
+ let NumMicroOps = 4;
+}
+def : InstRW<[4GM7WriteVPERMT2Y], (instregex "VPERMT2(PS|PD|B|W|D|Q)Z256rr(kz)?")>;
+
+def 4GM7WriteVPERMT2YLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPERMT2Y.Latency);
+ let ReleaseAtCycles = [1, 1, 16];
+ let NumMicroOps = 4;
+}
+def : InstRW<[4GM7WriteVPERMT2YLd], (instregex "VPERMT2(PS|PD|B|W|D|Q)Z256rm(kz)?")>;
+
+def 4GM7WriteVPERMI2Y:SchedWriteRes<[4GM7FPU]> {
+ let Latency = 6;
+ let ReleaseAtCycles = [16];
+ let NumMicroOps = 4;
+}
+def : InstRW<[4GM7WriteVPERMI2Y], (instregex "VPERMI2(PS|PD|B|W|D|Q)Z256rr(kz)?")>;
+
+def 4GM7WriteVPERMI2YLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPERMI2Y.Latency);
+ let ReleaseAtCycles = [1, 1, 16];
+ let NumMicroOps = 4;
+}
+def : InstRW<[4GM7WriteVPERMI2YLd], (instregex "VPERMI2(PS|PD|B|W|D|Q)Z256rm(kz)?")>;
+
+def 4GM7WriteVPERMI2Z_VPERMT2Z:SchedWriteRes<[4GM7FPU]> {
+ let Latency = 16;
+ let ReleaseAtCycles = [64];
+ let NumMicroOps = 16;
+}
+def : InstRW<[4GM7WriteVPERMI2Z_VPERMT2Z], (instregex "VPERM(I|T)2(PS|PD|B|W|D|Q)Zrr(kz)?")>;
+
+def 4GM7WriteVPERMI2Z_VPERMT2ZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPERMI2Z_VPERMT2Z.Latency);
+ let ReleaseAtCycles = [1, 1, 64];
+ let NumMicroOps = 16;
+}
+def : InstRW<[4GM7WriteVPERMI2Z_VPERMT2ZLd], (instregex "VPERM(I|T)2(PS|PD|B|W|D|Q)Zrm(kz)?")>;
+
+// VPERMIL
+def 4GM7WriteVPERMILXY:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPERMILXY], (instregex "VPERMIL(PS|PD)(Z128|Z256)rrk$")>;
+
+def 4GM7WriteVPERMILXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPERMILXY.Latency);
+ let ReleaseAtCycles = [1, 1, 4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPERMILXYLd], (instregex "VPERMIL(PS|PD)(Z128|Z256)rmk$")>;
+
+def 4GM7WriteVPERMILZ:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 3;
+ let ReleaseAtCycles = [8];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPERMILZ], (instregex "VPERMIL(PS|PD)Z(rr|rrkz)$")>;
+
+def 4GM7WriteVPERMILZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPERMILZ.Latency);
+ let ReleaseAtCycles = [1, 1, 8];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPERMILZLd], (instregex "VPERMIL(PS|PD)Z(rm|rmkz)$")>;
+
+def 4GM7WriteVPERMILZrrk:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [8];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPERMILZrrk], (instregex "VPERMIL(PS|PD)Zrrk$")>;
+
+def 4GM7WriteVPERMILZrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPERMILZrrk.Latency);
+ let ReleaseAtCycles = [1, 1, 8];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPERMILZrmk], (instregex "VPERMIL(PS|PD)Zrmk$")>;
+
+def 4GM7WriteVPERMILZrik:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 2;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPERMILZrik], (instregex "VPERMIL(PS|PD)Zri(k|kz)?")>;
+
+def 4GM7WriteVPERMILZmik:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPERMILZrik.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteVPERMILZmik], (instregex "VPERMIL(PS|PD)Zmi(k|kz)?")>;
+
+// ALIGN
+def 4GM7WriteALIGNX:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 2;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteALIGNX], (instrs VALIGNDZ128rrik, VALIGNDZ128rrikz,
+ VALIGNQZ128rrik, VALIGNQZ128rrikz)>;
+
+def 4GM7WriteALIGNXLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteALIGNX.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteALIGNXLd], (instrs VALIGNDZ128rmik, VALIGNDZ128rmikz,
+ VALIGNQZ128rmik, VALIGNQZ128rmikz)>;
+
+def 4GM7WriteALIGNY:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 3;
+ let ReleaseAtCycles = [4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteALIGNY], (instrs VALIGNDZ256rri, VALIGNDZ256rrikz,
+ VALIGNQZ256rri, VALIGNQZ256rrikz)>;
+
+def 4GM7WriteALIGNYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteALIGNY.Latency);
+ let ReleaseAtCycles = [1, 1, 4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteALIGNYLd], (instrs VALIGNDZ256rmi, VALIGNDZ256rmikz,
+ VALIGNQZ256rmi, VALIGNQZ256rmikz)>;
+
+def 4GM7WriteALIGNYrrik:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteALIGNYrrik], (instrs VALIGNDZ256rrik, VALIGNQZ256rrik)>;
+
+def 4GM7WriteALIGNYrmik:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteALIGNYrrik.Latency);
+ let ReleaseAtCycles = [1, 1, 4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteALIGNYrmik], (instrs VALIGNDZ256rmik, VALIGNQZ256rmik)>;
+
+def 4GM7WriteALIGNZ:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [8];
+ let NumMicroOps = 8;
+}
+def : InstRW<[4GM7WriteALIGNZ], (instrs VALIGNDZrri, VALIGNQZrri,
+ VALIGNDZrrik, VALIGNQZrrik,
+ VALIGNDZrrikz, VALIGNQZrrikz)>;
+
+def 4GM7WriteALIGNZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteALIGNZ.Latency);
+ let ReleaseAtCycles = [1, 1, 8];
+ let NumMicroOps = 8;
+}
+def : InstRW<[4GM7WriteALIGNZLd], (instrs VALIGNDZrmi, VALIGNQZrmi,
+ VALIGNDZrmik, VALIGNQZrmik,
+ VALIGNDZrmikz, VALIGNQZrmikz)>;
+
+// PALIGN
+def 4GM7WritePALIGNX:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 2;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WritePALIGNX], (instrs VPALIGNRZrrik, VPALIGNRZrrikz)>;
+
+def 4GM7WritePALIGNXLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WritePALIGNX.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WritePALIGNXLd], (instrs VPALIGNRZrmik, VPALIGNRZrmikz)>;
+
+def 4GM7WritePALIGNY:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 2;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WritePALIGNY], (instrs VPALIGNRZ128rrik, VPALIGNRZ128rrikz)>;
+
+def 4GM7WritePALIGNYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WritePALIGNY.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WritePALIGNYLd], (instrs VPALIGNRZ128rmik, VPALIGNRZ128rmikz)>;
+
+def 4GM7WritePALIGNZ:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 2;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WritePALIGNZ], (instrs VPALIGNRZ256rrik, VPALIGNRZ256rrikz)>;
+
+def 4GM7WritePALIGNZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WritePALIGNZ.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WritePALIGNZLd], (instrs VPALIGNRZ256rmik, VPALIGNRZ256rmikz)>;
+
+// DBPSADBWZ
+def 4GM7WriteDBPSADBWZ:SchedWriteRes<[4GM7FPU02, 4GM7FPU13]> {
+ let Latency = 3;
+ let ReleaseAtCycles = [6, 6];
+ let NumMicroOps = 5;
+}
+def : InstRW<[4GM7WriteDBPSADBWZ], (instrs VDBPSADBWZrri, VDBPSADBWZrrikz,
+ VDBPSADBWZ128rri, VDBPSADBWZ128rrikz,
+ VDBPSADBWZ256rri, VDBPSADBWZ256rrikz)>;
+
+def 4GM7WriteDBPSADBWZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteDBPSADBWZ.Latency);
+ let ReleaseAtCycles = [1, 1, 6, 6];
+ let NumMicroOps = 5;
+}
+def : InstRW<[4GM7WriteDBPSADBWZLd], (instrs VDBPSADBWZrmi, VDBPSADBWZrmikz,
+ VDBPSADBWZ128rmi, VDBPSADBWZ128rmikz,
+ VDBPSADBWZ256rmi, VDBPSADBWZ256rmikz)>;
+
+def 4GM7WriteDBPSADBWZrrik:SchedWriteRes<[4GM7FPU02, 4GM7FPU13]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [6, 6];
+ let NumMicroOps = 5;
+}
+def : InstRW<[4GM7WriteDBPSADBWZrrik], (instrs VDBPSADBWZrrik, VDBPSADBWZ128rrik, VDBPSADBWZ256rrik)>;
+
+def 4GM7WriteDBPSADBWZrmikLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteDBPSADBWZrrik.Latency);
+ let ReleaseAtCycles = [1, 1, 6, 6];
+ let NumMicroOps = 5;
+}
+def : InstRW<[4GM7WriteDBPSADBWZrmikLd], (instrs VDBPSADBWZrmik, VDBPSADBWZ128rmik, VDBPSADBWZ256rmik)>;
+
+// VecLogicZ rrk
+def 4GM7WriteVecLogicZ:SchedWriteRes<[4GM7FPU]> {
+ let Latency = 2;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVecLogicZ], (instregex "VPAND(D|Q)Z(128|256)?rrk$",
+ "VPANDN(D|Q)Z(128|256)?rrk$",
+ "VPOR(D|Q)Z(128|256)?rrk$",
+ "VPXOR(D|Q)Z(128|256)?rrk$",
+ "VANDNP(D|S)Z(128|256)?rrk$",
+ "VANDP(D|S)Z(128|256)?rrk$",
+ "VORP(D|S)Z(128|256)?rrk$",
+ "VXORP(D|S)Z(128|256)?rrk$")>;
+
+def 4GM7WriteVecLogicZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVecLogicZ.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVecLogicZLd], (instregex "VPAND(D|Q)Z(128|256)?rmk$",
+ "VPANDN(D|Q)Z(128|256)?rmk$",
+ "VPOR(D|Q)Z(128|256)?rmk$",
+ "VPXOR(D|Q)Z(128|256)?rmk$",
+ "VANDNP(D|S)Z(128|256)?rmk$",
+ "VANDP(D|S)Z(128|256)?rmk$",
+ "VORP(D|S)Z(128|256)?rmk$",
+ "VXORP(D|S)Z(128|256)?rmk$")>;
+
+// GF2P8MULB
+def 4GM7WriteGF2P8MULB:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 3;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteGF2P8MULB], (instrs GF2P8MULBrr, VGF2P8MULBrr, VGF2P8MULBYrr)>;
+
+def 4GM7WriteGF2P8MULBLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteGF2P8MULB.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteGF2P8MULBLd], (instrs GF2P8MULBrm, VGF2P8MULBrm, VGF2P8MULBYrm)>;
+
+def 4GM7WriteGF2P8MULBXYZ:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 3;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteGF2P8MULBXYZ], (instrs VGF2P8MULBZrr, VGF2P8MULBZrrkz,
+ VGF2P8MULBZ128rr, VGF2P8MULBZ128rrkz,
+ VGF2P8MULBZ256rr, VGF2P8MULBZ256rrkz)>;
+
+def 4GM7WriteGF2P8MULBXYZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteGF2P8MULBXYZ.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteGF2P8MULBXYZLd], (instrs VGF2P8MULBZrm, VGF2P8MULBZrmkz,
+ VGF2P8MULBZ128rm, VGF2P8MULBZ128rmkz,
+ VGF2P8MULBZ256rm, VGF2P8MULBZ256rmkz)>;
+
+def 4GM7WriteGF2P8MULBXYZrrk:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteGF2P8MULBXYZrrk], (instrs VGF2P8MULBZrrk, VGF2P8MULBZ128rrk, VGF2P8MULBZ256rrk)>;
+
+def 4GM7WriteGF2P8MULBXYZrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteGF2P8MULBXYZrrk.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteGF2P8MULBXYZrmk], (instrs VGF2P8MULBZrmk, VGF2P8MULBZ128rmk, VGF2P8MULBZ256rmk)>;
+
+// VGF2P8AFFINE
+def 4GM7WriteVGF2P8AFFINEZ:SchedWriteRes<[4GM7FPU13]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVGF2P8AFFINEZ], (instrs VGF2P8AFFINEQBZrrik, VGF2P8AFFINEQBZ128rrik, VGF2P8AFFINEQBZ256rrik,
+ VGF2P8AFFINEINVQBZrrik, VGF2P8AFFINEINVQBZ128rrik, VGF2P8AFFINEINVQBZ256rrik)>;
+
+def 4GM7WriteVGF2P8AFFINEZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVGF2P8AFFINEZ.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteVGF2P8AFFINEZLd], (instrs VGF2P8AFFINEQBZrmik, VGF2P8AFFINEQBZ128rmik, VGF2P8AFFINEQBZ256rmik,
+ VGF2P8AFFINEINVQBZrmik, VGF2P8AFFINEINVQBZ128rmik, VGF2P8AFFINEINVQBZ256rmik)>;
+
+// Vector insert/extract operations.
+defm : 4GM7WriteResFPPair<WriteVecInsert, [4GM7FPU13], 2>;
+defm : 4GM7WriteRes<WriteVecExtract, [4GM7FPU02], 1, [4], 1>;
+defm : 4GM7WriteRes<WriteVecExtractSt, [4GM7FPU02, 4GM7AGU, 4GM7Store], 3, [4, 1, 1], 1>;
+
+// MOVMSK Instructions.
+defm : 4GM7WriteRes<WriteFMOVMSK, [4GM7FPU13], 1>;
+defm : 4GM7WriteRes<WriteMMXMOVMSK, [4GM7FPU13], 1>;
+defm : 4GM7WriteRes<WriteVecMOVMSK, [4GM7FPU13], 1>;
+defm : 4GM7WriteRes<WriteVecMOVMSKY, [4GM7FPU13], 1>;
+
+// Strings instructions.
+defm : 4GM7WriteResFPPair<WritePCmpIStrM, [4GM7FPU], 7, [25], 3>;
+defm : 4GM7WriteResFPPair<WritePCmpEStrM, [4GM7FPU], 7, [25], 8>;
+defm : 4GM7WriteResFPPair<WritePCmpIStrI, [4GM7FPU], 2, [8], 2>;
+defm : 4GM7WriteResFPPair<WritePCmpEStrI, [4GM7FPU], 8, [13], 8>;
+
+// AES Instructions.
+defm : 4GM7WriteResFPPair<WriteAESDecEnc, [4GM7FPU13], 3>;
+defm : 4GM7WriteResFPPair<WriteAESIMC, [4GM7FPU13], 3>;
+defm : 4GM7WriteResFPPair<WriteAESKeyGen, [4GM7FPU13], 3>;
+
+// SHA Instructions.
+
+def 4GM7WriteSHA1rr:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 1;
+ let ReleaseAtCycles = [1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteSHA1rr], (instrs SHA1MSG1rr, SHA1MSG2rr, SHA1NEXTErr)>;
+
+def 4GM7WriteSHA1rm:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteSHA1rr.Latency);
+ let ReleaseAtCycles = [1, 1, 1];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteSHA1rm], (instrs SHA1MSG1rm, SHA1MSG2rm, SHA1NEXTErm)>;
+
+def 4GM7WriteSHA256MSG1rr:SchedWriteRes<[4GM7FPU]> {
+ let Latency = 2;
+ let ReleaseAtCycles = [2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteSHA256MSG1rr], (instrs SHA256MSG1rr)>;
+
+def 4GM7WriteSHA256MSG1rm:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteSHA256MSG1rr.Latency);
+ let ReleaseAtCycles = [1, 1, 2];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteSHA256MSG1rm], (instrs SHA256MSG1rm)>;
+
+def 4GM7WriteSHA256rr:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteSHA256rr], (instrs SHA256MSG2rr, SHA256RNDS2rr)>;
+
+def 4GM7WriteSHA256rm:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteSHA256rr.Latency);
+ let ReleaseAtCycles = [1, 1, 4];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteSHA256rm], (instrs SHA256MSG2rm, SHA256RNDS2rm)>;
+
+def 4GM7WriteSHA1RNDS4rri:SchedWriteRes<[4GM7FPU02]> {
+ let Latency = 5;
+ let ReleaseAtCycles = [8];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteSHA1RNDS4rri], (instrs SHA1RNDS4rri)>;
+
+def 4GM7WriteSHA1RNDS4rmi:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteSHA1RNDS4rri.Latency);
+ let ReleaseAtCycles = [1, 1, 8];
+ let NumMicroOps = 1;
+}
+def : InstRW<[4GM7WriteSHA1RNDS4rmi], (instrs SHA1RNDS4rmi)>;
+
+defm : 4GM7WriteRes<WriteFence, [4GM7AGU]>;
+defm : 4GM7WriteRes<WriteNop, []>;
+
+//===----------------------------------------------------------------------===//
+// Zero Cycle Move
+//===----------------------------------------------------------------------===//
+
+def 4GM7WriteZeroLatency : SchedWriteRes<[]> {
+ let Latency = 0;
+ let ReleaseAtCycles = [];
+ let NumMicroOps = 1;
+}
+
+def : InstRW<[4GM7WriteZeroLatency], (instrs MOV32rr, MOV32rr_REV,
+ MOV64rr, MOV64rr_REV,
+ MOVSX32rr32)>;
+
+def 4GM7WriteSwapRenameable : SchedWriteRes<[]> {
+ let Latency = 0;
+ let ReleaseAtCycles = [];
+ let NumMicroOps = 2;
+}
+def : InstRW<[4GM7WriteSwapRenameable], (instrs XCHG32rr, XCHG32ar,
+ XCHG64rr, XCHG64ar)>;
+
+defm : 4GM7WriteRes<WriteXCHG, [4GM7ALU], 0, [8], 2>;
+
+defm : 4GM7WriteRes<WriteFMoveX, [], 0, [], 1>;
+defm : 4GM7WriteRes<WriteFMoveY, [], 0, [], 1>;
+defm : 4GM7WriteRes<WriteFMoveZ, [], 0, [], 1>;
+
+defm : 4GM7WriteRes<WriteVecMove, [], 0, [], 1>;
+defm : 4GM7WriteRes<WriteVecMoveX, [], 0, [], 1>;
+defm : 4GM7WriteRes<WriteVecMoveY, [], 0, [], 1>;
+defm : 4GM7WriteRes<WriteVecMoveZ, [], 0, [], 1>;
+
+def : IsOptimizableRegisterMove<[
+ InstructionEquivalenceClass<[
+ // GPR variants.
+ MOV32rr, MOV32rr_REV,
+ MOV64rr, MOV64rr_REV,
+ MOVSX32rr32,
+ XCHG32rr, XCHG32ar,
+ XCHG64rr, XCHG64ar,
+
+ // MMX variants.
+ // MMX moves are *NOT* eliminated.
+
+ // SSE variants.
+ MOVAPSrr, MOVAPSrr_REV,
+ MOVUPSrr, MOVUPSrr_REV,
+ MOVAPDrr, MOVAPDrr_REV,
+ MOVUPDrr, MOVUPDrr_REV,
+ MOVDQArr, MOVDQArr_REV,
+ MOVDQUrr, MOVDQUrr_REV,
+
+ // AVX variants.
+ VMOVAPSrr, VMOVAPSrr_REV,
+ VMOVUPSrr, VMOVUPSrr_REV,
+ VMOVAPDrr, VMOVAPDrr_REV,
+ VMOVUPDrr, VMOVUPDrr_REV,
+ VMOVDQArr, VMOVDQArr_REV,
+ VMOVDQUrr, VMOVDQUrr_REV,
+
+ // AVX YMM variants.
+ VMOVAPSYrr, VMOVAPSYrr_REV,
+ VMOVUPSYrr, VMOVUPSYrr_REV,
+ VMOVAPDYrr, VMOVAPDYrr_REV,
+ VMOVUPDYrr, VMOVUPDYrr_REV,
+ VMOVDQAYrr, VMOVDQAYrr_REV,
+ VMOVDQUYrr, VMOVDQUYrr_REV,
+ ], TruePred >
+]>;
+
+//===----------------------------------------------------------------------===//
+// Dependency breaking instructions.
+//===----------------------------------------------------------------------===//
+
+def 4GM7WriteZeroIdiom : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM7WriteZeroLatency]>,
+ SchedVar<NoSchedPred, [WriteALU]>
+]>;
+def : InstRW<[4GM7WriteZeroIdiom], (instrs XOR32rr, XOR32rr_REV,
+ XOR64rr, XOR64rr_REV,
+ SUB32rr, SUB32rr_REV,
+ SUB64rr, SUB64rr_REV)>;
+
+def 4GM7WriteZeroIdiomEFLAGS : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<CheckSameRegOperand<0, 1>>, [4GM7WriteZeroLatency]>,
+ SchedVar<NoSchedPred, [WriteALU]>
+]>;
+def : InstRW<[4GM7WriteZeroIdiomEFLAGS], (instrs CMP8rr, CMP8rr_REV,
+ CMP16rr, CMP16rr_REV,
+ CMP32rr, CMP32rr_REV,
+ CMP64rr, CMP64rr_REV)>;
+
+def 4GM7WriteFZeroIdiom : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM7WriteZeroLatency]>,
+ SchedVar<NoSchedPred, [WriteFLogic]>
+]>;
+
+def : InstRW<[4GM7WriteFZeroIdiom], (instrs VXORPSrr, VXORPDrr,
+ VXORPSZ128rr,
+ VXORPDZ128rr,
+ VANDNPSrr, VANDNPDrr,
+ VANDNPSZ128rr,
+ VANDNPDZ128rr)>;
+
+def 4GM7WriteFZeroIdiomY : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM7WriteZeroLatency]>,
+ SchedVar<NoSchedPred, [WriteFLogicY]>
+]>;
+def : InstRW<[4GM7WriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr,
+ VXORPSZ256rr,
+ VXORPDZ256rr,
+ VANDNPSYrr, VANDNPDYrr,
+ VANDNPSZ256rr,
+ VANDNPDZ256rr)>;
+
+def 4GM7WriteFZeroIdiomZ : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM7WriteZeroLatency]>,
+ SchedVar<NoSchedPred, [WriteFLogicZ]>
+]>;
+def : InstRW<[4GM7WriteFZeroIdiomZ], (instrs VXORPSZrr, VXORPDZrr,
+ VANDNPSZrr, VANDNPDZrr)>;
+
+def 4GM7WriteVZeroIdiomLogicX : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM7WriteZeroLatency]>,
+ SchedVar<NoSchedPred, [WriteVecLogicX]>
+]>;
+
+def : InstRW<[4GM7WriteVZeroIdiomLogicX], (instrs VPXORrr,
+ VPXORDZ128rr,
+ VPXORQZ128rr,
+ VPANDNrr,
+ VPANDNDZ128rr,
+ VPANDNQZ128rr)>;
+
+def 4GM7WriteVZeroIdiomLogicY : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM7WriteZeroLatency]>,
+ SchedVar<NoSchedPred, [WriteVecLogicY]>
+]>;
+def : InstRW<[4GM7WriteVZeroIdiomLogicY], (instrs VPXORYrr,
+ VPXORDZ256rr,
+ VPXORQZ256rr,
+ VPANDNYrr,
+ VPANDNDZ256rr,
+ VPANDNQZ256rr)>;
+
+def 4GM7WriteVZeroIdiomLogicZ : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM7WriteZeroLatency]>,
+ SchedVar<NoSchedPred, [WriteVecLogicZ]>
+]>;
+def : InstRW<[4GM7WriteVZeroIdiomLogicZ], (instrs VPXORDZrr, VPXORQZrr,
+ VPANDNDZrr, VPANDNQZrr)>;
+
+def 4GM7WriteVZeroIdiomALUX : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM7WriteZeroLatency]>,
+ SchedVar<NoSchedPred, [WriteVecALUX]>
+]>;
+
+
+def : InstRW<[4GM7WriteVZeroIdiomALUX],
+ (instrs VPSUBBrr, VPSUBWrr, VPSUBDrr, VPSUBQrr,
+ VPSUBBZ128rr, VPSUBWZ128rr, VPSUBDZ128rr, VPSUBQZ128rr,
+ VPCMPGTBrr, VPCMPGTWrr, VPCMPGTDrr, VPCMPGTQrr,
+ VPCMPGTBZ128rr, VPCMPGTWZ128rr,
+ VPCMPGTDZ128rr, VPCMPGTQZ128rr)>;
+
+def 4GM7WriteVZeroIdiomALUY : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM7WriteZeroLatency]>,
+ SchedVar<NoSchedPred, [WriteVecALUY]>
+]>;
+def : InstRW<[4GM7WriteVZeroIdiomALUY],
+ (instrs VPSUBBYrr, VPSUBWYrr, VPSUBDYrr, VPSUBQYrr,
+ VPSUBBZ256rr, VPSUBWZ256rr, VPSUBDZ256rr, VPSUBQZ256rr,
+ VPCMPGTBYrr, VPCMPGTWYrr, VPCMPGTDYrr, VPCMPGTQYrr,
+ VPCMPGTBZ256rr, VPCMPGTWZ256rr,
+ VPCMPGTDZ256rr, VPCMPGTQZ256rr)>;
+
+def 4GM7WriteVZeroIdiomALUZ : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM7WriteZeroLatency]>,
+ SchedVar<NoSchedPred, [WriteVecALUZ]>
+]>;
+def : InstRW<[4GM7WriteVZeroIdiomALUY],
+ (instrs VPSUBBZrr, VPSUBWZrr, VPSUBDZrr, VPSUBQZrr,
+ VPCMPGTBZrr, VPCMPGTWZrr, VPCMPGTDZrr, VPCMPGTQZrr)>;
+
+def : IsZeroIdiomFunction<[
+ // GPR Zero-idioms.
+ DepBreakingClass<[ XOR32rr, XOR32rr_REV,
+ XOR64rr, XOR64rr_REV,
+ SUB32rr, SUB32rr_REV,
+ SUB64rr, SUB64rr_REV ], ZeroIdiomPredicate>,
+
+ // SSE XMM Zero-idioms.
+ DepBreakingClass<[
+ // fp variants.
+ XORPSrr, XORPDrr,
+ ANDNPSrr, ANDNPDrr,
+
+ // int variants.
+ PXORrr,
+ PANDNrr,
+ PSUBBrr, PSUBWrr, PSUBDrr, PSUBQrr,
+ PSUBSBrr, PSUBSWrr,
+ PSUBUSBrr, PSUBUSWrr,
+ PCMPGTBrr, PCMPGTWrr, PCMPGTDrr, PCMPGTQrr
+ ], ZeroIdiomPredicate>,
+
+ // AVX XMM Zero-idioms.
+ DepBreakingClass<[
+ // fp variants.
+ VXORPSrr, VXORPDrr,
+ VANDNPSrr, VANDNPDrr,
+
+ // int variants.
+ VPXORrr,
+ VPANDNrr,
+ VPSUBBrr, VPSUBWrr, VPSUBDrr, VPSUBQrr,
+ VPSUBSBrr, VPSUBSWrr,
+ VPSUBUSBrr, VPSUBUSWrr,
+ VPCMPGTBrr, VPCMPGTWrr, VPCMPGTDrr, VPCMPGTQrr,
+ ], ZeroIdiomPredicate>,
+
+ // AVX YMM Zero-idioms.
+ DepBreakingClass<[
+ // fp variants.
+ VXORPSYrr, VXORPDYrr,
+ VANDNPSYrr, VANDNPDYrr,
+
+ // int variants.
+ VPXORYrr,
+ VPANDNYrr,
+ VPSUBBYrr, VPSUBWYrr, VPSUBDYrr, VPSUBQYrr,
+ VPSUBSBYrr, VPSUBSWYrr,
+ VPSUBUSBYrr, VPSUBUSWYrr,
+ VPCMPGTBYrr, VPCMPGTWYrr, VPCMPGTDYrr, VPCMPGTQYrr
+ ], ZeroIdiomPredicate>,
+
+ // AVX ZMM Zero-idioms.
+ DepBreakingClass<[
+ // fp variants.
+ VXORPSZrr, VXORPDZrr,
+ VXORPSZ128rr, VXORPDZ128rr, VXORPSZ256rr, VXORPDZ256rr,
+ VANDNPSZrr, VANDNPDZrr,
+ VANDNPSZ128rr, VANDNPDZ128rr, VANDNPSZ256rr, VANDNPDZ256rr,
+
+ // int variants.
+ VPCMPGTBZrr, VPCMPGTWZrr, VPCMPGTDZrr, VPCMPGTQZrr,
+ VPCMPGTBZ128rr, VPCMPGTWZ128rr, VPCMPGTDZ128rr, VPCMPGTQZ128rr,
+ VPCMPGTBZ256rr, VPCMPGTWZ256rr, VPCMPGTDZ256rr, VPCMPGTQZ256rr,
+ VPANDNDZrr, VPANDNQZrr,
+ VPANDNDZ128rr, VPANDNQZ128rr, VPANDNDZ256rr, VPANDNQZ256rr,
+ VPXORDZrr, VPXORQZrr,
+ VPXORDZ128rr, VPXORQZ128rr, VPXORDZ256rr, VPXORQZ256rr,
+ VPSUBBZrr, VPSUBWZrr, VPSUBDZrr, VPSUBQZrr,
+ VPSUBBZ128rr, VPSUBWZ128rr, VPSUBDZ128rr, VPSUBQZ128rr,
+ VPSUBBZ256rr, VPSUBWZ256rr, VPSUBDZ256rr, VPSUBQZ256rr,
+ ], ZeroIdiomPredicate>,
+]>;
+
+def : IsDepBreakingFunction<[
+ // GPR
+ DepBreakingClass<[ SBB32rr, SBB32rr_REV,
+ SBB64rr, SBB64rr_REV ], ZeroIdiomPredicate>,
+ DepBreakingClass<[ CMP8rr, CMP8rr_REV,
+ CMP16rr, CMP16rr_REV,
+ CMP32rr, CMP32rr_REV,
+ CMP64rr, CMP64rr_REV ], CheckSameRegOperand<0, 1> >,
+ // SSE
+ DepBreakingClass<[
+ PCMPEQBrr, PCMPEQWrr, PCMPEQDrr, PCMPEQQrr
+ ], ZeroIdiomPredicate>,
+
+ // AVX XMM
+ DepBreakingClass<[
+ VPCMPEQBrr, VPCMPEQWrr, VPCMPEQDrr, VPCMPEQQrr
+ ], ZeroIdiomPredicate>,
+
+ // AVX YMM
+ DepBreakingClass<[
+ VPCMPEQBYrr, VPCMPEQWYrr, VPCMPEQDYrr, VPCMPEQQYrr
+ ], ZeroIdiomPredicate>,
+]>;
+
+} // SchedModel
\ No newline at end of file
diff --git a/llvm/test/CodeGen/X86/bypass-slow-division-64.ll b/llvm/test/CodeGen/X86/bypass-slow-division-64.ll
index f60d7f011c7d5..98c51f2260d96 100644
--- a/llvm/test/CodeGen/X86/bypass-slow-division-64.ll
+++ b/llvm/test/CodeGen/X86/bypass-slow-division-64.ll
@@ -25,6 +25,7 @@
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver5 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver6 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
+; Hygon
; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m4 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m6 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
; RUN: llc < %s -mtriple=x86_64-- -mcpu=c86-4g-m7 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-adx.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-adx.s
new file mode 100644
index 0000000000000..97ac4c0b59242
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-adx.s
@@ -0,0 +1,66 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+adcx %ebx, %ecx
+adcx (%rbx), %ecx
+adcx %rbx, %rcx
+adcx (%rbx), %rcx
+
+adox %ebx, %ecx
+adox (%rbx), %ecx
+adox %rbx, %rcx
+adox (%rbx), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.17 adcxl %ebx, %ecx
+# CHECK-NEXT: 1 5 0.50 * adcxl (%rbx), %ecx
+# CHECK-NEXT: 1 1 0.17 adcxq %rbx, %rcx
+# CHECK-NEXT: 1 5 0.50 * adcxq (%rbx), %rcx
+# CHECK-NEXT: 1 1 0.17 adoxl %ebx, %ecx
+# CHECK-NEXT: 1 5 0.50 * adoxl (%rbx), %ecx
+# CHECK-NEXT: 1 1 0.17 adoxq %rbx, %rcx
+# CHECK-NEXT: 1 5 0.50 * adoxq (%rbx), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: 1.33 1.33 1.33 2.67 1.33 1.33 2.67 - - - - 1.33 1.33 1.33 2.00 2.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - adcxl %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - adcxl (%rbx), %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - adcxq %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - adcxq (%rbx), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - adoxl %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - adoxl (%rbx), %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - adoxq %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - adoxq (%rbx), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-aes.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-aes.s
new file mode 100644
index 0000000000000..7d15f2c3b0e2b
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-aes.s
@@ -0,0 +1,82 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+aesdec %xmm0, %xmm2
+aesdec (%rax), %xmm2
+
+aesdeclast %xmm0, %xmm2
+aesdeclast (%rax), %xmm2
+
+aesenc %xmm0, %xmm2
+aesenc (%rax), %xmm2
+
+aesenclast %xmm0, %xmm2
+aesenclast (%rax), %xmm2
+
+aesimc %xmm0, %xmm2
+aesimc (%rax), %xmm2
+
+aeskeygenassist $22, %xmm0, %xmm2
+aeskeygenassist $22, (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 4 0.50 aesdec %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * aesdec (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 aesdeclast %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * aesdeclast (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 aesenc %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * aesenc (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 aesenclast %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * aesenclast (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 aesimc %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * aesimc (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 aeskeygenassist $22, %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * aeskeygenassist $22, (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: 2.00 2.00 2.00 - - - - - - 6.00 6.00 2.00 2.00 2.00 3.00 3.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - aesdec %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 0.50 0.33 0.33 0.33 0.50 0.50 - - - aesdec (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - aesdeclast %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 0.50 0.33 0.33 0.33 0.50 0.50 - - - aesdeclast (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - aesenc %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 0.50 0.33 0.33 0.33 0.50 0.50 - - - aesenc (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - aesenclast %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 0.50 0.33 0.33 0.33 0.50 0.50 - - - aesenclast (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - aesimc %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 0.50 0.33 0.33 0.33 0.50 0.50 - - - aesimc (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - aeskeygenassist $22, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 0.50 0.33 0.33 0.33 0.50 0.50 - - - aeskeygenassist $22, (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-avx1.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-avx1.s
new file mode 100644
index 0000000000000..89282a4c67e16
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-avx1.s
@@ -0,0 +1,2442 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+vaddpd %xmm0, %xmm1, %xmm2
+vaddpd (%rax), %xmm1, %xmm2
+
+vaddpd %ymm0, %ymm1, %ymm2
+vaddpd (%rax), %ymm1, %ymm2
+
+vaddps %xmm0, %xmm1, %xmm2
+vaddps (%rax), %xmm1, %xmm2
+
+vaddps %ymm0, %ymm1, %ymm2
+vaddps (%rax), %ymm1, %ymm2
+
+vaddsd %xmm0, %xmm1, %xmm2
+vaddsd (%rax), %xmm1, %xmm2
+
+vaddss %xmm0, %xmm1, %xmm2
+vaddss (%rax), %xmm1, %xmm2
+
+vaddsubpd %xmm0, %xmm1, %xmm2
+vaddsubpd (%rax), %xmm1, %xmm2
+
+vaddsubpd %ymm0, %ymm1, %ymm2
+vaddsubpd (%rax), %ymm1, %ymm2
+
+vaddsubps %xmm0, %xmm1, %xmm2
+vaddsubps (%rax), %xmm1, %xmm2
+
+vaddsubps %ymm0, %ymm1, %ymm2
+vaddsubps (%rax), %ymm1, %ymm2
+
+vaesdec %xmm0, %xmm1, %xmm2
+vaesdec (%rax), %xmm1, %xmm2
+
+vaesdeclast %xmm0, %xmm1, %xmm2
+vaesdeclast (%rax), %xmm1, %xmm2
+
+vaesenc %xmm0, %xmm1, %xmm2
+vaesenc (%rax), %xmm1, %xmm2
+
+vaesenclast %xmm0, %xmm1, %xmm2
+vaesenclast (%rax), %xmm1, %xmm2
+
+vaesimc %xmm0, %xmm2
+vaesimc (%rax), %xmm2
+
+vaeskeygenassist $22, %xmm0, %xmm2
+vaeskeygenassist $22, (%rax), %xmm2
+
+vandnpd %xmm0, %xmm1, %xmm2
+vandnpd (%rax), %xmm1, %xmm2
+
+vandnpd %ymm0, %ymm1, %ymm2
+vandnpd (%rax), %ymm1, %ymm2
+
+vandnps %xmm0, %xmm1, %xmm2
+vandnps (%rax), %xmm1, %xmm2
+
+vandnps %ymm0, %ymm1, %ymm2
+vandnps (%rax), %ymm1, %ymm2
+
+vandpd %xmm0, %xmm1, %xmm2
+vandpd (%rax), %xmm1, %xmm2
+
+vandpd %ymm0, %ymm1, %ymm2
+vandpd (%rax), %ymm1, %ymm2
+
+vandps %xmm0, %xmm1, %xmm2
+vandps (%rax), %xmm1, %xmm2
+
+vandps %ymm0, %ymm1, %ymm2
+vandps (%rax), %ymm1, %ymm2
+
+vblendpd $11, %xmm0, %xmm1, %xmm2
+vblendpd $11, (%rax), %xmm1, %xmm2
+
+vblendpd $11, %ymm0, %ymm1, %ymm2
+vblendpd $11, (%rax), %ymm1, %ymm2
+
+vblendps $11, %xmm0, %xmm1, %xmm2
+vblendps $11, (%rax), %xmm1, %xmm2
+
+vblendps $11, %ymm0, %ymm1, %ymm2
+vblendps $11, (%rax), %ymm1, %ymm2
+
+vblendvpd %xmm3, %xmm0, %xmm1, %xmm2
+vblendvpd %xmm3, (%rax), %xmm1, %xmm2
+
+vblendvpd %ymm3, %ymm0, %ymm1, %ymm2
+vblendvpd %ymm3, (%rax), %ymm1, %ymm2
+
+vblendvps %xmm3, %xmm0, %xmm1, %xmm2
+vblendvps %xmm3, (%rax), %xmm1, %xmm2
+
+vblendvps %ymm3, %ymm0, %ymm1, %ymm2
+vblendvps %ymm3, (%rax), %ymm1, %ymm2
+
+vbroadcastf128 (%rax), %ymm2
+
+vbroadcastsd (%rax), %ymm2
+
+vbroadcastss (%rax), %xmm2
+vbroadcastss (%rax), %ymm2
+
+vcmppd $0, %xmm0, %xmm1, %xmm2
+vcmppd $0, (%rax), %xmm1, %xmm2
+
+vcmppd $0, %ymm0, %ymm1, %ymm2
+vcmppd $0, (%rax), %ymm1, %ymm2
+
+vcmpps $0, %xmm0, %xmm1, %xmm2
+vcmpps $0, (%rax), %xmm1, %xmm2
+
+vcmpps $0, %ymm0, %ymm1, %ymm2
+vcmpps $0, (%rax), %ymm1, %ymm2
+
+vcmpsd $0, %xmm0, %xmm1, %xmm2
+vcmpsd $0, (%rax), %xmm1, %xmm2
+
+vcmpss $0, %xmm0, %xmm1, %xmm2
+vcmpss $0, (%rax), %xmm1, %xmm2
+
+vcomisd %xmm0, %xmm1
+vcomisd (%rax), %xmm1
+
+vcomiss %xmm0, %xmm1
+vcomiss (%rax), %xmm1
+
+vcvtdq2pd %xmm0, %xmm2
+vcvtdq2pd (%rax), %xmm2
+
+vcvtdq2pd %xmm0, %ymm2
+vcvtdq2pd (%rax), %ymm2
+
+vcvtdq2ps %xmm0, %xmm2
+vcvtdq2ps (%rax), %xmm2
+
+vcvtdq2ps %ymm0, %ymm2
+vcvtdq2ps (%rax), %ymm2
+
+vcvtpd2dqx %xmm0, %xmm2
+vcvtpd2dqx (%rax), %xmm2
+
+vcvtpd2dqy %ymm0, %xmm2
+vcvtpd2dqy (%rax), %xmm2
+
+vcvtpd2psx %xmm0, %xmm2
+vcvtpd2psx (%rax), %xmm2
+
+vcvtpd2psy %ymm0, %xmm2
+vcvtpd2psy (%rax), %xmm2
+
+vcvtps2dq %xmm0, %xmm2
+vcvtps2dq (%rax), %xmm2
+
+vcvtps2dq %ymm0, %ymm2
+vcvtps2dq (%rax), %ymm2
+
+vcvtps2pd %xmm0, %xmm2
+vcvtps2pd (%rax), %xmm2
+
+vcvtps2pd %xmm0, %ymm2
+vcvtps2pd (%rax), %ymm2
+
+vcvtsd2si %xmm0, %ecx
+vcvtsd2si %xmm0, %rcx
+vcvtsd2si (%rax), %ecx
+vcvtsd2si (%rax), %rcx
+
+vcvtsd2ss %xmm0, %xmm1, %xmm2
+vcvtsd2ss (%rax), %xmm1, %xmm2
+
+vcvtsi2sdl %ecx, %xmm0, %xmm2
+vcvtsi2sdq %rcx, %xmm0, %xmm2
+vcvtsi2sdl (%rax), %xmm0, %xmm2
+vcvtsi2sdq (%rax), %xmm0, %xmm2
+
+vcvtsi2ssl %ecx, %xmm0, %xmm2
+vcvtsi2ssq %rcx, %xmm0, %xmm2
+vcvtsi2ssl (%rax), %xmm0, %xmm2
+vcvtsi2ssq (%rax), %xmm0, %xmm2
+
+vcvtss2sd %xmm0, %xmm1, %xmm2
+vcvtss2sd (%rax), %xmm1, %xmm2
+
+vcvtss2si %xmm0, %ecx
+vcvtss2si %xmm0, %rcx
+vcvtss2si (%rax), %ecx
+vcvtss2si (%rax), %rcx
+
+vcvttpd2dqx %xmm0, %xmm2
+vcvttpd2dqx (%rax), %xmm2
+
+vcvttpd2dqy %ymm0, %xmm2
+vcvttpd2dqy (%rax), %xmm2
+
+vcvttps2dq %xmm0, %xmm2
+vcvttps2dq (%rax), %xmm2
+
+vcvttps2dq %ymm0, %ymm2
+vcvttps2dq (%rax), %ymm2
+
+vcvttsd2si %xmm0, %ecx
+vcvttsd2si %xmm0, %rcx
+vcvttsd2si (%rax), %ecx
+vcvttsd2si (%rax), %rcx
+
+vcvttss2si %xmm0, %ecx
+vcvttss2si %xmm0, %rcx
+vcvttss2si (%rax), %ecx
+vcvttss2si (%rax), %rcx
+
+vdivpd %xmm0, %xmm1, %xmm2
+vdivpd (%rax), %xmm1, %xmm2
+
+vdivpd %ymm0, %ymm1, %ymm2
+vdivpd (%rax), %ymm1, %ymm2
+
+vdivps %xmm0, %xmm1, %xmm2
+vdivps (%rax), %xmm1, %xmm2
+
+vdivps %ymm0, %ymm1, %ymm2
+vdivps (%rax), %ymm1, %ymm2
+
+vdivsd %xmm0, %xmm1, %xmm2
+vdivsd (%rax), %xmm1, %xmm2
+
+vdivss %xmm0, %xmm1, %xmm2
+vdivss (%rax), %xmm1, %xmm2
+
+vdppd $22, %xmm0, %xmm1, %xmm2
+vdppd $22, (%rax), %xmm1, %xmm2
+
+vdpps $22, %xmm0, %xmm1, %xmm2
+vdpps $22, (%rax), %xmm1, %xmm2
+
+vdpps $22, %ymm0, %ymm1, %ymm2
+vdpps $22, (%rax), %ymm1, %ymm2
+
+vextractf128 $1, %ymm0, %xmm2
+vextractf128 $1, %ymm0, (%rax)
+
+vextractps $1, %xmm0, %rcx
+vextractps $1, %xmm0, (%rax)
+
+vhaddpd %xmm0, %xmm1, %xmm2
+vhaddpd (%rax), %xmm1, %xmm2
+
+vhaddpd %ymm0, %ymm1, %ymm2
+vhaddpd (%rax), %ymm1, %ymm2
+
+vhaddps %xmm0, %xmm1, %xmm2
+vhaddps (%rax), %xmm1, %xmm2
+
+vhaddps %ymm0, %ymm1, %ymm2
+vhaddps (%rax), %ymm1, %ymm2
+
+vhsubpd %xmm0, %xmm1, %xmm2
+vhsubpd (%rax), %xmm1, %xmm2
+
+vhsubpd %ymm0, %ymm1, %ymm2
+vhsubpd (%rax), %ymm1, %ymm2
+
+vhsubps %xmm0, %xmm1, %xmm2
+vhsubps (%rax), %xmm1, %xmm2
+
+vhsubps %ymm0, %ymm1, %ymm2
+vhsubps (%rax), %ymm1, %ymm2
+
+vinsertf128 $1, %xmm0, %ymm1, %ymm2
+vinsertf128 $1, (%rax), %ymm1, %ymm2
+
+vinsertps $1, %xmm0, %xmm1, %xmm2
+vinsertps $1, (%rax), %xmm1, %xmm2
+
+vlddqu (%rax), %xmm2
+vlddqu (%rax), %ymm2
+
+vldmxcsr (%rax)
+
+vmaskmovdqu %xmm0, %xmm1
+
+vmaskmovpd (%rax), %xmm0, %xmm2
+vmaskmovpd (%rax), %ymm0, %ymm2
+
+vmaskmovpd %xmm0, %xmm1, (%rax)
+vmaskmovpd %ymm0, %ymm1, (%rax)
+
+vmaskmovps (%rax), %xmm0, %xmm2
+vmaskmovps (%rax), %ymm0, %ymm2
+
+vmaskmovps %xmm0, %xmm1, (%rax)
+vmaskmovps %ymm0, %ymm1, (%rax)
+
+vmaxpd %xmm0, %xmm1, %xmm2
+vmaxpd (%rax), %xmm1, %xmm2
+
+vmaxpd %ymm0, %ymm1, %ymm2
+vmaxpd (%rax), %ymm1, %ymm2
+
+vmaxps %xmm0, %xmm1, %xmm2
+vmaxps (%rax), %xmm1, %xmm2
+
+vmaxps %ymm0, %ymm1, %ymm2
+vmaxps (%rax), %ymm1, %ymm2
+
+vmaxsd %xmm0, %xmm1, %xmm2
+vmaxsd (%rax), %xmm1, %xmm2
+
+vmaxss %xmm0, %xmm1, %xmm2
+vmaxss (%rax), %xmm1, %xmm2
+
+vminpd %xmm0, %xmm1, %xmm2
+vminpd (%rax), %xmm1, %xmm2
+
+vminpd %ymm0, %ymm1, %ymm2
+vminpd (%rax), %ymm1, %ymm2
+
+vminps %xmm0, %xmm1, %xmm2
+vminps (%rax), %xmm1, %xmm2
+
+vminps %ymm0, %ymm1, %ymm2
+vminps (%rax), %ymm1, %ymm2
+
+vminsd %xmm0, %xmm1, %xmm2
+vminsd (%rax), %xmm1, %xmm2
+
+vminss %xmm0, %xmm1, %xmm2
+vminss (%rax), %xmm1, %xmm2
+
+vmovapd %xmm0, %xmm2
+vmovapd %xmm0, (%rax)
+vmovapd (%rax), %xmm2
+
+vmovapd %ymm0, %ymm2
+vmovapd %ymm0, (%rax)
+vmovapd (%rax), %ymm2
+
+vmovaps %xmm0, %xmm2
+vmovaps %xmm0, (%rax)
+vmovaps (%rax), %xmm2
+
+vmovaps %ymm0, %ymm2
+vmovaps %ymm0, (%rax)
+vmovaps (%rax), %ymm2
+
+vmovd %eax, %xmm2
+vmovd (%rax), %xmm2
+
+vmovd %xmm0, %ecx
+vmovd %xmm0, (%rax)
+
+vmovddup %xmm0, %xmm2
+vmovddup (%rax), %xmm2
+
+vmovddup %ymm0, %ymm2
+vmovddup (%rax), %ymm2
+
+vmovdqa %xmm0, %xmm2
+vmovdqa %xmm0, (%rax)
+vmovdqa (%rax), %xmm2
+
+vmovdqa %ymm0, %ymm2
+vmovdqa %ymm0, (%rax)
+vmovdqa (%rax), %ymm2
+
+vmovdqu %xmm0, %xmm2
+vmovdqu %xmm0, (%rax)
+vmovdqu (%rax), %xmm2
+
+vmovdqu %ymm0, %ymm2
+vmovdqu %ymm0, (%rax)
+vmovdqu (%rax), %ymm2
+
+vmovhlps %xmm0, %xmm1, %xmm2
+vmovlhps %xmm0, %xmm1, %xmm2
+
+vmovhpd %xmm0, (%rax)
+vmovhpd (%rax), %xmm1, %xmm2
+
+vmovhps %xmm0, (%rax)
+vmovhps (%rax), %xmm1, %xmm2
+
+vmovlpd %xmm0, (%rax)
+vmovlpd (%rax), %xmm1, %xmm2
+
+vmovlps %xmm0, (%rax)
+vmovlps (%rax), %xmm1, %xmm2
+
+vmovmskpd %xmm0, %rcx
+vmovmskpd %ymm0, %rcx
+
+vmovmskps %xmm0, %rcx
+vmovmskps %ymm0, %rcx
+
+vmovntdq %xmm0, (%rax)
+vmovntdq %ymm0, (%rax)
+
+vmovntdqa (%rax), %xmm2
+vmovntdqa (%rax), %ymm2
+
+vmovntpd %xmm0, (%rax)
+vmovntpd %ymm0, (%rax)
+
+vmovntps %xmm0, (%rax)
+vmovntps %ymm0, (%rax)
+
+vmovq %xmm0, %xmm2
+
+vmovq %rax, %xmm2
+vmovq (%rax), %xmm2
+
+vmovq %xmm0, %rcx
+vmovq %xmm0, (%rax)
+
+vmovsd %xmm0, %xmm1, %xmm2
+vmovsd %xmm0, (%rax)
+vmovsd (%rax), %xmm2
+
+vmovshdup %xmm0, %xmm2
+vmovshdup (%rax), %xmm2
+
+vmovshdup %ymm0, %ymm2
+vmovshdup (%rax), %ymm2
+
+vmovsldup %xmm0, %xmm2
+vmovsldup (%rax), %xmm2
+
+vmovsldup %ymm0, %ymm2
+vmovsldup (%rax), %ymm2
+
+vmovss %xmm0, %xmm1, %xmm2
+vmovss %xmm0, (%rax)
+vmovss (%rax), %xmm2
+
+vmovupd %xmm0, %xmm2
+vmovupd %xmm0, (%rax)
+vmovupd (%rax), %xmm2
+
+vmovupd %ymm0, %ymm2
+vmovupd %ymm0, (%rax)
+vmovupd (%rax), %ymm2
+
+vmovups %xmm0, %xmm2
+vmovups %xmm0, (%rax)
+vmovups (%rax), %xmm2
+
+vmovups %ymm0, %ymm2
+vmovups %ymm0, (%rax)
+vmovups (%rax), %ymm2
+
+vmpsadbw $1, %xmm0, %xmm1, %xmm2
+vmpsadbw $1, (%rax), %xmm1, %xmm2
+
+vmulpd %xmm0, %xmm1, %xmm2
+vmulpd (%rax), %xmm1, %xmm2
+
+vmulpd %ymm0, %ymm1, %ymm2
+vmulpd (%rax), %ymm1, %ymm2
+
+vmulps %xmm0, %xmm1, %xmm2
+vmulps (%rax), %xmm1, %xmm2
+
+vmulps %ymm0, %ymm1, %ymm2
+vmulps (%rax), %ymm1, %ymm2
+
+vmulsd %xmm0, %xmm1, %xmm2
+vmulsd (%rax), %xmm1, %xmm2
+
+vmulss %xmm0, %xmm1, %xmm2
+vmulss (%rax), %xmm1, %xmm2
+
+vorpd %xmm0, %xmm1, %xmm2
+vorpd (%rax), %xmm1, %xmm2
+
+vorpd %ymm0, %ymm1, %ymm2
+vorpd (%rax), %ymm1, %ymm2
+
+vorps %xmm0, %xmm1, %xmm2
+vorps (%rax), %xmm1, %xmm2
+
+vorps %ymm0, %ymm1, %ymm2
+vorps (%rax), %ymm1, %ymm2
+
+vpabsb %xmm0, %xmm2
+vpabsb (%rax), %xmm2
+
+vpabsd %xmm0, %xmm2
+vpabsd (%rax), %xmm2
+
+vpabsw %xmm0, %xmm2
+vpabsw (%rax), %xmm2
+
+vpackssdw %xmm0, %xmm1, %xmm2
+vpackssdw (%rax), %xmm1, %xmm2
+
+vpacksswb %xmm0, %xmm1, %xmm2
+vpacksswb (%rax), %xmm1, %xmm2
+
+vpackusdw %xmm0, %xmm1, %xmm2
+vpackusdw (%rax), %xmm1, %xmm2
+
+vpackuswb %xmm0, %xmm1, %xmm2
+vpackuswb (%rax), %xmm1, %xmm2
+
+vpaddb %xmm0, %xmm1, %xmm2
+vpaddb (%rax), %xmm1, %xmm2
+
+vpaddd %xmm0, %xmm1, %xmm2
+vpaddd (%rax), %xmm1, %xmm2
+
+vpaddq %xmm0, %xmm1, %xmm2
+vpaddq (%rax), %xmm1, %xmm2
+
+vpaddsb %xmm0, %xmm1, %xmm2
+vpaddsb (%rax), %xmm1, %xmm2
+
+vpaddsw %xmm0, %xmm1, %xmm2
+vpaddsw (%rax), %xmm1, %xmm2
+
+vpaddusb %xmm0, %xmm1, %xmm2
+vpaddusb (%rax), %xmm1, %xmm2
+
+vpaddusw %xmm0, %xmm1, %xmm2
+vpaddusw (%rax), %xmm1, %xmm2
+
+vpaddw %xmm0, %xmm1, %xmm2
+vpaddw (%rax), %xmm1, %xmm2
+
+vpalignr $1, %xmm0, %xmm1, %xmm2
+vpalignr $1, (%rax), %xmm1, %xmm2
+
+vpand %xmm0, %xmm1, %xmm2
+vpand (%rax), %xmm1, %xmm2
+
+vpandn %xmm0, %xmm1, %xmm2
+vpandn (%rax), %xmm1, %xmm2
+
+vpavgb %xmm0, %xmm1, %xmm2
+vpavgb (%rax), %xmm1, %xmm2
+
+vpavgw %xmm0, %xmm1, %xmm2
+vpavgw (%rax), %xmm1, %xmm2
+
+vpblendvb %xmm3, %xmm0, %xmm1, %xmm2
+vpblendvb %xmm3, (%rax), %xmm1, %xmm2
+
+vpblendw $11, %xmm0, %xmm1, %xmm2
+vpblendw $11, (%rax), %xmm1, %xmm2
+
+vpclmulqdq $11, %xmm0, %xmm1, %xmm2
+vpclmulqdq $11, (%rax), %xmm1, %xmm2
+
+vpcmpeqb %xmm0, %xmm1, %xmm2
+vpcmpeqb (%rax), %xmm1, %xmm2
+
+vpcmpeqd %xmm0, %xmm1, %xmm2
+vpcmpeqd (%rax), %xmm1, %xmm2
+
+vpcmpeqq %xmm0, %xmm1, %xmm2
+vpcmpeqq (%rax), %xmm1, %xmm2
+
+vpcmpeqw %xmm0, %xmm1, %xmm2
+vpcmpeqw (%rax), %xmm1, %xmm2
+
+vpcmpestri $1, %xmm0, %xmm2
+vpcmpestri $1, (%rax), %xmm2
+
+vpcmpestrm $1, %xmm0, %xmm2
+vpcmpestrm $1, (%rax), %xmm2
+
+vpcmpgtb %xmm0, %xmm1, %xmm2
+vpcmpgtb (%rax), %xmm1, %xmm2
+
+vpcmpgtd %xmm0, %xmm1, %xmm2
+vpcmpgtd (%rax), %xmm1, %xmm2
+
+vpcmpgtq %xmm0, %xmm1, %xmm2
+vpcmpgtq (%rax), %xmm1, %xmm2
+
+vpcmpgtw %xmm0, %xmm1, %xmm2
+vpcmpgtw (%rax), %xmm1, %xmm2
+
+vpcmpistri $1, %xmm0, %xmm2
+vpcmpistri $1, (%rax), %xmm2
+
+vpcmpistrm $1, %xmm0, %xmm2
+vpcmpistrm $1, (%rax), %xmm2
+
+vperm2f128 $1, %ymm0, %ymm1, %ymm2
+vperm2f128 $1, (%rax), %ymm1, %ymm2
+
+vpermilpd $1, %xmm0, %xmm2
+vpermilpd $1, (%rax), %xmm2
+vpermilpd %xmm0, %xmm1, %xmm2
+vpermilpd (%rax), %xmm1, %xmm2
+
+vpermilpd $1, %ymm0, %ymm2
+vpermilpd $1, (%rax), %ymm2
+vpermilpd %ymm0, %ymm1, %ymm2
+vpermilpd (%rax), %ymm1, %ymm2
+
+vpermilps $1, %xmm0, %xmm2
+vpermilps $1, (%rax), %xmm2
+vpermilps %xmm0, %xmm1, %xmm2
+vpermilps (%rax), %xmm1, %xmm2
+
+vpermilps $1, %ymm0, %ymm2
+vpermilps $1, (%rax), %ymm2
+vpermilps %ymm0, %ymm1, %ymm2
+vpermilps (%rax), %ymm1, %ymm2
+
+vpextrb $1, %xmm0, %ecx
+vpextrb $1, %xmm0, (%rax)
+
+vpextrd $1, %xmm0, %ecx
+vpextrd $1, %xmm0, (%rax)
+
+vpextrq $1, %xmm0, %rcx
+vpextrq $1, %xmm0, (%rax)
+
+vpextrw $1, %xmm0, %ecx
+vpextrw $1, %xmm0, (%rax)
+
+vphaddd %xmm0, %xmm1, %xmm2
+vphaddd (%rax), %xmm1, %xmm2
+
+vphaddsw %xmm0, %xmm1, %xmm2
+vphaddsw (%rax), %xmm1, %xmm2
+
+vphaddw %xmm0, %xmm1, %xmm2
+vphaddw (%rax), %xmm1, %xmm2
+
+vphminposuw %xmm0, %xmm2
+vphminposuw (%rax), %xmm2
+
+vphsubd %xmm0, %xmm1, %xmm2
+vphsubd (%rax), %xmm1, %xmm2
+
+vphsubsw %xmm0, %xmm1, %xmm2
+vphsubsw (%rax), %xmm1, %xmm2
+
+vphsubw %xmm0, %xmm1, %xmm2
+vphsubw (%rax), %xmm1, %xmm2
+
+vpinsrb $1, %eax, %xmm1, %xmm2
+vpinsrb $1, (%rax), %xmm1, %xmm2
+
+vpinsrd $1, %eax, %xmm1, %xmm2
+vpinsrd $1, (%rax), %xmm1, %xmm2
+
+vpinsrq $1, %rax, %xmm1, %xmm2
+vpinsrq $1, (%rax), %xmm1, %xmm2
+
+vpinsrw $1, %eax, %xmm1, %xmm2
+vpinsrw $1, (%rax), %xmm1, %xmm2
+
+vpmaddubsw %xmm0, %xmm1, %xmm2
+vpmaddubsw (%rax), %xmm1, %xmm2
+
+vpmaddwd %xmm0, %xmm1, %xmm2
+vpmaddwd (%rax), %xmm1, %xmm2
+
+vpmaxsb %xmm0, %xmm1, %xmm2
+vpmaxsb (%rax), %xmm1, %xmm2
+
+vpmaxsd %xmm0, %xmm1, %xmm2
+vpmaxsd (%rax), %xmm1, %xmm2
+
+vpmaxsw %xmm0, %xmm1, %xmm2
+vpmaxsw (%rax), %xmm1, %xmm2
+
+vpmaxub %xmm0, %xmm1, %xmm2
+vpmaxub (%rax), %xmm1, %xmm2
+
+vpmaxud %xmm0, %xmm1, %xmm2
+vpmaxud (%rax), %xmm1, %xmm2
+
+vpmaxuw %xmm0, %xmm1, %xmm2
+vpmaxuw (%rax), %xmm1, %xmm2
+
+vpminsb %xmm0, %xmm1, %xmm2
+vpminsb (%rax), %xmm1, %xmm2
+
+vpminsd %xmm0, %xmm1, %xmm2
+vpminsd (%rax), %xmm1, %xmm2
+
+vpminsw %xmm0, %xmm1, %xmm2
+vpminsw (%rax), %xmm1, %xmm2
+
+vpminub %xmm0, %xmm1, %xmm2
+vpminub (%rax), %xmm1, %xmm2
+
+vpminud %xmm0, %xmm1, %xmm2
+vpminud (%rax), %xmm1, %xmm2
+
+vpminuw %xmm0, %xmm1, %xmm2
+vpminuw (%rax), %xmm1, %xmm2
+
+vpmovmskb %xmm0, %rcx
+
+vpmovsxbd %xmm0, %xmm2
+vpmovsxbd (%rax), %xmm2
+
+vpmovsxbq %xmm0, %xmm2
+vpmovsxbq (%rax), %xmm2
+
+vpmovsxbw %xmm0, %xmm2
+vpmovsxbw (%rax), %xmm2
+
+vpmovsxdq %xmm0, %xmm2
+vpmovsxdq (%rax), %xmm2
+
+vpmovsxwd %xmm0, %xmm2
+vpmovsxwd (%rax), %xmm2
+
+vpmovsxwq %xmm0, %xmm2
+vpmovsxwq (%rax), %xmm2
+
+vpmovzxbd %xmm0, %xmm2
+vpmovzxbd (%rax), %xmm2
+
+vpmovzxbq %xmm0, %xmm2
+vpmovzxbq (%rax), %xmm2
+
+vpmovzxbw %xmm0, %xmm2
+vpmovzxbw (%rax), %xmm2
+
+vpmovzxdq %xmm0, %xmm2
+vpmovzxdq (%rax), %xmm2
+
+vpmovzxwd %xmm0, %xmm2
+vpmovzxwd (%rax), %xmm2
+
+vpmovzxwq %xmm0, %xmm2
+vpmovzxwq (%rax), %xmm2
+
+vpmuldq %xmm0, %xmm1, %xmm2
+vpmuldq (%rax), %xmm1, %xmm2
+
+vpmulhrsw %xmm0, %xmm1, %xmm2
+vpmulhrsw (%rax), %xmm1, %xmm2
+
+vpmulhuw %xmm0, %xmm1, %xmm2
+vpmulhuw (%rax), %xmm1, %xmm2
+
+vpmulhw %xmm0, %xmm1, %xmm2
+vpmulhw (%rax), %xmm1, %xmm2
+
+vpmulld %xmm0, %xmm1, %xmm2
+vpmulld (%rax), %xmm1, %xmm2
+
+vpmullw %xmm0, %xmm1, %xmm2
+vpmullw (%rax), %xmm1, %xmm2
+
+vpmuludq %xmm0, %xmm1, %xmm2
+vpmuludq (%rax), %xmm1, %xmm2
+
+vpor %xmm0, %xmm1, %xmm2
+vpor (%rax), %xmm1, %xmm2
+
+vpsadbw %xmm0, %xmm1, %xmm2
+vpsadbw (%rax), %xmm1, %xmm2
+
+vpshufb %xmm0, %xmm1, %xmm2
+vpshufb (%rax), %xmm1, %xmm2
+
+vpshufd $1, %xmm0, %xmm2
+vpshufd $1, (%rax), %xmm2
+
+vpshufhw $1, %xmm0, %xmm2
+vpshufhw $1, (%rax), %xmm2
+
+vpshuflw $1, %xmm0, %xmm2
+vpshuflw $1, (%rax), %xmm2
+
+vpsignb %xmm0, %xmm1, %xmm2
+vpsignb (%rax), %xmm1, %xmm2
+
+vpsignd %xmm0, %xmm1, %xmm2
+vpsignd (%rax), %xmm1, %xmm2
+
+vpsignw %xmm0, %xmm1, %xmm2
+vpsignw (%rax), %xmm1, %xmm2
+
+vpslld $1, %xmm0, %xmm2
+vpslld %xmm0, %xmm1, %xmm2
+vpslld (%rax), %xmm1, %xmm2
+
+vpslldq $1, %xmm1, %xmm2
+
+vpsllq $1, %xmm0, %xmm2
+vpsllq %xmm0, %xmm1, %xmm2
+vpsllq (%rax), %xmm1, %xmm2
+
+vpsllw $1, %xmm0, %xmm2
+vpsllw %xmm0, %xmm1, %xmm2
+vpsllw (%rax), %xmm1, %xmm2
+
+vpsrad $1, %xmm0, %xmm2
+vpsrad %xmm0, %xmm1, %xmm2
+vpsrad (%rax), %xmm1, %xmm2
+
+vpsraw $1, %xmm0, %xmm2
+vpsraw %xmm0, %xmm1, %xmm2
+vpsraw (%rax), %xmm1, %xmm2
+
+vpsrld $1, %xmm0, %xmm2
+vpsrld %xmm0, %xmm1, %xmm2
+vpsrld (%rax), %xmm1, %xmm2
+
+vpsrldq $1, %xmm1, %xmm2
+
+vpsrlq $1, %xmm0, %xmm2
+vpsrlq %xmm0, %xmm1, %xmm2
+vpsrlq (%rax), %xmm1, %xmm2
+
+vpsrlw $1, %xmm0, %xmm2
+vpsrlw %xmm0, %xmm1, %xmm2
+vpsrlw (%rax), %xmm1, %xmm2
+
+vpsubb %xmm0, %xmm1, %xmm2
+vpsubb (%rax), %xmm1, %xmm2
+
+vpsubd %xmm0, %xmm1, %xmm2
+vpsubd (%rax), %xmm1, %xmm2
+
+vpsubq %xmm0, %xmm1, %xmm2
+vpsubq (%rax), %xmm1, %xmm2
+
+vpsubsb %xmm0, %xmm1, %xmm2
+vpsubsb (%rax), %xmm1, %xmm2
+
+vpsubsw %xmm0, %xmm1, %xmm2
+vpsubsw (%rax), %xmm1, %xmm2
+
+vpsubusb %xmm0, %xmm1, %xmm2
+vpsubusb (%rax), %xmm1, %xmm2
+
+vpsubusw %xmm0, %xmm1, %xmm2
+vpsubusw (%rax), %xmm1, %xmm2
+
+vpsubw %xmm0, %xmm1, %xmm2
+vpsubw (%rax), %xmm1, %xmm2
+
+vptest %xmm0, %xmm1
+vptest (%rax), %xmm1
+
+vptest %ymm0, %ymm1
+vptest (%rax), %ymm1
+
+vpunpckhbw %xmm0, %xmm1, %xmm2
+vpunpckhbw (%rax), %xmm1, %xmm2
+
+vpunpckhdq %xmm0, %xmm1, %xmm2
+vpunpckhdq (%rax), %xmm1, %xmm2
+
+vpunpckhqdq %xmm0, %xmm1, %xmm2
+vpunpckhqdq (%rax), %xmm1, %xmm2
+
+vpunpckhwd %xmm0, %xmm1, %xmm2
+vpunpckhwd (%rax), %xmm1, %xmm2
+
+vpunpcklbw %xmm0, %xmm1, %xmm2
+vpunpcklbw (%rax), %xmm1, %xmm2
+
+vpunpckldq %xmm0, %xmm1, %xmm2
+vpunpckldq (%rax), %xmm1, %xmm2
+
+vpunpcklqdq %xmm0, %xmm1, %xmm2
+vpunpcklqdq (%rax), %xmm1, %xmm2
+
+vpunpcklwd %xmm0, %xmm1, %xmm2
+vpunpcklwd (%rax), %xmm1, %xmm2
+
+vpxor %xmm0, %xmm1, %xmm2
+vpxor (%rax), %xmm1, %xmm2
+
+vrcpps %xmm0, %xmm2
+vrcpps (%rax), %xmm2
+
+vrcpps %ymm0, %ymm2
+vrcpps (%rax), %ymm2
+
+vrcpss %xmm0, %xmm1, %xmm2
+vrcpss (%rax), %xmm1, %xmm2
+
+vroundpd $1, %xmm0, %xmm2
+vroundpd $1, (%rax), %xmm2
+
+vroundpd $1, %ymm0, %ymm2
+vroundpd $1, (%rax), %ymm2
+
+vroundps $1, %xmm0, %xmm2
+vroundps $1, (%rax), %xmm2
+
+vroundps $1, %ymm0, %ymm2
+vroundps $1, (%rax), %ymm2
+
+vroundsd $1, %xmm0, %xmm1, %xmm2
+vroundsd $1, (%rax), %xmm1, %xmm2
+
+vroundss $1, %xmm0, %xmm1, %xmm2
+vroundss $1, (%rax), %xmm1, %xmm2
+
+vrsqrtps %xmm0, %xmm2
+vrsqrtps (%rax), %xmm2
+
+vrsqrtps %ymm0, %ymm2
+vrsqrtps (%rax), %ymm2
+
+vrsqrtss %xmm0, %xmm1, %xmm2
+vrsqrtss (%rax), %xmm1, %xmm2
+
+vshufpd $1, %xmm0, %xmm1, %xmm2
+vshufpd $1, (%rax), %xmm1, %xmm2
+
+vshufpd $1, %ymm0, %ymm1, %ymm2
+vshufpd $1, (%rax), %ymm1, %ymm2
+
+vshufps $1, %xmm0, %xmm1, %xmm2
+vshufps $1, (%rax), %xmm1, %xmm2
+
+vshufps $1, %ymm0, %ymm1, %ymm2
+vshufps $1, (%rax), %ymm1, %ymm2
+
+vsqrtpd %xmm0, %xmm2
+vsqrtpd (%rax), %xmm2
+
+vsqrtpd %ymm0, %ymm2
+vsqrtpd (%rax), %ymm2
+
+vsqrtps %xmm0, %xmm2
+vsqrtps (%rax), %xmm2
+
+vsqrtps %ymm0, %ymm2
+vsqrtps (%rax), %ymm2
+
+vsqrtsd %xmm0, %xmm1, %xmm2
+vsqrtsd (%rax), %xmm1, %xmm2
+
+vsqrtss %xmm0, %xmm1, %xmm2
+vsqrtss (%rax), %xmm1, %xmm2
+
+vstmxcsr (%rax)
+
+vsubpd %xmm0, %xmm1, %xmm2
+vsubpd (%rax), %xmm1, %xmm2
+
+vsubpd %ymm0, %ymm1, %ymm2
+vsubpd (%rax), %ymm1, %ymm2
+
+vsubps %xmm0, %xmm1, %xmm2
+vsubps (%rax), %xmm1, %xmm2
+
+vsubps %ymm0, %ymm1, %ymm2
+vsubps (%rax), %ymm1, %ymm2
+
+vsubsd %xmm0, %xmm1, %xmm2
+vsubsd (%rax), %xmm1, %xmm2
+
+vsubss %xmm0, %xmm1, %xmm2
+vsubss (%rax), %xmm1, %xmm2
+
+vtestpd %xmm0, %xmm1
+vtestpd (%rax), %xmm1
+
+vtestpd %ymm0, %ymm1
+vtestpd (%rax), %ymm1
+
+vtestps %xmm0, %xmm1
+vtestps (%rax), %xmm1
+
+vtestps %ymm0, %ymm1
+vtestps (%rax), %ymm1
+
+vucomisd %xmm0, %xmm1
+vucomisd (%rax), %xmm1
+
+vucomiss %xmm0, %xmm1
+vucomiss (%rax), %xmm1
+
+vunpckhpd %xmm0, %xmm1, %xmm2
+vunpckhpd (%rax), %xmm1, %xmm2
+
+vunpckhpd %ymm0, %ymm1, %ymm2
+vunpckhpd (%rax), %ymm1, %ymm2
+
+vunpckhps %xmm0, %xmm1, %xmm2
+vunpckhps (%rax), %xmm1, %xmm2
+
+vunpckhps %ymm0, %ymm1, %ymm2
+vunpckhps (%rax), %ymm1, %ymm2
+
+vunpcklpd %xmm0, %xmm1, %xmm2
+vunpcklpd (%rax), %xmm1, %xmm2
+
+vunpcklpd %ymm0, %ymm1, %ymm2
+vunpcklpd (%rax), %ymm1, %ymm2
+
+vunpcklps %xmm0, %xmm1, %xmm2
+vunpcklps (%rax), %xmm1, %xmm2
+
+vunpcklps %ymm0, %ymm1, %ymm2
+vunpcklps (%rax), %ymm1, %ymm2
+
+vxorpd %xmm0, %xmm1, %xmm2
+vxorpd (%rax), %xmm1, %xmm2
+
+vxorpd %ymm0, %ymm1, %ymm2
+vxorpd (%rax), %ymm1, %ymm2
+
+vxorps %xmm0, %xmm1, %xmm2
+vxorps (%rax), %xmm1, %xmm2
+
+vxorps %ymm0, %ymm1, %ymm2
+vxorps (%rax), %ymm1, %ymm2
+
+vzeroall
+vzeroupper
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 vaddpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vaddpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaddpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vaddpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vaddps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vaddps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaddps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vaddps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vaddsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vaddsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaddss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vaddss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaddsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vaddsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaddsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vaddsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vaddsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vaddsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaddsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vaddsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vaesdec %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vaesdec (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vaesdeclast %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vaesdeclast (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vaesenc %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vaesenc (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vaesenclast %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vaesenclast (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vaesimc %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vaesimc (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 vaeskeygenassist $22, %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vaeskeygenassist $22, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 vandnpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vandnpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vandnpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vandnpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vandnps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vandnps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vandnps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vandnps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vandpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vandpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vandpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vandpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vandps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vandps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vandps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vandps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vblendpd $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vblendpd $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vblendpd $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vblendpd $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vblendps $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vblendps $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vblendps $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vblendps $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vblendvpd %xmm3, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vblendvpd %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vblendvpd %ymm3, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vblendvpd %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vblendvps %xmm3, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vblendvps %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vblendvps %ymm3, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vblendvps %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vbroadcastf128 (%rax), %ymm2
+# CHECK-NEXT: 1 8 0.50 * vbroadcastsd (%rax), %ymm2
+# CHECK-NEXT: 1 8 0.50 * vbroadcastss (%rax), %xmm2
+# CHECK-NEXT: 1 8 0.50 * vbroadcastss (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vcmpeqpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vcmpeqpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vcmpeqpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vcmpeqpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vcmpeqps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vcmpeqps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vcmpeqps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vcmpeqps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vcmpeqsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vcmpeqsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vcmpeqss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vcmpeqss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 1.00 vcomisd %xmm0, %xmm1
+# CHECK-NEXT: 1 12 1.00 * vcomisd (%rax), %xmm1
+# CHECK-NEXT: 1 5 1.00 vcomiss %xmm0, %xmm1
+# CHECK-NEXT: 1 12 1.00 * vcomiss (%rax), %xmm1
+# CHECK-NEXT: 2 7 2.00 vcvtdq2pd %xmm0, %xmm2
+# CHECK-NEXT: 2 14 2.00 * vcvtdq2pd (%rax), %xmm2
+# CHECK-NEXT: 2 9 2.00 vcvtdq2pd %xmm0, %ymm2
+# CHECK-NEXT: 2 16 2.00 * vcvtdq2pd (%rax), %ymm2
+# CHECK-NEXT: 1 4 1.00 vcvtdq2ps %xmm0, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vcvtdq2ps (%rax), %xmm2
+# CHECK-NEXT: 1 4 1.00 vcvtdq2ps %ymm0, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vcvtdq2ps (%rax), %ymm2
+# CHECK-NEXT: 2 7 2.00 vcvtpd2dq %xmm0, %xmm2
+# CHECK-NEXT: 2 14 2.00 * vcvtpd2dqx (%rax), %xmm2
+# CHECK-NEXT: 2 9 2.00 vcvtpd2dq %ymm0, %xmm2
+# CHECK-NEXT: 2 16 2.00 * vcvtpd2dqy (%rax), %xmm2
+# CHECK-NEXT: 2 3 1.00 vcvtpd2ps %xmm0, %xmm2
+# CHECK-NEXT: 2 10 1.00 * vcvtpd2psx (%rax), %xmm2
+# CHECK-NEXT: 2 3 1.00 vcvtpd2ps %ymm0, %xmm2
+# CHECK-NEXT: 2 10 1.00 * vcvtpd2psy (%rax), %xmm2
+# CHECK-NEXT: 2 4 1.00 vcvtps2dq %xmm0, %xmm2
+# CHECK-NEXT: 2 11 1.00 * vcvtps2dq (%rax), %xmm2
+# CHECK-NEXT: 2 4 1.00 vcvtps2dq %ymm0, %ymm2
+# CHECK-NEXT: 2 11 1.00 * vcvtps2dq (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vcvtps2pd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vcvtps2pd (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 vcvtps2pd %xmm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vcvtps2pd (%rax), %ymm2
+# CHECK-NEXT: 2 2 3.00 vcvtsd2si %xmm0, %ecx
+# CHECK-NEXT: 2 2 3.00 vcvtsd2si %xmm0, %rcx
+# CHECK-NEXT: 2 9 3.00 * vcvtsd2si (%rax), %ecx
+# CHECK-NEXT: 2 9 3.00 * vcvtsd2si (%rax), %rcx
+# CHECK-NEXT: 1 4 1.00 vcvtsd2ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vcvtsd2ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 4 2.00 vcvtsi2sd %ecx, %xmm0, %xmm2
+# CHECK-NEXT: 2 4 2.00 vcvtsi2sd %rcx, %xmm0, %xmm2
+# CHECK-NEXT: 2 11 2.00 * vcvtsi2sdl (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 11 2.00 * vcvtsi2sdq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 4 1.00 vcvtsi2ss %ecx, %xmm0, %xmm2
+# CHECK-NEXT: 2 4 1.00 vcvtsi2ss %rcx, %xmm0, %xmm2
+# CHECK-NEXT: 2 11 1.00 * vcvtsi2ssl (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 11 1.00 * vcvtsi2ssq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 1 4 1.00 vcvtss2sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vcvtss2sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 2 2.00 vcvtss2si %xmm0, %ecx
+# CHECK-NEXT: 2 2 2.00 vcvtss2si %xmm0, %rcx
+# CHECK-NEXT: 2 9 2.00 * vcvtss2si (%rax), %ecx
+# CHECK-NEXT: 2 9 2.00 * vcvtss2si (%rax), %rcx
+# CHECK-NEXT: 2 7 2.00 vcvttpd2dq %xmm0, %xmm2
+# CHECK-NEXT: 2 14 2.00 * vcvttpd2dqx (%rax), %xmm2
+# CHECK-NEXT: 2 9 2.00 vcvttpd2dq %ymm0, %xmm2
+# CHECK-NEXT: 2 16 2.00 * vcvttpd2dqy (%rax), %xmm2
+# CHECK-NEXT: 2 4 1.00 vcvttps2dq %xmm0, %xmm2
+# CHECK-NEXT: 2 11 1.00 * vcvttps2dq (%rax), %xmm2
+# CHECK-NEXT: 2 4 1.00 vcvttps2dq %ymm0, %ymm2
+# CHECK-NEXT: 2 11 1.00 * vcvttps2dq (%rax), %ymm2
+# CHECK-NEXT: 2 2 2.00 vcvttsd2si %xmm0, %ecx
+# CHECK-NEXT: 2 2 2.00 vcvttsd2si %xmm0, %rcx
+# CHECK-NEXT: 2 9 2.00 * vcvttsd2si (%rax), %ecx
+# CHECK-NEXT: 2 9 2.00 * vcvttsd2si (%rax), %rcx
+# CHECK-NEXT: 2 2 2.00 vcvttss2si %xmm0, %ecx
+# CHECK-NEXT: 2 2 2.00 vcvttss2si %xmm0, %rcx
+# CHECK-NEXT: 2 9 2.00 * vcvttss2si (%rax), %ecx
+# CHECK-NEXT: 2 9 2.00 * vcvttss2si (%rax), %rcx
+# CHECK-NEXT: 1 8 6.00 vdivpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 15 6.00 * vdivpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 8 6.00 vdivpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 15 6.00 * vdivpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 10 5.00 vdivps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 17 5.00 * vdivps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 10 5.00 vdivps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 17 5.00 * vdivps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 8 6.00 vdivsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 15 6.00 * vdivsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 10 5.00 vdivss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 17 5.00 * vdivss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 10 8.00 vdppd $22, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 17 8.00 * vdppd $22, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 100 0.25 vdpps $22, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 100 0.25 * vdpps $22, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 100 0.25 vdpps $22, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 100 0.25 * vdpps $22, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 1.00 vextractf128 $1, %ymm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * vextractf128 $1, %ymm0, (%rax)
+# CHECK-NEXT: 2 2 2.00 vextractps $1, %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 * vextractps $1, %xmm0, (%rax)
+# CHECK-NEXT: 4 7 4.00 vhaddpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 7 14 4.00 * vhaddpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 7 4.00 vhaddpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 7 14 4.00 * vhaddpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 4 7 4.00 vhaddps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 7 14 4.00 * vhaddps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 7 4.00 vhaddps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 7 14 4.00 * vhaddps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 4 7 4.00 vhsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 7 14 4.00 * vhsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 7 4.00 vhsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 7 14 4.00 * vhsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 4 7 4.00 vhsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 7 14 4.00 * vhsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 7 4.00 vhsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 7 14 4.00 * vhsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 1.00 vinsertf128 $1, %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 1.00 * vinsertf128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vinsertps $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vinsertps $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vlddqu (%rax), %xmm2
+# CHECK-NEXT: 1 8 0.50 * vlddqu (%rax), %ymm2
+# CHECK-NEXT: 1 100 0.25 * * U vldmxcsr (%rax)
+# CHECK-NEXT: 1 1 0.33 * * U vmaskmovdqu %xmm0, %xmm1
+# CHECK-NEXT: 1 8 0.50 * vmaskmovpd (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vmaskmovpd (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 1 1 0.50 * * vmaskmovpd %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 1 1 0.50 * * vmaskmovpd %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmaskmovps (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vmaskmovps (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 1 1 0.50 * * vmaskmovps %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 1 1 0.50 * * vmaskmovps %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: 1 1 0.50 vmaxpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vmaxpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vmaxpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vmaxpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vmaxps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vmaxps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vmaxps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vmaxps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vmaxsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vmaxsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vmaxss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vmaxss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vminpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vminpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vminpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vminpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vminps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vminps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vminps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vminps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vminsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vminsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vminss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vminss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 0 0.25 vmovapd %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * vmovapd %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovapd (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 vmovapd %ymm0, %ymm2
+# CHECK-NEXT: 1 1 0.33 * vmovapd %ymm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovapd (%rax), %ymm2
+# CHECK-NEXT: 1 0 0.25 vmovaps %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * vmovaps %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovaps (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 vmovaps %ymm0, %ymm2
+# CHECK-NEXT: 1 1 0.33 * vmovaps %ymm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovaps (%rax), %ymm2
+# CHECK-NEXT: 1 1 1.00 vmovd %eax, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vmovd (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 vmovd %xmm0, %ecx
+# CHECK-NEXT: 1 1 0.33 * vmovd %xmm0, (%rax)
+# CHECK-NEXT: 1 1 0.50 vmovddup %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vmovddup (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vmovddup %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vmovddup (%rax), %ymm2
+# CHECK-NEXT: 1 0 0.25 vmovdqa %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * vmovdqa %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovdqa (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 vmovdqa %ymm0, %ymm2
+# CHECK-NEXT: 1 1 0.33 * vmovdqa %ymm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovdqa (%rax), %ymm2
+# CHECK-NEXT: 1 0 0.25 vmovdqu %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * vmovdqu %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovdqu (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 vmovdqu %ymm0, %ymm2
+# CHECK-NEXT: 1 1 0.33 * vmovdqu %ymm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovdqu (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vmovhlps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vmovlhps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 * vmovhpd %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovhpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 * vmovhps %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovhps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 * vmovlpd %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovlpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 * vmovlps %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovlps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 1.00 vmovmskpd %xmm0, %ecx
+# CHECK-NEXT: 1 1 1.00 vmovmskpd %ymm0, %ecx
+# CHECK-NEXT: 1 1 1.00 vmovmskps %xmm0, %ecx
+# CHECK-NEXT: 1 1 1.00 vmovmskps %ymm0, %ecx
+# CHECK-NEXT: 1 5 1.00 * vmovntdq %xmm0, (%rax)
+# CHECK-NEXT: 1 5 1.00 * vmovntdq %ymm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovntdqa (%rax), %xmm2
+# CHECK-NEXT: 1 8 0.50 * vmovntdqa (%rax), %ymm2
+# CHECK-NEXT: 1 5 1.00 * vmovntpd %xmm0, (%rax)
+# CHECK-NEXT: 1 5 1.00 * vmovntpd %ymm0, (%rax)
+# CHECK-NEXT: 1 5 1.00 * vmovntps %xmm0, (%rax)
+# CHECK-NEXT: 1 5 1.00 * vmovntps %ymm0, (%rax)
+# CHECK-NEXT: 1 1 0.25 vmovq %xmm0, %xmm2
+# CHECK-NEXT: 1 1 1.00 vmovq %rax, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vmovq (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 vmovq %xmm0, %rcx
+# CHECK-NEXT: 1 1 0.33 * vmovq %xmm0, (%rax)
+# CHECK-NEXT: 1 1 0.50 vmovsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 * vmovsd %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vmovshdup %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vmovshdup (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vmovshdup %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vmovshdup (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vmovsldup %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vmovsldup (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vmovsldup %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vmovsldup (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vmovss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 * vmovss %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovss (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 vmovupd %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * vmovupd %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovupd (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 vmovupd %ymm0, %ymm2
+# CHECK-NEXT: 1 1 0.33 * vmovupd %ymm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovupd (%rax), %ymm2
+# CHECK-NEXT: 1 0 0.25 vmovups %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * vmovups %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovups (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 vmovups %ymm0, %ymm2
+# CHECK-NEXT: 1 1 0.33 * vmovups %ymm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovups (%rax), %ymm2
+# CHECK-NEXT: 1 4 2.00 vmpsadbw $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 2.00 * vmpsadbw $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vmulpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vmulpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vmulpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vmulpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vmulps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vmulps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vmulps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vmulps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vmulsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vmulsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vmulss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vmulss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vorpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vorpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vorpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vorpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vorps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vorps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vorps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vorps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpabsb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpabsb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 vpabsd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpabsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 vpabsw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpabsw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpackssdw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpackssdw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpacksswb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpacksswb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpackusdw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpackusdw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpackuswb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpackuswb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpaddb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpaddb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpaddd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpaddd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpaddq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpaddq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpaddsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpaddsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpaddsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpaddsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpaddusb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpaddusb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpaddusw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpaddusw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpaddw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpaddw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpalignr $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpalignr $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpand %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpand (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpandn %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpandn (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpavgb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpavgb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpavgw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpavgw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 1.00 vpblendvb %xmm3, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 1.00 * vpblendvb %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpblendw $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpblendw $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.00 vpclmulqdq $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 1.00 * vpclmulqdq $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpcmpeqb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpcmpeqb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpcmpeqd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpcmpeqd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpcmpeqq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpcmpeqq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpcmpeqw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpcmpeqw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 8 2 3.25 vpcmpestri $1, %xmm0, %xmm2
+# CHECK-NEXT: 8 9 3.25 * vpcmpestri $1, (%rax), %xmm2
+# CHECK-NEXT: 8 8 6.25 vpcmpestrm $1, %xmm0, %xmm2
+# CHECK-NEXT: 8 15 6.25 * vpcmpestrm $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 vpcmpgtb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpcmpgtb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpcmpgtd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpcmpgtd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpcmpgtq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpcmpgtq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpcmpgtw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpcmpgtw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 1 2.00 vpcmpistri $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 8 2.00 * vpcmpistri $1, (%rax), %xmm2
+# CHECK-NEXT: 3 7 6.25 vpcmpistrm $1, %xmm0, %xmm2
+# CHECK-NEXT: 3 14 6.25 * vpcmpistrm $1, (%rax), %xmm2
+# CHECK-NEXT: 3 7 0.50 vperm2f128 $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 3 14 0.50 * vperm2f128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpermilpd $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpermilpd $1, (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 vpermilpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vpermilpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpermilpd $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpermilpd $1, (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpermilpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpermilpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpermilps $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpermilps $1, (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 vpermilps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vpermilps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpermilps $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpermilps $1, (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpermilps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpermilps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 2 2.00 vpextrb $1, %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 * vpextrb $1, %xmm0, (%rax)
+# CHECK-NEXT: 2 2 2.00 vpextrd $1, %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 * vpextrd $1, %xmm0, (%rax)
+# CHECK-NEXT: 2 2 2.00 vpextrq $1, %xmm0, %rcx
+# CHECK-NEXT: 2 2 1.00 * vpextrq $1, %xmm0, (%rax)
+# CHECK-NEXT: 2 2 2.00 vpextrw $1, %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 * vpextrw $1, %xmm0, (%rax)
+# CHECK-NEXT: 4 3 4.00 vphaddd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 7 10 4.00 * vphaddd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 3 4.00 vphaddsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 7 10 4.00 * vphaddsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 3 4.00 vphaddw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 7 10 4.00 * vphaddw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.00 vphminposuw %xmm0, %xmm2
+# CHECK-NEXT: 1 10 1.00 * vphminposuw (%rax), %xmm2
+# CHECK-NEXT: 4 3 4.00 vphsubd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 7 10 4.00 * vphsubd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 3 4.00 vphsubsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 7 10 4.00 * vphsubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 3 4.00 vphsubw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 7 10 4.00 * vphsubw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 2 0.50 vpinsrb $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT: 1 9 0.50 * vpinsrb $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 2 0.50 vpinsrd $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT: 1 9 0.50 * vpinsrd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 2 0.50 vpinsrq $1, %rax, %xmm1, %xmm2
+# CHECK-NEXT: 1 9 0.50 * vpinsrq $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 2 0.50 vpinsrw $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT: 1 9 0.50 * vpinsrw $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vpmaddubsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vpmaddubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.00 vpmaddwd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 1.00 * vpmaddwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpmaxsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmaxsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpmaxsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmaxsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpmaxsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmaxsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpmaxub %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmaxub (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpmaxud %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmaxud (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpmaxuw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmaxuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpminsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpminsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpminsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpminsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpminsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpminsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpminub %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpminub (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpminud %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpminud (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpminuw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpminuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 1.00 vpmovmskb %xmm0, %ecx
+# CHECK-NEXT: 1 1 0.50 vpmovsxbd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovsxbd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovsxbq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovsxbq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovsxbw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovsxbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovsxdq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovsxdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovsxwd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovsxwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovsxwq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovsxwq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovzxbd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovzxbd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovzxbq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovzxbq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovzxbw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovzxbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovzxdq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovzxdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovzxwd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovzxwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovzxwq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovzxwq (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 vpmuldq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 1.00 * vpmuldq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vpmulhrsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 1.00 * vpmulhrsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.00 vpmulhuw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 1.00 * vpmulhuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.00 vpmulhw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 1.00 * vpmulhw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vpmulld %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 2.00 * vpmulld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.00 vpmullw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 1.00 * vpmullw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.00 vpmuludq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 1.00 * vpmuludq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpor %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpor (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.00 vpsadbw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 1.00 * vpsadbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpshufb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpshufb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpshufd $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpshufd $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpshufhw $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpshufhw $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpshuflw $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpshuflw $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 vpsignb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsignb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpsignd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsignd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpsignw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsignw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 1.00 vpslld $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 1 1.00 vpslld %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 1.00 * vpslld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpslldq $1, %xmm1, %xmm2
+# CHECK-NEXT: 1 1 1.00 vpsllq $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 1 1.00 vpsllq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 1.00 * vpsllq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 1.00 vpsllw $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 1 1.00 vpsllw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 1.00 * vpsllw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 1.00 vpsrad $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 1 1.00 vpsrad %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 1.00 * vpsrad (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 1.00 vpsraw $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 1 1.00 vpsraw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 1.00 * vpsraw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 1.00 vpsrld $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 1 1.00 vpsrld %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 1.00 * vpsrld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrldq $1, %xmm1, %xmm2
+# CHECK-NEXT: 1 1 1.00 vpsrlq $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 1 1.00 vpsrlq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 1.00 * vpsrlq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 1.00 vpsrlw $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 1 1.00 vpsrlw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 1.00 * vpsrlw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpsubb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsubb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpsubd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsubd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpsubq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsubq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpsubsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsubsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpsubsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpsubusb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsubusb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpsubusw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsubusw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpsubw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsubw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vptest %xmm0, %xmm1
+# CHECK-NEXT: 8 11 2.00 * vptest (%rax), %xmm1
+# CHECK-NEXT: 1 8 2.00 vptest %ymm0, %ymm1
+# CHECK-NEXT: 8 15 2.00 * vptest (%rax), %ymm1
+# CHECK-NEXT: 1 1 0.50 vpunpckhbw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpunpckhbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhdq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpunpckhdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhqdq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpunpckhqdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhwd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpunpckhwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpcklbw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpunpcklbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpckldq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpunpckldq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpcklqdq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpunpcklqdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpcklwd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpunpcklwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpxor %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpxor (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vrcpps %xmm0, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vrcpps (%rax), %xmm2
+# CHECK-NEXT: 1 5 0.50 vrcpps %ymm0, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vrcpps (%rax), %ymm2
+# CHECK-NEXT: 1 5 0.50 vrcpss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vrcpss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vroundpd $1, %xmm0, %xmm2
+# CHECK-NEXT: 8 11 1.00 * vroundpd $1, (%rax), %xmm2
+# CHECK-NEXT: 1 4 1.00 vroundpd $1, %ymm0, %ymm2
+# CHECK-NEXT: 8 11 1.00 * vroundpd $1, (%rax), %ymm2
+# CHECK-NEXT: 1 4 1.00 vroundps $1, %xmm0, %xmm2
+# CHECK-NEXT: 8 11 1.00 * vroundps $1, (%rax), %xmm2
+# CHECK-NEXT: 1 4 1.00 vroundps $1, %ymm0, %ymm2
+# CHECK-NEXT: 8 11 1.00 * vroundps $1, (%rax), %ymm2
+# CHECK-NEXT: 1 4 1.00 vroundsd $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 8 11 1.00 * vroundsd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 1.00 vroundss $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 8 11 1.00 * vroundss $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vrsqrtps %xmm0, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vrsqrtps (%rax), %xmm2
+# CHECK-NEXT: 1 5 0.50 vrsqrtps %ymm0, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vrsqrtps (%rax), %ymm2
+# CHECK-NEXT: 1 5 0.50 vrsqrtss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vrsqrtss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vshufpd $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vshufpd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vshufpd $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vshufpd $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vshufps $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vshufps $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vshufps $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vshufps $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 8 10.00 vsqrtpd %xmm0, %xmm2
+# CHECK-NEXT: 1 15 10.00 * vsqrtpd (%rax), %xmm2
+# CHECK-NEXT: 1 8 10.00 vsqrtpd %ymm0, %ymm2
+# CHECK-NEXT: 1 15 10.00 * vsqrtpd (%rax), %ymm2
+# CHECK-NEXT: 1 8 7.00 vsqrtps %xmm0, %xmm2
+# CHECK-NEXT: 1 15 7.00 * vsqrtps (%rax), %xmm2
+# CHECK-NEXT: 1 8 7.00 vsqrtps %ymm0, %ymm2
+# CHECK-NEXT: 1 15 7.00 * vsqrtps (%rax), %ymm2
+# CHECK-NEXT: 1 8 10.00 vsqrtsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 15 10.00 * vsqrtsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 8 7.00 vsqrtss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 15 7.00 * vsqrtss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 100 0.25 * U vstmxcsr (%rax)
+# CHECK-NEXT: 1 3 0.50 vsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vsubsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vsubsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vsubss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vsubss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 2.00 vtestpd %xmm0, %xmm1
+# CHECK-NEXT: 8 11 2.00 * vtestpd (%rax), %xmm1
+# CHECK-NEXT: 1 8 2.00 vtestpd %ymm0, %ymm1
+# CHECK-NEXT: 8 15 2.00 * vtestpd (%rax), %ymm1
+# CHECK-NEXT: 1 4 2.00 vtestps %xmm0, %xmm1
+# CHECK-NEXT: 8 11 2.00 * vtestps (%rax), %xmm1
+# CHECK-NEXT: 1 8 2.00 vtestps %ymm0, %ymm1
+# CHECK-NEXT: 8 15 2.00 * vtestps (%rax), %ymm1
+# CHECK-NEXT: 1 5 1.00 vucomisd %xmm0, %xmm1
+# CHECK-NEXT: 1 12 1.00 * vucomisd (%rax), %xmm1
+# CHECK-NEXT: 1 5 1.00 vucomiss %xmm0, %xmm1
+# CHECK-NEXT: 1 12 1.00 * vucomiss (%rax), %xmm1
+# CHECK-NEXT: 1 1 0.50 vunpckhpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vunpckhpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vunpckhpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vunpckhpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vunpckhps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vunpckhps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vunpckhps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vunpckhps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vunpcklpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vunpcklpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vunpcklpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vunpcklpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vunpcklps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vunpcklps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vunpcklps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vunpcklps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vxorpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vxorpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vxorpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vxorpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vxorps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vxorps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vxorps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vxorps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 100 0.25 U vzeroall
+# CHECK-NEXT: 1 100 0.25 U vzeroupper
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: 118.33 118.33 118.33 - - 8.00 - 232.25 663.25 124.25 212.25 118.00 118.00 118.00 156.00 156.00 14.00 14.00 14.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - vaddpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - vaddpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - vaddpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - vaddpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - vaddps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - vaddps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - vaddps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - vaddps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - vaddsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - vaddsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - vaddss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - vaddss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - vaddsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - vaddsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - vaddsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - vaddsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - vaddsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - vaddsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - vaddsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - vaddsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - vaesdec %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 0.50 0.33 0.33 0.33 0.50 0.50 - - - vaesdec (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - vaesdeclast %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 0.50 0.33 0.33 0.33 0.50 0.50 - - - vaesdeclast (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - vaesenc %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 0.50 0.33 0.33 0.33 0.50 0.50 - - - vaesenc (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - vaesenclast %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 0.50 0.33 0.33 0.33 0.50 0.50 - - - vaesenclast (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - vaesimc %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 0.50 0.33 0.33 0.33 0.50 0.50 - - - vaesimc (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - - - - - vaeskeygenassist $22, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 0.50 0.33 0.33 0.33 0.50 0.50 - - - vaeskeygenassist $22, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vandnpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vandnpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vandnpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vandnpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vandnps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vandnps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vandnps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vandnps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vandpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vandpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vandpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vandpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vandps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vandps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vandps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vandps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vblendpd $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vblendpd $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vblendpd $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vblendpd $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vblendps $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vblendps $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vblendps $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vblendps $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vblendvpd %xmm3, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vblendvpd %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vblendvpd %ymm3, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vblendvpd %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vblendvps %xmm3, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vblendvps %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vblendvps %ymm3, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vblendvps %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vbroadcastf128 (%rax), %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vbroadcastsd (%rax), %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vbroadcastss (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vbroadcastss (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vcmpeqpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vcmpeqpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vcmpeqpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vcmpeqpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vcmpeqps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vcmpeqps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vcmpeqps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vcmpeqps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vcmpeqsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vcmpeqsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vcmpeqss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vcmpeqss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 1.00 0.50 - - - - - - - - - vcomisd %xmm0, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 1.00 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vcomisd (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - 0.50 1.00 0.50 - - - - - - - - - vcomiss %xmm0, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 1.00 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vcomiss (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - 0.50 2.50 - - - - - - - - - - vcvtdq2pd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 2.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vcvtdq2pd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 2.50 - - - - - - - - - - vcvtdq2pd %xmm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 2.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vcvtdq2pd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vcvtdq2ps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vcvtdq2ps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vcvtdq2ps %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vcvtdq2ps (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 2.50 - - - - - - - - - - vcvtpd2dq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 2.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vcvtpd2dqx (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 2.50 - - - - - - - - - - vcvtpd2dq %ymm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 2.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vcvtpd2dqy (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.50 - 0.50 - - - - - - - - vcvtpd2ps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - vcvtpd2psx (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.50 - 0.50 - - - - - - - - vcvtpd2ps %ymm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - vcvtpd2psy (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vcvtps2dq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vcvtps2dq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vcvtps2dq %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vcvtps2dq (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - vcvtps2pd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - vcvtps2pd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - vcvtps2pd %xmm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - vcvtps2pd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 3.00 - - - - - - - - - - vcvtsd2si %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - 3.00 - - - - - - - - - - vcvtsd2si %xmm0, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vcvtsd2si (%rax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vcvtsd2si (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vcvtsd2ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vcvtsd2ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - 2.00 - - - - - - - - - - vcvtsi2sd %ecx, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - 2.00 - - - - - - - - - - vcvtsi2sd %rcx, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - 1.00 - - 2.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vcvtsi2sdl (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - 1.00 - - 2.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vcvtsi2sdq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - 1.00 - - - - - - - - - - vcvtsi2ss %ecx, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - 1.00 - - - - - - - - - - vcvtsi2ss %rcx, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - 1.00 - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vcvtsi2ssl (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - 1.00 - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vcvtsi2ssq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vcvtss2sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vcvtss2sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - vcvtss2si %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - vcvtss2si %xmm0, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vcvtss2si (%rax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vcvtss2si (%rax), %rcx
+# CHECK-NEXT: - - - - - - - 0.50 2.50 - - - - - - - - - - vcvttpd2dq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 2.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vcvttpd2dqx (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 2.50 - - - - - - - - - - vcvttpd2dq %ymm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 2.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vcvttpd2dqy (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vcvttps2dq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vcvttps2dq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vcvttps2dq %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vcvttps2dq (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - vcvttsd2si %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - vcvttsd2si %xmm0, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vcvttsd2si (%rax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vcvttsd2si (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - vcvttss2si %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - vcvttss2si %xmm0, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vcvttss2si (%rax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vcvttss2si (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - 6.00 - - - - - - - - - - vdivpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 6.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vdivpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 6.00 - - - - - - - - - - vdivpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 6.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vdivpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 5.00 - - - - - - - - - - vdivps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 5.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vdivps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 5.00 - - - - - - - - - - vdivps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 5.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vdivps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 6.00 - - - - - - - - - - vdivsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 6.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vdivsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 5.00 - - - - - - - - - - vdivss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 5.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vdivss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 8.00 - - - - - - - - - - vdppd $22, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vdppd $22, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vdpps $22, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vdpps $22, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vdpps $22, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vdpps $22, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - vextractf128 $1, %ymm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vextractf128 $1, %ymm0, (%rax)
+# CHECK-NEXT: - - - - - - - 0.50 2.50 - - - - - - - - - - vextractps $1, %xmm0, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 1.50 - - 0.67 0.67 0.67 - - 0.67 0.67 0.67 vextractps $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - vhaddpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - vhaddpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - vhaddpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - vhaddpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - vhaddps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - vhaddps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - vhaddps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - vhaddps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - vhsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - vhsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - vhsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - vhsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - vhsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - vhsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - vhsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - vhsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - vinsertf128 $1, %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vinsertf128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vinsertps $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vinsertps $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vlddqu (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vlddqu (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vldmxcsr (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vmaskmovdqu %xmm0, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vmaskmovpd (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vmaskmovpd (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vmaskmovpd %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vmaskmovpd %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vmaskmovps (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vmaskmovps (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vmaskmovps %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vmaskmovps %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vmaxpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vmaxpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vmaxpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vmaxpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vmaxps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vmaxps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vmaxps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vmaxps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vmaxsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vmaxsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vmaxss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vmaxss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vminpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vminpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vminpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vminpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vminps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vminps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vminps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vminps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vminsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vminsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vminss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vminss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vmovapd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vmovapd %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vmovapd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vmovapd %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vmovapd %ymm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vmovapd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vmovaps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vmovaps %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vmovaps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vmovaps %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vmovaps %ymm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vmovaps (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vmovd %eax, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vmovd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vmovd %xmm0, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vmovd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vmovddup %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vmovddup (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vmovddup %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vmovddup (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vmovdqa %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vmovdqa %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vmovdqa (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vmovdqa %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vmovdqa %ymm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vmovdqa (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vmovdqu %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vmovdqu %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vmovdqu (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vmovdqu %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vmovdqu %ymm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vmovdqu (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vmovhlps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vmovlhps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vmovhpd %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vmovhpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vmovhps %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vmovhps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vmovlpd %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vmovlpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vmovlps %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vmovlps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vmovmskpd %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vmovmskpd %ymm0, %ecx
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vmovmskps %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vmovmskps %ymm0, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vmovntdq %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vmovntdq %ymm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vmovntdqa (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vmovntdqa (%rax), %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vmovntpd %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vmovntpd %ymm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vmovntps %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vmovntps %ymm0, (%rax)
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vmovq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vmovq %rax, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vmovq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vmovq %xmm0, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vmovq %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vmovsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vmovsd %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vmovsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vmovshdup %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vmovshdup (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vmovshdup %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vmovshdup (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vmovsldup %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vmovsldup (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vmovsldup %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vmovsldup (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vmovss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vmovss %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vmovss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vmovupd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vmovupd %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vmovupd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vmovupd %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vmovupd %ymm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vmovupd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vmovups %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vmovups %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vmovups (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vmovups %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vmovups %ymm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vmovups (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - 2.00 2.00 2.00 2.00 - - - - - - - - vmpsadbw $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 2.00 2.00 2.00 2.00 0.33 0.33 0.33 0.50 0.50 - - - vmpsadbw $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vmulpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vmulpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vmulpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vmulpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vmulps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vmulps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vmulps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vmulps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vmulsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vmulsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vmulss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vmulss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vorpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vorpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vorpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vorpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vorps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vorps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vorps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vorps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpabsb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpabsb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpabsd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpabsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpabsw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpabsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpackssdw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpackssdw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpacksswb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpacksswb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpackusdw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpackusdw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpackuswb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpackuswb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpaddb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpaddb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpaddd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpaddd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpaddq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpaddq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpaddsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpaddsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpaddsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpaddsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpaddusb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpaddusb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpaddusw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpaddusw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpaddw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpaddw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpalignr $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpalignr $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpand %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpand (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpandn %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpandn (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpavgb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpavgb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpavgw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpavgw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - vpblendvb %xmm3, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpblendvb %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpblendw $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpblendw $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - vpclmulqdq $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - 1.00 0.33 0.33 0.33 0.50 0.50 - - - vpclmulqdq $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpcmpeqb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpcmpeqb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpcmpeqd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpcmpeqd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpcmpeqq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpcmpeqq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpcmpeqw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpcmpeqw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 3.25 3.25 3.25 3.25 - - - - - - - - vpcmpestri $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 3.25 3.25 3.25 3.25 0.33 0.33 0.33 0.50 0.50 - - - vpcmpestri $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 6.25 6.25 6.25 6.25 - - - - - - - - vpcmpestrm $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 6.25 6.25 6.25 6.25 0.33 0.33 0.33 0.50 0.50 - - - vpcmpestrm $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpcmpgtb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpcmpgtb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpcmpgtd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpcmpgtd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpcmpgtq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpcmpgtq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpcmpgtw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpcmpgtw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 2.00 2.00 2.00 2.00 - - - - - - - - vpcmpistri $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 2.00 2.00 2.00 2.00 0.33 0.33 0.33 0.50 0.50 - - - vpcmpistri $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 6.25 6.25 6.25 6.25 - - - - - - - - vpcmpistrm $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 6.25 6.25 6.25 6.25 0.33 0.33 0.33 0.50 0.50 - - - vpcmpistrm $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vperm2f128 $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vperm2f128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpermilpd $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpermilpd $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpermilpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpermilpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpermilpd $1, %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpermilpd $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpermilpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpermilpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpermilps $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpermilps $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpermilps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpermilps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpermilps $1, %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpermilps $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpermilps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpermilps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 2.50 - - - - - - - - - - vpextrb $1, %xmm0, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 1.50 - - 0.67 0.67 0.67 - - 0.67 0.67 0.67 vpextrb $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - 0.50 2.50 - - - - - - - - - - vpextrd $1, %xmm0, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 1.50 - - 0.67 0.67 0.67 - - 0.67 0.67 0.67 vpextrd $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - 0.50 2.50 - - - - - - - - - - vpextrq $1, %xmm0, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 1.50 - - 0.67 0.67 0.67 - - 0.67 0.67 0.67 vpextrq $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - 0.50 2.50 - - - - - - - - - - vpextrw $1, %xmm0, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 1.50 - - 0.67 0.67 0.67 - - 0.67 0.67 0.67 vpextrw $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - vphaddd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - vphaddd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - vphaddsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - vphaddsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - vphaddw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - vphaddw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - vphminposuw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vphminposuw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - vphsubd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - vphsubd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - vphsubsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - vphsubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - vphsubw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - vphsubw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpinsrb $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpinsrb $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpinsrd $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpinsrd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpinsrq $1, %rax, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpinsrq $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpinsrw $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpinsrw $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - vpmaddubsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpmaddubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - vpmaddwd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpmaddwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpmaxsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpmaxsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpmaxsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpmaxsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpmaxsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpmaxsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpmaxub %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpmaxub (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpmaxud %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpmaxud (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpmaxuw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpmaxuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpminsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpminsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpminsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpminsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpminsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpminsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpminub %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpminub (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpminud %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpminud (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpminuw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpminuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpmovmskb %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpmovsxbd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpmovsxbd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpmovsxbq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpmovsxbq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpmovsxbw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpmovsxbw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpmovsxdq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpmovsxdq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpmovsxwd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpmovsxwd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpmovsxwq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpmovsxwq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpmovzxbd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpmovzxbd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpmovzxbq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpmovzxbq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpmovzxbw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpmovzxbw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpmovzxdq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpmovzxdq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpmovzxwd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpmovzxwd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpmovzxwq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpmovzxwq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - vpmuldq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpmuldq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - vpmulhrsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpmulhrsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - vpmulhuw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpmulhuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - vpmulhw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpmulhw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 2.00 - - - - - - - - - - - vpmulld %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 2.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpmulld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - vpmullw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpmullw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - vpmuludq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpmuludq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpor %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpor (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - vpsadbw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpsadbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpshufb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpshufb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpshufd $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpshufd $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpshufhw $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpshufhw $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpshuflw $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpshuflw $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpsignb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpsignb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpsignd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpsignd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpsignw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpsignw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpslld $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpslld %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vpslld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpslldq $1, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpsllq $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpsllq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vpsllq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpsllw $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpsllw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vpsllw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpsrad $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpsrad %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vpsrad (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpsraw $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpsraw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vpsraw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpsrld $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpsrld %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vpsrld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpsrldq $1, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpsrlq $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpsrlq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vpsrlq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpsrlw $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpsrlw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vpsrlw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpsubb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpsubb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpsubd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpsubd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpsubq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpsubq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpsubsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpsubsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpsubsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpsubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpsubusb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpsubusb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpsubusw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpsubusw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpsubw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpsubw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 2.50 - - - - - - - - - - vptest %xmm0, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 2.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vptest (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - 0.50 2.50 - - - - - - - - - - vptest %ymm0, %ymm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 2.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vptest (%rax), %ymm1
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpunpckhbw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpunpckhbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpunpckhdq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpunpckhdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpunpckhqdq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpunpckhqdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpunpckhwd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpunpckhwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpunpcklbw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpunpcklbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpunpckldq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpunpckldq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpunpcklqdq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpunpcklqdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpunpcklwd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpunpcklwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpxor %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpxor (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vrcpps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vrcpps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vrcpps %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vrcpps (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vrcpss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vrcpss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vroundpd $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - - - - - - - - - vroundpd $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vroundpd $1, %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - - - - - - - - - vroundpd $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vroundps $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - - - - - - - - - vroundps $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vroundps $1, %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - - - - - - - - - vroundps $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vroundsd $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - - - - - - - - - vroundsd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vroundss $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - - - - - - - - - vroundss $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vrsqrtps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vrsqrtps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vrsqrtps %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vrsqrtps (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vrsqrtss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vrsqrtss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vshufpd $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vshufpd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vshufpd $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vshufpd $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vshufps $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vshufps $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vshufps $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vshufps $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 10.00 - - - - - - - - - - vsqrtpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 10.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vsqrtpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 10.00 - - - - - - - - - - vsqrtpd %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 10.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vsqrtpd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 7.00 - - - - - - - - - - vsqrtps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 7.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vsqrtps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 7.00 - - - - - - - - - - vsqrtps %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 7.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vsqrtps (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 10.00 - - - - - - - - - - vsqrtsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 10.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vsqrtsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 7.00 - - - - - - - - - - vsqrtss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 7.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vsqrtss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vstmxcsr (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - vsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - vsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - vsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - vsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - vsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - vsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - vsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - vsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - vsubsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - vsubsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - vsubss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - vsubss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 2.50 - - - - - - - - - - vtestpd %xmm0, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 2.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vtestpd (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - 0.50 2.50 - - - - - - - - - - vtestpd %ymm0, %ymm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 2.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vtestpd (%rax), %ymm1
+# CHECK-NEXT: - - - - - - - 0.50 2.50 - - - - - - - - - - vtestps %xmm0, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 2.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vtestps (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - 0.50 2.50 - - - - - - - - - - vtestps %ymm0, %ymm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 2.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vtestps (%rax), %ymm1
+# CHECK-NEXT: - - - - - - - 0.50 1.00 0.50 - - - - - - - - - vucomisd %xmm0, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 1.00 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vucomisd (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - 0.50 1.00 0.50 - - - - - - - - - vucomiss %xmm0, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 1.00 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vucomiss (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vunpckhpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vunpckhpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vunpckhpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vunpckhpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vunpckhps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vunpckhps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vunpckhps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vunpckhps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vunpcklpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vunpcklpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vunpcklpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vunpcklpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vunpcklps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vunpcklps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vunpcklps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vunpcklps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vxorpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vxorpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vxorpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vxorpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vxorps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vxorps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vxorps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vxorps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vzeroall
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vzeroupper
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-avx2.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-avx2.s
new file mode 100644
index 0000000000000..bf21daa91aa1d
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-avx2.s
@@ -0,0 +1,1092 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+vbroadcasti128 (%rax), %ymm0
+
+vbroadcastsd %xmm0, %ymm0
+vbroadcastss %xmm0, %ymm0
+
+vextracti128 $1, %ymm0, %xmm2
+vextracti128 $1, %ymm0, (%rax)
+
+vgatherdpd %xmm0, (%rax,%xmm1,2), %xmm2
+vgatherdpd %ymm0, (%rax,%xmm1,2), %ymm2
+
+vgatherdps %xmm0, (%rax,%xmm1,2), %xmm2
+vgatherdps %ymm0, (%rax,%ymm1,2), %ymm2
+
+vgatherqpd %xmm0, (%rax,%xmm1,2), %xmm2
+vgatherqpd %ymm0, (%rax,%ymm1,2), %ymm2
+
+vgatherqps %xmm0, (%rax,%xmm1,2), %xmm2
+vgatherqps %xmm0, (%rax,%ymm1,2), %xmm2
+
+vinserti128 $1, %xmm0, %ymm1, %ymm2
+vinserti128 $1, (%rax), %ymm1, %ymm2
+
+vmovntdqa (%rax), %ymm0
+
+vmpsadbw $1, %ymm0, %ymm1, %ymm2
+vmpsadbw $1, (%rax), %ymm1, %ymm2
+
+vpabsb %ymm0, %ymm2
+vpabsb (%rax), %ymm2
+
+vpabsd %ymm0, %ymm2
+vpabsd (%rax), %ymm2
+
+vpabsw %ymm0, %ymm2
+vpabsw (%rax), %ymm2
+
+vpackssdw %ymm0, %ymm1, %ymm2
+vpackssdw (%rax), %ymm1, %ymm2
+
+vpacksswb %ymm0, %ymm1, %ymm2
+vpacksswb (%rax), %ymm1, %ymm2
+
+vpackusdw %ymm0, %ymm1, %ymm2
+vpackusdw (%rax), %ymm1, %ymm2
+
+vpackuswb %ymm0, %ymm1, %ymm2
+vpackuswb (%rax), %ymm1, %ymm2
+
+vpaddb %ymm0, %ymm1, %ymm2
+vpaddb (%rax), %ymm1, %ymm2
+
+vpaddd %ymm0, %ymm1, %ymm2
+vpaddd (%rax), %ymm1, %ymm2
+
+vpaddq %ymm0, %ymm1, %ymm2
+vpaddq (%rax), %ymm1, %ymm2
+
+vpaddsb %ymm0, %ymm1, %ymm2
+vpaddsb (%rax), %ymm1, %ymm2
+
+vpaddsw %ymm0, %ymm1, %ymm2
+vpaddsw (%rax), %ymm1, %ymm2
+
+vpaddusb %ymm0, %ymm1, %ymm2
+vpaddusb (%rax), %ymm1, %ymm2
+
+vpaddusw %ymm0, %ymm1, %ymm2
+vpaddusw (%rax), %ymm1, %ymm2
+
+vpaddw %ymm0, %ymm1, %ymm2
+vpaddw (%rax), %ymm1, %ymm2
+
+vpalignr $1, %ymm0, %ymm1, %ymm2
+vpalignr $1, (%rax), %ymm1, %ymm2
+
+vpand %ymm0, %ymm1, %ymm2
+vpand (%rax), %ymm1, %ymm2
+
+vpandn %ymm0, %ymm1, %ymm2
+vpandn (%rax), %ymm1, %ymm2
+
+vpavgb %ymm0, %ymm1, %ymm2
+vpavgb (%rax), %ymm1, %ymm2
+
+vpavgw %ymm0, %ymm1, %ymm2
+vpavgw (%rax), %ymm1, %ymm2
+
+vpblendd $11, %xmm0, %xmm1, %xmm2
+vpblendd $11, (%rax), %xmm1, %xmm2
+
+vpblendd $11, %ymm0, %ymm1, %ymm2
+vpblendd $11, (%rax), %ymm1, %ymm2
+
+vpblendvb %ymm3, %ymm0, %ymm1, %ymm2
+vpblendvb %ymm3, (%rax), %ymm1, %ymm2
+
+vpblendw $11, %ymm0, %ymm1, %ymm2
+vpblendw $11, (%rax), %ymm1, %ymm2
+
+vpbroadcastb %xmm0, %xmm0
+vpbroadcastb (%rax), %xmm0
+
+vpbroadcastb %xmm0, %ymm0
+vpbroadcastb (%rax), %ymm0
+
+vpbroadcastd %xmm0, %xmm0
+vpbroadcastd (%rax), %xmm0
+
+vpbroadcastd %xmm0, %ymm0
+vpbroadcastd (%rax), %ymm0
+
+vpbroadcastq %xmm0, %xmm0
+vpbroadcastq (%rax), %xmm0
+
+vpbroadcastq %xmm0, %ymm0
+vpbroadcastq (%rax), %ymm0
+
+vpbroadcastw %xmm0, %xmm0
+vpbroadcastw (%rax), %xmm0
+
+vpbroadcastw %xmm0, %ymm0
+vpbroadcastw (%rax), %ymm0
+
+vpcmpeqb %ymm0, %ymm1, %ymm2
+vpcmpeqb (%rax), %ymm1, %ymm2
+
+vpcmpeqd %ymm0, %ymm1, %ymm2
+vpcmpeqd (%rax), %ymm1, %ymm2
+
+vpcmpeqq %ymm0, %ymm1, %ymm2
+vpcmpeqq (%rax), %ymm1, %ymm2
+
+vpcmpeqw %ymm0, %ymm1, %ymm2
+vpcmpeqw (%rax), %ymm1, %ymm2
+
+vpcmpgtb %ymm0, %ymm1, %ymm2
+vpcmpgtb (%rax), %ymm1, %ymm2
+
+vpcmpgtd %ymm0, %ymm1, %ymm2
+vpcmpgtd (%rax), %ymm1, %ymm2
+
+vpcmpgtq %ymm0, %ymm1, %ymm2
+vpcmpgtq (%rax), %ymm1, %ymm2
+
+vpcmpgtw %ymm0, %ymm1, %ymm2
+vpcmpgtw (%rax), %ymm1, %ymm2
+
+vperm2i128 $1, %ymm0, %ymm1, %ymm2
+vperm2i128 $1, (%rax), %ymm1, %ymm2
+
+vpermd %ymm0, %ymm1, %ymm2
+vpermd (%rax), %ymm1, %ymm2
+
+vpermpd $1, %ymm0, %ymm2
+vpermpd $1, (%rax), %ymm2
+
+vpermps %ymm0, %ymm1, %ymm2
+vpermps (%rax), %ymm1, %ymm2
+
+vpermq $1, %ymm0, %ymm2
+vpermq $1, (%rax), %ymm2
+
+vpgatherdd %xmm0, (%rax,%xmm1,2), %xmm2
+vpgatherdd %ymm0, (%rax,%ymm1,2), %ymm2
+
+vpgatherdq %xmm0, (%rax,%xmm1,2), %xmm2
+vpgatherdq %ymm0, (%rax,%xmm1,2), %ymm2
+
+vpgatherqd %xmm0, (%rax,%xmm1,2), %xmm2
+vpgatherqd %xmm0, (%rax,%ymm1,2), %xmm2
+
+vpgatherqq %xmm0, (%rax,%xmm1,2), %xmm2
+vpgatherqq %ymm0, (%rax,%ymm1,2), %ymm2
+
+vphaddd %ymm0, %ymm1, %ymm2
+vphaddd (%rax), %ymm1, %ymm2
+
+vphaddsw %ymm0, %ymm1, %ymm2
+vphaddsw (%rax), %ymm1, %ymm2
+
+vphaddw %ymm0, %ymm1, %ymm2
+vphaddw (%rax), %ymm1, %ymm2
+
+vphsubd %ymm0, %ymm1, %ymm2
+vphsubd (%rax), %ymm1, %ymm2
+
+vphsubsw %ymm0, %ymm1, %ymm2
+vphsubsw (%rax), %ymm1, %ymm2
+
+vphsubw %ymm0, %ymm1, %ymm2
+vphsubw (%rax), %ymm1, %ymm2
+
+vpmaddubsw %ymm0, %ymm1, %ymm2
+vpmaddubsw (%rax), %ymm1, %ymm2
+
+vpmaddwd %ymm0, %ymm1, %ymm2
+vpmaddwd (%rax), %ymm1, %ymm2
+
+vpmaskmovd (%rax), %xmm0, %xmm2
+vpmaskmovd (%rax), %ymm0, %ymm2
+
+vpmaskmovd %xmm0, %xmm1, (%rax)
+vpmaskmovd %ymm0, %ymm1, (%rax)
+
+vpmaskmovq (%rax), %xmm0, %xmm2
+vpmaskmovq (%rax), %ymm0, %ymm2
+
+vpmaskmovq %xmm0, %xmm1, (%rax)
+vpmaskmovq %ymm0, %ymm1, (%rax)
+
+vpmaxsb %ymm0, %ymm1, %ymm2
+vpmaxsb (%rax), %ymm1, %ymm2
+
+vpmaxsd %ymm0, %ymm1, %ymm2
+vpmaxsd (%rax), %ymm1, %ymm2
+
+vpmaxsw %ymm0, %ymm1, %ymm2
+vpmaxsw (%rax), %ymm1, %ymm2
+
+vpmaxub %ymm0, %ymm1, %ymm2
+vpmaxub (%rax), %ymm1, %ymm2
+
+vpmaxud %ymm0, %ymm1, %ymm2
+vpmaxud (%rax), %ymm1, %ymm2
+
+vpmaxuw %ymm0, %ymm1, %ymm2
+vpmaxuw (%rax), %ymm1, %ymm2
+
+vpminsb %ymm0, %ymm1, %ymm2
+vpminsb (%rax), %ymm1, %ymm2
+
+vpminsd %ymm0, %ymm1, %ymm2
+vpminsd (%rax), %ymm1, %ymm2
+
+vpminsw %ymm0, %ymm1, %ymm2
+vpminsw (%rax), %ymm1, %ymm2
+
+vpminub %ymm0, %ymm1, %ymm2
+vpminub (%rax), %ymm1, %ymm2
+
+vpminud %ymm0, %ymm1, %ymm2
+vpminud (%rax), %ymm1, %ymm2
+
+vpminuw %ymm0, %ymm1, %ymm2
+vpminuw (%rax), %ymm1, %ymm2
+
+vpmovmskb %ymm0, %rcx
+
+vpmovsxbd %xmm0, %ymm2
+vpmovsxbd (%rax), %ymm2
+
+vpmovsxbq %xmm0, %ymm2
+vpmovsxbq (%rax), %ymm2
+
+vpmovsxbw %xmm0, %ymm2
+vpmovsxbw (%rax), %ymm2
+
+vpmovsxdq %xmm0, %ymm2
+vpmovsxdq (%rax), %ymm2
+
+vpmovsxwd %xmm0, %ymm2
+vpmovsxwd (%rax), %ymm2
+
+vpmovsxwq %xmm0, %ymm2
+vpmovsxwq (%rax), %ymm2
+
+vpmovzxbd %xmm0, %ymm2
+vpmovzxbd (%rax), %ymm2
+
+vpmovzxbq %xmm0, %ymm2
+vpmovzxbq (%rax), %ymm2
+
+vpmovzxbw %xmm0, %ymm2
+vpmovzxbw (%rax), %ymm2
+
+vpmovzxdq %xmm0, %ymm2
+vpmovzxdq (%rax), %ymm2
+
+vpmovzxwd %xmm0, %ymm2
+vpmovzxwd (%rax), %ymm2
+
+vpmovzxwq %xmm0, %ymm2
+vpmovzxwq (%rax), %ymm2
+
+vpmuldq %ymm0, %ymm1, %ymm2
+vpmuldq (%rax), %ymm1, %ymm2
+
+vpmulhrsw %ymm0, %ymm1, %ymm2
+vpmulhrsw (%rax), %ymm1, %ymm2
+
+vpmulhuw %ymm0, %ymm1, %ymm2
+vpmulhuw (%rax), %ymm1, %ymm2
+
+vpmulhw %ymm0, %ymm1, %ymm2
+vpmulhw (%rax), %ymm1, %ymm2
+
+vpmulld %ymm0, %ymm1, %ymm2
+vpmulld (%rax), %ymm1, %ymm2
+
+vpmullw %ymm0, %ymm1, %ymm2
+vpmullw (%rax), %ymm1, %ymm2
+
+vpmuludq %ymm0, %ymm1, %ymm2
+vpmuludq (%rax), %ymm1, %ymm2
+
+vpor %ymm0, %ymm1, %ymm2
+vpor (%rax), %ymm1, %ymm2
+
+vpsadbw %ymm0, %ymm1, %ymm2
+vpsadbw (%rax), %ymm1, %ymm2
+
+vpshufb %ymm0, %ymm1, %ymm2
+vpshufb (%rax), %ymm1, %ymm2
+
+vpshufd $1, %ymm0, %ymm2
+vpshufd $1, (%rax), %ymm2
+
+vpshufhw $1, %ymm0, %ymm2
+vpshufhw $1, (%rax), %ymm2
+
+vpshuflw $1, %ymm0, %ymm2
+vpshuflw $1, (%rax), %ymm2
+
+vpsignb %ymm0, %ymm1, %ymm2
+vpsignb (%rax), %ymm1, %ymm2
+
+vpsignd %ymm0, %ymm1, %ymm2
+vpsignd (%rax), %ymm1, %ymm2
+
+vpsignw %ymm0, %ymm1, %ymm2
+vpsignw (%rax), %ymm1, %ymm2
+
+vpslld $1, %ymm0, %ymm2
+vpslld %xmm0, %ymm1, %ymm2
+vpslld (%rax), %ymm1, %ymm2
+
+vpslldq $1, %ymm1, %ymm2
+
+vpsllq $1, %ymm0, %ymm2
+vpsllq %xmm0, %ymm1, %ymm2
+vpsllq (%rax), %ymm1, %ymm2
+
+vpsllvd %xmm0, %xmm1, %xmm2
+vpsllvd (%rax), %xmm1, %xmm2
+
+vpsllvd %ymm0, %ymm1, %ymm2
+vpsllvd (%rax), %ymm1, %ymm2
+
+vpsllvq %xmm0, %xmm1, %xmm2
+vpsllvq (%rax), %xmm1, %xmm2
+
+vpsllvq %ymm0, %ymm1, %ymm2
+vpsllvq (%rax), %ymm1, %ymm2
+
+vpsllw $1, %ymm0, %ymm2
+vpsllw %xmm0, %ymm1, %ymm2
+vpsllw (%rax), %ymm1, %ymm2
+
+vpsrad $1, %ymm0, %ymm2
+vpsrad %xmm0, %ymm1, %ymm2
+vpsrad (%rax), %ymm1, %ymm2
+
+vpsravd %xmm0, %xmm1, %xmm2
+vpsravd (%rax), %xmm1, %xmm2
+
+vpsravd %ymm0, %ymm1, %ymm2
+vpsravd (%rax), %ymm1, %ymm2
+
+vpsraw $1, %ymm0, %ymm2
+vpsraw %xmm0, %ymm1, %ymm2
+vpsraw (%rax), %ymm1, %ymm2
+
+vpsrld $1, %ymm0, %ymm2
+vpsrld %xmm0, %ymm1, %ymm2
+vpsrld (%rax), %ymm1, %ymm2
+
+vpsrldq $1, %ymm1, %ymm2
+
+vpsrlq $1, %ymm0, %ymm2
+vpsrlq %xmm0, %ymm1, %ymm2
+vpsrlq (%rax), %ymm1, %ymm2
+
+vpsrlvd %xmm0, %xmm1, %xmm2
+vpsrlvd (%rax), %xmm1, %xmm2
+
+vpsrlvd %ymm0, %ymm1, %ymm2
+vpsrlvd (%rax), %ymm1, %ymm2
+
+vpsrlvq %xmm0, %xmm1, %xmm2
+vpsrlvq (%rax), %xmm1, %xmm2
+
+vpsrlvq %ymm0, %ymm1, %ymm2
+vpsrlvq (%rax), %ymm1, %ymm2
+
+vpsrlw $1, %ymm0, %ymm2
+vpsrlw %xmm0, %ymm1, %ymm2
+vpsrlw (%rax), %ymm1, %ymm2
+
+vpsubb %ymm0, %ymm1, %ymm2
+vpsubb (%rax), %ymm1, %ymm2
+
+vpsubd %ymm0, %ymm1, %ymm2
+vpsubd (%rax), %ymm1, %ymm2
+
+vpsubq %ymm0, %ymm1, %ymm2
+vpsubq (%rax), %ymm1, %ymm2
+
+vpsubsb %ymm0, %ymm1, %ymm2
+vpsubsb (%rax), %ymm1, %ymm2
+
+vpsubsw %ymm0, %ymm1, %ymm2
+vpsubsw (%rax), %ymm1, %ymm2
+
+vpsubusb %ymm0, %ymm1, %ymm2
+vpsubusb (%rax), %ymm1, %ymm2
+
+vpsubusw %ymm0, %ymm1, %ymm2
+vpsubusw (%rax), %ymm1, %ymm2
+
+vpsubw %ymm0, %ymm1, %ymm2
+vpsubw (%rax), %ymm1, %ymm2
+
+vpunpckhbw %ymm0, %ymm1, %ymm2
+vpunpckhbw (%rax), %ymm1, %ymm2
+
+vpunpckhdq %ymm0, %ymm1, %ymm2
+vpunpckhdq (%rax), %ymm1, %ymm2
+
+vpunpckhqdq %ymm0, %ymm1, %ymm2
+vpunpckhqdq (%rax), %ymm1, %ymm2
+
+vpunpckhwd %ymm0, %ymm1, %ymm2
+vpunpckhwd (%rax), %ymm1, %ymm2
+
+vpunpcklbw %ymm0, %ymm1, %ymm2
+vpunpcklbw (%rax), %ymm1, %ymm2
+
+vpunpckldq %ymm0, %ymm1, %ymm2
+vpunpckldq (%rax), %ymm1, %ymm2
+
+vpunpcklqdq %ymm0, %ymm1, %ymm2
+vpunpcklqdq (%rax), %ymm1, %ymm2
+
+vpunpcklwd %ymm0, %ymm1, %ymm2
+vpunpcklwd (%rax), %ymm1, %ymm2
+
+vpxor %ymm0, %ymm1, %ymm2
+vpxor (%rax), %ymm1, %ymm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 8 0.50 * vbroadcasti128 (%rax), %ymm0
+# CHECK-NEXT: 1 3 1.00 vbroadcastsd %xmm0, %ymm0
+# CHECK-NEXT: 1 3 1.00 vbroadcastss %xmm0, %ymm0
+# CHECK-NEXT: 1 3 0.50 vextracti128 $1, %ymm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * vextracti128 $1, %ymm0, (%rax)
+# CHECK-NEXT: 2 8 0.50 * vgatherdpd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 2 8 0.50 * vgatherdpd %ymm0, (%rax,%xmm1,2), %ymm2
+# CHECK-NEXT: 2 8 0.50 * vgatherdps %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 2 8 0.50 * vgatherdps %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 2 8 0.50 * vgatherqpd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 2 8 0.50 * vgatherqpd %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 2 8 0.50 * vgatherqps %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 2 8 0.50 * vgatherqps %xmm0, (%rax,%ymm1,2), %xmm2
+# CHECK-NEXT: 1 3 0.50 vinserti128 $1, %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vinserti128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vmovntdqa (%rax), %ymm0
+# CHECK-NEXT: 1 4 2.00 vmpsadbw $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.00 * vmpsadbw $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpabsb %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpabsb (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.25 vpabsd %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpabsd (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.25 vpabsw %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpabsw (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vpackssdw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpackssdw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpacksswb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpacksswb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpackusdw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpackusdw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpackuswb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpackuswb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpaddb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpaddb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpaddd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpaddd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpaddq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpaddq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpaddsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpaddsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpaddsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpaddsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpaddusb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpaddusb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpaddusw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpaddusw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpaddw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpaddw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpalignr $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpalignr $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpand %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpand (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpandn %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpandn (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpavgb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpavgb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpavgw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpavgw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpblendd $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpblendd $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpblendd $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpblendd $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 1.00 vpblendvb %ymm3, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 1.00 * vpblendvb %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpblendw $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpblendw $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpbroadcastb %xmm0, %xmm0
+# CHECK-NEXT: 1 8 0.50 * vpbroadcastb (%rax), %xmm0
+# CHECK-NEXT: 1 3 0.50 vpbroadcastb %xmm0, %ymm0
+# CHECK-NEXT: 1 8 0.50 * vpbroadcastb (%rax), %ymm0
+# CHECK-NEXT: 1 1 0.50 vpbroadcastd %xmm0, %xmm0
+# CHECK-NEXT: 1 8 0.50 * vpbroadcastd (%rax), %xmm0
+# CHECK-NEXT: 1 3 0.50 vpbroadcastd %xmm0, %ymm0
+# CHECK-NEXT: 1 8 0.50 * vpbroadcastd (%rax), %ymm0
+# CHECK-NEXT: 1 1 0.50 vpbroadcastq %xmm0, %xmm0
+# CHECK-NEXT: 1 8 0.50 * vpbroadcastq (%rax), %xmm0
+# CHECK-NEXT: 1 3 0.50 vpbroadcastq %xmm0, %ymm0
+# CHECK-NEXT: 1 8 0.50 * vpbroadcastq (%rax), %ymm0
+# CHECK-NEXT: 1 1 0.50 vpbroadcastw %xmm0, %xmm0
+# CHECK-NEXT: 1 8 0.50 * vpbroadcastw (%rax), %xmm0
+# CHECK-NEXT: 1 3 0.50 vpbroadcastw %xmm0, %ymm0
+# CHECK-NEXT: 1 8 0.50 * vpbroadcastw (%rax), %ymm0
+# CHECK-NEXT: 1 1 0.25 vpcmpeqb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpcmpeqb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpcmpeqd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpcmpeqd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpcmpeqq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpcmpeqq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpcmpeqw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpcmpeqw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpcmpgtb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpcmpgtb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpcmpgtd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpcmpgtd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpcmpgtq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpcmpgtq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpcmpgtw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpcmpgtw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 3 7 0.50 vperm2i128 $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 3 14 0.50 * vperm2i128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 3 3 1.00 vpermd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 1.00 * vpermd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 1.00 vpermpd $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 10 1.00 * vpermpd $1, (%rax), %ymm2
+# CHECK-NEXT: 1 3 1.00 vpermps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 1.00 * vpermps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vpermq $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpermq $1, (%rax), %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpgatherdd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpgatherdd %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpgatherdq %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpgatherdq %ymm0, (%rax,%xmm1,2), %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpgatherqd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpgatherqd %xmm0, (%rax,%ymm1,2), %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpgatherqq %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 2 8 0.50 * vpgatherqq %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 4 3 4.00 vphaddd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 7 10 4.00 * vphaddd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 4 3 4.00 vphaddsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 7 10 4.00 * vphaddsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 4 3 4.00 vphaddw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 7 10 4.00 * vphaddw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 4 3 4.00 vphsubd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 7 10 4.00 * vphsubd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 4 3 4.00 vphsubsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 7 10 4.00 * vphsubsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 4 3 4.00 vphsubw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 7 10 4.00 * vphsubw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vpmaddubsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vpmaddubsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 1.00 vpmaddwd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 1.00 * vpmaddwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 8 1.00 * vpmaskmovd (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 1 8 1.00 * vpmaskmovd (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 1 2 0.50 * * vpmaskmovd %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 1 2 0.50 * * vpmaskmovd %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: 1 8 1.00 * vpmaskmovq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 1 8 1.00 * vpmaskmovq (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 1 2 0.50 * * vpmaskmovq %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 1 2 0.50 * * vpmaskmovq %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: 1 1 0.25 vpmaxsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpmaxsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpmaxsd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpmaxsd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpmaxsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpmaxsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpmaxub %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpmaxub (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpmaxud %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpmaxud (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpmaxuw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpmaxuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpminsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpminsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpminsd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpminsd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpminsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpminsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpminub %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpminub (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpminud %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpminud (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpminuw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpminuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 1.00 vpmovmskb %ymm0, %ecx
+# CHECK-NEXT: 1 3 0.50 vpmovsxbd %xmm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmovsxbd (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovsxbq %xmm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmovsxbq (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovsxbw %xmm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmovsxbw (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovsxdq %xmm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmovsxdq (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovsxwd %xmm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmovsxwd (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovsxwq %xmm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmovsxwq (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovzxbd %xmm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmovzxbd (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovzxbq %xmm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmovzxbq (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovzxbw %xmm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmovzxbw (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovzxdq %xmm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmovzxdq (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovzxwd %xmm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmovzxwd (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovzxwq %xmm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmovzxwq (%rax), %ymm2
+# CHECK-NEXT: 1 3 1.00 vpmuldq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 1.00 * vpmuldq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 1.00 vpmulhrsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 1.00 * vpmulhrsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 1.00 vpmulhuw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 1.00 * vpmulhuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 1.00 vpmulhw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 1.00 * vpmulhw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 2.00 vpmulld %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.00 * vpmulld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 1.00 vpmullw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 1.00 * vpmullw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 1.00 vpmuludq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 1.00 * vpmuludq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpor %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpor (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 1.00 vpsadbw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 1.00 * vpsadbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpshufb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpshufb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpshufd $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpshufd $1, (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vpshufhw $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpshufhw $1, (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vpshuflw $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpshuflw $1, (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.25 vpsignb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsignb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpsignd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsignd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpsignw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsignw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 1.00 vpslld $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 3 1.00 vpslld %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 1.00 * vpslld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpslldq $1, %ymm1, %ymm2
+# CHECK-NEXT: 1 1 1.00 vpsllq $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 3 1.00 vpsllq %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 1.00 * vpsllq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 2.00 vpsllvd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vpsllvd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 2.00 vpsllvd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 2.00 * vpsllvd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 2.00 vpsllvq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vpsllvq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 2.00 vpsllvq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 2.00 * vpsllvq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 1.00 vpsllw $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 3 1.00 vpsllw %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 1.00 * vpsllw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 1.00 vpsrad $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 3 1.00 vpsrad %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 1.00 * vpsrad (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 2.00 vpsravd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vpsravd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 2.00 vpsravd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 2.00 * vpsravd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 1.00 vpsraw $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 3 1.00 vpsraw %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 1.00 * vpsraw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 1.00 vpsrld $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 3 1.00 vpsrld %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 1.00 * vpsrld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsrldq $1, %ymm1, %ymm2
+# CHECK-NEXT: 1 1 1.00 vpsrlq $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 3 1.00 vpsrlq %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 1.00 * vpsrlq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 2.00 vpsrlvd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vpsrlvd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 2.00 vpsrlvd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 2.00 * vpsrlvd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 2.00 vpsrlvq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vpsrlvq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 2.00 vpsrlvq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 2.00 * vpsrlvq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 1.00 vpsrlw $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 3 1.00 vpsrlw %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 1.00 * vpsrlw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpsubb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsubb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpsubd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsubd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpsubq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsubq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpsubsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsubsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpsubsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsubsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpsubusb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsubusb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpsubusw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsubusw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpsubw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpsubw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhbw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpunpckhbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhdq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpunpckhdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhqdq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpunpckhqdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhwd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpunpckhwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpcklbw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpunpcklbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpckldq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpunpckldq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpcklqdq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpunpcklqdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpcklwd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpunpcklwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpxor %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpxor (%rax), %ymm1, %ymm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: 52.33 52.33 52.33 - - - - 149.50 144.50 35.50 77.50 52.33 52.33 52.33 76.00 76.00 1.67 1.67 1.67
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vbroadcasti128 (%rax), %ymm0
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - vbroadcastsd %xmm0, %ymm0
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - vbroadcastss %xmm0, %ymm0
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vextracti128 $1, %ymm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vextracti128 $1, %ymm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vgatherdpd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vgatherdpd %ymm0, (%rax,%xmm1,2), %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vgatherdps %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vgatherdps %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vgatherqpd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vgatherqpd %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vgatherqps %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vgatherqps %xmm0, (%rax,%ymm1,2), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vinserti128 $1, %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vinserti128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vmovntdqa (%rax), %ymm0
+# CHECK-NEXT: - - - - - - - 2.00 2.00 2.00 2.00 - - - - - - - - vmpsadbw $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 2.00 2.00 2.00 2.00 0.33 0.33 0.33 0.50 0.50 - - - vmpsadbw $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpabsb %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpabsb (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpabsd %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpabsd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpabsw %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpabsw (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpackssdw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpackssdw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpacksswb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpacksswb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpackusdw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpackusdw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpackuswb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpackuswb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpaddb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpaddb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpaddd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpaddd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpaddq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpaddq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpaddsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpaddsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpaddsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpaddsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpaddusb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpaddusb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpaddusw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpaddusw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpaddw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpaddw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpalignr $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpalignr $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpand %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpand (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpandn %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpandn (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpavgb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpavgb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpavgw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpavgw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpblendd $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpblendd $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpblendd $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpblendd $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - vpblendvb %ymm3, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpblendvb %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpblendw $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpblendw $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpbroadcastb %xmm0, %xmm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpbroadcastb (%rax), %xmm0
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpbroadcastb %xmm0, %ymm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpbroadcastb (%rax), %ymm0
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpbroadcastd %xmm0, %xmm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpbroadcastd (%rax), %xmm0
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpbroadcastd %xmm0, %ymm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpbroadcastd (%rax), %ymm0
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpbroadcastq %xmm0, %xmm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpbroadcastq (%rax), %xmm0
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpbroadcastq %xmm0, %ymm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpbroadcastq (%rax), %ymm0
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpbroadcastw %xmm0, %xmm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpbroadcastw (%rax), %xmm0
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpbroadcastw %xmm0, %ymm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpbroadcastw (%rax), %ymm0
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpcmpeqb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpcmpeqb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpcmpeqd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpcmpeqd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpcmpeqq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpcmpeqq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpcmpeqw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpcmpeqw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpcmpgtb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpcmpgtb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpcmpgtd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpcmpgtd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpcmpgtq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpcmpgtq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpcmpgtw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpcmpgtw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vperm2i128 $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vperm2i128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - vpermd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpermd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - vpermpd $1, %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpermpd $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - vpermps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpermps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpermq $1, %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpermq $1, (%rax), %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vpgatherdd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vpgatherdd %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vpgatherdq %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vpgatherdq %ymm0, (%rax,%xmm1,2), %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vpgatherqd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vpgatherqd %xmm0, (%rax,%ymm1,2), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vpgatherqq %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - vpgatherqq %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - vphaddd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - vphaddd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - vphaddsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - vphaddsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - vphaddw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - vphaddw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - vphsubd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - vphsubd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - vphsubsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - vphsubsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - vphsubw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - vphsubw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - vpmaddubsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpmaddubsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - vpmaddwd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpmaddwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - 1.00 - 0.33 0.33 0.33 0.50 0.50 - - - vpmaskmovd (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - 1.00 - 0.33 0.33 0.33 0.50 0.50 - - - vpmaskmovd (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vpmaskmovd %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vpmaskmovd %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - 1.00 - 0.33 0.33 0.33 0.50 0.50 - - - vpmaskmovq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - 1.00 - 0.33 0.33 0.33 0.50 0.50 - - - vpmaskmovq (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vpmaskmovq %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vpmaskmovq %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpmaxsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpmaxsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpmaxsd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpmaxsd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpmaxsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpmaxsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpmaxub %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpmaxub (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpmaxud %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpmaxud (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpmaxuw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpmaxuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpminsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpminsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpminsd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpminsd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpminsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpminsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpminub %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpminub (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpminud %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpminud (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpminuw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpminuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpmovmskb %ymm0, %ecx
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpmovsxbd %xmm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpmovsxbd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpmovsxbq %xmm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpmovsxbq (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpmovsxbw %xmm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpmovsxbw (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpmovsxdq %xmm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpmovsxdq (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpmovsxwd %xmm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpmovsxwd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpmovsxwq %xmm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpmovsxwq (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpmovzxbd %xmm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpmovzxbd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpmovzxbq %xmm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpmovzxbq (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpmovzxbw %xmm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpmovzxbw (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpmovzxdq %xmm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpmovzxdq (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpmovzxwd %xmm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpmovzxwd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpmovzxwq %xmm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpmovzxwq (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - vpmuldq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpmuldq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - vpmulhrsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpmulhrsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - vpmulhuw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpmulhuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - vpmulhw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpmulhw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 2.00 - - - - - - - - - - - vpmulld %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 2.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpmulld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - vpmullw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpmullw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - vpmuludq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpmuludq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpor %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpor (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - vpsadbw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpsadbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpshufb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpshufb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpshufd $1, %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpshufd $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpshufhw $1, %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpshufhw $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpshuflw $1, %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpshuflw $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpsignb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpsignb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpsignd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpsignd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpsignw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpsignw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpslld $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpslld %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vpslld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpslldq $1, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpsllq $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpsllq %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vpsllq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 2.00 - - - - - - - - - - - vpsllvd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 2.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpsllvd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 2.00 - - - - - - - - - - - vpsllvd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 2.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpsllvd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 2.00 - - - - - - - - - - - vpsllvq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 2.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpsllvq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 2.00 - - - - - - - - - - - vpsllvq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 2.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpsllvq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpsllw $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpsllw %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vpsllw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpsrad $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpsrad %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vpsrad (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 2.00 - - - - - - - - - - - vpsravd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 2.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpsravd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 2.00 - - - - - - - - - - - vpsravd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 2.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpsravd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpsraw $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpsraw %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vpsraw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpsrld $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpsrld %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vpsrld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpsrldq $1, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpsrlq $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpsrlq %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vpsrlq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 2.00 - - - - - - - - - - - vpsrlvd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 2.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpsrlvd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 2.00 - - - - - - - - - - - vpsrlvd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 2.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpsrlvd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 2.00 - - - - - - - - - - - vpsrlvq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 2.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpsrlvq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 2.00 - - - - - - - - - - - vpsrlvq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 2.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vpsrlvq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpsrlw $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - vpsrlw %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vpsrlw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpsubb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpsubb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpsubd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpsubd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpsubq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpsubq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpsubsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpsubsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpsubsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpsubsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpsubusb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpsubusb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpsubusw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpsubusw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpsubw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpsubw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpunpckhbw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpunpckhbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpunpckhdq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpunpckhdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpunpckhqdq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpunpckhqdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpunpckhwd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpunpckhwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpunpcklbw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpunpcklbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpunpckldq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpunpckldq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpunpcklqdq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpunpcklqdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - vpunpcklwd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - vpunpcklwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - vpxor %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - vpxor (%rax), %ymm1, %ymm2
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-bmi1.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-bmi1.s
new file mode 100644
index 0000000000000..9390c311497ee
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-bmi1.s
@@ -0,0 +1,131 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+andn %eax, %ebx, %ecx
+andn (%rax), %ebx, %ecx
+
+andn %rax, %rbx, %rcx
+andn (%rax), %rbx, %rcx
+
+bextr %eax, %ebx, %ecx
+bextr %eax, (%rbx), %ecx
+
+bextr %rax, %rbx, %rcx
+bextr %rax, (%rbx), %rcx
+
+blsi %eax, %ecx
+blsi (%rax), %ecx
+
+blsi %rax, %rcx
+blsi (%rax), %rcx
+
+blsmsk %eax, %ecx
+blsmsk (%rax), %ecx
+
+blsmsk %rax, %rcx
+blsmsk (%rax), %rcx
+
+blsr %eax, %ecx
+blsr (%rax), %ecx
+
+blsr %rax, %rcx
+blsr (%rax), %rcx
+
+tzcnt %ax, %cx
+tzcnt (%rax), %cx
+
+tzcnt %eax, %ecx
+tzcnt (%rax), %ecx
+
+tzcnt %rax, %rcx
+tzcnt (%rax), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.17 andnl %eax, %ebx, %ecx
+# CHECK-NEXT: 1 5 0.50 * andnl (%rax), %ebx, %ecx
+# CHECK-NEXT: 1 1 0.17 andnq %rax, %rbx, %rcx
+# CHECK-NEXT: 1 5 0.50 * andnq (%rax), %rbx, %rcx
+# CHECK-NEXT: 1 1 0.17 bextrl %eax, %ebx, %ecx
+# CHECK-NEXT: 5 5 0.50 * bextrl %eax, (%rbx), %ecx
+# CHECK-NEXT: 1 1 0.17 bextrq %rax, %rbx, %rcx
+# CHECK-NEXT: 5 5 0.50 * bextrq %rax, (%rbx), %rcx
+# CHECK-NEXT: 2 2 0.33 blsil %eax, %ecx
+# CHECK-NEXT: 6 6 0.50 * blsil (%rax), %ecx
+# CHECK-NEXT: 2 2 0.33 blsiq %rax, %rcx
+# CHECK-NEXT: 6 6 0.50 * blsiq (%rax), %rcx
+# CHECK-NEXT: 2 2 0.33 blsmskl %eax, %ecx
+# CHECK-NEXT: 6 6 0.50 * blsmskl (%rax), %ecx
+# CHECK-NEXT: 2 2 0.33 blsmskq %rax, %rcx
+# CHECK-NEXT: 6 6 0.50 * blsmskq (%rax), %rcx
+# CHECK-NEXT: 2 2 0.33 blsrl %eax, %ecx
+# CHECK-NEXT: 6 6 0.50 * blsrl (%rax), %ecx
+# CHECK-NEXT: 2 2 0.33 blsrq %rax, %rcx
+# CHECK-NEXT: 6 6 0.50 * blsrq (%rax), %rcx
+# CHECK-NEXT: 2 2 0.33 tzcntw %ax, %cx
+# CHECK-NEXT: 6 6 0.33 * tzcntw (%rax), %cx
+# CHECK-NEXT: 2 2 0.33 tzcntl %eax, %ecx
+# CHECK-NEXT: 6 6 0.33 * tzcntl (%rax), %ecx
+# CHECK-NEXT: 2 2 0.33 tzcntq %rax, %rcx
+# CHECK-NEXT: 6 6 0.33 * tzcntq (%rax), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: 4.33 4.33 4.33 14.67 7.33 7.33 14.67 - - - - 3.33 3.33 3.33 5.00 5.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - andnl %eax, %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - andnl (%rax), %ebx, %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - andnq %rax, %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - andnq (%rax), %rbx, %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - bextrl %eax, %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - bextrl %eax, (%rbx), %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - bextrq %rax, %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - bextrq %rax, (%rbx), %rcx
+# CHECK-NEXT: - - - 0.67 0.33 0.33 0.67 - - - - - - - - - - - - blsil %eax, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.67 0.33 0.33 0.67 - - - - 0.33 0.33 0.33 0.50 0.50 - - - blsil (%rax), %ecx
+# CHECK-NEXT: - - - 0.67 0.33 0.33 0.67 - - - - - - - - - - - - blsiq %rax, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.67 0.33 0.33 0.67 - - - - 0.33 0.33 0.33 0.50 0.50 - - - blsiq (%rax), %rcx
+# CHECK-NEXT: - - - 0.67 0.33 0.33 0.67 - - - - - - - - - - - - blsmskl %eax, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.67 0.33 0.33 0.67 - - - - 0.33 0.33 0.33 0.50 0.50 - - - blsmskl (%rax), %ecx
+# CHECK-NEXT: - - - 0.67 0.33 0.33 0.67 - - - - - - - - - - - - blsmskq %rax, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.67 0.33 0.33 0.67 - - - - 0.33 0.33 0.33 0.50 0.50 - - - blsmskq (%rax), %rcx
+# CHECK-NEXT: - - - 0.67 0.33 0.33 0.67 - - - - - - - - - - - - blsrl %eax, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.67 0.33 0.33 0.67 - - - - 0.33 0.33 0.33 0.50 0.50 - - - blsrl (%rax), %ecx
+# CHECK-NEXT: - - - 0.67 0.33 0.33 0.67 - - - - - - - - - - - - blsrq %rax, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.67 0.33 0.33 0.67 - - - - 0.33 0.33 0.33 0.50 0.50 - - - blsrq (%rax), %rcx
+# CHECK-NEXT: - - - 0.67 0.33 0.33 0.67 - - - - - - - - - - - - tzcntw %ax, %cx
+# CHECK-NEXT: 0.33 0.33 0.33 0.67 0.33 0.33 0.67 - - - - - - - - - - - - tzcntw (%rax), %cx
+# CHECK-NEXT: - - - 0.67 0.33 0.33 0.67 - - - - - - - - - - - - tzcntl %eax, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.67 0.33 0.33 0.67 - - - - - - - - - - - - tzcntl (%rax), %ecx
+# CHECK-NEXT: - - - 0.67 0.33 0.33 0.67 - - - - - - - - - - - - tzcntq %rax, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.67 0.33 0.33 0.67 - - - - - - - - - - - - tzcntq (%rax), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-bmi2.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-bmi2.s
new file mode 100644
index 0000000000000..dda307e7f47a2
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-bmi2.s
@@ -0,0 +1,152 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+bzhi %eax, %ebx, %ecx
+bzhi %eax, (%rbx), %ecx
+
+bzhi %rax, %rbx, %rcx
+bzhi %rax, (%rbx), %rcx
+
+mulx %eax, %ebx, %ecx
+mulx (%rax), %ebx, %ecx
+
+mulx %rax, %rbx, %rcx
+mulx (%rax), %rbx, %rcx
+
+pdep %eax, %ebx, %ecx
+pdep (%rax), %ebx, %ecx
+
+pdep %rax, %rbx, %rcx
+pdep (%rax), %rbx, %rcx
+
+pext %eax, %ebx, %ecx
+pext (%rax), %ebx, %ecx
+
+pext %rax, %rbx, %rcx
+pext (%rax), %rbx, %rcx
+
+rorx $1, %eax, %ecx
+rorx $1, (%rax), %ecx
+
+rorx $1, %rax, %rcx
+rorx $1, (%rax), %rcx
+
+sarx %eax, %ebx, %ecx
+sarx %eax, (%rbx), %ecx
+
+sarx %rax, %rbx, %rcx
+sarx %rax, (%rbx), %rcx
+
+shlx %eax, %ebx, %ecx
+shlx %eax, (%rbx), %ecx
+
+shlx %rax, %rbx, %rcx
+shlx %rax, (%rbx), %rcx
+
+shrx %eax, %ebx, %ecx
+shrx %eax, (%rbx), %ecx
+
+shrx %rax, %rbx, %rcx
+shrx %rax, (%rbx), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.17 bzhil %eax, %ebx, %ecx
+# CHECK-NEXT: 1 5 0.50 * bzhil %eax, (%rbx), %ecx
+# CHECK-NEXT: 1 1 0.17 bzhiq %rax, %rbx, %rcx
+# CHECK-NEXT: 1 5 0.50 * bzhiq %rax, (%rbx), %rcx
+# CHECK-NEXT: 1 4 1.00 mulxl %eax, %ebx, %ecx
+# CHECK-NEXT: 1 11 1.00 * mulxl (%rax), %ebx, %ecx
+# CHECK-NEXT: 1 4 1.00 mulxq %rax, %rbx, %rcx
+# CHECK-NEXT: 1 11 1.00 * mulxq (%rax), %rbx, %rcx
+# CHECK-NEXT: 1 100 0.25 pdepl %eax, %ebx, %ecx
+# CHECK-NEXT: 1 100 0.25 * pdepl (%rax), %ebx, %ecx
+# CHECK-NEXT: 1 100 0.25 pdepq %rax, %rbx, %rcx
+# CHECK-NEXT: 1 100 0.25 * pdepq (%rax), %rbx, %rcx
+# CHECK-NEXT: 1 100 0.25 pextl %eax, %ebx, %ecx
+# CHECK-NEXT: 1 100 0.25 * pextl (%rax), %ebx, %ecx
+# CHECK-NEXT: 1 100 0.25 pextq %rax, %rbx, %rcx
+# CHECK-NEXT: 1 100 0.25 * pextq (%rax), %rbx, %rcx
+# CHECK-NEXT: 1 1 0.17 rorxl $1, %eax, %ecx
+# CHECK-NEXT: 1 5 0.50 * rorxl $1, (%rax), %ecx
+# CHECK-NEXT: 1 1 0.17 rorxq $1, %rax, %rcx
+# CHECK-NEXT: 1 5 0.50 * rorxq $1, (%rax), %rcx
+# CHECK-NEXT: 1 1 0.17 sarxl %eax, %ebx, %ecx
+# CHECK-NEXT: 1 5 0.50 * sarxl %eax, (%rbx), %ecx
+# CHECK-NEXT: 1 1 0.17 sarxq %rax, %rbx, %rcx
+# CHECK-NEXT: 1 5 0.50 * sarxq %rax, (%rbx), %rcx
+# CHECK-NEXT: 1 1 0.17 shlxl %eax, %ebx, %ecx
+# CHECK-NEXT: 1 5 0.50 * shlxl %eax, (%rbx), %ecx
+# CHECK-NEXT: 1 1 0.17 shlxq %rax, %rbx, %rcx
+# CHECK-NEXT: 1 5 0.50 * shlxq %rax, (%rbx), %rcx
+# CHECK-NEXT: 1 1 0.17 shrxl %eax, %ebx, %ecx
+# CHECK-NEXT: 1 5 0.50 * shrxl %eax, (%rbx), %ecx
+# CHECK-NEXT: 1 1 0.17 shrxq %rax, %rbx, %rcx
+# CHECK-NEXT: 1 5 0.50 * shrxq %rax, (%rbx), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: 4.00 4.00 4.00 6.67 7.33 3.33 6.67 - - - - 4.00 4.00 4.00 6.00 6.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - bzhil %eax, %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - bzhil %eax, (%rbx), %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - bzhiq %rax, %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - bzhiq %rax, (%rbx), %rcx
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - mulxl %eax, %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - 1.00 - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - mulxl (%rax), %ebx, %ecx
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - mulxq %rax, %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - 1.00 - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - mulxq (%rax), %rbx, %rcx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - pdepl %eax, %ebx, %ecx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - pdepl (%rax), %ebx, %ecx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - pdepq %rax, %rbx, %rcx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - pdepq (%rax), %rbx, %rcx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - pextl %eax, %ebx, %ecx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - pextl (%rax), %ebx, %ecx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - pextq %rax, %rbx, %rcx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - pextq (%rax), %rbx, %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rorxl $1, %eax, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - rorxl $1, (%rax), %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rorxq $1, %rax, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - rorxq $1, (%rax), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sarxl %eax, %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - sarxl %eax, (%rbx), %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sarxq %rax, %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - sarxq %rax, (%rbx), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - shlxl %eax, %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - shlxl %eax, (%rbx), %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - shlxq %rax, %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - shlxq %rax, (%rbx), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - shrxl %eax, %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - shrxl %eax, (%rbx), %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - shrxq %rax, %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - shrxq %rax, (%rbx), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-clflushopt.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-clflushopt.s
new file mode 100644
index 0000000000000..c30b36d482d99
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-clflushopt.s
@@ -0,0 +1,44 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+clflushopt (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 5 0.50 * * U clflushopt (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - clflushopt (%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-clzero.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-clzero.s
new file mode 100644
index 0000000000000..49cfad21a0dcd
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-clzero.s
@@ -0,0 +1,44 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+clzero
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 5 0.50 U clzero
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - clzero
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-cmov.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-cmov.s
new file mode 100644
index 0000000000000..299eaeb410909
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-cmov.s
@@ -0,0 +1,334 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+cmovow %si, %di
+cmovnow %si, %di
+cmovbw %si, %di
+cmovaew %si, %di
+cmovew %si, %di
+cmovnew %si, %di
+cmovbew %si, %di
+cmovaw %si, %di
+cmovsw %si, %di
+cmovnsw %si, %di
+cmovpw %si, %di
+cmovnpw %si, %di
+cmovlw %si, %di
+cmovgew %si, %di
+cmovlew %si, %di
+cmovgw %si, %di
+
+cmovow (%rax), %di
+cmovnow (%rax), %di
+cmovbw (%rax), %di
+cmovaew (%rax), %di
+cmovew (%rax), %di
+cmovnew (%rax), %di
+cmovbew (%rax), %di
+cmovaw (%rax), %di
+cmovsw (%rax), %di
+cmovnsw (%rax), %di
+cmovpw (%rax), %di
+cmovnpw (%rax), %di
+cmovlw (%rax), %di
+cmovgew (%rax), %di
+cmovlew (%rax), %di
+cmovgw (%rax), %di
+
+cmovol %esi, %edi
+cmovnol %esi, %edi
+cmovbl %esi, %edi
+cmovael %esi, %edi
+cmovel %esi, %edi
+cmovnel %esi, %edi
+cmovbel %esi, %edi
+cmoval %esi, %edi
+cmovsl %esi, %edi
+cmovnsl %esi, %edi
+cmovpl %esi, %edi
+cmovnpl %esi, %edi
+cmovll %esi, %edi
+cmovgel %esi, %edi
+cmovlel %esi, %edi
+cmovgl %esi, %edi
+
+cmovol (%rax), %edi
+cmovnol (%rax), %edi
+cmovbl (%rax), %edi
+cmovael (%rax), %edi
+cmovel (%rax), %edi
+cmovnel (%rax), %edi
+cmovbel (%rax), %edi
+cmoval (%rax), %edi
+cmovsl (%rax), %edi
+cmovnsl (%rax), %edi
+cmovpl (%rax), %edi
+cmovnpl (%rax), %edi
+cmovll (%rax), %edi
+cmovgel (%rax), %edi
+cmovlel (%rax), %edi
+cmovgl (%rax), %edi
+
+cmovoq %rsi, %rdi
+cmovnoq %rsi, %rdi
+cmovbq %rsi, %rdi
+cmovaeq %rsi, %rdi
+cmoveq %rsi, %rdi
+cmovneq %rsi, %rdi
+cmovbeq %rsi, %rdi
+cmovaq %rsi, %rdi
+cmovsq %rsi, %rdi
+cmovnsq %rsi, %rdi
+cmovpq %rsi, %rdi
+cmovnpq %rsi, %rdi
+cmovlq %rsi, %rdi
+cmovgeq %rsi, %rdi
+cmovleq %rsi, %rdi
+cmovgq %rsi, %rdi
+
+cmovoq (%rax), %rdi
+cmovnoq (%rax), %rdi
+cmovbq (%rax), %rdi
+cmovaeq (%rax), %rdi
+cmoveq (%rax), %rdi
+cmovneq (%rax), %rdi
+cmovbeq (%rax), %rdi
+cmovaq (%rax), %rdi
+cmovsq (%rax), %rdi
+cmovnsq (%rax), %rdi
+cmovpq (%rax), %rdi
+cmovnpq (%rax), %rdi
+cmovlq (%rax), %rdi
+cmovgeq (%rax), %rdi
+cmovleq (%rax), %rdi
+cmovgq (%rax), %rdi
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.17 cmovow %si, %di
+# CHECK-NEXT: 1 1 0.17 cmovnow %si, %di
+# CHECK-NEXT: 1 1 0.17 cmovbw %si, %di
+# CHECK-NEXT: 1 1 0.17 cmovaew %si, %di
+# CHECK-NEXT: 1 1 0.17 cmovew %si, %di
+# CHECK-NEXT: 1 1 0.17 cmovnew %si, %di
+# CHECK-NEXT: 1 1 0.17 cmovbew %si, %di
+# CHECK-NEXT: 1 1 0.17 cmovaw %si, %di
+# CHECK-NEXT: 1 1 0.17 cmovsw %si, %di
+# CHECK-NEXT: 1 1 0.17 cmovnsw %si, %di
+# CHECK-NEXT: 1 1 0.17 cmovpw %si, %di
+# CHECK-NEXT: 1 1 0.17 cmovnpw %si, %di
+# CHECK-NEXT: 1 1 0.17 cmovlw %si, %di
+# CHECK-NEXT: 1 1 0.17 cmovgew %si, %di
+# CHECK-NEXT: 1 1 0.17 cmovlew %si, %di
+# CHECK-NEXT: 1 1 0.17 cmovgw %si, %di
+# CHECK-NEXT: 1 5 0.50 * cmovow (%rax), %di
+# CHECK-NEXT: 1 5 0.50 * cmovnow (%rax), %di
+# CHECK-NEXT: 1 5 0.50 * cmovbw (%rax), %di
+# CHECK-NEXT: 1 5 0.50 * cmovaew (%rax), %di
+# CHECK-NEXT: 1 5 0.50 * cmovew (%rax), %di
+# CHECK-NEXT: 1 5 0.50 * cmovnew (%rax), %di
+# CHECK-NEXT: 1 5 0.50 * cmovbew (%rax), %di
+# CHECK-NEXT: 1 5 0.50 * cmovaw (%rax), %di
+# CHECK-NEXT: 1 5 0.50 * cmovsw (%rax), %di
+# CHECK-NEXT: 1 5 0.50 * cmovnsw (%rax), %di
+# CHECK-NEXT: 1 5 0.50 * cmovpw (%rax), %di
+# CHECK-NEXT: 1 5 0.50 * cmovnpw (%rax), %di
+# CHECK-NEXT: 1 5 0.50 * cmovlw (%rax), %di
+# CHECK-NEXT: 1 5 0.50 * cmovgew (%rax), %di
+# CHECK-NEXT: 1 5 0.50 * cmovlew (%rax), %di
+# CHECK-NEXT: 1 5 0.50 * cmovgw (%rax), %di
+# CHECK-NEXT: 1 1 0.17 cmovol %esi, %edi
+# CHECK-NEXT: 1 1 0.17 cmovnol %esi, %edi
+# CHECK-NEXT: 1 1 0.17 cmovbl %esi, %edi
+# CHECK-NEXT: 1 1 0.17 cmovael %esi, %edi
+# CHECK-NEXT: 1 1 0.17 cmovel %esi, %edi
+# CHECK-NEXT: 1 1 0.17 cmovnel %esi, %edi
+# CHECK-NEXT: 1 1 0.17 cmovbel %esi, %edi
+# CHECK-NEXT: 1 1 0.17 cmoval %esi, %edi
+# CHECK-NEXT: 1 1 0.17 cmovsl %esi, %edi
+# CHECK-NEXT: 1 1 0.17 cmovnsl %esi, %edi
+# CHECK-NEXT: 1 1 0.17 cmovpl %esi, %edi
+# CHECK-NEXT: 1 1 0.17 cmovnpl %esi, %edi
+# CHECK-NEXT: 1 1 0.17 cmovll %esi, %edi
+# CHECK-NEXT: 1 1 0.17 cmovgel %esi, %edi
+# CHECK-NEXT: 1 1 0.17 cmovlel %esi, %edi
+# CHECK-NEXT: 1 1 0.17 cmovgl %esi, %edi
+# CHECK-NEXT: 1 5 0.50 * cmovol (%rax), %edi
+# CHECK-NEXT: 1 5 0.50 * cmovnol (%rax), %edi
+# CHECK-NEXT: 1 5 0.50 * cmovbl (%rax), %edi
+# CHECK-NEXT: 1 5 0.50 * cmovael (%rax), %edi
+# CHECK-NEXT: 1 5 0.50 * cmovel (%rax), %edi
+# CHECK-NEXT: 1 5 0.50 * cmovnel (%rax), %edi
+# CHECK-NEXT: 1 5 0.50 * cmovbel (%rax), %edi
+# CHECK-NEXT: 1 5 0.50 * cmoval (%rax), %edi
+# CHECK-NEXT: 1 5 0.50 * cmovsl (%rax), %edi
+# CHECK-NEXT: 1 5 0.50 * cmovnsl (%rax), %edi
+# CHECK-NEXT: 1 5 0.50 * cmovpl (%rax), %edi
+# CHECK-NEXT: 1 5 0.50 * cmovnpl (%rax), %edi
+# CHECK-NEXT: 1 5 0.50 * cmovll (%rax), %edi
+# CHECK-NEXT: 1 5 0.50 * cmovgel (%rax), %edi
+# CHECK-NEXT: 1 5 0.50 * cmovlel (%rax), %edi
+# CHECK-NEXT: 1 5 0.50 * cmovgl (%rax), %edi
+# CHECK-NEXT: 1 1 0.17 cmovoq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.17 cmovnoq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.17 cmovbq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.17 cmovaeq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.17 cmoveq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.17 cmovneq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.17 cmovbeq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.17 cmovaq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.17 cmovsq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.17 cmovnsq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.17 cmovpq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.17 cmovnpq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.17 cmovlq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.17 cmovgeq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.17 cmovleq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.17 cmovgq %rsi, %rdi
+# CHECK-NEXT: 1 5 0.50 * cmovoq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.50 * cmovnoq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.50 * cmovbq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.50 * cmovaeq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.50 * cmoveq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.50 * cmovneq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.50 * cmovbeq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.50 * cmovaq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.50 * cmovsq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.50 * cmovnsq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.50 * cmovpq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.50 * cmovnpq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.50 * cmovlq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.50 * cmovgeq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.50 * cmovleq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.50 * cmovgq (%rax), %rdi
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: 16.00 16.00 16.00 32.00 16.00 16.00 32.00 - - - - 16.00 16.00 16.00 24.00 24.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovow %si, %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovnow %si, %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovbw %si, %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovaew %si, %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovew %si, %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovnew %si, %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovbew %si, %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovaw %si, %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovsw %si, %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovnsw %si, %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovpw %si, %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovnpw %si, %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovlw %si, %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovgew %si, %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovlew %si, %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovgw %si, %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovow (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovnow (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovbw (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovaew (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovew (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovnew (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovbew (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovaw (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovsw (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovnsw (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovpw (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovnpw (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovlw (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovgew (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovlew (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovgw (%rax), %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovol %esi, %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovnol %esi, %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovbl %esi, %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovael %esi, %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovel %esi, %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovnel %esi, %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovbel %esi, %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmoval %esi, %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovsl %esi, %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovnsl %esi, %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovpl %esi, %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovnpl %esi, %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovll %esi, %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovgel %esi, %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovlel %esi, %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovgl %esi, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovol (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovnol (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovbl (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovael (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovel (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovnel (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovbel (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmoval (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovsl (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovnsl (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovpl (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovnpl (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovll (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovgel (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovlel (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovgl (%rax), %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovoq %rsi, %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovnoq %rsi, %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovbq %rsi, %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovaeq %rsi, %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmoveq %rsi, %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovneq %rsi, %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovbeq %rsi, %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovaq %rsi, %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovsq %rsi, %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovnsq %rsi, %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovpq %rsi, %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovnpq %rsi, %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovlq %rsi, %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovgeq %rsi, %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovleq %rsi, %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmovgq %rsi, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovoq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovnoq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovbq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovaeq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmoveq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovneq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovbeq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovaq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovsq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovnsq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovpq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovnpq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovlq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovgeq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovleq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmovgq (%rax), %rdi
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-cmpxchg.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-cmpxchg.s
new file mode 100644
index 0000000000000..e95bb3c77a268
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-cmpxchg.s
@@ -0,0 +1,53 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+cmpxchg8b (%rax)
+cmpxchg16b (%rax)
+lock cmpxchg8b (%rax)
+lock cmpxchg16b (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 3 5 0.33 * * cmpxchg8b (%rax)
+# CHECK-NEXT: 3 5 0.33 * * cmpxchg16b (%rax)
+# CHECK-NEXT: 3 5 0.33 * * lock cmpxchg8b (%rax)
+# CHECK-NEXT: 3 5 0.33 * * lock cmpxchg16b (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: 1.33 1.33 1.33 1.33 0.67 0.67 1.33 - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmpxchg8b (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmpxchg16b (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - - - - - - - - - lock cmpxchg8b (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - - - - - - - - - lock cmpxchg16b (%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-f16c.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-f16c.s
new file mode 100644
index 0000000000000..cd714d5b9daf7
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-f16c.s
@@ -0,0 +1,68 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+vcvtph2ps %xmm0, %xmm2
+vcvtph2ps (%rax), %xmm2
+
+vcvtph2ps %xmm0, %ymm2
+vcvtph2ps (%rax), %ymm2
+
+vcvtps2ph $0, %xmm0, %xmm2
+vcvtps2ph $0, %xmm0, (%rax)
+
+vcvtps2ph $0, %ymm0, %xmm2
+vcvtps2ph $0, %ymm0, (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 7 2.00 vcvtph2ps %xmm0, %xmm2
+# CHECK-NEXT: 1 14 2.00 * vcvtph2ps (%rax), %xmm2
+# CHECK-NEXT: 1 9 1.00 vcvtph2ps %xmm0, %ymm2
+# CHECK-NEXT: 1 16 1.00 * vcvtph2ps (%rax), %ymm2
+# CHECK-NEXT: 1 7 1.00 vcvtps2ph $0, %xmm0, %xmm2
+# CHECK-NEXT: 2 8 1.00 * vcvtps2ph $0, %xmm0, (%rax)
+# CHECK-NEXT: 1 9 2.00 vcvtps2ph $0, %ymm0, %xmm2
+# CHECK-NEXT: 3 10 2.00 * vcvtps2ph $0, %ymm0, (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: 1.33 1.33 1.33 - - - - 4.00 8.00 - - 1.33 1.33 1.33 1.00 1.00 0.67 0.67 0.67
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - vcvtph2ps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - - 0.33 0.33 0.33 0.50 0.50 - - - vcvtph2ps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - vcvtph2ps %xmm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - vcvtph2ps (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - vcvtps2ph $0, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vcvtps2ph $0, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - vcvtps2ph $0, %ymm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 vcvtps2ph $0, %ymm0, (%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-fma.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-fma.s
new file mode 100644
index 0000000000000..9695dad251087
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-fma.s
@@ -0,0 +1,712 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+vfmadd132pd %xmm0, %xmm1, %xmm2
+vfmadd132pd (%rax), %xmm1, %xmm2
+
+vfmadd132pd %ymm0, %ymm1, %ymm2
+vfmadd132pd (%rax), %ymm1, %ymm2
+
+vfmadd213pd %xmm0, %xmm1, %xmm2
+vfmadd213pd (%rax), %xmm1, %xmm2
+
+vfmadd213pd %ymm0, %ymm1, %ymm2
+vfmadd213pd (%rax), %ymm1, %ymm2
+
+vfmadd231pd %xmm0, %xmm1, %xmm2
+vfmadd231pd (%rax), %xmm1, %xmm2
+
+vfmadd231pd %ymm0, %ymm1, %ymm2
+vfmadd231pd (%rax), %ymm1, %ymm2
+
+vfmadd132ps %xmm0, %xmm1, %xmm2
+vfmadd132ps (%rax), %xmm1, %xmm2
+
+vfmadd132ps %ymm0, %ymm1, %ymm2
+vfmadd132ps (%rax), %ymm1, %ymm2
+
+vfmadd213ps %xmm0, %xmm1, %xmm2
+vfmadd213ps (%rax), %xmm1, %xmm2
+
+vfmadd213ps %ymm0, %ymm1, %ymm2
+vfmadd213ps (%rax), %ymm1, %ymm2
+
+vfmadd231ps %xmm0, %xmm1, %xmm2
+vfmadd231ps (%rax), %xmm1, %xmm2
+
+vfmadd231ps %ymm0, %ymm1, %ymm2
+vfmadd231ps (%rax), %ymm1, %ymm2
+
+vfmadd132sd %xmm0, %xmm1, %xmm2
+vfmadd132sd (%rax), %xmm1, %xmm2
+
+vfmadd213sd %xmm0, %xmm1, %xmm2
+vfmadd213sd (%rax), %xmm1, %xmm2
+
+vfmadd231sd %xmm0, %xmm1, %xmm2
+vfmadd231sd (%rax), %xmm1, %xmm2
+
+vfmadd132ss %xmm0, %xmm1, %xmm2
+vfmadd132ss (%rax), %xmm1, %xmm2
+
+vfmadd213ss %xmm0, %xmm1, %xmm2
+vfmadd213ss (%rax), %xmm1, %xmm2
+
+vfmadd231ss %xmm0, %xmm1, %xmm2
+vfmadd231ss (%rax), %xmm1, %xmm2
+
+vfmaddsub132pd %xmm0, %xmm1, %xmm2
+vfmaddsub132pd (%rax), %xmm1, %xmm2
+
+vfmaddsub132pd %ymm0, %ymm1, %ymm2
+vfmaddsub132pd (%rax), %ymm1, %ymm2
+
+vfmaddsub213pd %xmm0, %xmm1, %xmm2
+vfmaddsub213pd (%rax), %xmm1, %xmm2
+
+vfmaddsub213pd %ymm0, %ymm1, %ymm2
+vfmaddsub213pd (%rax), %ymm1, %ymm2
+
+vfmaddsub231pd %xmm0, %xmm1, %xmm2
+vfmaddsub231pd (%rax), %xmm1, %xmm2
+
+vfmaddsub231pd %ymm0, %ymm1, %ymm2
+vfmaddsub231pd (%rax), %ymm1, %ymm2
+
+vfmaddsub132ps %xmm0, %xmm1, %xmm2
+vfmaddsub132ps (%rax), %xmm1, %xmm2
+
+vfmaddsub132ps %ymm0, %ymm1, %ymm2
+vfmaddsub132ps (%rax), %ymm1, %ymm2
+
+vfmaddsub213ps %xmm0, %xmm1, %xmm2
+vfmaddsub213ps (%rax), %xmm1, %xmm2
+
+vfmaddsub213ps %ymm0, %ymm1, %ymm2
+vfmaddsub213ps (%rax), %ymm1, %ymm2
+
+vfmaddsub231ps %xmm0, %xmm1, %xmm2
+vfmaddsub231ps (%rax), %xmm1, %xmm2
+
+vfmaddsub231ps %ymm0, %ymm1, %ymm2
+vfmaddsub231ps (%rax), %ymm1, %ymm2
+
+vfmsub132pd %xmm0, %xmm1, %xmm2
+vfmsub132pd (%rax), %xmm1, %xmm2
+
+vfmsub132pd %ymm0, %ymm1, %ymm2
+vfmsub132pd (%rax), %ymm1, %ymm2
+
+vfmsub213pd %xmm0, %xmm1, %xmm2
+vfmsub213pd (%rax), %xmm1, %xmm2
+
+vfmsub213pd %ymm0, %ymm1, %ymm2
+vfmsub213pd (%rax), %ymm1, %ymm2
+
+vfmsub231pd %xmm0, %xmm1, %xmm2
+vfmsub231pd (%rax), %xmm1, %xmm2
+
+vfmsub231pd %ymm0, %ymm1, %ymm2
+vfmsub231pd (%rax), %ymm1, %ymm2
+
+vfmsub132ps %xmm0, %xmm1, %xmm2
+vfmsub132ps (%rax), %xmm1, %xmm2
+
+vfmsub132ps %ymm0, %ymm1, %ymm2
+vfmsub132ps (%rax), %ymm1, %ymm2
+
+vfmsub213ps %xmm0, %xmm1, %xmm2
+vfmsub213ps (%rax), %xmm1, %xmm2
+
+vfmsub213ps %ymm0, %ymm1, %ymm2
+vfmsub213ps (%rax), %ymm1, %ymm2
+
+vfmsub231ps %xmm0, %xmm1, %xmm2
+vfmsub231ps (%rax), %xmm1, %xmm2
+
+vfmsub231ps %ymm0, %ymm1, %ymm2
+vfmsub231ps (%rax), %ymm1, %ymm2
+
+vfmsub132sd %xmm0, %xmm1, %xmm2
+vfmsub132sd (%rax), %xmm1, %xmm2
+
+vfmsub213sd %xmm0, %xmm1, %xmm2
+vfmsub213sd (%rax), %xmm1, %xmm2
+
+vfmsub231sd %xmm0, %xmm1, %xmm2
+vfmsub231sd (%rax), %xmm1, %xmm2
+
+vfmsub132ss %xmm0, %xmm1, %xmm2
+vfmsub132ss (%rax), %xmm1, %xmm2
+
+vfmsub213ss %xmm0, %xmm1, %xmm2
+vfmsub213ss (%rax), %xmm1, %xmm2
+
+vfmsub231ss %xmm0, %xmm1, %xmm2
+vfmsub231ss (%rax), %xmm1, %xmm2
+
+vfmsubadd132pd %xmm0, %xmm1, %xmm2
+vfmsubadd132pd (%rax), %xmm1, %xmm2
+
+vfmsubadd132pd %ymm0, %ymm1, %ymm2
+vfmsubadd132pd (%rax), %ymm1, %ymm2
+
+vfmsubadd213pd %xmm0, %xmm1, %xmm2
+vfmsubadd213pd (%rax), %xmm1, %xmm2
+
+vfmsubadd213pd %ymm0, %ymm1, %ymm2
+vfmsubadd213pd (%rax), %ymm1, %ymm2
+
+vfmsubadd231pd %xmm0, %xmm1, %xmm2
+vfmsubadd231pd (%rax), %xmm1, %xmm2
+
+vfmsubadd231pd %ymm0, %ymm1, %ymm2
+vfmsubadd231pd (%rax), %ymm1, %ymm2
+
+vfmsubadd132ps %xmm0, %xmm1, %xmm2
+vfmsubadd132ps (%rax), %xmm1, %xmm2
+
+vfmsubadd132ps %ymm0, %ymm1, %ymm2
+vfmsubadd132ps (%rax), %ymm1, %ymm2
+
+vfmsubadd213ps %xmm0, %xmm1, %xmm2
+vfmsubadd213ps (%rax), %xmm1, %xmm2
+
+vfmsubadd213ps %ymm0, %ymm1, %ymm2
+vfmsubadd213ps (%rax), %ymm1, %ymm2
+
+vfmsubadd231ps %xmm0, %xmm1, %xmm2
+vfmsubadd231ps (%rax), %xmm1, %xmm2
+
+vfmsubadd231ps %ymm0, %ymm1, %ymm2
+vfmsubadd231ps (%rax), %ymm1, %ymm2
+
+vfnmadd132pd %xmm0, %xmm1, %xmm2
+vfnmadd132pd (%rax), %xmm1, %xmm2
+
+vfnmadd132pd %ymm0, %ymm1, %ymm2
+vfnmadd132pd (%rax), %ymm1, %ymm2
+
+vfnmadd213pd %xmm0, %xmm1, %xmm2
+vfnmadd213pd (%rax), %xmm1, %xmm2
+
+vfnmadd213pd %ymm0, %ymm1, %ymm2
+vfnmadd213pd (%rax), %ymm1, %ymm2
+
+vfnmadd231pd %xmm0, %xmm1, %xmm2
+vfnmadd231pd (%rax), %xmm1, %xmm2
+
+vfnmadd231pd %ymm0, %ymm1, %ymm2
+vfnmadd231pd (%rax), %ymm1, %ymm2
+
+vfnmadd132ps %xmm0, %xmm1, %xmm2
+vfnmadd132ps (%rax), %xmm1, %xmm2
+
+vfnmadd132ps %ymm0, %ymm1, %ymm2
+vfnmadd132ps (%rax), %ymm1, %ymm2
+
+vfnmadd213ps %xmm0, %xmm1, %xmm2
+vfnmadd213ps (%rax), %xmm1, %xmm2
+
+vfnmadd213ps %ymm0, %ymm1, %ymm2
+vfnmadd213ps (%rax), %ymm1, %ymm2
+
+vfnmadd231ps %xmm0, %xmm1, %xmm2
+vfnmadd231ps (%rax), %xmm1, %xmm2
+
+vfnmadd231ps %ymm0, %ymm1, %ymm2
+vfnmadd231ps (%rax), %ymm1, %ymm2
+
+vfnmadd132sd %xmm0, %xmm1, %xmm2
+vfnmadd132sd (%rax), %xmm1, %xmm2
+
+vfnmadd213sd %xmm0, %xmm1, %xmm2
+vfnmadd213sd (%rax), %xmm1, %xmm2
+
+vfnmadd231sd %xmm0, %xmm1, %xmm2
+vfnmadd231sd (%rax), %xmm1, %xmm2
+
+vfnmadd132ss %xmm0, %xmm1, %xmm2
+vfnmadd132ss (%rax), %xmm1, %xmm2
+
+vfnmadd213ss %xmm0, %xmm1, %xmm2
+vfnmadd213ss (%rax), %xmm1, %xmm2
+
+vfnmadd231ss %xmm0, %xmm1, %xmm2
+vfnmadd231ss (%rax), %xmm1, %xmm2
+
+vfnmsub132pd %xmm0, %xmm1, %xmm2
+vfnmsub132pd (%rax), %xmm1, %xmm2
+
+vfnmsub132pd %ymm0, %ymm1, %ymm2
+vfnmsub132pd (%rax), %ymm1, %ymm2
+
+vfnmsub213pd %xmm0, %xmm1, %xmm2
+vfnmsub213pd (%rax), %xmm1, %xmm2
+
+vfnmsub213pd %ymm0, %ymm1, %ymm2
+vfnmsub213pd (%rax), %ymm1, %ymm2
+
+vfnmsub231pd %xmm0, %xmm1, %xmm2
+vfnmsub231pd (%rax), %xmm1, %xmm2
+
+vfnmsub231pd %ymm0, %ymm1, %ymm2
+vfnmsub231pd (%rax), %ymm1, %ymm2
+
+vfnmsub132ps %xmm0, %xmm1, %xmm2
+vfnmsub132ps (%rax), %xmm1, %xmm2
+
+vfnmsub132ps %ymm0, %ymm1, %ymm2
+vfnmsub132ps (%rax), %ymm1, %ymm2
+
+vfnmsub213ps %xmm0, %xmm1, %xmm2
+vfnmsub213ps (%rax), %xmm1, %xmm2
+
+vfnmsub213ps %ymm0, %ymm1, %ymm2
+vfnmsub213ps (%rax), %ymm1, %ymm2
+
+vfnmsub231ps %xmm0, %xmm1, %xmm2
+vfnmsub231ps (%rax), %xmm1, %xmm2
+
+vfnmsub231ps %ymm0, %ymm1, %ymm2
+vfnmsub231ps (%rax), %ymm1, %ymm2
+
+vfnmsub132sd %xmm0, %xmm1, %xmm2
+vfnmsub132sd (%rax), %xmm1, %xmm2
+
+vfnmsub213sd %xmm0, %xmm1, %xmm2
+vfnmsub213sd (%rax), %xmm1, %xmm2
+
+vfnmsub231sd %xmm0, %xmm1, %xmm2
+vfnmsub231sd (%rax), %xmm1, %xmm2
+
+vfnmsub132ss %xmm0, %xmm1, %xmm2
+vfnmsub132ss (%rax), %xmm1, %xmm2
+
+vfnmsub213ss %xmm0, %xmm1, %xmm2
+vfnmsub213ss (%rax), %xmm1, %xmm2
+
+vfnmsub231ss %xmm0, %xmm1, %xmm2
+vfnmsub231ss (%rax), %xmm1, %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 5 0.50 vfmadd132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmadd132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfmadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfmadd213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmadd213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfmadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfmadd231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmadd231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfmadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfmadd132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmadd132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfmadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfmadd213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmadd213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfmadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfmadd231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmadd231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfmadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfmadd132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmadd132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmadd213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmadd213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmadd231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmadd231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmadd132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmadd132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmadd213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmadd213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmadd231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmadd231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmaddsub132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmaddsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmaddsub132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfmaddsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfmaddsub213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmaddsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmaddsub213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfmaddsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfmaddsub231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmaddsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmaddsub231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfmaddsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfmaddsub132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmaddsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmaddsub132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfmaddsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfmaddsub213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmaddsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmaddsub213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfmaddsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfmaddsub231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmaddsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmaddsub231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfmaddsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfmsub132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmsub132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfmsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfmsub213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmsub213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfmsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfmsub231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmsub231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfmsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfmsub132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmsub132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfmsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfmsub213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmsub213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfmsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfmsub231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmsub231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfmsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfmsub132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmsub132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmsub213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmsub213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmsub231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmsub231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmsub132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmsub132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmsub213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmsub213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmsub231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmsub231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmsubadd132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmsubadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmsubadd132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfmsubadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfmsubadd213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmsubadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmsubadd213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfmsubadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfmsubadd231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmsubadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmsubadd231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfmsubadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfmsubadd132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmsubadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmsubadd132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfmsubadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfmsubadd213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmsubadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmsubadd213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfmsubadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfmsubadd231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfmsubadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfmsubadd231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfmsubadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfnmadd132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfnmadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfnmadd132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfnmadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfnmadd213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfnmadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfnmadd213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfnmadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfnmadd231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfnmadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfnmadd231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfnmadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfnmadd132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfnmadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfnmadd132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfnmadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfnmadd213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfnmadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfnmadd213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfnmadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfnmadd231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfnmadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfnmadd231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfnmadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfnmadd132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfnmadd132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfnmadd213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfnmadd213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfnmadd231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfnmadd231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfnmadd132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfnmadd132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfnmadd213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfnmadd213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfnmadd231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfnmadd231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfnmsub132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfnmsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfnmsub132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfnmsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfnmsub213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfnmsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfnmsub213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfnmsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfnmsub231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfnmsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfnmsub231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfnmsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfnmsub132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfnmsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfnmsub132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfnmsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfnmsub213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfnmsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfnmsub213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfnmsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfnmsub231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfnmsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfnmsub231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 12 0.50 * vfnmsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 5 0.50 vfnmsub132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfnmsub132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfnmsub213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfnmsub213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfnmsub231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfnmsub231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfnmsub132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfnmsub132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfnmsub213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfnmsub213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 0.50 vfnmsub231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 0.50 * vfnmsub231ss (%rax), %xmm1, %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: 32.00 32.00 32.00 - - - - 96.00 - 96.00 - 32.00 32.00 32.00 48.00 48.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmadd132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmadd132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmadd213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmadd213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmadd231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmadd231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmadd132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmadd132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmadd213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmadd213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmadd231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmadd231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmadd132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmadd132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmadd213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmadd213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmadd231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmadd231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmadd132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmadd132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmadd213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmadd213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmadd231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmadd231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmaddsub132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmaddsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmaddsub132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmaddsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmaddsub213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmaddsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmaddsub213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmaddsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmaddsub231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmaddsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmaddsub231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmaddsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmaddsub132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmaddsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmaddsub132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmaddsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmaddsub213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmaddsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmaddsub213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmaddsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmaddsub231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmaddsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmaddsub231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmaddsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmsub132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmsub132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmsub213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmsub213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmsub231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmsub231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmsub132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmsub132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmsub213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmsub213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmsub231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmsub231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmsub132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmsub132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmsub213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmsub213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmsub231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmsub231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmsub132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmsub132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmsub213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmsub213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmsub231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmsub231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmsubadd132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmsubadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmsubadd132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmsubadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmsubadd213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmsubadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmsubadd213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmsubadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmsubadd231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmsubadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmsubadd231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmsubadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmsubadd132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmsubadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmsubadd132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmsubadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmsubadd213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmsubadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmsubadd213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmsubadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmsubadd231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmsubadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfmsubadd231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfmsubadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmadd132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmadd132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmadd213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmadd213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmadd231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmadd231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmadd132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmadd132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmadd213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmadd213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmadd231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmadd231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmadd132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmadd132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmadd213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmadd213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmadd231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmadd231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmadd132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmadd132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmadd213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmadd213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmadd231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmadd231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmsub132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmsub132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmsub213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmsub213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmsub231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmsub231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmsub132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmsub132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmsub213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmsub213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmsub231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmsub231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmsub132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmsub132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmsub213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmsub213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmsub231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmsub231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmsub132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmsub132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmsub213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmsub213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - vfnmsub231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - vfnmsub231ss (%rax), %xmm1, %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-fsgsbase.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-fsgsbase.s
new file mode 100644
index 0000000000000..2081e76900ad2
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-fsgsbase.s
@@ -0,0 +1,68 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+rdfsbase %eax
+rdfsbase %rax
+
+rdgsbase %eax
+rdgsbase %rax
+
+wrfsbase %edi
+wrfsbase %rdi
+
+wrgsbase %edi
+wrgsbase %rdi
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 100 0.25 * * U rdfsbasel %eax
+# CHECK-NEXT: 1 100 0.25 * * U rdfsbaseq %rax
+# CHECK-NEXT: 1 100 0.25 * * U rdgsbasel %eax
+# CHECK-NEXT: 1 100 0.25 * * U rdgsbaseq %rax
+# CHECK-NEXT: 1 100 0.25 * * U wrfsbasel %edi
+# CHECK-NEXT: 1 100 0.25 * * U wrfsbaseq %rdi
+# CHECK-NEXT: 1 100 0.25 * * U wrgsbasel %edi
+# CHECK-NEXT: 1 100 0.25 * * U wrgsbaseq %rdi
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - rdfsbasel %eax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - rdfsbaseq %rax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - rdgsbasel %eax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - rdgsbaseq %rax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - wrfsbasel %edi
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - wrfsbaseq %rdi
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - wrgsbasel %edi
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - wrgsbaseq %rdi
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-lea.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-lea.s
new file mode 100644
index 0000000000000..1d107c38784e8
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-lea.s
@@ -0,0 +1,448 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+lea 0(), %cx
+lea 0(), %ecx
+lea 0(), %rcx
+lea (%eax), %cx
+lea (%eax), %ecx
+lea (%eax), %rcx
+lea (%rax), %cx
+lea (%rax), %ecx
+lea (%rax), %rcx
+lea (, %ebx), %cx
+lea (, %ebx), %ecx
+lea (, %ebx), %rcx
+lea (, %rbx), %cx
+lea (, %rbx), %ecx
+lea (, %rbx), %rcx
+lea (, %ebx, 1), %cx
+lea (, %ebx, 1), %ecx
+lea (, %ebx, 1), %rcx
+lea (, %rbx, 1), %cx
+lea (, %rbx, 1), %ecx
+lea (, %rbx, 1), %rcx
+lea (, %ebx, 2), %cx
+lea (, %ebx, 2), %ecx
+lea (, %ebx, 2), %rcx
+lea (, %rbx, 2), %cx
+lea (, %rbx, 2), %ecx
+lea (, %rbx, 2), %rcx
+lea (%eax, %ebx), %cx
+lea (%eax, %ebx), %ecx
+lea (%eax, %ebx), %rcx
+lea (%rax, %rbx), %cx
+lea (%rax, %rbx), %ecx
+lea (%rax, %rbx), %rcx
+lea (%eax, %ebx, 1), %cx
+lea (%eax, %ebx, 1), %ecx
+lea (%eax, %ebx, 1), %rcx
+lea (%rax, %rbx, 1), %cx
+lea (%rax, %rbx, 1), %ecx
+lea (%rax, %rbx, 1), %rcx
+lea (%eax, %ebx, 2), %cx
+lea (%eax, %ebx, 2), %ecx
+lea (%eax, %ebx, 2), %rcx
+lea (%rax, %rbx, 2), %cx
+lea (%rax, %rbx, 2), %ecx
+lea (%rax, %rbx, 2), %rcx
+
+lea -16(), %cx
+lea -16(), %ecx
+lea -16(), %rcx
+lea -16(%eax), %cx
+lea -16(%eax), %ecx
+lea -16(%eax), %rcx
+lea -16(%rax), %cx
+lea -16(%rax), %ecx
+lea -16(%rax), %rcx
+lea -16(, %ebx), %cx
+lea -16(, %ebx), %ecx
+lea -16(, %ebx), %rcx
+lea -16(, %rbx), %cx
+lea -16(, %rbx), %ecx
+lea -16(, %rbx), %rcx
+lea -16(, %ebx, 1), %cx
+lea -16(, %ebx, 1), %ecx
+lea -16(, %ebx, 1), %rcx
+lea -16(, %rbx, 1), %cx
+lea -16(, %rbx, 1), %ecx
+lea -16(, %rbx, 1), %rcx
+lea -16(, %ebx, 2), %cx
+lea -16(, %ebx, 2), %ecx
+lea -16(, %ebx, 2), %rcx
+lea -16(, %rbx, 2), %cx
+lea -16(, %rbx, 2), %ecx
+lea -16(, %rbx, 2), %rcx
+lea -16(%eax, %ebx), %cx
+lea -16(%eax, %ebx), %ecx
+lea -16(%eax, %ebx), %rcx
+lea -16(%rax, %rbx), %cx
+lea -16(%rax, %rbx), %ecx
+lea -16(%rax, %rbx), %rcx
+lea -16(%eax, %ebx, 1), %cx
+lea -16(%eax, %ebx, 1), %ecx
+lea -16(%eax, %ebx, 1), %rcx
+lea -16(%rax, %rbx, 1), %cx
+lea -16(%rax, %rbx, 1), %ecx
+lea -16(%rax, %rbx, 1), %rcx
+lea -16(%eax, %ebx, 2), %cx
+lea -16(%eax, %ebx, 2), %ecx
+lea -16(%eax, %ebx, 2), %rcx
+lea -16(%rax, %rbx, 2), %cx
+lea -16(%rax, %rbx, 2), %ecx
+lea -16(%rax, %rbx, 2), %rcx
+
+lea 1024(), %cx
+lea 1024(), %ecx
+lea 1024(), %rcx
+lea 1024(%eax), %cx
+lea 1024(%eax), %ecx
+lea 1024(%eax), %rcx
+lea 1024(%rax), %cx
+lea 1024(%rax), %ecx
+lea 1024(%rax), %rcx
+lea 1024(, %ebx), %cx
+lea 1024(, %ebx), %ecx
+lea 1024(, %ebx), %rcx
+lea 1024(, %rbx), %cx
+lea 1024(, %rbx), %ecx
+lea 1024(, %rbx), %rcx
+lea 1024(, %ebx, 1), %cx
+lea 1024(, %ebx, 1), %ecx
+lea 1024(, %ebx, 1), %rcx
+lea 1024(, %rbx, 1), %cx
+lea 1024(, %rbx, 1), %ecx
+lea 1024(, %rbx, 1), %rcx
+lea 1024(, %ebx, 2), %cx
+lea 1024(, %ebx, 2), %ecx
+lea 1024(, %ebx, 2), %rcx
+lea 1024(, %rbx, 2), %cx
+lea 1024(, %rbx, 2), %ecx
+lea 1024(, %rbx, 2), %rcx
+lea 1024(%eax, %ebx), %cx
+lea 1024(%eax, %ebx), %ecx
+lea 1024(%eax, %ebx), %rcx
+lea 1024(%rax, %rbx), %cx
+lea 1024(%rax, %rbx), %ecx
+lea 1024(%rax, %rbx), %rcx
+lea 1024(%eax, %ebx, 1), %cx
+lea 1024(%eax, %ebx, 1), %ecx
+lea 1024(%eax, %ebx, 1), %rcx
+lea 1024(%rax, %rbx, 1), %cx
+lea 1024(%rax, %rbx, 1), %ecx
+lea 1024(%rax, %rbx, 1), %rcx
+lea 1024(%eax, %ebx, 2), %cx
+lea 1024(%eax, %ebx, 2), %ecx
+lea 1024(%eax, %ebx, 2), %rcx
+lea 1024(%rax, %rbx, 2), %cx
+lea 1024(%rax, %rbx, 2), %ecx
+lea 1024(%rax, %rbx, 2), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.17 leaw 0, %cx
+# CHECK-NEXT: 1 1 0.17 leal 0, %ecx
+# CHECK-NEXT: 1 1 0.17 leaq 0, %rcx
+# CHECK-NEXT: 1 1 0.17 leaw (%eax), %cx
+# CHECK-NEXT: 1 1 0.17 leal (%eax), %ecx
+# CHECK-NEXT: 1 1 0.17 leaq (%eax), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw (%rax), %cx
+# CHECK-NEXT: 1 1 0.17 leal (%rax), %ecx
+# CHECK-NEXT: 1 1 0.17 leaq (%rax), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw (,%ebx), %cx
+# CHECK-NEXT: 1 1 0.17 leal (,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.17 leaq (,%ebx), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw (,%rbx), %cx
+# CHECK-NEXT: 1 1 0.17 leal (,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.17 leaq (,%rbx), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw (,%ebx), %cx
+# CHECK-NEXT: 1 1 0.17 leal (,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.17 leaq (,%ebx), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw (,%rbx), %cx
+# CHECK-NEXT: 1 1 0.17 leal (,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.17 leaq (,%rbx), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw (,%ebx,2), %cx
+# CHECK-NEXT: 2 2 0.50 leal (,%ebx,2), %ecx
+# CHECK-NEXT: 2 2 0.50 leaq (,%ebx,2), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw (,%rbx,2), %cx
+# CHECK-NEXT: 2 2 0.50 leal (,%rbx,2), %ecx
+# CHECK-NEXT: 2 2 0.50 leaq (,%rbx,2), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw (%eax,%ebx), %cx
+# CHECK-NEXT: 1 1 0.17 leal (%eax,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.17 leaq (%eax,%ebx), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw (%rax,%rbx), %cx
+# CHECK-NEXT: 1 1 0.17 leal (%rax,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.17 leaq (%rax,%rbx), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw (%eax,%ebx), %cx
+# CHECK-NEXT: 1 1 0.17 leal (%eax,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.17 leaq (%eax,%ebx), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw (%rax,%rbx), %cx
+# CHECK-NEXT: 1 1 0.17 leal (%rax,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.17 leaq (%rax,%rbx), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw (%eax,%ebx,2), %cx
+# CHECK-NEXT: 2 2 0.50 leal (%eax,%ebx,2), %ecx
+# CHECK-NEXT: 2 2 0.50 leaq (%eax,%ebx,2), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw (%rax,%rbx,2), %cx
+# CHECK-NEXT: 2 2 0.50 leal (%rax,%rbx,2), %ecx
+# CHECK-NEXT: 2 2 0.50 leaq (%rax,%rbx,2), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw -16, %cx
+# CHECK-NEXT: 1 1 0.17 leal -16, %ecx
+# CHECK-NEXT: 1 1 0.17 leaq -16, %rcx
+# CHECK-NEXT: 1 1 0.17 leaw -16(%eax), %cx
+# CHECK-NEXT: 1 1 0.17 leal -16(%eax), %ecx
+# CHECK-NEXT: 1 1 0.17 leaq -16(%eax), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw -16(%rax), %cx
+# CHECK-NEXT: 1 1 0.17 leal -16(%rax), %ecx
+# CHECK-NEXT: 1 1 0.17 leaq -16(%rax), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw -16(,%ebx), %cx
+# CHECK-NEXT: 1 1 0.17 leal -16(,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.17 leaq -16(,%ebx), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw -16(,%rbx), %cx
+# CHECK-NEXT: 1 1 0.17 leal -16(,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.17 leaq -16(,%rbx), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw -16(,%ebx), %cx
+# CHECK-NEXT: 1 1 0.17 leal -16(,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.17 leaq -16(,%ebx), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw -16(,%rbx), %cx
+# CHECK-NEXT: 1 1 0.17 leal -16(,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.17 leaq -16(,%rbx), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw -16(,%ebx,2), %cx
+# CHECK-NEXT: 2 2 0.50 leal -16(,%ebx,2), %ecx
+# CHECK-NEXT: 2 2 0.50 leaq -16(,%ebx,2), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw -16(,%rbx,2), %cx
+# CHECK-NEXT: 2 2 0.50 leal -16(,%rbx,2), %ecx
+# CHECK-NEXT: 2 2 0.50 leaq -16(,%rbx,2), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw -16(%eax,%ebx), %cx
+# CHECK-NEXT: 2 2 0.50 leal -16(%eax,%ebx), %ecx
+# CHECK-NEXT: 2 2 0.50 leaq -16(%eax,%ebx), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw -16(%rax,%rbx), %cx
+# CHECK-NEXT: 2 2 0.50 leal -16(%rax,%rbx), %ecx
+# CHECK-NEXT: 2 2 0.50 leaq -16(%rax,%rbx), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw -16(%eax,%ebx), %cx
+# CHECK-NEXT: 2 2 0.50 leal -16(%eax,%ebx), %ecx
+# CHECK-NEXT: 2 2 0.50 leaq -16(%eax,%ebx), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw -16(%rax,%rbx), %cx
+# CHECK-NEXT: 2 2 0.50 leal -16(%rax,%rbx), %ecx
+# CHECK-NEXT: 2 2 0.50 leaq -16(%rax,%rbx), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw -16(%eax,%ebx,2), %cx
+# CHECK-NEXT: 2 2 0.50 leal -16(%eax,%ebx,2), %ecx
+# CHECK-NEXT: 2 2 0.50 leaq -16(%eax,%ebx,2), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw -16(%rax,%rbx,2), %cx
+# CHECK-NEXT: 2 2 0.50 leal -16(%rax,%rbx,2), %ecx
+# CHECK-NEXT: 2 2 0.50 leaq -16(%rax,%rbx,2), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw 1024, %cx
+# CHECK-NEXT: 1 1 0.17 leal 1024, %ecx
+# CHECK-NEXT: 1 1 0.17 leaq 1024, %rcx
+# CHECK-NEXT: 1 1 0.17 leaw 1024(%eax), %cx
+# CHECK-NEXT: 1 1 0.17 leal 1024(%eax), %ecx
+# CHECK-NEXT: 1 1 0.17 leaq 1024(%eax), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw 1024(%rax), %cx
+# CHECK-NEXT: 1 1 0.17 leal 1024(%rax), %ecx
+# CHECK-NEXT: 1 1 0.17 leaq 1024(%rax), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw 1024(,%ebx), %cx
+# CHECK-NEXT: 1 1 0.17 leal 1024(,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.17 leaq 1024(,%ebx), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw 1024(,%rbx), %cx
+# CHECK-NEXT: 1 1 0.17 leal 1024(,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.17 leaq 1024(,%rbx), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw 1024(,%ebx), %cx
+# CHECK-NEXT: 1 1 0.17 leal 1024(,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.17 leaq 1024(,%ebx), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw 1024(,%rbx), %cx
+# CHECK-NEXT: 1 1 0.17 leal 1024(,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.17 leaq 1024(,%rbx), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw 1024(,%ebx,2), %cx
+# CHECK-NEXT: 2 2 0.50 leal 1024(,%ebx,2), %ecx
+# CHECK-NEXT: 2 2 0.50 leaq 1024(,%ebx,2), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw 1024(,%rbx,2), %cx
+# CHECK-NEXT: 2 2 0.50 leal 1024(,%rbx,2), %ecx
+# CHECK-NEXT: 2 2 0.50 leaq 1024(,%rbx,2), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw 1024(%eax,%ebx), %cx
+# CHECK-NEXT: 2 2 0.50 leal 1024(%eax,%ebx), %ecx
+# CHECK-NEXT: 2 2 0.50 leaq 1024(%eax,%ebx), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw 1024(%rax,%rbx), %cx
+# CHECK-NEXT: 2 2 0.50 leal 1024(%rax,%rbx), %ecx
+# CHECK-NEXT: 2 2 0.50 leaq 1024(%rax,%rbx), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw 1024(%eax,%ebx), %cx
+# CHECK-NEXT: 2 2 0.50 leal 1024(%eax,%ebx), %ecx
+# CHECK-NEXT: 2 2 0.50 leaq 1024(%eax,%ebx), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw 1024(%rax,%rbx), %cx
+# CHECK-NEXT: 2 2 0.50 leal 1024(%rax,%rbx), %ecx
+# CHECK-NEXT: 2 2 0.50 leaq 1024(%rax,%rbx), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw 1024(%eax,%ebx,2), %cx
+# CHECK-NEXT: 2 2 0.50 leal 1024(%eax,%ebx,2), %ecx
+# CHECK-NEXT: 2 2 0.50 leaq 1024(%eax,%ebx,2), %rcx
+# CHECK-NEXT: 1 1 0.17 leaw 1024(%rax,%rbx,2), %cx
+# CHECK-NEXT: 2 2 0.50 leal 1024(%rax,%rbx,2), %ecx
+# CHECK-NEXT: 2 2 0.50 leaq 1024(%rax,%rbx,2), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: - - - 31.67 15.83 35.83 51.67 - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw 0, %cx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leal 0, %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaq 0, %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw (%eax), %cx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leal (%eax), %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaq (%eax), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw (%rax), %cx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leal (%rax), %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaq (%rax), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw (,%ebx), %cx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leal (,%ebx), %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaq (,%ebx), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw (,%rbx), %cx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leal (,%rbx), %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaq (,%rbx), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw (,%ebx), %cx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leal (,%ebx), %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaq (,%ebx), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw (,%rbx), %cx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leal (,%rbx), %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaq (,%rbx), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw (,%ebx,2), %cx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leal (,%ebx,2), %ecx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leaq (,%ebx,2), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw (,%rbx,2), %cx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leal (,%rbx,2), %ecx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leaq (,%rbx,2), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw (%eax,%ebx), %cx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leal (%eax,%ebx), %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaq (%eax,%ebx), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw (%rax,%rbx), %cx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leal (%rax,%rbx), %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaq (%rax,%rbx), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw (%eax,%ebx), %cx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leal (%eax,%ebx), %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaq (%eax,%ebx), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw (%rax,%rbx), %cx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leal (%rax,%rbx), %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaq (%rax,%rbx), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw (%eax,%ebx,2), %cx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leal (%eax,%ebx,2), %ecx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leaq (%eax,%ebx,2), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw (%rax,%rbx,2), %cx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leal (%rax,%rbx,2), %ecx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leaq (%rax,%rbx,2), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw -16, %cx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leal -16, %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaq -16, %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw -16(%eax), %cx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leal -16(%eax), %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaq -16(%eax), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw -16(%rax), %cx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leal -16(%rax), %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaq -16(%rax), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw -16(,%ebx), %cx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leal -16(,%ebx), %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaq -16(,%ebx), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw -16(,%rbx), %cx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leal -16(,%rbx), %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaq -16(,%rbx), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw -16(,%ebx), %cx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leal -16(,%ebx), %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaq -16(,%ebx), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw -16(,%rbx), %cx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leal -16(,%rbx), %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaq -16(,%rbx), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw -16(,%ebx,2), %cx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leal -16(,%ebx,2), %ecx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leaq -16(,%ebx,2), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw -16(,%rbx,2), %cx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leal -16(,%rbx,2), %ecx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leaq -16(,%rbx,2), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw -16(%eax,%ebx), %cx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leal -16(%eax,%ebx), %ecx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leaq -16(%eax,%ebx), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw -16(%rax,%rbx), %cx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leal -16(%rax,%rbx), %ecx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leaq -16(%rax,%rbx), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw -16(%eax,%ebx), %cx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leal -16(%eax,%ebx), %ecx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leaq -16(%eax,%ebx), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw -16(%rax,%rbx), %cx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leal -16(%rax,%rbx), %ecx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leaq -16(%rax,%rbx), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw -16(%eax,%ebx,2), %cx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leal -16(%eax,%ebx,2), %ecx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leaq -16(%eax,%ebx,2), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw -16(%rax,%rbx,2), %cx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leal -16(%rax,%rbx,2), %ecx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leaq -16(%rax,%rbx,2), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw 1024, %cx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leal 1024, %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaq 1024, %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw 1024(%eax), %cx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leal 1024(%eax), %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaq 1024(%eax), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw 1024(%rax), %cx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leal 1024(%rax), %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaq 1024(%rax), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw 1024(,%ebx), %cx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leal 1024(,%ebx), %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaq 1024(,%ebx), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw 1024(,%rbx), %cx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leal 1024(,%rbx), %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaq 1024(,%rbx), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw 1024(,%ebx), %cx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leal 1024(,%ebx), %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaq 1024(,%ebx), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw 1024(,%rbx), %cx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leal 1024(,%rbx), %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaq 1024(,%rbx), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw 1024(,%ebx,2), %cx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leal 1024(,%ebx,2), %ecx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leaq 1024(,%ebx,2), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw 1024(,%rbx,2), %cx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leal 1024(,%rbx,2), %ecx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leaq 1024(,%rbx,2), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw 1024(%eax,%ebx), %cx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leal 1024(%eax,%ebx), %ecx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leaq 1024(%eax,%ebx), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw 1024(%rax,%rbx), %cx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leal 1024(%rax,%rbx), %ecx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leaq 1024(%rax,%rbx), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw 1024(%eax,%ebx), %cx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leal 1024(%eax,%ebx), %ecx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leaq 1024(%eax,%ebx), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw 1024(%rax,%rbx), %cx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leal 1024(%rax,%rbx), %ecx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leaq 1024(%rax,%rbx), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw 1024(%eax,%ebx,2), %cx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leal 1024(%eax,%ebx,2), %ecx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leaq 1024(%eax,%ebx,2), %rcx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leaw 1024(%rax,%rbx,2), %cx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leal 1024(%rax,%rbx,2), %ecx
+# CHECK-NEXT: - - - - - 0.50 0.50 - - - - - - - - - - - - leaq 1024(%rax,%rbx,2), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-lzcnt.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-lzcnt.s
new file mode 100644
index 0000000000000..6477fc7c1a809
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-lzcnt.s
@@ -0,0 +1,61 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+lzcntw %cx, %cx
+lzcntw (%rax), %cx
+
+lzcntl %eax, %ecx
+lzcntl (%rax), %ecx
+
+lzcntq %rax, %rcx
+lzcntq (%rax), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.17 lzcntw %cx, %cx
+# CHECK-NEXT: 1 5 0.50 * lzcntw (%rax), %cx
+# CHECK-NEXT: 1 1 0.17 lzcntl %eax, %ecx
+# CHECK-NEXT: 1 5 0.50 * lzcntl (%rax), %ecx
+# CHECK-NEXT: 1 1 0.17 lzcntq %rax, %rcx
+# CHECK-NEXT: 1 5 0.50 * lzcntq (%rax), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: 1.00 1.00 1.00 2.00 1.00 1.00 2.00 - - - - 1.00 1.00 1.00 1.50 1.50 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - lzcntw %cx, %cx
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - lzcntw (%rax), %cx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - lzcntl %eax, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - lzcntl (%rax), %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - lzcntq %rax, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - lzcntq (%rax), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-mmx.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-mmx.s
new file mode 100644
index 0000000000000..b28973e12b598
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-mmx.s
@@ -0,0 +1,404 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+emms
+
+movd %eax, %mm2
+movd (%rax), %mm2
+
+movd %mm0, %ecx
+movd %mm0, (%rax)
+
+movq %rax, %mm2
+movq (%rax), %mm2
+
+movq %mm0, %rcx
+movq %mm0, (%rax)
+
+packsswb %mm0, %mm2
+packsswb (%rax), %mm2
+
+packssdw %mm0, %mm2
+packssdw (%rax), %mm2
+
+packuswb %mm0, %mm2
+packuswb (%rax), %mm2
+
+paddb %mm0, %mm2
+paddb (%rax), %mm2
+
+paddd %mm0, %mm2
+paddd (%rax), %mm2
+
+paddsb %mm0, %mm2
+paddsb (%rax), %mm2
+
+paddsw %mm0, %mm2
+paddsw (%rax), %mm2
+
+paddusb %mm0, %mm2
+paddusb (%rax), %mm2
+
+paddusw %mm0, %mm2
+paddusw (%rax), %mm2
+
+paddw %mm0, %mm2
+paddw (%rax), %mm2
+
+pand %mm0, %mm2
+pand (%rax), %mm2
+
+pandn %mm0, %mm2
+pandn (%rax), %mm2
+
+pcmpeqb %mm0, %mm2
+pcmpeqb (%rax), %mm2
+
+pcmpeqd %mm0, %mm2
+pcmpeqd (%rax), %mm2
+
+pcmpeqw %mm0, %mm2
+pcmpeqw (%rax), %mm2
+
+pcmpgtb %mm0, %mm2
+pcmpgtb (%rax), %mm2
+
+pcmpgtd %mm0, %mm2
+pcmpgtd (%rax), %mm2
+
+pcmpgtw %mm0, %mm2
+pcmpgtw (%rax), %mm2
+
+pmaddwd %mm0, %mm2
+pmaddwd (%rax), %mm2
+
+pmulhw %mm0, %mm2
+pmulhw (%rax), %mm2
+
+pmullw %mm0, %mm2
+pmullw (%rax), %mm2
+
+por %mm0, %mm2
+por (%rax), %mm2
+
+pslld $1, %mm2
+pslld %mm0, %mm2
+pslld (%rax), %mm2
+
+psllq $1, %mm2
+psllq %mm0, %mm2
+psllq (%rax), %mm2
+
+psllw $1, %mm2
+psllw %mm0, %mm2
+psllw (%rax), %mm2
+
+psrad $1, %mm2
+psrad %mm0, %mm2
+psrad (%rax), %mm2
+
+psraw $1, %mm2
+psraw %mm0, %mm2
+psraw (%rax), %mm2
+
+psrld $1, %mm2
+psrld %mm0, %mm2
+psrld (%rax), %mm2
+
+psrlq $1, %mm2
+psrlq %mm0, %mm2
+psrlq (%rax), %mm2
+
+psrlw $1, %mm2
+psrlw %mm0, %mm2
+psrlw (%rax), %mm2
+
+psubb %mm0, %mm2
+psubb (%rax), %mm2
+
+psubd %mm0, %mm2
+psubd (%rax), %mm2
+
+psubsb %mm0, %mm2
+psubsb (%rax), %mm2
+
+psubsw %mm0, %mm2
+psubsw (%rax), %mm2
+
+psubusb %mm0, %mm2
+psubusb (%rax), %mm2
+
+psubusw %mm0, %mm2
+psubusw (%rax), %mm2
+
+psubw %mm0, %mm2
+psubw (%rax), %mm2
+
+punpckhbw %mm0, %mm2
+punpckhbw (%rax), %mm2
+
+punpckhdq %mm0, %mm2
+punpckhdq (%rax), %mm2
+
+punpckhwd %mm0, %mm2
+punpckhwd (%rax), %mm2
+
+punpcklbw %mm0, %mm2
+punpcklbw (%rax), %mm2
+
+punpckldq %mm0, %mm2
+punpckldq (%rax), %mm2
+
+punpcklwd %mm0, %mm2
+punpcklwd (%rax), %mm2
+
+pxor %mm0, %mm2
+pxor (%rax), %mm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 0 0.25 * * U emms
+# CHECK-NEXT: 1 1 1.00 movd %eax, %mm2
+# CHECK-NEXT: 1 8 0.50 * movd (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 movd %mm0, %ecx
+# CHECK-NEXT: 1 1 0.33 * U movd %mm0, (%rax)
+# CHECK-NEXT: 1 1 1.00 movq %rax, %mm2
+# CHECK-NEXT: 1 8 0.50 * movq (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 movq %mm0, %rcx
+# CHECK-NEXT: 1 1 0.33 * movq %mm0, (%rax)
+# CHECK-NEXT: 1 1 0.50 packsswb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * packsswb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 packssdw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * packssdw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 packuswb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * packuswb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 paddb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * paddb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 paddd %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * paddd (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 paddsb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * paddsb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 paddsw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * paddsw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 paddusb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * paddusb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 paddusw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * paddusw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 paddw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * paddw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pand %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pand (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pandn %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pandn (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pcmpeqb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pcmpeqb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pcmpeqd %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pcmpeqd (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pcmpeqw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pcmpeqw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pcmpgtb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtd %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pcmpgtd (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pcmpgtw (%rax), %mm2
+# CHECK-NEXT: 1 3 1.00 pmaddwd %mm0, %mm2
+# CHECK-NEXT: 1 10 1.00 * pmaddwd (%rax), %mm2
+# CHECK-NEXT: 1 3 1.00 pmulhw %mm0, %mm2
+# CHECK-NEXT: 1 10 1.00 * pmulhw (%rax), %mm2
+# CHECK-NEXT: 1 3 1.00 pmullw %mm0, %mm2
+# CHECK-NEXT: 1 10 1.00 * pmullw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 por %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * por (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 pslld $1, %mm2
+# CHECK-NEXT: 1 1 1.00 pslld %mm0, %mm2
+# CHECK-NEXT: 1 8 1.00 * pslld (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 psllq $1, %mm2
+# CHECK-NEXT: 1 1 1.00 psllq %mm0, %mm2
+# CHECK-NEXT: 1 8 1.00 * psllq (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 psllw $1, %mm2
+# CHECK-NEXT: 1 1 1.00 psllw %mm0, %mm2
+# CHECK-NEXT: 1 8 1.00 * psllw (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 psrad $1, %mm2
+# CHECK-NEXT: 1 1 1.00 psrad %mm0, %mm2
+# CHECK-NEXT: 1 8 1.00 * psrad (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 psraw $1, %mm2
+# CHECK-NEXT: 1 1 1.00 psraw %mm0, %mm2
+# CHECK-NEXT: 1 8 1.00 * psraw (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 psrld $1, %mm2
+# CHECK-NEXT: 1 1 1.00 psrld %mm0, %mm2
+# CHECK-NEXT: 1 8 1.00 * psrld (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 psrlq $1, %mm2
+# CHECK-NEXT: 1 1 1.00 psrlq %mm0, %mm2
+# CHECK-NEXT: 1 8 1.00 * psrlq (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 psrlw $1, %mm2
+# CHECK-NEXT: 1 1 1.00 psrlw %mm0, %mm2
+# CHECK-NEXT: 1 8 1.00 * psrlw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 psubb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psubb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 psubd %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psubd (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 psubsb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psubsb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 psubsw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psubsw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 psubusb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psubusb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 psubusw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psubusw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 psubw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psubw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 punpckhbw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * punpckhbw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 punpckhdq %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * punpckhdq (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 punpckhwd %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * punpckhwd (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 punpcklbw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * punpcklbw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 punpckldq %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * punpckldq (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 punpcklwd %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * punpcklwd (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pxor %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pxor (%rax), %mm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: 16.00 16.00 16.00 - - - - 27.25 49.25 12.25 12.25 16.00 16.00 16.00 23.00 23.00 0.67 0.67 0.67
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - emms
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - movd %eax, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - movd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - movd %mm0, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 movd %mm0, (%rax)
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - movq %rax, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - movq (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - movq %mm0, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 movq %mm0, (%rax)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - packsswb %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - packsswb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - packssdw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - packssdw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - packuswb %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - packuswb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - paddb %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - paddb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - paddd %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - paddd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - paddsb %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - paddsb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - paddsw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - paddsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - paddusb %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - paddusb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - paddusw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - paddusw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - paddw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - paddw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pand %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pand (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pandn %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pandn (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pcmpeqb %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pcmpeqb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pcmpeqd %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pcmpeqd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pcmpeqw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pcmpeqw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pcmpgtb %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pcmpgtb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pcmpgtd %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pcmpgtd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pcmpgtw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pcmpgtw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - pmaddwd %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - pmaddwd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - pmulhw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - pmulhw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - pmullw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - pmullw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - por %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - por (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - pslld $1, %mm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - pslld %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - pslld (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - psllq $1, %mm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - psllq %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - psllq (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - psllw $1, %mm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - psllw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - psllw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - psrad $1, %mm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - psrad %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - psrad (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - psraw $1, %mm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - psraw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - psraw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - psrld $1, %mm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - psrld %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - psrld (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - psrlq $1, %mm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - psrlq %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - psrlq (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - psrlw $1, %mm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - psrlw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - psrlw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - psubb %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - psubb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - psubd %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - psubd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - psubsb %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - psubsb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - psubsw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - psubsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - psubusb %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - psubusb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - psubusw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - psubusw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - psubw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - psubw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - punpckhbw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - punpckhbw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - punpckhdq %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - punpckhdq (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - punpckhwd %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - punpckhwd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - punpcklbw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - punpcklbw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - punpckldq %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - punpckldq (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - punpcklwd %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - punpcklwd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pxor %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pxor (%rax), %mm2
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-movbe.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-movbe.s
new file mode 100644
index 0000000000000..3cdc93d6cb4a2
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-movbe.s
@@ -0,0 +1,61 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+movbe %cx, (%rax)
+movbe (%rax), %cx
+
+movbe %ecx, (%rax)
+movbe (%rax), %ecx
+
+movbe %rcx, (%rax)
+movbe (%rax), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.33 * movbew %cx, (%rax)
+# CHECK-NEXT: 1 5 0.50 * movbew (%rax), %cx
+# CHECK-NEXT: 1 1 0.33 * movbel %ecx, (%rax)
+# CHECK-NEXT: 1 5 0.50 * movbel (%rax), %ecx
+# CHECK-NEXT: 1 1 0.33 * movbeq %rcx, (%rax)
+# CHECK-NEXT: 1 5 0.50 * movbeq (%rax), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: 2.00 2.00 2.00 1.00 0.50 0.50 1.00 - - - - 2.00 2.00 2.00 1.50 1.50 1.00 1.00 1.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 movbew %cx, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - movbew (%rax), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 movbel %ecx, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - movbel (%rax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 movbeq %rcx, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - movbeq (%rax), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-mwaitx.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-mwaitx.s
new file mode 100644
index 0000000000000..e362aae6586d9
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-mwaitx.s
@@ -0,0 +1,47 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+monitorx
+mwaitx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 100 0.25 U monitorx
+# CHECK-NEXT: 1 100 0.25 U mwaitx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - monitorx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - mwaitx
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-pclmul.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-pclmul.s
new file mode 100644
index 0000000000000..2710726ce22ce
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-pclmul.s
@@ -0,0 +1,47 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+pclmulqdq $11, %xmm0, %xmm2
+pclmulqdq $11, (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 1.00 pclmulqdq $11, %xmm0, %xmm2
+# CHECK-NEXT: 1 10 1.00 * pclmulqdq $11, (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - 2.00 0.33 0.33 0.33 0.50 0.50 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - pclmulqdq $11, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - 1.00 0.33 0.33 0.33 0.50 0.50 - - - pclmulqdq $11, (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-popcnt.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-popcnt.s
new file mode 100644
index 0000000000000..73d184b8e2b90
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-popcnt.s
@@ -0,0 +1,61 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+popcntw %cx, %cx
+popcntw (%rax), %cx
+
+popcntl %eax, %ecx
+popcntl (%rax), %ecx
+
+popcntq %rax, %rcx
+popcntq (%rax), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.17 popcntw %cx, %cx
+# CHECK-NEXT: 5 5 0.33 * popcntw (%rax), %cx
+# CHECK-NEXT: 1 1 0.17 popcntl %eax, %ecx
+# CHECK-NEXT: 5 5 0.33 * popcntl (%rax), %ecx
+# CHECK-NEXT: 1 1 0.17 popcntq %rax, %rcx
+# CHECK-NEXT: 5 5 0.33 * popcntq (%rax), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: 1.00 1.00 1.00 2.00 1.00 1.00 2.00 - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - popcntw %cx, %cx
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - - - - - - - - - popcntw (%rax), %cx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - popcntl %eax, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - - - - - - - - - popcntl (%rax), %ecx
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - popcntq %rax, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - - - - - - - - - popcntq (%rax), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-prefetchw.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-prefetchw.s
new file mode 100644
index 0000000000000..6304f7d3ec5cb
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-prefetchw.s
@@ -0,0 +1,47 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+prefetch (%rax)
+prefetchw (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 5 0.50 * * prefetch (%rax)
+# CHECK-NEXT: 1 5 0.50 * * prefetchw (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: 0.67 0.67 0.67 - - - - - - - - 0.67 0.67 0.67 1.00 1.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - prefetch (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - prefetchw (%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-rdrand.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-rdrand.s
new file mode 100644
index 0000000000000..9a1515bf77083
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-rdrand.s
@@ -0,0 +1,50 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+rdrand %ax
+rdrand %eax
+rdrand %rax
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 100 0.25 U rdrandw %ax
+# CHECK-NEXT: 1 100 0.25 U rdrandl %eax
+# CHECK-NEXT: 1 100 0.25 U rdrandq %rax
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - rdrandw %ax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - rdrandl %eax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - rdrandq %rax
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-rdseed.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-rdseed.s
new file mode 100644
index 0000000000000..8761f20a3545b
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-rdseed.s
@@ -0,0 +1,50 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+rdseed %ax
+rdseed %eax
+rdseed %rax
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 100 0.25 U rdseedw %ax
+# CHECK-NEXT: 1 100 0.25 U rdseedl %eax
+# CHECK-NEXT: 1 100 0.25 U rdseedq %rax
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - rdseedw %ax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - rdseedl %eax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - rdseedq %rax
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-sha.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-sha.s
new file mode 100644
index 0000000000000..b026d9f733c7e
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-sha.s
@@ -0,0 +1,89 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+sha1msg1 %xmm0, %xmm2
+sha1msg1 (%rax), %xmm2
+
+sha1msg2 %xmm0, %xmm2
+sha1msg2 (%rax), %xmm2
+
+sha1nexte %xmm0, %xmm2
+sha1nexte (%rax), %xmm2
+
+sha1rnds4 $3, %xmm0, %xmm2
+sha1rnds4 $3, (%rax), %xmm2
+
+sha256msg1 %xmm0, %xmm2
+sha256msg1 (%rax), %xmm2
+
+sha256msg2 %xmm0, %xmm2
+sha256msg2 (%rax), %xmm2
+
+sha256rnds2 %xmm0, %xmm2
+sha256rnds2 (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 sha1msg1 %xmm0, %xmm2
+# CHECK-NEXT: 1 8 1.00 * sha1msg1 (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 sha1msg2 %xmm0, %xmm2
+# CHECK-NEXT: 1 8 1.00 * sha1msg2 (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 sha1nexte %xmm0, %xmm2
+# CHECK-NEXT: 1 8 1.00 * sha1nexte (%rax), %xmm2
+# CHECK-NEXT: 1 6 1.00 sha1rnds4 $3, %xmm0, %xmm2
+# CHECK-NEXT: 1 13 1.00 * sha1rnds4 $3, (%rax), %xmm2
+# CHECK-NEXT: 1 2 1.00 sha256msg1 %xmm0, %xmm2
+# CHECK-NEXT: 1 9 1.00 * sha256msg1 (%rax), %xmm2
+# CHECK-NEXT: 1 4 1.00 sha256msg2 %xmm0, %xmm2
+# CHECK-NEXT: 1 11 1.00 * sha256msg2 (%rax), %xmm2
+# CHECK-NEXT: 1 4 1.00 sha256rnds2 %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: 1 11 1.00 * sha256rnds2 %xmm0, (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: 2.33 2.33 2.33 - - - - - - 14.00 - 2.33 2.33 2.33 3.50 3.50 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - sha1msg1 %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 0.33 0.33 0.33 0.50 0.50 - - - sha1msg1 (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - sha1msg2 %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 0.33 0.33 0.33 0.50 0.50 - - - sha1msg2 (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - sha1nexte %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 0.33 0.33 0.33 0.50 0.50 - - - sha1nexte (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - sha1rnds4 $3, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 0.33 0.33 0.33 0.50 0.50 - - - sha1rnds4 $3, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - sha256msg1 %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 0.33 0.33 0.33 0.50 0.50 - - - sha256msg1 (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - sha256msg2 %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 0.33 0.33 0.33 0.50 0.50 - - - sha256msg2 (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - sha256rnds2 %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 0.33 0.33 0.33 0.50 0.50 - - - sha256rnds2 %xmm0, (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse1.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse1.s
new file mode 100644
index 0000000000000..0f141a305d666
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse1.s
@@ -0,0 +1,472 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+addps %xmm0, %xmm2
+addps (%rax), %xmm2
+
+addss %xmm0, %xmm2
+addss (%rax), %xmm2
+
+andnps %xmm0, %xmm2
+andnps (%rax), %xmm2
+
+andps %xmm0, %xmm2
+andps (%rax), %xmm2
+
+cmpps $0, %xmm0, %xmm2
+cmpps $0, (%rax), %xmm2
+
+cmpss $0, %xmm0, %xmm2
+cmpss $0, (%rax), %xmm2
+
+comiss %xmm0, %xmm1
+comiss (%rax), %xmm1
+
+cvtpi2ps %mm0, %xmm2
+cvtpi2ps (%rax), %xmm2
+
+cvtps2pi %xmm0, %mm2
+cvtps2pi (%rax), %mm2
+
+cvtsi2ss %ecx, %xmm2
+cvtsi2ss %rcx, %xmm2
+cvtsi2ssl (%rax), %xmm2
+cvtsi2ssq (%rax), %xmm2
+
+cvtss2si %xmm0, %ecx
+cvtss2si %xmm0, %rcx
+cvtss2si (%rax), %ecx
+cvtss2si (%rax), %rcx
+
+cvttps2pi %xmm0, %mm2
+cvttps2pi (%rax), %mm2
+
+cvttss2si %xmm0, %ecx
+cvttss2si %xmm0, %rcx
+cvttss2si (%rax), %ecx
+cvttss2si (%rax), %rcx
+
+divps %xmm0, %xmm2
+divps (%rax), %xmm2
+
+divss %xmm0, %xmm2
+divss (%rax), %xmm2
+
+ldmxcsr (%rax)
+
+maskmovq %mm0, %mm1
+
+maxps %xmm0, %xmm2
+maxps (%rax), %xmm2
+
+maxss %xmm0, %xmm2
+maxss (%rax), %xmm2
+
+minps %xmm0, %xmm2
+minps (%rax), %xmm2
+
+minss %xmm0, %xmm2
+minss (%rax), %xmm2
+
+movaps %xmm0, %xmm2
+movaps %xmm0, (%rax)
+movaps (%rax), %xmm2
+
+movhlps %xmm0, %xmm2
+movlhps %xmm0, %xmm2
+
+movhps %xmm0, (%rax)
+movhps (%rax), %xmm2
+
+movlps %xmm0, (%rax)
+movlps (%rax), %xmm2
+
+movmskps %xmm0, %rcx
+
+movntps %xmm0, (%rax)
+movntq %mm0, (%rax)
+
+movss %xmm0, %xmm2
+movss %xmm0, (%rax)
+movss (%rax), %xmm2
+
+movups %xmm0, %xmm2
+movups %xmm0, (%rax)
+movups (%rax), %xmm2
+
+mulps %xmm0, %xmm2
+mulps (%rax), %xmm2
+
+mulss %xmm0, %xmm2
+mulss (%rax), %xmm2
+
+orps %xmm0, %xmm2
+orps (%rax), %xmm2
+
+pavgb %mm0, %mm2
+pavgb (%rax), %mm2
+
+pavgw %mm0, %mm2
+pavgw (%rax), %mm2
+
+pextrw $1, %mm0, %rcx
+
+pinsrw $1, %rax, %mm2
+pinsrw $1, (%rax), %mm2
+
+pmaxsw %mm0, %mm2
+pmaxsw (%rax), %mm2
+
+pmaxub %mm0, %mm2
+pmaxub (%rax), %mm2
+
+pminsw %mm0, %mm2
+pminsw (%rax), %mm2
+
+pminub %mm0, %mm2
+pminub (%rax), %mm2
+
+pmovmskb %mm0, %rcx
+
+pmulhuw %mm0, %mm2
+pmulhuw (%rax), %mm2
+
+prefetcht0 (%rax)
+prefetcht1 (%rax)
+prefetcht2 (%rax)
+prefetchnta (%rax)
+
+psadbw %mm0, %mm2
+psadbw (%rax), %mm2
+
+pshufw $1, %mm0, %mm2
+pshufw $1, (%rax), %mm2
+
+rcpps %xmm0, %xmm2
+rcpps (%rax), %xmm2
+
+rcpss %xmm0, %xmm2
+rcpss (%rax), %xmm2
+
+rsqrtps %xmm0, %xmm2
+rsqrtps (%rax), %xmm2
+
+rsqrtss %xmm0, %xmm2
+rsqrtss (%rax), %xmm2
+
+sfence
+
+shufps $1, %xmm0, %xmm2
+shufps $1, (%rax), %xmm2
+
+sqrtps %xmm0, %xmm2
+sqrtps (%rax), %xmm2
+
+sqrtss %xmm0, %xmm2
+sqrtss (%rax), %xmm2
+
+stmxcsr (%rax)
+
+subps %xmm0, %xmm2
+subps (%rax), %xmm2
+
+subss %xmm0, %xmm2
+subss (%rax), %xmm2
+
+ucomiss %xmm0, %xmm1
+ucomiss (%rax), %xmm1
+
+unpckhps %xmm0, %xmm2
+unpckhps (%rax), %xmm2
+
+unpcklps %xmm0, %xmm2
+unpcklps (%rax), %xmm2
+
+xorps %xmm0, %xmm2
+xorps (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 addps %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * addps (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 addss %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * addss (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 andnps %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * andnps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 andps %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * andps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 cmpeqps %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * cmpeqps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 cmpeqss %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * cmpeqss (%rax), %xmm2
+# CHECK-NEXT: 1 5 1.00 comiss %xmm0, %xmm1
+# CHECK-NEXT: 1 12 1.00 * comiss (%rax), %xmm1
+# CHECK-NEXT: 1 4 1.00 cvtpi2ps %mm0, %xmm2
+# CHECK-NEXT: 1 11 1.00 * cvtpi2ps (%rax), %xmm2
+# CHECK-NEXT: 2 4 1.00 cvtps2pi %xmm0, %mm2
+# CHECK-NEXT: 2 11 1.00 * cvtps2pi (%rax), %mm2
+# CHECK-NEXT: 2 4 1.00 cvtsi2ss %ecx, %xmm2
+# CHECK-NEXT: 2 4 1.00 cvtsi2ss %rcx, %xmm2
+# CHECK-NEXT: 2 11 1.00 * cvtsi2ssl (%rax), %xmm2
+# CHECK-NEXT: 2 11 1.00 * cvtsi2ssq (%rax), %xmm2
+# CHECK-NEXT: 2 2 2.00 cvtss2si %xmm0, %ecx
+# CHECK-NEXT: 2 2 2.00 cvtss2si %xmm0, %rcx
+# CHECK-NEXT: 2 9 2.00 * cvtss2si (%rax), %ecx
+# CHECK-NEXT: 2 9 2.00 * cvtss2si (%rax), %rcx
+# CHECK-NEXT: 2 4 1.00 cvttps2pi %xmm0, %mm2
+# CHECK-NEXT: 2 11 1.00 * cvttps2pi (%rax), %mm2
+# CHECK-NEXT: 2 2 2.00 cvttss2si %xmm0, %ecx
+# CHECK-NEXT: 2 2 2.00 cvttss2si %xmm0, %rcx
+# CHECK-NEXT: 2 9 2.00 * cvttss2si (%rax), %ecx
+# CHECK-NEXT: 2 9 2.00 * cvttss2si (%rax), %rcx
+# CHECK-NEXT: 1 10 5.00 divps %xmm0, %xmm2
+# CHECK-NEXT: 1 17 5.00 * divps (%rax), %xmm2
+# CHECK-NEXT: 1 10 5.00 divss %xmm0, %xmm2
+# CHECK-NEXT: 1 17 5.00 * divss (%rax), %xmm2
+# CHECK-NEXT: 1 100 0.25 * * U ldmxcsr (%rax)
+# CHECK-NEXT: 1 1 0.50 * * U maskmovq %mm0, %mm1
+# CHECK-NEXT: 1 1 0.50 maxps %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * maxps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 maxss %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * maxss (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 minps %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * minps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 minss %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * minss (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 movaps %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * movaps %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * movaps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 movhlps %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.50 movlhps %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * movhps %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * movhps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 * movlps %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * movlps (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 movmskps %xmm0, %ecx
+# CHECK-NEXT: 1 5 1.00 * movntps %xmm0, (%rax)
+# CHECK-NEXT: 1 5 1.00 * * U movntq %mm0, (%rax)
+# CHECK-NEXT: 1 1 0.50 movss %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * movss %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * movss (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 movups %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * movups %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * movups (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 mulps %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * mulps (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 mulss %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * mulss (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 orps %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * orps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pavgb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pavgb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pavgw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pavgw (%rax), %mm2
+# CHECK-NEXT: 2 2 2.00 pextrw $1, %mm0, %ecx
+# CHECK-NEXT: 1 1 0.50 pinsrw $1, %eax, %mm2
+# CHECK-NEXT: 1 8 0.50 * pinsrw $1, (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pmaxsw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pmaxsw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pmaxub %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pmaxub (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pminsw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pminsw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pminub %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pminub (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 pmovmskb %mm0, %ecx
+# CHECK-NEXT: 1 3 1.00 pmulhuw %mm0, %mm2
+# CHECK-NEXT: 1 10 1.00 * pmulhuw (%rax), %mm2
+# CHECK-NEXT: 1 5 0.50 * * prefetcht0 (%rax)
+# CHECK-NEXT: 1 5 0.50 * * prefetcht1 (%rax)
+# CHECK-NEXT: 1 5 0.50 * * prefetcht2 (%rax)
+# CHECK-NEXT: 1 5 0.50 * * prefetchnta (%rax)
+# CHECK-NEXT: 1 3 1.00 psadbw %mm0, %mm2
+# CHECK-NEXT: 1 10 1.00 * psadbw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 pshufw $1, %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pshufw $1, (%rax), %mm2
+# CHECK-NEXT: 1 5 0.50 rcpps %xmm0, %xmm2
+# CHECK-NEXT: 1 12 0.50 * rcpps (%rax), %xmm2
+# CHECK-NEXT: 1 5 0.50 rcpss %xmm0, %xmm2
+# CHECK-NEXT: 1 12 0.50 * rcpss (%rax), %xmm2
+# CHECK-NEXT: 1 5 0.50 rsqrtps %xmm0, %xmm2
+# CHECK-NEXT: 1 12 0.50 * rsqrtps (%rax), %xmm2
+# CHECK-NEXT: 1 5 0.50 rsqrtss %xmm0, %xmm2
+# CHECK-NEXT: 1 12 0.50 * rsqrtss (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 * * U sfence
+# CHECK-NEXT: 1 1 0.50 shufps $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * shufps $1, (%rax), %xmm2
+# CHECK-NEXT: 1 8 7.00 sqrtps %xmm0, %xmm2
+# CHECK-NEXT: 1 15 7.00 * sqrtps (%rax), %xmm2
+# CHECK-NEXT: 1 8 7.00 sqrtss %xmm0, %xmm2
+# CHECK-NEXT: 1 15 7.00 * sqrtss (%rax), %xmm2
+# CHECK-NEXT: 1 100 0.25 * U stmxcsr (%rax)
+# CHECK-NEXT: 1 3 0.50 subps %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * subps (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 subss %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * subss (%rax), %xmm2
+# CHECK-NEXT: 1 5 1.00 ucomiss %xmm0, %xmm1
+# CHECK-NEXT: 1 12 1.00 * ucomiss (%rax), %xmm1
+# CHECK-NEXT: 1 1 0.50 unpckhps %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * unpckhps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 unpcklps %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * unpcklps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 xorps %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * xorps (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: 21.67 21.67 21.67 - - 4.00 - 31.50 101.50 19.00 9.00 21.33 21.33 21.33 28.50 28.50 2.33 2.33 2.33
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - addps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - addps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - addss %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - addss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - andnps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - andnps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - andps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - andps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - cmpeqps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - cmpeqps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - cmpeqss %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - cmpeqss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 1.00 0.50 - - - - - - - - - comiss %xmm0, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 1.00 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - comiss (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - cvtpi2ps %mm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - cvtpi2ps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - cvtps2pi %xmm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - cvtps2pi (%rax), %mm2
+# CHECK-NEXT: - - - - - 1.00 - - 1.00 - - - - - - - - - - cvtsi2ss %ecx, %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - 1.00 - - - - - - - - - - cvtsi2ss %rcx, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - 1.00 - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - cvtsi2ssl (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - 1.00 - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - cvtsi2ssq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - cvtss2si %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - cvtss2si %xmm0, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - - 0.33 0.33 0.33 0.50 0.50 - - - cvtss2si (%rax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - - 0.33 0.33 0.33 0.50 0.50 - - - cvtss2si (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - cvttps2pi %xmm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - cvttps2pi (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - cvttss2si %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - 2.00 - - - - - - - - - - cvttss2si %xmm0, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - - 0.33 0.33 0.33 0.50 0.50 - - - cvttss2si (%rax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - - 0.33 0.33 0.33 0.50 0.50 - - - cvttss2si (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - 5.00 - - - - - - - - - - divps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 5.00 - - 0.33 0.33 0.33 0.50 0.50 - - - divps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 5.00 - - - - - - - - - - divss %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 5.00 - - 0.33 0.33 0.33 0.50 0.50 - - - divss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - ldmxcsr (%rax)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - maskmovq %mm0, %mm1
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - maxps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - maxps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - maxss %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - maxss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - minps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - minps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - minss %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - minss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - movaps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 movaps %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - movaps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - movhlps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - movlhps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 movhps %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - movhps (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 movlps %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - movlps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - movmskps %xmm0, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 movntps %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 movntq %mm0, (%rax)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - movss %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 movss %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - movss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - movups %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 movups %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - movups (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - mulps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - mulps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - mulss %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - mulss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - orps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - orps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pavgb %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pavgb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pavgw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pavgw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.50 2.50 - - - - - - - - - - pextrw $1, %mm0, %ecx
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - pinsrw $1, %eax, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - pinsrw $1, (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pmaxsw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pmaxsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pmaxub %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pmaxub (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pminsw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pminsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pminub %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pminub (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - pmovmskb %mm0, %ecx
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - pmulhuw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - pmulhuw (%rax), %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - prefetcht0 (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - prefetcht1 (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - prefetcht2 (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - prefetchnta (%rax)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - psadbw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - psadbw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - pshufw $1, %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - pshufw $1, (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - rcpps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - rcpps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - rcpss %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - rcpss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - rsqrtps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - rsqrtps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - rsqrtss %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - rsqrtss (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - sfence
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - shufps $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - shufps $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 7.00 - - - - - - - - - - sqrtps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 7.00 - - 0.33 0.33 0.33 0.50 0.50 - - - sqrtps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 7.00 - - - - - - - - - - sqrtss %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 7.00 - - 0.33 0.33 0.33 0.50 0.50 - - - sqrtss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - stmxcsr (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - subps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - subps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - subss %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - subss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 1.00 0.50 - - - - - - - - - ucomiss %xmm0, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 1.00 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - ucomiss (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - unpckhps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - unpckhps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - unpcklps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - unpcklps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - xorps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - xorps (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse2.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse2.s
new file mode 100644
index 0000000000000..d269e853b7535
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse2.s
@@ -0,0 +1,971 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+addpd %xmm0, %xmm2
+addpd (%rax), %xmm2
+
+addsd %xmm0, %xmm2
+addsd (%rax), %xmm2
+
+andnpd %xmm0, %xmm2
+andnpd (%rax), %xmm2
+
+andpd %xmm0, %xmm2
+andpd (%rax), %xmm2
+
+clflush (%rax)
+
+cmppd $0, %xmm0, %xmm2
+cmppd $0, (%rax), %xmm2
+
+cmpsd $0, %xmm0, %xmm2
+cmpsd $0, (%rax), %xmm2
+
+comisd %xmm0, %xmm1
+comisd (%rax), %xmm1
+
+cvtdq2pd %xmm0, %xmm2
+cvtdq2pd (%rax), %xmm2
+
+cvtdq2ps %xmm0, %xmm2
+cvtdq2ps (%rax), %xmm2
+
+cvtpd2dq %xmm0, %xmm2
+cvtpd2dq (%rax), %xmm2
+
+cvtpd2pi %xmm0, %mm2
+cvtpd2pi (%rax), %mm2
+
+cvtpd2ps %xmm0, %xmm2
+cvtpd2ps (%rax), %xmm2
+
+cvtpi2pd %mm0, %xmm2
+cvtpi2pd (%rax), %xmm2
+
+cvtps2dq %xmm0, %xmm2
+cvtps2dq (%rax), %xmm2
+
+cvtps2pd %xmm0, %xmm2
+cvtps2pd (%rax), %xmm2
+
+cvtsd2si %xmm0, %ecx
+cvtsd2si %xmm0, %rcx
+cvtsd2si (%rax), %ecx
+cvtsd2si (%rax), %rcx
+
+cvtsd2ss %xmm0, %xmm2
+cvtsd2ss (%rax), %xmm2
+
+cvtsi2sd %ecx, %xmm2
+cvtsi2sd %rcx, %xmm2
+cvtsi2sdl (%rax), %xmm2
+cvtsi2sdq (%rax), %xmm2
+
+cvtss2sd %xmm0, %xmm2
+cvtss2sd (%rax), %xmm2
+
+cvttpd2dq %xmm0, %xmm2
+cvttpd2dq (%rax), %xmm2
+
+cvttpd2pi %xmm0, %mm2
+cvttpd2pi (%rax), %mm2
+
+cvttps2dq %xmm0, %xmm2
+cvttps2dq (%rax), %xmm2
+
+cvttsd2si %xmm0, %ecx
+cvttsd2si %xmm0, %rcx
+cvttsd2si (%rax), %ecx
+cvttsd2si (%rax), %rcx
+
+divpd %xmm0, %xmm2
+divpd (%rax), %xmm2
+
+divsd %xmm0, %xmm2
+divsd (%rax), %xmm2
+
+lfence
+
+maskmovdqu %xmm0, %xmm1
+
+maxpd %xmm0, %xmm2
+maxpd (%rax), %xmm2
+
+maxsd %xmm0, %xmm2
+maxsd (%rax), %xmm2
+
+mfence
+
+minpd %xmm0, %xmm2
+minpd (%rax), %xmm2
+
+minsd %xmm0, %xmm2
+minsd (%rax), %xmm2
+
+movapd %xmm0, %xmm2
+movapd %xmm0, (%rax)
+movapd (%rax), %xmm2
+
+movd %eax, %xmm2
+movd (%rax), %xmm2
+
+movd %xmm0, %ecx
+movd %xmm0, (%rax)
+
+movdqa %xmm0, %xmm2
+movdqa %xmm0, (%rax)
+movdqa (%rax), %xmm2
+
+movdqu %xmm0, %xmm2
+movdqu %xmm0, (%rax)
+movdqu (%rax), %xmm2
+
+movdq2q %xmm0, %mm2
+
+movhpd %xmm0, (%rax)
+movhpd (%rax), %xmm2
+
+movlpd %xmm0, (%rax)
+movlpd (%rax), %xmm2
+
+movmskpd %xmm0, %rcx
+
+movntil %eax, (%rax)
+movntiq %rax, (%rax)
+
+movntdq %xmm0, (%rax)
+movntpd %xmm0, (%rax)
+
+movq %xmm0, %xmm2
+
+movq %rax, %xmm2
+movq (%rax), %xmm2
+
+movq %xmm0, %rcx
+movq %xmm0, (%rax)
+
+movq2dq %mm0, %xmm2
+
+movsd %xmm0, %xmm2
+movsd %xmm0, (%rax)
+movsd (%rax), %xmm2
+
+movupd %xmm0, %xmm2
+movupd %xmm0, (%rax)
+movupd (%rax), %xmm2
+
+mulpd %xmm0, %xmm2
+mulpd (%rax), %xmm2
+
+mulsd %xmm0, %xmm2
+mulsd (%rax), %xmm2
+
+orpd %xmm0, %xmm2
+orpd (%rax), %xmm2
+
+packssdw %xmm0, %xmm2
+packssdw (%rax), %xmm2
+
+packsswb %xmm0, %xmm2
+packsswb (%rax), %xmm2
+
+packuswb %xmm0, %xmm2
+packuswb (%rax), %xmm2
+
+paddb %xmm0, %xmm2
+paddb (%rax), %xmm2
+
+paddd %xmm0, %xmm2
+paddd (%rax), %xmm2
+
+paddq %mm0, %mm2
+paddq (%rax), %mm2
+
+paddq %xmm0, %xmm2
+paddq (%rax), %xmm2
+
+paddsb %xmm0, %xmm2
+paddsb (%rax), %xmm2
+
+paddsw %xmm0, %xmm2
+paddsw (%rax), %xmm2
+
+paddusb %xmm0, %xmm2
+paddusb (%rax), %xmm2
+
+paddusw %xmm0, %xmm2
+paddusw (%rax), %xmm2
+
+paddw %xmm0, %xmm2
+paddw (%rax), %xmm2
+
+pand %xmm0, %xmm2
+pand (%rax), %xmm2
+
+pandn %xmm0, %xmm2
+pandn (%rax), %xmm2
+
+pavgb %xmm0, %xmm2
+pavgb (%rax), %xmm2
+
+pavgw %xmm0, %xmm2
+pavgw (%rax), %xmm2
+
+pcmpeqb %xmm0, %xmm2
+pcmpeqb (%rax), %xmm2
+
+pcmpeqd %xmm0, %xmm2
+pcmpeqd (%rax), %xmm2
+
+pcmpeqw %xmm0, %xmm2
+pcmpeqw (%rax), %xmm2
+
+pcmpgtb %xmm0, %xmm2
+pcmpgtb (%rax), %xmm2
+
+pcmpgtd %xmm0, %xmm2
+pcmpgtd (%rax), %xmm2
+
+pcmpgtw %xmm0, %xmm2
+pcmpgtw (%rax), %xmm2
+
+pextrw $1, %xmm0, %rcx
+
+pinsrw $1, %rax, %xmm0
+pinsrw $1, (%rax), %xmm0
+
+pmaddwd %xmm0, %xmm2
+pmaddwd (%rax), %xmm2
+
+pmaxsw %xmm0, %xmm2
+pmaxsw (%rax), %xmm2
+
+pmaxub %xmm0, %xmm2
+pmaxub (%rax), %xmm2
+
+pminsw %xmm0, %xmm2
+pminsw (%rax), %xmm2
+
+pminub %xmm0, %xmm2
+pminub (%rax), %xmm2
+
+pmovmskb %xmm0, %rcx
+
+pmulhuw %xmm0, %xmm2
+pmulhuw (%rax), %xmm2
+
+pmulhw %xmm0, %xmm2
+pmulhw (%rax), %xmm2
+
+pmullw %xmm0, %xmm2
+pmullw (%rax), %xmm2
+
+pmuludq %mm0, %mm2
+pmuludq (%rax), %mm2
+
+pmuludq %xmm0, %xmm2
+pmuludq (%rax), %xmm2
+
+por %xmm0, %xmm2
+por (%rax), %xmm2
+
+psadbw %xmm0, %xmm2
+psadbw (%rax), %xmm2
+
+pshufd $1, %xmm0, %xmm2
+pshufd $1, (%rax), %xmm2
+
+pshufhw $1, %xmm0, %xmm2
+pshufhw $1, (%rax), %xmm2
+
+pshuflw $1, %xmm0, %xmm2
+pshuflw $1, (%rax), %xmm2
+
+pslld $1, %xmm2
+pslld %xmm0, %xmm2
+pslld (%rax), %xmm2
+
+pslldq $1, %xmm2
+
+psllq $1, %xmm2
+psllq %xmm0, %xmm2
+psllq (%rax), %xmm2
+
+psllw $1, %xmm2
+psllw %xmm0, %xmm2
+psllw (%rax), %xmm2
+
+psrad $1, %xmm2
+psrad %xmm0, %xmm2
+psrad (%rax), %xmm2
+
+psraw $1, %xmm2
+psraw %xmm0, %xmm2
+psraw (%rax), %xmm2
+
+psrld $1, %xmm2
+psrld %xmm0, %xmm2
+psrld (%rax), %xmm2
+
+psrldq $1, %xmm2
+
+psrlq $1, %xmm2
+psrlq %xmm0, %xmm2
+psrlq (%rax), %xmm2
+
+psrlw $1, %xmm2
+psrlw %xmm0, %xmm2
+psrlw (%rax), %xmm2
+
+psubb %xmm0, %xmm2
+psubb (%rax), %xmm2
+
+psubd %xmm0, %xmm2
+psubd (%rax), %xmm2
+
+psubq %mm0, %mm2
+psubq (%rax), %mm2
+
+psubq %xmm0, %xmm2
+psubq (%rax), %xmm2
+
+psubsb %xmm0, %xmm2
+psubsb (%rax), %xmm2
+
+psubsw %xmm0, %xmm2
+psubsw (%rax), %xmm2
+
+psubusb %xmm0, %xmm2
+psubusb (%rax), %xmm2
+
+psubusw %xmm0, %xmm2
+psubusw (%rax), %xmm2
+
+psubw %xmm0, %xmm2
+psubw (%rax), %xmm2
+
+punpckhbw %xmm0, %xmm2
+punpckhbw (%rax), %xmm2
+
+punpckhdq %xmm0, %xmm2
+punpckhdq (%rax), %xmm2
+
+punpckhqdq %xmm0, %xmm2
+punpckhqdq (%rax), %xmm2
+
+punpckhwd %xmm0, %xmm2
+punpckhwd (%rax), %xmm2
+
+punpcklbw %xmm0, %xmm2
+punpcklbw (%rax), %xmm2
+
+punpckldq %xmm0, %xmm2
+punpckldq (%rax), %xmm2
+
+punpcklqdq %xmm0, %xmm2
+punpcklqdq (%rax), %xmm2
+
+punpcklwd %xmm0, %xmm2
+punpcklwd (%rax), %xmm2
+
+pxor %xmm0, %xmm2
+pxor (%rax), %xmm2
+
+shufpd $1, %xmm0, %xmm2
+shufpd $1, (%rax), %xmm2
+
+sqrtpd %xmm0, %xmm2
+sqrtpd (%rax), %xmm2
+
+sqrtsd %xmm0, %xmm2
+sqrtsd (%rax), %xmm2
+
+subpd %xmm0, %xmm2
+subpd (%rax), %xmm2
+
+subsd %xmm0, %xmm2
+subsd (%rax), %xmm2
+
+ucomisd %xmm0, %xmm1
+ucomisd (%rax), %xmm1
+
+unpckhpd %xmm0, %xmm2
+unpckhpd (%rax), %xmm2
+
+unpcklpd %xmm0, %xmm2
+unpcklpd (%rax), %xmm2
+
+xorpd %xmm0, %xmm2
+xorpd (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 addpd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * addpd (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 addsd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * addsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 andnpd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * andnpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 andpd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * andpd (%rax), %xmm2
+# CHECK-NEXT: 1 5 0.50 * * U clflush (%rax)
+# CHECK-NEXT: 1 1 0.50 cmpeqpd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * cmpeqpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 cmpeqsd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * cmpeqsd (%rax), %xmm2
+# CHECK-NEXT: 1 5 1.00 comisd %xmm0, %xmm1
+# CHECK-NEXT: 1 12 1.00 * comisd (%rax), %xmm1
+# CHECK-NEXT: 2 7 2.00 cvtdq2pd %xmm0, %xmm2
+# CHECK-NEXT: 2 14 2.00 * cvtdq2pd (%rax), %xmm2
+# CHECK-NEXT: 1 4 1.00 cvtdq2ps %xmm0, %xmm2
+# CHECK-NEXT: 1 11 1.00 * cvtdq2ps (%rax), %xmm2
+# CHECK-NEXT: 2 7 2.00 cvtpd2dq %xmm0, %xmm2
+# CHECK-NEXT: 2 14 2.00 * cvtpd2dq (%rax), %xmm2
+# CHECK-NEXT: 2 7 2.00 cvtpd2pi %xmm0, %mm2
+# CHECK-NEXT: 2 14 2.00 * cvtpd2pi (%rax), %mm2
+# CHECK-NEXT: 2 3 1.00 cvtpd2ps %xmm0, %xmm2
+# CHECK-NEXT: 2 10 1.00 * cvtpd2ps (%rax), %xmm2
+# CHECK-NEXT: 2 7 2.00 cvtpi2pd %mm0, %xmm2
+# CHECK-NEXT: 2 14 2.00 * cvtpi2pd (%rax), %xmm2
+# CHECK-NEXT: 2 4 1.00 cvtps2dq %xmm0, %xmm2
+# CHECK-NEXT: 2 11 1.00 * cvtps2dq (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 cvtps2pd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * cvtps2pd (%rax), %xmm2
+# CHECK-NEXT: 2 2 3.00 cvtsd2si %xmm0, %ecx
+# CHECK-NEXT: 2 2 3.00 cvtsd2si %xmm0, %rcx
+# CHECK-NEXT: 2 9 3.00 * cvtsd2si (%rax), %ecx
+# CHECK-NEXT: 2 9 3.00 * cvtsd2si (%rax), %rcx
+# CHECK-NEXT: 1 4 1.00 cvtsd2ss %xmm0, %xmm2
+# CHECK-NEXT: 1 11 1.00 * cvtsd2ss (%rax), %xmm2
+# CHECK-NEXT: 2 4 2.00 cvtsi2sd %ecx, %xmm2
+# CHECK-NEXT: 2 4 2.00 cvtsi2sd %rcx, %xmm2
+# CHECK-NEXT: 2 11 2.00 * cvtsi2sdl (%rax), %xmm2
+# CHECK-NEXT: 2 11 2.00 * cvtsi2sdq (%rax), %xmm2
+# CHECK-NEXT: 1 4 1.00 cvtss2sd %xmm0, %xmm2
+# CHECK-NEXT: 1 11 1.00 * cvtss2sd (%rax), %xmm2
+# CHECK-NEXT: 2 7 2.00 cvttpd2dq %xmm0, %xmm2
+# CHECK-NEXT: 2 14 2.00 * cvttpd2dq (%rax), %xmm2
+# CHECK-NEXT: 2 7 2.00 cvttpd2pi %xmm0, %mm2
+# CHECK-NEXT: 2 14 2.00 * cvttpd2pi (%rax), %mm2
+# CHECK-NEXT: 2 4 1.00 cvttps2dq %xmm0, %xmm2
+# CHECK-NEXT: 2 11 1.00 * cvttps2dq (%rax), %xmm2
+# CHECK-NEXT: 2 2 3.00 cvttsd2si %xmm0, %ecx
+# CHECK-NEXT: 2 2 3.00 cvttsd2si %xmm0, %rcx
+# CHECK-NEXT: 2 9 3.00 * cvttsd2si (%rax), %ecx
+# CHECK-NEXT: 2 9 3.00 * cvttsd2si (%rax), %rcx
+# CHECK-NEXT: 1 8 6.00 divpd %xmm0, %xmm2
+# CHECK-NEXT: 1 15 6.00 * divpd (%rax), %xmm2
+# CHECK-NEXT: 1 8 6.00 divsd %xmm0, %xmm2
+# CHECK-NEXT: 1 15 6.00 * divsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 * * U lfence
+# CHECK-NEXT: 1 1 0.33 * * U maskmovdqu %xmm0, %xmm1
+# CHECK-NEXT: 1 1 0.50 maxpd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * maxpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 maxsd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * maxsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 * * U mfence
+# CHECK-NEXT: 1 1 0.50 minpd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * minpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 minsd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * minsd (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 movapd %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * movapd %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * movapd (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 movd %eax, %xmm2
+# CHECK-NEXT: 1 8 0.50 * movd (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 movd %xmm0, %ecx
+# CHECK-NEXT: 1 1 0.33 * movd %xmm0, (%rax)
+# CHECK-NEXT: 1 0 0.25 movdqa %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * movdqa %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * movdqa (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 movdqu %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * movdqu %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * movdqu (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 movdq2q %xmm0, %mm2
+# CHECK-NEXT: 1 1 0.33 * movhpd %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * movhpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 * movlpd %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * movlpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 movmskpd %xmm0, %ecx
+# CHECK-NEXT: 1 1 0.33 * movntil %eax, (%rax)
+# CHECK-NEXT: 1 1 0.33 * movntiq %rax, (%rax)
+# CHECK-NEXT: 1 5 1.00 * movntdq %xmm0, (%rax)
+# CHECK-NEXT: 1 5 1.00 * movntpd %xmm0, (%rax)
+# CHECK-NEXT: 1 1 0.25 movq %xmm0, %xmm2
+# CHECK-NEXT: 1 1 1.00 movq %rax, %xmm2
+# CHECK-NEXT: 1 8 0.50 * movq (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 movq %xmm0, %rcx
+# CHECK-NEXT: 1 1 0.33 * movq %xmm0, (%rax)
+# CHECK-NEXT: 1 0 0.25 movq2dq %mm0, %xmm2
+# CHECK-NEXT: 1 1 0.50 movsd %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * movsd %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * movsd (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 movupd %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * movupd %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * movupd (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 mulpd %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * mulpd (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 mulsd %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * mulsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 orpd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * orpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 packssdw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * packssdw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 packsswb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * packsswb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 packuswb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * packuswb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 paddb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * paddb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 paddd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * paddd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 paddq %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * paddq (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 paddq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * paddq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 paddsb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * paddsb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 paddsw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * paddsw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 paddusb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * paddusb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 paddusw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * paddusw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 paddw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * paddw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pand %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pand (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pandn %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pandn (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pavgb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pavgb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pavgw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pavgw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pcmpeqb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pcmpeqb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pcmpeqd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pcmpeqd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pcmpeqw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pcmpeqw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pcmpgtb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pcmpgtd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pcmpgtw (%rax), %xmm2
+# CHECK-NEXT: 2 2 2.00 pextrw $1, %xmm0, %ecx
+# CHECK-NEXT: 1 2 0.50 pinsrw $1, %eax, %xmm0
+# CHECK-NEXT: 1 9 0.50 * pinsrw $1, (%rax), %xmm0
+# CHECK-NEXT: 1 3 1.00 pmaddwd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 1.00 * pmaddwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pmaxsw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmaxsw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pmaxub %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmaxub (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pminsw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pminsw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pminub %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pminub (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 pmovmskb %xmm0, %ecx
+# CHECK-NEXT: 1 3 1.00 pmulhuw %xmm0, %xmm2
+# CHECK-NEXT: 1 10 1.00 * pmulhuw (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 pmulhw %xmm0, %xmm2
+# CHECK-NEXT: 1 10 1.00 * pmulhw (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 pmullw %xmm0, %xmm2
+# CHECK-NEXT: 1 10 1.00 * pmullw (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 pmuludq %mm0, %mm2
+# CHECK-NEXT: 1 10 1.00 * pmuludq (%rax), %mm2
+# CHECK-NEXT: 1 3 1.00 pmuludq %xmm0, %xmm2
+# CHECK-NEXT: 1 10 1.00 * pmuludq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 por %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * por (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 psadbw %xmm0, %xmm2
+# CHECK-NEXT: 1 10 1.00 * psadbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pshufd $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pshufd $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pshufhw $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pshufhw $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pshuflw $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pshuflw $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 pslld $1, %xmm2
+# CHECK-NEXT: 1 1 1.00 pslld %xmm0, %xmm2
+# CHECK-NEXT: 1 8 1.00 * pslld (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pslldq $1, %xmm2
+# CHECK-NEXT: 1 1 1.00 psllq $1, %xmm2
+# CHECK-NEXT: 1 1 1.00 psllq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 1.00 * psllq (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 psllw $1, %xmm2
+# CHECK-NEXT: 1 1 1.00 psllw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 1.00 * psllw (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 psrad $1, %xmm2
+# CHECK-NEXT: 1 1 1.00 psrad %xmm0, %xmm2
+# CHECK-NEXT: 1 8 1.00 * psrad (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 psraw $1, %xmm2
+# CHECK-NEXT: 1 1 1.00 psraw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 1.00 * psraw (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 psrld $1, %xmm2
+# CHECK-NEXT: 1 1 1.00 psrld %xmm0, %xmm2
+# CHECK-NEXT: 1 8 1.00 * psrld (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psrldq $1, %xmm2
+# CHECK-NEXT: 1 1 1.00 psrlq $1, %xmm2
+# CHECK-NEXT: 1 1 1.00 psrlq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 1.00 * psrlq (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 psrlw $1, %xmm2
+# CHECK-NEXT: 1 1 1.00 psrlw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 1.00 * psrlw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 psubb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psubb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 psubd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psubd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 psubq %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psubq (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 psubq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psubq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 psubsb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psubsb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 psubsw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psubsw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 psubusb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psubusb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 psubusw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psubusw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 psubw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psubw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpckhbw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * punpckhbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpckhdq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * punpckhdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpckhqdq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * punpckhqdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpckhwd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * punpckhwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpcklbw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * punpcklbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpckldq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * punpckldq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpcklqdq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * punpcklqdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpcklwd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * punpcklwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pxor %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pxor (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 shufpd $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * shufpd $1, (%rax), %xmm2
+# CHECK-NEXT: 1 8 10.00 sqrtpd %xmm0, %xmm2
+# CHECK-NEXT: 1 15 10.00 * sqrtpd (%rax), %xmm2
+# CHECK-NEXT: 1 8 10.00 sqrtsd %xmm0, %xmm2
+# CHECK-NEXT: 1 15 10.00 * sqrtsd (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 subpd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * subpd (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 subsd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * subsd (%rax), %xmm2
+# CHECK-NEXT: 1 5 1.00 ucomisd %xmm0, %xmm1
+# CHECK-NEXT: 1 12 1.00 * ucomisd (%rax), %xmm1
+# CHECK-NEXT: 1 1 0.50 unpckhpd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * unpckhpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 unpcklpd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * unpcklpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 xorpd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * xorpd (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: 44.67 44.67 44.67 - - 4.00 - 70.25 222.25 29.25 25.25 44.00 44.00 44.00 59.00 59.00 4.67 4.67 4.67
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - addpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - addpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - addsd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - addsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - andnpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - andnpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - andpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - andpd (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - clflush (%rax)
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - cmpeqpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - cmpeqpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - cmpeqsd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - cmpeqsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 1.00 0.50 - - - - - - - - - comisd %xmm0, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 1.00 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - comisd (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - 0.50 2.50 - - - - - - - - - - cvtdq2pd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 2.50 - - 0.33 0.33 0.33 0.50 0.50 - - - cvtdq2pd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - cvtdq2ps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - cvtdq2ps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 2.50 - - - - - - - - - - cvtpd2dq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 2.50 - - 0.33 0.33 0.33 0.50 0.50 - - - cvtpd2dq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 2.50 - - - - - - - - - - cvtpd2pi %xmm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 2.50 - - 0.33 0.33 0.33 0.50 0.50 - - - cvtpd2pi (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 1.50 - 0.50 - - - - - - - - cvtpd2ps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - cvtpd2ps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 2.50 - - - - - - - - - - cvtpi2pd %mm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 2.50 - - 0.33 0.33 0.33 0.50 0.50 - - - cvtpi2pd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - cvtps2dq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - cvtps2dq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - cvtps2pd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - cvtps2pd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 3.00 - - - - - - - - - - cvtsd2si %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - 3.00 - - - - - - - - - - cvtsd2si %xmm0, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 - - 0.33 0.33 0.33 0.50 0.50 - - - cvtsd2si (%rax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 - - 0.33 0.33 0.33 0.50 0.50 - - - cvtsd2si (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - cvtsd2ss %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - cvtsd2ss (%rax), %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - 2.00 - - - - - - - - - - cvtsi2sd %ecx, %xmm2
+# CHECK-NEXT: - - - - - 1.00 - - 2.00 - - - - - - - - - - cvtsi2sd %rcx, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - 1.00 - - 2.00 - - 0.33 0.33 0.33 0.50 0.50 - - - cvtsi2sdl (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - 1.00 - - 2.00 - - 0.33 0.33 0.33 0.50 0.50 - - - cvtsi2sdq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - cvtss2sd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - cvtss2sd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 2.50 - - - - - - - - - - cvttpd2dq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 2.50 - - 0.33 0.33 0.33 0.50 0.50 - - - cvttpd2dq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 2.50 - - - - - - - - - - cvttpd2pi %xmm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 2.50 - - 0.33 0.33 0.33 0.50 0.50 - - - cvttpd2pi (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - cvttps2dq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - cvttps2dq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 3.00 - - - - - - - - - - cvttsd2si %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - 3.00 - - - - - - - - - - cvttsd2si %xmm0, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 - - 0.33 0.33 0.33 0.50 0.50 - - - cvttsd2si (%rax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 - - 0.33 0.33 0.33 0.50 0.50 - - - cvttsd2si (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - 6.00 - - - - - - - - - - divpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 6.00 - - 0.33 0.33 0.33 0.50 0.50 - - - divpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 6.00 - - - - - - - - - - divsd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 6.00 - - 0.33 0.33 0.33 0.50 0.50 - - - divsd (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - lfence
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 maskmovdqu %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - maxpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - maxpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - maxsd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - maxsd (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - mfence
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - minpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - minpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - minsd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - minsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - movapd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 movapd %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - movapd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - movd %eax, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - movd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - movd %xmm0, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 movd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - movdqa %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 movdqa %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - movdqa (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - movdqu %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 movdqu %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - movdqu (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - movdq2q %xmm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 movhpd %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - movhpd (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 movlpd %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - movlpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - movmskpd %xmm0, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 movntil %eax, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 movntiq %rax, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 movntdq %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 movntpd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - movq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - movq %rax, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - movq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - movq %xmm0, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 movq %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - movq2dq %mm0, %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - movsd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 movsd %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - movsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - movupd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 movupd %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - movupd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - mulpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - mulpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - mulsd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - mulsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - orpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - orpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - packssdw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - packssdw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - packsswb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - packsswb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - packuswb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - packuswb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - paddb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - paddb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - paddd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - paddd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - paddq %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - paddq (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - paddq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - paddq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - paddsb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - paddsb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - paddsw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - paddsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - paddusb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - paddusb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - paddusw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - paddusw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - paddw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - paddw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pand %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pand (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pandn %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pandn (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pavgb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pavgb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pavgw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pavgw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pcmpeqb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pcmpeqb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pcmpeqd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pcmpeqd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pcmpeqw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pcmpeqw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pcmpgtb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pcmpgtb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pcmpgtd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pcmpgtd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pcmpgtw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pcmpgtw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 2.50 - - - - - - - - - - pextrw $1, %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - pinsrw $1, %eax, %xmm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - pinsrw $1, (%rax), %xmm0
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - pmaddwd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - pmaddwd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pmaxsw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pmaxsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pmaxub %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pmaxub (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pminsw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pminsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pminub %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pminub (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - pmovmskb %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - pmulhuw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - pmulhuw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - pmulhw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - pmulhw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - pmullw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - pmullw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - pmuludq %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - pmuludq (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - pmuludq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - pmuludq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - por %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - por (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - psadbw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - psadbw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - pshufd $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - pshufd $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - pshufhw $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - pshufhw $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - pshuflw $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - pshuflw $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - pslld $1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - pslld %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - pslld (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - pslldq $1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - psllq $1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - psllq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - psllq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - psllw $1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - psllw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - psllw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - psrad $1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - psrad %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - psrad (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - psraw $1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - psraw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - psraw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - psrld $1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - psrld %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - psrld (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - psrldq $1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - psrlq $1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - psrlq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - psrlq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - psrlw $1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - psrlw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 0.50 0.50 - - - psrlw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - psubb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - psubb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - psubd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - psubd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - psubq %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - psubq (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - psubq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - psubq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - psubsb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - psubsb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - psubsw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - psubsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - psubusb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - psubusb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - psubusw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - psubusw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - psubw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - psubw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - punpckhbw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - punpckhbw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - punpckhdq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - punpckhdq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - punpckhqdq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - punpckhqdq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - punpckhwd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - punpckhwd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - punpcklbw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - punpcklbw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - punpckldq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - punpckldq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - punpcklqdq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - punpcklqdq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - punpcklwd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - punpcklwd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pxor %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pxor (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - shufpd $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - shufpd $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 10.00 - - - - - - - - - - sqrtpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 10.00 - - 0.33 0.33 0.33 0.50 0.50 - - - sqrtpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 10.00 - - - - - - - - - - sqrtsd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 10.00 - - 0.33 0.33 0.33 0.50 0.50 - - - sqrtsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - subpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - subpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - subsd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - subsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 1.00 0.50 - - - - - - - - - ucomisd %xmm0, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 1.00 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - ucomisd (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - unpckhpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - unpckhpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - unpcklpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - unpcklpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - xorpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - xorpd (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse3.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse3.s
new file mode 100644
index 0000000000000..fc6ed3f89a153
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse3.s
@@ -0,0 +1,115 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+addsubpd %xmm0, %xmm2
+addsubpd (%rax), %xmm2
+
+addsubps %xmm0, %xmm2
+addsubps (%rax), %xmm2
+
+haddpd %xmm0, %xmm2
+haddpd (%rax), %xmm2
+
+haddps %xmm0, %xmm2
+haddps (%rax), %xmm2
+
+hsubpd %xmm0, %xmm2
+hsubpd (%rax), %xmm2
+
+hsubps %xmm0, %xmm2
+hsubps (%rax), %xmm2
+
+lddqu (%rax), %xmm2
+
+monitor
+
+movddup %xmm0, %xmm2
+movddup (%rax), %xmm2
+
+movshdup %xmm0, %xmm2
+movshdup (%rax), %xmm2
+
+movsldup %xmm0, %xmm2
+movsldup (%rax), %xmm2
+
+mwait
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 addsubpd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * addsubpd (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 addsubps %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * addsubps (%rax), %xmm2
+# CHECK-NEXT: 4 7 4.00 haddpd %xmm0, %xmm2
+# CHECK-NEXT: 7 14 4.00 * haddpd (%rax), %xmm2
+# CHECK-NEXT: 4 7 4.00 haddps %xmm0, %xmm2
+# CHECK-NEXT: 7 14 4.00 * haddps (%rax), %xmm2
+# CHECK-NEXT: 4 7 4.00 hsubpd %xmm0, %xmm2
+# CHECK-NEXT: 7 14 4.00 * hsubpd (%rax), %xmm2
+# CHECK-NEXT: 4 7 4.00 hsubps %xmm0, %xmm2
+# CHECK-NEXT: 7 14 4.00 * hsubps (%rax), %xmm2
+# CHECK-NEXT: 1 8 0.50 * lddqu (%rax), %xmm2
+# CHECK-NEXT: 1 100 0.25 U monitor
+# CHECK-NEXT: 1 1 0.50 movddup %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * movddup (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 movshdup %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * movshdup (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 movsldup %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * movsldup (%rax), %xmm2
+# CHECK-NEXT: 1 100 0.25 * * U mwait
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: 3.33 3.33 3.33 - - - - 3.00 37.00 - 34.00 3.33 3.33 3.33 5.00 5.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - addsubpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - addsubpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - addsubps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - addsubps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - haddpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - haddpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - haddps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - haddps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - hsubpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - hsubpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - hsubps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - hsubps (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - lddqu (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - monitor
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - movddup %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - movddup (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - movshdup %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - movshdup (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - movsldup %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - movsldup (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - mwait
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse41.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse41.s
new file mode 100644
index 0000000000000..78ac11ad6f163
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse41.s
@@ -0,0 +1,377 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+blendpd $11, %xmm0, %xmm2
+blendpd $11, (%rax), %xmm2
+
+blendps $11, %xmm0, %xmm2
+blendps $11, (%rax), %xmm2
+
+blendvpd %xmm0, %xmm2
+blendvpd (%rax), %xmm2
+
+blendvps %xmm0, %xmm2
+blendvps (%rax), %xmm2
+
+dppd $22, %xmm0, %xmm2
+dppd $22, (%rax), %xmm2
+
+dpps $22, %xmm0, %xmm2
+dpps $22, (%rax), %xmm2
+
+extractps $1, %xmm0, %rcx
+extractps $1, %xmm0, (%rax)
+
+insertps $1, %xmm0, %xmm2
+insertps $1, (%rax), %xmm2
+
+movntdqa (%rax), %xmm2
+
+mpsadbw $1, %xmm0, %xmm2
+mpsadbw $1, (%rax), %xmm2
+
+packusdw %xmm0, %xmm2
+packusdw (%rax), %xmm2
+
+pblendvb %xmm0, %xmm2
+pblendvb (%rax), %xmm2
+
+pblendw $11, %xmm0, %xmm2
+pblendw $11, (%rax), %xmm2
+
+pcmpeqq %xmm0, %xmm2
+pcmpeqq (%rax), %xmm2
+
+pextrb $1, %xmm0, %ecx
+pextrb $1, %xmm0, (%rax)
+
+pextrd $1, %xmm0, %ecx
+pextrd $1, %xmm0, (%rax)
+
+pextrq $1, %xmm0, %rcx
+pextrq $1, %xmm0, (%rax)
+
+pextrw $1, %xmm0, (%rax)
+
+phminposuw %xmm0, %xmm2
+phminposuw (%rax), %xmm2
+
+pinsrb $1, %eax, %xmm1
+pinsrb $1, (%rax), %xmm1
+
+pinsrd $1, %eax, %xmm1
+pinsrd $1, (%rax), %xmm1
+
+pinsrq $1, %rax, %xmm1
+pinsrq $1, (%rax), %xmm1
+
+pmaxsb %xmm0, %xmm2
+pmaxsb (%rax), %xmm2
+
+pmaxsd %xmm0, %xmm2
+pmaxsd (%rax), %xmm2
+
+pmaxud %xmm0, %xmm2
+pmaxud (%rax), %xmm2
+
+pmaxuw %xmm0, %xmm2
+pmaxuw (%rax), %xmm2
+
+pminsb %xmm0, %xmm2
+pminsb (%rax), %xmm2
+
+pminsd %xmm0, %xmm2
+pminsd (%rax), %xmm2
+
+pminud %xmm0, %xmm2
+pminud (%rax), %xmm2
+
+pminuw %xmm0, %xmm2
+pminuw (%rax), %xmm2
+
+pmovsxbd %xmm0, %xmm2
+pmovsxbd (%rax), %xmm2
+
+pmovsxbq %xmm0, %xmm2
+pmovsxbq (%rax), %xmm2
+
+pmovsxbw %xmm0, %xmm2
+pmovsxbw (%rax), %xmm2
+
+pmovsxdq %xmm0, %xmm2
+pmovsxdq (%rax), %xmm2
+
+pmovsxwd %xmm0, %xmm2
+pmovsxwd (%rax), %xmm2
+
+pmovsxwq %xmm0, %xmm2
+pmovsxwq (%rax), %xmm2
+
+pmovzxbd %xmm0, %xmm2
+pmovzxbd (%rax), %xmm2
+
+pmovzxbq %xmm0, %xmm2
+pmovzxbq (%rax), %xmm2
+
+pmovzxbw %xmm0, %xmm2
+pmovzxbw (%rax), %xmm2
+
+pmovzxdq %xmm0, %xmm2
+pmovzxdq (%rax), %xmm2
+
+pmovzxwd %xmm0, %xmm2
+pmovzxwd (%rax), %xmm2
+
+pmovzxwq %xmm0, %xmm2
+pmovzxwq (%rax), %xmm2
+
+pmuldq %xmm0, %xmm2
+pmuldq (%rax), %xmm2
+
+pmulld %xmm0, %xmm2
+pmulld (%rax), %xmm2
+
+ptest %xmm0, %xmm1
+ptest (%rax), %xmm1
+
+roundpd $1, %xmm0, %xmm2
+roundpd $1, (%rax), %xmm2
+
+roundps $1, %xmm0, %xmm2
+roundps $1, (%rax), %xmm2
+
+roundsd $1, %xmm0, %xmm2
+roundsd $1, (%rax), %xmm2
+
+roundss $1, %xmm0, %xmm2
+roundss $1, (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.50 blendpd $11, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * blendpd $11, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 blendps $11, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * blendps $11, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 blendvpd %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * blendvpd %xmm0, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 blendvps %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * blendvps %xmm0, (%rax), %xmm2
+# CHECK-NEXT: 4 10 8.00 dppd $22, %xmm0, %xmm2
+# CHECK-NEXT: 4 17 8.00 * dppd $22, (%rax), %xmm2
+# CHECK-NEXT: 1 100 0.25 dpps $22, %xmm0, %xmm2
+# CHECK-NEXT: 1 100 0.25 * dpps $22, (%rax), %xmm2
+# CHECK-NEXT: 2 2 2.00 extractps $1, %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 * extractps $1, %xmm0, (%rax)
+# CHECK-NEXT: 1 1 0.50 insertps $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * insertps $1, (%rax), %xmm2
+# CHECK-NEXT: 1 8 0.50 * movntdqa (%rax), %xmm2
+# CHECK-NEXT: 1 4 2.00 mpsadbw $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 11 2.00 * mpsadbw $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 packusdw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * packusdw (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 pblendvb %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 1.00 * pblendvb %xmm0, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pblendw $11, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pblendw $11, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pcmpeqq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pcmpeqq (%rax), %xmm2
+# CHECK-NEXT: 2 2 2.00 pextrb $1, %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 * pextrb $1, %xmm0, (%rax)
+# CHECK-NEXT: 2 2 2.00 pextrd $1, %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 * pextrd $1, %xmm0, (%rax)
+# CHECK-NEXT: 2 2 2.00 pextrq $1, %xmm0, %rcx
+# CHECK-NEXT: 2 2 1.00 * pextrq $1, %xmm0, (%rax)
+# CHECK-NEXT: 2 2 1.00 * pextrw $1, %xmm0, (%rax)
+# CHECK-NEXT: 1 3 1.00 phminposuw %xmm0, %xmm2
+# CHECK-NEXT: 1 10 1.00 * phminposuw (%rax), %xmm2
+# CHECK-NEXT: 1 2 0.50 pinsrb $1, %eax, %xmm1
+# CHECK-NEXT: 1 9 0.50 * pinsrb $1, (%rax), %xmm1
+# CHECK-NEXT: 1 2 0.50 pinsrd $1, %eax, %xmm1
+# CHECK-NEXT: 1 9 0.50 * pinsrd $1, (%rax), %xmm1
+# CHECK-NEXT: 1 2 0.50 pinsrq $1, %rax, %xmm1
+# CHECK-NEXT: 1 9 0.50 * pinsrq $1, (%rax), %xmm1
+# CHECK-NEXT: 1 1 0.25 pmaxsb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmaxsb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pmaxsd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmaxsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pmaxud %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmaxud (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pmaxuw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmaxuw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pminsb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pminsb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pminsd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pminsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pminud %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pminud (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pminuw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pminuw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovsxbd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovsxbd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovsxbq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovsxbq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovsxbw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovsxbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovsxdq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovsxdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovsxwd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovsxwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovsxwq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovsxwq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovzxbd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovzxbd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovzxbq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovzxbq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovzxbw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovzxbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovzxdq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovzxdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovzxwd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovzxwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovzxwq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovzxwq (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 pmuldq %xmm0, %xmm2
+# CHECK-NEXT: 1 10 1.00 * pmuldq (%rax), %xmm2
+# CHECK-NEXT: 1 4 2.00 pmulld %xmm0, %xmm2
+# CHECK-NEXT: 1 11 2.00 * pmulld (%rax), %xmm2
+# CHECK-NEXT: 1 4 2.00 ptest %xmm0, %xmm1
+# CHECK-NEXT: 8 11 2.00 * ptest (%rax), %xmm1
+# CHECK-NEXT: 1 4 1.00 roundpd $1, %xmm0, %xmm2
+# CHECK-NEXT: 8 11 1.00 * roundpd $1, (%rax), %xmm2
+# CHECK-NEXT: 1 4 1.00 roundps $1, %xmm0, %xmm2
+# CHECK-NEXT: 8 11 1.00 * roundps $1, (%rax), %xmm2
+# CHECK-NEXT: 1 4 1.00 roundsd $1, %xmm0, %xmm2
+# CHECK-NEXT: 8 11 1.00 * roundsd $1, (%rax), %xmm2
+# CHECK-NEXT: 1 4 1.00 roundss $1, %xmm0, %xmm2
+# CHECK-NEXT: 8 11 1.00 * roundss $1, (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: 16.00 16.00 16.00 - - - - 45.50 72.50 13.00 9.00 16.33 16.33 16.33 19.50 19.50 3.33 3.33 3.33
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - blendpd $11, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - blendpd $11, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - blendps $11, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - blendps $11, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - blendvpd %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - blendvpd %xmm0, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - blendvps %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - blendvps %xmm0, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 8.00 - - - - - - - - - - dppd $22, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 - - 0.33 0.33 0.33 0.50 0.50 - - - dppd $22, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - dpps $22, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - dpps $22, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 2.50 - - - - - - - - - - extractps $1, %xmm0, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 1.50 - - 0.67 0.67 0.67 - - 0.67 0.67 0.67 extractps $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - insertps $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - insertps $1, (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - movntdqa (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 2.00 2.00 2.00 2.00 - - - - - - - - mpsadbw $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 2.00 2.00 2.00 2.00 0.33 0.33 0.33 0.50 0.50 - - - mpsadbw $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - packusdw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - packusdw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - pblendvb %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - pblendvb %xmm0, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pblendw $11, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pblendw $11, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pcmpeqq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pcmpeqq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 2.50 - - - - - - - - - - pextrb $1, %xmm0, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 1.50 - - 0.67 0.67 0.67 - - 0.67 0.67 0.67 pextrb $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - 0.50 2.50 - - - - - - - - - - pextrd $1, %xmm0, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 1.50 - - 0.67 0.67 0.67 - - 0.67 0.67 0.67 pextrd $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - 0.50 2.50 - - - - - - - - - - pextrq $1, %xmm0, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 1.50 - - 0.67 0.67 0.67 - - 0.67 0.67 0.67 pextrq $1, %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 1.50 - - 0.67 0.67 0.67 - - 0.67 0.67 0.67 pextrw $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - phminposuw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - phminposuw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - pinsrb $1, %eax, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - pinsrb $1, (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - pinsrd $1, %eax, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - pinsrd $1, (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - pinsrq $1, %rax, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - pinsrq $1, (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pmaxsb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pmaxsb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pmaxsd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pmaxsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pmaxud %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pmaxud (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pmaxuw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pmaxuw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pminsb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pminsb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pminsd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pminsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pminud %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pminud (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pminuw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pminuw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - pmovsxbd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - pmovsxbd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - pmovsxbq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - pmovsxbq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - pmovsxbw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - pmovsxbw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - pmovsxdq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - pmovsxdq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - pmovsxwd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - pmovsxwd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - pmovsxwq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - pmovsxwq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - pmovzxbd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - pmovzxbd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - pmovzxbq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - pmovzxbq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - pmovzxbw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - pmovzxbw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - pmovzxdq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - pmovzxdq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - pmovzxwd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - pmovzxwd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - pmovzxwq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - pmovzxwq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - pmuldq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - pmuldq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 2.00 - - - - - - - - - - - pmulld %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 2.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - pmulld (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 2.50 - - - - - - - - - - ptest %xmm0, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 2.50 - - 0.33 0.33 0.33 0.50 0.50 - - - ptest (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - roundpd $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - - - - - - - - - roundpd $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - roundps $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - - - - - - - - - roundps $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - roundsd $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - - - - - - - - - roundsd $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - roundss $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - - - - - - - - - roundss $1, (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse42.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse42.s
new file mode 100644
index 0000000000000..070b0aac36cbc
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse42.s
@@ -0,0 +1,110 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+crc32b %al, %ecx
+crc32b (%rax), %ecx
+
+crc32l %eax, %ecx
+crc32l (%rax), %ecx
+
+crc32w %ax, %ecx
+crc32w (%rax), %ecx
+
+crc32b %al, %rcx
+crc32b (%rax), %rcx
+
+crc32q %rax, %rcx
+crc32q (%rax), %rcx
+
+pcmpestri $1, %xmm0, %xmm2
+pcmpestri $1, (%rax), %xmm2
+
+pcmpestrm $1, %xmm0, %xmm2
+pcmpestrm $1, (%rax), %xmm2
+
+pcmpistri $1, %xmm0, %xmm2
+pcmpistri $1, (%rax), %xmm2
+
+pcmpistrm $1, %xmm0, %xmm2
+pcmpistrm $1, (%rax), %xmm2
+
+pcmpgtq %xmm0, %xmm2
+pcmpgtq (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 3 3 3.00 crc32b %al, %ecx
+# CHECK-NEXT: 3 7 3.00 * crc32b (%rax), %ecx
+# CHECK-NEXT: 3 3 3.00 crc32l %eax, %ecx
+# CHECK-NEXT: 3 7 3.00 * crc32l (%rax), %ecx
+# CHECK-NEXT: 3 3 3.00 crc32w %ax, %ecx
+# CHECK-NEXT: 3 7 3.00 * crc32w (%rax), %ecx
+# CHECK-NEXT: 3 3 3.00 crc32b %al, %rcx
+# CHECK-NEXT: 3 7 3.00 * crc32b (%rax), %rcx
+# CHECK-NEXT: 3 3 3.00 crc32q %rax, %rcx
+# CHECK-NEXT: 3 7 3.00 * crc32q (%rax), %rcx
+# CHECK-NEXT: 8 2 3.25 pcmpestri $1, %xmm0, %xmm2
+# CHECK-NEXT: 8 9 3.25 * pcmpestri $1, (%rax), %xmm2
+# CHECK-NEXT: 8 8 6.25 pcmpestrm $1, %xmm0, %xmm2
+# CHECK-NEXT: 8 15 6.25 * pcmpestrm $1, (%rax), %xmm2
+# CHECK-NEXT: 2 1 2.00 pcmpistri $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 8 2.00 * pcmpistri $1, (%rax), %xmm2
+# CHECK-NEXT: 3 7 6.25 pcmpistrm $1, %xmm0, %xmm2
+# CHECK-NEXT: 3 14 6.25 * pcmpistrm $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pcmpgtq (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: 3.33 3.33 3.33 - - - 30.00 36.00 36.00 36.00 36.00 3.33 3.33 3.33 5.00 5.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: - - - - - - 3.00 - - - - - - - - - - - - crc32b %al, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - 3.00 - - - - 0.33 0.33 0.33 0.50 0.50 - - - crc32b (%rax), %ecx
+# CHECK-NEXT: - - - - - - 3.00 - - - - - - - - - - - - crc32l %eax, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - 3.00 - - - - 0.33 0.33 0.33 0.50 0.50 - - - crc32l (%rax), %ecx
+# CHECK-NEXT: - - - - - - 3.00 - - - - - - - - - - - - crc32w %ax, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - 3.00 - - - - 0.33 0.33 0.33 0.50 0.50 - - - crc32w (%rax), %ecx
+# CHECK-NEXT: - - - - - - 3.00 - - - - - - - - - - - - crc32b %al, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - 3.00 - - - - 0.33 0.33 0.33 0.50 0.50 - - - crc32b (%rax), %rcx
+# CHECK-NEXT: - - - - - - 3.00 - - - - - - - - - - - - crc32q %rax, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - 3.00 - - - - 0.33 0.33 0.33 0.50 0.50 - - - crc32q (%rax), %rcx
+# CHECK-NEXT: - - - - - - - 3.25 3.25 3.25 3.25 - - - - - - - - pcmpestri $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 3.25 3.25 3.25 3.25 0.33 0.33 0.33 0.50 0.50 - - - pcmpestri $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 6.25 6.25 6.25 6.25 - - - - - - - - pcmpestrm $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 6.25 6.25 6.25 6.25 0.33 0.33 0.33 0.50 0.50 - - - pcmpestrm $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 2.00 2.00 2.00 2.00 - - - - - - - - pcmpistri $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 2.00 2.00 2.00 2.00 0.33 0.33 0.33 0.50 0.50 - - - pcmpistri $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 6.25 6.25 6.25 6.25 - - - - - - - - pcmpistrm $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 6.25 6.25 6.25 6.25 0.33 0.33 0.33 0.50 0.50 - - - pcmpistrm $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pcmpgtq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pcmpgtq (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse4a.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse4a.s
new file mode 100644
index 0000000000000..6ac045f4f3640
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse4a.s
@@ -0,0 +1,61 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+extrq %xmm0, %xmm2
+extrq $22, $2, %xmm2
+
+insertq %xmm0, %xmm2
+insertq $22, $22, %xmm0, %xmm2
+
+movntsd %xmm0, (%rax)
+movntss %xmm0, (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.25 extrq %xmm0, %xmm2
+# CHECK-NEXT: 1 3 0.25 extrq $22, $2, %xmm2
+# CHECK-NEXT: 1 3 0.25 insertq %xmm0, %xmm2
+# CHECK-NEXT: 1 3 0.25 insertq $22, $22, %xmm0, %xmm2
+# CHECK-NEXT: 1 5 1.00 * movntsd %xmm0, (%rax)
+# CHECK-NEXT: 1 5 1.00 * movntss %xmm0, (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: 0.67 0.67 0.67 - - - - 1.00 3.00 1.00 1.00 0.67 0.67 0.67 - - 0.67 0.67 0.67
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - extrq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - extrq $22, $2, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - insertq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - insertq $22, $22, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 movntsd %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 movntss %xmm0, (%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-ssse3.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-ssse3.s
new file mode 100644
index 0000000000000..c9408d820add8
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-ssse3.s
@@ -0,0 +1,264 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+pabsb %mm0, %mm2
+pabsb (%rax), %mm2
+
+pabsb %xmm0, %xmm2
+pabsb (%rax), %xmm2
+
+pabsd %mm0, %mm2
+pabsd (%rax), %mm2
+
+pabsd %xmm0, %xmm2
+pabsd (%rax), %xmm2
+
+pabsw %mm0, %mm2
+pabsw (%rax), %mm2
+
+pabsw %xmm0, %xmm2
+pabsw (%rax), %xmm2
+
+palignr $1, %mm0, %mm2
+palignr $1, (%rax), %mm2
+
+palignr $1, %xmm0, %xmm2
+palignr $1, (%rax), %xmm2
+
+phaddd %mm0, %mm2
+phaddd (%rax), %mm2
+
+phaddd %xmm0, %xmm2
+phaddd (%rax), %xmm2
+
+phaddsw %mm0, %mm2
+phaddsw (%rax), %mm2
+
+phaddsw %xmm0, %xmm2
+phaddsw (%rax), %xmm2
+
+phaddw %mm0, %mm2
+phaddw (%rax), %mm2
+
+phaddw %xmm0, %xmm2
+phaddw (%rax), %xmm2
+
+phsubd %mm0, %mm2
+phsubd (%rax), %mm2
+
+phsubd %xmm0, %xmm2
+phsubd (%rax), %xmm2
+
+phsubsw %mm0, %mm2
+phsubsw (%rax), %mm2
+
+phsubsw %xmm0, %xmm2
+phsubsw (%rax), %xmm2
+
+phsubw %mm0, %mm2
+phsubw (%rax), %mm2
+
+phsubw %xmm0, %xmm2
+phsubw (%rax), %xmm2
+
+pmaddubsw %mm0, %mm2
+pmaddubsw (%rax), %mm2
+
+pmaddubsw %xmm0, %xmm2
+pmaddubsw (%rax), %xmm2
+
+pmulhrsw %mm0, %mm2
+pmulhrsw (%rax), %mm2
+
+pmulhrsw %xmm0, %xmm2
+pmulhrsw (%rax), %xmm2
+
+pshufb %mm0, %mm2
+pshufb (%rax), %mm2
+
+pshufb %xmm0, %xmm2
+pshufb (%rax), %xmm2
+
+psignb %mm0, %mm2
+psignb (%rax), %mm2
+
+psignb %xmm0, %xmm2
+psignb (%rax), %xmm2
+
+psignd %mm0, %mm2
+psignd (%rax), %mm2
+
+psignd %xmm0, %xmm2
+psignd (%rax), %xmm2
+
+psignw %mm0, %mm2
+psignw (%rax), %mm2
+
+psignw %xmm0, %xmm2
+psignw (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.25 pabsb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pabsb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pabsb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pabsb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pabsd %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pabsd (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pabsd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pabsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pabsw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pabsw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pabsw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pabsw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 palignr $1, %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * palignr $1, (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 palignr $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * palignr $1, (%rax), %xmm2
+# CHECK-NEXT: 4 3 4.00 phaddd %mm0, %mm2
+# CHECK-NEXT: 7 10 4.00 * phaddd (%rax), %mm2
+# CHECK-NEXT: 4 3 4.00 phaddd %xmm0, %xmm2
+# CHECK-NEXT: 7 10 4.00 * phaddd (%rax), %xmm2
+# CHECK-NEXT: 4 3 4.00 phaddsw %mm0, %mm2
+# CHECK-NEXT: 7 10 4.00 * phaddsw (%rax), %mm2
+# CHECK-NEXT: 4 3 4.00 phaddsw %xmm0, %xmm2
+# CHECK-NEXT: 7 10 4.00 * phaddsw (%rax), %xmm2
+# CHECK-NEXT: 4 3 4.00 phaddw %mm0, %mm2
+# CHECK-NEXT: 7 10 4.00 * phaddw (%rax), %mm2
+# CHECK-NEXT: 4 3 4.00 phaddw %xmm0, %xmm2
+# CHECK-NEXT: 7 10 4.00 * phaddw (%rax), %xmm2
+# CHECK-NEXT: 4 3 4.00 phsubd %mm0, %mm2
+# CHECK-NEXT: 7 10 4.00 * phsubd (%rax), %mm2
+# CHECK-NEXT: 4 3 4.00 phsubd %xmm0, %xmm2
+# CHECK-NEXT: 7 10 4.00 * phsubd (%rax), %xmm2
+# CHECK-NEXT: 4 3 4.00 phsubsw %mm0, %mm2
+# CHECK-NEXT: 7 10 4.00 * phsubsw (%rax), %mm2
+# CHECK-NEXT: 4 3 4.00 phsubsw %xmm0, %xmm2
+# CHECK-NEXT: 7 10 4.00 * phsubsw (%rax), %xmm2
+# CHECK-NEXT: 4 3 4.00 phsubw %mm0, %mm2
+# CHECK-NEXT: 7 10 4.00 * phsubw (%rax), %mm2
+# CHECK-NEXT: 4 3 4.00 phsubw %xmm0, %xmm2
+# CHECK-NEXT: 7 10 4.00 * phsubw (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 pmaddubsw %mm0, %mm2
+# CHECK-NEXT: 1 10 1.00 * pmaddubsw (%rax), %mm2
+# CHECK-NEXT: 1 4 1.00 pmaddubsw %xmm0, %xmm2
+# CHECK-NEXT: 1 11 1.00 * pmaddubsw (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 pmulhrsw %mm0, %mm2
+# CHECK-NEXT: 1 10 1.00 * pmulhrsw (%rax), %mm2
+# CHECK-NEXT: 1 4 1.00 pmulhrsw %xmm0, %xmm2
+# CHECK-NEXT: 1 11 1.00 * pmulhrsw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pshufb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pshufb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 pshufb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pshufb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 psignb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psignb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 psignb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psignb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 psignd %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psignd (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 psignd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psignd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 psignw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psignw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 psignw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psignw (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: 10.67 10.67 10.67 - - - - 18.00 106.00 6.00 102.00 10.67 10.67 10.67 16.00 16.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pabsb %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pabsb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pabsb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pabsb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pabsd %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pabsd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pabsd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pabsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pabsw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pabsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - pabsw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - pabsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - palignr $1, %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - palignr $1, (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - palignr $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - palignr $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - phaddd %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - phaddd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - phaddd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - phaddd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - phaddsw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - phaddsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - phaddsw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - phaddsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - phaddw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - phaddw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - phaddw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - phaddw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - phsubd %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - phsubd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - phsubd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - phsubd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - phsubsw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - phsubsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - phsubsw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - phsubsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - phsubw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - phsubw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - phsubw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 0.33 0.33 0.33 0.50 0.50 - - - phsubw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - pmaddubsw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - pmaddubsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - pmaddubsw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - pmaddubsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - pmulhrsw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - pmulhrsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - pmulhrsw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 1.00 - - - 0.33 0.33 0.33 0.50 0.50 - - - pmulhrsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - pshufb %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - pshufb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.50 0.50 - - - - - - - - - - pshufb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 0.50 - - 0.33 0.33 0.33 0.50 0.50 - - - pshufb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - psignb %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - psignb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - psignb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - psignb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - psignd %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - psignd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - psignd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - psignd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - psignw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - psignw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - psignw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 0.50 0.50 - - - psignw (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-x86_32.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-x86_32.s
new file mode 100644
index 0000000000000..8a35d6e33c0b7
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-x86_32.s
@@ -0,0 +1,89 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=i686-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+aaa
+
+aad
+aad $7
+
+aam
+aam $7
+
+aas
+
+bound %bx, (%eax)
+bound %ebx, (%eax)
+
+daa
+
+das
+
+into
+
+leave
+
+salc
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 100 0.25 aaa
+# CHECK-NEXT: 1 100 0.25 aad
+# CHECK-NEXT: 1 100 0.25 aad $7
+# CHECK-NEXT: 1 100 0.25 aam
+# CHECK-NEXT: 1 100 0.25 aam $7
+# CHECK-NEXT: 1 100 0.25 aas
+# CHECK-NEXT: 1 100 0.25 U bound %bx, (%eax)
+# CHECK-NEXT: 1 100 0.25 U bound %ebx, (%eax)
+# CHECK-NEXT: 1 100 0.25 daa
+# CHECK-NEXT: 1 100 0.25 das
+# CHECK-NEXT: 1 100 0.25 U into
+# CHECK-NEXT: 1 1 0.17 * leave
+# CHECK-NEXT: 1 1 0.17 U salc
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: - - - 0.67 0.33 0.33 0.67 - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - aaa
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - aad
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - aad $7
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - aam
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - aam $7
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - aas
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - bound %bx, (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - bound %ebx, (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - daa
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - das
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - into
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leave
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - salc
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-x86_64.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-x86_64.s
new file mode 100644
index 0000000000000..516ab85e6dba8
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-x86_64.s
@@ -0,0 +1,2890 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+adcb $0, %al
+adcb $0, %dil
+adcb $0, (%rax)
+lock adcb $0, (%rax)
+adcb $7, %al
+adcb $7, %dil
+adcb $7, (%rax)
+lock adcb $7, (%rax)
+adcb %sil, %dil
+adcb %sil, (%rax)
+lock adcb %sil, (%rax)
+adcb (%rax), %dil
+
+adcw $0, %ax
+adcw $0, %di
+adcw $0, (%rax)
+lock adcw $0, (%rax)
+adcw $511, %ax
+adcw $511, %di
+adcw $511, (%rax)
+lock adcw $511, (%rax)
+adcw $7, %di
+adcw $7, (%rax)
+lock adcw $7, (%rax)
+adcw %si, %di
+adcw %si, (%rax)
+lock adcw %si, (%rax)
+adcw (%rax), %di
+
+adcl $0, %eax
+adcl $0, %edi
+adcl $0, (%rax)
+lock adcl $0, (%rax)
+adcl $665536, %eax
+adcl $665536, %edi
+adcl $665536, (%rax)
+lock adcl $665536, (%rax)
+adcl $7, %edi
+adcl $7, (%rax)
+lock adcl $7, (%rax)
+adcl %esi, %edi
+adcl %esi, (%rax)
+lock adcl %esi, (%rax)
+adcl (%rax), %edi
+
+adcq $0, %rax
+adcq $0, %rdi
+adcq $0, (%rax)
+lock adcq $0, (%rax)
+adcq $665536, %rax
+adcq $665536, %rdi
+adcq $665536, (%rax)
+lock adcq $665536, (%rax)
+adcq $7, %rdi
+adcq $7, (%rax)
+lock adcq $7, (%rax)
+adcq %rsi, %rdi
+adcq %rsi, (%rax)
+lock adcq %rsi, (%rax)
+adcq (%rax), %rdi
+
+addb $7, %al
+addb $7, %dil
+addb $7, (%rax)
+lock addb $7, (%rax)
+addb %sil, %dil
+addb %sil, (%rax)
+lock addb %sil, (%rax)
+addb (%rax), %dil
+
+addw $511, %ax
+addw $511, %di
+addw $511, (%rax)
+lock addw $511, (%rax)
+addw $7, %di
+addw $7, (%rax)
+lock addw $7, (%rax)
+addw %si, %di
+addw %si, (%rax)
+lock addw %si, (%rax)
+addw (%rax), %di
+
+addl $665536, %eax
+addl $665536, %edi
+addl $665536, (%rax)
+lock addl $665536, (%rax)
+addl $7, %edi
+addl $7, (%rax)
+lock addl $7, (%rax)
+addl %esi, %edi
+addl %esi, (%rax)
+lock addl %esi, (%rax)
+addl (%rax), %edi
+
+addq $665536, %rax
+addq $665536, %rdi
+addq $665536, (%rax)
+lock addq $665536, (%rax)
+addq $7, %rdi
+addq $7, (%rax)
+lock addq $7, (%rax)
+addq %rsi, %rdi
+addq %rsi, (%rax)
+lock addq %rsi, (%rax)
+addq (%rax), %rdi
+
+andb $7, %al
+andb $7, %dil
+andb $7, (%rax)
+lock andb $7, (%rax)
+andb %sil, %dil
+andb %sil, (%rax)
+lock andb %sil, (%rax)
+andb (%rax), %dil
+
+andw $511, %ax
+andw $511, %di
+andw $511, (%rax)
+lock andw $511, (%rax)
+andw $7, %di
+andw $7, (%rax)
+lock andw $7, (%rax)
+andw %si, %di
+andw %si, (%rax)
+lock andw %si, (%rax)
+andw (%rax), %di
+
+andl $665536, %eax
+andl $665536, %edi
+andl $665536, (%rax)
+lock andl $665536, (%rax)
+andl $7, %edi
+andl $7, (%rax)
+lock andl $7, (%rax)
+andl %esi, %edi
+andl %esi, (%rax)
+lock andl %esi, (%rax)
+andl (%rax), %edi
+
+andq $665536, %rax
+andq $665536, %rdi
+andq $665536, (%rax)
+lock andq $665536, (%rax)
+andq $7, %rdi
+andq $7, (%rax)
+lock andq $7, (%rax)
+andq %rsi, %rdi
+andq %rsi, (%rax)
+lock andq %rsi, (%rax)
+andq (%rax), %rdi
+
+bsfw %si, %di
+bsrw %si, %di
+bsfw (%rax), %di
+bsrw (%rax), %di
+
+bsfl %esi, %edi
+bsrl %esi, %edi
+bsfl (%rax), %edi
+bsrl (%rax), %edi
+
+bsfq %rsi, %rdi
+bsrq %rsi, %rdi
+bsfq (%rax), %rdi
+bsrq (%rax), %rdi
+
+bswap %eax
+bswap %rax
+
+btw %si, %di
+btcw %si, %di
+btrw %si, %di
+btsw %si, %di
+btw %si, (%rax)
+btcw %si, (%rax)
+btrw %si, (%rax)
+btsw %si, (%rax)
+lock btcw %si, (%rax)
+lock btrw %si, (%rax)
+lock btsw %si, (%rax)
+btw $7, %di
+btcw $7, %di
+btrw $7, %di
+btsw $7, %di
+btw $7, (%rax)
+btcw $7, (%rax)
+btrw $7, (%rax)
+btsw $7, (%rax)
+lock btcw $7, (%rax)
+lock btrw $7, (%rax)
+lock btsw $7, (%rax)
+
+btl %esi, %edi
+btcl %esi, %edi
+btrl %esi, %edi
+btsl %esi, %edi
+btl %esi, (%rax)
+btcl %esi, (%rax)
+btrl %esi, (%rax)
+btsl %esi, (%rax)
+lock btcl %esi, (%rax)
+lock btrl %esi, (%rax)
+lock btsl %esi, (%rax)
+btl $7, %edi
+btcl $7, %edi
+btrl $7, %edi
+btsl $7, %edi
+btl $7, (%rax)
+btcl $7, (%rax)
+btrl $7, (%rax)
+btsl $7, (%rax)
+lock btcl $7, (%rax)
+lock btrl $7, (%rax)
+lock btsl $7, (%rax)
+
+btq %rsi, %rdi
+btcq %rsi, %rdi
+btrq %rsi, %rdi
+btsq %rsi, %rdi
+btq %rsi, (%rax)
+btcq %rsi, (%rax)
+btrq %rsi, (%rax)
+btsq %rsi, (%rax)
+lock btcq %rsi, (%rax)
+lock btrq %rsi, (%rax)
+lock btsq %rsi, (%rax)
+btq $7, %rdi
+btcq $7, %rdi
+btrq $7, %rdi
+btsq $7, %rdi
+btq $7, (%rax)
+btcq $7, (%rax)
+btrq $7, (%rax)
+btsq $7, (%rax)
+lock btcq $7, (%rax)
+lock btrq $7, (%rax)
+lock btsq $7, (%rax)
+
+cbw
+cwde
+cdqe
+cwd
+cdq
+cqo
+
+clc
+cld
+cmc
+
+cmpb $7, %al
+cmpb $7, %dil
+cmpb $7, (%rax)
+cmpb %sil, %dil
+cmpb %sil, (%rax)
+cmpb (%rax), %dil
+
+cmpw $511, %ax
+cmpw $511, %di
+cmpw $511, (%rax)
+cmpw $7, %di
+cmpw $7, (%rax)
+cmpw %si, %di
+cmpw %si, (%rax)
+cmpw (%rax), %di
+
+cmpl $665536, %eax
+cmpl $665536, %edi
+cmpl $665536, (%rax)
+cmpl $7, %edi
+cmpl $7, (%rax)
+cmpl %esi, %edi
+cmpl %esi, (%rax)
+cmpl (%rax), %edi
+
+cmpq $665536, %rax
+cmpq $665536, %rdi
+cmpq $665536, (%rax)
+cmpq $7, %rdi
+cmpq $7, (%rax)
+cmpq %rsi, %rdi
+cmpq %rsi, (%rax)
+cmpq (%rax), %rdi
+
+cmpsb
+cmpsw
+cmpsl
+cmpsq
+
+cmpxchgb %cl, %bl
+cmpxchgb %cl, (%rbx)
+lock cmpxchgb %cl, (%rbx)
+
+cmpxchgw %cx, %bx
+cmpxchgw %cx, (%rbx)
+lock cmpxchgw %cx, (%rbx)
+
+cmpxchgl %ecx, %ebx
+cmpxchgl %ecx, (%rbx)
+lock cmpxchgl %ecx, (%rbx)
+
+cmpxchgq %rcx, %rbx
+cmpxchgq %rcx, (%rbx)
+lock cmpxchgq %rcx, (%rbx)
+
+cpuid
+
+decb %dil
+decb (%rax)
+lock decb (%rax)
+decw %di
+decw (%rax)
+lock decw (%rax)
+decl %edi
+decl (%rax)
+lock decl (%rax)
+decq %rdi
+decq (%rax)
+lock decq (%rax)
+
+divb %dil
+divb (%rax)
+divw %si
+divw (%rax)
+divl %edx
+divl (%rax)
+divq %rcx
+divq (%rax)
+
+enter $7, $4095
+
+idivb %dil
+idivb (%rax)
+idivw %si
+idivw (%rax)
+idivl %edx
+idivl (%rax)
+idivq %rcx
+idivq (%rax)
+
+imulb %dil
+imulb (%rax)
+
+imulw %di
+imulw (%rax)
+imulw %si, %di
+imulw (%rax), %di
+imulw $511, %si, %di
+imulw $511, (%rax), %di
+imulw $7, %si, %di
+imulw $7, (%rax), %di
+
+imull %edi
+imull (%rax)
+imull %esi, %edi
+imull (%rax), %edi
+imull $665536, %esi, %edi
+imull $665536, (%rax), %edi
+imull $7, %esi, %edi
+imull $7, (%rax), %edi
+
+imulq %rdi
+imulq (%rax)
+imulq %rsi, %rdi
+imulq (%rax), %rdi
+imulq $665536, %rsi, %rdi
+imulq $665536, (%rax), %rdi
+imulq $7, %rsi, %rdi
+imulq $7, (%rax), %rdi
+
+inb $7, %al
+inb %dx, %al
+inw $7, %ax
+inw %dx, %ax
+inl $7, %eax
+inl %dx, %eax
+
+incb %dil
+incb (%rax)
+lock incb (%rax)
+incw %di
+incw (%rax)
+lock incw (%rax)
+incl %edi
+incl (%rax)
+lock incl (%rax)
+incq %rdi
+incq (%rax)
+lock incq (%rax)
+
+insb
+insw
+insl
+
+int $7
+
+invlpg (%rax)
+invlpga %rax, %ecx
+
+lahf
+
+leave
+
+lodsb
+lodsw
+lodsl
+lodsq
+
+loop 0
+loope 0
+loopne 0
+
+movsb
+movsw
+movsl
+movsq
+
+movsbw %al, %di
+movzbw %al, %di
+movsbw (%rax), %di
+movzbw (%rax), %di
+movsbl %al, %edi
+movzbl %al, %edi
+movsbl (%rax), %edi
+movzbl (%rax), %edi
+movsbq %al, %rdi
+movzbq %al, %rdi
+movsbq (%rax), %rdi
+movzbq (%rax), %rdi
+
+movswl %ax, %edi
+movzwl %ax, %edi
+movswl (%rax), %edi
+movzwl (%rax), %edi
+movswq %ax, %rdi
+movzwq %ax, %rdi
+movswq (%rax), %rdi
+movzwq (%rax), %rdi
+
+movslq %eax, %rdi
+movslq (%rax), %rdi
+
+mulb %dil
+mulb (%rax)
+mulw %si
+mulw (%rax)
+mull %edx
+mull (%rax)
+mulq %rcx
+mulq (%rax)
+
+negb %dil
+negb (%r8)
+lock negb (%r8)
+negw %si
+negw (%r9)
+lock negw (%r9)
+negl %edx
+negl (%rax)
+lock negl (%rax)
+negq %rcx
+negq (%r10)
+lock negq (%r10)
+
+nop
+nopw %di
+nopw (%rcx)
+nopl %esi
+nopl (%r8)
+nopq %rdx
+nopq (%r9)
+
+notb %dil
+notb (%r8)
+lock notb (%r8)
+notw %si
+notw (%r9)
+lock notw (%r9)
+notl %edx
+notl (%rax)
+lock notl (%rax)
+notq %rcx
+notq (%r10)
+lock notq (%r10)
+
+orb $7, %al
+orb $7, %dil
+orb $7, (%rax)
+lock orb $7, (%rax)
+orb %sil, %dil
+orb %sil, (%rax)
+lock orb %sil, (%rax)
+orb (%rax), %dil
+
+orw $511, %ax
+orw $511, %di
+orw $511, (%rax)
+lock orw $511, (%rax)
+orw $7, %di
+orw $7, (%rax)
+lock orw $7, (%rax)
+orw %si, %di
+orw %si, (%rax)
+lock orw %si, (%rax)
+orw (%rax), %di
+
+orl $665536, %eax
+orl $665536, %edi
+orl $665536, (%rax)
+lock orl $665536, (%rax)
+orl $7, %edi
+orl $7, (%rax)
+lock orl $7, (%rax)
+orl %esi, %edi
+orl %esi, (%rax)
+lock orl %esi, (%rax)
+orl (%rax), %edi
+
+orq $665536, %rax
+orq $665536, %rdi
+orq $665536, (%rax)
+lock orq $665536, (%rax)
+orq $7, %rdi
+orq $7, (%rax)
+lock orq $7, (%rax)
+orq %rsi, %rdi
+orq %rsi, (%rax)
+lock orq %rsi, (%rax)
+orq (%rax), %rdi
+
+outb %al, $7
+outb %al, %dx
+outw %ax, $7
+outw %ax, %dx
+outl %eax, $7
+outl %eax, %dx
+
+outsb
+outsw
+outsl
+
+pause
+
+rclb %dil
+rcrb %dil
+rclb (%rax)
+rcrb (%rax)
+rclb $7, %dil
+rcrb $7, %dil
+rclb $7, (%rax)
+rcrb $7, (%rax)
+rclb %cl, %dil
+rcrb %cl, %dil
+rclb %cl, (%rax)
+rcrb %cl, (%rax)
+
+rclw %di
+rcrw %di
+rclw (%rax)
+rcrw (%rax)
+rclw $7, %di
+rcrw $7, %di
+rclw $7, (%rax)
+rcrw $7, (%rax)
+rclw %cl, %di
+rcrw %cl, %di
+rclw %cl, (%rax)
+rcrw %cl, (%rax)
+
+rcll %edi
+rcrl %edi
+rcll (%rax)
+rcrl (%rax)
+rcll $7, %edi
+rcrl $7, %edi
+rcll $7, (%rax)
+rcrl $7, (%rax)
+rcll %cl, %edi
+rcrl %cl, %edi
+rcll %cl, (%rax)
+rcrl %cl, (%rax)
+
+rclq %rdi
+rcrq %rdi
+rclq (%rax)
+rcrq (%rax)
+rclq $7, %rdi
+rcrq $7, %rdi
+rclq $7, (%rax)
+rcrq $7, (%rax)
+rclq %cl, %rdi
+rcrq %cl, %rdi
+rclq %cl, (%rax)
+rcrq %cl, (%rax)
+
+rdmsr
+rdpmc
+rdtsc
+rdtscp
+
+rolb %dil
+rorb %dil
+rolb (%rax)
+rorb (%rax)
+rolb $7, %dil
+rorb $7, %dil
+rolb $7, (%rax)
+rorb $7, (%rax)
+rolb %cl, %dil
+rorb %cl, %dil
+rolb %cl, (%rax)
+rorb %cl, (%rax)
+
+rolw %di
+rorw %di
+rolw (%rax)
+rorw (%rax)
+rolw $7, %di
+rorw $7, %di
+rolw $7, (%rax)
+rorw $7, (%rax)
+rolw %cl, %di
+rorw %cl, %di
+rolw %cl, (%rax)
+rorw %cl, (%rax)
+
+roll %edi
+rorl %edi
+roll (%rax)
+rorl (%rax)
+roll $7, %edi
+rorl $7, %edi
+roll $7, (%rax)
+rorl $7, (%rax)
+roll %cl, %edi
+rorl %cl, %edi
+roll %cl, (%rax)
+rorl %cl, (%rax)
+
+rolq %rdi
+rorq %rdi
+rolq (%rax)
+rorq (%rax)
+rolq $7, %rdi
+rorq $7, %rdi
+rolq $7, (%rax)
+rorq $7, (%rax)
+rolq %cl, %rdi
+rorq %cl, %rdi
+rolq %cl, (%rax)
+rorq %cl, (%rax)
+
+sahf
+
+sarb %dil
+shlb %dil
+shrb %dil
+sarb (%rax)
+shlb (%rax)
+shrb (%rax)
+sarb $7, %dil
+shlb $7, %dil
+shrb $7, %dil
+sarb $7, (%rax)
+shlb $7, (%rax)
+shrb $7, (%rax)
+sarb %cl, %dil
+shlb %cl, %dil
+shrb %cl, %dil
+sarb %cl, (%rax)
+shlb %cl, (%rax)
+shrb %cl, (%rax)
+
+sarw %di
+shlw %di
+shrw %di
+sarw (%rax)
+shlw (%rax)
+shrw (%rax)
+sarw $7, %di
+shlw $7, %di
+shrw $7, %di
+sarw $7, (%rax)
+shlw $7, (%rax)
+shrw $7, (%rax)
+sarw %cl, %di
+shlw %cl, %di
+shrw %cl, %di
+sarw %cl, (%rax)
+shlw %cl, (%rax)
+shrw %cl, (%rax)
+
+sarl %edi
+shll %edi
+shrl %edi
+sarl (%rax)
+shll (%rax)
+shrl (%rax)
+sarl $7, %edi
+shll $7, %edi
+shrl $7, %edi
+sarl $7, (%rax)
+shll $7, (%rax)
+shrl $7, (%rax)
+sarl %cl, %edi
+shll %cl, %edi
+shrl %cl, %edi
+sarl %cl, (%rax)
+shll %cl, (%rax)
+shrl %cl, (%rax)
+
+sarq %rdi
+shlq %rdi
+shrq %rdi
+sarq (%rax)
+shlq (%rax)
+shrq (%rax)
+sarq $7, %rdi
+shlq $7, %rdi
+shrq $7, %rdi
+sarq $7, (%rax)
+shlq $7, (%rax)
+shrq $7, (%rax)
+sarq %cl, %rdi
+shlq %cl, %rdi
+shrq %cl, %rdi
+sarq %cl, (%rax)
+shlq %cl, (%rax)
+shrq %cl, (%rax)
+
+sbbb $0, %al
+sbbb $0, %dil
+sbbb $0, (%rax)
+lock sbbb $0, (%rax)
+sbbb $7, %al
+sbbb $7, %dil
+sbbb $7, (%rax)
+lock sbbb $7, (%rax)
+sbbb %sil, %dil
+sbbb %sil, (%rax)
+lock sbbb %sil, (%rax)
+sbbb (%rax), %dil
+
+sbbw $0, %ax
+sbbw $0, %di
+sbbw $0, (%rax)
+lock sbbw $0, (%rax)
+sbbw $511, %ax
+sbbw $511, %di
+sbbw $511, (%rax)
+lock sbbw $511, (%rax)
+sbbw $7, %di
+sbbw $7, (%rax)
+lock sbbw $7, (%rax)
+sbbw %si, %di
+sbbw %si, (%rax)
+lock sbbw %si, (%rax)
+sbbw (%rax), %di
+
+sbbl $0, %eax
+sbbl $0, %edi
+sbbl $0, (%rax)
+lock sbbl $0, (%rax)
+sbbl $665536, %eax
+sbbl $665536, %edi
+sbbl $665536, (%rax)
+lock sbbl $665536, (%rax)
+sbbl $7, %edi
+sbbl $7, (%rax)
+lock sbbl $7, (%rax)
+sbbl %esi, %edi
+sbbl %esi, (%rax)
+lock sbbl %esi, (%rax)
+sbbl (%rax), %edi
+
+sbbq $0, %rax
+sbbq $0, %rdi
+sbbq $0, (%rax)
+lock sbbq $0, (%rax)
+sbbq $665536, %rax
+sbbq $665536, %rdi
+sbbq $665536, (%rax)
+lock sbbq $665536, (%rax)
+sbbq $7, %rdi
+sbbq $7, (%rax)
+lock sbbq $7, (%rax)
+sbbq %rsi, %rdi
+sbbq %rsi, (%rax)
+lock sbbq %rsi, (%rax)
+sbbq (%rax), %rdi
+
+scasb
+scasw
+scasl
+scasq
+
+seto %al
+seto (%rax)
+setno %al
+setno (%rax)
+setb %al
+setb (%rax)
+setnb %al
+setnb (%rax)
+setz %al
+setz (%rax)
+setnz %al
+setnz (%rax)
+seta %al
+seta (%rax)
+setna %al
+setna (%rax)
+sets %al
+sets (%rax)
+setns %al
+setns (%rax)
+setp %al
+setp (%rax)
+setnp %al
+setnp (%rax)
+setl %al
+setl (%rax)
+setnl %al
+setnl (%rax)
+setg %al
+setg (%rax)
+setng %al
+setng (%rax)
+
+shldw %cl, %si, %di
+shrdw %cl, %si, %di
+shldw %cl, %si, (%rax)
+shrdw %cl, %si, (%rax)
+shldw $7, %si, %di
+shrdw $7, %si, %di
+shldw $7, %si, (%rax)
+shrdw $7, %si, (%rax)
+
+shldl %cl, %esi, %edi
+shrdl %cl, %esi, %edi
+shldl %cl, %esi, (%rax)
+shrdl %cl, %esi, (%rax)
+shldl $7, %esi, %edi
+shrdl $7, %esi, %edi
+shldl $7, %esi, (%rax)
+shrdl $7, %esi, (%rax)
+
+shldq %cl, %rsi, %rdi
+shrdq %cl, %rsi, %rdi
+shldq %cl, %rsi, (%rax)
+shrdq %cl, %rsi, (%rax)
+shldq $7, %rsi, %rdi
+shrdq $7, %rsi, %rdi
+shldq $7, %rsi, (%rax)
+shrdq $7, %rsi, (%rax)
+
+stc
+std
+
+stosb
+stosw
+stosl
+stosq
+
+subb $7, %al
+subb $7, %dil
+subb $7, (%rax)
+lock subb $7, (%rax)
+subb %sil, %dil
+subb %sil, (%rax)
+lock subb %sil, (%rax)
+subb (%rax), %dil
+
+subw $511, %ax
+subw $511, %di
+subw $511, (%rax)
+lock subw $511, (%rax)
+subw $7, %di
+subw $7, (%rax)
+lock subw $7, (%rax)
+subw %si, %di
+subw %si, (%rax)
+lock subw %si, (%rax)
+subw (%rax), %di
+
+subl $665536, %eax
+subl $665536, %edi
+subl $665536, (%rax)
+lock subl $665536, (%rax)
+subl $7, %edi
+subl $7, (%rax)
+lock subl $7, (%rax)
+subl %esi, %edi
+subl %esi, (%rax)
+lock subl %esi, (%rax)
+subl (%rax), %edi
+
+subq $665536, %rax
+subq $665536, %rdi
+subq $665536, (%rax)
+lock subq $665536, (%rax)
+subq $7, %rdi
+subq $7, (%rax)
+lock subq $7, (%rax)
+subq %rsi, %rdi
+subq %rsi, (%rax)
+lock subq %rsi, (%rax)
+subq (%rax), %rdi
+
+testb $7, %al
+testb $7, %dil
+testb $7, (%rax)
+testb %sil, %dil
+testb %sil, (%rax)
+
+testw $511, %ax
+testw $511, %di
+testw $511, (%rax)
+testw $7, %di
+testw $7, (%rax)
+testw %si, %di
+testw %si, (%rax)
+
+testl $665536, %eax
+testl $665536, %edi
+testl $665536, (%rax)
+testl $7, %edi
+testl $7, (%rax)
+testl %esi, %edi
+testl %esi, (%rax)
+
+testq $665536, %rax
+testq $665536, %rdi
+testq $665536, (%rax)
+testq $7, %rdi
+testq $7, (%rax)
+testq %rsi, %rdi
+testq %rsi, (%rax)
+
+ud2
+
+wrmsr
+
+xaddb %bl, %cl
+xaddb %bl, (%rcx)
+lock xaddb %bl, (%rcx)
+
+xaddw %bx, %cx
+xaddw %ax, (%rbx)
+lock xaddw %ax, (%rbx)
+
+xaddl %ebx, %ecx
+xaddl %eax, (%rbx)
+lock xaddl %eax, (%rbx)
+
+xaddq %rbx, %rcx
+xaddq %rax, (%rbx)
+lock xaddq %rax, (%rbx)
+
+xchgb %bl, %cl
+xchgb %bl, (%rbx)
+lock xchgb %bl, (%rbx)
+
+xchgw %ax, %bx
+xchgw %bx, %cx
+xchgw %ax, (%rbx)
+lock xchgw %ax, (%rbx)
+
+xchgl %eax, %ebx
+xchgl %ebx, %ecx
+xchgl %eax, (%rbx)
+lock xchgl %eax, (%rbx)
+
+xchgq %rax, %rbx
+xchgq %rbx, %rcx
+xchgq %rax, (%rbx)
+lock xchgq %rax, (%rbx)
+
+xlatb
+
+xorb $7, %al
+xorb $7, %dil
+xorb $7, (%rax)
+lock xorb $7, (%rax)
+xorb %sil, %dil
+xorb %sil, (%rax)
+lock xorb %sil, (%rax)
+xorb (%rax), %dil
+
+xorw $511, %ax
+xorw $511, %di
+xorw $511, (%rax)
+lock xorw $511, (%rax)
+xorw $7, %di
+xorw $7, (%rax)
+lock xorw $7, (%rax)
+xorw %si, %di
+xorw %si, (%rax)
+lock xorw %si, (%rax)
+xorw (%rax), %di
+
+xorl $665536, %eax
+xorl $665536, %edi
+xorl $665536, (%rax)
+lock xorl $665536, (%rax)
+xorl $7, %edi
+xorl $7, (%rax)
+lock xorl $7, (%rax)
+xorl %esi, %edi
+xorl %esi, (%rax)
+lock xorl %esi, (%rax)
+xorl (%rax), %edi
+
+xorq $665536, %rax
+xorq $665536, %rdi
+xorq $665536, (%rax)
+lock xorq $665536, (%rax)
+xorq $7, %rdi
+xorq $7, (%rax)
+lock xorq $7, (%rax)
+xorq %rsi, %rdi
+xorq %rsi, (%rax)
+lock xorq %rsi, (%rax)
+xorq (%rax), %rdi
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.17 adcb $0, %al
+# CHECK-NEXT: 1 1 0.17 adcb $0, %dil
+# CHECK-NEXT: 2 6 0.67 * * adcb $0, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock adcb $0, (%rax)
+# CHECK-NEXT: 1 1 0.17 adcb $7, %al
+# CHECK-NEXT: 1 1 0.17 adcb $7, %dil
+# CHECK-NEXT: 2 6 0.67 * * adcb $7, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock adcb $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 adcb %sil, %dil
+# CHECK-NEXT: 2 6 0.67 * * adcb %sil, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock adcb %sil, (%rax)
+# CHECK-NEXT: 1 5 0.50 * adcb (%rax), %dil
+# CHECK-NEXT: 1 1 0.17 adcw $0, %ax
+# CHECK-NEXT: 1 1 0.17 adcw $0, %di
+# CHECK-NEXT: 2 6 0.67 * * adcw $0, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock adcw $0, (%rax)
+# CHECK-NEXT: 1 1 0.17 adcw $511, %ax
+# CHECK-NEXT: 1 1 0.17 adcw $511, %di
+# CHECK-NEXT: 2 6 0.67 * * adcw $511, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock adcw $511, (%rax)
+# CHECK-NEXT: 1 1 0.17 adcw $7, %di
+# CHECK-NEXT: 2 6 0.67 * * adcw $7, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock adcw $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 adcw %si, %di
+# CHECK-NEXT: 2 6 0.67 * * adcw %si, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock adcw %si, (%rax)
+# CHECK-NEXT: 1 5 0.50 * adcw (%rax), %di
+# CHECK-NEXT: 1 1 0.17 adcl $0, %eax
+# CHECK-NEXT: 1 1 0.17 adcl $0, %edi
+# CHECK-NEXT: 2 6 0.67 * * adcl $0, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock adcl $0, (%rax)
+# CHECK-NEXT: 1 1 0.17 adcl $665536, %eax
+# CHECK-NEXT: 1 1 0.17 adcl $665536, %edi
+# CHECK-NEXT: 2 6 0.67 * * adcl $665536, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock adcl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.17 adcl $7, %edi
+# CHECK-NEXT: 2 6 0.67 * * adcl $7, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock adcl $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 adcl %esi, %edi
+# CHECK-NEXT: 2 6 0.67 * * adcl %esi, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock adcl %esi, (%rax)
+# CHECK-NEXT: 1 5 0.50 * adcl (%rax), %edi
+# CHECK-NEXT: 1 1 0.17 adcq $0, %rax
+# CHECK-NEXT: 1 1 0.17 adcq $0, %rdi
+# CHECK-NEXT: 2 6 0.67 * * adcq $0, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock adcq $0, (%rax)
+# CHECK-NEXT: 1 1 0.17 adcq $665536, %rax
+# CHECK-NEXT: 1 1 0.17 adcq $665536, %rdi
+# CHECK-NEXT: 2 6 0.67 * * adcq $665536, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock adcq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.17 adcq $7, %rdi
+# CHECK-NEXT: 2 6 0.67 * * adcq $7, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock adcq $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 adcq %rsi, %rdi
+# CHECK-NEXT: 2 6 0.67 * * adcq %rsi, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock adcq %rsi, (%rax)
+# CHECK-NEXT: 1 5 0.50 * adcq (%rax), %rdi
+# CHECK-NEXT: 1 1 0.17 addb $7, %al
+# CHECK-NEXT: 1 1 0.17 addb $7, %dil
+# CHECK-NEXT: 2 6 0.67 * * addb $7, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock addb $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 addb %sil, %dil
+# CHECK-NEXT: 2 6 0.67 * * addb %sil, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock addb %sil, (%rax)
+# CHECK-NEXT: 1 5 0.50 * addb (%rax), %dil
+# CHECK-NEXT: 1 1 0.17 addw $511, %ax
+# CHECK-NEXT: 1 1 0.17 addw $511, %di
+# CHECK-NEXT: 2 6 0.67 * * addw $511, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock addw $511, (%rax)
+# CHECK-NEXT: 1 1 0.17 addw $7, %di
+# CHECK-NEXT: 2 6 0.67 * * addw $7, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock addw $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 addw %si, %di
+# CHECK-NEXT: 2 6 0.67 * * addw %si, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock addw %si, (%rax)
+# CHECK-NEXT: 1 5 0.50 * addw (%rax), %di
+# CHECK-NEXT: 1 1 0.17 addl $665536, %eax
+# CHECK-NEXT: 1 1 0.17 addl $665536, %edi
+# CHECK-NEXT: 2 6 0.67 * * addl $665536, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock addl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.17 addl $7, %edi
+# CHECK-NEXT: 2 6 0.67 * * addl $7, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock addl $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 addl %esi, %edi
+# CHECK-NEXT: 2 6 0.67 * * addl %esi, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock addl %esi, (%rax)
+# CHECK-NEXT: 1 5 0.50 * addl (%rax), %edi
+# CHECK-NEXT: 1 1 0.17 addq $665536, %rax
+# CHECK-NEXT: 1 1 0.17 addq $665536, %rdi
+# CHECK-NEXT: 2 6 0.67 * * addq $665536, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock addq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.17 addq $7, %rdi
+# CHECK-NEXT: 2 6 0.67 * * addq $7, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock addq $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 addq %rsi, %rdi
+# CHECK-NEXT: 2 6 0.67 * * addq %rsi, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock addq %rsi, (%rax)
+# CHECK-NEXT: 1 5 0.50 * addq (%rax), %rdi
+# CHECK-NEXT: 1 1 0.17 andb $7, %al
+# CHECK-NEXT: 1 1 0.17 andb $7, %dil
+# CHECK-NEXT: 2 6 0.67 * * andb $7, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock andb $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 andb %sil, %dil
+# CHECK-NEXT: 2 6 0.67 * * andb %sil, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock andb %sil, (%rax)
+# CHECK-NEXT: 1 5 0.50 * andb (%rax), %dil
+# CHECK-NEXT: 1 1 0.17 andw $511, %ax
+# CHECK-NEXT: 1 1 0.17 andw $511, %di
+# CHECK-NEXT: 2 6 0.67 * * andw $511, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock andw $511, (%rax)
+# CHECK-NEXT: 1 1 0.17 andw $7, %di
+# CHECK-NEXT: 2 6 0.67 * * andw $7, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock andw $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 andw %si, %di
+# CHECK-NEXT: 2 6 0.67 * * andw %si, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock andw %si, (%rax)
+# CHECK-NEXT: 1 5 0.50 * andw (%rax), %di
+# CHECK-NEXT: 1 1 0.17 andl $665536, %eax
+# CHECK-NEXT: 1 1 0.17 andl $665536, %edi
+# CHECK-NEXT: 2 6 0.67 * * andl $665536, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock andl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.17 andl $7, %edi
+# CHECK-NEXT: 2 6 0.67 * * andl $7, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock andl $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 andl %esi, %edi
+# CHECK-NEXT: 2 6 0.67 * * andl %esi, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock andl %esi, (%rax)
+# CHECK-NEXT: 1 5 0.50 * andl (%rax), %edi
+# CHECK-NEXT: 1 1 0.17 andq $665536, %rax
+# CHECK-NEXT: 1 1 0.17 andq $665536, %rdi
+# CHECK-NEXT: 2 6 0.67 * * andq $665536, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock andq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.17 andq $7, %rdi
+# CHECK-NEXT: 2 6 0.67 * * andq $7, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock andq $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 andq %rsi, %rdi
+# CHECK-NEXT: 2 6 0.67 * * andq %rsi, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock andq %rsi, (%rax)
+# CHECK-NEXT: 1 5 0.50 * andq (%rax), %rdi
+# CHECK-NEXT: 6 3 2.00 bsfw %si, %di
+# CHECK-NEXT: 6 4 2.67 bsrw %si, %di
+# CHECK-NEXT: 10 7 2.00 * bsfw (%rax), %di
+# CHECK-NEXT: 10 8 2.67 * bsrw (%rax), %di
+# CHECK-NEXT: 6 3 2.00 bsfl %esi, %edi
+# CHECK-NEXT: 6 4 2.67 bsrl %esi, %edi
+# CHECK-NEXT: 10 7 2.00 * bsfl (%rax), %edi
+# CHECK-NEXT: 10 8 2.67 * bsrl (%rax), %edi
+# CHECK-NEXT: 6 3 2.00 bsfq %rsi, %rdi
+# CHECK-NEXT: 6 4 2.67 bsrq %rsi, %rdi
+# CHECK-NEXT: 10 7 2.00 * bsfq (%rax), %rdi
+# CHECK-NEXT: 10 8 2.67 * bsrq (%rax), %rdi
+# CHECK-NEXT: 1 1 0.67 bswapl %eax
+# CHECK-NEXT: 1 1 0.67 bswapq %rax
+# CHECK-NEXT: 1 1 0.17 btw %si, %di
+# CHECK-NEXT: 2 2 0.17 btcw %si, %di
+# CHECK-NEXT: 2 2 0.17 btrw %si, %di
+# CHECK-NEXT: 2 2 0.17 btsw %si, %di
+# CHECK-NEXT: 7 5 0.50 * btw %si, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * btcw %si, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * btrw %si, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * btsw %si, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * lock btcw %si, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * lock btrw %si, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * lock btsw %si, (%rax)
+# CHECK-NEXT: 1 1 0.17 btw $7, %di
+# CHECK-NEXT: 2 2 0.17 btcw $7, %di
+# CHECK-NEXT: 2 2 0.17 btrw $7, %di
+# CHECK-NEXT: 2 2 0.17 btsw $7, %di
+# CHECK-NEXT: 2 5 0.50 * btw $7, (%rax)
+# CHECK-NEXT: 3 7 0.67 * * btcw $7, (%rax)
+# CHECK-NEXT: 3 7 0.67 * * btrw $7, (%rax)
+# CHECK-NEXT: 3 7 0.67 * * btsw $7, (%rax)
+# CHECK-NEXT: 3 7 0.67 * * lock btcw $7, (%rax)
+# CHECK-NEXT: 3 7 0.67 * * lock btrw $7, (%rax)
+# CHECK-NEXT: 3 7 0.67 * * lock btsw $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 btl %esi, %edi
+# CHECK-NEXT: 2 2 0.17 btcl %esi, %edi
+# CHECK-NEXT: 2 2 0.17 btrl %esi, %edi
+# CHECK-NEXT: 2 2 0.17 btsl %esi, %edi
+# CHECK-NEXT: 7 5 0.50 * btl %esi, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * btcl %esi, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * btrl %esi, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * btsl %esi, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * lock btcl %esi, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * lock btrl %esi, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * lock btsl %esi, (%rax)
+# CHECK-NEXT: 1 1 0.17 btl $7, %edi
+# CHECK-NEXT: 2 2 0.17 btcl $7, %edi
+# CHECK-NEXT: 2 2 0.17 btrl $7, %edi
+# CHECK-NEXT: 2 2 0.17 btsl $7, %edi
+# CHECK-NEXT: 2 5 0.50 * btl $7, (%rax)
+# CHECK-NEXT: 3 7 0.67 * * btcl $7, (%rax)
+# CHECK-NEXT: 3 7 0.67 * * btrl $7, (%rax)
+# CHECK-NEXT: 3 7 0.67 * * btsl $7, (%rax)
+# CHECK-NEXT: 3 7 0.67 * * lock btcl $7, (%rax)
+# CHECK-NEXT: 3 7 0.67 * * lock btrl $7, (%rax)
+# CHECK-NEXT: 3 7 0.67 * * lock btsl $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 btq %rsi, %rdi
+# CHECK-NEXT: 2 2 0.17 btcq %rsi, %rdi
+# CHECK-NEXT: 2 2 0.17 btrq %rsi, %rdi
+# CHECK-NEXT: 2 2 0.17 btsq %rsi, %rdi
+# CHECK-NEXT: 7 5 0.50 * btq %rsi, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * btcq %rsi, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * btrq %rsi, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * btsq %rsi, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * lock btcq %rsi, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * lock btrq %rsi, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * lock btsq %rsi, (%rax)
+# CHECK-NEXT: 1 1 0.17 btq $7, %rdi
+# CHECK-NEXT: 2 2 0.17 btcq $7, %rdi
+# CHECK-NEXT: 2 2 0.17 btrq $7, %rdi
+# CHECK-NEXT: 2 2 0.17 btsq $7, %rdi
+# CHECK-NEXT: 2 5 0.50 * btq $7, (%rax)
+# CHECK-NEXT: 3 7 0.67 * * btcq $7, (%rax)
+# CHECK-NEXT: 3 7 0.67 * * btrq $7, (%rax)
+# CHECK-NEXT: 3 7 0.67 * * btsq $7, (%rax)
+# CHECK-NEXT: 3 7 0.67 * * lock btcq $7, (%rax)
+# CHECK-NEXT: 3 7 0.67 * * lock btrq $7, (%rax)
+# CHECK-NEXT: 3 7 0.67 * * lock btsq $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 cbtw
+# CHECK-NEXT: 1 1 0.17 cwtl
+# CHECK-NEXT: 1 1 0.17 cltq
+# CHECK-NEXT: 1 1 0.17 cwtd
+# CHECK-NEXT: 1 1 0.17 cltd
+# CHECK-NEXT: 1 1 0.17 cqto
+# CHECK-NEXT: 1 1 0.17 U clc
+# CHECK-NEXT: 1 1 0.17 U cld
+# CHECK-NEXT: 1 1 0.17 U cmc
+# CHECK-NEXT: 1 1 0.17 cmpb $7, %al
+# CHECK-NEXT: 1 1 0.17 cmpb $7, %dil
+# CHECK-NEXT: 1 5 0.50 * cmpb $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 cmpb %sil, %dil
+# CHECK-NEXT: 1 5 0.50 * cmpb %sil, (%rax)
+# CHECK-NEXT: 1 5 0.50 * cmpb (%rax), %dil
+# CHECK-NEXT: 1 1 0.17 cmpw $511, %ax
+# CHECK-NEXT: 1 1 0.17 cmpw $511, %di
+# CHECK-NEXT: 1 5 0.50 * cmpw $511, (%rax)
+# CHECK-NEXT: 1 1 0.17 cmpw $7, %di
+# CHECK-NEXT: 1 5 0.50 * cmpw $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 cmpw %si, %di
+# CHECK-NEXT: 1 5 0.50 * cmpw %si, (%rax)
+# CHECK-NEXT: 1 5 0.50 * cmpw (%rax), %di
+# CHECK-NEXT: 1 1 0.17 cmpl $665536, %eax
+# CHECK-NEXT: 1 1 0.17 cmpl $665536, %edi
+# CHECK-NEXT: 1 5 0.50 * cmpl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.17 cmpl $7, %edi
+# CHECK-NEXT: 1 5 0.50 * cmpl $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 cmpl %esi, %edi
+# CHECK-NEXT: 1 5 0.50 * cmpl %esi, (%rax)
+# CHECK-NEXT: 1 5 0.50 * cmpl (%rax), %edi
+# CHECK-NEXT: 1 1 0.17 cmpq $665536, %rax
+# CHECK-NEXT: 1 1 0.17 cmpq $665536, %rdi
+# CHECK-NEXT: 1 5 0.50 * cmpq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.17 cmpq $7, %rdi
+# CHECK-NEXT: 1 5 0.50 * cmpq $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 cmpq %rsi, %rdi
+# CHECK-NEXT: 1 5 0.50 * cmpq %rsi, (%rax)
+# CHECK-NEXT: 1 5 0.50 * cmpq (%rax), %rdi
+# CHECK-NEXT: 1 100 0.25 U cmpsb %es:(%rdi), (%rsi)
+# CHECK-NEXT: 1 100 0.25 U cmpsw %es:(%rdi), (%rsi)
+# CHECK-NEXT: 1 100 0.25 U cmpsl %es:(%rdi), (%rsi)
+# CHECK-NEXT: 1 100 0.25 U cmpsq %es:(%rdi), (%rsi)
+# CHECK-NEXT: 1 3 0.17 cmpxchgb %cl, %bl
+# CHECK-NEXT: 3 5 0.33 * * cmpxchgb %cl, (%rbx)
+# CHECK-NEXT: 3 5 0.33 * * lock cmpxchgb %cl, (%rbx)
+# CHECK-NEXT: 1 3 0.17 cmpxchgw %cx, %bx
+# CHECK-NEXT: 3 5 0.33 * * cmpxchgw %cx, (%rbx)
+# CHECK-NEXT: 3 5 0.33 * * lock cmpxchgw %cx, (%rbx)
+# CHECK-NEXT: 1 3 0.17 cmpxchgl %ecx, %ebx
+# CHECK-NEXT: 3 5 0.33 * * cmpxchgl %ecx, (%rbx)
+# CHECK-NEXT: 3 5 0.33 * * lock cmpxchgl %ecx, (%rbx)
+# CHECK-NEXT: 1 3 0.17 cmpxchgq %rcx, %rbx
+# CHECK-NEXT: 3 5 0.33 * * cmpxchgq %rcx, (%rbx)
+# CHECK-NEXT: 3 5 0.33 * * lock cmpxchgq %rcx, (%rbx)
+# CHECK-NEXT: 1 100 0.25 U cpuid
+# CHECK-NEXT: 1 1 0.17 decb %dil
+# CHECK-NEXT: 2 6 0.67 * * decb (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock decb (%rax)
+# CHECK-NEXT: 1 1 0.17 decw %di
+# CHECK-NEXT: 2 6 0.67 * * decw (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock decw (%rax)
+# CHECK-NEXT: 1 1 0.17 decl %edi
+# CHECK-NEXT: 2 6 0.67 * * decl (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock decl (%rax)
+# CHECK-NEXT: 1 1 0.17 decq %rdi
+# CHECK-NEXT: 2 6 0.67 * * decq (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock decq (%rax)
+# CHECK-NEXT: 2 12 12.00 U divb %dil
+# CHECK-NEXT: 2 16 12.00 * U divb (%rax)
+# CHECK-NEXT: 2 17 17.00 U divw %si
+# CHECK-NEXT: 2 21 17.00 * U divw (%rax)
+# CHECK-NEXT: 2 25 25.00 U divl %edx
+# CHECK-NEXT: 2 29 25.00 * U divl (%rax)
+# CHECK-NEXT: 1 41 41.00 U divq %rcx
+# CHECK-NEXT: 1 45 41.00 * U divq (%rax)
+# CHECK-NEXT: 1 100 0.25 U enter $7, $4095
+# CHECK-NEXT: 2 12 12.00 U idivb %dil
+# CHECK-NEXT: 2 16 12.00 * U idivb (%rax)
+# CHECK-NEXT: 2 17 17.00 U idivw %si
+# CHECK-NEXT: 2 21 17.00 * U idivw (%rax)
+# CHECK-NEXT: 2 25 25.00 U idivl %edx
+# CHECK-NEXT: 2 29 25.00 * U idivl (%rax)
+# CHECK-NEXT: 1 41 41.00 U idivq %rcx
+# CHECK-NEXT: 1 45 41.00 * U idivq (%rax)
+# CHECK-NEXT: 1 3 3.00 imulb %dil
+# CHECK-NEXT: 1 7 3.00 * imulb (%rax)
+# CHECK-NEXT: 1 3 3.00 imulw %di
+# CHECK-NEXT: 1 7 3.00 * imulw (%rax)
+# CHECK-NEXT: 1 3 1.00 imulw %si, %di
+# CHECK-NEXT: 1 7 1.00 * imulw (%rax), %di
+# CHECK-NEXT: 2 4 4.00 imulw $511, %si, %di
+# CHECK-NEXT: 2 8 4.00 * imulw $511, (%rax), %di
+# CHECK-NEXT: 2 4 4.00 imulw $7, %si, %di
+# CHECK-NEXT: 2 8 4.00 * imulw $7, (%rax), %di
+# CHECK-NEXT: 1 3 3.00 imull %edi
+# CHECK-NEXT: 1 7 3.00 * imull (%rax)
+# CHECK-NEXT: 1 3 1.00 imull %esi, %edi
+# CHECK-NEXT: 1 7 1.00 * imull (%rax), %edi
+# CHECK-NEXT: 2 3 3.00 imull $665536, %esi, %edi
+# CHECK-NEXT: 2 7 3.00 * imull $665536, (%rax), %edi
+# CHECK-NEXT: 2 3 3.00 imull $7, %esi, %edi
+# CHECK-NEXT: 2 7 3.00 * imull $7, (%rax), %edi
+# CHECK-NEXT: 1 3 3.00 imulq %rdi
+# CHECK-NEXT: 1 7 3.00 * imulq (%rax)
+# CHECK-NEXT: 1 3 1.00 imulq %rsi, %rdi
+# CHECK-NEXT: 1 7 1.00 * imulq (%rax), %rdi
+# CHECK-NEXT: 2 3 3.00 imulq $665536, %rsi, %rdi
+# CHECK-NEXT: 2 7 3.00 * imulq $665536, (%rax), %rdi
+# CHECK-NEXT: 2 3 3.00 imulq $7, %rsi, %rdi
+# CHECK-NEXT: 2 7 3.00 * imulq $7, (%rax), %rdi
+# CHECK-NEXT: 1 100 0.25 U inb $7, %al
+# CHECK-NEXT: 1 100 0.25 U inb %dx, %al
+# CHECK-NEXT: 1 100 0.25 U inw $7, %ax
+# CHECK-NEXT: 1 100 0.25 U inw %dx, %ax
+# CHECK-NEXT: 1 100 0.25 U inl $7, %eax
+# CHECK-NEXT: 1 100 0.25 U inl %dx, %eax
+# CHECK-NEXT: 1 1 0.17 incb %dil
+# CHECK-NEXT: 2 6 0.67 * * incb (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock incb (%rax)
+# CHECK-NEXT: 1 1 0.17 incw %di
+# CHECK-NEXT: 2 6 0.67 * * incw (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock incw (%rax)
+# CHECK-NEXT: 1 1 0.17 incl %edi
+# CHECK-NEXT: 2 6 0.67 * * incl (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock incl (%rax)
+# CHECK-NEXT: 1 1 0.17 incq %rdi
+# CHECK-NEXT: 2 6 0.67 * * incq (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock incq (%rax)
+# CHECK-NEXT: 1 100 0.25 U insb %dx, %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 U insw %dx, %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 U insl %dx, %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 * * U int $7
+# CHECK-NEXT: 1 100 0.25 U invlpg (%rax)
+# CHECK-NEXT: 1 100 0.25 U invlpga
+# CHECK-NEXT: 2 2 0.17 lahf
+# CHECK-NEXT: 1 1 0.17 * leave
+# CHECK-NEXT: 1 100 0.25 U lodsb (%rsi), %al
+# CHECK-NEXT: 1 100 0.25 U lodsw (%rsi), %ax
+# CHECK-NEXT: 1 100 0.25 U lodsl (%rsi), %eax
+# CHECK-NEXT: 1 100 0.25 U lodsq (%rsi), %rax
+# CHECK-NEXT: 1 1 0.17 U loop 0
+# CHECK-NEXT: 1 1 0.17 U loope 0
+# CHECK-NEXT: 1 1 0.17 U loopne 0
+# CHECK-NEXT: 1 100 0.25 U movsb (%rsi), %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 U movsw (%rsi), %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 U movsl (%rsi), %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 U movsq (%rsi), %es:(%rdi)
+# CHECK-NEXT: 1 1 0.17 movsbw %al, %di
+# CHECK-NEXT: 1 1 0.17 movzbw %al, %di
+# CHECK-NEXT: 1 5 0.50 * movsbw (%rax), %di
+# CHECK-NEXT: 1 5 0.50 * movzbw (%rax), %di
+# CHECK-NEXT: 1 1 0.17 movsbl %al, %edi
+# CHECK-NEXT: 1 1 0.17 movzbl %al, %edi
+# CHECK-NEXT: 1 5 0.50 * movsbl (%rax), %edi
+# CHECK-NEXT: 1 5 0.50 * movzbl (%rax), %edi
+# CHECK-NEXT: 1 1 0.17 movsbq %al, %rdi
+# CHECK-NEXT: 1 1 0.17 movzbq %al, %rdi
+# CHECK-NEXT: 1 5 0.50 * movsbq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.50 * movzbq (%rax), %rdi
+# CHECK-NEXT: 1 1 0.17 movswl %ax, %edi
+# CHECK-NEXT: 1 1 0.17 movzwl %ax, %edi
+# CHECK-NEXT: 1 5 0.50 * movswl (%rax), %edi
+# CHECK-NEXT: 1 5 0.50 * movzwl (%rax), %edi
+# CHECK-NEXT: 1 1 0.17 movswq %ax, %rdi
+# CHECK-NEXT: 1 1 0.17 movzwq %ax, %rdi
+# CHECK-NEXT: 1 5 0.50 * movswq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.50 * movzwq (%rax), %rdi
+# CHECK-NEXT: 1 1 0.17 movslq %eax, %rdi
+# CHECK-NEXT: 1 5 0.50 * movslq (%rax), %rdi
+# CHECK-NEXT: 1 3 3.00 mulb %dil
+# CHECK-NEXT: 1 7 3.00 * mulb (%rax)
+# CHECK-NEXT: 1 3 3.00 mulw %si
+# CHECK-NEXT: 1 7 3.00 * mulw (%rax)
+# CHECK-NEXT: 1 3 3.00 mull %edx
+# CHECK-NEXT: 1 7 3.00 * mull (%rax)
+# CHECK-NEXT: 1 3 3.00 mulq %rcx
+# CHECK-NEXT: 1 7 3.00 * mulq (%rax)
+# CHECK-NEXT: 1 1 0.17 negb %dil
+# CHECK-NEXT: 2 6 0.67 * * negb (%r8)
+# CHECK-NEXT: 2 6 0.67 * * lock negb (%r8)
+# CHECK-NEXT: 1 1 0.17 negw %si
+# CHECK-NEXT: 2 6 0.67 * * negw (%r9)
+# CHECK-NEXT: 2 6 0.67 * * lock negw (%r9)
+# CHECK-NEXT: 1 1 0.17 negl %edx
+# CHECK-NEXT: 2 6 0.67 * * negl (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock negl (%rax)
+# CHECK-NEXT: 1 1 0.17 negq %rcx
+# CHECK-NEXT: 2 6 0.67 * * negq (%r10)
+# CHECK-NEXT: 2 6 0.67 * * lock negq (%r10)
+# CHECK-NEXT: 1 1 0.25 nop
+# CHECK-NEXT: 1 1 0.25 nopw %di
+# CHECK-NEXT: 1 1 0.25 nopw (%rcx)
+# CHECK-NEXT: 1 1 0.25 nopl %esi
+# CHECK-NEXT: 1 1 0.25 nopl (%r8)
+# CHECK-NEXT: 1 1 0.25 nopq %rdx
+# CHECK-NEXT: 1 1 0.25 nopq (%r9)
+# CHECK-NEXT: 1 1 0.17 notb %dil
+# CHECK-NEXT: 2 6 0.67 * * notb (%r8)
+# CHECK-NEXT: 2 6 0.67 * * lock notb (%r8)
+# CHECK-NEXT: 1 1 0.17 notw %si
+# CHECK-NEXT: 2 6 0.67 * * notw (%r9)
+# CHECK-NEXT: 2 6 0.67 * * lock notw (%r9)
+# CHECK-NEXT: 1 1 0.17 notl %edx
+# CHECK-NEXT: 2 6 0.67 * * notl (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock notl (%rax)
+# CHECK-NEXT: 1 1 0.17 notq %rcx
+# CHECK-NEXT: 2 6 0.67 * * notq (%r10)
+# CHECK-NEXT: 2 6 0.67 * * lock notq (%r10)
+# CHECK-NEXT: 1 1 0.17 orb $7, %al
+# CHECK-NEXT: 1 1 0.17 orb $7, %dil
+# CHECK-NEXT: 2 6 0.67 * * orb $7, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock orb $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 orb %sil, %dil
+# CHECK-NEXT: 2 6 0.67 * * orb %sil, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock orb %sil, (%rax)
+# CHECK-NEXT: 1 5 0.50 * orb (%rax), %dil
+# CHECK-NEXT: 1 1 0.17 orw $511, %ax
+# CHECK-NEXT: 1 1 0.17 orw $511, %di
+# CHECK-NEXT: 2 6 0.67 * * orw $511, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock orw $511, (%rax)
+# CHECK-NEXT: 1 1 0.17 orw $7, %di
+# CHECK-NEXT: 2 6 0.67 * * orw $7, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock orw $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 orw %si, %di
+# CHECK-NEXT: 2 6 0.67 * * orw %si, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock orw %si, (%rax)
+# CHECK-NEXT: 1 5 0.50 * orw (%rax), %di
+# CHECK-NEXT: 1 1 0.17 orl $665536, %eax
+# CHECK-NEXT: 1 1 0.17 orl $665536, %edi
+# CHECK-NEXT: 2 6 0.67 * * orl $665536, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock orl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.17 orl $7, %edi
+# CHECK-NEXT: 2 6 0.67 * * orl $7, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock orl $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 orl %esi, %edi
+# CHECK-NEXT: 2 6 0.67 * * orl %esi, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock orl %esi, (%rax)
+# CHECK-NEXT: 1 5 0.50 * orl (%rax), %edi
+# CHECK-NEXT: 1 1 0.17 orq $665536, %rax
+# CHECK-NEXT: 1 1 0.17 orq $665536, %rdi
+# CHECK-NEXT: 2 6 0.67 * * orq $665536, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock orq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.17 orq $7, %rdi
+# CHECK-NEXT: 2 6 0.67 * * orq $7, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock orq $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 orq %rsi, %rdi
+# CHECK-NEXT: 2 6 0.67 * * orq %rsi, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock orq %rsi, (%rax)
+# CHECK-NEXT: 1 5 0.50 * orq (%rax), %rdi
+# CHECK-NEXT: 1 100 0.25 U outb %al, $7
+# CHECK-NEXT: 1 100 0.25 U outb %al, %dx
+# CHECK-NEXT: 1 100 0.25 U outw %ax, $7
+# CHECK-NEXT: 1 100 0.25 U outw %ax, %dx
+# CHECK-NEXT: 1 100 0.25 U outl %eax, $7
+# CHECK-NEXT: 1 100 0.25 U outl %eax, %dx
+# CHECK-NEXT: 1 100 0.25 U outsb (%rsi), %dx
+# CHECK-NEXT: 1 100 0.25 U outsw (%rsi), %dx
+# CHECK-NEXT: 1 100 0.25 U outsl (%rsi), %dx
+# CHECK-NEXT: 1 1 0.25 * * U pause
+# CHECK-NEXT: 1 1 0.17 rclb %dil
+# CHECK-NEXT: 1 1 0.17 rcrb %dil
+# CHECK-NEXT: 2 5 0.67 * * rclb (%rax)
+# CHECK-NEXT: 2 5 0.67 * * rcrb (%rax)
+# CHECK-NEXT: 1 1 0.17 rclb $7, %dil
+# CHECK-NEXT: 1 1 0.17 rcrb $7, %dil
+# CHECK-NEXT: 2 5 0.67 * * rclb $7, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * rcrb $7, (%rax)
+# CHECK-NEXT: 1 4 0.17 rclb %cl, %dil
+# CHECK-NEXT: 1 3 0.17 rcrb %cl, %dil
+# CHECK-NEXT: 1 11 0.50 * * rclb %cl, (%rax)
+# CHECK-NEXT: 1 10 0.50 * * rcrb %cl, (%rax)
+# CHECK-NEXT: 1 1 0.17 rclw %di
+# CHECK-NEXT: 1 1 0.17 rcrw %di
+# CHECK-NEXT: 2 5 0.67 * * rclw (%rax)
+# CHECK-NEXT: 2 5 0.67 * * rcrw (%rax)
+# CHECK-NEXT: 1 1 0.17 rclw $7, %di
+# CHECK-NEXT: 1 1 0.17 rcrw $7, %di
+# CHECK-NEXT: 2 5 0.67 * * rclw $7, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * rcrw $7, (%rax)
+# CHECK-NEXT: 1 4 0.17 rclw %cl, %di
+# CHECK-NEXT: 1 3 0.17 rcrw %cl, %di
+# CHECK-NEXT: 1 11 0.50 * * rclw %cl, (%rax)
+# CHECK-NEXT: 1 10 0.50 * * rcrw %cl, (%rax)
+# CHECK-NEXT: 1 1 0.17 rcll %edi
+# CHECK-NEXT: 1 1 0.17 rcrl %edi
+# CHECK-NEXT: 2 5 0.67 * * rcll (%rax)
+# CHECK-NEXT: 2 5 0.67 * * rcrl (%rax)
+# CHECK-NEXT: 1 1 0.17 rcll $7, %edi
+# CHECK-NEXT: 1 1 0.17 rcrl $7, %edi
+# CHECK-NEXT: 2 5 0.67 * * rcll $7, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * rcrl $7, (%rax)
+# CHECK-NEXT: 1 4 0.17 rcll %cl, %edi
+# CHECK-NEXT: 1 3 0.17 rcrl %cl, %edi
+# CHECK-NEXT: 1 11 0.50 * * rcll %cl, (%rax)
+# CHECK-NEXT: 1 10 0.50 * * rcrl %cl, (%rax)
+# CHECK-NEXT: 1 1 0.17 rclq %rdi
+# CHECK-NEXT: 1 1 0.17 rcrq %rdi
+# CHECK-NEXT: 2 5 0.67 * * rclq (%rax)
+# CHECK-NEXT: 2 5 0.67 * * rcrq (%rax)
+# CHECK-NEXT: 1 1 0.17 rclq $7, %rdi
+# CHECK-NEXT: 1 1 0.17 rcrq $7, %rdi
+# CHECK-NEXT: 2 5 0.67 * * rclq $7, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * rcrq $7, (%rax)
+# CHECK-NEXT: 1 4 0.17 rclq %cl, %rdi
+# CHECK-NEXT: 1 3 0.17 rcrq %cl, %rdi
+# CHECK-NEXT: 1 11 0.50 * * rclq %cl, (%rax)
+# CHECK-NEXT: 1 10 0.50 * * rcrq %cl, (%rax)
+# CHECK-NEXT: 1 100 0.25 U rdmsr
+# CHECK-NEXT: 1 100 0.25 U rdpmc
+# CHECK-NEXT: 1 100 0.25 U rdtsc
+# CHECK-NEXT: 1 100 0.25 U rdtscp
+# CHECK-NEXT: 1 1 0.17 rolb %dil
+# CHECK-NEXT: 1 1 0.17 rorb %dil
+# CHECK-NEXT: 2 5 0.67 * * rolb (%rax)
+# CHECK-NEXT: 2 5 0.67 * * rorb (%rax)
+# CHECK-NEXT: 1 1 0.17 rolb $7, %dil
+# CHECK-NEXT: 1 1 0.17 rorb $7, %dil
+# CHECK-NEXT: 2 5 0.67 * * rolb $7, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * rorb $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 rolb %cl, %dil
+# CHECK-NEXT: 1 1 0.17 rorb %cl, %dil
+# CHECK-NEXT: 2 5 0.67 * * rolb %cl, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * rorb %cl, (%rax)
+# CHECK-NEXT: 1 1 0.17 rolw %di
+# CHECK-NEXT: 1 1 0.17 rorw %di
+# CHECK-NEXT: 2 5 0.67 * * rolw (%rax)
+# CHECK-NEXT: 2 5 0.67 * * rorw (%rax)
+# CHECK-NEXT: 1 1 0.17 rolw $7, %di
+# CHECK-NEXT: 1 1 0.17 rorw $7, %di
+# CHECK-NEXT: 2 5 0.67 * * rolw $7, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * rorw $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 rolw %cl, %di
+# CHECK-NEXT: 1 1 0.17 rorw %cl, %di
+# CHECK-NEXT: 2 5 0.67 * * rolw %cl, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * rorw %cl, (%rax)
+# CHECK-NEXT: 1 1 0.17 roll %edi
+# CHECK-NEXT: 1 1 0.17 rorl %edi
+# CHECK-NEXT: 2 5 0.67 * * roll (%rax)
+# CHECK-NEXT: 2 5 0.67 * * rorl (%rax)
+# CHECK-NEXT: 1 1 0.17 roll $7, %edi
+# CHECK-NEXT: 1 1 0.17 rorl $7, %edi
+# CHECK-NEXT: 2 5 0.67 * * roll $7, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * rorl $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 roll %cl, %edi
+# CHECK-NEXT: 1 1 0.17 rorl %cl, %edi
+# CHECK-NEXT: 2 5 0.67 * * roll %cl, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * rorl %cl, (%rax)
+# CHECK-NEXT: 1 1 0.17 rolq %rdi
+# CHECK-NEXT: 1 1 0.17 rorq %rdi
+# CHECK-NEXT: 2 5 0.67 * * rolq (%rax)
+# CHECK-NEXT: 2 5 0.67 * * rorq (%rax)
+# CHECK-NEXT: 1 1 0.17 rolq $7, %rdi
+# CHECK-NEXT: 1 1 0.17 rorq $7, %rdi
+# CHECK-NEXT: 2 5 0.67 * * rolq $7, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * rorq $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 rolq %cl, %rdi
+# CHECK-NEXT: 1 1 0.17 rorq %cl, %rdi
+# CHECK-NEXT: 2 5 0.67 * * rolq %cl, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * rorq %cl, (%rax)
+# CHECK-NEXT: 2 2 0.17 sahf
+# CHECK-NEXT: 1 1 0.17 sarb %dil
+# CHECK-NEXT: 1 1 0.17 shlb %dil
+# CHECK-NEXT: 1 1 0.17 shrb %dil
+# CHECK-NEXT: 2 5 0.67 * * sarb (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shlb (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shrb (%rax)
+# CHECK-NEXT: 1 1 0.17 sarb $7, %dil
+# CHECK-NEXT: 1 1 0.17 shlb $7, %dil
+# CHECK-NEXT: 1 1 0.17 shrb $7, %dil
+# CHECK-NEXT: 2 5 0.67 * * sarb $7, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shlb $7, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shrb $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 sarb %cl, %dil
+# CHECK-NEXT: 1 1 0.17 shlb %cl, %dil
+# CHECK-NEXT: 1 1 0.17 shrb %cl, %dil
+# CHECK-NEXT: 2 5 0.67 * * sarb %cl, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shlb %cl, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shrb %cl, (%rax)
+# CHECK-NEXT: 1 1 0.17 sarw %di
+# CHECK-NEXT: 1 1 0.17 shlw %di
+# CHECK-NEXT: 1 1 0.17 shrw %di
+# CHECK-NEXT: 2 5 0.67 * * sarw (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shlw (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shrw (%rax)
+# CHECK-NEXT: 1 1 0.17 sarw $7, %di
+# CHECK-NEXT: 1 1 0.17 shlw $7, %di
+# CHECK-NEXT: 1 1 0.17 shrw $7, %di
+# CHECK-NEXT: 2 5 0.67 * * sarw $7, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shlw $7, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shrw $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 sarw %cl, %di
+# CHECK-NEXT: 1 1 0.17 shlw %cl, %di
+# CHECK-NEXT: 1 1 0.17 shrw %cl, %di
+# CHECK-NEXT: 2 5 0.67 * * sarw %cl, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shlw %cl, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shrw %cl, (%rax)
+# CHECK-NEXT: 1 1 0.17 sarl %edi
+# CHECK-NEXT: 1 1 0.17 shll %edi
+# CHECK-NEXT: 1 1 0.17 shrl %edi
+# CHECK-NEXT: 2 5 0.67 * * sarl (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shll (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shrl (%rax)
+# CHECK-NEXT: 1 1 0.17 sarl $7, %edi
+# CHECK-NEXT: 1 1 0.17 shll $7, %edi
+# CHECK-NEXT: 1 1 0.17 shrl $7, %edi
+# CHECK-NEXT: 2 5 0.67 * * sarl $7, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shll $7, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shrl $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 sarl %cl, %edi
+# CHECK-NEXT: 1 1 0.17 shll %cl, %edi
+# CHECK-NEXT: 1 1 0.17 shrl %cl, %edi
+# CHECK-NEXT: 2 5 0.67 * * sarl %cl, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shll %cl, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shrl %cl, (%rax)
+# CHECK-NEXT: 1 1 0.17 sarq %rdi
+# CHECK-NEXT: 1 1 0.17 shlq %rdi
+# CHECK-NEXT: 1 1 0.17 shrq %rdi
+# CHECK-NEXT: 2 5 0.67 * * sarq (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shlq (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shrq (%rax)
+# CHECK-NEXT: 1 1 0.17 sarq $7, %rdi
+# CHECK-NEXT: 1 1 0.17 shlq $7, %rdi
+# CHECK-NEXT: 1 1 0.17 shrq $7, %rdi
+# CHECK-NEXT: 2 5 0.67 * * sarq $7, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shlq $7, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shrq $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 sarq %cl, %rdi
+# CHECK-NEXT: 1 1 0.17 shlq %cl, %rdi
+# CHECK-NEXT: 1 1 0.17 shrq %cl, %rdi
+# CHECK-NEXT: 2 5 0.67 * * sarq %cl, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shlq %cl, (%rax)
+# CHECK-NEXT: 2 5 0.67 * * shrq %cl, (%rax)
+# CHECK-NEXT: 1 1 0.17 sbbb $0, %al
+# CHECK-NEXT: 1 1 0.17 sbbb $0, %dil
+# CHECK-NEXT: 2 6 0.67 * * sbbb $0, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock sbbb $0, (%rax)
+# CHECK-NEXT: 1 1 0.17 sbbb $7, %al
+# CHECK-NEXT: 1 1 0.17 sbbb $7, %dil
+# CHECK-NEXT: 2 6 0.67 * * sbbb $7, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock sbbb $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 sbbb %sil, %dil
+# CHECK-NEXT: 2 6 0.67 * * sbbb %sil, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock sbbb %sil, (%rax)
+# CHECK-NEXT: 1 5 0.50 * sbbb (%rax), %dil
+# CHECK-NEXT: 1 1 0.17 sbbw $0, %ax
+# CHECK-NEXT: 1 1 0.17 sbbw $0, %di
+# CHECK-NEXT: 2 6 0.67 * * sbbw $0, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock sbbw $0, (%rax)
+# CHECK-NEXT: 1 1 0.17 sbbw $511, %ax
+# CHECK-NEXT: 1 1 0.17 sbbw $511, %di
+# CHECK-NEXT: 2 6 0.67 * * sbbw $511, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock sbbw $511, (%rax)
+# CHECK-NEXT: 1 1 0.17 sbbw $7, %di
+# CHECK-NEXT: 2 6 0.67 * * sbbw $7, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock sbbw $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 sbbw %si, %di
+# CHECK-NEXT: 2 6 0.67 * * sbbw %si, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock sbbw %si, (%rax)
+# CHECK-NEXT: 1 5 0.50 * sbbw (%rax), %di
+# CHECK-NEXT: 1 1 0.17 sbbl $0, %eax
+# CHECK-NEXT: 1 1 0.17 sbbl $0, %edi
+# CHECK-NEXT: 2 6 0.67 * * sbbl $0, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock sbbl $0, (%rax)
+# CHECK-NEXT: 1 1 0.17 sbbl $665536, %eax
+# CHECK-NEXT: 1 1 0.17 sbbl $665536, %edi
+# CHECK-NEXT: 2 6 0.67 * * sbbl $665536, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock sbbl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.17 sbbl $7, %edi
+# CHECK-NEXT: 2 6 0.67 * * sbbl $7, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock sbbl $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 sbbl %esi, %edi
+# CHECK-NEXT: 2 6 0.67 * * sbbl %esi, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock sbbl %esi, (%rax)
+# CHECK-NEXT: 1 5 0.50 * sbbl (%rax), %edi
+# CHECK-NEXT: 1 1 0.17 sbbq $0, %rax
+# CHECK-NEXT: 1 1 0.17 sbbq $0, %rdi
+# CHECK-NEXT: 2 6 0.67 * * sbbq $0, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock sbbq $0, (%rax)
+# CHECK-NEXT: 1 1 0.17 sbbq $665536, %rax
+# CHECK-NEXT: 1 1 0.17 sbbq $665536, %rdi
+# CHECK-NEXT: 2 6 0.67 * * sbbq $665536, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock sbbq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.17 sbbq $7, %rdi
+# CHECK-NEXT: 2 6 0.67 * * sbbq $7, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock sbbq $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 sbbq %rsi, %rdi
+# CHECK-NEXT: 2 6 0.67 * * sbbq %rsi, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock sbbq %rsi, (%rax)
+# CHECK-NEXT: 1 5 0.50 * sbbq (%rax), %rdi
+# CHECK-NEXT: 1 100 0.25 U scasb %es:(%rdi), %al
+# CHECK-NEXT: 1 100 0.25 U scasw %es:(%rdi), %ax
+# CHECK-NEXT: 1 100 0.25 U scasl %es:(%rdi), %eax
+# CHECK-NEXT: 1 100 0.25 U scasq %es:(%rdi), %rax
+# CHECK-NEXT: 1 1 0.17 seto %al
+# CHECK-NEXT: 1 1 0.33 * seto (%rax)
+# CHECK-NEXT: 1 1 0.17 setno %al
+# CHECK-NEXT: 1 1 0.33 * setno (%rax)
+# CHECK-NEXT: 1 1 0.17 setb %al
+# CHECK-NEXT: 1 1 0.33 * setb (%rax)
+# CHECK-NEXT: 1 1 0.17 setae %al
+# CHECK-NEXT: 1 1 0.33 * setae (%rax)
+# CHECK-NEXT: 1 1 0.17 sete %al
+# CHECK-NEXT: 1 1 0.33 * sete (%rax)
+# CHECK-NEXT: 1 1 0.17 setne %al
+# CHECK-NEXT: 1 1 0.33 * setne (%rax)
+# CHECK-NEXT: 1 1 0.17 seta %al
+# CHECK-NEXT: 1 1 0.33 * seta (%rax)
+# CHECK-NEXT: 1 1 0.17 setbe %al
+# CHECK-NEXT: 1 1 0.33 * setbe (%rax)
+# CHECK-NEXT: 1 1 0.17 sets %al
+# CHECK-NEXT: 1 1 0.33 * sets (%rax)
+# CHECK-NEXT: 1 1 0.17 setns %al
+# CHECK-NEXT: 1 1 0.33 * setns (%rax)
+# CHECK-NEXT: 1 1 0.17 setp %al
+# CHECK-NEXT: 1 1 0.33 * setp (%rax)
+# CHECK-NEXT: 1 1 0.17 setnp %al
+# CHECK-NEXT: 1 1 0.33 * setnp (%rax)
+# CHECK-NEXT: 1 1 0.17 setl %al
+# CHECK-NEXT: 1 1 0.33 * setl (%rax)
+# CHECK-NEXT: 1 1 0.17 setge %al
+# CHECK-NEXT: 1 1 0.33 * setge (%rax)
+# CHECK-NEXT: 1 1 0.17 setg %al
+# CHECK-NEXT: 1 1 0.33 * setg (%rax)
+# CHECK-NEXT: 1 1 0.17 setle %al
+# CHECK-NEXT: 1 1 0.33 * setle (%rax)
+# CHECK-NEXT: 7 3 0.83 shldw %cl, %si, %di
+# CHECK-NEXT: 7 3 0.83 shrdw %cl, %si, %di
+# CHECK-NEXT: 8 5 0.83 * * shldw %cl, %si, (%rax)
+# CHECK-NEXT: 8 5 0.83 * * shrdw %cl, %si, (%rax)
+# CHECK-NEXT: 6 3 0.50 shldw $7, %si, %di
+# CHECK-NEXT: 6 3 0.50 shrdw $7, %si, %di
+# CHECK-NEXT: 8 5 0.83 * * shldw $7, %si, (%rax)
+# CHECK-NEXT: 8 5 0.83 * * shrdw $7, %si, (%rax)
+# CHECK-NEXT: 7 3 0.83 shldl %cl, %esi, %edi
+# CHECK-NEXT: 7 3 0.83 shrdl %cl, %esi, %edi
+# CHECK-NEXT: 8 5 0.83 * * shldl %cl, %esi, (%rax)
+# CHECK-NEXT: 8 5 0.83 * * shrdl %cl, %esi, (%rax)
+# CHECK-NEXT: 6 3 0.50 shldl $7, %esi, %edi
+# CHECK-NEXT: 6 3 0.50 shrdl $7, %esi, %edi
+# CHECK-NEXT: 8 5 0.83 * * shldl $7, %esi, (%rax)
+# CHECK-NEXT: 8 5 0.83 * * shrdl $7, %esi, (%rax)
+# CHECK-NEXT: 7 3 0.83 shldq %cl, %rsi, %rdi
+# CHECK-NEXT: 7 3 0.83 shrdq %cl, %rsi, %rdi
+# CHECK-NEXT: 8 5 0.83 * * shldq %cl, %rsi, (%rax)
+# CHECK-NEXT: 8 5 0.83 * * shrdq %cl, %rsi, (%rax)
+# CHECK-NEXT: 6 3 0.50 shldq $7, %rsi, %rdi
+# CHECK-NEXT: 6 3 0.50 shrdq $7, %rsi, %rdi
+# CHECK-NEXT: 8 5 0.83 * * shldq $7, %rsi, (%rax)
+# CHECK-NEXT: 8 5 0.83 * * shrdq $7, %rsi, (%rax)
+# CHECK-NEXT: 1 1 0.17 U stc
+# CHECK-NEXT: 1 1 0.17 U std
+# CHECK-NEXT: 1 100 0.25 U stosb %al, %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 U stosw %ax, %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 U stosl %eax, %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 U stosq %rax, %es:(%rdi)
+# CHECK-NEXT: 1 1 0.17 subb $7, %al
+# CHECK-NEXT: 1 1 0.17 subb $7, %dil
+# CHECK-NEXT: 2 6 0.67 * * subb $7, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock subb $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 subb %sil, %dil
+# CHECK-NEXT: 2 6 0.67 * * subb %sil, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock subb %sil, (%rax)
+# CHECK-NEXT: 1 5 0.50 * subb (%rax), %dil
+# CHECK-NEXT: 1 1 0.17 subw $511, %ax
+# CHECK-NEXT: 1 1 0.17 subw $511, %di
+# CHECK-NEXT: 2 6 0.67 * * subw $511, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock subw $511, (%rax)
+# CHECK-NEXT: 1 1 0.17 subw $7, %di
+# CHECK-NEXT: 2 6 0.67 * * subw $7, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock subw $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 subw %si, %di
+# CHECK-NEXT: 2 6 0.67 * * subw %si, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock subw %si, (%rax)
+# CHECK-NEXT: 1 5 0.50 * subw (%rax), %di
+# CHECK-NEXT: 1 1 0.17 subl $665536, %eax
+# CHECK-NEXT: 1 1 0.17 subl $665536, %edi
+# CHECK-NEXT: 2 6 0.67 * * subl $665536, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock subl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.17 subl $7, %edi
+# CHECK-NEXT: 2 6 0.67 * * subl $7, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock subl $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 subl %esi, %edi
+# CHECK-NEXT: 2 6 0.67 * * subl %esi, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock subl %esi, (%rax)
+# CHECK-NEXT: 1 5 0.50 * subl (%rax), %edi
+# CHECK-NEXT: 1 1 0.17 subq $665536, %rax
+# CHECK-NEXT: 1 1 0.17 subq $665536, %rdi
+# CHECK-NEXT: 2 6 0.67 * * subq $665536, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock subq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.17 subq $7, %rdi
+# CHECK-NEXT: 2 6 0.67 * * subq $7, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock subq $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 subq %rsi, %rdi
+# CHECK-NEXT: 2 6 0.67 * * subq %rsi, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock subq %rsi, (%rax)
+# CHECK-NEXT: 1 5 0.50 * subq (%rax), %rdi
+# CHECK-NEXT: 1 1 0.17 testb $7, %al
+# CHECK-NEXT: 1 1 0.17 testb $7, %dil
+# CHECK-NEXT: 1 5 0.50 * testb $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 testb %sil, %dil
+# CHECK-NEXT: 1 5 0.50 * testb %sil, (%rax)
+# CHECK-NEXT: 1 1 0.17 testw $511, %ax
+# CHECK-NEXT: 1 1 0.17 testw $511, %di
+# CHECK-NEXT: 1 5 0.50 * testw $511, (%rax)
+# CHECK-NEXT: 1 1 0.17 testw $7, %di
+# CHECK-NEXT: 1 5 0.50 * testw $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 testw %si, %di
+# CHECK-NEXT: 1 5 0.50 * testw %si, (%rax)
+# CHECK-NEXT: 1 1 0.17 testl $665536, %eax
+# CHECK-NEXT: 1 1 0.17 testl $665536, %edi
+# CHECK-NEXT: 1 5 0.50 * testl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.17 testl $7, %edi
+# CHECK-NEXT: 1 5 0.50 * testl $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 testl %esi, %edi
+# CHECK-NEXT: 1 5 0.50 * testl %esi, (%rax)
+# CHECK-NEXT: 1 1 0.17 testq $665536, %rax
+# CHECK-NEXT: 1 1 0.17 testq $665536, %rdi
+# CHECK-NEXT: 1 5 0.50 * testq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.17 testq $7, %rdi
+# CHECK-NEXT: 1 5 0.50 * testq $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 testq %rsi, %rdi
+# CHECK-NEXT: 1 5 0.50 * testq %rsi, (%rax)
+# CHECK-NEXT: 1 100 0.25 * U ud2
+# CHECK-NEXT: 1 100 0.25 U wrmsr
+# CHECK-NEXT: 1 1 0.33 xaddb %bl, %cl
+# CHECK-NEXT: 2 5 0.67 * * xaddb %bl, (%rcx)
+# CHECK-NEXT: 2 5 0.67 * * lock xaddb %bl, (%rcx)
+# CHECK-NEXT: 1 1 0.33 xaddw %bx, %cx
+# CHECK-NEXT: 2 5 0.67 * * xaddw %ax, (%rbx)
+# CHECK-NEXT: 2 5 0.67 * * lock xaddw %ax, (%rbx)
+# CHECK-NEXT: 1 1 0.33 xaddl %ebx, %ecx
+# CHECK-NEXT: 2 5 0.67 * * xaddl %eax, (%rbx)
+# CHECK-NEXT: 2 5 0.67 * * lock xaddl %eax, (%rbx)
+# CHECK-NEXT: 1 1 0.33 xaddq %rbx, %rcx
+# CHECK-NEXT: 2 5 0.67 * * xaddq %rax, (%rbx)
+# CHECK-NEXT: 2 5 0.67 * * lock xaddq %rax, (%rbx)
+# CHECK-NEXT: 1 1 0.33 xchgb %bl, %cl
+# CHECK-NEXT: 1 5 0.50 * * xchgb %bl, (%rbx)
+# CHECK-NEXT: 1 5 0.50 * * lock xchgb %bl, (%rbx)
+# CHECK-NEXT: 1 1 0.33 xchgw %bx, %ax
+# CHECK-NEXT: 1 1 0.33 xchgw %bx, %cx
+# CHECK-NEXT: 1 5 0.50 * * xchgw %ax, (%rbx)
+# CHECK-NEXT: 1 5 0.50 * * lock xchgw %ax, (%rbx)
+# CHECK-NEXT: 2 0 0.50 xchgl %ebx, %eax
+# CHECK-NEXT: 2 0 0.50 xchgl %ebx, %ecx
+# CHECK-NEXT: 1 5 0.50 * * xchgl %eax, (%rbx)
+# CHECK-NEXT: 1 5 0.50 * * lock xchgl %eax, (%rbx)
+# CHECK-NEXT: 2 0 0.50 xchgq %rbx, %rax
+# CHECK-NEXT: 2 0 0.50 xchgq %rbx, %rcx
+# CHECK-NEXT: 1 5 0.50 * * xchgq %rax, (%rbx)
+# CHECK-NEXT: 1 5 0.50 * * lock xchgq %rax, (%rbx)
+# CHECK-NEXT: 1 5 0.50 * xlatb
+# CHECK-NEXT: 1 1 0.17 xorb $7, %al
+# CHECK-NEXT: 1 1 0.17 xorb $7, %dil
+# CHECK-NEXT: 2 6 0.67 * * xorb $7, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock xorb $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 xorb %sil, %dil
+# CHECK-NEXT: 2 6 0.67 * * xorb %sil, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock xorb %sil, (%rax)
+# CHECK-NEXT: 1 5 0.50 * xorb (%rax), %dil
+# CHECK-NEXT: 1 1 0.17 xorw $511, %ax
+# CHECK-NEXT: 1 1 0.17 xorw $511, %di
+# CHECK-NEXT: 2 6 0.67 * * xorw $511, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock xorw $511, (%rax)
+# CHECK-NEXT: 1 1 0.17 xorw $7, %di
+# CHECK-NEXT: 2 6 0.67 * * xorw $7, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock xorw $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 xorw %si, %di
+# CHECK-NEXT: 2 6 0.67 * * xorw %si, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock xorw %si, (%rax)
+# CHECK-NEXT: 1 5 0.50 * xorw (%rax), %di
+# CHECK-NEXT: 1 1 0.17 xorl $665536, %eax
+# CHECK-NEXT: 1 1 0.17 xorl $665536, %edi
+# CHECK-NEXT: 2 6 0.67 * * xorl $665536, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock xorl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.17 xorl $7, %edi
+# CHECK-NEXT: 2 6 0.67 * * xorl $7, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock xorl $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 xorl %esi, %edi
+# CHECK-NEXT: 2 6 0.67 * * xorl %esi, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock xorl %esi, (%rax)
+# CHECK-NEXT: 1 5 0.50 * xorl (%rax), %edi
+# CHECK-NEXT: 1 1 0.17 xorq $665536, %rax
+# CHECK-NEXT: 1 1 0.17 xorq $665536, %rdi
+# CHECK-NEXT: 2 6 0.67 * * xorq $665536, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock xorq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.17 xorq $7, %rdi
+# CHECK-NEXT: 2 6 0.67 * * xorq $7, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock xorq $7, (%rax)
+# CHECK-NEXT: 1 1 0.17 xorq %rsi, %rdi
+# CHECK-NEXT: 2 6 0.67 * * xorq %rsi, (%rax)
+# CHECK-NEXT: 2 6 0.67 * * lock xorq %rsi, (%rax)
+# CHECK-NEXT: 1 5 0.50 * xorq (%rax), %rdi
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: 262.33 262.33 262.33 350.33 269.17 555.17 350.33 - - - - 261.67 261.67 261.67 223.50 223.50 112.67 112.67 112.67
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - adcb $0, %al
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - adcb $0, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 adcb $0, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock adcb $0, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - adcb $7, %al
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - adcb $7, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 adcb $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock adcb $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - adcb %sil, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 adcb %sil, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock adcb %sil, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - adcb (%rax), %dil
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - adcw $0, %ax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - adcw $0, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 adcw $0, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock adcw $0, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - adcw $511, %ax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - adcw $511, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 adcw $511, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock adcw $511, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - adcw $7, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 adcw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock adcw $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - adcw %si, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 adcw %si, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock adcw %si, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - adcw (%rax), %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - adcl $0, %eax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - adcl $0, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 adcl $0, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock adcl $0, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - adcl $665536, %eax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - adcl $665536, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 adcl $665536, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock adcl $665536, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - adcl $7, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 adcl $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock adcl $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - adcl %esi, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 adcl %esi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock adcl %esi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - adcl (%rax), %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - adcq $0, %rax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - adcq $0, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 adcq $0, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock adcq $0, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - adcq $665536, %rax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - adcq $665536, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 adcq $665536, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock adcq $665536, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - adcq $7, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 adcq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock adcq $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - adcq %rsi, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 adcq %rsi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock adcq %rsi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - adcq (%rax), %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - addb $7, %al
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - addb $7, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 addb $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock addb $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - addb %sil, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 addb %sil, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock addb %sil, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - addb (%rax), %dil
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - addw $511, %ax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - addw $511, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 addw $511, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock addw $511, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - addw $7, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 addw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock addw $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - addw %si, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 addw %si, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock addw %si, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - addw (%rax), %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - addl $665536, %eax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - addl $665536, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 addl $665536, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock addl $665536, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - addl $7, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 addl $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock addl $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - addl %esi, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 addl %esi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock addl %esi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - addl (%rax), %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - addq $665536, %rax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - addq $665536, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 addq $665536, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock addq $665536, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - addq $7, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 addq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock addq $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - addq %rsi, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 addq %rsi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock addq %rsi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - addq (%rax), %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - andb $7, %al
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - andb $7, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 andb $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock andb $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - andb %sil, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 andb %sil, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock andb %sil, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - andb (%rax), %dil
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - andw $511, %ax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - andw $511, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 andw $511, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock andw $511, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - andw $7, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 andw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock andw $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - andw %si, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 andw %si, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock andw %si, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - andw (%rax), %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - andl $665536, %eax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - andl $665536, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 andl $665536, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock andl $665536, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - andl $7, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 andl $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock andl $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - andl %esi, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 andl %esi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock andl %esi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - andl (%rax), %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - andq $665536, %rax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - andq $665536, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 andq $665536, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock andq $665536, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - andq $7, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 andq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock andq $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - andq %rsi, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 andq %rsi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock andq %rsi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - andq (%rax), %rdi
+# CHECK-NEXT: - - - 4.00 2.00 2.00 4.00 - - - - - - - - - - - - bsfw %si, %di
+# CHECK-NEXT: - - - 5.33 2.67 2.67 5.33 - - - - - - - - - - - - bsrw %si, %di
+# CHECK-NEXT: 0.33 0.33 0.33 4.00 2.00 2.00 4.00 - - - - 0.67 0.67 0.67 1.00 1.00 - - - bsfw (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 5.33 2.67 2.67 5.33 - - - - 0.67 0.67 0.67 1.00 1.00 - - - bsrw (%rax), %di
+# CHECK-NEXT: - - - 4.00 2.00 2.00 4.00 - - - - - - - - - - - - bsfl %esi, %edi
+# CHECK-NEXT: - - - 5.33 2.67 2.67 5.33 - - - - - - - - - - - - bsrl %esi, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 4.00 2.00 2.00 4.00 - - - - 0.67 0.67 0.67 1.00 1.00 - - - bsfl (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 5.33 2.67 2.67 5.33 - - - - 0.67 0.67 0.67 1.00 1.00 - - - bsrl (%rax), %edi
+# CHECK-NEXT: - - - 4.00 2.00 2.00 4.00 - - - - - - - - - - - - bsfq %rsi, %rdi
+# CHECK-NEXT: - - - 5.33 2.67 2.67 5.33 - - - - - - - - - - - - bsrq %rsi, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 4.00 2.00 2.00 4.00 - - - - 0.67 0.67 0.67 1.00 1.00 - - - bsfq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 5.33 2.67 2.67 5.33 - - - - 0.67 0.67 0.67 1.00 1.00 - - - bsrq (%rax), %rdi
+# CHECK-NEXT: - - - 1.33 0.67 0.67 1.33 - - - - - - - - - - - - bswapl %eax
+# CHECK-NEXT: - - - 1.33 0.67 0.67 1.33 - - - - - - - - - - - - bswapq %rax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - btw %si, %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - btcw %si, %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - btrw %si, %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - btsw %si, %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - btw %si, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 btcw %si, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 btrw %si, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 btsw %si, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock btcw %si, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock btrw %si, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock btsw %si, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - btw $7, %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - btcw $7, %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - btrw $7, %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - btsw $7, %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - btw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 btcw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 btrw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 btsw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock btcw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock btrw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock btsw $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - btl %esi, %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - btcl %esi, %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - btrl %esi, %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - btsl %esi, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - btl %esi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 btcl %esi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 btrl %esi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 btsl %esi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock btcl %esi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock btrl %esi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock btsl %esi, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - btl $7, %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - btcl $7, %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - btrl $7, %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - btsl $7, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - btl $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 btcl $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 btrl $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 btsl $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock btcl $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock btrl $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock btsl $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - btq %rsi, %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - btcq %rsi, %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - btrq %rsi, %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - btsq %rsi, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - btq %rsi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 btcq %rsi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 btrq %rsi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 btsq %rsi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock btcq %rsi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock btrq %rsi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock btsq %rsi, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - btq $7, %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - btcq $7, %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - btrq $7, %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - btsq $7, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - btq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 btcq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 btrq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 btsq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock btcq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock btrq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock btsq $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cbtw
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cwtl
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cltq
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cwtd
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cltd
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cqto
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - clc
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cld
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmc
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmpb $7, %al
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmpb $7, %dil
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmpb $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmpb %sil, %dil
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmpb %sil, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmpb (%rax), %dil
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmpw $511, %ax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmpw $511, %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmpw $511, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmpw $7, %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmpw $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmpw %si, %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmpw %si, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmpw (%rax), %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmpl $665536, %eax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmpl $665536, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmpl $665536, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmpl $7, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmpl $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmpl %esi, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmpl %esi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmpl (%rax), %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmpq $665536, %rax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmpq $665536, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmpq $665536, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmpq $7, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmpq $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmpq %rsi, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmpq %rsi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - cmpq (%rax), %rdi
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - cmpsb %es:(%rdi), (%rsi)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - cmpsw %es:(%rdi), (%rsi)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - cmpsl %es:(%rdi), (%rsi)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - cmpsq %es:(%rdi), (%rsi)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmpxchgb %cl, %bl
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmpxchgb %cl, (%rbx)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - - - - - - - - - lock cmpxchgb %cl, (%rbx)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmpxchgw %cx, %bx
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmpxchgw %cx, (%rbx)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - - - - - - - - - lock cmpxchgw %cx, (%rbx)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmpxchgl %ecx, %ebx
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmpxchgl %ecx, (%rbx)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - - - - - - - - - lock cmpxchgl %ecx, (%rbx)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmpxchgq %rcx, %rbx
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - - - - - - - - - cmpxchgq %rcx, (%rbx)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - - - - - - - - - lock cmpxchgq %rcx, (%rbx)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - cpuid
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - decb %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 decb (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock decb (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - decw %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 decw (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock decw (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - decl %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 decl (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock decl (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - decq %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 decq (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock decq (%rax)
+# CHECK-NEXT: - - - - - 12.00 - - - - - - - - - - - - - divb %dil
+# CHECK-NEXT: 0.33 0.33 0.33 - - 12.00 - - - - - 0.33 0.33 0.33 0.50 0.50 - - - divb (%rax)
+# CHECK-NEXT: - - - - - 17.00 - - - - - - - - - - - - - divw %si
+# CHECK-NEXT: 0.33 0.33 0.33 - - 17.00 - - - - - 0.33 0.33 0.33 0.50 0.50 - - - divw (%rax)
+# CHECK-NEXT: - - - - - 25.00 - - - - - - - - - - - - - divl %edx
+# CHECK-NEXT: 0.33 0.33 0.33 - - 25.00 - - - - - 0.33 0.33 0.33 0.50 0.50 - - - divl (%rax)
+# CHECK-NEXT: - - - - - 41.00 - - - - - - - - - - - - - divq %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - 41.00 - - - - - 0.33 0.33 0.33 0.50 0.50 - - - divq (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - enter $7, $4095
+# CHECK-NEXT: - - - - - 12.00 - - - - - - - - - - - - - idivb %dil
+# CHECK-NEXT: 0.33 0.33 0.33 - - 12.00 - - - - - 0.33 0.33 0.33 0.50 0.50 - - - idivb (%rax)
+# CHECK-NEXT: - - - - - 17.00 - - - - - - - - - - - - - idivw %si
+# CHECK-NEXT: 0.33 0.33 0.33 - - 17.00 - - - - - 0.33 0.33 0.33 0.50 0.50 - - - idivw (%rax)
+# CHECK-NEXT: - - - - - 25.00 - - - - - - - - - - - - - idivl %edx
+# CHECK-NEXT: 0.33 0.33 0.33 - - 25.00 - - - - - 0.33 0.33 0.33 0.50 0.50 - - - idivl (%rax)
+# CHECK-NEXT: - - - - - 41.00 - - - - - - - - - - - - - idivq %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - 41.00 - - - - - 0.33 0.33 0.33 0.50 0.50 - - - idivq (%rax)
+# CHECK-NEXT: - - - - 3.00 - - - - - - - - - - - - - - imulb %dil
+# CHECK-NEXT: 0.33 0.33 0.33 - 3.00 - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - imulb (%rax)
+# CHECK-NEXT: - - - - 3.00 - - - - - - - - - - - - - - imulw %di
+# CHECK-NEXT: 0.33 0.33 0.33 - 3.00 - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - imulw (%rax)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - imulw %si, %di
+# CHECK-NEXT: 0.33 0.33 0.33 - 1.00 - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - imulw (%rax), %di
+# CHECK-NEXT: - - - - 4.00 - - - - - - - - - - - - - - imulw $511, %si, %di
+# CHECK-NEXT: 0.33 0.33 0.33 - 4.00 - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - imulw $511, (%rax), %di
+# CHECK-NEXT: - - - - 4.00 - - - - - - - - - - - - - - imulw $7, %si, %di
+# CHECK-NEXT: 0.33 0.33 0.33 - 4.00 - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - imulw $7, (%rax), %di
+# CHECK-NEXT: - - - - 3.00 - - - - - - - - - - - - - - imull %edi
+# CHECK-NEXT: 0.33 0.33 0.33 - 3.00 - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - imull (%rax)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - imull %esi, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 - 1.00 - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - imull (%rax), %edi
+# CHECK-NEXT: - - - - 3.00 - - - - - - - - - - - - - - imull $665536, %esi, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 - 3.00 - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - imull $665536, (%rax), %edi
+# CHECK-NEXT: - - - - 3.00 - - - - - - - - - - - - - - imull $7, %esi, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 - 3.00 - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - imull $7, (%rax), %edi
+# CHECK-NEXT: - - - - 3.00 - - - - - - - - - - - - - - imulq %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 - 3.00 - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - imulq (%rax)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - imulq %rsi, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 - 1.00 - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - imulq (%rax), %rdi
+# CHECK-NEXT: - - - - 3.00 - - - - - - - - - - - - - - imulq $665536, %rsi, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 - 3.00 - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - imulq $665536, (%rax), %rdi
+# CHECK-NEXT: - - - - 3.00 - - - - - - - - - - - - - - imulq $7, %rsi, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 - 3.00 - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - imulq $7, (%rax), %rdi
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - inb $7, %al
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - inb %dx, %al
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - inw $7, %ax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - inw %dx, %ax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - inl $7, %eax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - inl %dx, %eax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - incb %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 incb (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock incb (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - incw %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 incw (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock incw (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - incl %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 incl (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock incl (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - incq %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 incq (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock incq (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - insb %dx, %es:(%rdi)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - insw %dx, %es:(%rdi)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - insl %dx, %es:(%rdi)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - int $7
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - invlpg (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - invlpga
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - lahf
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - leave
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - lodsb (%rsi), %al
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - lodsw (%rsi), %ax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - lodsl (%rsi), %eax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - lodsq (%rsi), %rax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - loop 0
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - loope 0
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - loopne 0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - movsb (%rsi), %es:(%rdi)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - movsw (%rsi), %es:(%rdi)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - movsl (%rsi), %es:(%rdi)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - movsq (%rsi), %es:(%rdi)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - movsbw %al, %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - movzbw %al, %di
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - movsbw (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - movzbw (%rax), %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - movsbl %al, %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - movzbl %al, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - movsbl (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - movzbl (%rax), %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - movsbq %al, %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - movzbq %al, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - movsbq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - movzbq (%rax), %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - movswl %ax, %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - movzwl %ax, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - movswl (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - movzwl (%rax), %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - movswq %ax, %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - movzwq %ax, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - movswq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - movzwq (%rax), %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - movslq %eax, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - movslq (%rax), %rdi
+# CHECK-NEXT: - - - - 3.00 - - - - - - - - - - - - - - mulb %dil
+# CHECK-NEXT: 0.33 0.33 0.33 - 3.00 - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - mulb (%rax)
+# CHECK-NEXT: - - - - 3.00 - - - - - - - - - - - - - - mulw %si
+# CHECK-NEXT: 0.33 0.33 0.33 - 3.00 - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - mulw (%rax)
+# CHECK-NEXT: - - - - 3.00 - - - - - - - - - - - - - - mull %edx
+# CHECK-NEXT: 0.33 0.33 0.33 - 3.00 - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - mull (%rax)
+# CHECK-NEXT: - - - - 3.00 - - - - - - - - - - - - - - mulq %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - 3.00 - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - mulq (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - negb %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 negb (%r8)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock negb (%r8)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - negw %si
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 negw (%r9)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock negw (%r9)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - negl %edx
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 negl (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock negl (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - negq %rcx
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 negq (%r10)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock negq (%r10)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - nop
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - nopw %di
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - nopw (%rcx)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - nopl %esi
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - nopl (%r8)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - nopq %rdx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - nopq (%r9)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - notb %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 notb (%r8)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock notb (%r8)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - notw %si
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 notw (%r9)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock notw (%r9)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - notl %edx
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 notl (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock notl (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - notq %rcx
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 notq (%r10)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock notq (%r10)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - orb $7, %al
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - orb $7, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 orb $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock orb $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - orb %sil, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 orb %sil, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock orb %sil, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - orb (%rax), %dil
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - orw $511, %ax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - orw $511, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 orw $511, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock orw $511, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - orw $7, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 orw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock orw $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - orw %si, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 orw %si, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock orw %si, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - orw (%rax), %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - orl $665536, %eax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - orl $665536, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 orl $665536, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock orl $665536, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - orl $7, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 orl $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock orl $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - orl %esi, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 orl %esi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock orl %esi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - orl (%rax), %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - orq $665536, %rax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - orq $665536, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 orq $665536, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock orq $665536, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - orq $7, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 orq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock orq $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - orq %rsi, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 orq %rsi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock orq %rsi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - orq (%rax), %rdi
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - outb %al, $7
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - outb %al, %dx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - outw %ax, $7
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - outw %ax, %dx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - outl %eax, $7
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - outl %eax, %dx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - outsb (%rsi), %dx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - outsw (%rsi), %dx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - outsl (%rsi), %dx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - pause
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rclb %dil
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rcrb %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rclb (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rcrb (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rclb $7, %dil
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rcrb $7, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rclb $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rcrb $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rclb %cl, %dil
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rcrb %cl, %dil
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - rclb %cl, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - rcrb %cl, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rclw %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rcrw %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rclw (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rcrw (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rclw $7, %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rcrw $7, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rclw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rcrw $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rclw %cl, %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rcrw %cl, %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - rclw %cl, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - rcrw %cl, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rcll %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rcrl %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rcll (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rcrl (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rcll $7, %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rcrl $7, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rcll $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rcrl $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rcll %cl, %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rcrl %cl, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - rcll %cl, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - rcrl %cl, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rclq %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rcrq %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rclq (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rcrq (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rclq $7, %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rcrq $7, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rclq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rcrq $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rclq %cl, %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rcrq %cl, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - rclq %cl, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - rcrq %cl, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - rdmsr
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - rdpmc
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - rdtsc
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - rdtscp
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rolb %dil
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rorb %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rolb (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rorb (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rolb $7, %dil
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rorb $7, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rolb $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rorb $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rolb %cl, %dil
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rorb %cl, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rolb %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rorb %cl, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rolw %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rorw %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rolw (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rorw (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rolw $7, %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rorw $7, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rolw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rorw $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rolw %cl, %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rorw %cl, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rolw %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rorw %cl, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - roll %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rorl %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 roll (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rorl (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - roll $7, %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rorl $7, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 roll $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rorl $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - roll %cl, %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rorl %cl, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 roll %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rorl %cl, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rolq %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rorq %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rolq (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rorq (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rolq $7, %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rorq $7, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rolq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rorq $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rolq %cl, %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - rorq %cl, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rolq %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 rorq %cl, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sahf
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sarb %dil
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - shlb %dil
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - shrb %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 sarb (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 shlb (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 shrb (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sarb $7, %dil
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - shlb $7, %dil
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - shrb $7, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 sarb $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 shlb $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 shrb $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sarb %cl, %dil
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - shlb %cl, %dil
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - shrb %cl, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 sarb %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 shlb %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 shrb %cl, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sarw %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - shlw %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - shrw %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 sarw (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 shlw (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 shrw (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sarw $7, %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - shlw $7, %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - shrw $7, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 sarw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 shlw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 shrw $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sarw %cl, %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - shlw %cl, %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - shrw %cl, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 sarw %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 shlw %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 shrw %cl, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sarl %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - shll %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - shrl %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 sarl (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 shll (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 shrl (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sarl $7, %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - shll $7, %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - shrl $7, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 sarl $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 shll $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 shrl $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sarl %cl, %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - shll %cl, %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - shrl %cl, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 sarl %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 shll %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 shrl %cl, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sarq %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - shlq %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - shrq %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 sarq (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 shlq (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 shrq (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sarq $7, %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - shlq $7, %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - shrq $7, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 sarq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 shlq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 shrq $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sarq %cl, %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - shlq %cl, %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - shrq %cl, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 sarq %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 shlq %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 shrq %cl, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sbbb $0, %al
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sbbb $0, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 sbbb $0, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock sbbb $0, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sbbb $7, %al
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sbbb $7, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 sbbb $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock sbbb $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sbbb %sil, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 sbbb %sil, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock sbbb %sil, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - sbbb (%rax), %dil
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sbbw $0, %ax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sbbw $0, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 sbbw $0, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock sbbw $0, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sbbw $511, %ax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sbbw $511, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 sbbw $511, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock sbbw $511, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sbbw $7, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 sbbw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock sbbw $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sbbw %si, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 sbbw %si, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock sbbw %si, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - sbbw (%rax), %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sbbl $0, %eax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sbbl $0, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 sbbl $0, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock sbbl $0, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sbbl $665536, %eax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sbbl $665536, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 sbbl $665536, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock sbbl $665536, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sbbl $7, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 sbbl $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock sbbl $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sbbl %esi, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 sbbl %esi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock sbbl %esi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - sbbl (%rax), %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sbbq $0, %rax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sbbq $0, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 sbbq $0, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock sbbq $0, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sbbq $665536, %rax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sbbq $665536, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 sbbq $665536, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock sbbq $665536, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sbbq $7, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 sbbq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock sbbq $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sbbq %rsi, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 sbbq %rsi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock sbbq %rsi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - sbbq (%rax), %rdi
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - scasb %es:(%rdi), %al
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - scasw %es:(%rdi), %ax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - scasl %es:(%rdi), %eax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - scasq %es:(%rdi), %rax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - seto %al
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 seto (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - setno %al
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 setno (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - setb %al
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 setb (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - setae %al
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 setae (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sete %al
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 sete (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - setne %al
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 setne (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - seta %al
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 seta (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - setbe %al
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 setbe (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - sets %al
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 sets (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - setns %al
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 setns (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - setp %al
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 setp (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - setnp %al
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 setnp (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - setl %al
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 setl (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - setge %al
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 setge (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - setg %al
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 setg (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - setle %al
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 setle (%rax)
+# CHECK-NEXT: - - - 1.67 0.83 0.83 1.67 - - - - - - - - - - - - shldw %cl, %si, %di
+# CHECK-NEXT: - - - 1.67 0.83 0.83 1.67 - - - - - - - - - - - - shrdw %cl, %si, %di
+# CHECK-NEXT: - - - 1.67 0.83 0.83 1.67 - - - - - - - - - - - - shldw %cl, %si, (%rax)
+# CHECK-NEXT: - - - 1.67 0.83 0.83 1.67 - - - - - - - - - - - - shrdw %cl, %si, (%rax)
+# CHECK-NEXT: - - - 1.00 0.50 0.50 1.00 - - - - - - - - - - - - shldw $7, %si, %di
+# CHECK-NEXT: - - - 1.00 0.50 0.50 1.00 - - - - - - - - - - - - shrdw $7, %si, %di
+# CHECK-NEXT: - - - 1.67 0.83 0.83 1.67 - - - - - - - - - - - - shldw $7, %si, (%rax)
+# CHECK-NEXT: - - - 1.67 0.83 0.83 1.67 - - - - - - - - - - - - shrdw $7, %si, (%rax)
+# CHECK-NEXT: - - - 1.67 0.83 0.83 1.67 - - - - - - - - - - - - shldl %cl, %esi, %edi
+# CHECK-NEXT: - - - 1.67 0.83 0.83 1.67 - - - - - - - - - - - - shrdl %cl, %esi, %edi
+# CHECK-NEXT: - - - 1.67 0.83 0.83 1.67 - - - - - - - - - - - - shldl %cl, %esi, (%rax)
+# CHECK-NEXT: - - - 1.67 0.83 0.83 1.67 - - - - - - - - - - - - shrdl %cl, %esi, (%rax)
+# CHECK-NEXT: - - - 1.00 0.50 0.50 1.00 - - - - - - - - - - - - shldl $7, %esi, %edi
+# CHECK-NEXT: - - - 1.00 0.50 0.50 1.00 - - - - - - - - - - - - shrdl $7, %esi, %edi
+# CHECK-NEXT: - - - 1.67 0.83 0.83 1.67 - - - - - - - - - - - - shldl $7, %esi, (%rax)
+# CHECK-NEXT: - - - 1.67 0.83 0.83 1.67 - - - - - - - - - - - - shrdl $7, %esi, (%rax)
+# CHECK-NEXT: - - - 1.67 0.83 0.83 1.67 - - - - - - - - - - - - shldq %cl, %rsi, %rdi
+# CHECK-NEXT: - - - 1.67 0.83 0.83 1.67 - - - - - - - - - - - - shrdq %cl, %rsi, %rdi
+# CHECK-NEXT: - - - 1.67 0.83 0.83 1.67 - - - - - - - - - - - - shldq %cl, %rsi, (%rax)
+# CHECK-NEXT: - - - 1.67 0.83 0.83 1.67 - - - - - - - - - - - - shrdq %cl, %rsi, (%rax)
+# CHECK-NEXT: - - - 1.00 0.50 0.50 1.00 - - - - - - - - - - - - shldq $7, %rsi, %rdi
+# CHECK-NEXT: - - - 1.00 0.50 0.50 1.00 - - - - - - - - - - - - shrdq $7, %rsi, %rdi
+# CHECK-NEXT: - - - 1.67 0.83 0.83 1.67 - - - - - - - - - - - - shldq $7, %rsi, (%rax)
+# CHECK-NEXT: - - - 1.67 0.83 0.83 1.67 - - - - - - - - - - - - shrdq $7, %rsi, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - stc
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - std
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - stosb %al, %es:(%rdi)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - stosw %ax, %es:(%rdi)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - stosl %eax, %es:(%rdi)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - stosq %rax, %es:(%rdi)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - subb $7, %al
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - subb $7, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 subb $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock subb $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - subb %sil, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 subb %sil, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock subb %sil, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - subb (%rax), %dil
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - subw $511, %ax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - subw $511, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 subw $511, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock subw $511, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - subw $7, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 subw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock subw $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - subw %si, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 subw %si, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock subw %si, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - subw (%rax), %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - subl $665536, %eax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - subl $665536, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 subl $665536, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock subl $665536, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - subl $7, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 subl $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock subl $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - subl %esi, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 subl %esi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock subl %esi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - subl (%rax), %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - subq $665536, %rax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - subq $665536, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 subq $665536, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock subq $665536, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - subq $7, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 subq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock subq $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - subq %rsi, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 subq %rsi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock subq %rsi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - subq (%rax), %rdi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - testb $7, %al
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - testb $7, %dil
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - testb $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - testb %sil, %dil
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - testb %sil, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - testw $511, %ax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - testw $511, %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - testw $511, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - testw $7, %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - testw $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - testw %si, %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - testw %si, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - testl $665536, %eax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - testl $665536, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - testl $665536, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - testl $7, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - testl $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - testl %esi, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - testl %esi, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - testq $665536, %rax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - testq $665536, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - testq $665536, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - testq $7, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - testq $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - testq %rsi, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - testq %rsi, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - ud2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - wrmsr
+# CHECK-NEXT: - - - 0.67 0.33 0.33 0.67 - - - - - - - - - - - - xaddb %bl, %cl
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 xaddb %bl, (%rcx)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock xaddb %bl, (%rcx)
+# CHECK-NEXT: - - - 0.67 0.33 0.33 0.67 - - - - - - - - - - - - xaddw %bx, %cx
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 xaddw %ax, (%rbx)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock xaddw %ax, (%rbx)
+# CHECK-NEXT: - - - 0.67 0.33 0.33 0.67 - - - - - - - - - - - - xaddl %ebx, %ecx
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 xaddl %eax, (%rbx)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock xaddl %eax, (%rbx)
+# CHECK-NEXT: - - - 0.67 0.33 0.33 0.67 - - - - - - - - - - - - xaddq %rbx, %rcx
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 xaddq %rax, (%rbx)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock xaddq %rax, (%rbx)
+# CHECK-NEXT: - - - 0.67 0.33 0.33 0.67 - - - - - - - - - - - - xchgb %bl, %cl
+# CHECK-NEXT: 0.33 0.33 0.33 0.67 0.33 0.33 0.67 - - - - 0.33 0.33 0.33 0.50 0.50 - - - xchgb %bl, (%rbx)
+# CHECK-NEXT: 0.33 0.33 0.33 0.67 0.33 0.33 0.67 - - - - 0.33 0.33 0.33 0.50 0.50 - - - lock xchgb %bl, (%rbx)
+# CHECK-NEXT: - - - 0.67 0.33 0.33 0.67 - - - - - - - - - - - - xchgw %bx, %ax
+# CHECK-NEXT: - - - 0.67 0.33 0.33 0.67 - - - - - - - - - - - - xchgw %bx, %cx
+# CHECK-NEXT: 0.33 0.33 0.33 0.67 0.33 0.33 0.67 - - - - 0.33 0.33 0.33 0.50 0.50 - - - xchgw %ax, (%rbx)
+# CHECK-NEXT: 0.33 0.33 0.33 0.67 0.33 0.33 0.67 - - - - 0.33 0.33 0.33 0.50 0.50 - - - lock xchgw %ax, (%rbx)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - xchgl %ebx, %eax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - xchgl %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.67 0.33 0.33 0.67 - - - - 0.33 0.33 0.33 0.50 0.50 - - - xchgl %eax, (%rbx)
+# CHECK-NEXT: 0.33 0.33 0.33 0.67 0.33 0.33 0.67 - - - - 0.33 0.33 0.33 0.50 0.50 - - - lock xchgl %eax, (%rbx)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - xchgq %rbx, %rax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - xchgq %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.67 0.33 0.33 0.67 - - - - 0.33 0.33 0.33 0.50 0.50 - - - xchgq %rax, (%rbx)
+# CHECK-NEXT: 0.33 0.33 0.33 0.67 0.33 0.33 0.67 - - - - 0.33 0.33 0.33 0.50 0.50 - - - lock xchgq %rax, (%rbx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - xlatb
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - xorb $7, %al
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - xorb $7, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 xorb $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock xorb $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - xorb %sil, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 xorb %sil, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock xorb %sil, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - xorb (%rax), %dil
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - xorw $511, %ax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - xorw $511, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 xorw $511, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock xorw $511, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - xorw $7, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 xorw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock xorw $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - xorw %si, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 xorw %si, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock xorw %si, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - xorw (%rax), %di
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - xorl $665536, %eax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - xorl $665536, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 xorl $665536, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock xorl $665536, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - xorl $7, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 xorl $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock xorl $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - xorl %esi, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 xorl %esi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock xorl %esi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - xorl (%rax), %edi
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - xorq $665536, %rax
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - xorq $665536, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 xorq $665536, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock xorq $665536, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - xorq $7, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 xorq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock xorq $7, (%rax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - xorq %rsi, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 xorq %rsi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.33 0.17 0.17 0.33 - - - - 0.67 0.67 0.67 0.50 0.50 0.33 0.33 0.33 lock xorq %rsi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.33 0.17 0.17 0.33 - - - - 0.33 0.33 0.33 0.50 0.50 - - - xorq (%rax), %rdi
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-x87.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-x87.s
new file mode 100644
index 0000000000000..137fe8dc521ec
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-x87.s
@@ -0,0 +1,532 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+f2xm1
+
+fabs
+
+fadd %st, %st(1)
+fadd %st(2)
+fadds (%ecx)
+faddl (%ecx)
+faddp %st(1)
+faddp %st(2)
+fiadds (%ecx)
+fiaddl (%ecx)
+
+fbld (%ecx)
+fbstp (%eax)
+
+fchs
+
+fnclex
+
+fcmovb %st(1), %st
+fcmovbe %st(1), %st
+fcmove %st(1), %st
+fcmovnb %st(1), %st
+fcmovnbe %st(1), %st
+fcmovne %st(1), %st
+fcmovnu %st(1), %st
+fcmovu %st(1), %st
+
+fcom %st(1)
+fcom %st(3)
+fcoms (%ecx)
+fcoml (%eax)
+fcomp %st(1)
+fcomp %st(3)
+fcomps (%ecx)
+fcompl (%eax)
+fcompp
+
+fcomi %st(3)
+fcompi %st(3)
+
+fcos
+
+fdecstp
+
+fdiv %st, %st(1)
+fdiv %st(2)
+fdivs (%ecx)
+fdivl (%eax)
+fdivp %st(1)
+fdivp %st(2)
+fidivs (%ecx)
+fidivl (%eax)
+
+fdivr %st, %st(1)
+fdivr %st(2)
+fdivrs (%ecx)
+fdivrl (%eax)
+fdivrp %st(1)
+fdivrp %st(2)
+fidivrs (%ecx)
+fidivrl (%eax)
+
+ffree %st(0)
+
+ficoms (%ecx)
+ficoml (%eax)
+ficomps (%ecx)
+ficompl (%eax)
+
+filds (%edx)
+fildl (%ecx)
+fildll (%eax)
+
+fincstp
+
+fninit
+
+fists (%edx)
+fistl (%ecx)
+fistps (%edx)
+fistpl (%ecx)
+fistpll (%eax)
+
+fisttps (%edx)
+fisttpl (%ecx)
+fisttpll (%eax)
+
+fld %st(0)
+flds (%edx)
+fldl (%ecx)
+fldt (%eax)
+
+fldcw (%eax)
+fldenv (%eax)
+
+fld1
+fldl2e
+fldl2t
+fldlg2
+fldln2
+fldpi
+fldz
+
+fmul %st, %st(1)
+fmul %st(2)
+fmuls (%ecx)
+fmull (%eax)
+fmulp %st(1)
+fmulp %st(2)
+fimuls (%ecx)
+fimull (%eax)
+
+fnop
+
+fpatan
+
+fprem
+fprem1
+
+fptan
+
+frndint
+
+frstor (%eax)
+
+fnsave (%eax)
+
+fscale
+
+fsin
+
+fsincos
+
+fsqrt
+
+fst %st(0)
+fsts (%edx)
+fstl (%ecx)
+fstp %st(0)
+fstpl (%edx)
+fstpl (%ecx)
+fstpt (%eax)
+
+fnstcw (%eax)
+fnstenv (%eax)
+fnstsw (%eax)
+
+frstor (%eax)
+fsave (%eax)
+
+fsub %st, %st(1)
+fsub %st(2)
+fsubs (%ecx)
+fsubl (%eax)
+fsubp %st(1)
+fsubp %st(2)
+fisubs (%ecx)
+fisubl (%eax)
+
+fsubr %st, %st(1)
+fsubr %st(2)
+fsubrs (%ecx)
+fsubrl (%eax)
+fsubrp %st(1)
+fsubrp %st(2)
+fisubrs (%ecx)
+fisubrl (%eax)
+
+ftst
+
+fucom %st(1)
+fucom %st(3)
+fucomp %st(1)
+fucomp %st(3)
+fucompp
+
+fucomi %st(3)
+fucompi %st(3)
+
+fwait
+
+fxam
+
+fxch %st(1)
+fxch %st(3)
+
+fxrstor (%eax)
+fxsave (%eax)
+
+fxtract
+
+fyl2x
+fyl2xp1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 100 0.25 U f2xm1
+# CHECK-NEXT: 1 1 0.50 U fabs
+# CHECK-NEXT: 1 3 0.50 U fadd %st, %st(1)
+# CHECK-NEXT: 1 3 0.50 U fadd %st(2), %st
+# CHECK-NEXT: 1 10 0.50 * U fadds (%ecx)
+# CHECK-NEXT: 1 10 0.50 * U faddl (%ecx)
+# CHECK-NEXT: 1 3 0.50 U faddp %st, %st(1)
+# CHECK-NEXT: 1 3 0.50 U faddp %st, %st(2)
+# CHECK-NEXT: 1 10 0.50 * U fiadds (%ecx)
+# CHECK-NEXT: 1 10 0.50 * U fiaddl (%ecx)
+# CHECK-NEXT: 1 100 0.25 * U fbld (%ecx)
+# CHECK-NEXT: 1 100 0.25 * U fbstp (%eax)
+# CHECK-NEXT: 1 1 0.50 U fchs
+# CHECK-NEXT: 1 100 0.25 U fnclex
+# CHECK-NEXT: 1 100 0.25 U fcmovb %st(1), %st
+# CHECK-NEXT: 1 100 0.25 U fcmovbe %st(1), %st
+# CHECK-NEXT: 1 100 0.25 U fcmove %st(1), %st
+# CHECK-NEXT: 1 100 0.25 U fcmovnb %st(1), %st
+# CHECK-NEXT: 1 100 0.25 U fcmovnbe %st(1), %st
+# CHECK-NEXT: 1 100 0.25 U fcmovne %st(1), %st
+# CHECK-NEXT: 1 100 0.25 U fcmovnu %st(1), %st
+# CHECK-NEXT: 1 100 0.25 U fcmovu %st(1), %st
+# CHECK-NEXT: 1 5 1.00 U fcom %st(1)
+# CHECK-NEXT: 1 5 1.00 U fcom %st(3)
+# CHECK-NEXT: 1 12 1.00 * U fcoms (%ecx)
+# CHECK-NEXT: 1 12 1.00 * U fcoml (%eax)
+# CHECK-NEXT: 1 5 1.00 U fcomp %st(1)
+# CHECK-NEXT: 1 5 1.00 U fcomp %st(3)
+# CHECK-NEXT: 1 12 1.00 * U fcomps (%ecx)
+# CHECK-NEXT: 1 12 1.00 * U fcompl (%eax)
+# CHECK-NEXT: 1 100 0.25 U fcompp
+# CHECK-NEXT: 1 5 1.00 U fcomi %st(3), %st
+# CHECK-NEXT: 1 5 1.00 U fcompi %st(3), %st
+# CHECK-NEXT: 1 100 0.25 U fcos
+# CHECK-NEXT: 1 100 0.25 U fdecstp
+# CHECK-NEXT: 1 10 5.00 U fdiv %st, %st(1)
+# CHECK-NEXT: 1 10 5.00 U fdiv %st(2), %st
+# CHECK-NEXT: 1 17 5.00 * U fdivs (%ecx)
+# CHECK-NEXT: 1 17 5.00 * U fdivl (%eax)
+# CHECK-NEXT: 1 10 5.00 U fdivp %st, %st(1)
+# CHECK-NEXT: 1 10 5.00 U fdivp %st, %st(2)
+# CHECK-NEXT: 1 17 5.00 * U fidivs (%ecx)
+# CHECK-NEXT: 1 17 5.00 * U fidivl (%eax)
+# CHECK-NEXT: 1 10 5.00 U fdivr %st, %st(1)
+# CHECK-NEXT: 1 10 5.00 U fdivr %st(2), %st
+# CHECK-NEXT: 1 17 5.00 * U fdivrs (%ecx)
+# CHECK-NEXT: 1 17 5.00 * U fdivrl (%eax)
+# CHECK-NEXT: 1 10 5.00 U fdivrp %st, %st(1)
+# CHECK-NEXT: 1 10 5.00 U fdivrp %st, %st(2)
+# CHECK-NEXT: 1 17 5.00 * U fidivrs (%ecx)
+# CHECK-NEXT: 1 17 5.00 * U fidivrl (%eax)
+# CHECK-NEXT: 1 100 0.25 U ffree %st(0)
+# CHECK-NEXT: 1 12 1.00 * U ficoms (%ecx)
+# CHECK-NEXT: 1 12 1.00 * U ficoml (%eax)
+# CHECK-NEXT: 1 12 1.00 * U ficomps (%ecx)
+# CHECK-NEXT: 1 12 1.00 * U ficompl (%eax)
+# CHECK-NEXT: 1 5 0.50 * U filds (%edx)
+# CHECK-NEXT: 1 5 0.50 * U fildl (%ecx)
+# CHECK-NEXT: 1 5 0.50 * U fildll (%eax)
+# CHECK-NEXT: 1 100 0.25 U fincstp
+# CHECK-NEXT: 1 100 0.25 U fninit
+# CHECK-NEXT: 1 1 0.33 * U fists (%edx)
+# CHECK-NEXT: 1 1 0.33 * U fistl (%ecx)
+# CHECK-NEXT: 1 1 0.33 * U fistps (%edx)
+# CHECK-NEXT: 1 1 0.33 * U fistpl (%ecx)
+# CHECK-NEXT: 1 1 0.33 * U fistpll (%eax)
+# CHECK-NEXT: 1 1 0.33 * U fisttps (%edx)
+# CHECK-NEXT: 1 1 0.33 * U fisttpl (%ecx)
+# CHECK-NEXT: 1 1 0.33 * U fisttpll (%eax)
+# CHECK-NEXT: 1 1 0.17 U fld %st(0)
+# CHECK-NEXT: 1 5 0.50 * U flds (%edx)
+# CHECK-NEXT: 1 5 0.50 * U fldl (%ecx)
+# CHECK-NEXT: 1 5 0.50 * U fldt (%eax)
+# CHECK-NEXT: 1 5 0.50 * U fldcw (%eax)
+# CHECK-NEXT: 1 100 0.25 * U fldenv (%eax)
+# CHECK-NEXT: 1 8 1.00 U fld1
+# CHECK-NEXT: 1 8 1.00 U fldl2e
+# CHECK-NEXT: 1 8 1.00 U fldl2t
+# CHECK-NEXT: 1 8 1.00 U fldlg2
+# CHECK-NEXT: 1 8 1.00 U fldln2
+# CHECK-NEXT: 1 8 1.00 U fldpi
+# CHECK-NEXT: 1 8 1.00 U fldz
+# CHECK-NEXT: 1 3 0.50 U fmul %st, %st(1)
+# CHECK-NEXT: 1 3 0.50 U fmul %st(2), %st
+# CHECK-NEXT: 1 10 0.50 * U fmuls (%ecx)
+# CHECK-NEXT: 1 10 0.50 * U fmull (%eax)
+# CHECK-NEXT: 1 3 0.50 U fmulp %st, %st(1)
+# CHECK-NEXT: 1 3 0.50 U fmulp %st, %st(2)
+# CHECK-NEXT: 1 10 0.50 * U fimuls (%ecx)
+# CHECK-NEXT: 1 10 0.50 * U fimull (%eax)
+# CHECK-NEXT: 1 1 0.25 U fnop
+# CHECK-NEXT: 1 100 0.25 U fpatan
+# CHECK-NEXT: 1 100 0.25 U fprem
+# CHECK-NEXT: 1 100 0.25 U fprem1
+# CHECK-NEXT: 1 100 0.25 U fptan
+# CHECK-NEXT: 1 100 0.25 U frndint
+# CHECK-NEXT: 1 100 0.25 * U frstor (%eax)
+# CHECK-NEXT: 1 100 0.25 * U fnsave (%eax)
+# CHECK-NEXT: 1 100 0.25 U fscale
+# CHECK-NEXT: 1 100 0.25 U fsin
+# CHECK-NEXT: 1 100 0.25 U fsincos
+# CHECK-NEXT: 1 22 22.00 U fsqrt
+# CHECK-NEXT: 1 1 0.17 U fst %st(0)
+# CHECK-NEXT: 1 1 0.33 * U fsts (%edx)
+# CHECK-NEXT: 1 1 0.33 * U fstl (%ecx)
+# CHECK-NEXT: 1 1 0.17 U fstp %st(0)
+# CHECK-NEXT: 1 1 0.33 * U fstpl (%edx)
+# CHECK-NEXT: 1 1 0.33 * U fstpl (%ecx)
+# CHECK-NEXT: 1 1 0.33 * U fstpt (%eax)
+# CHECK-NEXT: 1 1 0.17 * U fnstcw (%eax)
+# CHECK-NEXT: 1 100 0.25 * U fnstenv (%eax)
+# CHECK-NEXT: 1 100 0.25 * U fnstsw (%eax)
+# CHECK-NEXT: 1 100 0.25 * U frstor (%eax)
+# CHECK-NEXT: 1 100 0.25 U wait
+# CHECK-NEXT: 1 100 0.25 * U fnsave (%eax)
+# CHECK-NEXT: 1 3 0.50 U fsub %st, %st(1)
+# CHECK-NEXT: 1 3 0.50 U fsub %st(2), %st
+# CHECK-NEXT: 1 10 0.50 * U fsubs (%ecx)
+# CHECK-NEXT: 1 10 0.50 * U fsubl (%eax)
+# CHECK-NEXT: 1 3 0.50 U fsubp %st, %st(1)
+# CHECK-NEXT: 1 3 0.50 U fsubp %st, %st(2)
+# CHECK-NEXT: 1 10 0.50 * U fisubs (%ecx)
+# CHECK-NEXT: 1 10 0.50 * U fisubl (%eax)
+# CHECK-NEXT: 1 3 0.50 U fsubr %st, %st(1)
+# CHECK-NEXT: 1 3 0.50 U fsubr %st(2), %st
+# CHECK-NEXT: 1 10 0.50 * U fsubrs (%ecx)
+# CHECK-NEXT: 1 10 0.50 * U fsubrl (%eax)
+# CHECK-NEXT: 1 3 0.50 U fsubrp %st, %st(1)
+# CHECK-NEXT: 1 3 0.50 U fsubrp %st, %st(2)
+# CHECK-NEXT: 1 10 0.50 * U fisubrs (%ecx)
+# CHECK-NEXT: 1 10 0.50 * U fisubrl (%eax)
+# CHECK-NEXT: 1 5 1.00 U ftst
+# CHECK-NEXT: 1 5 1.00 U fucom %st(1)
+# CHECK-NEXT: 1 5 1.00 U fucom %st(3)
+# CHECK-NEXT: 1 5 1.00 U fucomp %st(1)
+# CHECK-NEXT: 1 5 1.00 U fucomp %st(3)
+# CHECK-NEXT: 1 5 1.00 U fucompp
+# CHECK-NEXT: 1 5 1.00 U fucomi %st(3), %st
+# CHECK-NEXT: 1 5 1.00 U fucompi %st(3), %st
+# CHECK-NEXT: 1 100 0.25 U wait
+# CHECK-NEXT: 1 4 2.00 U fxam
+# CHECK-NEXT: 1 1 0.17 U fxch %st(1)
+# CHECK-NEXT: 1 1 0.17 U fxch %st(3)
+# CHECK-NEXT: 1 100 0.25 * * U fxrstor (%eax)
+# CHECK-NEXT: 1 100 0.25 * * U fxsave (%eax)
+# CHECK-NEXT: 1 100 0.25 U fxtract
+# CHECK-NEXT: 1 100 0.25 U fyl2x
+# CHECK-NEXT: 1 100 0.25 U fyl2xp1
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: 22.00 22.00 22.00 2.00 1.00 1.00 2.00 15.50 146.50 15.00 13.00 17.33 17.33 17.33 19.50 19.50 4.33 4.33 4.33
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - f2xm1
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - fabs
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - fadd %st, %st(1)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - fadd %st(2), %st
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - fadds (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - faddl (%ecx)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - faddp %st, %st(1)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - faddp %st, %st(2)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - fiadds (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - fiaddl (%ecx)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fbld (%ecx)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fbstp (%eax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - fchs
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fnclex
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fcmovb %st(1), %st
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fcmovbe %st(1), %st
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fcmove %st(1), %st
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fcmovnb %st(1), %st
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fcmovnbe %st(1), %st
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fcmovne %st(1), %st
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fcmovnu %st(1), %st
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fcmovu %st(1), %st
+# CHECK-NEXT: - - - - - - - 0.50 1.00 0.50 - - - - - - - - - fcom %st(1)
+# CHECK-NEXT: - - - - - - - 0.50 1.00 0.50 - - - - - - - - - fcom %st(3)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 1.00 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - fcoms (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 1.00 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - fcoml (%eax)
+# CHECK-NEXT: - - - - - - - 0.50 1.00 0.50 - - - - - - - - - fcomp %st(1)
+# CHECK-NEXT: - - - - - - - 0.50 1.00 0.50 - - - - - - - - - fcomp %st(3)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 1.00 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - fcomps (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 1.00 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - fcompl (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fcompp
+# CHECK-NEXT: - - - - - - - 0.50 1.00 0.50 - - - - - - - - - fcomi %st(3), %st
+# CHECK-NEXT: - - - - - - - 0.50 1.00 0.50 - - - - - - - - - fcompi %st(3), %st
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fcos
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fdecstp
+# CHECK-NEXT: - - - - - - - - 5.00 - - - - - - - - - - fdiv %st, %st(1)
+# CHECK-NEXT: - - - - - - - - 5.00 - - - - - - - - - - fdiv %st(2), %st
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 5.00 - - 0.33 0.33 0.33 0.50 0.50 - - - fdivs (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 5.00 - - 0.33 0.33 0.33 0.50 0.50 - - - fdivl (%eax)
+# CHECK-NEXT: - - - - - - - - 5.00 - - - - - - - - - - fdivp %st, %st(1)
+# CHECK-NEXT: - - - - - - - - 5.00 - - - - - - - - - - fdivp %st, %st(2)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 5.00 - - 0.33 0.33 0.33 0.50 0.50 - - - fidivs (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 5.00 - - 0.33 0.33 0.33 0.50 0.50 - - - fidivl (%eax)
+# CHECK-NEXT: - - - - - - - - 5.00 - - - - - - - - - - fdivr %st, %st(1)
+# CHECK-NEXT: - - - - - - - - 5.00 - - - - - - - - - - fdivr %st(2), %st
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 5.00 - - 0.33 0.33 0.33 0.50 0.50 - - - fdivrs (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 5.00 - - 0.33 0.33 0.33 0.50 0.50 - - - fdivrl (%eax)
+# CHECK-NEXT: - - - - - - - - 5.00 - - - - - - - - - - fdivrp %st, %st(1)
+# CHECK-NEXT: - - - - - - - - 5.00 - - - - - - - - - - fdivrp %st, %st(2)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 5.00 - - 0.33 0.33 0.33 0.50 0.50 - - - fidivrs (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 5.00 - - 0.33 0.33 0.33 0.50 0.50 - - - fidivrl (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - ffree %st(0)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 1.00 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - ficoms (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 1.00 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - ficoml (%eax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 1.00 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - ficomps (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 1.00 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - ficompl (%eax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - filds (%edx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - fildl (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - fildll (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fincstp
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fninit
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 fists (%edx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 fistl (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 fistps (%edx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 fistpl (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 fistpll (%eax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 fisttps (%edx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 fisttpl (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 fisttpll (%eax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - fld %st(0)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - flds (%edx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - fldl (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - fldt (%eax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - - fldcw (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fldenv (%eax)
+# CHECK-NEXT: 0.67 0.67 0.67 - - - - - 1.00 - - - - - - - - - - fld1
+# CHECK-NEXT: 0.67 0.67 0.67 - - - - - 1.00 - - - - - - - - - - fldl2e
+# CHECK-NEXT: 0.67 0.67 0.67 - - - - - 1.00 - - - - - - - - - - fldl2t
+# CHECK-NEXT: 0.67 0.67 0.67 - - - - - 1.00 - - - - - - - - - - fldlg2
+# CHECK-NEXT: 0.67 0.67 0.67 - - - - - 1.00 - - - - - - - - - - fldln2
+# CHECK-NEXT: 0.67 0.67 0.67 - - - - - 1.00 - - - - - - - - - - fldpi
+# CHECK-NEXT: 0.67 0.67 0.67 - - - - - 1.00 - - - - - - - - - - fldz
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - fmul %st, %st(1)
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - fmul %st(2), %st
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - fmuls (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - fmull (%eax)
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - fmulp %st, %st(1)
+# CHECK-NEXT: - - - - - - - 0.50 - 0.50 - - - - - - - - - fmulp %st, %st(2)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - fimuls (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - 0.50 - 0.50 - 0.33 0.33 0.33 0.50 0.50 - - - fimull (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fnop
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fpatan
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fprem
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fprem1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fptan
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - frndint
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - frstor (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fnsave (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fscale
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fsin
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fsincos
+# CHECK-NEXT: - - - - - - - - 22.00 - - - - - - - - - - fsqrt
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - fst %st(0)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 fsts (%edx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 fstl (%ecx)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - fstp %st(0)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 fstpl (%edx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 fstpl (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - 0.33 0.33 0.33 - - 0.33 0.33 0.33 fstpt (%eax)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - fnstcw (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fnstenv (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fnstsw (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - frstor (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - wait
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fnsave (%eax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - fsub %st, %st(1)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - fsub %st(2), %st
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - fsubs (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - fsubl (%eax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - fsubp %st, %st(1)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - fsubp %st, %st(2)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - fisubs (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - fisubl (%eax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - fsubr %st, %st(1)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - fsubr %st(2), %st
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - fsubrs (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - fsubrl (%eax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - fsubrp %st, %st(1)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - fsubrp %st, %st(2)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - fisubrs (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 0.33 0.33 0.33 0.50 0.50 - - - fisubrl (%eax)
+# CHECK-NEXT: - - - - - - - 0.50 1.00 0.50 - - - - - - - - - ftst
+# CHECK-NEXT: - - - - - - - 0.50 1.00 0.50 - - - - - - - - - fucom %st(1)
+# CHECK-NEXT: - - - - - - - 0.50 1.00 0.50 - - - - - - - - - fucom %st(3)
+# CHECK-NEXT: - - - - - - - 0.50 1.00 0.50 - - - - - - - - - fucomp %st(1)
+# CHECK-NEXT: - - - - - - - 0.50 1.00 0.50 - - - - - - - - - fucomp %st(3)
+# CHECK-NEXT: - - - - - - - 0.50 1.00 0.50 - - - - - - - - - fucompp
+# CHECK-NEXT: - - - - - - - 0.50 1.00 0.50 - - - - - - - - - fucomi %st(3), %st
+# CHECK-NEXT: - - - - - - - 0.50 1.00 0.50 - - - - - - - - - fucompi %st(3), %st
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - wait
+# CHECK-NEXT: - - - - - - - 0.50 2.50 - - - - - - - - - - fxam
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - fxch %st(1)
+# CHECK-NEXT: - - - 0.33 0.17 0.17 0.33 - - - - - - - - - - - - fxch %st(3)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fxrstor (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fxsave (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fxtract
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fyl2x
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - fyl2xp1
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-xsave.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-xsave.s
new file mode 100644
index 0000000000000..dabd74a11c322
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-xsave.s
@@ -0,0 +1,60 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -instruction-tables < %s | FileCheck %s
+
+xgetbv
+
+xrstor (%rax)
+
+xrstors (%rax)
+
+xsave (%rax)
+
+xsetbv
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 100 0.25 U xgetbv
+# CHECK-NEXT: 1 100 0.25 * * U xrstor (%rax)
+# CHECK-NEXT: 1 100 0.25 * * U xrstors (%rax)
+# CHECK-NEXT: 1 100 0.25 * * U xsave (%rax)
+# CHECK-NEXT: 1 100 0.25 * * U xsetbv
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - xgetbv
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - xrstor (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - xrstors (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - xsave (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - xsetbv
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/zero-idioms.s b/llvm/test/tools/llvm-mca/X86/4GM4/zero-idioms.s
new file mode 100644
index 0000000000000..fa96aa36589b6
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/zero-idioms.s
@@ -0,0 +1,507 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m4 -timeline -register-file-stats -iterations=1 < %s | FileCheck %s
+
+subl %eax, %eax
+subq %rax, %rax
+xorl %eax, %eax
+xorq %rax, %rax
+
+pcmpgtb %mm2, %mm2
+pcmpgtd %mm2, %mm2
+# pcmpgtq %mm2, %mm2 # invalid operand for instruction
+pcmpgtw %mm2, %mm2
+
+pcmpgtb %xmm2, %xmm2
+pcmpgtd %xmm2, %xmm2
+pcmpgtq %xmm2, %xmm2
+pcmpgtw %xmm2, %xmm2
+
+vpcmpgtb %xmm3, %xmm3, %xmm3
+vpcmpgtd %xmm3, %xmm3, %xmm3
+vpcmpgtq %xmm3, %xmm3, %xmm3
+vpcmpgtw %xmm3, %xmm3, %xmm3
+
+vpcmpgtb %xmm3, %xmm3, %xmm5
+vpcmpgtd %xmm3, %xmm3, %xmm5
+vpcmpgtq %xmm3, %xmm3, %xmm5
+vpcmpgtw %xmm3, %xmm3, %xmm5
+
+vpcmpgtb %ymm3, %ymm3, %ymm3
+vpcmpgtd %ymm3, %ymm3, %ymm3
+vpcmpgtq %ymm3, %ymm3, %ymm3
+vpcmpgtw %ymm3, %ymm3, %ymm3
+
+vpcmpgtb %ymm3, %ymm3, %ymm5
+vpcmpgtd %ymm3, %ymm3, %ymm5
+vpcmpgtq %ymm3, %ymm3, %ymm5
+vpcmpgtw %ymm3, %ymm3, %ymm5
+
+psubb %mm2, %mm2
+psubd %mm2, %mm2
+psubq %mm2, %mm2
+psubw %mm2, %mm2
+psubb %xmm2, %xmm2
+psubd %xmm2, %xmm2
+psubq %xmm2, %xmm2
+psubw %xmm2, %xmm2
+vpsubb %xmm3, %xmm3, %xmm3
+vpsubd %xmm3, %xmm3, %xmm3
+vpsubq %xmm3, %xmm3, %xmm3
+vpsubw %xmm3, %xmm3, %xmm3
+vpsubb %ymm3, %ymm3, %ymm3
+vpsubd %ymm3, %ymm3, %ymm3
+vpsubq %ymm3, %ymm3, %ymm3
+vpsubw %ymm3, %ymm3, %ymm3
+
+vpsubb %xmm3, %xmm3, %xmm5
+vpsubd %xmm3, %xmm3, %xmm5
+vpsubq %xmm3, %xmm3, %xmm5
+vpsubw %xmm3, %xmm3, %xmm5
+vpsubb %ymm3, %ymm3, %ymm5
+vpsubd %ymm3, %ymm3, %ymm5
+vpsubq %ymm3, %ymm3, %ymm5
+vpsubw %ymm3, %ymm3, %ymm5
+
+andnps %xmm0, %xmm0
+andnpd %xmm1, %xmm1
+vandnps %xmm2, %xmm2, %xmm2
+vandnpd %xmm1, %xmm1, %xmm1
+vandnps %ymm2, %ymm2, %ymm2
+vandnpd %ymm1, %ymm1, %ymm1
+pandn %mm2, %mm2
+pandn %xmm2, %xmm2
+vpandn %xmm3, %xmm3, %xmm3
+vpandn %ymm3, %ymm3, %ymm3
+
+vandnps %xmm2, %xmm2, %xmm5
+vandnpd %xmm1, %xmm1, %xmm5
+vpandn %xmm3, %xmm3, %xmm5
+vandnps %ymm2, %ymm2, %ymm5
+vandnpd %ymm1, %ymm1, %ymm5
+vpandn %ymm3, %ymm3, %ymm5
+
+xorps %xmm0, %xmm0
+xorpd %xmm1, %xmm1
+vxorps %xmm2, %xmm2, %xmm2
+vxorpd %xmm1, %xmm1, %xmm1
+vxorps %ymm2, %ymm2, %ymm2
+vxorpd %ymm1, %ymm1, %ymm1
+pxor %mm2, %mm2
+pxor %xmm2, %xmm2
+vpxor %xmm3, %xmm3, %xmm3
+vpxor %ymm3, %ymm3, %ymm3
+
+vxorps %xmm4, %xmm4, %xmm5
+vxorpd %xmm1, %xmm1, %xmm3
+vxorps %ymm4, %ymm4, %ymm5
+vxorpd %ymm1, %ymm1, %ymm3
+vpxor %xmm3, %xmm3, %xmm5
+vpxor %ymm3, %ymm3, %ymm5
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 83
+# CHECK-NEXT: Total Cycles: 23
+# CHECK-NEXT: Total uOps: 83
+
+# CHECK: Dispatch Width: 4
+# CHECK-NEXT: uOps Per Cycle: 3.61
+# CHECK-NEXT: IPC: 3.61
+# CHECK-NEXT: Block RThroughput: 20.8
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 0 0.25 subl %eax, %eax
+# CHECK-NEXT: 1 0 0.25 subq %rax, %rax
+# CHECK-NEXT: 1 0 0.25 xorl %eax, %eax
+# CHECK-NEXT: 1 0 0.25 xorq %rax, %rax
+# CHECK-NEXT: 1 1 0.25 pcmpgtb %mm2, %mm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtd %mm2, %mm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtw %mm2, %mm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtb %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtd %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtq %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtw %xmm2, %xmm2
+# CHECK-NEXT: 1 0 0.25 vpcmpgtb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 0 0.25 vpcmpgtd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 0 0.25 vpcmpgtq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 0 0.25 vpcmpgtw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 0 0.25 vpcmpgtb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 0 0.25 vpcmpgtd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 0 0.25 vpcmpgtq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 0 0.25 vpcmpgtw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 0 0.25 vpcmpgtb %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 0 0.25 vpcmpgtd %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 0 0.25 vpcmpgtq %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 0 0.25 vpcmpgtw %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 0 0.25 vpcmpgtb %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 0 0.25 vpcmpgtd %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 0 0.25 vpcmpgtq %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 0 0.25 vpcmpgtw %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 1 0.25 psubb %mm2, %mm2
+# CHECK-NEXT: 1 1 0.25 psubd %mm2, %mm2
+# CHECK-NEXT: 1 1 0.25 psubq %mm2, %mm2
+# CHECK-NEXT: 1 1 0.25 psubw %mm2, %mm2
+# CHECK-NEXT: 1 1 0.25 psubb %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.25 psubd %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.25 psubq %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.25 psubw %xmm2, %xmm2
+# CHECK-NEXT: 1 0 0.25 vpsubb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 0 0.25 vpsubd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 0 0.25 vpsubq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 0 0.25 vpsubw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 0 0.25 vpsubb %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 0 0.25 vpsubd %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 0 0.25 vpsubq %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 0 0.25 vpsubw %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 0 0.25 vpsubb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 0 0.25 vpsubd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 0 0.25 vpsubq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 0 0.25 vpsubw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 0 0.25 vpsubb %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 0 0.25 vpsubd %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 0 0.25 vpsubq %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 0 0.25 vpsubw %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 1 0.25 andnps %xmm0, %xmm0
+# CHECK-NEXT: 1 1 0.25 andnpd %xmm1, %xmm1
+# CHECK-NEXT: 1 0 0.25 vandnps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: 1 0 0.25 vandnpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: 1 0 0.25 vandnps %ymm2, %ymm2, %ymm2
+# CHECK-NEXT: 1 0 0.25 vandnpd %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: 1 1 0.25 pandn %mm2, %mm2
+# CHECK-NEXT: 1 1 0.25 pandn %xmm2, %xmm2
+# CHECK-NEXT: 1 0 0.25 vpandn %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 0 0.25 vpandn %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 0 0.25 vandnps %xmm2, %xmm2, %xmm5
+# CHECK-NEXT: 1 0 0.25 vandnpd %xmm1, %xmm1, %xmm5
+# CHECK-NEXT: 1 0 0.25 vpandn %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 0 0.25 vandnps %ymm2, %ymm2, %ymm5
+# CHECK-NEXT: 1 0 0.25 vandnpd %ymm1, %ymm1, %ymm5
+# CHECK-NEXT: 1 0 0.25 vpandn %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 1 0.25 xorps %xmm0, %xmm0
+# CHECK-NEXT: 1 1 0.25 xorpd %xmm1, %xmm1
+# CHECK-NEXT: 1 0 0.25 vxorps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: 1 0 0.25 vxorpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: 1 0 0.25 vxorps %ymm2, %ymm2, %ymm2
+# CHECK-NEXT: 1 0 0.25 vxorpd %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: 1 1 0.25 pxor %mm2, %mm2
+# CHECK-NEXT: 1 1 0.25 pxor %xmm2, %xmm2
+# CHECK-NEXT: 1 0 0.25 vpxor %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 0 0.25 vpxor %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 0 0.25 vxorps %xmm4, %xmm4, %xmm5
+# CHECK-NEXT: 1 0 0.25 vxorpd %xmm1, %xmm1, %xmm3
+# CHECK-NEXT: 1 0 0.25 vxorps %ymm4, %ymm4, %ymm5
+# CHECK-NEXT: 1 0 0.25 vxorpd %ymm1, %ymm1, %ymm3
+# CHECK-NEXT: 1 0 0.25 vpxor %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 0 0.25 vpxor %ymm3, %ymm3, %ymm5
+
+# CHECK: Register File statistics:
+# CHECK-NEXT: Total number of mappings created: 9
+# CHECK-NEXT: Max number of mappings used: 4
+
+# CHECK: * Register File #1 -- 4GM4FpuPRF:
+# CHECK-NEXT: Number of physical registers: 176
+# CHECK-NEXT: Total number of mappings created: 9
+# CHECK-NEXT: Max number of mappings used: 4
+
+# CHECK: * Register File #2 -- 4GM4IntegerPRF:
+# CHECK-NEXT: Number of physical registers: 192
+# CHECK-NEXT: Total number of mappings created: 0
+# CHECK-NEXT: Max number of mappings used: 0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM4AGU0
+# CHECK-NEXT: [1] - 4GM4AGU1
+# CHECK-NEXT: [2] - 4GM4AGU2
+# CHECK-NEXT: [3] - 4GM4ALU0
+# CHECK-NEXT: [4] - 4GM4ALU1
+# CHECK-NEXT: [5] - 4GM4ALU2
+# CHECK-NEXT: [6] - 4GM4ALU3
+# CHECK-NEXT: [7] - 4GM4FPU0
+# CHECK-NEXT: [8] - 4GM4FPU1
+# CHECK-NEXT: [9] - 4GM4FPU2
+# CHECK-NEXT: [10] - 4GM4FPU3
+# CHECK-NEXT: [11.0] - 4GM4LSU
+# CHECK-NEXT: [11.1] - 4GM4LSU
+# CHECK-NEXT: [11.2] - 4GM4LSU
+# CHECK-NEXT: [12.0] - 4GM4Load
+# CHECK-NEXT: [12.1] - 4GM4Load
+# CHECK-NEXT: [13.0] - 4GM4Store
+# CHECK-NEXT: [13.1] - 4GM4Store
+# CHECK-NEXT: [13.2] - 4GM4Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
+# CHECK-NEXT: - - - - - - - 5.00 6.00 6.00 6.00 - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - subl %eax, %eax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - subq %rax, %rax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - xorl %eax, %eax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - xorq %rax, %rax
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - pcmpgtb %mm2, %mm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - pcmpgtd %mm2, %mm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - pcmpgtw %mm2, %mm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - pcmpgtb %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - pcmpgtd %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - pcmpgtq %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - pcmpgtw %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpcmpgtb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpcmpgtd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpcmpgtq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpcmpgtw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpcmpgtb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpcmpgtd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpcmpgtq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpcmpgtw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpcmpgtb %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpcmpgtd %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpcmpgtq %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpcmpgtw %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpcmpgtb %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpcmpgtd %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpcmpgtq %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpcmpgtw %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - psubb %mm2, %mm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - psubd %mm2, %mm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - psubq %mm2, %mm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - psubw %mm2, %mm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - psubb %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - psubd %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - psubq %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - psubw %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpsubb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpsubd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpsubq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpsubw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpsubb %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpsubd %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpsubq %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpsubw %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpsubb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpsubd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpsubq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpsubw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpsubb %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpsubd %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpsubq %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpsubw %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - andnps %xmm0, %xmm0
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - andnpd %xmm1, %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vandnps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vandnpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vandnps %ymm2, %ymm2, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vandnpd %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - pandn %mm2, %mm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - pandn %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpandn %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpandn %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vandnps %xmm2, %xmm2, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vandnpd %xmm1, %xmm1, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpandn %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vandnps %ymm2, %ymm2, %ymm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vandnpd %ymm1, %ymm1, %ymm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpandn %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - xorps %xmm0, %xmm0
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - xorpd %xmm1, %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vxorps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vxorpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vxorps %ymm2, %ymm2, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vxorpd %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - pxor %mm2, %mm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - pxor %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpxor %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpxor %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vxorps %xmm4, %xmm4, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vxorpd %xmm1, %xmm1, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vxorps %ymm4, %ymm4, %ymm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vxorpd %ymm1, %ymm1, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpxor %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - vpxor %ymm3, %ymm3, %ymm5
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789
+# CHECK-NEXT: Index 0123456789 012
+
+# CHECK: [0,0] DR . . . . . subl %eax, %eax
+# CHECK-NEXT: [0,1] DR . . . . . subq %rax, %rax
+# CHECK-NEXT: [0,2] DR . . . . . xorl %eax, %eax
+# CHECK-NEXT: [0,3] DR . . . . . xorq %rax, %rax
+# CHECK-NEXT: [0,4] .DeER. . . . . pcmpgtb %mm2, %mm2
+# CHECK-NEXT: [0,5] .D=eER . . . . pcmpgtd %mm2, %mm2
+# CHECK-NEXT: [0,6] .D==eER . . . . pcmpgtw %mm2, %mm2
+# CHECK-NEXT: [0,7] .DeE--R . . . . pcmpgtb %xmm2, %xmm2
+# CHECK-NEXT: [0,8] . DeE-R . . . . pcmpgtd %xmm2, %xmm2
+# CHECK-NEXT: [0,9] . DeE-R . . . . pcmpgtq %xmm2, %xmm2
+# CHECK-NEXT: [0,10] . DeE-R . . . . pcmpgtw %xmm2, %xmm2
+# CHECK-NEXT: [0,11] . D---R . . . . vpcmpgtb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,12] . D--R . . . . vpcmpgtd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,13] . D--R . . . . vpcmpgtq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,14] . D---R . . . . vpcmpgtw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,15] . D---R . . . . vpcmpgtb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,16] . D--R . . . . vpcmpgtd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,17] . D--R . . . . vpcmpgtq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,18] . D--R . . . . vpcmpgtw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,19] . D--R . . . . vpcmpgtb %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,20] . D-R . . . . vpcmpgtd %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,21] . D-R . . . . vpcmpgtq %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,22] . D--R . . . . vpcmpgtw %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,23] . D--R . . . . vpcmpgtb %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,24] . .D-R . . . . vpcmpgtd %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,25] . .D-R . . . . vpcmpgtq %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,26] . .D-R . . . . vpcmpgtw %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,27] . .DeER. . . . psubb %mm2, %mm2
+# CHECK-NEXT: [0,28] . . DeER . . . psubd %mm2, %mm2
+# CHECK-NEXT: [0,29] . . D=eER . . . psubq %mm2, %mm2
+# CHECK-NEXT: [0,30] . . D==eER . . . psubw %mm2, %mm2
+# CHECK-NEXT: [0,31] . . DeE--R . . . psubb %xmm2, %xmm2
+# CHECK-NEXT: [0,32] . . DeE-R . . . psubd %xmm2, %xmm2
+# CHECK-NEXT: [0,33] . . DeE-R . . . psubq %xmm2, %xmm2
+# CHECK-NEXT: [0,34] . . DeE-R . . . psubw %xmm2, %xmm2
+# CHECK-NEXT: [0,35] . . D---R . . . vpsubb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,36] . . D--R . . . vpsubd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,37] . . D--R . . . vpsubq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,38] . . D---R . . . vpsubw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,39] . . D---R . . . vpsubb %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,40] . . D--R . . . vpsubd %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,41] . . D--R . . . vpsubq %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,42] . . D--R . . . vpsubw %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,43] . . D--R . . . vpsubb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,44] . . .D-R . . . vpsubd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,45] . . .D-R . . . vpsubq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,46] . . .D--R. . . vpsubw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,47] . . .D--R. . . vpsubb %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,48] . . . D-R. . . vpsubd %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,49] . . . D-R. . . vpsubq %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,50] . . . D-R. . . vpsubw %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,51] . . . DeER . . andnps %xmm0, %xmm0
+# CHECK-NEXT: [0,52] . . . DeER . . andnpd %xmm1, %xmm1
+# CHECK-NEXT: [0,53] . . . D--R . . vandnps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: [0,54] . . . D--R . . vandnpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: [0,55] . . . D--R . . vandnps %ymm2, %ymm2, %ymm2
+# CHECK-NEXT: [0,56] . . . D-R . . vandnpd %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: [0,57] . . . DeER . . pandn %mm2, %mm2
+# CHECK-NEXT: [0,58] . . . DeER . . pandn %xmm2, %xmm2
+# CHECK-NEXT: [0,59] . . . D--R . . vpandn %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,60] . . . D-R . . vpandn %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,61] . . . D-R . . vandnps %xmm2, %xmm2, %xmm5
+# CHECK-NEXT: [0,62] . . . D-R . . vandnpd %xmm1, %xmm1, %xmm5
+# CHECK-NEXT: [0,63] . . . D-R . . vpandn %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,64] . . . .DR . . vandnps %ymm2, %ymm2, %ymm5
+# CHECK-NEXT: [0,65] . . . .D-R . . vandnpd %ymm1, %ymm1, %ymm5
+# CHECK-NEXT: [0,66] . . . .D-R . . vpandn %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,67] . . . .DeER. . xorps %xmm0, %xmm0
+# CHECK-NEXT: [0,68] . . . . DeER . xorpd %xmm1, %xmm1
+# CHECK-NEXT: [0,69] . . . . D--R . vxorps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: [0,70] . . . . D--R . vxorpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: [0,71] . . . . D--R . vxorps %ymm2, %ymm2, %ymm2
+# CHECK-NEXT: [0,72] . . . . D-R . vxorpd %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: [0,73] . . . . DeER. pxor %mm2, %mm2
+# CHECK-NEXT: [0,74] . . . . DeER. pxor %xmm2, %xmm2
+# CHECK-NEXT: [0,75] . . . . D--R. vpxor %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,76] . . . . D-R. vpxor %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,77] . . . . D-R. vxorps %xmm4, %xmm4, %xmm5
+# CHECK-NEXT: [0,78] . . . . D-R. vxorpd %xmm1, %xmm1, %xmm3
+# CHECK-NEXT: [0,79] . . . . D-R. vxorps %ymm4, %ymm4, %ymm5
+# CHECK-NEXT: [0,80] . . . . DR. vxorpd %ymm1, %ymm1, %ymm3
+# CHECK-NEXT: [0,81] . . . . D-R vpxor %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,82] . . . . D-R vpxor %ymm3, %ymm3, %ymm5
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 0.0 0.0 0.0 subl %eax, %eax
+# CHECK-NEXT: 1. 1 0.0 0.0 0.0 subq %rax, %rax
+# CHECK-NEXT: 2. 1 0.0 0.0 0.0 xorl %eax, %eax
+# CHECK-NEXT: 3. 1 0.0 0.0 0.0 xorq %rax, %rax
+# CHECK-NEXT: 4. 1 1.0 1.0 0.0 pcmpgtb %mm2, %mm2
+# CHECK-NEXT: 5. 1 2.0 0.0 0.0 pcmpgtd %mm2, %mm2
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 pcmpgtw %mm2, %mm2
+# CHECK-NEXT: 7. 1 1.0 1.0 2.0 pcmpgtb %xmm2, %xmm2
+# CHECK-NEXT: 8. 1 1.0 1.0 1.0 pcmpgtd %xmm2, %xmm2
+# CHECK-NEXT: 9. 1 1.0 1.0 1.0 pcmpgtq %xmm2, %xmm2
+# CHECK-NEXT: 10. 1 1.0 1.0 1.0 pcmpgtw %xmm2, %xmm2
+# CHECK-NEXT: 11. 1 0.0 0.0 3.0 vpcmpgtb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 12. 1 0.0 0.0 2.0 vpcmpgtd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 13. 1 0.0 0.0 2.0 vpcmpgtq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 14. 1 0.0 0.0 3.0 vpcmpgtw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 15. 1 0.0 0.0 3.0 vpcmpgtb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 16. 1 0.0 0.0 2.0 vpcmpgtd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 17. 1 0.0 0.0 2.0 vpcmpgtq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 18. 1 0.0 0.0 2.0 vpcmpgtw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 19. 1 0.0 0.0 2.0 vpcmpgtb %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 20. 1 0.0 0.0 1.0 vpcmpgtd %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 21. 1 0.0 0.0 1.0 vpcmpgtq %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 22. 1 0.0 0.0 2.0 vpcmpgtw %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 23. 1 0.0 0.0 2.0 vpcmpgtb %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 24. 1 0.0 0.0 1.0 vpcmpgtd %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 25. 1 0.0 0.0 1.0 vpcmpgtq %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 26. 1 0.0 0.0 1.0 vpcmpgtw %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 27. 1 1.0 1.0 0.0 psubb %mm2, %mm2
+# CHECK-NEXT: 28. 1 1.0 0.0 0.0 psubd %mm2, %mm2
+# CHECK-NEXT: 29. 1 2.0 0.0 0.0 psubq %mm2, %mm2
+# CHECK-NEXT: 30. 1 3.0 0.0 0.0 psubw %mm2, %mm2
+# CHECK-NEXT: 31. 1 1.0 1.0 2.0 psubb %xmm2, %xmm2
+# CHECK-NEXT: 32. 1 1.0 1.0 1.0 psubd %xmm2, %xmm2
+# CHECK-NEXT: 33. 1 1.0 1.0 1.0 psubq %xmm2, %xmm2
+# CHECK-NEXT: 34. 1 1.0 1.0 1.0 psubw %xmm2, %xmm2
+# CHECK-NEXT: 35. 1 0.0 0.0 3.0 vpsubb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 36. 1 0.0 0.0 2.0 vpsubd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 37. 1 0.0 0.0 2.0 vpsubq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 38. 1 0.0 0.0 3.0 vpsubw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 39. 1 0.0 0.0 3.0 vpsubb %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 40. 1 0.0 0.0 2.0 vpsubd %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 41. 1 0.0 0.0 2.0 vpsubq %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 42. 1 0.0 0.0 2.0 vpsubw %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 43. 1 0.0 0.0 2.0 vpsubb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 44. 1 0.0 0.0 1.0 vpsubd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 45. 1 0.0 0.0 1.0 vpsubq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 46. 1 0.0 0.0 2.0 vpsubw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 47. 1 0.0 0.0 2.0 vpsubb %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 48. 1 0.0 0.0 1.0 vpsubd %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 49. 1 0.0 0.0 1.0 vpsubq %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 50. 1 0.0 0.0 1.0 vpsubw %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 51. 1 1.0 1.0 0.0 andnps %xmm0, %xmm0
+# CHECK-NEXT: 52. 1 1.0 1.0 0.0 andnpd %xmm1, %xmm1
+# CHECK-NEXT: 53. 1 0.0 0.0 2.0 vandnps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: 54. 1 0.0 0.0 2.0 vandnpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: 55. 1 0.0 0.0 2.0 vandnps %ymm2, %ymm2, %ymm2
+# CHECK-NEXT: 56. 1 0.0 0.0 1.0 vandnpd %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: 57. 1 1.0 1.0 0.0 pandn %mm2, %mm2
+# CHECK-NEXT: 58. 1 1.0 1.0 0.0 pandn %xmm2, %xmm2
+# CHECK-NEXT: 59. 1 0.0 0.0 2.0 vpandn %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 60. 1 0.0 0.0 1.0 vpandn %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 61. 1 0.0 0.0 1.0 vandnps %xmm2, %xmm2, %xmm5
+# CHECK-NEXT: 62. 1 0.0 0.0 1.0 vandnpd %xmm1, %xmm1, %xmm5
+# CHECK-NEXT: 63. 1 0.0 0.0 1.0 vpandn %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 64. 1 0.0 0.0 0.0 vandnps %ymm2, %ymm2, %ymm5
+# CHECK-NEXT: 65. 1 0.0 0.0 1.0 vandnpd %ymm1, %ymm1, %ymm5
+# CHECK-NEXT: 66. 1 0.0 0.0 1.0 vpandn %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 67. 1 1.0 1.0 0.0 xorps %xmm0, %xmm0
+# CHECK-NEXT: 68. 1 1.0 1.0 0.0 xorpd %xmm1, %xmm1
+# CHECK-NEXT: 69. 1 0.0 0.0 2.0 vxorps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: 70. 1 0.0 0.0 2.0 vxorpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: 71. 1 0.0 0.0 2.0 vxorps %ymm2, %ymm2, %ymm2
+# CHECK-NEXT: 72. 1 0.0 0.0 1.0 vxorpd %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: 73. 1 1.0 1.0 0.0 pxor %mm2, %mm2
+# CHECK-NEXT: 74. 1 1.0 1.0 0.0 pxor %xmm2, %xmm2
+# CHECK-NEXT: 75. 1 0.0 0.0 2.0 vpxor %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 76. 1 0.0 0.0 1.0 vpxor %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 77. 1 0.0 0.0 1.0 vxorps %xmm4, %xmm4, %xmm5
+# CHECK-NEXT: 78. 1 0.0 0.0 1.0 vxorpd %xmm1, %xmm1, %xmm3
+# CHECK-NEXT: 79. 1 0.0 0.0 1.0 vxorps %ymm4, %ymm4, %ymm5
+# CHECK-NEXT: 80. 1 0.0 0.0 0.0 vxorpd %ymm1, %ymm1, %ymm3
+# CHECK-NEXT: 81. 1 0.0 0.0 1.0 vpxor %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 82. 1 0.0 0.0 1.0 vpxor %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 0.3 0.2 1.2 <total>
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/independent-load-stores.s b/llvm/test/tools/llvm-mca/X86/4GM7/independent-load-stores.s
new file mode 100644
index 0000000000000..bd3e2c7626ad3
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/independent-load-stores.s
@@ -0,0 +1,155 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -timeline -timeline-max-iterations=1 < %s | FileCheck %s -check-prefixes=ALL,NOALIAS
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -timeline -timeline-max-iterations=1 -noalias=false < %s | FileCheck %s -check-prefixes=ALL,YESALIAS
+
+ addq $44, 64(%r14)
+ addq $44, 128(%r14)
+ addq $44, 192(%r14)
+ addq $44, 256(%r14)
+ addq $44, 320(%r14)
+ addq $44, 384(%r14)
+ addq $44, 448(%r14)
+ addq $44, 512(%r14)
+ addq $44, 576(%r14)
+ addq $44, 640(%r14)
+
+# ALL: Iterations: 100
+# ALL-NEXT: Instructions: 1000
+
+# NOALIAS-NEXT: Total Cycles: 675
+# YESALIAS-NEXT: Total Cycles: 6003
+
+# ALL-NEXT: Total uOps: 1000
+
+# ALL: Dispatch Width: 4
+
+# NOALIAS-NEXT: uOps Per Cycle: 1.48
+# NOALIAS-NEXT: IPC: 1.48
+
+# YESALIAS-NEXT: uOps Per Cycle: 0.17
+# YESALIAS-NEXT: IPC: 0.17
+
+# ALL-NEXT: Block RThroughput: 6.7
+
+# ALL: Instruction Info:
+# ALL-NEXT: [1]: #uOps
+# ALL-NEXT: [2]: Latency
+# ALL-NEXT: [3]: RThroughput
+# ALL-NEXT: [4]: MayLoad
+# ALL-NEXT: [5]: MayStore
+# ALL-NEXT: [6]: HasSideEffects (U)
+
+# ALL: [1] [2] [3] [4] [5] [6] Instructions:
+# ALL-NEXT: 1 6 0.67 * * addq $44, 64(%r14)
+# ALL-NEXT: 1 6 0.67 * * addq $44, 128(%r14)
+# ALL-NEXT: 1 6 0.67 * * addq $44, 192(%r14)
+# ALL-NEXT: 1 6 0.67 * * addq $44, 256(%r14)
+# ALL-NEXT: 1 6 0.67 * * addq $44, 320(%r14)
+# ALL-NEXT: 1 6 0.67 * * addq $44, 384(%r14)
+# ALL-NEXT: 1 6 0.67 * * addq $44, 448(%r14)
+# ALL-NEXT: 1 6 0.67 * * addq $44, 512(%r14)
+# ALL-NEXT: 1 6 0.67 * * addq $44, 576(%r14)
+# ALL-NEXT: 1 6 0.67 * * addq $44, 640(%r14)
+
+# ALL: Resources:
+# ALL-NEXT: [0] - 4GM7AGU0
+# ALL-NEXT: [1] - 4GM7AGU1
+# ALL-NEXT: [2] - 4GM7AGU2
+# ALL-NEXT: [3] - 4GM7ALU0
+# ALL-NEXT: [4] - 4GM7ALU1
+# ALL-NEXT: [5] - 4GM7ALU2
+# ALL-NEXT: [6] - 4GM7ALU3
+# ALL-NEXT: [7] - 4GM7BRU1
+# ALL-NEXT: [8] - 4GM7FPU0
+# ALL-NEXT: [9] - 4GM7FPU1
+# ALL-NEXT: [10] - 4GM7FPU2
+# ALL-NEXT: [11] - 4GM7FPU3
+# ALL-NEXT: [12.0] - 4GM7LSU
+# ALL-NEXT: [12.1] - 4GM7LSU
+# ALL-NEXT: [12.2] - 4GM7LSU
+# ALL-NEXT: [12.3] - 4GM7LSU
+# ALL-NEXT: [13.0] - 4GM7Load
+# ALL-NEXT: [13.1] - 4GM7Load
+# ALL-NEXT: [13.2] - 4GM7Load
+# ALL-NEXT: [14.0] - 4GM7Store
+# ALL-NEXT: [14.1] - 4GM7Store
+# ALL-NEXT: [14.2] - 4GM7Store
+# ALL-NEXT: [14.3] - 4GM7Store
+
+# ALL: Resource pressure per iteration:
+# ALL-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# ALL-NEXT: 6.66 6.66 6.68 2.50 2.50 2.50 2.50 - - - - - 5.00 5.00 5.00 5.00 3.33 3.33 3.34 2.50 2.50 2.50 2.50
+
+# ALL: Resource pressure by instruction:
+# ALL-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# ALL-NEXT: 0.66 0.66 0.68 - 0.50 - 0.50 - - - - - - 1.00 - 1.00 0.33 0.33 0.34 - 0.50 - 0.50 addq $44, 64(%r14)
+# ALL-NEXT: 0.66 0.68 0.66 0.50 - 0.50 - - - - - - 1.00 - 1.00 - 0.33 0.34 0.33 0.50 - 0.50 - addq $44, 128(%r14)
+# ALL-NEXT: 0.68 0.66 0.66 - 0.50 - 0.50 - - - - - - 1.00 - 1.00 0.34 0.33 0.33 - 0.50 - 0.50 addq $44, 192(%r14)
+# ALL-NEXT: 0.66 0.66 0.68 0.50 - 0.50 - - - - - - 1.00 - 1.00 - 0.33 0.33 0.34 0.50 - 0.50 - addq $44, 256(%r14)
+# ALL-NEXT: 0.66 0.68 0.66 - 0.50 - 0.50 - - - - - - 1.00 - 1.00 0.33 0.34 0.33 - 0.50 - 0.50 addq $44, 320(%r14)
+# ALL-NEXT: 0.68 0.66 0.66 0.50 - 0.50 - - - - - - 1.00 - 1.00 - 0.34 0.33 0.33 0.50 - 0.50 - addq $44, 384(%r14)
+# ALL-NEXT: 0.66 0.66 0.68 - 0.50 - 0.50 - - - - - - 1.00 - 1.00 0.33 0.33 0.34 - 0.50 - 0.50 addq $44, 448(%r14)
+# ALL-NEXT: 0.66 0.68 0.66 0.50 - 0.50 - - - - - - 1.00 - 1.00 - 0.33 0.34 0.33 0.50 - 0.50 - addq $44, 512(%r14)
+# ALL-NEXT: 0.68 0.66 0.66 - 0.50 - 0.50 - - - - - - 1.00 - 1.00 0.34 0.33 0.33 - 0.50 - 0.50 addq $44, 576(%r14)
+# ALL-NEXT: 0.66 0.66 0.68 0.50 - 0.50 - - - - - - 1.00 - 1.00 - 0.33 0.33 0.34 0.50 - 0.50 - addq $44, 640(%r14)
+
+# ALL: Timeline view:
+
+# NOALIAS-NEXT: 01234
+# NOALIAS-NEXT: Index 0123456789
+
+# YESALIAS-NEXT: 0123456789 0123456789 0123456789
+# YESALIAS-NEXT: Index 0123456789 0123456789 0123456789 012
+
+# NOALIAS: [0,0] DeeeeeeER . . addq $44, 64(%r14)
+# NOALIAS-NEXT: [0,1] DeeeeeeER . . addq $44, 128(%r14)
+# NOALIAS-NEXT: [0,2] DeeeeeeER . . addq $44, 192(%r14)
+# NOALIAS-NEXT: [0,3] D==eeeeeeER . addq $44, 256(%r14)
+# NOALIAS-NEXT: [0,4] .D=eeeeeeER . addq $44, 320(%r14)
+# NOALIAS-NEXT: [0,5] .D=eeeeeeER . addq $44, 384(%r14)
+# NOALIAS-NEXT: [0,6] .D===eeeeeeER . addq $44, 448(%r14)
+# NOALIAS-NEXT: [0,7] .D===eeeeeeER . addq $44, 512(%r14)
+# NOALIAS-NEXT: [0,8] . D==eeeeeeER . addq $44, 576(%r14)
+# NOALIAS-NEXT: [0,9] . D====eeeeeeER addq $44, 640(%r14)
+
+# YESALIAS: [0,0] DeeeeeeER . . . . . . . . . . . . addq $44, 64(%r14)
+# YESALIAS-NEXT: [0,1] D======eeeeeeER. . . . . . . . . . . addq $44, 128(%r14)
+# YESALIAS-NEXT: [0,2] D============eeeeeeER . . . . . . . . . addq $44, 192(%r14)
+# YESALIAS-NEXT: [0,3] D==================eeeeeeER . . . . . . . . addq $44, 256(%r14)
+# YESALIAS-NEXT: [0,4] .D=======================eeeeeeER . . . . . . . addq $44, 320(%r14)
+# YESALIAS-NEXT: [0,5] .D=============================eeeeeeER . . . . . . addq $44, 384(%r14)
+# YESALIAS-NEXT: [0,6] .D===================================eeeeeeER. . . . . addq $44, 448(%r14)
+# YESALIAS-NEXT: [0,7] .D=========================================eeeeeeER . . . addq $44, 512(%r14)
+# YESALIAS-NEXT: [0,8] . D==============================================eeeeeeER . . addq $44, 576(%r14)
+# YESALIAS-NEXT: [0,9] . D====================================================eeeeeeER addq $44, 640(%r14)
+
+# ALL: Average Wait times (based on the timeline view):
+# ALL-NEXT: [0]: Executions
+# ALL-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# ALL-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# ALL-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# ALL: [0] [1] [2] [3]
+# ALL-NEXT: 0. 1 1.0 1.0 0.0 addq $44, 64(%r14)
+
+# NOALIAS-NEXT: 1. 1 1.0 0.0 0.0 addq $44, 128(%r14)
+# NOALIAS-NEXT: 2. 1 1.0 0.0 0.0 addq $44, 192(%r14)
+# NOALIAS-NEXT: 3. 1 3.0 2.0 0.0 addq $44, 256(%r14)
+# NOALIAS-NEXT: 4. 1 2.0 0.0 0.0 addq $44, 320(%r14)
+# NOALIAS-NEXT: 5. 1 2.0 0.0 0.0 addq $44, 384(%r14)
+# NOALIAS-NEXT: 6. 1 4.0 2.0 0.0 addq $44, 448(%r14)
+# NOALIAS-NEXT: 7. 1 4.0 0.0 0.0 addq $44, 512(%r14)
+# NOALIAS-NEXT: 8. 1 3.0 0.0 0.0 addq $44, 576(%r14)
+# NOALIAS-NEXT: 9. 1 5.0 2.0 0.0 addq $44, 640(%r14)
+# NOALIAS-NEXT: 1 2.6 0.7 0.0 <total>
+
+# YESALIAS-NEXT: 1. 1 7.0 0.0 0.0 addq $44, 128(%r14)
+# YESALIAS-NEXT: 2. 1 13.0 0.0 0.0 addq $44, 192(%r14)
+# YESALIAS-NEXT: 3. 1 19.0 0.0 0.0 addq $44, 256(%r14)
+# YESALIAS-NEXT: 4. 1 24.0 0.0 0.0 addq $44, 320(%r14)
+# YESALIAS-NEXT: 5. 1 30.0 0.0 0.0 addq $44, 384(%r14)
+# YESALIAS-NEXT: 6. 1 36.0 0.0 0.0 addq $44, 448(%r14)
+# YESALIAS-NEXT: 7. 1 42.0 0.0 0.0 addq $44, 512(%r14)
+# YESALIAS-NEXT: 8. 1 47.0 0.0 0.0 addq $44, 576(%r14)
+# YESALIAS-NEXT: 9. 1 53.0 0.0 0.0 addq $44, 640(%r14)
+# YESALIAS-NEXT: 1 27.2 0.1 0.0 <total>
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/partially-overlapping-group-resources.s b/llvm/test/tools/llvm-mca/X86/4GM7/partially-overlapping-group-resources.s
new file mode 100644
index 0000000000000..595bc4c310586
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/partially-overlapping-group-resources.s
@@ -0,0 +1,91 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -timeline -timeline-max-iterations=1 < %s | FileCheck %s
+
+# This is a test for issue #108157.
+#
+# llvm-mca was crashing when analyzing the following code snippet. This was due to a bug in the
+# instruction issue logic (from class ResourceManager) which was affecting instructions declaring
+# consumption of partially overlapping resources.
+# This test makes sure that analysis is successful, and that no crash occurs.
+
+.intel_syntax
+vpconflictd zmm0, zmm3
+kxnorw k1, k1, k1
+vpxord zmm1, zmm1, zmm1
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 300
+# CHECK-NEXT: Total Cycles: 603
+# CHECK-NEXT: Total uOps: 1800
+
+# CHECK: Dispatch Width: 4
+# CHECK-NEXT: uOps Per Cycle: 2.99
+# CHECK-NEXT: IPC: 0.50
+# CHECK-NEXT: Block RThroughput: 6.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 16 7 6.00 vpconflictd zmm0, zmm3
+# CHECK-NEXT: 1 1 0.25 kxnorw k1, k1, k1
+# CHECK-NEXT: 1 0 0.25 vpxord zmm1, zmm1, zmm1
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: - - - - - - - - 0.50 6.00 0.50 6.00 - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - - 6.00 - 6.00 - - - - - - - - - - - vpconflictd zmm0, zmm3
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - kxnorw k1, k1, k1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpxord zmm1, zmm1, zmm1
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeeER vpconflictd zmm0, zmm3
+# CHECK-NEXT: [0,1] . DeE--R kxnorw k1, k1, k1
+# CHECK-NEXT: [0,2] . D----R vpxord zmm1, zmm1, zmm1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 vpconflictd zmm0, zmm3
+# CHECK-NEXT: 1. 1 1.0 1.0 2.0 kxnorw k1, k1, k1
+# CHECK-NEXT: 2. 1 0.0 0.0 4.0 vpxord zmm1, zmm1, zmm1
+# CHECK-NEXT: 1 0.7 0.7 2.0 <total>
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-adx.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-adx.s
new file mode 100644
index 0000000000000..fbc39b5675ebb
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-adx.s
@@ -0,0 +1,70 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+adcx %ebx, %ecx
+adcx (%rbx), %ecx
+adcx %rbx, %rcx
+adcx (%rbx), %rcx
+
+adox %ebx, %ecx
+adox (%rbx), %ecx
+adox %rbx, %rcx
+adox (%rbx), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.25 adcxl %ebx, %ecx
+# CHECK-NEXT: 1 5 0.33 * adcxl (%rbx), %ecx
+# CHECK-NEXT: 1 1 0.25 adcxq %rbx, %rcx
+# CHECK-NEXT: 1 5 0.33 * adcxq (%rbx), %rcx
+# CHECK-NEXT: 1 1 0.25 adoxl %ebx, %ecx
+# CHECK-NEXT: 1 5 0.33 * adoxl (%rbx), %ecx
+# CHECK-NEXT: 1 1 0.25 adoxq %rbx, %rcx
+# CHECK-NEXT: 1 5 0.33 * adoxq (%rbx), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 1.33 1.33 1.33 2.00 2.00 2.00 2.00 - - - - - 1.00 1.00 1.00 1.00 1.33 1.33 1.33 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - adcxl %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - adcxl (%rbx), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - adcxq %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - adcxq (%rbx), %rcx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - adoxl %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - adoxl (%rbx), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - adoxq %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - adoxq (%rbx), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-aes.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-aes.s
new file mode 100644
index 0000000000000..485a87bd3510b
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-aes.s
@@ -0,0 +1,86 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+aesdec %xmm0, %xmm2
+aesdec (%rax), %xmm2
+
+aesdeclast %xmm0, %xmm2
+aesdeclast (%rax), %xmm2
+
+aesenc %xmm0, %xmm2
+aesenc (%rax), %xmm2
+
+aesenclast %xmm0, %xmm2
+aesenclast (%rax), %xmm2
+
+aesimc %xmm0, %xmm2
+aesimc (%rax), %xmm2
+
+aeskeygenassist $22, %xmm0, %xmm2
+aeskeygenassist $22, (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 aesdec %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * aesdec (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 aesdeclast %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * aesdeclast (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 aesenc %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * aesenc (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 aesenclast %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * aesenclast (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 aesimc %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * aesimc (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 aeskeygenassist $22, %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * aeskeygenassist $22, (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 2.00 2.00 2.00 - - - - - - 6.00 - 6.00 1.50 1.50 1.50 1.50 2.00 2.00 2.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - aesdec %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - aesdec (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - aesdeclast %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - aesdeclast (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - aesenc %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - aesenc (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - aesenclast %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - aesenclast (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - aesimc %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - aesimc (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - aeskeygenassist $22, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - aeskeygenassist $22, (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx1.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx1.s
new file mode 100644
index 0000000000000..298157418cef0
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx1.s
@@ -0,0 +1,2446 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+vaddpd %xmm0, %xmm1, %xmm2
+vaddpd (%rax), %xmm1, %xmm2
+
+vaddpd %ymm0, %ymm1, %ymm2
+vaddpd (%rax), %ymm1, %ymm2
+
+vaddps %xmm0, %xmm1, %xmm2
+vaddps (%rax), %xmm1, %xmm2
+
+vaddps %ymm0, %ymm1, %ymm2
+vaddps (%rax), %ymm1, %ymm2
+
+vaddsd %xmm0, %xmm1, %xmm2
+vaddsd (%rax), %xmm1, %xmm2
+
+vaddss %xmm0, %xmm1, %xmm2
+vaddss (%rax), %xmm1, %xmm2
+
+vaddsubpd %xmm0, %xmm1, %xmm2
+vaddsubpd (%rax), %xmm1, %xmm2
+
+vaddsubpd %ymm0, %ymm1, %ymm2
+vaddsubpd (%rax), %ymm1, %ymm2
+
+vaddsubps %xmm0, %xmm1, %xmm2
+vaddsubps (%rax), %xmm1, %xmm2
+
+vaddsubps %ymm0, %ymm1, %ymm2
+vaddsubps (%rax), %ymm1, %ymm2
+
+vaesdec %xmm0, %xmm1, %xmm2
+vaesdec (%rax), %xmm1, %xmm2
+
+vaesdeclast %xmm0, %xmm1, %xmm2
+vaesdeclast (%rax), %xmm1, %xmm2
+
+vaesenc %xmm0, %xmm1, %xmm2
+vaesenc (%rax), %xmm1, %xmm2
+
+vaesenclast %xmm0, %xmm1, %xmm2
+vaesenclast (%rax), %xmm1, %xmm2
+
+vaesimc %xmm0, %xmm2
+vaesimc (%rax), %xmm2
+
+vaeskeygenassist $22, %xmm0, %xmm2
+vaeskeygenassist $22, (%rax), %xmm2
+
+vandnpd %xmm0, %xmm1, %xmm2
+vandnpd (%rax), %xmm1, %xmm2
+
+vandnpd %ymm0, %ymm1, %ymm2
+vandnpd (%rax), %ymm1, %ymm2
+
+vandnps %xmm0, %xmm1, %xmm2
+vandnps (%rax), %xmm1, %xmm2
+
+vandnps %ymm0, %ymm1, %ymm2
+vandnps (%rax), %ymm1, %ymm2
+
+vandpd %xmm0, %xmm1, %xmm2
+vandpd (%rax), %xmm1, %xmm2
+
+vandpd %ymm0, %ymm1, %ymm2
+vandpd (%rax), %ymm1, %ymm2
+
+vandps %xmm0, %xmm1, %xmm2
+vandps (%rax), %xmm1, %xmm2
+
+vandps %ymm0, %ymm1, %ymm2
+vandps (%rax), %ymm1, %ymm2
+
+vblendpd $11, %xmm0, %xmm1, %xmm2
+vblendpd $11, (%rax), %xmm1, %xmm2
+
+vblendpd $11, %ymm0, %ymm1, %ymm2
+vblendpd $11, (%rax), %ymm1, %ymm2
+
+vblendps $11, %xmm0, %xmm1, %xmm2
+vblendps $11, (%rax), %xmm1, %xmm2
+
+vblendps $11, %ymm0, %ymm1, %ymm2
+vblendps $11, (%rax), %ymm1, %ymm2
+
+vblendvpd %xmm3, %xmm0, %xmm1, %xmm2
+vblendvpd %xmm3, (%rax), %xmm1, %xmm2
+
+vblendvpd %ymm3, %ymm0, %ymm1, %ymm2
+vblendvpd %ymm3, (%rax), %ymm1, %ymm2
+
+vblendvps %xmm3, %xmm0, %xmm1, %xmm2
+vblendvps %xmm3, (%rax), %xmm1, %xmm2
+
+vblendvps %ymm3, %ymm0, %ymm1, %ymm2
+vblendvps %ymm3, (%rax), %ymm1, %ymm2
+
+vbroadcastf128 (%rax), %ymm2
+
+vbroadcastsd (%rax), %ymm2
+
+vbroadcastss (%rax), %xmm2
+vbroadcastss (%rax), %ymm2
+
+vcmppd $0, %xmm0, %xmm1, %xmm2
+vcmppd $0, (%rax), %xmm1, %xmm2
+
+vcmppd $0, %ymm0, %ymm1, %ymm2
+vcmppd $0, (%rax), %ymm1, %ymm2
+
+vcmpps $0, %xmm0, %xmm1, %xmm2
+vcmpps $0, (%rax), %xmm1, %xmm2
+
+vcmpps $0, %ymm0, %ymm1, %ymm2
+vcmpps $0, (%rax), %ymm1, %ymm2
+
+vcmpsd $0, %xmm0, %xmm1, %xmm2
+vcmpsd $0, (%rax), %xmm1, %xmm2
+
+vcmpss $0, %xmm0, %xmm1, %xmm2
+vcmpss $0, (%rax), %xmm1, %xmm2
+
+vcomisd %xmm0, %xmm1
+vcomisd (%rax), %xmm1
+
+vcomiss %xmm0, %xmm1
+vcomiss (%rax), %xmm1
+
+vcvtdq2pd %xmm0, %xmm2
+vcvtdq2pd (%rax), %xmm2
+
+vcvtdq2pd %xmm0, %ymm2
+vcvtdq2pd (%rax), %ymm2
+
+vcvtdq2ps %xmm0, %xmm2
+vcvtdq2ps (%rax), %xmm2
+
+vcvtdq2ps %ymm0, %ymm2
+vcvtdq2ps (%rax), %ymm2
+
+vcvtpd2dqx %xmm0, %xmm2
+vcvtpd2dqx (%rax), %xmm2
+
+vcvtpd2dqy %ymm0, %xmm2
+vcvtpd2dqy (%rax), %xmm2
+
+vcvtpd2psx %xmm0, %xmm2
+vcvtpd2psx (%rax), %xmm2
+
+vcvtpd2psy %ymm0, %xmm2
+vcvtpd2psy (%rax), %xmm2
+
+vcvtps2dq %xmm0, %xmm2
+vcvtps2dq (%rax), %xmm2
+
+vcvtps2dq %ymm0, %ymm2
+vcvtps2dq (%rax), %ymm2
+
+vcvtps2pd %xmm0, %xmm2
+vcvtps2pd (%rax), %xmm2
+
+vcvtps2pd %xmm0, %ymm2
+vcvtps2pd (%rax), %ymm2
+
+vcvtsd2si %xmm0, %ecx
+vcvtsd2si %xmm0, %rcx
+vcvtsd2si (%rax), %ecx
+vcvtsd2si (%rax), %rcx
+
+vcvtsd2ss %xmm0, %xmm1, %xmm2
+vcvtsd2ss (%rax), %xmm1, %xmm2
+
+vcvtsi2sdl %ecx, %xmm0, %xmm2
+vcvtsi2sdq %rcx, %xmm0, %xmm2
+vcvtsi2sdl (%rax), %xmm0, %xmm2
+vcvtsi2sdq (%rax), %xmm0, %xmm2
+
+vcvtsi2ssl %ecx, %xmm0, %xmm2
+vcvtsi2ssq %rcx, %xmm0, %xmm2
+vcvtsi2ssl (%rax), %xmm0, %xmm2
+vcvtsi2ssq (%rax), %xmm0, %xmm2
+
+vcvtss2sd %xmm0, %xmm1, %xmm2
+vcvtss2sd (%rax), %xmm1, %xmm2
+
+vcvtss2si %xmm0, %ecx
+vcvtss2si %xmm0, %rcx
+vcvtss2si (%rax), %ecx
+vcvtss2si (%rax), %rcx
+
+vcvttpd2dqx %xmm0, %xmm2
+vcvttpd2dqx (%rax), %xmm2
+
+vcvttpd2dqy %ymm0, %xmm2
+vcvttpd2dqy (%rax), %xmm2
+
+vcvttps2dq %xmm0, %xmm2
+vcvttps2dq (%rax), %xmm2
+
+vcvttps2dq %ymm0, %ymm2
+vcvttps2dq (%rax), %ymm2
+
+vcvttsd2si %xmm0, %ecx
+vcvttsd2si %xmm0, %rcx
+vcvttsd2si (%rax), %ecx
+vcvttsd2si (%rax), %rcx
+
+vcvttss2si %xmm0, %ecx
+vcvttss2si %xmm0, %rcx
+vcvttss2si (%rax), %ecx
+vcvttss2si (%rax), %rcx
+
+vdivpd %xmm0, %xmm1, %xmm2
+vdivpd (%rax), %xmm1, %xmm2
+
+vdivpd %ymm0, %ymm1, %ymm2
+vdivpd (%rax), %ymm1, %ymm2
+
+vdivps %xmm0, %xmm1, %xmm2
+vdivps (%rax), %xmm1, %xmm2
+
+vdivps %ymm0, %ymm1, %ymm2
+vdivps (%rax), %ymm1, %ymm2
+
+vdivsd %xmm0, %xmm1, %xmm2
+vdivsd (%rax), %xmm1, %xmm2
+
+vdivss %xmm0, %xmm1, %xmm2
+vdivss (%rax), %xmm1, %xmm2
+
+vdppd $22, %xmm0, %xmm1, %xmm2
+vdppd $22, (%rax), %xmm1, %xmm2
+
+vdpps $22, %xmm0, %xmm1, %xmm2
+vdpps $22, (%rax), %xmm1, %xmm2
+
+vdpps $22, %ymm0, %ymm1, %ymm2
+vdpps $22, (%rax), %ymm1, %ymm2
+
+vextractf128 $1, %ymm0, %xmm2
+vextractf128 $1, %ymm0, (%rax)
+
+vextractps $1, %xmm0, %rcx
+vextractps $1, %xmm0, (%rax)
+
+vhaddpd %xmm0, %xmm1, %xmm2
+vhaddpd (%rax), %xmm1, %xmm2
+
+vhaddpd %ymm0, %ymm1, %ymm2
+vhaddpd (%rax), %ymm1, %ymm2
+
+vhaddps %xmm0, %xmm1, %xmm2
+vhaddps (%rax), %xmm1, %xmm2
+
+vhaddps %ymm0, %ymm1, %ymm2
+vhaddps (%rax), %ymm1, %ymm2
+
+vhsubpd %xmm0, %xmm1, %xmm2
+vhsubpd (%rax), %xmm1, %xmm2
+
+vhsubpd %ymm0, %ymm1, %ymm2
+vhsubpd (%rax), %ymm1, %ymm2
+
+vhsubps %xmm0, %xmm1, %xmm2
+vhsubps (%rax), %xmm1, %xmm2
+
+vhsubps %ymm0, %ymm1, %ymm2
+vhsubps (%rax), %ymm1, %ymm2
+
+vinsertf128 $1, %xmm0, %ymm1, %ymm2
+vinsertf128 $1, (%rax), %ymm1, %ymm2
+
+vinsertps $1, %xmm0, %xmm1, %xmm2
+vinsertps $1, (%rax), %xmm1, %xmm2
+
+vlddqu (%rax), %xmm2
+vlddqu (%rax), %ymm2
+
+vldmxcsr (%rax)
+
+vmaskmovdqu %xmm0, %xmm1
+
+vmaskmovpd (%rax), %xmm0, %xmm2
+vmaskmovpd (%rax), %ymm0, %ymm2
+
+vmaskmovpd %xmm0, %xmm1, (%rax)
+vmaskmovpd %ymm0, %ymm1, (%rax)
+
+vmaskmovps (%rax), %xmm0, %xmm2
+vmaskmovps (%rax), %ymm0, %ymm2
+
+vmaskmovps %xmm0, %xmm1, (%rax)
+vmaskmovps %ymm0, %ymm1, (%rax)
+
+vmaxpd %xmm0, %xmm1, %xmm2
+vmaxpd (%rax), %xmm1, %xmm2
+
+vmaxpd %ymm0, %ymm1, %ymm2
+vmaxpd (%rax), %ymm1, %ymm2
+
+vmaxps %xmm0, %xmm1, %xmm2
+vmaxps (%rax), %xmm1, %xmm2
+
+vmaxps %ymm0, %ymm1, %ymm2
+vmaxps (%rax), %ymm1, %ymm2
+
+vmaxsd %xmm0, %xmm1, %xmm2
+vmaxsd (%rax), %xmm1, %xmm2
+
+vmaxss %xmm0, %xmm1, %xmm2
+vmaxss (%rax), %xmm1, %xmm2
+
+vminpd %xmm0, %xmm1, %xmm2
+vminpd (%rax), %xmm1, %xmm2
+
+vminpd %ymm0, %ymm1, %ymm2
+vminpd (%rax), %ymm1, %ymm2
+
+vminps %xmm0, %xmm1, %xmm2
+vminps (%rax), %xmm1, %xmm2
+
+vminps %ymm0, %ymm1, %ymm2
+vminps (%rax), %ymm1, %ymm2
+
+vminsd %xmm0, %xmm1, %xmm2
+vminsd (%rax), %xmm1, %xmm2
+
+vminss %xmm0, %xmm1, %xmm2
+vminss (%rax), %xmm1, %xmm2
+
+vmovapd %xmm0, %xmm2
+vmovapd %xmm0, (%rax)
+vmovapd (%rax), %xmm2
+
+vmovapd %ymm0, %ymm2
+vmovapd %ymm0, (%rax)
+vmovapd (%rax), %ymm2
+
+vmovaps %xmm0, %xmm2
+vmovaps %xmm0, (%rax)
+vmovaps (%rax), %xmm2
+
+vmovaps %ymm0, %ymm2
+vmovaps %ymm0, (%rax)
+vmovaps (%rax), %ymm2
+
+vmovd %eax, %xmm2
+vmovd (%rax), %xmm2
+
+vmovd %xmm0, %ecx
+vmovd %xmm0, (%rax)
+
+vmovddup %xmm0, %xmm2
+vmovddup (%rax), %xmm2
+
+vmovddup %ymm0, %ymm2
+vmovddup (%rax), %ymm2
+
+vmovdqa %xmm0, %xmm2
+vmovdqa %xmm0, (%rax)
+vmovdqa (%rax), %xmm2
+
+vmovdqa %ymm0, %ymm2
+vmovdqa %ymm0, (%rax)
+vmovdqa (%rax), %ymm2
+
+vmovdqu %xmm0, %xmm2
+vmovdqu %xmm0, (%rax)
+vmovdqu (%rax), %xmm2
+
+vmovdqu %ymm0, %ymm2
+vmovdqu %ymm0, (%rax)
+vmovdqu (%rax), %ymm2
+
+vmovhlps %xmm0, %xmm1, %xmm2
+vmovlhps %xmm0, %xmm1, %xmm2
+
+vmovhpd %xmm0, (%rax)
+vmovhpd (%rax), %xmm1, %xmm2
+
+vmovhps %xmm0, (%rax)
+vmovhps (%rax), %xmm1, %xmm2
+
+vmovlpd %xmm0, (%rax)
+vmovlpd (%rax), %xmm1, %xmm2
+
+vmovlps %xmm0, (%rax)
+vmovlps (%rax), %xmm1, %xmm2
+
+vmovmskpd %xmm0, %rcx
+vmovmskpd %ymm0, %rcx
+
+vmovmskps %xmm0, %rcx
+vmovmskps %ymm0, %rcx
+
+vmovntdq %xmm0, (%rax)
+vmovntdq %ymm0, (%rax)
+
+vmovntdqa (%rax), %xmm2
+vmovntdqa (%rax), %ymm2
+
+vmovntpd %xmm0, (%rax)
+vmovntpd %ymm0, (%rax)
+
+vmovntps %xmm0, (%rax)
+vmovntps %ymm0, (%rax)
+
+vmovq %xmm0, %xmm2
+
+vmovq %rax, %xmm2
+vmovq (%rax), %xmm2
+
+vmovq %xmm0, %rcx
+vmovq %xmm0, (%rax)
+
+vmovsd %xmm0, %xmm1, %xmm2
+vmovsd %xmm0, (%rax)
+vmovsd (%rax), %xmm2
+
+vmovshdup %xmm0, %xmm2
+vmovshdup (%rax), %xmm2
+
+vmovshdup %ymm0, %ymm2
+vmovshdup (%rax), %ymm2
+
+vmovsldup %xmm0, %xmm2
+vmovsldup (%rax), %xmm2
+
+vmovsldup %ymm0, %ymm2
+vmovsldup (%rax), %ymm2
+
+vmovss %xmm0, %xmm1, %xmm2
+vmovss %xmm0, (%rax)
+vmovss (%rax), %xmm2
+
+vmovupd %xmm0, %xmm2
+vmovupd %xmm0, (%rax)
+vmovupd (%rax), %xmm2
+
+vmovupd %ymm0, %ymm2
+vmovupd %ymm0, (%rax)
+vmovupd (%rax), %ymm2
+
+vmovups %xmm0, %xmm2
+vmovups %xmm0, (%rax)
+vmovups (%rax), %xmm2
+
+vmovups %ymm0, %ymm2
+vmovups %ymm0, (%rax)
+vmovups (%rax), %ymm2
+
+vmpsadbw $1, %xmm0, %xmm1, %xmm2
+vmpsadbw $1, (%rax), %xmm1, %xmm2
+
+vmulpd %xmm0, %xmm1, %xmm2
+vmulpd (%rax), %xmm1, %xmm2
+
+vmulpd %ymm0, %ymm1, %ymm2
+vmulpd (%rax), %ymm1, %ymm2
+
+vmulps %xmm0, %xmm1, %xmm2
+vmulps (%rax), %xmm1, %xmm2
+
+vmulps %ymm0, %ymm1, %ymm2
+vmulps (%rax), %ymm1, %ymm2
+
+vmulsd %xmm0, %xmm1, %xmm2
+vmulsd (%rax), %xmm1, %xmm2
+
+vmulss %xmm0, %xmm1, %xmm2
+vmulss (%rax), %xmm1, %xmm2
+
+vorpd %xmm0, %xmm1, %xmm2
+vorpd (%rax), %xmm1, %xmm2
+
+vorpd %ymm0, %ymm1, %ymm2
+vorpd (%rax), %ymm1, %ymm2
+
+vorps %xmm0, %xmm1, %xmm2
+vorps (%rax), %xmm1, %xmm2
+
+vorps %ymm0, %ymm1, %ymm2
+vorps (%rax), %ymm1, %ymm2
+
+vpabsb %xmm0, %xmm2
+vpabsb (%rax), %xmm2
+
+vpabsd %xmm0, %xmm2
+vpabsd (%rax), %xmm2
+
+vpabsw %xmm0, %xmm2
+vpabsw (%rax), %xmm2
+
+vpackssdw %xmm0, %xmm1, %xmm2
+vpackssdw (%rax), %xmm1, %xmm2
+
+vpacksswb %xmm0, %xmm1, %xmm2
+vpacksswb (%rax), %xmm1, %xmm2
+
+vpackusdw %xmm0, %xmm1, %xmm2
+vpackusdw (%rax), %xmm1, %xmm2
+
+vpackuswb %xmm0, %xmm1, %xmm2
+vpackuswb (%rax), %xmm1, %xmm2
+
+vpaddb %xmm0, %xmm1, %xmm2
+vpaddb (%rax), %xmm1, %xmm2
+
+vpaddd %xmm0, %xmm1, %xmm2
+vpaddd (%rax), %xmm1, %xmm2
+
+vpaddq %xmm0, %xmm1, %xmm2
+vpaddq (%rax), %xmm1, %xmm2
+
+vpaddsb %xmm0, %xmm1, %xmm2
+vpaddsb (%rax), %xmm1, %xmm2
+
+vpaddsw %xmm0, %xmm1, %xmm2
+vpaddsw (%rax), %xmm1, %xmm2
+
+vpaddusb %xmm0, %xmm1, %xmm2
+vpaddusb (%rax), %xmm1, %xmm2
+
+vpaddusw %xmm0, %xmm1, %xmm2
+vpaddusw (%rax), %xmm1, %xmm2
+
+vpaddw %xmm0, %xmm1, %xmm2
+vpaddw (%rax), %xmm1, %xmm2
+
+vpalignr $1, %xmm0, %xmm1, %xmm2
+vpalignr $1, (%rax), %xmm1, %xmm2
+
+vpand %xmm0, %xmm1, %xmm2
+vpand (%rax), %xmm1, %xmm2
+
+vpandn %xmm0, %xmm1, %xmm2
+vpandn (%rax), %xmm1, %xmm2
+
+vpavgb %xmm0, %xmm1, %xmm2
+vpavgb (%rax), %xmm1, %xmm2
+
+vpavgw %xmm0, %xmm1, %xmm2
+vpavgw (%rax), %xmm1, %xmm2
+
+vpblendvb %xmm3, %xmm0, %xmm1, %xmm2
+vpblendvb %xmm3, (%rax), %xmm1, %xmm2
+
+vpblendw $11, %xmm0, %xmm1, %xmm2
+vpblendw $11, (%rax), %xmm1, %xmm2
+
+vpclmulqdq $11, %xmm0, %xmm1, %xmm2
+vpclmulqdq $11, (%rax), %xmm1, %xmm2
+
+vpcmpeqb %xmm0, %xmm1, %xmm2
+vpcmpeqb (%rax), %xmm1, %xmm2
+
+vpcmpeqd %xmm0, %xmm1, %xmm2
+vpcmpeqd (%rax), %xmm1, %xmm2
+
+vpcmpeqq %xmm0, %xmm1, %xmm2
+vpcmpeqq (%rax), %xmm1, %xmm2
+
+vpcmpeqw %xmm0, %xmm1, %xmm2
+vpcmpeqw (%rax), %xmm1, %xmm2
+
+vpcmpestri $1, %xmm0, %xmm2
+vpcmpestri $1, (%rax), %xmm2
+
+vpcmpestrm $1, %xmm0, %xmm2
+vpcmpestrm $1, (%rax), %xmm2
+
+vpcmpgtb %xmm0, %xmm1, %xmm2
+vpcmpgtb (%rax), %xmm1, %xmm2
+
+vpcmpgtd %xmm0, %xmm1, %xmm2
+vpcmpgtd (%rax), %xmm1, %xmm2
+
+vpcmpgtq %xmm0, %xmm1, %xmm2
+vpcmpgtq (%rax), %xmm1, %xmm2
+
+vpcmpgtw %xmm0, %xmm1, %xmm2
+vpcmpgtw (%rax), %xmm1, %xmm2
+
+vpcmpistri $1, %xmm0, %xmm2
+vpcmpistri $1, (%rax), %xmm2
+
+vpcmpistrm $1, %xmm0, %xmm2
+vpcmpistrm $1, (%rax), %xmm2
+
+vperm2f128 $1, %ymm0, %ymm1, %ymm2
+vperm2f128 $1, (%rax), %ymm1, %ymm2
+
+vpermilpd $1, %xmm0, %xmm2
+vpermilpd $1, (%rax), %xmm2
+vpermilpd %xmm0, %xmm1, %xmm2
+vpermilpd (%rax), %xmm1, %xmm2
+
+vpermilpd $1, %ymm0, %ymm2
+vpermilpd $1, (%rax), %ymm2
+vpermilpd %ymm0, %ymm1, %ymm2
+vpermilpd (%rax), %ymm1, %ymm2
+
+vpermilps $1, %xmm0, %xmm2
+vpermilps $1, (%rax), %xmm2
+vpermilps %xmm0, %xmm1, %xmm2
+vpermilps (%rax), %xmm1, %xmm2
+
+vpermilps $1, %ymm0, %ymm2
+vpermilps $1, (%rax), %ymm2
+vpermilps %ymm0, %ymm1, %ymm2
+vpermilps (%rax), %ymm1, %ymm2
+
+vpextrb $1, %xmm0, %ecx
+vpextrb $1, %xmm0, (%rax)
+
+vpextrd $1, %xmm0, %ecx
+vpextrd $1, %xmm0, (%rax)
+
+vpextrq $1, %xmm0, %rcx
+vpextrq $1, %xmm0, (%rax)
+
+vpextrw $1, %xmm0, %ecx
+vpextrw $1, %xmm0, (%rax)
+
+vphaddd %xmm0, %xmm1, %xmm2
+vphaddd (%rax), %xmm1, %xmm2
+
+vphaddsw %xmm0, %xmm1, %xmm2
+vphaddsw (%rax), %xmm1, %xmm2
+
+vphaddw %xmm0, %xmm1, %xmm2
+vphaddw (%rax), %xmm1, %xmm2
+
+vphminposuw %xmm0, %xmm2
+vphminposuw (%rax), %xmm2
+
+vphsubd %xmm0, %xmm1, %xmm2
+vphsubd (%rax), %xmm1, %xmm2
+
+vphsubsw %xmm0, %xmm1, %xmm2
+vphsubsw (%rax), %xmm1, %xmm2
+
+vphsubw %xmm0, %xmm1, %xmm2
+vphsubw (%rax), %xmm1, %xmm2
+
+vpinsrb $1, %eax, %xmm1, %xmm2
+vpinsrb $1, (%rax), %xmm1, %xmm2
+
+vpinsrd $1, %eax, %xmm1, %xmm2
+vpinsrd $1, (%rax), %xmm1, %xmm2
+
+vpinsrq $1, %rax, %xmm1, %xmm2
+vpinsrq $1, (%rax), %xmm1, %xmm2
+
+vpinsrw $1, %eax, %xmm1, %xmm2
+vpinsrw $1, (%rax), %xmm1, %xmm2
+
+vpmaddubsw %xmm0, %xmm1, %xmm2
+vpmaddubsw (%rax), %xmm1, %xmm2
+
+vpmaddwd %xmm0, %xmm1, %xmm2
+vpmaddwd (%rax), %xmm1, %xmm2
+
+vpmaxsb %xmm0, %xmm1, %xmm2
+vpmaxsb (%rax), %xmm1, %xmm2
+
+vpmaxsd %xmm0, %xmm1, %xmm2
+vpmaxsd (%rax), %xmm1, %xmm2
+
+vpmaxsw %xmm0, %xmm1, %xmm2
+vpmaxsw (%rax), %xmm1, %xmm2
+
+vpmaxub %xmm0, %xmm1, %xmm2
+vpmaxub (%rax), %xmm1, %xmm2
+
+vpmaxud %xmm0, %xmm1, %xmm2
+vpmaxud (%rax), %xmm1, %xmm2
+
+vpmaxuw %xmm0, %xmm1, %xmm2
+vpmaxuw (%rax), %xmm1, %xmm2
+
+vpminsb %xmm0, %xmm1, %xmm2
+vpminsb (%rax), %xmm1, %xmm2
+
+vpminsd %xmm0, %xmm1, %xmm2
+vpminsd (%rax), %xmm1, %xmm2
+
+vpminsw %xmm0, %xmm1, %xmm2
+vpminsw (%rax), %xmm1, %xmm2
+
+vpminub %xmm0, %xmm1, %xmm2
+vpminub (%rax), %xmm1, %xmm2
+
+vpminud %xmm0, %xmm1, %xmm2
+vpminud (%rax), %xmm1, %xmm2
+
+vpminuw %xmm0, %xmm1, %xmm2
+vpminuw (%rax), %xmm1, %xmm2
+
+vpmovmskb %xmm0, %rcx
+
+vpmovsxbd %xmm0, %xmm2
+vpmovsxbd (%rax), %xmm2
+
+vpmovsxbq %xmm0, %xmm2
+vpmovsxbq (%rax), %xmm2
+
+vpmovsxbw %xmm0, %xmm2
+vpmovsxbw (%rax), %xmm2
+
+vpmovsxdq %xmm0, %xmm2
+vpmovsxdq (%rax), %xmm2
+
+vpmovsxwd %xmm0, %xmm2
+vpmovsxwd (%rax), %xmm2
+
+vpmovsxwq %xmm0, %xmm2
+vpmovsxwq (%rax), %xmm2
+
+vpmovzxbd %xmm0, %xmm2
+vpmovzxbd (%rax), %xmm2
+
+vpmovzxbq %xmm0, %xmm2
+vpmovzxbq (%rax), %xmm2
+
+vpmovzxbw %xmm0, %xmm2
+vpmovzxbw (%rax), %xmm2
+
+vpmovzxdq %xmm0, %xmm2
+vpmovzxdq (%rax), %xmm2
+
+vpmovzxwd %xmm0, %xmm2
+vpmovzxwd (%rax), %xmm2
+
+vpmovzxwq %xmm0, %xmm2
+vpmovzxwq (%rax), %xmm2
+
+vpmuldq %xmm0, %xmm1, %xmm2
+vpmuldq (%rax), %xmm1, %xmm2
+
+vpmulhrsw %xmm0, %xmm1, %xmm2
+vpmulhrsw (%rax), %xmm1, %xmm2
+
+vpmulhuw %xmm0, %xmm1, %xmm2
+vpmulhuw (%rax), %xmm1, %xmm2
+
+vpmulhw %xmm0, %xmm1, %xmm2
+vpmulhw (%rax), %xmm1, %xmm2
+
+vpmulld %xmm0, %xmm1, %xmm2
+vpmulld (%rax), %xmm1, %xmm2
+
+vpmullw %xmm0, %xmm1, %xmm2
+vpmullw (%rax), %xmm1, %xmm2
+
+vpmuludq %xmm0, %xmm1, %xmm2
+vpmuludq (%rax), %xmm1, %xmm2
+
+vpor %xmm0, %xmm1, %xmm2
+vpor (%rax), %xmm1, %xmm2
+
+vpsadbw %xmm0, %xmm1, %xmm2
+vpsadbw (%rax), %xmm1, %xmm2
+
+vpshufb %xmm0, %xmm1, %xmm2
+vpshufb (%rax), %xmm1, %xmm2
+
+vpshufd $1, %xmm0, %xmm2
+vpshufd $1, (%rax), %xmm2
+
+vpshufhw $1, %xmm0, %xmm2
+vpshufhw $1, (%rax), %xmm2
+
+vpshuflw $1, %xmm0, %xmm2
+vpshuflw $1, (%rax), %xmm2
+
+vpsignb %xmm0, %xmm1, %xmm2
+vpsignb (%rax), %xmm1, %xmm2
+
+vpsignd %xmm0, %xmm1, %xmm2
+vpsignd (%rax), %xmm1, %xmm2
+
+vpsignw %xmm0, %xmm1, %xmm2
+vpsignw (%rax), %xmm1, %xmm2
+
+vpslld $1, %xmm0, %xmm2
+vpslld %xmm0, %xmm1, %xmm2
+vpslld (%rax), %xmm1, %xmm2
+
+vpslldq $1, %xmm1, %xmm2
+
+vpsllq $1, %xmm0, %xmm2
+vpsllq %xmm0, %xmm1, %xmm2
+vpsllq (%rax), %xmm1, %xmm2
+
+vpsllw $1, %xmm0, %xmm2
+vpsllw %xmm0, %xmm1, %xmm2
+vpsllw (%rax), %xmm1, %xmm2
+
+vpsrad $1, %xmm0, %xmm2
+vpsrad %xmm0, %xmm1, %xmm2
+vpsrad (%rax), %xmm1, %xmm2
+
+vpsraw $1, %xmm0, %xmm2
+vpsraw %xmm0, %xmm1, %xmm2
+vpsraw (%rax), %xmm1, %xmm2
+
+vpsrld $1, %xmm0, %xmm2
+vpsrld %xmm0, %xmm1, %xmm2
+vpsrld (%rax), %xmm1, %xmm2
+
+vpsrldq $1, %xmm1, %xmm2
+
+vpsrlq $1, %xmm0, %xmm2
+vpsrlq %xmm0, %xmm1, %xmm2
+vpsrlq (%rax), %xmm1, %xmm2
+
+vpsrlw $1, %xmm0, %xmm2
+vpsrlw %xmm0, %xmm1, %xmm2
+vpsrlw (%rax), %xmm1, %xmm2
+
+vpsubb %xmm0, %xmm1, %xmm2
+vpsubb (%rax), %xmm1, %xmm2
+
+vpsubd %xmm0, %xmm1, %xmm2
+vpsubd (%rax), %xmm1, %xmm2
+
+vpsubq %xmm0, %xmm1, %xmm2
+vpsubq (%rax), %xmm1, %xmm2
+
+vpsubsb %xmm0, %xmm1, %xmm2
+vpsubsb (%rax), %xmm1, %xmm2
+
+vpsubsw %xmm0, %xmm1, %xmm2
+vpsubsw (%rax), %xmm1, %xmm2
+
+vpsubusb %xmm0, %xmm1, %xmm2
+vpsubusb (%rax), %xmm1, %xmm2
+
+vpsubusw %xmm0, %xmm1, %xmm2
+vpsubusw (%rax), %xmm1, %xmm2
+
+vpsubw %xmm0, %xmm1, %xmm2
+vpsubw (%rax), %xmm1, %xmm2
+
+vptest %xmm0, %xmm1
+vptest (%rax), %xmm1
+
+vptest %ymm0, %ymm1
+vptest (%rax), %ymm1
+
+vpunpckhbw %xmm0, %xmm1, %xmm2
+vpunpckhbw (%rax), %xmm1, %xmm2
+
+vpunpckhdq %xmm0, %xmm1, %xmm2
+vpunpckhdq (%rax), %xmm1, %xmm2
+
+vpunpckhqdq %xmm0, %xmm1, %xmm2
+vpunpckhqdq (%rax), %xmm1, %xmm2
+
+vpunpckhwd %xmm0, %xmm1, %xmm2
+vpunpckhwd (%rax), %xmm1, %xmm2
+
+vpunpcklbw %xmm0, %xmm1, %xmm2
+vpunpcklbw (%rax), %xmm1, %xmm2
+
+vpunpckldq %xmm0, %xmm1, %xmm2
+vpunpckldq (%rax), %xmm1, %xmm2
+
+vpunpcklqdq %xmm0, %xmm1, %xmm2
+vpunpcklqdq (%rax), %xmm1, %xmm2
+
+vpunpcklwd %xmm0, %xmm1, %xmm2
+vpunpcklwd (%rax), %xmm1, %xmm2
+
+vpxor %xmm0, %xmm1, %xmm2
+vpxor (%rax), %xmm1, %xmm2
+
+vrcpps %xmm0, %xmm2
+vrcpps (%rax), %xmm2
+
+vrcpps %ymm0, %ymm2
+vrcpps (%rax), %ymm2
+
+vrcpss %xmm0, %xmm1, %xmm2
+vrcpss (%rax), %xmm1, %xmm2
+
+vroundpd $1, %xmm0, %xmm2
+vroundpd $1, (%rax), %xmm2
+
+vroundpd $1, %ymm0, %ymm2
+vroundpd $1, (%rax), %ymm2
+
+vroundps $1, %xmm0, %xmm2
+vroundps $1, (%rax), %xmm2
+
+vroundps $1, %ymm0, %ymm2
+vroundps $1, (%rax), %ymm2
+
+vroundsd $1, %xmm0, %xmm1, %xmm2
+vroundsd $1, (%rax), %xmm1, %xmm2
+
+vroundss $1, %xmm0, %xmm1, %xmm2
+vroundss $1, (%rax), %xmm1, %xmm2
+
+vrsqrtps %xmm0, %xmm2
+vrsqrtps (%rax), %xmm2
+
+vrsqrtps %ymm0, %ymm2
+vrsqrtps (%rax), %ymm2
+
+vrsqrtss %xmm0, %xmm1, %xmm2
+vrsqrtss (%rax), %xmm1, %xmm2
+
+vshufpd $1, %xmm0, %xmm1, %xmm2
+vshufpd $1, (%rax), %xmm1, %xmm2
+
+vshufpd $1, %ymm0, %ymm1, %ymm2
+vshufpd $1, (%rax), %ymm1, %ymm2
+
+vshufps $1, %xmm0, %xmm1, %xmm2
+vshufps $1, (%rax), %xmm1, %xmm2
+
+vshufps $1, %ymm0, %ymm1, %ymm2
+vshufps $1, (%rax), %ymm1, %ymm2
+
+vsqrtpd %xmm0, %xmm2
+vsqrtpd (%rax), %xmm2
+
+vsqrtpd %ymm0, %ymm2
+vsqrtpd (%rax), %ymm2
+
+vsqrtps %xmm0, %xmm2
+vsqrtps (%rax), %xmm2
+
+vsqrtps %ymm0, %ymm2
+vsqrtps (%rax), %ymm2
+
+vsqrtsd %xmm0, %xmm1, %xmm2
+vsqrtsd (%rax), %xmm1, %xmm2
+
+vsqrtss %xmm0, %xmm1, %xmm2
+vsqrtss (%rax), %xmm1, %xmm2
+
+vstmxcsr (%rax)
+
+vsubpd %xmm0, %xmm1, %xmm2
+vsubpd (%rax), %xmm1, %xmm2
+
+vsubpd %ymm0, %ymm1, %ymm2
+vsubpd (%rax), %ymm1, %ymm2
+
+vsubps %xmm0, %xmm1, %xmm2
+vsubps (%rax), %xmm1, %xmm2
+
+vsubps %ymm0, %ymm1, %ymm2
+vsubps (%rax), %ymm1, %ymm2
+
+vsubsd %xmm0, %xmm1, %xmm2
+vsubsd (%rax), %xmm1, %xmm2
+
+vsubss %xmm0, %xmm1, %xmm2
+vsubss (%rax), %xmm1, %xmm2
+
+vtestpd %xmm0, %xmm1
+vtestpd (%rax), %xmm1
+
+vtestpd %ymm0, %ymm1
+vtestpd (%rax), %ymm1
+
+vtestps %xmm0, %xmm1
+vtestps (%rax), %xmm1
+
+vtestps %ymm0, %ymm1
+vtestps (%rax), %ymm1
+
+vucomisd %xmm0, %xmm1
+vucomisd (%rax), %xmm1
+
+vucomiss %xmm0, %xmm1
+vucomiss (%rax), %xmm1
+
+vunpckhpd %xmm0, %xmm1, %xmm2
+vunpckhpd (%rax), %xmm1, %xmm2
+
+vunpckhpd %ymm0, %ymm1, %ymm2
+vunpckhpd (%rax), %ymm1, %ymm2
+
+vunpckhps %xmm0, %xmm1, %xmm2
+vunpckhps (%rax), %xmm1, %xmm2
+
+vunpckhps %ymm0, %ymm1, %ymm2
+vunpckhps (%rax), %ymm1, %ymm2
+
+vunpcklpd %xmm0, %xmm1, %xmm2
+vunpcklpd (%rax), %xmm1, %xmm2
+
+vunpcklpd %ymm0, %ymm1, %ymm2
+vunpcklpd (%rax), %ymm1, %ymm2
+
+vunpcklps %xmm0, %xmm1, %xmm2
+vunpcklps (%rax), %xmm1, %xmm2
+
+vunpcklps %ymm0, %ymm1, %ymm2
+vunpcklps (%rax), %ymm1, %ymm2
+
+vxorpd %xmm0, %xmm1, %xmm2
+vxorpd (%rax), %xmm1, %xmm2
+
+vxorpd %ymm0, %ymm1, %ymm2
+vxorpd (%rax), %ymm1, %ymm2
+
+vxorps %xmm0, %xmm1, %xmm2
+vxorps (%rax), %xmm1, %xmm2
+
+vxorps %ymm0, %ymm1, %ymm2
+vxorps (%rax), %ymm1, %ymm2
+
+vzeroall
+vzeroupper
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 vaddpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vaddpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaddpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vaddpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vaddps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vaddps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaddps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vaddps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vaddsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vaddsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaddss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vaddss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaddsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vaddsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaddsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vaddsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vaddsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vaddsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaddsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vaddsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vaesdec %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vaesdec (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaesdeclast %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vaesdeclast (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaesenc %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vaesenc (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaesenclast %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vaesenclast (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaesimc %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vaesimc (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 vaeskeygenassist $22, %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vaeskeygenassist $22, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 vandnpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vandnpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vandnpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vandnpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vandnps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vandnps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vandnps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vandnps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vandpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vandpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vandpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vandpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vandps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vandps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vandps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vandps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vblendpd $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vblendpd $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vblendpd $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vblendpd $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vblendps $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vblendps $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vblendps $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vblendps $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vblendvpd %xmm3, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vblendvpd %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vblendvpd %ymm3, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vblendvpd %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vblendvps %xmm3, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vblendvps %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vblendvps %ymm3, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vblendvps %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vbroadcastf128 (%rax), %ymm2
+# CHECK-NEXT: 1 8 0.50 * vbroadcastsd (%rax), %ymm2
+# CHECK-NEXT: 1 8 0.50 * vbroadcastss (%rax), %xmm2
+# CHECK-NEXT: 1 8 0.50 * vbroadcastss (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vcmpeqpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vcmpeqpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vcmpeqpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vcmpeqpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vcmpeqps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vcmpeqps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vcmpeqps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vcmpeqps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vcmpeqsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vcmpeqsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vcmpeqss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vcmpeqss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 1 0.50 vcomisd %xmm0, %xmm1
+# CHECK-NEXT: 2 8 0.50 * vcomisd (%rax), %xmm1
+# CHECK-NEXT: 2 1 0.50 vcomiss %xmm0, %xmm1
+# CHECK-NEXT: 2 8 0.50 * vcomiss (%rax), %xmm1
+# CHECK-NEXT: 1 4 0.50 vcvtdq2pd %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vcvtdq2pd (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 vcvtdq2pd %xmm0, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vcvtdq2pd (%rax), %ymm2
+# CHECK-NEXT: 1 4 0.50 vcvtdq2ps %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vcvtdq2ps (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 vcvtdq2ps %ymm0, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vcvtdq2ps (%rax), %ymm2
+# CHECK-NEXT: 1 4 0.50 vcvtpd2dq %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2dqx (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 vcvtpd2dq %ymm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2dqy (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 vcvtpd2ps %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2psx (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 vcvtpd2ps %ymm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2psy (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 vcvtps2dq %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vcvtps2dq (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 vcvtps2dq %ymm0, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vcvtps2dq (%rax), %ymm2
+# CHECK-NEXT: 1 4 0.50 vcvtps2pd %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vcvtps2pd (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 vcvtps2pd %xmm0, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vcvtps2pd (%rax), %ymm2
+# CHECK-NEXT: 2 2 1.00 vcvtsd2si %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 vcvtsd2si %xmm0, %rcx
+# CHECK-NEXT: 2 9 1.00 * vcvtsd2si (%rax), %ecx
+# CHECK-NEXT: 2 9 1.00 * vcvtsd2si (%rax), %rcx
+# CHECK-NEXT: 1 4 0.50 vcvtsd2ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vcvtsd2ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vcvtsi2sd %ecx, %xmm0, %xmm2
+# CHECK-NEXT: 2 4 1.50 vcvtsi2sd %rcx, %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vcvtsi2sdl (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 11 1.50 * vcvtsi2sdq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 1 4 0.50 vcvtsi2ss %ecx, %xmm0, %xmm2
+# CHECK-NEXT: 2 4 1.50 vcvtsi2ss %rcx, %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vcvtsi2ssl (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 11 1.50 * vcvtsi2ssq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 1 4 0.50 vcvtss2sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vcvtss2sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 2 1.00 vcvtss2si %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 vcvtss2si %xmm0, %rcx
+# CHECK-NEXT: 2 9 1.00 * vcvtss2si (%rax), %ecx
+# CHECK-NEXT: 2 9 1.00 * vcvtss2si (%rax), %rcx
+# CHECK-NEXT: 1 4 0.50 vcvttpd2dq %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2dqx (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 vcvttpd2dq %ymm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2dqy (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 vcvttps2dq %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vcvttps2dq (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 vcvttps2dq %ymm0, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vcvttps2dq (%rax), %ymm2
+# CHECK-NEXT: 2 2 1.00 vcvttsd2si %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 vcvttsd2si %xmm0, %rcx
+# CHECK-NEXT: 2 9 1.00 * vcvttsd2si (%rax), %ecx
+# CHECK-NEXT: 2 9 1.00 * vcvttsd2si (%rax), %rcx
+# CHECK-NEXT: 2 2 1.00 vcvttss2si %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 vcvttss2si %xmm0, %rcx
+# CHECK-NEXT: 2 9 1.00 * vcvttss2si (%rax), %ecx
+# CHECK-NEXT: 2 9 1.00 * vcvttss2si (%rax), %rcx
+# CHECK-NEXT: 1 8 6.00 vdivpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 15 6.00 * vdivpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 8 6.00 vdivpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 15 6.00 * vdivpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 10 4.50 vdivps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 17 4.50 * vdivps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 10 4.50 vdivps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 17 4.50 * vdivps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 8 6.00 vdivsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 15 6.00 * vdivsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 10 4.50 vdivss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 17 4.50 * vdivss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 9 4.00 vdppd $22, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4 16 4.00 * vdppd $22, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 8 14 4.00 vdpps $22, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 8 21 4.00 * vdpps $22, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 8 14 4.00 vdpps $22, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 8 21 4.00 * vdpps $22, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vextractf128 $1, %ymm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * vextractf128 $1, %ymm0, (%rax)
+# CHECK-NEXT: 1 1 2.00 vextractps $1, %xmm0, %ecx
+# CHECK-NEXT: 1 3 2.00 * vextractps $1, %xmm0, (%rax)
+# CHECK-NEXT: 4 7 4.00 vhaddpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 7 14 4.00 * vhaddpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 7 4.00 vhaddpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 7 14 4.00 * vhaddpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 4 7 4.00 vhaddps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 7 14 4.00 * vhaddps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 7 4.00 vhaddps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 7 14 4.00 * vhaddps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 4 7 4.00 vhsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 7 14 4.00 * vhsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 7 4.00 vhsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 7 14 4.00 * vhsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 4 7 4.00 vhsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 7 14 4.00 * vhsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 7 4.00 vhsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 7 14 4.00 * vhsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vinsertf128 $1, %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vinsertf128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vinsertps $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vinsertps $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vlddqu (%rax), %xmm2
+# CHECK-NEXT: 1 8 0.33 * vlddqu (%rax), %ymm2
+# CHECK-NEXT: 1 100 0.25 * * U vldmxcsr (%rax)
+# CHECK-NEXT: 1 1 0.33 * * U vmaskmovdqu %xmm0, %xmm1
+# CHECK-NEXT: 1 8 0.50 * vmaskmovpd (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vmaskmovpd (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 1 1 0.50 * * vmaskmovpd %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 1 1 0.50 * * vmaskmovpd %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmaskmovps (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.50 * vmaskmovps (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 1 1 0.50 * * vmaskmovps %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 1 1 0.50 * * vmaskmovps %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: 1 1 0.50 vmaxpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vmaxpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vmaxpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vmaxpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vmaxps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vmaxps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vmaxps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vmaxps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vmaxsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vmaxsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vmaxss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vmaxss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vminpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vminpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vminpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vminpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vminps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vminps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vminps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vminps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vminsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vminsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vminss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vminss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 0 0.25 vmovapd %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * vmovapd %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.33 * vmovapd (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 vmovapd %ymm0, %ymm2
+# CHECK-NEXT: 1 1 0.33 * vmovapd %ymm0, (%rax)
+# CHECK-NEXT: 1 8 0.33 * vmovapd (%rax), %ymm2
+# CHECK-NEXT: 1 0 0.25 vmovaps %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * vmovaps %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.33 * vmovaps (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 vmovaps %ymm0, %ymm2
+# CHECK-NEXT: 1 1 0.33 * vmovaps %ymm0, (%rax)
+# CHECK-NEXT: 1 8 0.33 * vmovaps (%rax), %ymm2
+# CHECK-NEXT: 2 1 1.00 vmovd %eax, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vmovd (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 vmovd %xmm0, %ecx
+# CHECK-NEXT: 1 1 0.33 * vmovd %xmm0, (%rax)
+# CHECK-NEXT: 1 1 0.50 vmovddup %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vmovddup (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vmovddup %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vmovddup (%rax), %ymm2
+# CHECK-NEXT: 1 0 0.25 vmovdqa %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * vmovdqa %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.33 * vmovdqa (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 vmovdqa %ymm0, %ymm2
+# CHECK-NEXT: 1 1 0.33 * vmovdqa %ymm0, (%rax)
+# CHECK-NEXT: 1 8 0.33 * vmovdqa (%rax), %ymm2
+# CHECK-NEXT: 1 0 0.25 vmovdqu %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * vmovdqu %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.33 * vmovdqu (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 vmovdqu %ymm0, %ymm2
+# CHECK-NEXT: 1 1 0.33 * vmovdqu %ymm0, (%rax)
+# CHECK-NEXT: 1 8 0.33 * vmovdqu (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vmovhlps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vmovlhps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 * vmovhpd %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovhpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 * vmovhps %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovhps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 * vmovlpd %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovlpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 * vmovlps %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * vmovlps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vmovmskpd %xmm0, %ecx
+# CHECK-NEXT: 1 1 0.50 vmovmskpd %ymm0, %ecx
+# CHECK-NEXT: 1 1 0.50 vmovmskps %xmm0, %ecx
+# CHECK-NEXT: 1 1 0.50 vmovmskps %ymm0, %ecx
+# CHECK-NEXT: 1 2 1.00 * vmovntdq %xmm0, (%rax)
+# CHECK-NEXT: 1 2 1.00 * vmovntdq %ymm0, (%rax)
+# CHECK-NEXT: 1 8 0.33 * vmovntdqa (%rax), %xmm2
+# CHECK-NEXT: 1 8 0.33 * vmovntdqa (%rax), %ymm2
+# CHECK-NEXT: 1 2 1.00 * vmovntpd %xmm0, (%rax)
+# CHECK-NEXT: 1 2 1.00 * vmovntpd %ymm0, (%rax)
+# CHECK-NEXT: 1 2 1.00 * vmovntps %xmm0, (%rax)
+# CHECK-NEXT: 1 2 1.00 * vmovntps %ymm0, (%rax)
+# CHECK-NEXT: 1 1 0.25 vmovq %xmm0, %xmm2
+# CHECK-NEXT: 2 1 1.00 vmovq %rax, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vmovq (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 vmovq %xmm0, %rcx
+# CHECK-NEXT: 1 1 0.33 * vmovq %xmm0, (%rax)
+# CHECK-NEXT: 1 1 0.50 vmovsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 * vmovsd %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.33 * vmovsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vmovshdup %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vmovshdup (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vmovshdup %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vmovshdup (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vmovsldup %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vmovsldup (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vmovsldup %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vmovsldup (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vmovss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.33 * vmovss %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.33 * vmovss (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 vmovupd %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * vmovupd %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.33 * vmovupd (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 vmovupd %ymm0, %ymm2
+# CHECK-NEXT: 1 1 0.33 * vmovupd %ymm0, (%rax)
+# CHECK-NEXT: 1 8 0.33 * vmovupd (%rax), %ymm2
+# CHECK-NEXT: 1 0 0.25 vmovups %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * vmovups %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.33 * vmovups (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 vmovups %ymm0, %ymm2
+# CHECK-NEXT: 1 1 0.33 * vmovups %ymm0, (%rax)
+# CHECK-NEXT: 1 8 0.33 * vmovups (%rax), %ymm2
+# CHECK-NEXT: 1 4 2.00 vmpsadbw $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 2.00 * vmpsadbw $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vmulpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vmulpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vmulpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vmulpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vmulps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vmulps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vmulps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vmulps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vmulsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vmulsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vmulss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vmulss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vorpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vorpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vorpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vorpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vorps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vorps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vorps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vorps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpabsb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpabsb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 vpabsd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpabsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 vpabsw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpabsw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpackssdw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpackssdw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpacksswb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpacksswb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpackusdw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpackusdw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpackuswb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpackuswb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpaddb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpaddb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpaddd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpaddd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpaddq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpaddq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpaddsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpaddsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpaddsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpaddsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpaddusb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpaddusb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpaddusw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpaddusw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpaddw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpaddw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpalignr $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpalignr $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpand %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpand (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpandn %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpandn (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpavgb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpavgb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpavgw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpavgw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpblendvb %xmm3, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpblendvb %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpblendw $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpblendw $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vpclmulqdq $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vpclmulqdq $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpcmpeqb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpcmpeqd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpcmpeqq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpcmpeqw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 8 8 3.25 vpcmpestri $1, %xmm0, %xmm2
+# CHECK-NEXT: 8 15 3.25 * vpcmpestri $1, (%rax), %xmm2
+# CHECK-NEXT: 8 7 6.25 vpcmpestrm $1, %xmm0, %xmm2
+# CHECK-NEXT: 8 14 6.25 * vpcmpestrm $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 vpcmpgtb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpcmpgtb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpcmpgtd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpcmpgtd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpcmpgtq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpcmpgtq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpcmpgtw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpcmpgtw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 2 2.00 vpcmpistri $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 9 2.00 * vpcmpistri $1, (%rax), %xmm2
+# CHECK-NEXT: 3 7 6.25 vpcmpistrm $1, %xmm0, %xmm2
+# CHECK-NEXT: 3 14 6.25 * vpcmpistrm $1, (%rax), %xmm2
+# CHECK-NEXT: 8 8 8.00 vperm2f128 $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 8 15 8.00 * vperm2f128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpermilpd $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpermilpd $1, (%rax), %xmm2
+# CHECK-NEXT: 1 3 2.00 vpermilpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vpermilpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpermilpd $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpermilpd $1, (%rax), %ymm2
+# CHECK-NEXT: 1 3 2.00 vpermilpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 2.00 * vpermilpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpermilps $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpermilps $1, (%rax), %xmm2
+# CHECK-NEXT: 1 3 2.00 vpermilps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 2.00 * vpermilps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpermilps $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpermilps $1, (%rax), %ymm2
+# CHECK-NEXT: 1 3 2.00 vpermilps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 2.00 * vpermilps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 2.00 vpextrb $1, %xmm0, %ecx
+# CHECK-NEXT: 1 3 2.00 * vpextrb $1, %xmm0, (%rax)
+# CHECK-NEXT: 1 1 2.00 vpextrd $1, %xmm0, %ecx
+# CHECK-NEXT: 1 3 2.00 * vpextrd $1, %xmm0, (%rax)
+# CHECK-NEXT: 1 1 2.00 vpextrq $1, %xmm0, %rcx
+# CHECK-NEXT: 1 3 2.00 * vpextrq $1, %xmm0, (%rax)
+# CHECK-NEXT: 1 1 2.00 vpextrw $1, %xmm0, %ecx
+# CHECK-NEXT: 1 3 2.00 * vpextrw $1, %xmm0, (%rax)
+# CHECK-NEXT: 4 3 4.00 vphaddd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 7 10 4.00 * vphaddd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 3 4.00 vphaddsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 7 10 4.00 * vphaddsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 3 4.00 vphaddw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 7 10 4.00 * vphaddw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.00 vphminposuw %xmm0, %xmm2
+# CHECK-NEXT: 1 10 1.00 * vphminposuw (%rax), %xmm2
+# CHECK-NEXT: 4 3 4.00 vphsubd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 7 10 4.00 * vphsubd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 3 4.00 vphsubsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 7 10 4.00 * vphsubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 3 4.00 vphsubw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 7 10 4.00 * vphsubw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 2 0.50 vpinsrb $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT: 1 9 0.50 * vpinsrb $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 2 0.50 vpinsrd $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT: 1 9 0.50 * vpinsrd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 2 0.50 vpinsrq $1, %rax, %xmm1, %xmm2
+# CHECK-NEXT: 1 9 0.50 * vpinsrq $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 2 0.50 vpinsrw $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT: 1 9 0.50 * vpinsrw $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vpmaddubsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vpmaddubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vpmaddwd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vpmaddwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpmaxsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpmaxsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpmaxsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpmaxsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpmaxsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpmaxsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpmaxub %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpmaxub (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpmaxud %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpmaxud (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpmaxuw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpmaxuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpminsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpminsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpminsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpminsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpminsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpminsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpminub %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpminub (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpminud %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpminud (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpminuw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpminuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovmskb %xmm0, %ecx
+# CHECK-NEXT: 1 1 0.50 vpmovsxbd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovsxbd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovsxbq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovsxbq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovsxbw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovsxbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovsxdq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovsxdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovsxwd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovsxwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovsxwq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovsxwq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovzxbd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovzxbd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovzxbq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovzxbq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovzxbw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovzxbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovzxdq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovzxdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovzxwd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovzxwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpmovzxwq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpmovzxwq (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 vpmuldq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vpmuldq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vpmulhrsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vpmulhrsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vpmulhuw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vpmulhuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vpmulhw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vpmulhw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vpmulld %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vpmulld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vpmullw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vpmullw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vpmuludq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vpmuludq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpor %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpor (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 1.00 vpsadbw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 1.00 * vpsadbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpshufb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpshufb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpshufd $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpshufd $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpshufhw $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpshufhw $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 vpshuflw $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpshuflw $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 vpsignb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpsignb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpsignd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpsignd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpsignw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpsignw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpslld $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpslld %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpslld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpslldq $1, %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsllq $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsllq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsllq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsllw $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsllw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsllw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrad $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrad %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsrad (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsraw $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsraw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsraw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrld $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrld %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsrld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrldq $1, %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrlq $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrlq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsrlq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrlw $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpsrlw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpsrlw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpsubb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpsubb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpsubd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpsubd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpsubq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpsubq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpsubsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpsubsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpsubsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpsubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpsubusb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpsubusb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpsubusw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpsubusw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpsubw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpsubw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vptest %xmm0, %xmm1
+# CHECK-NEXT: 1 8 0.50 * vptest (%rax), %xmm1
+# CHECK-NEXT: 1 1 0.50 vptest %ymm0, %ymm1
+# CHECK-NEXT: 1 8 0.50 * vptest (%rax), %ymm1
+# CHECK-NEXT: 1 1 0.50 vpunpckhbw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpunpckhbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhdq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpunpckhdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhqdq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpunpckhqdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhwd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpunpckhwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpcklbw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpunpcklbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpckldq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpunpckldq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpcklqdq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpunpcklqdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vpunpcklwd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vpunpcklwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpxor %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpxor (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 1.00 vrcpps %xmm0, %xmm2
+# CHECK-NEXT: 1 12 1.00 * vrcpps (%rax), %xmm2
+# CHECK-NEXT: 1 5 1.00 vrcpps %ymm0, %ymm2
+# CHECK-NEXT: 1 12 1.00 * vrcpps (%rax), %ymm2
+# CHECK-NEXT: 1 5 1.00 vrcpss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 1.00 * vrcpss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vroundpd $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vroundpd $1, (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 vroundpd $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vroundpd $1, (%rax), %ymm2
+# CHECK-NEXT: 1 4 0.50 vroundps $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vroundps $1, (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 vroundps $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vroundps $1, (%rax), %ymm2
+# CHECK-NEXT: 1 4 0.50 vroundsd $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vroundsd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vroundss $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vroundss $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 5 1.00 vrsqrtps %xmm0, %xmm2
+# CHECK-NEXT: 1 12 1.00 * vrsqrtps (%rax), %xmm2
+# CHECK-NEXT: 1 5 1.00 vrsqrtps %ymm0, %ymm2
+# CHECK-NEXT: 1 12 1.00 * vrsqrtps (%rax), %ymm2
+# CHECK-NEXT: 1 5 1.00 vrsqrtss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 12 1.00 * vrsqrtss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vshufpd $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vshufpd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vshufpd $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vshufpd $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vshufps $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vshufps $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vshufps $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vshufps $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 8 9.50 vsqrtpd %xmm0, %xmm2
+# CHECK-NEXT: 1 15 9.50 * vsqrtpd (%rax), %xmm2
+# CHECK-NEXT: 1 8 9.50 vsqrtpd %ymm0, %ymm2
+# CHECK-NEXT: 1 15 9.50 * vsqrtpd (%rax), %ymm2
+# CHECK-NEXT: 1 8 6.50 vsqrtps %xmm0, %xmm2
+# CHECK-NEXT: 1 15 6.50 * vsqrtps (%rax), %xmm2
+# CHECK-NEXT: 1 8 6.50 vsqrtps %ymm0, %ymm2
+# CHECK-NEXT: 1 15 6.50 * vsqrtps (%rax), %ymm2
+# CHECK-NEXT: 1 8 9.50 vsqrtsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 15 9.50 * vsqrtsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 8 6.50 vsqrtss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 15 6.50 * vsqrtss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 100 0.25 * U vstmxcsr (%rax)
+# CHECK-NEXT: 1 3 0.50 vsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vsubsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vsubsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vsubss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vsubss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vtestpd %xmm0, %xmm1
+# CHECK-NEXT: 1 8 0.50 * vtestpd (%rax), %xmm1
+# CHECK-NEXT: 1 1 0.50 vtestpd %ymm0, %ymm1
+# CHECK-NEXT: 1 8 0.50 * vtestpd (%rax), %ymm1
+# CHECK-NEXT: 1 1 0.50 vtestps %xmm0, %xmm1
+# CHECK-NEXT: 1 8 0.50 * vtestps (%rax), %xmm1
+# CHECK-NEXT: 1 1 0.50 vtestps %ymm0, %ymm1
+# CHECK-NEXT: 1 8 0.50 * vtestps (%rax), %ymm1
+# CHECK-NEXT: 2 1 0.50 vucomisd %xmm0, %xmm1
+# CHECK-NEXT: 2 8 0.50 * vucomisd (%rax), %xmm1
+# CHECK-NEXT: 2 1 0.50 vucomiss %xmm0, %xmm1
+# CHECK-NEXT: 2 8 0.50 * vucomiss (%rax), %xmm1
+# CHECK-NEXT: 1 1 0.50 vunpckhpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vunpckhpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vunpckhpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vunpckhpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vunpckhps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vunpckhps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vunpckhps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vunpckhps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vunpcklpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vunpcklpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vunpcklpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vunpcklpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vunpcklps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.50 * vunpcklps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.50 vunpcklps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vunpcklps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vxorpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vxorpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vxorpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vxorpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vxorps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vxorps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vxorps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vxorps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 100 0.25 U vzeroall
+# CHECK-NEXT: 1 100 0.25 U vzeroupper
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 119.00 119.00 119.00 - - - - - 202.25 547.25 198.25 537.25 89.25 89.25 89.25 89.25 106.67 106.67 106.67 9.25 9.25 9.25 9.25
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaddpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaddpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaddps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaddps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaddsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaddss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaddsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaddsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaddsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaddsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaesdec %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaesdec (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaesdeclast %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaesdeclast (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaesenc %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaesenc (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaesenclast %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaesenclast (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaesimc %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaesimc (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaeskeygenassist $22, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaeskeygenassist $22, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandnpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandnpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandnps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandnps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vblendpd $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vblendpd $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vblendpd $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vblendpd $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vblendps $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vblendps $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vblendps $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vblendps $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vblendvpd %xmm3, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vblendvpd %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vblendvpd %ymm3, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vblendvpd %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vblendvps %xmm3, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vblendvps %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vblendvps %ymm3, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vblendvps %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastf128 (%rax), %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastsd (%rax), %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastss (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastss (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vcmpeqpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vcmpeqpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vcmpeqps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vcmpeqps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vcmpeqsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vcmpeqss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vcomisd %xmm0, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcomisd (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vcomiss %xmm0, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcomiss (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtdq2pd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2pd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtdq2pd %xmm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2pd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtdq2ps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2ps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtdq2ps %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2ps (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtpd2dq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2dqx (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtpd2dq %ymm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2dqy (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtpd2ps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2psx (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtpd2ps %ymm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2psy (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtps2dq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2dq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtps2dq %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2dq (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtps2pd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2pd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtps2pd %xmm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2pd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtsd2si %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtsd2si %xmm0, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtsd2si (%rax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtsd2si (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtsd2ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtsd2ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtsi2sd %ecx, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.50 - 1.50 - - - - - - - - - - - vcvtsi2sd %rcx, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtsi2sdl (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.50 - 1.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtsi2sdq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtsi2ss %ecx, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.50 - 1.50 - - - - - - - - - - - vcvtsi2ss %rcx, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtsi2ssl (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.50 - 1.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtsi2ssq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtss2sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtss2sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtss2si %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtss2si %xmm0, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtss2si (%rax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtss2si (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvttpd2dq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2dqx (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvttpd2dq %ymm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2dqy (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvttps2dq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2dq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvttps2dq %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2dq (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttsd2si %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttsd2si %xmm0, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttsd2si (%rax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttsd2si (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttss2si %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttss2si %xmm0, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttss2si (%rax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttss2si (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - - 6.00 - 6.00 - - - - - - - - - - - vdivpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.00 - 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 6.00 - 6.00 - - - - - - - - - - - vdivpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.00 - 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 4.50 - 4.50 - - - - - - - - - - - vdivps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.50 - 4.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 4.50 - 4.50 - - - - - - - - - - - vdivps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.50 - 4.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 6.00 - 6.00 - - - - - - - - - - - vdivsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.00 - 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 4.50 - 4.50 - - - - - - - - - - - vdivss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.50 - 4.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - vdppd $22, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdppd $22, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - vdpps $22, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdpps $22, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - vdpps $22, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdpps $22, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vextractf128 $1, %ymm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vextractf128 $1, %ymm0, (%rax)
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vextractps $1, %xmm0, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vextractps $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - vhaddpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vhaddpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - vhaddpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vhaddpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - vhaddps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vhaddps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - vhaddps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vhaddps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - vhsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vhsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - vhsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vhsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - vhsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vhsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - vhsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vhsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vinsertf128 $1, %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vinsertf128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vinsertps $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vinsertps $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vlddqu (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vlddqu (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vldmxcsr (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmaskmovdqu %xmm0, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaskmovpd (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaskmovpd (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmaskmovpd %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmaskmovpd %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaskmovps (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaskmovps (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmaskmovps %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmaskmovps %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmaxpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmaxpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmaxps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmaxps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmaxsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmaxss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vminpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vminpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vminps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vminps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vminsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vminss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovapd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovapd %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovapd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovapd %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovapd %ymm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovapd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovaps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovaps %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovaps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovaps %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovaps %ymm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovaps (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - vmovd %eax, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vmovd %xmm0, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vmovddup %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovddup (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vmovddup %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovddup (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqa %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqa %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqa (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqa %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqa %ymm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqa (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqu %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqu %ymm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vmovhlps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vmovlhps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovhpd %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovhpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovhps %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovhps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovlpd %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovlpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovlps %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovlps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vmovmskpd %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vmovmskpd %ymm0, %ecx
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vmovmskps %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vmovmskps %ymm0, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovntdq %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovntdq %ymm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovntdqa (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovntdqa (%rax), %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovntpd %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovntpd %ymm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovntps %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovntps %ymm0, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vmovq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - vmovq %rax, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vmovq %xmm0, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovq %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vmovsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovsd %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vmovshdup %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovshdup (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vmovshdup %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovshdup (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vmovsldup %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovsldup (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vmovsldup %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovsldup (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vmovss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovss %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovupd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovupd %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovupd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovupd %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovupd %ymm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovupd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovups %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovups %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovups (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovups %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovups %ymm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovups (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 2.00 2.00 2.00 2.00 - - - - - - - - - - - vmpsadbw $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 2.00 2.00 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmpsadbw $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmulpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmulpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmulps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmulps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmulsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmulss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vorpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vorpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vorps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vorps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpabsb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpabsd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpabsw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpackssdw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackssdw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpacksswb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpacksswb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpackusdw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackusdw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpackuswb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackuswb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddusb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddusb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddusw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddusw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpalignr $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpalignr $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpand %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpand (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpandn %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpandn (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpavgb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpavgb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpavgw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpavgw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpblendvb %xmm3, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpblendvb %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpblendw $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpblendw $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpclmulqdq $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpclmulqdq $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpeqb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpeqd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpeqq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpeqw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 3.25 3.25 3.25 3.25 - - - - - - - - - - - vpcmpestri $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.25 3.25 3.25 3.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpestri $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 6.25 6.25 6.25 6.25 - - - - - - - - - - - vpcmpestrm $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 6.25 6.25 6.25 6.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpestrm $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpgtb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpgtd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpgtq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpgtw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 2.00 2.00 2.00 - - - - - - - - - - - vpcmpistri $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 2.00 2.00 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpistri $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 6.25 6.25 6.25 6.25 - - - - - - - - - - - vpcmpistrm $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 6.25 6.25 6.25 6.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpistrm $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 8.00 8.00 8.00 8.00 - - - - - - - - - - - vperm2f128 $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 8.00 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vperm2f128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpermilpd $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermilpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpermilpd $1, %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermilpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpermilps $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermilps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpermilps $1, %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermilps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpextrb $1, %xmm0, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vpextrb $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpextrd $1, %xmm0, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vpextrd $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpextrq $1, %xmm0, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vpextrq $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpextrw $1, %xmm0, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vpextrw $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - vphaddd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vphaddd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - vphaddsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vphaddsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - vphaddw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vphaddw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vphminposuw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vphminposuw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - vphsubd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vphsubd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - vphsubsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vphsubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - vphsubw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vphsubw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpinsrb $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpinsrb $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpinsrd $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpinsrd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpinsrq $1, %rax, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpinsrq $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpinsrw $1, %eax, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpinsrw $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmaddubsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaddubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmaddwd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaddwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxub %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxub (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxud %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxud (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxuw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminub %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminub (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminud %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminud (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminuw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovmskb %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovsxbd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovsxbq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovsxbw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovsxdq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxdq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovsxwd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxwd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovsxwq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxwq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovzxbd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovzxbq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovzxbw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovzxdq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxdq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovzxwd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxwd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovzxwq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxwq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmuldq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmuldq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmulhrsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhrsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmulhuw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmulhw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmulld %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmullw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmullw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmuludq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmuludq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpor %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpor (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsadbw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsadbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpshufb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpshufd $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufd $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpshufhw $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufhw $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpshuflw $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshuflw $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsignb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsignb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsignd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsignd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsignw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsignw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpslld $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpslld %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpslld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpslldq $1, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsllq $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsllq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsllw $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsllw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsrad $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsrad %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrad (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsraw $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsraw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsraw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsrld $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsrld %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpsrldq $1, %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsrlq $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsrlq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsrlw $1, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsrlw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubsb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubsw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubusb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubusb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubusw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubusw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vptest %xmm0, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptest (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vptest %ymm0, %ymm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptest (%rax), %ymm1
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckhbw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckhdq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckhqdq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhqdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckhwd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpcklbw %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpcklbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckldq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckldq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpcklqdq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpcklqdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpcklwd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpcklwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpxor %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpxor (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vrcpps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrcpps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vrcpps %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrcpps (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vrcpss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrcpss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vroundpd $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vroundpd $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vroundpd $1, %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vroundpd $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vroundps $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vroundps $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vroundps $1, %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vroundps $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vroundsd $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vroundsd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vroundss $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vroundss $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vrsqrtps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrsqrtps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vrsqrtps %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrsqrtps (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vrsqrtss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrsqrtss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vshufpd $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshufpd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vshufpd $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshufpd $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vshufps $1, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshufps $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vshufps $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshufps $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 9.50 - 9.50 - - - - - - - - - - - vsqrtpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 9.50 - 9.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 9.50 - 9.50 - - - - - - - - - - - vsqrtpd %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 9.50 - 9.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtpd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 6.50 - 6.50 - - - - - - - - - - - vsqrtps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.50 - 6.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 6.50 - 6.50 - - - - - - - - - - - vsqrtps %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.50 - 6.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtps (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 9.50 - 9.50 - - - - - - - - - - - vsqrtsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 9.50 - 9.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 6.50 - 6.50 - - - - - - - - - - - vsqrtss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.50 - 6.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vstmxcsr (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vsubsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vsubss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vtestpd %xmm0, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vtestpd (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vtestpd %ymm0, %ymm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vtestpd (%rax), %ymm1
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vtestps %xmm0, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vtestps (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vtestps %ymm0, %ymm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vtestps (%rax), %ymm1
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vucomisd %xmm0, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vucomisd (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vucomiss %xmm0, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vucomiss (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vunpckhpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vunpckhpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vunpckhps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vunpckhps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vunpcklpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vunpcklpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vunpcklps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vunpcklps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vxorpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vxorpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vxorps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vxorps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vzeroall
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vzeroupper
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx2.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx2.s
new file mode 100644
index 0000000000000..7a7be4de64f7f
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx2.s
@@ -0,0 +1,1096 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+vbroadcasti128 (%rax), %ymm0
+
+vbroadcastsd %xmm0, %ymm0
+vbroadcastss %xmm0, %ymm0
+
+vextracti128 $1, %ymm0, %xmm2
+vextracti128 $1, %ymm0, (%rax)
+
+vgatherdpd %xmm0, (%rax,%xmm1,2), %xmm2
+vgatherdpd %ymm0, (%rax,%xmm1,2), %ymm2
+
+vgatherdps %xmm0, (%rax,%xmm1,2), %xmm2
+vgatherdps %ymm0, (%rax,%ymm1,2), %ymm2
+
+vgatherqpd %xmm0, (%rax,%xmm1,2), %xmm2
+vgatherqpd %ymm0, (%rax,%ymm1,2), %ymm2
+
+vgatherqps %xmm0, (%rax,%xmm1,2), %xmm2
+vgatherqps %xmm0, (%rax,%ymm1,2), %xmm2
+
+vinserti128 $1, %xmm0, %ymm1, %ymm2
+vinserti128 $1, (%rax), %ymm1, %ymm2
+
+vmovntdqa (%rax), %ymm0
+
+vmpsadbw $1, %ymm0, %ymm1, %ymm2
+vmpsadbw $1, (%rax), %ymm1, %ymm2
+
+vpabsb %ymm0, %ymm2
+vpabsb (%rax), %ymm2
+
+vpabsd %ymm0, %ymm2
+vpabsd (%rax), %ymm2
+
+vpabsw %ymm0, %ymm2
+vpabsw (%rax), %ymm2
+
+vpackssdw %ymm0, %ymm1, %ymm2
+vpackssdw (%rax), %ymm1, %ymm2
+
+vpacksswb %ymm0, %ymm1, %ymm2
+vpacksswb (%rax), %ymm1, %ymm2
+
+vpackusdw %ymm0, %ymm1, %ymm2
+vpackusdw (%rax), %ymm1, %ymm2
+
+vpackuswb %ymm0, %ymm1, %ymm2
+vpackuswb (%rax), %ymm1, %ymm2
+
+vpaddb %ymm0, %ymm1, %ymm2
+vpaddb (%rax), %ymm1, %ymm2
+
+vpaddd %ymm0, %ymm1, %ymm2
+vpaddd (%rax), %ymm1, %ymm2
+
+vpaddq %ymm0, %ymm1, %ymm2
+vpaddq (%rax), %ymm1, %ymm2
+
+vpaddsb %ymm0, %ymm1, %ymm2
+vpaddsb (%rax), %ymm1, %ymm2
+
+vpaddsw %ymm0, %ymm1, %ymm2
+vpaddsw (%rax), %ymm1, %ymm2
+
+vpaddusb %ymm0, %ymm1, %ymm2
+vpaddusb (%rax), %ymm1, %ymm2
+
+vpaddusw %ymm0, %ymm1, %ymm2
+vpaddusw (%rax), %ymm1, %ymm2
+
+vpaddw %ymm0, %ymm1, %ymm2
+vpaddw (%rax), %ymm1, %ymm2
+
+vpalignr $1, %ymm0, %ymm1, %ymm2
+vpalignr $1, (%rax), %ymm1, %ymm2
+
+vpand %ymm0, %ymm1, %ymm2
+vpand (%rax), %ymm1, %ymm2
+
+vpandn %ymm0, %ymm1, %ymm2
+vpandn (%rax), %ymm1, %ymm2
+
+vpavgb %ymm0, %ymm1, %ymm2
+vpavgb (%rax), %ymm1, %ymm2
+
+vpavgw %ymm0, %ymm1, %ymm2
+vpavgw (%rax), %ymm1, %ymm2
+
+vpblendd $11, %xmm0, %xmm1, %xmm2
+vpblendd $11, (%rax), %xmm1, %xmm2
+
+vpblendd $11, %ymm0, %ymm1, %ymm2
+vpblendd $11, (%rax), %ymm1, %ymm2
+
+vpblendvb %ymm3, %ymm0, %ymm1, %ymm2
+vpblendvb %ymm3, (%rax), %ymm1, %ymm2
+
+vpblendw $11, %ymm0, %ymm1, %ymm2
+vpblendw $11, (%rax), %ymm1, %ymm2
+
+vpbroadcastb %xmm0, %xmm0
+vpbroadcastb (%rax), %xmm0
+
+vpbroadcastb %xmm0, %ymm0
+vpbroadcastb (%rax), %ymm0
+
+vpbroadcastd %xmm0, %xmm0
+vpbroadcastd (%rax), %xmm0
+
+vpbroadcastd %xmm0, %ymm0
+vpbroadcastd (%rax), %ymm0
+
+vpbroadcastq %xmm0, %xmm0
+vpbroadcastq (%rax), %xmm0
+
+vpbroadcastq %xmm0, %ymm0
+vpbroadcastq (%rax), %ymm0
+
+vpbroadcastw %xmm0, %xmm0
+vpbroadcastw (%rax), %xmm0
+
+vpbroadcastw %xmm0, %ymm0
+vpbroadcastw (%rax), %ymm0
+
+vpcmpeqb %ymm0, %ymm1, %ymm2
+vpcmpeqb (%rax), %ymm1, %ymm2
+
+vpcmpeqd %ymm0, %ymm1, %ymm2
+vpcmpeqd (%rax), %ymm1, %ymm2
+
+vpcmpeqq %ymm0, %ymm1, %ymm2
+vpcmpeqq (%rax), %ymm1, %ymm2
+
+vpcmpeqw %ymm0, %ymm1, %ymm2
+vpcmpeqw (%rax), %ymm1, %ymm2
+
+vpcmpgtb %ymm0, %ymm1, %ymm2
+vpcmpgtb (%rax), %ymm1, %ymm2
+
+vpcmpgtd %ymm0, %ymm1, %ymm2
+vpcmpgtd (%rax), %ymm1, %ymm2
+
+vpcmpgtq %ymm0, %ymm1, %ymm2
+vpcmpgtq (%rax), %ymm1, %ymm2
+
+vpcmpgtw %ymm0, %ymm1, %ymm2
+vpcmpgtw (%rax), %ymm1, %ymm2
+
+vperm2i128 $1, %ymm0, %ymm1, %ymm2
+vperm2i128 $1, (%rax), %ymm1, %ymm2
+
+vpermd %ymm0, %ymm1, %ymm2
+vpermd (%rax), %ymm1, %ymm2
+
+vpermpd $1, %ymm0, %ymm2
+vpermpd $1, (%rax), %ymm2
+
+vpermps %ymm0, %ymm1, %ymm2
+vpermps (%rax), %ymm1, %ymm2
+
+vpermq $1, %ymm0, %ymm2
+vpermq $1, (%rax), %ymm2
+
+vpgatherdd %xmm0, (%rax,%xmm1,2), %xmm2
+vpgatherdd %ymm0, (%rax,%ymm1,2), %ymm2
+
+vpgatherdq %xmm0, (%rax,%xmm1,2), %xmm2
+vpgatherdq %ymm0, (%rax,%xmm1,2), %ymm2
+
+vpgatherqd %xmm0, (%rax,%xmm1,2), %xmm2
+vpgatherqd %xmm0, (%rax,%ymm1,2), %xmm2
+
+vpgatherqq %xmm0, (%rax,%xmm1,2), %xmm2
+vpgatherqq %ymm0, (%rax,%ymm1,2), %ymm2
+
+vphaddd %ymm0, %ymm1, %ymm2
+vphaddd (%rax), %ymm1, %ymm2
+
+vphaddsw %ymm0, %ymm1, %ymm2
+vphaddsw (%rax), %ymm1, %ymm2
+
+vphaddw %ymm0, %ymm1, %ymm2
+vphaddw (%rax), %ymm1, %ymm2
+
+vphsubd %ymm0, %ymm1, %ymm2
+vphsubd (%rax), %ymm1, %ymm2
+
+vphsubsw %ymm0, %ymm1, %ymm2
+vphsubsw (%rax), %ymm1, %ymm2
+
+vphsubw %ymm0, %ymm1, %ymm2
+vphsubw (%rax), %ymm1, %ymm2
+
+vpmaddubsw %ymm0, %ymm1, %ymm2
+vpmaddubsw (%rax), %ymm1, %ymm2
+
+vpmaddwd %ymm0, %ymm1, %ymm2
+vpmaddwd (%rax), %ymm1, %ymm2
+
+vpmaskmovd (%rax), %xmm0, %xmm2
+vpmaskmovd (%rax), %ymm0, %ymm2
+
+vpmaskmovd %xmm0, %xmm1, (%rax)
+vpmaskmovd %ymm0, %ymm1, (%rax)
+
+vpmaskmovq (%rax), %xmm0, %xmm2
+vpmaskmovq (%rax), %ymm0, %ymm2
+
+vpmaskmovq %xmm0, %xmm1, (%rax)
+vpmaskmovq %ymm0, %ymm1, (%rax)
+
+vpmaxsb %ymm0, %ymm1, %ymm2
+vpmaxsb (%rax), %ymm1, %ymm2
+
+vpmaxsd %ymm0, %ymm1, %ymm2
+vpmaxsd (%rax), %ymm1, %ymm2
+
+vpmaxsw %ymm0, %ymm1, %ymm2
+vpmaxsw (%rax), %ymm1, %ymm2
+
+vpmaxub %ymm0, %ymm1, %ymm2
+vpmaxub (%rax), %ymm1, %ymm2
+
+vpmaxud %ymm0, %ymm1, %ymm2
+vpmaxud (%rax), %ymm1, %ymm2
+
+vpmaxuw %ymm0, %ymm1, %ymm2
+vpmaxuw (%rax), %ymm1, %ymm2
+
+vpminsb %ymm0, %ymm1, %ymm2
+vpminsb (%rax), %ymm1, %ymm2
+
+vpminsd %ymm0, %ymm1, %ymm2
+vpminsd (%rax), %ymm1, %ymm2
+
+vpminsw %ymm0, %ymm1, %ymm2
+vpminsw (%rax), %ymm1, %ymm2
+
+vpminub %ymm0, %ymm1, %ymm2
+vpminub (%rax), %ymm1, %ymm2
+
+vpminud %ymm0, %ymm1, %ymm2
+vpminud (%rax), %ymm1, %ymm2
+
+vpminuw %ymm0, %ymm1, %ymm2
+vpminuw (%rax), %ymm1, %ymm2
+
+vpmovmskb %ymm0, %rcx
+
+vpmovsxbd %xmm0, %ymm2
+vpmovsxbd (%rax), %ymm2
+
+vpmovsxbq %xmm0, %ymm2
+vpmovsxbq (%rax), %ymm2
+
+vpmovsxbw %xmm0, %ymm2
+vpmovsxbw (%rax), %ymm2
+
+vpmovsxdq %xmm0, %ymm2
+vpmovsxdq (%rax), %ymm2
+
+vpmovsxwd %xmm0, %ymm2
+vpmovsxwd (%rax), %ymm2
+
+vpmovsxwq %xmm0, %ymm2
+vpmovsxwq (%rax), %ymm2
+
+vpmovzxbd %xmm0, %ymm2
+vpmovzxbd (%rax), %ymm2
+
+vpmovzxbq %xmm0, %ymm2
+vpmovzxbq (%rax), %ymm2
+
+vpmovzxbw %xmm0, %ymm2
+vpmovzxbw (%rax), %ymm2
+
+vpmovzxdq %xmm0, %ymm2
+vpmovzxdq (%rax), %ymm2
+
+vpmovzxwd %xmm0, %ymm2
+vpmovzxwd (%rax), %ymm2
+
+vpmovzxwq %xmm0, %ymm2
+vpmovzxwq (%rax), %ymm2
+
+vpmuldq %ymm0, %ymm1, %ymm2
+vpmuldq (%rax), %ymm1, %ymm2
+
+vpmulhrsw %ymm0, %ymm1, %ymm2
+vpmulhrsw (%rax), %ymm1, %ymm2
+
+vpmulhuw %ymm0, %ymm1, %ymm2
+vpmulhuw (%rax), %ymm1, %ymm2
+
+vpmulhw %ymm0, %ymm1, %ymm2
+vpmulhw (%rax), %ymm1, %ymm2
+
+vpmulld %ymm0, %ymm1, %ymm2
+vpmulld (%rax), %ymm1, %ymm2
+
+vpmullw %ymm0, %ymm1, %ymm2
+vpmullw (%rax), %ymm1, %ymm2
+
+vpmuludq %ymm0, %ymm1, %ymm2
+vpmuludq (%rax), %ymm1, %ymm2
+
+vpor %ymm0, %ymm1, %ymm2
+vpor (%rax), %ymm1, %ymm2
+
+vpsadbw %ymm0, %ymm1, %ymm2
+vpsadbw (%rax), %ymm1, %ymm2
+
+vpshufb %ymm0, %ymm1, %ymm2
+vpshufb (%rax), %ymm1, %ymm2
+
+vpshufd $1, %ymm0, %ymm2
+vpshufd $1, (%rax), %ymm2
+
+vpshufhw $1, %ymm0, %ymm2
+vpshufhw $1, (%rax), %ymm2
+
+vpshuflw $1, %ymm0, %ymm2
+vpshuflw $1, (%rax), %ymm2
+
+vpsignb %ymm0, %ymm1, %ymm2
+vpsignb (%rax), %ymm1, %ymm2
+
+vpsignd %ymm0, %ymm1, %ymm2
+vpsignd (%rax), %ymm1, %ymm2
+
+vpsignw %ymm0, %ymm1, %ymm2
+vpsignw (%rax), %ymm1, %ymm2
+
+vpslld $1, %ymm0, %ymm2
+vpslld %xmm0, %ymm1, %ymm2
+vpslld (%rax), %ymm1, %ymm2
+
+vpslldq $1, %ymm1, %ymm2
+
+vpsllq $1, %ymm0, %ymm2
+vpsllq %xmm0, %ymm1, %ymm2
+vpsllq (%rax), %ymm1, %ymm2
+
+vpsllvd %xmm0, %xmm1, %xmm2
+vpsllvd (%rax), %xmm1, %xmm2
+
+vpsllvd %ymm0, %ymm1, %ymm2
+vpsllvd (%rax), %ymm1, %ymm2
+
+vpsllvq %xmm0, %xmm1, %xmm2
+vpsllvq (%rax), %xmm1, %xmm2
+
+vpsllvq %ymm0, %ymm1, %ymm2
+vpsllvq (%rax), %ymm1, %ymm2
+
+vpsllw $1, %ymm0, %ymm2
+vpsllw %xmm0, %ymm1, %ymm2
+vpsllw (%rax), %ymm1, %ymm2
+
+vpsrad $1, %ymm0, %ymm2
+vpsrad %xmm0, %ymm1, %ymm2
+vpsrad (%rax), %ymm1, %ymm2
+
+vpsravd %xmm0, %xmm1, %xmm2
+vpsravd (%rax), %xmm1, %xmm2
+
+vpsravd %ymm0, %ymm1, %ymm2
+vpsravd (%rax), %ymm1, %ymm2
+
+vpsraw $1, %ymm0, %ymm2
+vpsraw %xmm0, %ymm1, %ymm2
+vpsraw (%rax), %ymm1, %ymm2
+
+vpsrld $1, %ymm0, %ymm2
+vpsrld %xmm0, %ymm1, %ymm2
+vpsrld (%rax), %ymm1, %ymm2
+
+vpsrldq $1, %ymm1, %ymm2
+
+vpsrlq $1, %ymm0, %ymm2
+vpsrlq %xmm0, %ymm1, %ymm2
+vpsrlq (%rax), %ymm1, %ymm2
+
+vpsrlvd %xmm0, %xmm1, %xmm2
+vpsrlvd (%rax), %xmm1, %xmm2
+
+vpsrlvd %ymm0, %ymm1, %ymm2
+vpsrlvd (%rax), %ymm1, %ymm2
+
+vpsrlvq %xmm0, %xmm1, %xmm2
+vpsrlvq (%rax), %xmm1, %xmm2
+
+vpsrlvq %ymm0, %ymm1, %ymm2
+vpsrlvq (%rax), %ymm1, %ymm2
+
+vpsrlw $1, %ymm0, %ymm2
+vpsrlw %xmm0, %ymm1, %ymm2
+vpsrlw (%rax), %ymm1, %ymm2
+
+vpsubb %ymm0, %ymm1, %ymm2
+vpsubb (%rax), %ymm1, %ymm2
+
+vpsubd %ymm0, %ymm1, %ymm2
+vpsubd (%rax), %ymm1, %ymm2
+
+vpsubq %ymm0, %ymm1, %ymm2
+vpsubq (%rax), %ymm1, %ymm2
+
+vpsubsb %ymm0, %ymm1, %ymm2
+vpsubsb (%rax), %ymm1, %ymm2
+
+vpsubsw %ymm0, %ymm1, %ymm2
+vpsubsw (%rax), %ymm1, %ymm2
+
+vpsubusb %ymm0, %ymm1, %ymm2
+vpsubusb (%rax), %ymm1, %ymm2
+
+vpsubusw %ymm0, %ymm1, %ymm2
+vpsubusw (%rax), %ymm1, %ymm2
+
+vpsubw %ymm0, %ymm1, %ymm2
+vpsubw (%rax), %ymm1, %ymm2
+
+vpunpckhbw %ymm0, %ymm1, %ymm2
+vpunpckhbw (%rax), %ymm1, %ymm2
+
+vpunpckhdq %ymm0, %ymm1, %ymm2
+vpunpckhdq (%rax), %ymm1, %ymm2
+
+vpunpckhqdq %ymm0, %ymm1, %ymm2
+vpunpckhqdq (%rax), %ymm1, %ymm2
+
+vpunpckhwd %ymm0, %ymm1, %ymm2
+vpunpckhwd (%rax), %ymm1, %ymm2
+
+vpunpcklbw %ymm0, %ymm1, %ymm2
+vpunpcklbw (%rax), %ymm1, %ymm2
+
+vpunpckldq %ymm0, %ymm1, %ymm2
+vpunpckldq (%rax), %ymm1, %ymm2
+
+vpunpcklqdq %ymm0, %ymm1, %ymm2
+vpunpcklqdq (%rax), %ymm1, %ymm2
+
+vpunpcklwd %ymm0, %ymm1, %ymm2
+vpunpcklwd (%rax), %ymm1, %ymm2
+
+vpxor %ymm0, %ymm1, %ymm2
+vpxor (%rax), %ymm1, %ymm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 8 0.50 * vbroadcasti128 (%rax), %ymm0
+# CHECK-NEXT: 1 3 0.50 vbroadcastsd %xmm0, %ymm0
+# CHECK-NEXT: 1 3 0.50 vbroadcastss %xmm0, %ymm0
+# CHECK-NEXT: 1 3 0.50 vextracti128 $1, %ymm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * vextracti128 $1, %ymm0, (%rax)
+# CHECK-NEXT: 2 8 0.33 * vgatherdpd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 2 8 0.33 * vgatherdpd %ymm0, (%rax,%xmm1,2), %ymm2
+# CHECK-NEXT: 2 8 0.33 * vgatherdps %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 2 8 0.33 * vgatherdps %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 2 8 0.33 * vgatherqpd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 2 8 0.33 * vgatherqpd %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 2 8 0.33 * vgatherqps %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 2 8 0.33 * vgatherqps %xmm0, (%rax,%ymm1,2), %xmm2
+# CHECK-NEXT: 1 3 0.50 vinserti128 $1, %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vinserti128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vmovntdqa (%rax), %ymm0
+# CHECK-NEXT: 1 4 2.00 vmpsadbw $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 2.00 * vmpsadbw $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpabsb %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpabsb (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.25 vpabsd %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpabsd (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.25 vpabsw %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpabsw (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vpackssdw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpackssdw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpacksswb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpacksswb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpackusdw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpackusdw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpackuswb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpackuswb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpaddb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpaddb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpaddd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpaddd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpaddq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpaddq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpaddsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpaddsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpaddsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpaddsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpaddusb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpaddusb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpaddusw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpaddusw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpaddw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpaddw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpalignr $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpalignr $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpand %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpand (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpandn %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpandn (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpavgb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpavgb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpavgw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpavgw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpblendd $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 0.33 * vpblendd $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 0.25 vpblendd $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpblendd $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpblendvb %ymm3, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpblendvb %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpblendw $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpblendw $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpbroadcastb %xmm0, %xmm0
+# CHECK-NEXT: 1 8 0.50 * vpbroadcastb (%rax), %xmm0
+# CHECK-NEXT: 1 3 0.50 vpbroadcastb %xmm0, %ymm0
+# CHECK-NEXT: 1 8 0.50 * vpbroadcastb (%rax), %ymm0
+# CHECK-NEXT: 1 1 0.50 vpbroadcastd %xmm0, %xmm0
+# CHECK-NEXT: 1 8 0.50 * vpbroadcastd (%rax), %xmm0
+# CHECK-NEXT: 1 3 0.50 vpbroadcastd %xmm0, %ymm0
+# CHECK-NEXT: 1 8 0.50 * vpbroadcastd (%rax), %ymm0
+# CHECK-NEXT: 1 1 0.50 vpbroadcastq %xmm0, %xmm0
+# CHECK-NEXT: 1 8 0.50 * vpbroadcastq (%rax), %xmm0
+# CHECK-NEXT: 1 3 0.50 vpbroadcastq %xmm0, %ymm0
+# CHECK-NEXT: 1 8 0.50 * vpbroadcastq (%rax), %ymm0
+# CHECK-NEXT: 1 1 0.50 vpbroadcastw %xmm0, %xmm0
+# CHECK-NEXT: 1 8 0.50 * vpbroadcastw (%rax), %xmm0
+# CHECK-NEXT: 1 3 0.50 vpbroadcastw %xmm0, %ymm0
+# CHECK-NEXT: 1 8 0.50 * vpbroadcastw (%rax), %ymm0
+# CHECK-NEXT: 1 1 0.25 vpcmpeqb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpcmpeqd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpcmpeqq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpcmpeqw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpcmpgtb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpcmpgtb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpcmpgtd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpcmpgtd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpcmpgtq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpcmpgtq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpcmpgtw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpcmpgtw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 8 8 8.00 vperm2i128 $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 8 15 8.00 * vperm2i128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 2 2.00 vpermd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 9 2.00 * vpermd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vpermpd $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpermpd $1, (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpermps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpermps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vpermq $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpermq $1, (%rax), %ymm2
+# CHECK-NEXT: 2 8 0.33 * vpgatherdd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 2 8 0.33 * vpgatherdd %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 2 8 0.33 * vpgatherdq %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 2 8 0.33 * vpgatherdq %ymm0, (%rax,%xmm1,2), %ymm2
+# CHECK-NEXT: 2 8 0.33 * vpgatherqd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 2 8 0.33 * vpgatherqd %xmm0, (%rax,%ymm1,2), %xmm2
+# CHECK-NEXT: 2 8 0.33 * vpgatherqq %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 2 8 0.33 * vpgatherqq %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 4 3 4.00 vphaddd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 7 10 4.00 * vphaddd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 4 3 4.00 vphaddsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 7 10 4.00 * vphaddsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 4 3 4.00 vphaddw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 7 10 4.00 * vphaddw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 4 3 4.00 vphsubd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 7 10 4.00 * vphsubd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 4 3 4.00 vphsubsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 7 10 4.00 * vphsubsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 4 3 4.00 vphsubw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 7 10 4.00 * vphsubw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmaddubsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmaddubsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmaddwd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmaddwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 8 1.00 * vpmaskmovd (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 1 8 1.00 * vpmaskmovd (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 1 2 0.50 * * vpmaskmovd %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 1 2 0.50 * * vpmaskmovd %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: 1 8 1.00 * vpmaskmovq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 1 8 1.00 * vpmaskmovq (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 1 2 0.50 * * vpmaskmovq %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 1 2 0.50 * * vpmaskmovq %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: 1 1 0.25 vpmaxsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpmaxsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpmaxsd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpmaxsd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpmaxsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpmaxsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpmaxub %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpmaxub (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpmaxud %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpmaxud (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpmaxuw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpmaxuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpminsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpminsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpminsd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpminsd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpminsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpminsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpminub %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpminub (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpminud %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpminud (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpminuw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpminuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpmovmskb %ymm0, %ecx
+# CHECK-NEXT: 1 3 0.50 vpmovsxbd %xmm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmovsxbd (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovsxbq %xmm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmovsxbq (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovsxbw %xmm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmovsxbw (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovsxdq %xmm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmovsxdq (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovsxwd %xmm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmovsxwd (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovsxwq %xmm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmovsxwq (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovzxbd %xmm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmovzxbd (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovzxbq %xmm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmovzxbq (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovzxbw %xmm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmovzxbw (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovzxdq %xmm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmovzxdq (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovzxwd %xmm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmovzxwd (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmovzxwq %xmm0, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmovzxwq (%rax), %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmuldq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmuldq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmulhrsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmulhrsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmulhuw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmulhuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmulhw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmulhw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmulld %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmulld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmullw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmullw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vpmuludq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpmuludq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpor %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpor (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 1.00 vpsadbw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 1.00 * vpsadbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpshufb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpshufb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpshufd $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpshufd $1, (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vpshufhw $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpshufhw $1, (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.50 vpshuflw $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpshuflw $1, (%rax), %ymm2
+# CHECK-NEXT: 1 1 0.25 vpsignb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpsignb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpsignd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpsignd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpsignw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpsignw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpslld $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 3 0.50 vpslld %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpslld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpslldq $1, %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsllq $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 3 0.50 vpsllq %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpsllq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 2.00 vpsllvd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 2.00 * vpsllvd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 2.00 vpsllvd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.00 * vpsllvd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 2.00 vpsllvq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 2.00 * vpsllvq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 2.00 vpsllvq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.00 * vpsllvq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsllw $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 3 0.50 vpsllw %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpsllw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsrad $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 3 0.50 vpsrad %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpsrad (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 2.00 vpsravd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 2.00 * vpsravd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 2.00 vpsravd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.00 * vpsravd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsraw $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 3 0.50 vpsraw %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpsraw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsrld $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 3 0.50 vpsrld %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpsrld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsrldq $1, %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsrlq $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 3 0.50 vpsrlq %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpsrlq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 2.00 vpsrlvd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 2.00 * vpsrlvd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 2.00 vpsrlvd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.00 * vpsrlvd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 2.00 vpsrlvq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 8 2.00 * vpsrlvq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 1 2.00 vpsrlvq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 2.00 * vpsrlvq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpsrlw $1, %ymm0, %ymm2
+# CHECK-NEXT: 1 3 0.50 vpsrlw %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vpsrlw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpsubb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpsubb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpsubd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpsubd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpsubq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpsubq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpsubsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpsubsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpsubsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpsubsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpsubusb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpsubusb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpsubusw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpsubusw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpsubw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpsubw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhbw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpunpckhbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhdq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpunpckhdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhqdq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpunpckhqdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpckhwd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpunpckhwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpcklbw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpunpcklbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpckldq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpunpckldq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpcklqdq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpunpcklqdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.50 vpunpcklwd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.50 * vpunpcklwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 1 0.25 vpxor %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 8 0.33 * vpxor (%rax), %ymm1, %ymm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 52.33 52.33 52.33 - - - - - 136.50 129.50 126.00 123.00 39.25 39.25 39.25 39.25 50.67 50.67 50.67 1.25 1.25 1.25 1.25
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcasti128 (%rax), %ymm0
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vbroadcastsd %xmm0, %ymm0
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vbroadcastss %xmm0, %ymm0
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vextracti128 $1, %ymm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vextracti128 $1, %ymm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgatherdpd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgatherdpd %ymm0, (%rax,%xmm1,2), %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgatherdps %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgatherdps %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgatherqpd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgatherqpd %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgatherqps %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgatherqps %xmm0, (%rax,%ymm1,2), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vinserti128 $1, %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vinserti128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovntdqa (%rax), %ymm0
+# CHECK-NEXT: - - - - - - - - 2.00 2.00 2.00 2.00 - - - - - - - - - - - vmpsadbw $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 2.00 2.00 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmpsadbw $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpabsb %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsb (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpabsd %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpabsw %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsw (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpackssdw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackssdw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpacksswb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpacksswb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpackusdw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackusdw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpackuswb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackuswb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddusb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddusb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddusw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddusw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpalignr $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpalignr $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpand %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpand (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpandn %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpandn (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpavgb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpavgb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpavgw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpavgw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpblendd $11, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpblendd $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpblendd $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpblendd $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpblendvb %ymm3, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpblendvb %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpblendw $11, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpblendw $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpbroadcastb %xmm0, %xmm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastb (%rax), %xmm0
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpbroadcastb %xmm0, %ymm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastb (%rax), %ymm0
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpbroadcastd %xmm0, %xmm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastd (%rax), %xmm0
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpbroadcastd %xmm0, %ymm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastd (%rax), %ymm0
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpbroadcastq %xmm0, %xmm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastq (%rax), %xmm0
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpbroadcastq %xmm0, %ymm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastq (%rax), %ymm0
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpbroadcastw %xmm0, %xmm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastw (%rax), %xmm0
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpbroadcastw %xmm0, %ymm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastw (%rax), %ymm0
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpeqb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpeqd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpeqq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpeqw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpgtb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpgtd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpgtq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpgtw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 8.00 8.00 8.00 8.00 - - - - - - - - - - - vperm2i128 $1, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 8.00 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vperm2i128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 2.00 - - - - - - - - - - - vpermd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpermpd $1, %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermpd $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpermps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpermq $1, %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermq $1, (%rax), %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpgatherdd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpgatherdd %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpgatherdq %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpgatherdq %ymm0, (%rax,%xmm1,2), %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpgatherqd %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpgatherqd %xmm0, (%rax,%ymm1,2), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpgatherqq %xmm0, (%rax,%xmm1,2), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpgatherqq %ymm0, (%rax,%ymm1,2), %ymm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - vphaddd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vphaddd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - vphaddsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vphaddsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - vphaddw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vphaddw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - vphsubd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vphsubd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - vphsubsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vphsubsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - vphsubw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vphsubw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmaddubsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaddubsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmaddwd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaddwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 1.00 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaskmovd (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 1.00 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaskmovd (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vpmaskmovd %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vpmaskmovd %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 1.00 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaskmovq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 1.00 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaskmovq (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vpmaskmovq %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vpmaskmovq %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxsd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxsd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxub %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxub (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxud %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxud (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxuw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminsd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminsd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminub %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminub (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminud %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminud (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminuw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovmskb %ymm0, %ecx
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxbd %xmm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxbq %xmm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbq (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxbw %xmm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbw (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxdq %xmm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxdq (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxwd %xmm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxwd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxwq %xmm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxwq (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxbd %xmm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxbq %xmm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbq (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxbw %xmm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbw (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxdq %xmm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxdq (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxwd %xmm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxwd (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxwq %xmm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxwq (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmuldq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmuldq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmulhrsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhrsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmulhuw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmulhw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmulld %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmullw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmullw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmuludq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmuludq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpor %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpor (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsadbw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsadbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpshufb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpshufd $1, %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufd $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpshufhw $1, %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufhw $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpshuflw $1, %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshuflw $1, (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsignb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsignb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsignd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsignd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsignw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsignw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpslld $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpslld %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpslld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpslldq $1, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsllq $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsllq %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpsllvd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllvd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpsllvd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllvd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpsllvq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllvq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpsllvq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllvq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsllw $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsllw %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsrad $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsrad %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrad (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpsravd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsravd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpsravd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsravd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsraw $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsraw %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsraw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsrld $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsrld %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpsrldq $1, %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsrlq $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsrlq %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpsrlvd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlvd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpsrlvd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlvd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpsrlvq %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlvq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpsrlvq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlvq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsrlw $1, %ymm0, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsrlw %xmm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubsb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubsw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubusb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubusb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubusw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubusw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckhbw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckhdq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckhqdq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhqdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckhwd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpcklbw %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpcklbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckldq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckldq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpcklqdq %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpcklqdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpcklwd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpcklwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpxor %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpxor (%rax), %ymm1, %ymm2
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512.s
new file mode 100644
index 0000000000000..3351cc25b2cf3
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512.s
@@ -0,0 +1,3264 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+kandw %k0, %k1, %k2
+kandnw %k0, %k1, %k2
+knotw %k0, %k2
+korw %k0, %k1, %k2
+kxnorw %k0, %k1, %k2
+kxorw %k0, %k1, %k2
+kshiftlw $2, %k1, %k2
+kshiftrw $2, %k1, %k2
+kunpckbw %k0, %k1, %k2
+
+vaddpd %zmm16, %zmm17, %zmm19
+vaddpd (%rax), %zmm17, %zmm19
+vaddpd (%rax){1to8}, %zmm17, %zmm19
+vaddpd %zmm16, %zmm17, %zmm19 {k1}
+vaddpd (%rax), %zmm17, %zmm19 {k1}
+vaddpd (%rax){1to8}, %zmm17, %zmm19 {k1}
+vaddpd %zmm16, %zmm17, %zmm19 {z}{k1}
+vaddpd (%rax), %zmm17, %zmm19 {z}{k1}
+vaddpd (%rax){1to8}, %zmm17, %zmm19 {z}{k1}
+
+vaddps %zmm16, %zmm17, %zmm19
+vaddps (%rax), %zmm17, %zmm19
+vaddps (%rax){1to16}, %zmm17, %zmm19
+vaddps %zmm16, %zmm17, %zmm19 {k1}
+vaddps (%rax), %zmm17, %zmm19 {k1}
+vaddps (%rax){1to16}, %zmm17, %zmm19 {k1}
+vaddps %zmm16, %zmm17, %zmm19 {z}{k1}
+vaddps (%rax), %zmm17, %zmm19 {z}{k1}
+vaddps (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
+
+valignd $1, %zmm16, %zmm17, %zmm19
+valignd $1, (%rax), %zmm17, %zmm19
+valignd $1, (%rax){1to16}, %zmm17, %zmm19
+valignd $1, %zmm16, %zmm17, %zmm19 {k1}
+valignd $1, (%rax), %zmm17, %zmm19 {k1}
+valignd $1, (%rax){1to16}, %zmm17, %zmm19 {k1}
+valignd $1, %zmm16, %zmm17, %zmm19 {z}{k1}
+valignd $1, (%rax), %zmm17, %zmm19 {z}{k1}
+valignd $1, (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
+
+valignq $1, %zmm16, %zmm17, %zmm19
+valignq $1, (%rax), %zmm17, %zmm19
+valignq $1, (%rax){1to8}, %zmm17, %zmm19
+valignq $1, %zmm16, %zmm17, %zmm19 {k1}
+valignq $1, (%rax), %zmm17, %zmm19 {k1}
+valignq $1, (%rax){1to8}, %zmm17, %zmm19 {k1}
+valignq $1, %zmm16, %zmm17, %zmm19 {z}{k1}
+valignq $1, (%rax), %zmm17, %zmm19 {z}{k1}
+valignq $1, (%rax){1to8}, %zmm17, %zmm19 {z}{k1}
+
+vbroadcastf32x4 (%rax), %zmm19
+vbroadcastf32x4 (%rax), %zmm19 {k1}
+vbroadcastf32x4 (%rax), %zmm19 {z}{k1}
+
+vbroadcastf64x4 (%rax), %zmm19
+vbroadcastf64x4 (%rax), %zmm19 {k1}
+vbroadcastf64x4 (%rax), %zmm19 {z}{k1}
+
+vbroadcasti32x4 (%rax), %zmm19
+vbroadcasti32x4 (%rax), %zmm19 {k1}
+vbroadcasti32x4 (%rax), %zmm19 {z}{k1}
+
+vbroadcasti64x4 (%rax), %zmm19
+vbroadcasti64x4 (%rax), %zmm19 {k1}
+vbroadcasti64x4 (%rax), %zmm19 {z}{k1}
+
+vbroadcastsd %xmm16, %zmm19
+vbroadcastsd (%rax), %zmm19
+vbroadcastsd %xmm16, %zmm19 {k1}
+vbroadcastsd (%rax), %zmm19 {k1}
+vbroadcastsd %xmm16, %zmm19 {z}{k1}
+vbroadcastsd (%rax), %zmm19 {z}{k1}
+
+vbroadcastss %xmm16, %zmm19
+vbroadcastss (%rax), %zmm19
+vbroadcastss %xmm16, %zmm19 {k1}
+vbroadcastss (%rax), %zmm19 {k1}
+vbroadcastss %xmm16, %zmm19 {z}{k1}
+vbroadcastss (%rax), %zmm19 {z}{k1}
+
+vcmppd $0, %zmm0, %zmm1, %k2
+vcmppd $0, (%rax), %zmm1, %k2
+vcmppd $0, (%rax){1to8}, %zmm1, %k2
+vcmppd $0, %zmm0, %zmm1, %k2 {k3}
+vcmppd $0, (%rax), %zmm1, %k2 {k3}
+vcmppd $0, (%rax){1to8}, %zmm1, %k2 {k3}
+
+vcmpps $0, %zmm0, %zmm1, %k2
+vcmpps $0, (%rax), %zmm1, %k2
+vcmpps $0, (%rax){1to16}, %zmm1, %k2
+vcmpps $0, %zmm0, %zmm1, %k2 {k3}
+vcmpps $0, (%rax), %zmm1, %k2 {k3}
+vcmpps $0, (%rax){1to16}, %zmm1, %k2 {k3}
+
+vcmpsd $0, %xmm0, %xmm1, %k2
+vcmpsd $0, (%rax), %xmm1, %k2
+vcmpsd $0, %xmm0, %xmm1, %k2 {k3}
+vcmpsd $0, (%rax), %xmm1, %k2 {k3}
+
+vcmpss $0, %xmm0, %xmm1, %k2
+vcmpss $0, (%rax), %xmm1, %k2
+vcmpss $0, %xmm0, %xmm1, %k2 {k3}
+vcmpss $0, (%rax), %xmm1, %k2 {k3}
+
+vcomiss %xmm16, %xmm17
+vcomiss (%rax), %xmm17
+
+vcvtdq2pd %ymm16, %zmm19
+vcvtdq2pd (%rax), %zmm19
+vcvtdq2pd (%rax){1to8}, %zmm19
+vcvtdq2pd %ymm16, %zmm19 {k1}
+vcvtdq2pd (%rax), %zmm19 {k1}
+vcvtdq2pd (%rax){1to8}, %zmm19 {k1}
+vcvtdq2pd %ymm16, %zmm19 {z}{k1}
+vcvtdq2pd (%rax), %zmm19 {z}{k1}
+vcvtdq2pd (%rax){1to8}, %zmm19 {z}{k1}
+
+vcvtdq2ps %zmm16, %zmm19
+vcvtdq2ps (%rax), %zmm19
+vcvtdq2ps (%rax){1to16}, %zmm19
+vcvtdq2ps %zmm16, %zmm19 {k1}
+vcvtdq2ps (%rax), %zmm19 {k1}
+vcvtdq2ps (%rax){1to16}, %zmm19 {k1}
+vcvtdq2ps %zmm16, %zmm19 {z}{k1}
+vcvtdq2ps (%rax), %zmm19 {z}{k1}
+vcvtdq2ps (%rax){1to16}, %zmm19 {z}{k1}
+
+vcvtpd2dq %zmm16, %ymm19
+vcvtpd2dq (%rax), %ymm19
+vcvtpd2dq (%rax){1to8}, %ymm19
+vcvtpd2dq %zmm16, %ymm19 {k1}
+vcvtpd2dq (%rax), %ymm19 {k1}
+vcvtpd2dq (%rax){1to8}, %ymm19 {k1}
+vcvtpd2dq %zmm16, %ymm19 {z}{k1}
+vcvtpd2dq (%rax), %ymm19 {z}{k1}
+vcvtpd2dq (%rax){1to8}, %ymm19 {z}{k1}
+
+vcvtpd2udq %zmm16, %ymm19
+vcvtpd2udq (%rax), %ymm19
+vcvtpd2udq (%rax){1to8}, %ymm19
+vcvtpd2udq %zmm16, %ymm19 {k1}
+vcvtpd2udq (%rax), %ymm19 {k1}
+vcvtpd2udq (%rax){1to8}, %ymm19 {k1}
+vcvtpd2udq %zmm16, %ymm19 {z}{k1}
+vcvtpd2udq (%rax), %ymm19 {z}{k1}
+vcvtpd2udq (%rax){1to8}, %ymm19 {z}{k1}
+
+vcvttpd2dq %zmm16, %ymm19
+vcvttpd2dq (%rax), %ymm19
+vcvttpd2dq (%rax){1to8}, %ymm19
+vcvttpd2dq %zmm16, %ymm19 {k1}
+vcvttpd2dq (%rax), %ymm19 {k1}
+vcvttpd2dq (%rax){1to8}, %ymm19 {k1}
+vcvttpd2dq %zmm16, %ymm19 {z}{k1}
+vcvttpd2dq (%rax), %ymm19 {z}{k1}
+vcvttpd2dq (%rax){1to8}, %ymm19 {z}{k1}
+
+vcvttpd2udq %zmm16, %ymm19
+vcvttpd2udq (%rax), %ymm19
+vcvttpd2udq (%rax){1to8}, %ymm19
+vcvttpd2udq %zmm16, %ymm19 {k1}
+vcvttpd2udq (%rax), %ymm19 {k1}
+vcvttpd2udq (%rax){1to8}, %ymm19 {k1}
+vcvttpd2udq %zmm16, %ymm19 {z}{k1}
+vcvttpd2udq (%rax), %ymm19 {z}{k1}
+vcvttpd2udq (%rax){1to8}, %ymm19 {z}{k1}
+
+vcvtpd2ps %zmm16, %ymm19
+vcvtpd2ps (%rax), %ymm19
+vcvtpd2ps (%rax){1to8}, %ymm19
+vcvtpd2ps %zmm16, %ymm19 {k1}
+vcvtpd2ps (%rax), %ymm19 {k1}
+vcvtpd2ps (%rax){1to8}, %ymm19 {k1}
+vcvtpd2ps %zmm16, %ymm19 {z}{k1}
+vcvtpd2ps (%rax), %ymm19 {z}{k1}
+vcvtpd2ps (%rax){1to8}, %ymm19 {z}{k1}
+
+vcvtps2dq %zmm16, %zmm19
+vcvtps2dq (%rax), %zmm19
+vcvtps2dq (%rax){1to16}, %zmm19
+vcvtps2dq %zmm16, %zmm19 {k1}
+vcvtps2dq (%rax), %zmm19 {k1}
+vcvtps2dq (%rax){1to16}, %zmm19 {k1}
+vcvtps2dq %zmm16, %zmm19 {z}{k1}
+vcvtps2dq (%rax), %zmm19 {z}{k1}
+vcvtps2dq (%rax){1to16}, %zmm19 {z}{k1}
+
+vcvttps2dq %zmm16, %zmm19
+vcvttps2dq (%rax), %zmm19
+vcvttps2dq (%rax){1to16}, %zmm19
+vcvttps2dq %zmm16, %zmm19 {k1}
+vcvttps2dq (%rax), %zmm19 {k1}
+vcvttps2dq (%rax){1to16}, %zmm19 {k1}
+vcvttps2dq %zmm16, %zmm19 {z}{k1}
+vcvttps2dq (%rax), %zmm19 {z}{k1}
+vcvttps2dq (%rax){1to16}, %zmm19 {z}{k1}
+
+vcvtps2pd %ymm16, %zmm19
+vcvtps2pd (%rax), %zmm19
+vcvtps2pd (%rax){1to8}, %zmm19
+vcvtps2pd %ymm16, %zmm19 {k1}
+vcvtps2pd (%rax), %zmm19 {k1}
+vcvtps2pd (%rax){1to8}, %zmm19 {k1}
+vcvtps2pd %ymm16, %zmm19 {z}{k1}
+vcvtps2pd (%rax), %zmm19 {z}{k1}
+vcvtps2pd (%rax){1to8}, %zmm19 {z}{k1}
+
+vcvtsd2usi %xmm0, %ecx
+vcvtsd2usi %xmm0, %rcx
+vcvtsd2usi (%rax), %ecx
+vcvtsd2usi (%rax), %rcx
+
+vcvtss2usi %xmm0, %ecx
+vcvtss2usi %xmm0, %rcx
+vcvtss2usi (%rax), %ecx
+vcvtss2usi (%rax), %rcx
+
+vcvtps2udq %zmm16, %zmm19
+vcvtps2udq (%rax), %zmm19
+vcvtps2udq (%rax){1to16}, %zmm19
+vcvtps2udq %zmm16, %zmm19 {k1}
+vcvtps2udq (%rax), %zmm19 {k1}
+vcvtps2udq (%rax){1to16}, %zmm19 {k1}
+vcvtps2udq %zmm16, %zmm19 {z}{k1}
+vcvtps2udq (%rax), %zmm19 {z}{k1}
+vcvtps2udq (%rax){1to16}, %zmm19 {z}{k1}
+
+vcvttps2udq %zmm16, %zmm19
+vcvttps2udq (%rax), %zmm19
+vcvttps2udq (%rax){1to16}, %zmm19
+vcvttps2udq %zmm16, %zmm19 {k1}
+vcvttps2udq (%rax), %zmm19 {k1}
+vcvttps2udq (%rax){1to16}, %zmm19 {k1}
+vcvttps2udq %zmm16, %zmm19 {z}{k1}
+vcvttps2udq (%rax), %zmm19 {z}{k1}
+vcvttps2udq (%rax){1to16}, %zmm19 {z}{k1}
+
+vcvttsd2usi %xmm0, %ecx
+vcvttsd2usi %xmm0, %rcx
+vcvttsd2usi (%rax), %ecx
+vcvttsd2usi (%rax), %rcx
+
+vcvttss2usi %xmm0, %ecx
+vcvttss2usi %xmm0, %rcx
+vcvttss2usi (%rax), %ecx
+vcvttss2usi (%rax), %rcx
+
+vcvtudq2pd %ymm16, %zmm19
+vcvtudq2pd (%rax), %zmm19
+vcvtudq2pd (%rax){1to8}, %zmm19
+vcvtudq2pd %ymm16, %zmm19 {k1}
+vcvtudq2pd (%rax), %zmm19 {k1}
+vcvtudq2pd (%rax){1to8}, %zmm19 {k1}
+vcvtudq2pd %ymm16, %zmm19 {z}{k1}
+vcvtudq2pd (%rax), %zmm19 {z}{k1}
+vcvtudq2pd (%rax){1to8}, %zmm19 {z}{k1}
+
+vcvtudq2ps %zmm16, %zmm19
+vcvtudq2ps (%rax), %zmm19
+vcvtudq2ps (%rax){1to16}, %zmm19
+vcvtudq2ps %zmm16, %zmm19 {k1}
+vcvtudq2ps (%rax), %zmm19 {k1}
+vcvtudq2ps (%rax){1to16}, %zmm19 {k1}
+vcvtudq2ps %zmm16, %zmm19 {z}{k1}
+vcvtudq2ps (%rax), %zmm19 {z}{k1}
+vcvtudq2ps (%rax){1to16}, %zmm19 {z}{k1}
+
+vcvtusi2sdl %ecx, %xmm0, %xmm2
+vcvtusi2sdq %rcx, %xmm0, %xmm2
+vcvtusi2sdl (%rax), %xmm0, %xmm2
+vcvtusi2sdq (%rax), %xmm0, %xmm2
+
+vcvtusi2ssl %ecx, %xmm0, %xmm2
+vcvtusi2ssq %rcx, %xmm0, %xmm2
+vcvtusi2ssl (%rax), %xmm0, %xmm2
+vcvtusi2ssq (%rax), %xmm0, %xmm2
+
+vdivpd %zmm16, %zmm17, %zmm19
+vdivpd (%rax), %zmm17, %zmm19
+vdivpd (%rax){1to8}, %zmm17, %zmm19
+vdivpd %zmm16, %zmm17, %zmm19 {k1}
+vdivpd (%rax), %zmm17, %zmm19 {k1}
+vdivpd (%rax){1to8}, %zmm17, %zmm19 {k1}
+vdivpd %zmm16, %zmm17, %zmm19 {z}{k1}
+vdivpd (%rax), %zmm17, %zmm19 {z}{k1}
+vdivpd (%rax){1to8}, %zmm17, %zmm19 {z}{k1}
+
+vdivps %zmm16, %zmm17, %zmm19
+vdivps (%rax), %zmm17, %zmm19
+vdivps (%rax){1to16}, %zmm17, %zmm19
+vdivps %zmm16, %zmm17, %zmm19 {k1}
+vdivps (%rax), %zmm17, %zmm19 {k1}
+vdivps (%rax){1to16}, %zmm17, %zmm19 {k1}
+vdivps %zmm16, %zmm17, %zmm19 {z}{k1}
+vdivps (%rax), %zmm17, %zmm19 {z}{k1}
+vdivps (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
+
+{evex} vextractps $1, %xmm0, %rcx
+{evex} vextractps $1, %xmm0, (%rax)
+
+vfmadd132pd %zmm16, %zmm17, %zmm19
+vfmadd132pd (%rax), %zmm17, %zmm19
+vfmadd132pd (%rax){1to8}, %zmm17, %zmm19
+vfmadd132pd %zmm16, %zmm17, %zmm19 {k1}
+vfmadd132pd (%rax), %zmm17, %zmm19 {k1}
+vfmadd132pd (%rax){1to8}, %zmm17, %zmm19 {k1}
+vfmadd132pd %zmm16, %zmm17, %zmm19 {z}{k1}
+vfmadd132pd (%rax), %zmm17, %zmm19 {z}{k1}
+vfmadd132pd (%rax){1to8}, %zmm17, %zmm19 {z}{k1}
+
+vfmadd213pd %zmm16, %zmm17, %zmm19
+vfmadd213pd (%rax), %zmm17, %zmm19
+vfmadd213pd (%rax){1to8}, %zmm17, %zmm19
+vfmadd213pd %zmm16, %zmm17, %zmm19 {k1}
+vfmadd213pd (%rax), %zmm17, %zmm19 {k1}
+vfmadd213pd (%rax){1to8}, %zmm17, %zmm19 {k1}
+vfmadd213pd %zmm16, %zmm17, %zmm19 {z}{k1}
+vfmadd213pd (%rax), %zmm17, %zmm19 {z}{k1}
+vfmadd213pd (%rax){1to8}, %zmm17, %zmm19 {z}{k1}
+
+vfmadd231pd %zmm16, %zmm17, %zmm19
+vfmadd231pd (%rax), %zmm17, %zmm19
+vfmadd231pd (%rax){1to8}, %zmm17, %zmm19
+vfmadd231pd %zmm16, %zmm17, %zmm19 {k1}
+vfmadd231pd (%rax), %zmm17, %zmm19 {k1}
+vfmadd231pd (%rax){1to8}, %zmm17, %zmm19 {k1}
+vfmadd231pd %zmm16, %zmm17, %zmm19 {z}{k1}
+vfmadd231pd (%rax), %zmm17, %zmm19 {z}{k1}
+vfmadd231pd (%rax){1to8}, %zmm17, %zmm19 {z}{k1}
+
+vfmadd132ps %zmm16, %zmm17, %zmm19
+vfmadd132ps (%rax), %zmm17, %zmm19
+vfmadd132ps (%rax){1to16}, %zmm17, %zmm19
+vfmadd132ps %zmm16, %zmm17, %zmm19 {k1}
+vfmadd132ps (%rax), %zmm17, %zmm19 {k1}
+vfmadd132ps (%rax){1to16}, %zmm17, %zmm19 {k1}
+vfmadd132ps %zmm16, %zmm17, %zmm19 {z}{k1}
+vfmadd132ps (%rax), %zmm17, %zmm19 {z}{k1}
+vfmadd132ps (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
+
+vfmadd213ps %zmm16, %zmm17, %zmm19
+vfmadd213ps (%rax), %zmm17, %zmm19
+vfmadd213ps (%rax){1to16}, %zmm17, %zmm19
+vfmadd213ps %zmm16, %zmm17, %zmm19 {k1}
+vfmadd213ps (%rax), %zmm17, %zmm19 {k1}
+vfmadd213ps (%rax){1to16}, %zmm17, %zmm19 {k1}
+vfmadd213ps %zmm16, %zmm17, %zmm19 {z}{k1}
+vfmadd213ps (%rax), %zmm17, %zmm19 {z}{k1}
+vfmadd213ps (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
+
+vfmadd231ps %zmm16, %zmm17, %zmm19
+vfmadd231ps (%rax), %zmm17, %zmm19
+vfmadd231ps (%rax){1to16}, %zmm17, %zmm19
+vfmadd231ps %zmm16, %zmm17, %zmm19 {k1}
+vfmadd231ps (%rax), %zmm17, %zmm19 {k1}
+vfmadd231ps (%rax){1to16}, %zmm17, %zmm19 {k1}
+vfmadd231ps %zmm16, %zmm17, %zmm19 {z}{k1}
+vfmadd231ps (%rax), %zmm17, %zmm19 {z}{k1}
+vfmadd231ps (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
+
+vgatherdpd (%rax,%ymm1,2), %zmm2 {k1}
+vgatherdps (%rax,%zmm1,2), %zmm2 {k1}
+vgatherqpd (%rax,%zmm1,2), %zmm2 {k1}
+vgatherqps (%rax,%zmm1,2), %ymm2 {k1}
+
+vmaxpd %zmm16, %zmm17, %zmm19
+vmaxpd (%rax), %zmm17, %zmm19
+vmaxpd (%rax){1to8}, %zmm17, %zmm19
+vmaxpd %zmm16, %zmm17, %zmm19 {k1}
+vmaxpd (%rax), %zmm17, %zmm19 {k1}
+vmaxpd (%rax){1to8}, %zmm17, %zmm19 {k1}
+vmaxpd %zmm16, %zmm17, %zmm19 {z}{k1}
+vmaxpd (%rax), %zmm17, %zmm19 {z}{k1}
+vmaxpd (%rax){1to8}, %zmm17, %zmm19 {z}{k1}
+
+vmaxps %zmm16, %zmm17, %zmm19
+vmaxps (%rax), %zmm17, %zmm19
+vmaxps (%rax){1to16}, %zmm17, %zmm19
+vmaxps %zmm16, %zmm17, %zmm19 {k1}
+vmaxps (%rax), %zmm17, %zmm19 {k1}
+vmaxps (%rax){1to16}, %zmm17, %zmm19 {k1}
+vmaxps %zmm16, %zmm17, %zmm19 {z}{k1}
+vmaxps (%rax), %zmm17, %zmm19 {z}{k1}
+vmaxps (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
+
+vminpd %zmm16, %zmm17, %zmm19
+vminpd (%rax), %zmm17, %zmm19
+vminpd (%rax){1to8}, %zmm17, %zmm19
+vminpd %zmm16, %zmm17, %zmm19 {k1}
+vminpd (%rax), %zmm17, %zmm19 {k1}
+vminpd (%rax){1to8}, %zmm17, %zmm19 {k1}
+vminpd %zmm16, %zmm17, %zmm19 {z}{k1}
+vminpd (%rax), %zmm17, %zmm19 {z}{k1}
+vminpd (%rax){1to8}, %zmm17, %zmm19 {z}{k1}
+
+vminps %zmm16, %zmm17, %zmm19
+vminps (%rax), %zmm17, %zmm19
+vminps (%rax){1to16}, %zmm17, %zmm19
+vminps %zmm16, %zmm17, %zmm19 {k1}
+vminps (%rax), %zmm17, %zmm19 {k1}
+vminps (%rax){1to16}, %zmm17, %zmm19 {k1}
+vminps %zmm16, %zmm17, %zmm19 {z}{k1}
+vminps (%rax), %zmm17, %zmm19 {z}{k1}
+vminps (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
+
+vmovapd %zmm16, %zmm19
+vmovapd (%rax), %zmm19
+vmovapd %zmm16, (%rax)
+vmovapd %zmm16, %zmm19 {k1}
+vmovapd (%rax), %zmm19 {k1}
+vmovapd %zmm16, (%rax) {k1}
+vmovapd %zmm16, %zmm19 {z}{k1}
+vmovapd (%rax), %zmm19 {z}{k1}
+
+vmovaps %zmm16, %zmm19
+vmovaps (%rax), %zmm19
+vmovaps %zmm16, (%rax)
+vmovaps %zmm16, %zmm19 {k1}
+vmovaps (%rax), %zmm19 {k1}
+vmovaps %zmm16, (%rax) {k1}
+vmovaps %zmm16, %zmm19 {z}{k1}
+vmovaps (%rax), %zmm19 {z}{k1}
+
+vmovddup %zmm16, %zmm19
+vmovddup (%rax), %zmm19
+vmovddup %zmm16, %zmm19 {k1}
+vmovddup (%rax), %zmm19 {k1}
+vmovddup %zmm16, %zmm19 {z}{k1}
+vmovddup (%rax), %zmm19 {z}{k1}
+
+vmovdqa32 %zmm16, %zmm19
+vmovdqa32 (%rax), %zmm19
+vmovdqa32 %zmm16, (%rax)
+vmovdqa32 %zmm16, %zmm19 {k1}
+vmovdqa32 (%rax), %zmm19 {k1}
+vmovdqa32 %zmm16, (%rax) {k1}
+vmovdqa32 %zmm16, %zmm19 {z}{k1}
+vmovdqa32 (%rax), %zmm19 {z}{k1}
+
+vmovdqa64 %zmm16, %zmm19
+vmovdqa64 (%rax), %zmm19
+vmovdqa64 %zmm16, (%rax)
+vmovdqa64 %zmm16, %zmm19 {k1}
+vmovdqa64 (%rax), %zmm19 {k1}
+vmovdqa64 %zmm16, (%rax) {k1}
+vmovdqa64 %zmm16, %zmm19 {z}{k1}
+vmovdqa64 (%rax), %zmm19 {z}{k1}
+
+vmovdqu32 %zmm16, %zmm19
+vmovdqu32 (%rax), %zmm19
+vmovdqu32 %zmm16, (%rax)
+vmovdqu32 %zmm16, %zmm19 {k1}
+vmovdqu32 (%rax), %zmm19 {k1}
+vmovdqu32 %zmm16, (%rax) {k1}
+vmovdqu32 %zmm16, %zmm19 {z}{k1}
+vmovdqu32 (%rax), %zmm19 {z}{k1}
+
+vmovdqu64 %zmm16, %zmm19
+vmovdqu64 (%rax), %zmm19
+vmovdqu64 %zmm16, (%rax)
+vmovdqu64 %zmm16, %zmm19 {k1}
+vmovdqu64 (%rax), %zmm19 {k1}
+vmovdqu64 %zmm16, (%rax) {k1}
+vmovdqu64 %zmm16, %zmm19 {z}{k1}
+vmovdqu64 (%rax), %zmm19 {z}{k1}
+
+vmovntdqa (%rax), %zmm0
+
+vmovshdup %zmm16, %zmm19
+vmovshdup (%rax), %zmm19
+vmovshdup %zmm16, %zmm19 {k1}
+vmovshdup (%rax), %zmm19 {k1}
+vmovshdup %zmm16, %zmm19 {z}{k1}
+vmovshdup (%rax), %zmm19 {z}{k1}
+
+vmovsldup %zmm16, %zmm19
+vmovsldup (%rax), %zmm19
+vmovsldup %zmm16, %zmm19 {k1}
+vmovsldup (%rax), %zmm19 {k1}
+vmovsldup %zmm16, %zmm19 {z}{k1}
+vmovsldup (%rax), %zmm19 {z}{k1}
+
+vmovupd %zmm16, %zmm19
+vmovupd (%rax), %zmm19
+vmovupd %zmm16, (%rax)
+vmovupd %zmm16, %zmm19 {k1}
+vmovupd (%rax), %zmm19 {k1}
+vmovupd %zmm16, (%rax) {k1}
+vmovupd %zmm16, %zmm19 {z}{k1}
+vmovupd (%rax), %zmm19 {z}{k1}
+
+vmovups %zmm16, %zmm19
+vmovups (%rax), %zmm19
+vmovups %zmm16, (%rax)
+vmovups %zmm16, %zmm19 {k1}
+vmovups (%rax), %zmm19 {k1}
+vmovups %zmm16, (%rax) {k1}
+vmovups %zmm16, %zmm19 {z}{k1}
+vmovups (%rax), %zmm19 {z}{k1}
+
+vmulpd %zmm16, %zmm17, %zmm19
+vmulpd (%rax), %zmm17, %zmm19
+vmulpd (%rax){1to8}, %zmm17, %zmm19
+vmulpd %zmm16, %zmm17, %zmm19 {k1}
+vmulpd (%rax), %zmm17, %zmm19 {k1}
+vmulpd (%rax){1to8}, %zmm17, %zmm19 {k1}
+vmulpd %zmm16, %zmm17, %zmm19 {z}{k1}
+vmulpd (%rax), %zmm17, %zmm19 {z}{k1}
+vmulpd (%rax){1to8}, %zmm17, %zmm19 {z}{k1}
+
+vmulps %zmm16, %zmm17, %zmm19
+vmulps (%rax), %zmm17, %zmm19
+vmulps (%rax){1to16}, %zmm17, %zmm19
+vmulps %zmm16, %zmm17, %zmm19 {k1}
+vmulps (%rax), %zmm17, %zmm19 {k1}
+vmulps (%rax){1to16}, %zmm17, %zmm19 {k1}
+vmulps %zmm16, %zmm17, %zmm19 {z}{k1}
+vmulps (%rax), %zmm17, %zmm19 {z}{k1}
+vmulps (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
+
+vpabsd %zmm16, %zmm19
+vpabsd (%rax), %zmm19
+vpabsd (%rax){1to16}, %zmm19
+vpabsd %zmm16, %zmm19 {k1}
+vpabsd (%rax), %zmm19 {k1}
+vpabsd (%rax){1to16}, %zmm19 {k1}
+vpabsd %zmm16, %zmm19 {z}{k1}
+vpabsd (%rax), %zmm19 {z}{k1}
+vpabsd (%rax){1to16}, %zmm19 {z}{k1}
+
+vpabsq %zmm16, %zmm19
+vpabsq (%rax), %zmm19
+vpabsq (%rax){1to8}, %zmm19
+vpabsq %zmm16, %zmm19 {k1}
+vpabsq (%rax), %zmm19 {k1}
+vpabsq (%rax){1to8}, %zmm19 {k1}
+vpabsq %zmm16, %zmm19 {z}{k1}
+vpabsq (%rax), %zmm19 {z}{k1}
+vpabsq (%rax){1to8}, %zmm19 {z}{k1}
+
+vpaddd %zmm16, %zmm17, %zmm19
+vpaddd (%rax), %zmm17, %zmm19
+vpaddd (%rax){1to16}, %zmm17, %zmm19
+vpaddd %zmm16, %zmm17, %zmm19 {k1}
+vpaddd (%rax), %zmm17, %zmm19 {k1}
+vpaddd (%rax){1to16}, %zmm17, %zmm19 {k1}
+vpaddd %zmm16, %zmm17, %zmm19 {z}{k1}
+vpaddd (%rax), %zmm17, %zmm19 {z}{k1}
+vpaddd (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
+
+vpaddq %zmm16, %zmm17, %zmm19
+vpaddq (%rax), %zmm17, %zmm19
+vpaddq (%rax){1to8}, %zmm17, %zmm19
+vpaddq %zmm16, %zmm17, %zmm19 {k1}
+vpaddq (%rax), %zmm17, %zmm19 {k1}
+vpaddq (%rax){1to8}, %zmm17, %zmm19 {k1}
+vpaddq %zmm16, %zmm17, %zmm19 {z}{k1}
+vpaddq (%rax), %zmm17, %zmm19 {z}{k1}
+vpaddq (%rax){1to8}, %zmm17, %zmm19 {z}{k1}
+
+vpbroadcastd %xmm16, %zmm19
+vpbroadcastd (%rax), %zmm19
+vpbroadcastd %xmm16, %zmm19 {k1}
+vpbroadcastd (%rax), %zmm19 {k1}
+vpbroadcastd %xmm16, %zmm19 {z}{k1}
+vpbroadcastd (%rax), %zmm19 {z}{k1}
+
+vpbroadcastq %xmm16, %zmm19
+vpbroadcastq (%rax), %zmm19
+vpbroadcastq %xmm16, %zmm19 {k1}
+vpbroadcastq (%rax), %zmm19 {k1}
+vpbroadcastq %xmm16, %zmm19 {z}{k1}
+vpbroadcastq (%rax), %zmm19 {z}{k1}
+
+vpcmpd $0, %zmm0, %zmm1, %k2
+vpcmpd $0, (%rax), %zmm1, %k2
+vpcmpd $0, (%rax){1to16}, %zmm1, %k2
+vpcmpd $0, %zmm0, %zmm1, %k2 {k3}
+vpcmpd $0, (%rax), %zmm1, %k2 {k3}
+vpcmpd $0, (%rax){1to16}, %zmm1, %k2 {k3}
+
+vpcmpeqd %zmm0, %zmm1, %k2
+vpcmpeqd (%rax), %zmm1, %k2
+vpcmpeqd (%rax){1to16}, %zmm1, %k2
+vpcmpeqd %zmm0, %zmm1, %k2 {k3}
+vpcmpeqd (%rax), %zmm1, %k2 {k3}
+vpcmpeqd (%rax){1to16}, %zmm1, %k2 {k3}
+
+vpcmpeqq %zmm0, %zmm1, %k2
+vpcmpeqq (%rax), %zmm1, %k2
+vpcmpeqq (%rax){1to8}, %zmm1, %k2
+vpcmpeqq %zmm0, %zmm1, %k2 {k3}
+vpcmpeqq (%rax), %zmm1, %k2 {k3}
+vpcmpeqq (%rax){1to8}, %zmm1, %k2 {k3}
+
+vpcmpgtd %zmm0, %zmm1, %k2
+vpcmpgtd (%rax), %zmm1, %k2
+vpcmpgtd (%rax){1to16}, %zmm1, %k2
+vpcmpgtd %zmm0, %zmm1, %k2 {k3}
+vpcmpgtd (%rax), %zmm1, %k2 {k3}
+vpcmpgtd (%rax){1to16}, %zmm1, %k2 {k3}
+
+vpcmpgtq %zmm0, %zmm1, %k2
+vpcmpgtq (%rax), %zmm1, %k2
+vpcmpgtq (%rax){1to8}, %zmm1, %k2
+vpcmpgtq %zmm0, %zmm1, %k2 {k3}
+vpcmpgtq (%rax), %zmm1, %k2 {k3}
+vpcmpgtq (%rax){1to8}, %zmm1, %k2 {k3}
+
+vpcmpq $0, %zmm0, %zmm1, %k2
+vpcmpq $0, (%rax), %zmm1, %k2
+vpcmpq $0, (%rax){1to8}, %zmm1, %k2
+vpcmpq $0, %zmm0, %zmm1, %k2 {k3}
+vpcmpq $0, (%rax), %zmm1, %k2 {k3}
+vpcmpq $0, (%rax){1to8}, %zmm1, %k2 {k3}
+
+vpcmpud $0, %zmm0, %zmm1, %k2
+vpcmpud $0, (%rax), %zmm1, %k2
+vpcmpud $0, (%rax){1to16}, %zmm1, %k2
+vpcmpud $0, %zmm0, %zmm1, %k2 {k3}
+vpcmpud $0, (%rax), %zmm1, %k2 {k3}
+vpcmpud $0, (%rax){1to16}, %zmm1, %k2 {k3}
+
+vpcmpuq $0, %zmm0, %zmm1, %k2
+vpcmpuq $0, (%rax), %zmm1, %k2
+vpcmpuq $0, (%rax){1to8}, %zmm1, %k2
+vpcmpuq $0, %zmm0, %zmm1, %k2 {k3}
+vpcmpuq $0, (%rax), %zmm1, %k2 {k3}
+vpcmpuq $0, (%rax){1to8}, %zmm1, %k2 {k3}
+
+vpgatherdq (%rax,%ymm1,2), %zmm2 {k1}
+vpgatherdd (%rax,%zmm1,2), %zmm2 {k1}
+vpgatherqq (%rax,%zmm1,2), %zmm2 {k1}
+vpgatherqd (%rax,%zmm1,2), %ymm2 {k1}
+
+vpmovdb %zmm19, %xmm16
+vpmovdb %zmm19, (%rax)
+vpmovdb %zmm19, %xmm16 {k1}
+vpmovdb %zmm19, (%rax) {k1}
+vpmovdb %zmm19, %xmm16 {k1}{z}
+
+vpmovdw %zmm19, %ymm16
+vpmovdw %zmm19, (%rax)
+vpmovdw %zmm19, %ymm16 {k1}
+vpmovdw %zmm19, (%rax) {k1}
+vpmovdw %zmm19, %ymm16 {k1}{z}
+
+vpmovqb %zmm19, %xmm16
+vpmovqb %zmm19, (%rax)
+vpmovqb %zmm19, %xmm16 {k1}
+vpmovqb %zmm19, (%rax) {k1}
+vpmovqb %zmm19, %xmm16 {k1}{z}
+
+vpmovqd %zmm19, %ymm16
+vpmovqd %zmm19, (%rax)
+vpmovqd %zmm19, %ymm16 {k1}
+vpmovqd %zmm19, (%rax) {k1}
+vpmovqd %zmm19, %ymm16 {k1}{z}
+
+vpmovqw %zmm19, %xmm16
+vpmovqw %zmm19, (%rax)
+vpmovqw %zmm19, %xmm16 {k1}
+vpmovqw %zmm19, (%rax) {k1}
+vpmovqw %zmm19, %xmm16 {k1}{z}
+
+vpmovsdb %zmm19, %xmm16
+vpmovsdb %zmm19, (%rax)
+vpmovsdb %zmm19, %xmm16 {k1}
+vpmovsdb %zmm19, (%rax) {k1}
+vpmovsdb %zmm19, %xmm16 {k1}{z}
+
+vpmovsdw %zmm19, %ymm16
+vpmovsdw %zmm19, (%rax)
+vpmovsdw %zmm19, %ymm16 {k1}
+vpmovsdw %zmm19, (%rax) {k1}
+vpmovsdw %zmm19, %ymm16 {k1}{z}
+
+vpmovsqb %zmm19, %xmm16
+vpmovsqb %zmm19, (%rax)
+vpmovsqb %zmm19, %xmm16 {k1}
+vpmovsqb %zmm19, (%rax) {k1}
+vpmovsqb %zmm19, %xmm16 {k1}{z}
+
+vpmovsqd %zmm19, %ymm16
+vpmovsqd %zmm19, (%rax)
+vpmovsqd %zmm19, %ymm16 {k1}
+vpmovsqd %zmm19, (%rax) {k1}
+vpmovsqd %zmm19, %ymm16 {k1}{z}
+
+vpmovsqw %zmm19, %xmm16
+vpmovsqw %zmm19, (%rax)
+vpmovsqw %zmm19, %xmm16 {k1}
+vpmovsqw %zmm19, (%rax) {k1}
+vpmovsqw %zmm19, %xmm16 {k1}{z}
+
+vpmovsxbd %xmm16, %zmm19
+vpmovsxbd (%rax), %zmm19
+vpmovsxbd %xmm16, %zmm19 {k1}
+vpmovsxbd (%rax), %zmm19 {k1}
+vpmovsxbd %xmm16, %zmm19 {z}{k1}
+vpmovsxbd (%rax), %zmm19 {z}{k1}
+
+vpmovsxbq %xmm16, %zmm19
+vpmovsxbq (%rax), %zmm19
+vpmovsxbq %xmm16, %zmm19 {k1}
+vpmovsxbq (%rax), %zmm19 {k1}
+vpmovsxbq %xmm16, %zmm19 {z}{k1}
+vpmovsxbq (%rax), %zmm19 {z}{k1}
+
+vpmovsxdq %ymm16, %zmm19
+vpmovsxdq (%rax), %zmm19
+vpmovsxdq %ymm16, %zmm19 {k1}
+vpmovsxdq (%rax), %zmm19 {k1}
+vpmovsxdq %ymm16, %zmm19 {z}{k1}
+vpmovsxdq (%rax), %zmm19 {z}{k1}
+
+vpmovsxwd %ymm16, %zmm19
+vpmovsxwd (%rax), %zmm19
+vpmovsxwd %ymm16, %zmm19 {k1}
+vpmovsxwd (%rax), %zmm19 {k1}
+vpmovsxwd %ymm16, %zmm19 {z}{k1}
+vpmovsxwd (%rax), %zmm19 {z}{k1}
+
+vpmovsxwq %xmm16, %zmm19
+vpmovsxwq (%rax), %zmm19
+vpmovsxwq %xmm16, %zmm19 {k1}
+vpmovsxwq (%rax), %zmm19 {k1}
+vpmovsxwq %xmm16, %zmm19 {z}{k1}
+vpmovsxwq (%rax), %zmm19 {z}{k1}
+
+vpmovusdb %zmm19, %xmm16
+vpmovusdb %zmm19, (%rax)
+vpmovusdb %zmm19, %xmm16 {k1}
+vpmovusdb %zmm19, (%rax) {k1}
+vpmovusdb %zmm19, %xmm16 {k1}{z}
+
+vpmovusdw %zmm19, %ymm16
+vpmovusdw %zmm19, (%rax)
+vpmovusdw %zmm19, %ymm16 {k1}
+vpmovusdw %zmm19, (%rax) {k1}
+vpmovusdw %zmm19, %ymm16 {k1}{z}
+
+vpmovusqb %zmm19, %xmm16
+vpmovusqb %zmm19, (%rax)
+vpmovusqb %zmm19, %xmm16 {k1}
+vpmovusqb %zmm19, (%rax) {k1}
+vpmovusqb %zmm19, %xmm16 {k1}{z}
+
+vpmovusqd %zmm19, %ymm16
+vpmovusqd %zmm19, (%rax)
+vpmovusqd %zmm19, %ymm16 {k1}
+vpmovusqd %zmm19, (%rax) {k1}
+vpmovusqd %zmm19, %ymm16 {k1}{z}
+
+vpmovusqw %zmm19, %xmm16
+vpmovusqw %zmm19, (%rax)
+vpmovusqw %zmm19, %xmm16 {k1}
+vpmovusqw %zmm19, (%rax) {k1}
+vpmovusqw %zmm19, %xmm16 {k1}{z}
+
+vpmovzxbd %xmm16, %zmm19
+vpmovzxbd (%rax), %zmm19
+vpmovzxbd %xmm16, %zmm19 {k1}
+vpmovzxbd (%rax), %zmm19 {k1}
+vpmovzxbd %xmm16, %zmm19 {z}{k1}
+vpmovzxbd (%rax), %zmm19 {z}{k1}
+
+vpmovzxbq %xmm16, %zmm19
+vpmovzxbq (%rax), %zmm19
+vpmovzxbq %xmm16, %zmm19 {k1}
+vpmovzxbq (%rax), %zmm19 {k1}
+vpmovzxbq %xmm16, %zmm19 {z}{k1}
+vpmovzxbq (%rax), %zmm19 {z}{k1}
+
+vpmovzxdq %ymm16, %zmm19
+vpmovzxdq (%rax), %zmm19
+vpmovzxdq %ymm16, %zmm19 {k1}
+vpmovzxdq (%rax), %zmm19 {k1}
+vpmovzxdq %ymm16, %zmm19 {z}{k1}
+vpmovzxdq (%rax), %zmm19 {z}{k1}
+
+vpmovzxwd %ymm16, %zmm19
+vpmovzxwd (%rax), %zmm19
+vpmovzxwd %ymm16, %zmm19 {k1}
+vpmovzxwd (%rax), %zmm19 {k1}
+vpmovzxwd %ymm16, %zmm19 {z}{k1}
+vpmovzxwd (%rax), %zmm19 {z}{k1}
+
+vpmovzxwq %xmm16, %zmm19
+vpmovzxwq (%rax), %zmm19
+vpmovzxwq %xmm16, %zmm19 {k1}
+vpmovzxwq (%rax), %zmm19 {k1}
+vpmovzxwq %xmm16, %zmm19 {z}{k1}
+vpmovzxwq (%rax), %zmm19 {z}{k1}
+
+vpmulld %zmm16, %zmm17, %zmm19
+vpmulld (%rax), %zmm17, %zmm19
+vpmulld (%rax){1to16}, %zmm17, %zmm19
+vpmulld %zmm16, %zmm17, %zmm19 {k1}
+vpmulld (%rax), %zmm17, %zmm19 {k1}
+vpmulld (%rax){1to16}, %zmm17, %zmm19 {k1}
+vpmulld %zmm16, %zmm17, %zmm19 {z}{k1}
+vpmulld (%rax), %zmm17, %zmm19 {z}{k1}
+vpmulld (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
+
+vpermd %zmm16, %zmm17, %zmm19
+vpermd (%rax), %zmm17, %zmm19
+vpermd (%rax){1to16}, %zmm17, %zmm19
+vpermd %zmm16, %zmm17, %zmm19 {k1}
+vpermd (%rax), %zmm17, %zmm19 {k1}
+vpermd (%rax){1to16}, %zmm17, %zmm19 {k1}
+vpermd %zmm16, %zmm17, %zmm19 {z}{k1}
+vpermd (%rax), %zmm17, %zmm19 {z}{k1}
+vpermd (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
+
+vpermilpd $0, %zmm16, %zmm19
+vpermilpd $0, (%rax), %zmm19
+vpermilpd $0, (%rax){1to8}, %zmm19
+vpermilpd $0, %zmm16, %zmm19 {k1}
+vpermilpd $0, (%rax), %zmm19 {k1}
+vpermilpd $0, (%rax){1to8}, %zmm19 {k1}
+vpermilpd $0, %zmm16, %zmm19 {z}{k1}
+vpermilpd $0, (%rax), %zmm19 {z}{k1}
+vpermilpd $0, (%rax){1to8}, %zmm19 {z}{k1}
+
+vpermilpd %zmm16, %zmm17, %zmm19
+vpermilpd (%rax), %zmm17, %zmm19
+vpermilpd (%rax){1to8}, %zmm17, %zmm19
+vpermilpd %zmm16, %zmm17, %zmm19 {k1}
+vpermilpd (%rax), %zmm17, %zmm19 {k1}
+vpermilpd (%rax){1to8}, %zmm17, %zmm19 {k1}
+vpermilpd %zmm16, %zmm17, %zmm19 {z}{k1}
+vpermilpd (%rax), %zmm17, %zmm19 {z}{k1}
+vpermilpd (%rax){1to8}, %zmm17, %zmm19 {z}{k1}
+
+vpermilps $0, %zmm16, %zmm19
+vpermilps $0, (%rax), %zmm19
+vpermilps $0, (%rax){1to16}, %zmm19
+vpermilps $0, %zmm16, %zmm19 {k1}
+vpermilps $0, (%rax), %zmm19 {k1}
+vpermilps $0, (%rax){1to16}, %zmm19 {k1}
+vpermilps $0, %zmm16, %zmm19 {z}{k1}
+vpermilps $0, (%rax), %zmm19 {z}{k1}
+vpermilps $0, (%rax){1to16}, %zmm19 {z}{k1}
+
+vpermilps %zmm16, %zmm17, %zmm19
+vpermilps (%rax), %zmm17, %zmm19
+vpermilps (%rax){1to16}, %zmm17, %zmm19
+vpermilps %zmm16, %zmm17, %zmm19 {k1}
+vpermilps (%rax), %zmm17, %zmm19 {k1}
+vpermilps (%rax){1to16}, %zmm17, %zmm19 {k1}
+vpermilps %zmm16, %zmm17, %zmm19 {z}{k1}
+vpermilps (%rax), %zmm17, %zmm19 {z}{k1}
+vpermilps (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
+
+vpermpd $0, %zmm16, %zmm19
+vpermpd $0, (%rax), %zmm19
+vpermpd $0, (%rax){1to8}, %zmm19
+vpermpd $0, %zmm16, %zmm19 {k1}
+vpermpd $0, (%rax), %zmm19 {k1}
+vpermpd $0, (%rax){1to8}, %zmm19 {k1}
+vpermpd $0, %zmm16, %zmm19 {z}{k1}
+vpermpd $0, (%rax), %zmm19 {z}{k1}
+vpermpd $0, (%rax){1to8}, %zmm19 {z}{k1}
+
+vpermpd %zmm16, %zmm17, %zmm19
+vpermpd (%rax), %zmm17, %zmm19
+vpermpd (%rax){1to8}, %zmm17, %zmm19
+vpermpd %zmm16, %zmm17, %zmm19 {k1}
+vpermpd (%rax), %zmm17, %zmm19 {k1}
+vpermpd (%rax){1to8}, %zmm17, %zmm19 {k1}
+vpermpd %zmm16, %zmm17, %zmm19 {z}{k1}
+vpermpd (%rax), %zmm17, %zmm19 {z}{k1}
+vpermpd (%rax){1to8}, %zmm17, %zmm19 {z}{k1}
+
+vpermps %zmm16, %zmm17, %zmm19
+vpermps (%rax), %zmm17, %zmm19
+vpermps (%rax){1to16}, %zmm17, %zmm19
+vpermps %zmm16, %zmm17, %zmm19 {k1}
+vpermps (%rax), %zmm17, %zmm19 {k1}
+vpermps (%rax){1to16}, %zmm17, %zmm19 {k1}
+vpermps %zmm16, %zmm17, %zmm19 {z}{k1}
+vpermps (%rax), %zmm17, %zmm19 {z}{k1}
+vpermps (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
+
+vpermq $0, %zmm16, %zmm19
+vpermq $0, (%rax), %zmm19
+vpermq $0, (%rax){1to8}, %zmm19
+vpermq $0, %zmm16, %zmm19 {k1}
+vpermq $0, (%rax), %zmm19 {k1}
+vpermq $0, (%rax){1to8}, %zmm19 {k1}
+vpermq $0, %zmm16, %zmm19 {z}{k1}
+vpermq $0, (%rax), %zmm19 {z}{k1}
+vpermq $0, (%rax){1to8}, %zmm19 {z}{k1}
+
+vpermq %zmm16, %zmm17, %zmm19
+vpermq (%rax), %zmm17, %zmm19
+vpermq (%rax){1to8}, %zmm17, %zmm19
+vpermq %zmm16, %zmm17, %zmm19 {k1}
+vpermq (%rax), %zmm17, %zmm19 {k1}
+vpermq (%rax){1to8}, %zmm17, %zmm19 {k1}
+vpermq %zmm16, %zmm17, %zmm19 {z}{k1}
+vpermq (%rax), %zmm17, %zmm19 {z}{k1}
+vpermq (%rax){1to8}, %zmm17, %zmm19 {z}{k1}
+
+vpscatterdd %zmm1, (%rdx,%zmm0,4) {%k1}
+vpscatterdq %zmm1, (%rdx,%ymm0,4) {%k1}
+vpscatterqd %ymm1, (%rdx,%zmm0,4) {%k1}
+vpscatterqq %zmm1, (%rdx,%zmm0,4) {%k1}
+
+vpshufd $0, %zmm16, %zmm19
+vpshufd $0, (%rax), %zmm19
+vpshufd $0, (%rax){1to16}, %zmm19
+vpshufd $0, %zmm16, %zmm19 {k1}
+vpshufd $0, (%rax), %zmm19 {k1}
+vpshufd $0, (%rax){1to16}, %zmm19 {k1}
+vpshufd $0, %zmm16, %zmm19 {z}{k1}
+vpshufd $0, (%rax), %zmm19 {z}{k1}
+vpshufd $0, (%rax){1to16}, %zmm19 {z}{k1}
+
+vpsubd %zmm16, %zmm17, %zmm19
+vpsubd (%rax), %zmm17, %zmm19
+vpsubd (%rax){1to16}, %zmm17, %zmm19
+vpsubd %zmm16, %zmm17, %zmm19 {k1}
+vpsubd (%rax), %zmm17, %zmm19 {k1}
+vpsubd (%rax){1to16}, %zmm17, %zmm19 {k1}
+vpsubd %zmm16, %zmm17, %zmm19 {z}{k1}
+vpsubd (%rax), %zmm17, %zmm19 {z}{k1}
+vpsubd (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
+
+vpsubq %zmm16, %zmm17, %zmm19
+vpsubq (%rax), %zmm17, %zmm19
+vpsubq (%rax){1to8}, %zmm17, %zmm19
+vpsubq %zmm16, %zmm17, %zmm19 {k1}
+vpsubq (%rax), %zmm17, %zmm19 {k1}
+vpsubq (%rax){1to8}, %zmm17, %zmm19 {k1}
+vpsubq %zmm16, %zmm17, %zmm19 {z}{k1}
+vpsubq (%rax), %zmm17, %zmm19 {z}{k1}
+vpsubq (%rax){1to8}, %zmm17, %zmm19 {z}{k1}
+
+vpunpckhdq %zmm16, %zmm17, %zmm19
+vpunpckhdq (%rax), %zmm17, %zmm19
+vpunpckhdq (%rax){1to16}, %zmm17, %zmm19
+vpunpckhdq %zmm16, %zmm17, %zmm19 {k1}
+vpunpckhdq (%rax), %zmm17, %zmm19 {k1}
+vpunpckhdq (%rax){1to16}, %zmm17, %zmm19 {k1}
+vpunpckhdq %zmm16, %zmm17, %zmm19 {z}{k1}
+vpunpckhdq (%rax), %zmm17, %zmm19 {z}{k1}
+vpunpckhdq (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
+
+vpunpckhqdq %zmm16, %zmm17, %zmm19
+vpunpckhqdq (%rax), %zmm17, %zmm19
+vpunpckhqdq (%rax){1to8}, %zmm17, %zmm19
+vpunpckhqdq %zmm16, %zmm17, %zmm19 {k1}
+vpunpckhqdq (%rax), %zmm17, %zmm19 {k1}
+vpunpckhqdq (%rax){1to8}, %zmm17, %zmm19 {k1}
+vpunpckhqdq %zmm16, %zmm17, %zmm19 {z}{k1}
+vpunpckhqdq (%rax), %zmm17, %zmm19 {z}{k1}
+vpunpckhqdq (%rax){1to8}, %zmm17, %zmm19 {z}{k1}
+
+vpunpckldq %zmm16, %zmm17, %zmm19
+vpunpckldq (%rax), %zmm17, %zmm19
+vpunpckldq (%rax){1to16}, %zmm17, %zmm19
+vpunpckldq %zmm16, %zmm17, %zmm19 {k1}
+vpunpckldq (%rax), %zmm17, %zmm19 {k1}
+vpunpckldq (%rax){1to16}, %zmm17, %zmm19 {k1}
+vpunpckldq %zmm16, %zmm17, %zmm19 {z}{k1}
+vpunpckldq (%rax), %zmm17, %zmm19 {z}{k1}
+vpunpckldq (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
+
+vpunpcklqdq %zmm16, %zmm17, %zmm19
+vpunpcklqdq (%rax), %zmm17, %zmm19
+vpunpcklqdq (%rax){1to8}, %zmm17, %zmm19
+vpunpcklqdq %zmm16, %zmm17, %zmm19 {k1}
+vpunpcklqdq (%rax), %zmm17, %zmm19 {k1}
+vpunpcklqdq (%rax){1to8}, %zmm17, %zmm19 {k1}
+vpunpcklqdq %zmm16, %zmm17, %zmm19 {z}{k1}
+vpunpcklqdq (%rax), %zmm17, %zmm19 {z}{k1}
+vpunpcklqdq (%rax){1to8}, %zmm17, %zmm19 {z}{k1}
+
+vscatterdps %zmm1, (%rdx,%zmm0,4) {%k1}
+vscatterdpd %zmm1, (%rdx,%ymm0,4) {%k1}
+vscatterqps %ymm1, (%rdx,%zmm0,4) {%k1}
+vscatterqpd %zmm1, (%rdx,%zmm0,4) {%k1}
+
+vshuff32x4 $0, %zmm16, %zmm17, %zmm19
+vshuff32x4 $0, (%rax), %zmm17, %zmm19
+vshuff32x4 $0, (%rax){1to16}, %zmm17, %zmm19
+vshuff32x4 $0, %zmm16, %zmm17, %zmm19 {k1}
+vshuff32x4 $0, (%rax), %zmm17, %zmm19 {k1}
+vshuff32x4 $0, (%rax){1to16}, %zmm17, %zmm19 {k1}
+vshuff32x4 $0, %zmm16, %zmm17, %zmm19 {z}{k1}
+vshuff32x4 $0, (%rax), %zmm17, %zmm19 {z}{k1}
+vshuff32x4 $0, (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
+
+vshuff64x2 $0, %zmm16, %zmm17, %zmm19
+vshuff64x2 $0, (%rax), %zmm17, %zmm19
+vshuff64x2 $0, (%rax){1to8}, %zmm17, %zmm19
+vshuff64x2 $0, %zmm16, %zmm17, %zmm19 {k1}
+vshuff64x2 $0, (%rax), %zmm17, %zmm19 {k1}
+vshuff64x2 $0, (%rax){1to8}, %zmm17, %zmm19 {k1}
+vshuff64x2 $0, %zmm16, %zmm17, %zmm19 {z}{k1}
+vshuff64x2 $0, (%rax), %zmm17, %zmm19 {z}{k1}
+vshuff64x2 $0, (%rax){1to8}, %zmm17, %zmm19 {z}{k1}
+
+vshufi32x4 $0, %zmm16, %zmm17, %zmm19
+vshufi32x4 $0, (%rax), %zmm17, %zmm19
+vshufi32x4 $0, (%rax){1to16}, %zmm17, %zmm19
+vshufi32x4 $0, %zmm16, %zmm17, %zmm19 {k1}
+vshufi32x4 $0, (%rax), %zmm17, %zmm19 {k1}
+vshufi32x4 $0, (%rax){1to16}, %zmm17, %zmm19 {k1}
+vshufi32x4 $0, %zmm16, %zmm17, %zmm19 {z}{k1}
+vshufi32x4 $0, (%rax), %zmm17, %zmm19 {z}{k1}
+vshufi32x4 $0, (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
+
+vshufi64x2 $0, %zmm16, %zmm17, %zmm19
+vshufi64x2 $0, (%rax), %zmm17, %zmm19
+vshufi64x2 $0, (%rax){1to8}, %zmm17, %zmm19
+vshufi64x2 $0, %zmm16, %zmm17, %zmm19 {k1}
+vshufi64x2 $0, (%rax), %zmm17, %zmm19 {k1}
+vshufi64x2 $0, (%rax){1to8}, %zmm17, %zmm19 {k1}
+vshufi64x2 $0, %zmm16, %zmm17, %zmm19 {z}{k1}
+vshufi64x2 $0, (%rax), %zmm17, %zmm19 {z}{k1}
+vshufi64x2 $0, (%rax){1to8}, %zmm17, %zmm19 {z}{k1}
+
+vsqrtpd %zmm16, %zmm19
+vsqrtpd (%rax), %zmm19
+vsqrtpd (%rax){1to8}, %zmm19
+vsqrtpd %zmm16, %zmm19 {k1}
+vsqrtpd (%rax), %zmm19 {k1}
+vsqrtpd (%rax){1to8}, %zmm19 {k1}
+vsqrtpd %zmm16, %zmm19 {z}{k1}
+vsqrtpd (%rax), %zmm19 {z}{k1}
+vsqrtpd (%rax){1to8}, %zmm19 {z}{k1}
+
+vsqrtps %zmm16, %zmm19
+vsqrtps (%rax), %zmm19
+vsqrtps (%rax){1to16}, %zmm19
+vsqrtps %zmm16, %zmm19 {k1}
+vsqrtps (%rax), %zmm19 {k1}
+vsqrtps (%rax){1to16}, %zmm19 {k1}
+vsqrtps %zmm16, %zmm19 {z}{k1}
+vsqrtps (%rax), %zmm19 {z}{k1}
+vsqrtps (%rax){1to16}, %zmm19 {z}{k1}
+
+vsqrtsd %xmm16, %xmm17, %xmm19
+vsqrtsd (%rax), %xmm17, %xmm19
+vsqrtsd %xmm16, %xmm17, %xmm19 {k1}
+vsqrtsd (%rax), %xmm17, %xmm19 {k1}
+vsqrtsd %xmm16, %xmm17, %xmm19 {z}{k1}
+vsqrtsd (%rax), %xmm17, %xmm19 {z}{k1}
+
+vsqrtss %xmm16, %xmm17, %xmm19
+vsqrtss (%rax), %xmm17, %xmm19
+vsqrtss %xmm16, %xmm17, %xmm19 {k1}
+vsqrtss (%rax), %xmm17, %xmm19 {k1}
+vsqrtss %xmm16, %xmm17, %xmm19 {z}{k1}
+vsqrtss (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpsubd %zmm16, %zmm17, %zmm19
+vpsubd (%rax), %zmm17, %zmm19
+vpsubd (%rax){1to16}, %zmm17, %zmm19
+vpsubd %zmm16, %zmm17, %zmm19 {k1}
+vpsubd (%rax), %zmm17, %zmm19 {k1}
+vpsubd (%rax){1to16}, %zmm17, %zmm19 {k1}
+vpsubd %zmm16, %zmm17, %zmm19 {z}{k1}
+vpsubd (%rax), %zmm17, %zmm19 {z}{k1}
+vpsubd (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
+
+vpsubq %zmm16, %zmm17, %zmm19
+vpsubq (%rax), %zmm17, %zmm19
+vpsubq (%rax){1to8}, %zmm17, %zmm19
+vpsubq %zmm16, %zmm17, %zmm19 {k1}
+vpsubq (%rax), %zmm17, %zmm19 {k1}
+vpsubq (%rax){1to8}, %zmm17, %zmm19 {k1}
+vpsubq %zmm16, %zmm17, %zmm19 {z}{k1}
+vpsubq (%rax), %zmm17, %zmm19 {z}{k1}
+vpsubq (%rax){1to8}, %zmm17, %zmm19 {z}{k1}
+
+vptestmd %zmm0, %zmm1, %k2
+vptestmd (%rax), %zmm1, %k2
+vptestmd (%rax){1to16}, %zmm1, %k2
+vptestmd %zmm0, %zmm1, %k2 {k3}
+vptestmd (%rax), %zmm1, %k2 {k3}
+vptestmd (%rax){1to16}, %zmm1, %k2 {k3}
+
+vptestmq %zmm0, %zmm1, %k2
+vptestmq (%rax), %zmm1, %k2
+vptestmq (%rax){1to8}, %zmm1, %k2
+vptestmq %zmm0, %zmm1, %k2 {k3}
+vptestmq (%rax), %zmm1, %k2 {k3}
+vptestmq (%rax){1to8}, %zmm1, %k2 {k3}
+
+vptestnmd %zmm0, %zmm1, %k2
+vptestnmd (%rax), %zmm1, %k2
+vptestnmd (%rax){1to16}, %zmm1, %k2
+vptestnmd %zmm0, %zmm1, %k2 {k3}
+vptestnmd (%rax), %zmm1, %k2 {k3}
+vptestnmd (%rax){1to16}, %zmm1, %k2 {k3}
+
+vptestnmq %zmm0, %zmm1, %k2
+vptestnmq (%rax), %zmm1, %k2
+vptestnmq (%rax){1to8}, %zmm1, %k2
+vptestnmq %zmm0, %zmm1, %k2 {k3}
+vptestnmq (%rax), %zmm1, %k2 {k3}
+vptestnmq (%rax){1to8}, %zmm1, %k2 {k3}
+
+vsubpd %zmm16, %zmm17, %zmm19
+vsubpd (%rax), %zmm17, %zmm19
+vsubpd (%rax){1to8}, %zmm17, %zmm19
+vsubpd %zmm16, %zmm17, %zmm19 {k1}
+vsubpd (%rax), %zmm17, %zmm19 {k1}
+vsubpd (%rax){1to8}, %zmm17, %zmm19 {k1}
+vsubpd %zmm16, %zmm17, %zmm19 {z}{k1}
+vsubpd (%rax), %zmm17, %zmm19 {z}{k1}
+vsubpd (%rax){1to8}, %zmm17, %zmm19 {z}{k1}
+
+vsubps %zmm16, %zmm17, %zmm19
+vsubps (%rax), %zmm17, %zmm19
+vsubps (%rax){1to16}, %zmm17, %zmm19
+vsubps %zmm16, %zmm17, %zmm19 {k1}
+vsubps (%rax), %zmm17, %zmm19 {k1}
+vsubps (%rax){1to16}, %zmm17, %zmm19 {k1}
+vsubps %zmm16, %zmm17, %zmm19 {z}{k1}
+vsubps (%rax), %zmm17, %zmm19 {z}{k1}
+vsubps (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
+
+vucomiss %xmm16, %xmm17
+vucomiss (%rax), %xmm17
+
+vunpckhpd %zmm16, %zmm17, %zmm19
+vunpckhpd (%rax), %zmm17, %zmm19
+vunpckhpd (%rax){1to8}, %zmm17, %zmm19
+vunpckhpd %zmm16, %zmm17, %zmm19 {k1}
+vunpckhpd (%rax), %zmm17, %zmm19 {k1}
+vunpckhpd (%rax){1to8}, %zmm17, %zmm19 {k1}
+vunpckhpd %zmm16, %zmm17, %zmm19 {z}{k1}
+vunpckhpd (%rax), %zmm17, %zmm19 {z}{k1}
+vunpckhpd (%rax){1to8}, %zmm17, %zmm19 {z}{k1}
+
+vunpckhps %zmm16, %zmm17, %zmm19
+vunpckhps (%rax), %zmm17, %zmm19
+vunpckhps (%rax){1to16}, %zmm17, %zmm19
+vunpckhps %zmm16, %zmm17, %zmm19 {k1}
+vunpckhps (%rax), %zmm17, %zmm19 {k1}
+vunpckhps (%rax){1to16}, %zmm17, %zmm19 {k1}
+vunpckhps %zmm16, %zmm17, %zmm19 {z}{k1}
+vunpckhps (%rax), %zmm17, %zmm19 {z}{k1}
+vunpckhps (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
+
+vunpcklpd %zmm16, %zmm17, %zmm19
+vunpcklpd (%rax), %zmm17, %zmm19
+vunpcklpd (%rax){1to8}, %zmm17, %zmm19
+vunpcklpd %zmm16, %zmm17, %zmm19 {k1}
+vunpcklpd (%rax), %zmm17, %zmm19 {k1}
+vunpcklpd (%rax){1to8}, %zmm17, %zmm19 {k1}
+vunpcklpd %zmm16, %zmm17, %zmm19 {z}{k1}
+vunpcklpd (%rax), %zmm17, %zmm19 {z}{k1}
+vunpcklpd (%rax){1to8}, %zmm17, %zmm19 {z}{k1}
+
+vunpcklps %zmm16, %zmm17, %zmm19
+vunpcklps (%rax), %zmm17, %zmm19
+vunpcklps (%rax){1to16}, %zmm17, %zmm19
+vunpcklps %zmm16, %zmm17, %zmm19 {k1}
+vunpcklps (%rax), %zmm17, %zmm19 {k1}
+vunpcklps (%rax){1to16}, %zmm17, %zmm19 {k1}
+vunpcklps %zmm16, %zmm17, %zmm19 {z}{k1}
+vunpcklps (%rax), %zmm17, %zmm19 {z}{k1}
+vunpcklps (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.25 kandw %k0, %k1, %k2
+# CHECK-NEXT: 1 1 0.25 kandnw %k0, %k1, %k2
+# CHECK-NEXT: 1 1 0.25 knotw %k0, %k2
+# CHECK-NEXT: 1 1 0.25 korw %k0, %k1, %k2
+# CHECK-NEXT: 1 1 0.25 kxnorw %k0, %k1, %k2
+# CHECK-NEXT: 1 1 0.25 kxorw %k0, %k1, %k2
+# CHECK-NEXT: 1 1 0.50 kshiftlw $2, %k1, %k2
+# CHECK-NEXT: 1 1 0.50 kshiftrw $2, %k1, %k2
+# CHECK-NEXT: 1 1 0.50 kunpckbw %k0, %k1, %k2
+# CHECK-NEXT: 1 3 1.00 vaddpd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vaddpd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vaddpd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 1 4 0.50 vaddpd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vaddpd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vaddpd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 3 1.00 vaddpd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vaddpd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vaddpd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 1.00 vaddps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vaddps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vaddps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 1 4 0.50 vaddps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vaddps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vaddps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 3 1.00 vaddps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vaddps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vaddps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 8 4 4.00 valignd $1, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 8 11 4.00 * valignd $1, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 8 1.00 * valignd $1, (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 8 4 4.00 valignd $1, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 8 11 4.00 * valignd $1, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 1.00 * valignd $1, (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 8 4 4.00 valignd $1, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 8 11 4.00 * valignd $1, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 1.00 * valignd $1, (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 8 4 4.00 valignq $1, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 8 11 4.00 * valignq $1, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 8 1.00 * valignq $1, (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 8 4 4.00 valignq $1, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 8 11 4.00 * valignq $1, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 1.00 * valignq $1, (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 8 4 4.00 valignq $1, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 8 11 4.00 * valignq $1, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 1.00 * valignq $1, (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vbroadcastf32x4 (%rax), %zmm19
+# CHECK-NEXT: 1 8 0.50 * vbroadcastf32x4 (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vbroadcastf32x4 (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vbroadcastf64x4 (%rax), %zmm19
+# CHECK-NEXT: 1 8 0.50 * vbroadcastf64x4 (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vbroadcastf64x4 (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vbroadcasti32x4 (%rax), %zmm19
+# CHECK-NEXT: 1 8 0.50 * vbroadcasti32x4 (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vbroadcasti32x4 (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vbroadcasti64x4 (%rax), %zmm19
+# CHECK-NEXT: 1 8 0.50 * vbroadcasti64x4 (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vbroadcasti64x4 (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 5 4.00 vbroadcastsd %xmm16, %zmm19
+# CHECK-NEXT: 2 12 4.00 * vbroadcastsd (%rax), %zmm19
+# CHECK-NEXT: 2 4 4.00 vbroadcastsd %xmm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 11 4.00 * vbroadcastsd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 2 5 4.00 vbroadcastsd %xmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 12 4.00 * vbroadcastsd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 5 4.00 vbroadcastss %xmm16, %zmm19
+# CHECK-NEXT: 2 12 4.00 * vbroadcastss (%rax), %zmm19
+# CHECK-NEXT: 2 4 4.00 vbroadcastss %xmm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 11 4.00 * vbroadcastss (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 2 5 4.00 vbroadcastss %xmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 12 4.00 * vbroadcastss (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vcmpeqpd %zmm0, %zmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vcmpeqpd (%rax), %zmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vcmpeqpd (%rax){1to8}, %zmm1, %k2
+# CHECK-NEXT: 4 5 5.00 vcmpeqpd %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 4 12 5.00 * vcmpeqpd (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.50 * vcmpeqpd (%rax){1to8}, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.50 vcmpeqps %zmm0, %zmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vcmpeqps (%rax), %zmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vcmpeqps (%rax){1to16}, %zmm1, %k2
+# CHECK-NEXT: 4 5 5.00 vcmpeqps %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 4 12 5.00 * vcmpeqps (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.50 * vcmpeqps (%rax){1to16}, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.50 vcmpeqsd %xmm0, %xmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vcmpeqsd (%rax), %xmm1, %k2
+# CHECK-NEXT: 4 5 5.00 vcmpeqsd %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 4 12 5.00 * vcmpeqsd (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.50 vcmpeqss %xmm0, %xmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vcmpeqss (%rax), %xmm1, %k2
+# CHECK-NEXT: 4 5 5.00 vcmpeqss %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 4 12 5.00 * vcmpeqss (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 2 1 0.50 vcomiss %xmm16, %xmm17
+# CHECK-NEXT: 2 8 0.50 * vcomiss (%rax), %xmm17
+# CHECK-NEXT: 2 5 1.00 vcvtdq2pd %ymm16, %zmm19
+# CHECK-NEXT: 2 12 1.00 * vcvtdq2pd (%rax), %zmm19
+# CHECK-NEXT: 2 12 1.00 * vcvtdq2pd (%rax){1to8}, %zmm19
+# CHECK-NEXT: 2 5 1.00 vcvtdq2pd %ymm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtdq2pd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtdq2pd (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: 2 5 1.00 vcvtdq2pd %ymm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 12 1.00 * vcvtdq2pd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 12 1.00 * vcvtdq2pd (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 4 1.00 vcvtdq2ps %zmm16, %zmm19
+# CHECK-NEXT: 2 11 1.00 * vcvtdq2ps (%rax), %zmm19
+# CHECK-NEXT: 2 11 1.00 * vcvtdq2ps (%rax){1to16}, %zmm19
+# CHECK-NEXT: 2 5 1.00 vcvtdq2ps %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtdq2ps (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtdq2ps (%rax){1to16}, %zmm19 {%k1}
+# CHECK-NEXT: 2 4 1.00 vcvtdq2ps %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vcvtdq2ps (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vcvtdq2ps (%rax){1to16}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 8 1.00 vcvtpd2dq %zmm16, %ymm19
+# CHECK-NEXT: 2 15 1.00 * vcvtpd2dq (%rax), %ymm19
+# CHECK-NEXT: 2 15 1.00 * vcvtpd2dq (%rax){1to8}, %ymm19
+# CHECK-NEXT: 2 5 1.00 vcvtpd2dq %zmm16, %ymm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtpd2dq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtpd2dq (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: 2 8 1.00 vcvtpd2dq %zmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 15 1.00 * vcvtpd2dq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 15 1.00 * vcvtpd2dq (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 8 1.00 vcvtpd2udq %zmm16, %ymm19
+# CHECK-NEXT: 2 15 1.00 * vcvtpd2udq (%rax), %ymm19
+# CHECK-NEXT: 2 15 1.00 * vcvtpd2udq (%rax){1to8}, %ymm19
+# CHECK-NEXT: 2 5 1.00 vcvtpd2udq %zmm16, %ymm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtpd2udq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtpd2udq (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: 2 8 1.00 vcvtpd2udq %zmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 15 1.00 * vcvtpd2udq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 15 1.00 * vcvtpd2udq (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 8 1.00 vcvttpd2dq %zmm16, %ymm19
+# CHECK-NEXT: 2 15 1.00 * vcvttpd2dq (%rax), %ymm19
+# CHECK-NEXT: 2 15 1.00 * vcvttpd2dq (%rax){1to8}, %ymm19
+# CHECK-NEXT: 2 5 1.00 vcvttpd2dq %zmm16, %ymm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvttpd2dq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvttpd2dq (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: 2 8 1.00 vcvttpd2dq %zmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 15 1.00 * vcvttpd2dq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 15 1.00 * vcvttpd2dq (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 8 1.00 vcvttpd2udq %zmm16, %ymm19
+# CHECK-NEXT: 2 15 1.00 * vcvttpd2udq (%rax), %ymm19
+# CHECK-NEXT: 2 15 1.00 * vcvttpd2udq (%rax){1to8}, %ymm19
+# CHECK-NEXT: 2 5 1.00 vcvttpd2udq %zmm16, %ymm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvttpd2udq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvttpd2udq (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: 2 8 1.00 vcvttpd2udq %zmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 15 1.00 * vcvttpd2udq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 15 1.00 * vcvttpd2udq (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 8 1.00 vcvtpd2ps %zmm16, %ymm19
+# CHECK-NEXT: 2 15 1.00 * vcvtpd2ps (%rax), %ymm19
+# CHECK-NEXT: 2 15 1.00 * vcvtpd2ps (%rax){1to8}, %ymm19
+# CHECK-NEXT: 2 5 1.00 vcvtpd2ps %zmm16, %ymm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtpd2ps (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtpd2ps (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: 2 8 1.00 vcvtpd2ps %zmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 15 1.00 * vcvtpd2ps (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 15 1.00 * vcvtpd2ps (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 4 1.00 vcvtps2dq %zmm16, %zmm19
+# CHECK-NEXT: 2 11 1.00 * vcvtps2dq (%rax), %zmm19
+# CHECK-NEXT: 2 11 1.00 * vcvtps2dq (%rax){1to16}, %zmm19
+# CHECK-NEXT: 2 5 1.00 vcvtps2dq %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtps2dq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtps2dq (%rax){1to16}, %zmm19 {%k1}
+# CHECK-NEXT: 2 4 1.00 vcvtps2dq %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vcvtps2dq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vcvtps2dq (%rax){1to16}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 4 1.00 vcvttps2dq %zmm16, %zmm19
+# CHECK-NEXT: 2 11 1.00 * vcvttps2dq (%rax), %zmm19
+# CHECK-NEXT: 2 11 1.00 * vcvttps2dq (%rax){1to16}, %zmm19
+# CHECK-NEXT: 2 5 1.00 vcvttps2dq %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvttps2dq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvttps2dq (%rax){1to16}, %zmm19 {%k1}
+# CHECK-NEXT: 2 4 1.00 vcvttps2dq %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vcvttps2dq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vcvttps2dq (%rax){1to16}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 5 1.00 vcvtps2pd %ymm16, %zmm19
+# CHECK-NEXT: 2 12 1.00 * vcvtps2pd (%rax), %zmm19
+# CHECK-NEXT: 2 12 1.00 * vcvtps2pd (%rax){1to8}, %zmm19
+# CHECK-NEXT: 2 5 1.00 vcvtps2pd %ymm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtps2pd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtps2pd (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: 2 5 1.00 vcvtps2pd %ymm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 12 1.00 * vcvtps2pd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 12 1.00 * vcvtps2pd (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 2 1.00 vcvtsd2usi %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 vcvtsd2usi %xmm0, %rcx
+# CHECK-NEXT: 2 9 1.00 * vcvtsd2usi (%rax), %ecx
+# CHECK-NEXT: 2 9 1.00 * vcvtsd2usi (%rax), %rcx
+# CHECK-NEXT: 2 2 1.00 vcvtss2usi %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 vcvtss2usi %xmm0, %rcx
+# CHECK-NEXT: 2 9 1.00 * vcvtss2usi (%rax), %ecx
+# CHECK-NEXT: 2 9 1.00 * vcvtss2usi (%rax), %rcx
+# CHECK-NEXT: 2 4 1.00 vcvtps2udq %zmm16, %zmm19
+# CHECK-NEXT: 2 11 1.00 * vcvtps2udq (%rax), %zmm19
+# CHECK-NEXT: 2 11 1.00 * vcvtps2udq (%rax){1to16}, %zmm19
+# CHECK-NEXT: 2 5 1.00 vcvtps2udq %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtps2udq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtps2udq (%rax){1to16}, %zmm19 {%k1}
+# CHECK-NEXT: 2 4 1.00 vcvtps2udq %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vcvtps2udq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vcvtps2udq (%rax){1to16}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 4 1.00 vcvttps2udq %zmm16, %zmm19
+# CHECK-NEXT: 2 11 1.00 * vcvttps2udq (%rax), %zmm19
+# CHECK-NEXT: 2 11 1.00 * vcvttps2udq (%rax){1to16}, %zmm19
+# CHECK-NEXT: 2 5 1.00 vcvttps2udq %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvttps2udq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvttps2udq (%rax){1to16}, %zmm19 {%k1}
+# CHECK-NEXT: 2 4 1.00 vcvttps2udq %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vcvttps2udq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vcvttps2udq (%rax){1to16}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 2 1.00 vcvttsd2usi %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 vcvttsd2usi %xmm0, %rcx
+# CHECK-NEXT: 2 9 1.00 * vcvttsd2usi (%rax), %ecx
+# CHECK-NEXT: 2 9 1.00 * vcvttsd2usi (%rax), %rcx
+# CHECK-NEXT: 2 2 1.00 vcvttss2usi %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 vcvttss2usi %xmm0, %rcx
+# CHECK-NEXT: 2 9 1.00 * vcvttss2usi (%rax), %ecx
+# CHECK-NEXT: 2 9 1.00 * vcvttss2usi (%rax), %rcx
+# CHECK-NEXT: 2 5 1.00 vcvtudq2pd %ymm16, %zmm19
+# CHECK-NEXT: 2 12 1.00 * vcvtudq2pd (%rax), %zmm19
+# CHECK-NEXT: 2 12 1.00 * vcvtudq2pd (%rax){1to8}, %zmm19
+# CHECK-NEXT: 2 5 1.00 vcvtudq2pd %ymm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtudq2pd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtudq2pd (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: 2 5 1.00 vcvtudq2pd %ymm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 12 1.00 * vcvtudq2pd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 12 1.00 * vcvtudq2pd (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 4 1.00 vcvtudq2ps %zmm16, %zmm19
+# CHECK-NEXT: 2 11 1.00 * vcvtudq2ps (%rax), %zmm19
+# CHECK-NEXT: 2 11 1.00 * vcvtudq2ps (%rax){1to16}, %zmm19
+# CHECK-NEXT: 2 5 1.00 vcvtudq2ps %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtudq2ps (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtudq2ps (%rax){1to16}, %zmm19 {%k1}
+# CHECK-NEXT: 2 4 1.00 vcvtudq2ps %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vcvtudq2ps (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vcvtudq2ps (%rax){1to16}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvtusi2sd %ecx, %xmm0, %xmm2
+# CHECK-NEXT: 2 4 1.50 vcvtusi2sd %rcx, %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vcvtusi2sdl (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 11 1.50 * vcvtusi2sdq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 1 4 0.50 vcvtusi2ss %ecx, %xmm0, %xmm2
+# CHECK-NEXT: 2 4 1.50 vcvtusi2ss %rcx, %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vcvtusi2ssl (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 11 1.50 * vcvtusi2ssq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 16 12.00 vdivpd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 2 23 12.00 * vdivpd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 2 23 12.00 * vdivpd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 2 16 12.00 vdivpd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 23 12.00 * vdivpd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 23 12.00 * vdivpd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 16 12.00 vdivpd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 23 12.00 * vdivpd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 23 12.00 * vdivpd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 18 9.00 vdivps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 2 25 9.00 * vdivps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 2 25 9.00 * vdivps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 2 18 9.00 vdivps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 25 9.00 * vdivps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 25 9.00 * vdivps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 18 9.00 vdivps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 25 9.00 * vdivps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 25 9.00 * vdivps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 2.00 {evex} vextractps $1, %xmm0, %ecx
+# CHECK-NEXT: 1 3 2.00 * {evex} vextractps $1, %xmm0, (%rax)
+# CHECK-NEXT: 2 4 1.00 vfmadd132pd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 2 11 1.00 * vfmadd132pd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 2 11 1.00 * vfmadd132pd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 2 5 1.00 vfmadd132pd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vfmadd132pd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vfmadd132pd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 4 1.00 vfmadd132pd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vfmadd132pd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vfmadd132pd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 4 1.00 vfmadd213pd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 2 11 1.00 * vfmadd213pd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 2 11 1.00 * vfmadd213pd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 2 5 1.00 vfmadd213pd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vfmadd213pd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vfmadd213pd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 4 1.00 vfmadd213pd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vfmadd213pd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vfmadd213pd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 4 1.00 vfmadd231pd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 2 11 1.00 * vfmadd231pd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 2 11 1.00 * vfmadd231pd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 2 5 1.00 vfmadd231pd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vfmadd231pd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vfmadd231pd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 4 1.00 vfmadd231pd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vfmadd231pd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vfmadd231pd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 4 1.00 vfmadd132ps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 2 11 1.00 * vfmadd132ps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 2 11 1.00 * vfmadd132ps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 2 5 1.00 vfmadd132ps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vfmadd132ps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vfmadd132ps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 4 1.00 vfmadd132ps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vfmadd132ps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vfmadd132ps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 4 1.00 vfmadd213ps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 2 11 1.00 * vfmadd213ps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 2 11 1.00 * vfmadd213ps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 2 5 1.00 vfmadd213ps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vfmadd213ps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vfmadd213ps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 4 1.00 vfmadd213ps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vfmadd213ps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vfmadd213ps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 4 1.00 vfmadd231ps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 2 11 1.00 * vfmadd231ps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 2 11 1.00 * vfmadd231ps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 2 5 1.00 vfmadd231ps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vfmadd231ps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vfmadd231ps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 4 1.00 vfmadd231ps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vfmadd231ps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vfmadd231ps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 8 0.33 * vgatherdpd (%rax,%ymm1,2), %zmm2 {%k1}
+# CHECK-NEXT: 2 8 0.33 * vgatherdps (%rax,%zmm1,2), %zmm2 {%k1}
+# CHECK-NEXT: 2 8 0.33 * vgatherqpd (%rax,%zmm1,2), %zmm2 {%k1}
+# CHECK-NEXT: 2 8 0.33 * vgatherqps (%rax,%zmm1,2), %ymm2 {%k1}
+# CHECK-NEXT: 1 1 0.50 vmaxpd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vmaxpd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vmaxpd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 2 2 1.00 vmaxpd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 9 1.00 * vmaxpd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 9 1.00 * vmaxpd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vmaxpd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vmaxpd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vmaxpd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vmaxps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vmaxps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vmaxps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 2 2 1.00 vmaxps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 9 1.00 * vmaxps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 9 1.00 * vmaxps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vmaxps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vmaxps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vmaxps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vminpd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vminpd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vminpd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 2 2 1.00 vminpd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 9 1.00 * vminpd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 9 1.00 * vminpd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vminpd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vminpd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vminpd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vminps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vminps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vminps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 2 2 1.00 vminps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 9 1.00 * vminps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 9 1.00 * vminps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vminps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vminps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vminps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 0 0.25 vmovapd %zmm16, %zmm19
+# CHECK-NEXT: 1 8 0.33 * vmovapd (%rax), %zmm19
+# CHECK-NEXT: 1 1 0.33 * vmovapd %zmm16, (%rax)
+# CHECK-NEXT: 1 0 0.25 vmovapd %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vmovapd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.33 * vmovapd %zmm16, (%rax) {%k1}
+# CHECK-NEXT: 1 0 0.25 vmovapd %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vmovapd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 0 0.25 vmovaps %zmm16, %zmm19
+# CHECK-NEXT: 1 8 0.33 * vmovaps (%rax), %zmm19
+# CHECK-NEXT: 1 1 0.33 * vmovaps %zmm16, (%rax)
+# CHECK-NEXT: 1 0 0.25 vmovaps %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vmovaps (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.33 * vmovaps %zmm16, (%rax) {%k1}
+# CHECK-NEXT: 1 0 0.25 vmovaps %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vmovaps (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 1.00 vmovddup %zmm16, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vmovddup (%rax), %zmm19
+# CHECK-NEXT: 1 1 1.00 vmovddup %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 1.00 * vmovddup (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 1 1.00 vmovddup %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 1.00 * vmovddup (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 0 0.25 vmovdqa32 %zmm16, %zmm19
+# CHECK-NEXT: 1 8 0.33 * vmovdqa32 (%rax), %zmm19
+# CHECK-NEXT: 1 1 0.33 * vmovdqa32 %zmm16, (%rax)
+# CHECK-NEXT: 1 0 0.25 vmovdqa32 %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vmovdqa32 (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.33 * vmovdqa32 %zmm16, (%rax) {%k1}
+# CHECK-NEXT: 1 0 0.25 vmovdqa32 %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vmovdqa32 (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 0 0.25 vmovdqa64 %zmm16, %zmm19
+# CHECK-NEXT: 1 8 0.33 * vmovdqa64 (%rax), %zmm19
+# CHECK-NEXT: 1 1 0.33 * vmovdqa64 %zmm16, (%rax)
+# CHECK-NEXT: 1 0 0.25 vmovdqa64 %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vmovdqa64 (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.33 * vmovdqa64 %zmm16, (%rax) {%k1}
+# CHECK-NEXT: 1 0 0.25 vmovdqa64 %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vmovdqa64 (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 0 0.25 vmovdqu32 %zmm16, %zmm19
+# CHECK-NEXT: 1 8 0.33 * vmovdqu32 (%rax), %zmm19
+# CHECK-NEXT: 1 1 0.33 * vmovdqu32 %zmm16, (%rax)
+# CHECK-NEXT: 1 0 0.25 vmovdqu32 %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vmovdqu32 (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.33 * vmovdqu32 %zmm16, (%rax) {%k1}
+# CHECK-NEXT: 1 0 0.25 vmovdqu32 %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vmovdqu32 (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 0 0.25 vmovdqu64 %zmm16, %zmm19
+# CHECK-NEXT: 1 8 0.33 * vmovdqu64 (%rax), %zmm19
+# CHECK-NEXT: 1 1 0.33 * vmovdqu64 %zmm16, (%rax)
+# CHECK-NEXT: 1 0 0.25 vmovdqu64 %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vmovdqu64 (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.33 * vmovdqu64 %zmm16, (%rax) {%k1}
+# CHECK-NEXT: 1 0 0.25 vmovdqu64 %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vmovdqu64 (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vmovntdqa (%rax), %zmm0
+# CHECK-NEXT: 1 1 1.00 vmovshdup %zmm16, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vmovshdup (%rax), %zmm19
+# CHECK-NEXT: 1 1 1.00 vmovshdup %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 1.00 * vmovshdup (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 1 1.00 vmovshdup %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 1.00 * vmovshdup (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 1.00 vmovsldup %zmm16, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vmovsldup (%rax), %zmm19
+# CHECK-NEXT: 1 1 1.00 vmovsldup %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 1.00 * vmovsldup (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 1 1.00 vmovsldup %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 1.00 * vmovsldup (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 0 0.25 vmovupd %zmm16, %zmm19
+# CHECK-NEXT: 1 8 0.33 * vmovupd (%rax), %zmm19
+# CHECK-NEXT: 1 1 0.33 * vmovupd %zmm16, (%rax)
+# CHECK-NEXT: 1 0 0.25 vmovupd %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vmovupd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.33 * vmovupd %zmm16, (%rax) {%k1}
+# CHECK-NEXT: 1 0 0.25 vmovupd %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vmovupd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 0 0.25 vmovups %zmm16, %zmm19
+# CHECK-NEXT: 1 8 0.33 * vmovups (%rax), %zmm19
+# CHECK-NEXT: 1 1 0.33 * vmovups %zmm16, (%rax)
+# CHECK-NEXT: 1 0 0.25 vmovups %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vmovups (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.33 * vmovups %zmm16, (%rax) {%k1}
+# CHECK-NEXT: 1 0 0.25 vmovups %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vmovups (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 1.00 vmulpd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vmulpd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vmulpd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 1 4 1.00 vmulpd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vmulpd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vmulpd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 3 1.00 vmulpd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vmulpd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vmulpd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 1.00 vmulps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vmulps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vmulps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 1 4 1.00 vmulps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vmulps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vmulps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 3 1.00 vmulps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vmulps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vmulps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpabsd %zmm16, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpabsd (%rax), %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpabsd (%rax){1to16}, %zmm19
+# CHECK-NEXT: 1 1 0.50 vpabsd %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpabsd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpabsd (%rax){1to16}, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpabsd %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpabsd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpabsd (%rax){1to16}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpabsq %zmm16, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpabsq (%rax), %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpabsq (%rax){1to8}, %zmm19
+# CHECK-NEXT: 1 1 0.50 vpabsq %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpabsq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpabsq (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpabsq %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpabsq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpabsq (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 2 0.50 vpaddd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 9 0.50 * vpaddd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpaddd (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 1 2 0.50 vpaddd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpaddd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpaddd (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 2 0.50 vpaddd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpaddd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpaddd (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 2 0.50 vpaddq %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 9 0.50 * vpaddq (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpaddq (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 1 2 0.50 vpaddq %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpaddq (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpaddq (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 2 0.50 vpaddq %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpaddq (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpaddq (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 5 4.00 vpbroadcastd %xmm16, %zmm19
+# CHECK-NEXT: 2 12 4.00 * vpbroadcastd (%rax), %zmm19
+# CHECK-NEXT: 2 4 4.00 vpbroadcastd %xmm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 11 4.00 * vpbroadcastd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 2 5 4.00 vpbroadcastd %xmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 12 4.00 * vpbroadcastd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 5 4.00 vpbroadcastq %xmm16, %zmm19
+# CHECK-NEXT: 2 12 4.00 * vpbroadcastq (%rax), %zmm19
+# CHECK-NEXT: 2 4 4.00 vpbroadcastq %xmm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 11 4.00 * vpbroadcastq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 2 5 4.00 vpbroadcastq %xmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 12 4.00 * vpbroadcastq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpcmpeqd %zmm0, %zmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vpcmpeqd (%rax), %zmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vpcmpeqd (%rax){1to16}, %zmm1, %k2
+# CHECK-NEXT: 4 4 4.50 vpcmpeqd %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 4 11 4.50 * vpcmpeqd (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.50 * vpcmpeqd (%rax){1to16}, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.50 vpcmpeqd %zmm0, %zmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vpcmpeqd (%rax), %zmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vpcmpeqd (%rax){1to16}, %zmm1, %k2
+# CHECK-NEXT: 4 4 4.50 vpcmpeqd %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 4 11 4.50 * vpcmpeqd (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.50 * vpcmpeqd (%rax){1to16}, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.50 vpcmpeqq %zmm0, %zmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vpcmpeqq (%rax), %zmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vpcmpeqq (%rax){1to8}, %zmm1, %k2
+# CHECK-NEXT: 4 4 4.50 vpcmpeqq %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 4 11 4.50 * vpcmpeqq (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.50 * vpcmpeqq (%rax){1to8}, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpgtd %zmm0, %zmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vpcmpgtd (%rax), %zmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vpcmpgtd (%rax){1to16}, %zmm1, %k2
+# CHECK-NEXT: 4 4 4.50 vpcmpgtd %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 4 11 4.50 * vpcmpgtd (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.50 * vpcmpgtd (%rax){1to16}, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpgtq %zmm0, %zmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vpcmpgtq (%rax), %zmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vpcmpgtq (%rax){1to8}, %zmm1, %k2
+# CHECK-NEXT: 4 4 4.50 vpcmpgtq %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 4 11 4.50 * vpcmpgtq (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.50 * vpcmpgtq (%rax){1to8}, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.50 vpcmpeqq %zmm0, %zmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vpcmpeqq (%rax), %zmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vpcmpeqq (%rax){1to8}, %zmm1, %k2
+# CHECK-NEXT: 4 4 4.50 vpcmpeqq %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 4 11 4.50 * vpcmpeqq (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.50 * vpcmpeqq (%rax){1to8}, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.50 vpcmpequd %zmm0, %zmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vpcmpequd (%rax), %zmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vpcmpequd (%rax){1to16}, %zmm1, %k2
+# CHECK-NEXT: 4 4 4.50 vpcmpequd %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 4 11 4.50 * vpcmpequd (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.50 * vpcmpequd (%rax){1to16}, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.50 vpcmpequq %zmm0, %zmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vpcmpequq (%rax), %zmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vpcmpequq (%rax){1to8}, %zmm1, %k2
+# CHECK-NEXT: 4 4 4.50 vpcmpequq %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 4 11 4.50 * vpcmpequq (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.50 * vpcmpequq (%rax){1to8}, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 2 8 0.33 * vpgatherdq (%rax,%ymm1,2), %zmm2 {%k1}
+# CHECK-NEXT: 2 8 0.33 * vpgatherdd (%rax,%zmm1,2), %zmm2 {%k1}
+# CHECK-NEXT: 2 8 0.33 * vpgatherqq (%rax,%zmm1,2), %zmm2 {%k1}
+# CHECK-NEXT: 2 8 0.33 * vpgatherqd (%rax,%zmm1,2), %ymm2 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovdb %zmm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovdb %zmm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovdb %zmm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovdb %zmm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovdb %zmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovdw %zmm19, %ymm16
+# CHECK-NEXT: 1 10 0.50 * vpmovdw %zmm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovdw %zmm19, %ymm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovdw %zmm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovdw %zmm19, %ymm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovqb %zmm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovqb %zmm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovqb %zmm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovqb %zmm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovqb %zmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovqd %zmm19, %ymm16
+# CHECK-NEXT: 1 10 0.50 * vpmovqd %zmm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovqd %zmm19, %ymm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovqd %zmm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovqd %zmm19, %ymm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovqw %zmm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovqw %zmm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovqw %zmm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovqw %zmm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovqw %zmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovsdb %zmm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovsdb %zmm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovsdb %zmm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovsdb %zmm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovsdb %zmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovsdw %zmm19, %ymm16
+# CHECK-NEXT: 1 10 0.50 * vpmovsdw %zmm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovsdw %zmm19, %ymm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovsdw %zmm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovsdw %zmm19, %ymm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovsqb %zmm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovsqb %zmm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovsqb %zmm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovsqb %zmm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovsqb %zmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovsqd %zmm19, %ymm16
+# CHECK-NEXT: 1 10 0.50 * vpmovsqd %zmm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovsqd %zmm19, %ymm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovsqd %zmm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovsqd %zmm19, %ymm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovsqw %zmm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovsqw %zmm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovsqw %zmm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovsqw %zmm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovsqw %zmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovsxbd %xmm16, %zmm19
+# CHECK-NEXT: 1 10 0.50 * vpmovsxbd (%rax), %zmm19
+# CHECK-NEXT: 1 3 0.50 vpmovsxbd %xmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovsxbd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovsxbd %xmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmovsxbd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovsxbq %xmm16, %zmm19
+# CHECK-NEXT: 1 10 0.50 * vpmovsxbq (%rax), %zmm19
+# CHECK-NEXT: 1 3 0.50 vpmovsxbq %xmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovsxbq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovsxbq %xmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmovsxbq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovsxdq %ymm16, %zmm19
+# CHECK-NEXT: 1 10 0.50 * vpmovsxdq (%rax), %zmm19
+# CHECK-NEXT: 1 3 0.50 vpmovsxdq %ymm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovsxdq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovsxdq %ymm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmovsxdq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovsxwd %ymm16, %zmm19
+# CHECK-NEXT: 1 10 0.50 * vpmovsxwd (%rax), %zmm19
+# CHECK-NEXT: 1 3 0.50 vpmovsxwd %ymm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovsxwd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovsxwd %ymm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmovsxwd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovsxwq %xmm16, %zmm19
+# CHECK-NEXT: 1 10 0.50 * vpmovsxwq (%rax), %zmm19
+# CHECK-NEXT: 1 3 0.50 vpmovsxwq %xmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovsxwq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovsxwq %xmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmovsxwq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovusdb %zmm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovusdb %zmm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovusdb %zmm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovusdb %zmm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovusdb %zmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovusdw %zmm19, %ymm16
+# CHECK-NEXT: 1 10 0.50 * vpmovusdw %zmm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovusdw %zmm19, %ymm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovusdw %zmm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovusdw %zmm19, %ymm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovusqb %zmm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovusqb %zmm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovusqb %zmm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovusqb %zmm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovusqb %zmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovusqd %zmm19, %ymm16
+# CHECK-NEXT: 1 10 0.50 * vpmovusqd %zmm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovusqd %zmm19, %ymm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovusqd %zmm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovusqd %zmm19, %ymm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovusqw %zmm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovusqw %zmm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovusqw %zmm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovusqw %zmm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovusqw %zmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovzxbd %xmm16, %zmm19
+# CHECK-NEXT: 1 10 0.50 * vpmovzxbd (%rax), %zmm19
+# CHECK-NEXT: 1 3 0.50 vpmovzxbd %xmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovzxbd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovzxbd %xmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmovzxbd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovzxbq %xmm16, %zmm19
+# CHECK-NEXT: 1 10 0.50 * vpmovzxbq (%rax), %zmm19
+# CHECK-NEXT: 1 3 0.50 vpmovzxbq %xmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovzxbq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovzxbq %xmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmovzxbq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovzxdq %ymm16, %zmm19
+# CHECK-NEXT: 1 10 0.50 * vpmovzxdq (%rax), %zmm19
+# CHECK-NEXT: 1 3 0.50 vpmovzxdq %ymm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovzxdq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovzxdq %ymm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmovzxdq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovzxwd %ymm16, %zmm19
+# CHECK-NEXT: 1 10 0.50 * vpmovzxwd (%rax), %zmm19
+# CHECK-NEXT: 1 3 0.50 vpmovzxwd %ymm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovzxwd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovzxwd %ymm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmovzxwd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovzxwq %xmm16, %zmm19
+# CHECK-NEXT: 1 10 0.50 * vpmovzxwq (%rax), %zmm19
+# CHECK-NEXT: 1 3 0.50 vpmovzxwq %xmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovzxwq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovzxwq %xmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmovzxwq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 1.00 vpmulld %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vpmulld (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vpmulld (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 1 4 1.00 vpmulld %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vpmulld (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 1.00 * vpmulld (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 3 1.00 vpmulld %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vpmulld (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vpmulld (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 8 8 8.00 vpermd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 8 15 8.00 * vpermd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 8 15 8.00 * vpermd (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 8 8 8.00 vpermd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 8 15 8.00 * vpermd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 8 15 8.00 * vpermd (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 8 8 8.00 vpermd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 8 15 8.00 * vpermd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 8 15 8.00 * vpermd (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 2 1.00 vpermilpd $0, %zmm16, %zmm19
+# CHECK-NEXT: 1 9 1.00 * vpermilpd $0, (%rax), %zmm19
+# CHECK-NEXT: 1 8 1.00 * vpermilpd $0, (%rax){1to8}, %zmm19
+# CHECK-NEXT: 1 2 1.00 vpermilpd $0, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpermilpd $0, (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 8 1.00 * vpermilpd $0, (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpermilpd $0, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpermilpd $0, (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 1.00 * vpermilpd $0, (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 4.00 vpermilpd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 10 4.00 * vpermilpd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 12 4.00 * vpermilpd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 1 4 4.00 vpermilpd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 11 4.00 * vpermilpd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 12 4.00 * vpermilpd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 3 4.00 vpermilpd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 4.00 * vpermilpd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 12 4.00 * vpermilpd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 2 1.00 vpermilps $0, %zmm16, %zmm19
+# CHECK-NEXT: 1 9 1.00 * vpermilps $0, (%rax), %zmm19
+# CHECK-NEXT: 1 8 1.00 * vpermilps $0, (%rax){1to16}, %zmm19
+# CHECK-NEXT: 1 2 1.00 vpermilps $0, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpermilps $0, (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 8 1.00 * vpermilps $0, (%rax){1to16}, %zmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpermilps $0, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpermilps $0, (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 1.00 * vpermilps $0, (%rax){1to16}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 4.00 vpermilps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 10 4.00 * vpermilps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 12 4.00 * vpermilps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 1 4 4.00 vpermilps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 11 4.00 * vpermilps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 12 4.00 * vpermilps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 3 4.00 vpermilps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 4.00 * vpermilps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 12 4.00 * vpermilps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 4.00 vpermpd $0, %zmm16, %zmm19
+# CHECK-NEXT: 1 11 4.00 * vpermpd $0, (%rax), %zmm19
+# CHECK-NEXT: 1 10 0.50 * vpermpd $0, (%rax){1to8}, %zmm19
+# CHECK-NEXT: 1 4 4.00 vpermpd $0, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 11 4.00 * vpermpd $0, (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpermpd $0, (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: 1 4 4.00 vpermpd $0, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 4.00 * vpermpd $0, (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpermpd $0, (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 8 8 8.00 vpermpd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 8 15 8.00 * vpermpd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 8 15 8.00 * vpermpd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 8 8 8.00 vpermpd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 8 15 8.00 * vpermpd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 8 15 8.00 * vpermpd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 8 8 8.00 vpermpd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 8 15 8.00 * vpermpd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 8 15 8.00 * vpermpd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 8 8 8.00 vpermps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 8 15 8.00 * vpermps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 8 15 8.00 * vpermps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 8 8 8.00 vpermps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 8 15 8.00 * vpermps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 8 15 8.00 * vpermps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 8 8 8.00 vpermps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 8 15 8.00 * vpermps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 8 15 8.00 * vpermps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 4.00 vpermq $0, %zmm16, %zmm19
+# CHECK-NEXT: 1 11 4.00 * vpermq $0, (%rax), %zmm19
+# CHECK-NEXT: 1 10 0.50 * vpermq $0, (%rax){1to8}, %zmm19
+# CHECK-NEXT: 1 4 4.00 vpermq $0, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 11 4.00 * vpermq $0, (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpermq $0, (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: 1 4 4.00 vpermq $0, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 4.00 * vpermq $0, (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpermq $0, (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 8 8 8.00 vpermq %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 8 15 8.00 * vpermq (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 8 15 8.00 * vpermq (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 8 8 8.00 vpermq %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 8 15 8.00 * vpermq (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 8 15 8.00 * vpermq (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 8 8 8.00 vpermq %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 8 15 8.00 * vpermq (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 8 15 8.00 * vpermq (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 * vpscatterdd %zmm1, (%rdx,%zmm0,4) {%k1}
+# CHECK-NEXT: 1 1 0.50 * vpscatterdq %zmm1, (%rdx,%ymm0,4) {%k1}
+# CHECK-NEXT: 1 1 0.50 * vpscatterqd %ymm1, (%rdx,%zmm0,4) {%k1}
+# CHECK-NEXT: 1 1 0.50 * vpscatterqq %zmm1, (%rdx,%zmm0,4) {%k1}
+# CHECK-NEXT: 1 1 1.00 vpshufd $0, %zmm16, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vpshufd $0, (%rax), %zmm19
+# CHECK-NEXT: 1 8 1.00 * vpshufd $0, (%rax){1to16}, %zmm19
+# CHECK-NEXT: 1 1 1.00 vpshufd $0, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 1.00 * vpshufd $0, (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 8 1.00 * vpshufd $0, (%rax){1to16}, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 1.00 vpshufd $0, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 1.00 * vpshufd $0, (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 1.00 * vpshufd $0, (%rax){1to16}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpsubd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpsubd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpsubd (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 1 2 0.50 vpsubd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpsubd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpsubd (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpsubd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpsubd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpsubd (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpsubq %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpsubq (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpsubq (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 1 2 0.50 vpsubq %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpsubq (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpsubq (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpsubq %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpsubq (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpsubq (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 1.00 vpunpckhdq %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vpunpckhdq (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vpunpckhdq (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 1 1 1.00 vpunpckhdq %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 1.00 * vpunpckhdq (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 1.00 * vpunpckhdq (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 1.00 vpunpckhdq %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 1.00 * vpunpckhdq (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 1.00 * vpunpckhdq (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 1.00 vpunpckhqdq %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vpunpckhqdq (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vpunpckhqdq (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 1 1 1.00 vpunpckhqdq %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 1.00 * vpunpckhqdq (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 1.00 * vpunpckhqdq (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 1.00 vpunpckhqdq %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 1.00 * vpunpckhqdq (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 1.00 * vpunpckhqdq (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 1.00 vpunpckldq %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vpunpckldq (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vpunpckldq (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 1 1 1.00 vpunpckldq %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 1.00 * vpunpckldq (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 1.00 * vpunpckldq (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 1.00 vpunpckldq %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 1.00 * vpunpckldq (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 1.00 * vpunpckldq (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 1.00 vpunpcklqdq %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vpunpcklqdq (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vpunpcklqdq (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 1 1 1.00 vpunpcklqdq %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 1.00 * vpunpcklqdq (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 1.00 * vpunpcklqdq (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 1.00 vpunpcklqdq %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 1.00 * vpunpcklqdq (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 1.00 * vpunpcklqdq (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 * vscatterdps %zmm1, (%rdx,%zmm0,4) {%k1}
+# CHECK-NEXT: 1 1 0.50 * vscatterdpd %zmm1, (%rdx,%ymm0,4) {%k1}
+# CHECK-NEXT: 1 1 0.50 * vscatterqps %ymm1, (%rdx,%zmm0,4) {%k1}
+# CHECK-NEXT: 1 1 0.50 * vscatterqpd %zmm1, (%rdx,%zmm0,4) {%k1}
+# CHECK-NEXT: 4 3 4.00 vshuff32x4 $0, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 4 10 4.00 * vshuff32x4 $0, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 10 0.50 * vshuff32x4 $0, (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 4 3 4.00 vshuff32x4 $0, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 4 10 4.00 * vshuff32x4 $0, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vshuff32x4 $0, (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 4 3 4.00 vshuff32x4 $0, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 4 10 4.00 * vshuff32x4 $0, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vshuff32x4 $0, (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 4 3 4.00 vshuff64x2 $0, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 4 10 4.00 * vshuff64x2 $0, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 10 0.50 * vshuff64x2 $0, (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 4 3 4.00 vshuff64x2 $0, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 4 10 4.00 * vshuff64x2 $0, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vshuff64x2 $0, (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 4 3 4.00 vshuff64x2 $0, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 4 10 4.00 * vshuff64x2 $0, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vshuff64x2 $0, (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 4 3 4.00 vshufi32x4 $0, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 4 10 4.00 * vshufi32x4 $0, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 10 0.50 * vshufi32x4 $0, (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 4 3 4.00 vshufi32x4 $0, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 4 10 4.00 * vshufi32x4 $0, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vshufi32x4 $0, (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 4 3 4.00 vshufi32x4 $0, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 4 10 4.00 * vshufi32x4 $0, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vshufi32x4 $0, (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 4 3 4.00 vshufi64x2 $0, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 4 10 4.00 * vshufi64x2 $0, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 10 0.50 * vshufi64x2 $0, (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 4 3 4.00 vshufi64x2 $0, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 4 10 4.00 * vshufi64x2 $0, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vshufi64x2 $0, (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 4 3 4.00 vshufi64x2 $0, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 4 10 4.00 * vshufi64x2 $0, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vshufi64x2 $0, (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 16 9.50 vsqrtpd %zmm16, %zmm19
+# CHECK-NEXT: 1 23 9.50 * vsqrtpd (%rax), %zmm19
+# CHECK-NEXT: 1 23 9.50 * vsqrtpd (%rax){1to8}, %zmm19
+# CHECK-NEXT: 1 16 9.50 vsqrtpd %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 23 9.50 * vsqrtpd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 23 9.50 * vsqrtpd (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: 1 16 9.50 vsqrtpd %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 23 9.50 * vsqrtpd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 23 9.50 * vsqrtpd (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 16 6.50 vsqrtps %zmm16, %zmm19
+# CHECK-NEXT: 1 23 6.50 * vsqrtps (%rax), %zmm19
+# CHECK-NEXT: 1 23 6.50 * vsqrtps (%rax){1to16}, %zmm19
+# CHECK-NEXT: 1 16 6.50 vsqrtps %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 23 6.50 * vsqrtps (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 23 6.50 * vsqrtps (%rax){1to16}, %zmm19 {%k1}
+# CHECK-NEXT: 1 16 6.50 vsqrtps %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 23 6.50 * vsqrtps (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 23 6.50 * vsqrtps (%rax){1to16}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 9.50 vsqrtsd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 15 9.50 * vsqrtsd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 8 9.50 vsqrtsd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 15 9.50 * vsqrtsd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 9.50 vsqrtsd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 15 9.50 * vsqrtsd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 6.50 vsqrtss %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 15 6.50 * vsqrtss (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 8 6.50 vsqrtss %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 15 6.50 * vsqrtss (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 6.50 vsqrtss %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 15 6.50 * vsqrtss (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpsubd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpsubd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpsubd (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 1 2 0.50 vpsubd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpsubd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpsubd (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpsubd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpsubd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpsubd (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpsubq %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpsubq (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpsubq (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 1 2 0.50 vpsubq %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpsubq (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpsubq (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpsubq %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpsubq (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpsubq (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vptestmd %zmm0, %zmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestmd (%rax), %zmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestmd (%rax){1to16}, %zmm1, %k2
+# CHECK-NEXT: 4 4 3.00 vptestmd %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 3 11 4.50 * vptestmd (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.33 * vptestmd (%rax){1to16}, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vptestmq %zmm0, %zmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestmq (%rax), %zmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestmq (%rax){1to8}, %zmm1, %k2
+# CHECK-NEXT: 4 4 3.00 vptestmq %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 3 11 4.50 * vptestmq (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.33 * vptestmq (%rax){1to8}, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vptestnmd %zmm0, %zmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestnmd (%rax), %zmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestnmd (%rax){1to16}, %zmm1, %k2
+# CHECK-NEXT: 4 4 3.00 vptestnmd %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 3 11 4.50 * vptestnmd (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.33 * vptestnmd (%rax){1to16}, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vptestnmq %zmm0, %zmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestnmq (%rax), %zmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestnmq (%rax){1to8}, %zmm1, %k2
+# CHECK-NEXT: 4 4 3.00 vptestnmq %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 3 11 4.50 * vptestnmq (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.33 * vptestnmq (%rax){1to8}, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 3 1.00 vsubpd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vsubpd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vsubpd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 1 4 0.50 vsubpd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vsubpd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vsubpd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 3 1.00 vsubpd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vsubpd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vsubpd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 1.00 vsubps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vsubps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vsubps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 1 4 0.50 vsubps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vsubps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vsubps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 3 1.00 vsubps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vsubps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vsubps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 1 0.50 vucomiss %xmm16, %xmm17
+# CHECK-NEXT: 2 8 0.50 * vucomiss (%rax), %xmm17
+# CHECK-NEXT: 1 1 1.00 vunpckhpd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vunpckhpd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vunpckhpd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 1 2 1.00 vunpckhpd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vunpckhpd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 1.00 * vunpckhpd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 1.00 vunpckhpd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 1.00 * vunpckhpd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 1.00 * vunpckhpd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 1.00 vunpckhps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vunpckhps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vunpckhps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 1 2 1.00 vunpckhps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vunpckhps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 1.00 * vunpckhps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 1.00 vunpckhps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 1.00 * vunpckhps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 1.00 * vunpckhps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 1.00 vunpcklpd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vunpcklpd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vunpcklpd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 1 2 1.00 vunpcklpd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vunpcklpd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 1.00 * vunpcklpd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 1.00 vunpcklpd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 1.00 * vunpcklpd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 1.00 * vunpcklpd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 1.00 vunpcklps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vunpcklps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vunpcklps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 1 2 1.00 vunpcklps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vunpcklps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 1.00 * vunpcklps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 1.00 vunpcklps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 1.00 * vunpcklps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 1.00 * vunpcklps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 213.00 213.00 213.00 - - - - - 963.50 1305.00 962.00 1303.50 161.75 161.75 161.75 161.75 204.67 204.67 204.67 8.25 8.25 8.25 8.25
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - kandw %k0, %k1, %k2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - kandnw %k0, %k1, %k2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - knotw %k0, %k2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - korw %k0, %k1, %k2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - kxnorw %k0, %k1, %k2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - kxorw %k0, %k1, %k2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - kshiftlw $2, %k1, %k2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - kshiftrw $2, %k1, %k2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - kunpckbw %k0, %k1, %k2
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vaddpd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddpd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddpd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vaddpd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddpd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddpd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vaddpd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddpd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddpd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vaddps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vaddps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vaddps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - valignd $1, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignd $1, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignd $1, (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - valignd $1, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignd $1, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignd $1, (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - valignd $1, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignd $1, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignd $1, (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - valignq $1, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignq $1, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignq $1, (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - valignq $1, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignq $1, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignq $1, (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - valignq $1, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignq $1, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignq $1, (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastf32x4 (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastf32x4 (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastf32x4 (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastf64x4 (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastf64x4 (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastf64x4 (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcasti32x4 (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcasti32x4 (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcasti32x4 (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcasti64x4 (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcasti64x4 (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcasti64x4 (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vbroadcastsd %xmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastsd (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vbroadcastsd %xmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastsd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vbroadcastsd %xmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastsd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vbroadcastss %xmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastss (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vbroadcastss %xmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastss (%rax), %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vbroadcastss %xmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastss (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vcmpeqpd %zmm0, %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqpd (%rax), %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqpd (%rax){1to8}, %zmm1, %k2
+# CHECK-NEXT: - - - - - - - - 5.00 5.00 5.00 5.00 - - - - - - - - - - - vcmpeqpd %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 5.00 5.00 5.00 5.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqpd (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqpd (%rax){1to8}, %zmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vcmpeqps %zmm0, %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqps (%rax), %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqps (%rax){1to16}, %zmm1, %k2
+# CHECK-NEXT: - - - - - - - - 5.00 5.00 5.00 5.00 - - - - - - - - - - - vcmpeqps %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 5.00 5.00 5.00 5.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqps (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqps (%rax){1to16}, %zmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vcmpeqsd %xmm0, %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqsd (%rax), %xmm1, %k2
+# CHECK-NEXT: - - - - - - - - 5.00 5.00 5.00 5.00 - - - - - - - - - - - vcmpeqsd %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 5.00 5.00 5.00 5.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqsd (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vcmpeqss %xmm0, %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqss (%rax), %xmm1, %k2
+# CHECK-NEXT: - - - - - - - - 5.00 5.00 5.00 5.00 - - - - - - - - - - - vcmpeqss %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 5.00 5.00 5.00 5.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqss (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vcomiss %xmm16, %xmm17
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcomiss (%rax), %xmm17
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtdq2pd %ymm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2pd (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2pd (%rax){1to8}, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtdq2pd %ymm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2pd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2pd (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtdq2pd %ymm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2pd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2pd (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtdq2ps %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2ps (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2ps (%rax){1to16}, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtdq2ps %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2ps (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2ps (%rax){1to16}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtdq2ps %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2ps (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2ps (%rax){1to16}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2dq %zmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2dq (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2dq (%rax){1to8}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2dq %zmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2dq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2dq (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2dq %zmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2dq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2dq (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2udq %zmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2udq (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2udq (%rax){1to8}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2udq %zmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2udq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2udq (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2udq %zmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2udq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2udq (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttpd2dq %zmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2dq (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2dq (%rax){1to8}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttpd2dq %zmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2dq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2dq (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttpd2dq %zmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2dq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2dq (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttpd2udq %zmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2udq (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2udq (%rax){1to8}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttpd2udq %zmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2udq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2udq (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttpd2udq %zmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2udq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2udq (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2ps %zmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2ps (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2ps (%rax){1to8}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2ps %zmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2ps (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2ps (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2ps %zmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2ps (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2ps (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtps2dq %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2dq (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2dq (%rax){1to16}, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtps2dq %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2dq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2dq (%rax){1to16}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtps2dq %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2dq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2dq (%rax){1to16}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttps2dq %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2dq (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2dq (%rax){1to16}, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttps2dq %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2dq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2dq (%rax){1to16}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttps2dq %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2dq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2dq (%rax){1to16}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtps2pd %ymm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2pd (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2pd (%rax){1to8}, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtps2pd %ymm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2pd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2pd (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtps2pd %ymm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2pd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2pd (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtsd2usi %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtsd2usi %xmm0, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtsd2usi (%rax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtsd2usi (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtss2usi %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtss2usi %xmm0, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtss2usi (%rax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtss2usi (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtps2udq %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2udq (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2udq (%rax){1to16}, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtps2udq %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2udq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2udq (%rax){1to16}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtps2udq %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2udq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2udq (%rax){1to16}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttps2udq %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2udq (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2udq (%rax){1to16}, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttps2udq %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2udq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2udq (%rax){1to16}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttps2udq %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2udq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2udq (%rax){1to16}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttsd2usi %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttsd2usi %xmm0, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttsd2usi (%rax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttsd2usi (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttss2usi %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttss2usi %xmm0, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttss2usi (%rax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttss2usi (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtudq2pd %ymm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtudq2pd (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtudq2pd (%rax){1to8}, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtudq2pd %ymm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtudq2pd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtudq2pd (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtudq2pd %ymm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtudq2pd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtudq2pd (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtudq2ps %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtudq2ps (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtudq2ps (%rax){1to16}, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtudq2ps %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtudq2ps (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtudq2ps (%rax){1to16}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtudq2ps %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtudq2ps (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtudq2ps (%rax){1to16}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtusi2sd %ecx, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.50 - 1.50 - - - - - - - - - - - vcvtusi2sd %rcx, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtusi2sdl (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.50 - 1.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtusi2sdq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtusi2ss %ecx, %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.50 - 1.50 - - - - - - - - - - - vcvtusi2ss %rcx, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtusi2ssl (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.50 - 1.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtusi2ssq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 12.00 - 12.00 - - - - - - - - - - - vdivpd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 12.00 - 12.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivpd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 12.00 - 12.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivpd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - - 12.00 - 12.00 - - - - - - - - - - - vdivpd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 12.00 - 12.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivpd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 12.00 - 12.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivpd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 12.00 - 12.00 - - - - - - - - - - - vdivpd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 12.00 - 12.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivpd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 12.00 - 12.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivpd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 9.00 - 9.00 - - - - - - - - - - - vdivps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 9.00 - 9.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 9.00 - 9.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - - 9.00 - 9.00 - - - - - - - - - - - vdivps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 9.00 - 9.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 9.00 - 9.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 9.00 - 9.00 - - - - - - - - - - - vdivps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 9.00 - 9.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 9.00 - 9.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - {evex} vextractps $1, %xmm0, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 {evex} vextractps $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vfmadd132pd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132pd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132pd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vfmadd132pd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132pd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132pd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vfmadd132pd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132pd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132pd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vfmadd213pd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213pd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213pd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vfmadd213pd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213pd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213pd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vfmadd213pd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213pd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213pd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vfmadd231pd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231pd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231pd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vfmadd231pd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231pd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231pd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vfmadd231pd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231pd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231pd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vfmadd132ps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132ps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132ps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vfmadd132ps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132ps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132ps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vfmadd132ps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132ps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132ps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vfmadd213ps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213ps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213ps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vfmadd213ps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213ps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213ps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vfmadd213ps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213ps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213ps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vfmadd231ps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231ps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231ps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vfmadd231ps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231ps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231ps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vfmadd231ps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231ps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231ps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgatherdpd (%rax,%ymm1,2), %zmm2 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgatherdps (%rax,%zmm1,2), %zmm2 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgatherqpd (%rax,%zmm1,2), %zmm2 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgatherqps (%rax,%zmm1,2), %ymm2 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmaxpd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxpd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxpd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vmaxpd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxpd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxpd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmaxpd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxpd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxpd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmaxps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vmaxps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmaxps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vminpd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminpd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminpd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vminpd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminpd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminpd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vminpd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminpd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminpd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vminps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vminps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vminps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovapd %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovapd (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovapd %zmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovapd %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovapd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovapd %zmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovapd %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovapd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovaps %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovaps (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovaps %zmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovaps %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovaps (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovaps %zmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovaps %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovaps (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vmovddup %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovddup (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vmovddup %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovddup (%rax), %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vmovddup %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovddup (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqa32 %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqa32 (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqa32 %zmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqa32 %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqa32 (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqa32 %zmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqa32 %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqa32 (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqa64 %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqa64 (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqa64 %zmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqa64 %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqa64 (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqa64 %zmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqa64 %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqa64 (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu32 %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu32 (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqu32 %zmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu32 %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu32 (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqu32 %zmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu32 %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu32 (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu64 %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu64 (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqu64 %zmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu64 %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu64 (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqu64 %zmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu64 %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu64 (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovntdqa (%rax), %zmm0
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vmovshdup %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovshdup (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vmovshdup %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovshdup (%rax), %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vmovshdup %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovshdup (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vmovsldup %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovsldup (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vmovsldup %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovsldup (%rax), %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vmovsldup %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovsldup (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovupd %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovupd (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovupd %zmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovupd %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovupd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovupd %zmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovupd %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovupd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovups %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovups (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovups %zmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovups %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovups (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovups %zmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovups %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovups (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vmulpd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulpd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulpd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vmulpd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulpd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulpd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vmulpd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulpd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulpd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vmulps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vmulps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vmulps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpabsd %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsd (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsd (%rax){1to16}, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpabsd %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsd (%rax){1to16}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpabsd %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsd (%rax){1to16}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpabsq %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsq (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsq (%rax){1to8}, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpabsq %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsq (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpabsq %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsq (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddd (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddd (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddd (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddq %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddq (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddq (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddq %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddq (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddq (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddq %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddq (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddq (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpbroadcastd %xmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastd (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpbroadcastd %xmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpbroadcastd %xmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpbroadcastq %xmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastq (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpbroadcastq %xmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpbroadcastq %xmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpcmpeqd %zmm0, %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqd (%rax), %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqd (%rax){1to16}, %zmm1, %k2
+# CHECK-NEXT: - - - - - - - - 3.00 6.00 3.00 6.00 - - - - - - - - - - - vpcmpeqd %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 6.00 3.00 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqd (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqd (%rax){1to16}, %zmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpcmpeqd %zmm0, %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqd (%rax), %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqd (%rax){1to16}, %zmm1, %k2
+# CHECK-NEXT: - - - - - - - - 3.00 6.00 3.00 6.00 - - - - - - - - - - - vpcmpeqd %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 6.00 3.00 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqd (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqd (%rax){1to16}, %zmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpcmpeqq %zmm0, %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqq (%rax), %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqq (%rax){1to8}, %zmm1, %k2
+# CHECK-NEXT: - - - - - - - - 3.00 6.00 3.00 6.00 - - - - - - - - - - - vpcmpeqq %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 6.00 3.00 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqq (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqq (%rax){1to8}, %zmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpgtd %zmm0, %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtd (%rax), %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtd (%rax){1to16}, %zmm1, %k2
+# CHECK-NEXT: - - - - - - - - 3.00 6.00 3.00 6.00 - - - - - - - - - - - vpcmpgtd %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 6.00 3.00 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtd (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtd (%rax){1to16}, %zmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpgtq %zmm0, %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtq (%rax), %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtq (%rax){1to8}, %zmm1, %k2
+# CHECK-NEXT: - - - - - - - - 3.00 6.00 3.00 6.00 - - - - - - - - - - - vpcmpgtq %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 6.00 3.00 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtq (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtq (%rax){1to8}, %zmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpcmpeqq %zmm0, %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqq (%rax), %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqq (%rax){1to8}, %zmm1, %k2
+# CHECK-NEXT: - - - - - - - - 3.00 6.00 3.00 6.00 - - - - - - - - - - - vpcmpeqq %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 6.00 3.00 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqq (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqq (%rax){1to8}, %zmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpcmpequd %zmm0, %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequd (%rax), %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequd (%rax){1to16}, %zmm1, %k2
+# CHECK-NEXT: - - - - - - - - 3.00 6.00 3.00 6.00 - - - - - - - - - - - vpcmpequd %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 6.00 3.00 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequd (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequd (%rax){1to16}, %zmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpcmpequq %zmm0, %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequq (%rax), %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequq (%rax){1to8}, %zmm1, %k2
+# CHECK-NEXT: - - - - - - - - 3.00 6.00 3.00 6.00 - - - - - - - - - - - vpcmpequq %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 6.00 3.00 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequq (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequq (%rax){1to8}, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpgatherdq (%rax,%ymm1,2), %zmm2 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpgatherdd (%rax,%zmm1,2), %zmm2 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpgatherqq (%rax,%zmm1,2), %zmm2 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpgatherqd (%rax,%zmm1,2), %ymm2 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovdb %zmm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovdb %zmm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovdb %zmm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovdb %zmm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovdb %zmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovdw %zmm19, %ymm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovdw %zmm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovdw %zmm19, %ymm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovdw %zmm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovdw %zmm19, %ymm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovqb %zmm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovqb %zmm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovqb %zmm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovqb %zmm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovqb %zmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovqd %zmm19, %ymm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovqd %zmm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovqd %zmm19, %ymm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovqd %zmm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovqd %zmm19, %ymm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovqw %zmm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovqw %zmm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovqw %zmm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovqw %zmm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovqw %zmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsdb %zmm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsdb %zmm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsdb %zmm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsdb %zmm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsdb %zmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsdw %zmm19, %ymm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsdw %zmm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsdw %zmm19, %ymm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsdw %zmm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsdw %zmm19, %ymm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsqb %zmm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsqb %zmm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsqb %zmm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsqb %zmm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsqb %zmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsqd %zmm19, %ymm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsqd %zmm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsqd %zmm19, %ymm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsqd %zmm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsqd %zmm19, %ymm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsqw %zmm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsqw %zmm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsqw %zmm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsqw %zmm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsqw %zmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxbd %xmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbd (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxbd %xmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxbd %xmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxbq %xmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbq (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxbq %xmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxbq %xmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxdq %ymm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxdq (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxdq %ymm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxdq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxdq %ymm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxdq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxwd %ymm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxwd (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxwd %ymm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxwd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxwd %ymm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxwd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxwq %xmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxwq (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxwq %xmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxwq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxwq %xmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxwq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusdb %zmm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovusdb %zmm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusdb %zmm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovusdb %zmm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusdb %zmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusdw %zmm19, %ymm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovusdw %zmm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusdw %zmm19, %ymm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovusdw %zmm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusdw %zmm19, %ymm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusqb %zmm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovusqb %zmm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusqb %zmm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovusqb %zmm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusqb %zmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusqd %zmm19, %ymm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovusqd %zmm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusqd %zmm19, %ymm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovusqd %zmm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusqd %zmm19, %ymm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusqw %zmm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovusqw %zmm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusqw %zmm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovusqw %zmm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusqw %zmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxbd %xmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbd (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxbd %xmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxbd %xmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxbq %xmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbq (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxbq %xmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxbq %xmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxdq %ymm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxdq (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxdq %ymm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxdq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxdq %ymm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxdq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxwd %ymm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxwd (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxwd %ymm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxwd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxwd %ymm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxwd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxwq %xmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxwq (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxwq %xmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxwq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxwq %xmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxwq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmulld %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulld (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulld (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmulld %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulld (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulld (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmulld %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulld (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulld (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 8.00 8.00 8.00 8.00 - - - - - - - - - - - vpermd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 8.00 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 8.00 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermd (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 8.00 8.00 8.00 8.00 - - - - - - - - - - - vpermd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 8.00 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 8.00 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermd (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 8.00 8.00 8.00 8.00 - - - - - - - - - - - vpermd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 8.00 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 8.00 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermd (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpermilpd $0, %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd $0, (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd $0, (%rax){1to8}, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpermilpd $0, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd $0, (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd $0, (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpermilpd $0, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd $0, (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd $0, (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpermilpd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpermilpd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpermilpd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpermilps $0, %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps $0, (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps $0, (%rax){1to16}, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpermilps $0, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps $0, (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps $0, (%rax){1to16}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpermilps $0, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps $0, (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps $0, (%rax){1to16}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpermilps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpermilps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpermilps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpermpd $0, %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermpd $0, (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermpd $0, (%rax){1to8}, %zmm19
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpermpd $0, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermpd $0, (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermpd $0, (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpermpd $0, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermpd $0, (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermpd $0, (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 8.00 8.00 8.00 8.00 - - - - - - - - - - - vpermpd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 8.00 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermpd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 8.00 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermpd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 8.00 8.00 8.00 8.00 - - - - - - - - - - - vpermpd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 8.00 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermpd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 8.00 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermpd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 8.00 8.00 8.00 8.00 - - - - - - - - - - - vpermpd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 8.00 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermpd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 8.00 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermpd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 8.00 8.00 8.00 8.00 - - - - - - - - - - - vpermps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 8.00 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 8.00 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 8.00 8.00 8.00 8.00 - - - - - - - - - - - vpermps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 8.00 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 8.00 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 8.00 8.00 8.00 8.00 - - - - - - - - - - - vpermps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 8.00 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 8.00 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpermq $0, %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermq $0, (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermq $0, (%rax){1to8}, %zmm19
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpermq $0, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermq $0, (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermq $0, (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpermq $0, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermq $0, (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermq $0, (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 8.00 8.00 8.00 8.00 - - - - - - - - - - - vpermq %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 8.00 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermq (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 8.00 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermq (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 8.00 8.00 8.00 8.00 - - - - - - - - - - - vpermq %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 8.00 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermq (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 8.00 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermq (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 8.00 8.00 8.00 8.00 - - - - - - - - - - - vpermq %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 8.00 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermq (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 8.00 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermq (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 vpscatterdd %zmm1, (%rdx,%zmm0,4) {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 vpscatterdq %zmm1, (%rdx,%ymm0,4) {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 vpscatterqd %ymm1, (%rdx,%zmm0,4) {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 vpscatterqq %zmm1, (%rdx,%zmm0,4) {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpshufd $0, %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufd $0, (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufd $0, (%rax){1to16}, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpshufd $0, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufd $0, (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufd $0, (%rax){1to16}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpshufd $0, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufd $0, (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufd $0, (%rax){1to16}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubd (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubd (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubd (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubq %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubq (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubq (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubq %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubq (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubq (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubq %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubq (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubq (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpunpckhdq %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhdq (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhdq (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpunpckhdq %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhdq (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhdq (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpunpckhdq %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhdq (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhdq (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpunpckhqdq %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhqdq (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhqdq (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpunpckhqdq %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhqdq (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhqdq (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpunpckhqdq %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhqdq (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhqdq (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpunpckldq %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckldq (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckldq (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpunpckldq %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckldq (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckldq (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpunpckldq %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckldq (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckldq (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpunpcklqdq %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpcklqdq (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpcklqdq (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpunpcklqdq %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpcklqdq (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpcklqdq (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpunpcklqdq %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpcklqdq (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpcklqdq (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 vscatterdps %zmm1, (%rdx,%zmm0,4) {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 vscatterdpd %zmm1, (%rdx,%ymm0,4) {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 vscatterqps %ymm1, (%rdx,%zmm0,4) {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 vscatterqpd %zmm1, (%rdx,%zmm0,4) {%k1}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vshuff32x4 $0, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshuff32x4 $0, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshuff32x4 $0, (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vshuff32x4 $0, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshuff32x4 $0, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshuff32x4 $0, (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vshuff32x4 $0, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshuff32x4 $0, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshuff32x4 $0, (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vshuff64x2 $0, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshuff64x2 $0, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshuff64x2 $0, (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vshuff64x2 $0, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshuff64x2 $0, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshuff64x2 $0, (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vshuff64x2 $0, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshuff64x2 $0, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshuff64x2 $0, (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vshufi32x4 $0, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshufi32x4 $0, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshufi32x4 $0, (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vshufi32x4 $0, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshufi32x4 $0, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshufi32x4 $0, (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vshufi32x4 $0, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshufi32x4 $0, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshufi32x4 $0, (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vshufi64x2 $0, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshufi64x2 $0, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshufi64x2 $0, (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vshufi64x2 $0, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshufi64x2 $0, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshufi64x2 $0, (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vshufi64x2 $0, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshufi64x2 $0, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshufi64x2 $0, (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 9.50 - 9.50 - - - - - - - - - - - vsqrtpd %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 9.50 - 9.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtpd (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 9.50 - 9.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtpd (%rax){1to8}, %zmm19
+# CHECK-NEXT: - - - - - - - - - 9.50 - 9.50 - - - - - - - - - - - vsqrtpd %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 9.50 - 9.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtpd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 9.50 - 9.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtpd (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 9.50 - 9.50 - - - - - - - - - - - vsqrtpd %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 9.50 - 9.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtpd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 9.50 - 9.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtpd (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 6.50 - 6.50 - - - - - - - - - - - vsqrtps %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.50 - 6.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtps (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.50 - 6.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtps (%rax){1to16}, %zmm19
+# CHECK-NEXT: - - - - - - - - - 6.50 - 6.50 - - - - - - - - - - - vsqrtps %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.50 - 6.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtps (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.50 - 6.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtps (%rax){1to16}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 6.50 - 6.50 - - - - - - - - - - - vsqrtps %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.50 - 6.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtps (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.50 - 6.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtps (%rax){1to16}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 9.50 - 9.50 - - - - - - - - - - - vsqrtsd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 9.50 - 9.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtsd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - - 9.50 - 9.50 - - - - - - - - - - - vsqrtsd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 9.50 - 9.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtsd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 9.50 - 9.50 - - - - - - - - - - - vsqrtsd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 9.50 - 9.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtsd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 6.50 - 6.50 - - - - - - - - - - - vsqrtss %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.50 - 6.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtss (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - - 6.50 - 6.50 - - - - - - - - - - - vsqrtss %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.50 - 6.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtss (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 6.50 - 6.50 - - - - - - - - - - - vsqrtss %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.50 - 6.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtss (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubd (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubd (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubd (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubq %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubq (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubq (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubq %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubq (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubq (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubq %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubq (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubq (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vptestmd %zmm0, %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmd (%rax), %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmd (%rax){1to16}, %zmm1, %k2
+# CHECK-NEXT: - - - - - - - - 2.00 4.00 2.00 4.00 - - - - - - - - - - - vptestmd %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 6.00 3.00 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmd (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmd (%rax){1to16}, %zmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vptestmq %zmm0, %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmq (%rax), %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmq (%rax){1to8}, %zmm1, %k2
+# CHECK-NEXT: - - - - - - - - 2.00 4.00 2.00 4.00 - - - - - - - - - - - vptestmq %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 6.00 3.00 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmq (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmq (%rax){1to8}, %zmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vptestnmd %zmm0, %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmd (%rax), %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmd (%rax){1to16}, %zmm1, %k2
+# CHECK-NEXT: - - - - - - - - 2.00 4.00 2.00 4.00 - - - - - - - - - - - vptestnmd %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 6.00 3.00 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmd (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmd (%rax){1to16}, %zmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vptestnmq %zmm0, %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmq (%rax), %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmq (%rax){1to8}, %zmm1, %k2
+# CHECK-NEXT: - - - - - - - - 2.00 4.00 2.00 4.00 - - - - - - - - - - - vptestnmq %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 6.00 3.00 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmq (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmq (%rax){1to8}, %zmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vsubpd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubpd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubpd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vsubpd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubpd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubpd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vsubpd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubpd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubpd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vsubps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vsubps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vsubps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vucomiss %xmm16, %xmm17
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vucomiss (%rax), %xmm17
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vunpckhpd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhpd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhpd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vunpckhpd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhpd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhpd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vunpckhpd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhpd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhpd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vunpckhps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vunpckhps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vunpckhps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vunpcklpd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklpd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklpd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vunpcklpd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklpd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklpd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vunpcklpd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklpd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklpd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vunpcklps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vunpcklps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vunpcklps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bitalg.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bitalg.s
new file mode 100644
index 0000000000000..ebe71e453be60
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bitalg.s
@@ -0,0 +1,95 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+vpopcntb %zmm1, %zmm0
+vpopcntb (%rdi), %zmm0
+vpopcntb %zmm1, %zmm0 {%k1}
+vpopcntb (%rdi), %zmm0 {%k1}
+vpopcntb %zmm1, %zmm0 {%k1} {z}
+vpopcntb (%rdi), %zmm0 {%k1} {z}
+
+vpopcntw %zmm1, %zmm0
+vpopcntw (%rdi), %zmm0
+vpopcntw %zmm1, %zmm0 {%k1}
+vpopcntw (%rdi), %zmm0 {%k1}
+vpopcntw %zmm1, %zmm0 {%k1} {z}
+vpopcntw (%rdi), %zmm0 {%k1} {z}
+
+vpshufbitqmb %zmm16, %zmm17, %k2
+vpshufbitqmb (%rdi), %zmm17, %k2
+vpshufbitqmb %zmm16, %zmm17, %k2 {%k1}
+vpshufbitqmb (%rdi), %zmm17, %k2 {%k1}
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.50 vpopcntb %zmm1, %zmm0
+# CHECK-NEXT: 1 8 0.50 * vpopcntb (%rdi), %zmm0
+# CHECK-NEXT: 1 2 0.50 vpopcntb %zmm1, %zmm0 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpopcntb (%rdi), %zmm0 {%k1}
+# CHECK-NEXT: 1 2 0.50 vpopcntb %zmm1, %zmm0 {%k1} {z}
+# CHECK-NEXT: 1 9 0.50 * vpopcntb (%rdi), %zmm0 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpopcntw %zmm1, %zmm0
+# CHECK-NEXT: 1 8 0.50 * vpopcntw (%rdi), %zmm0
+# CHECK-NEXT: 1 2 0.50 vpopcntw %zmm1, %zmm0 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpopcntw (%rdi), %zmm0 {%k1}
+# CHECK-NEXT: 1 2 0.50 vpopcntw %zmm1, %zmm0 {%k1} {z}
+# CHECK-NEXT: 1 9 0.50 * vpopcntw (%rdi), %zmm0 {%k1} {z}
+# CHECK-NEXT: 1 3 1.00 vpshufbitqmb %zmm16, %zmm17, %k2
+# CHECK-NEXT: 1 10 1.00 * vpshufbitqmb (%rdi), %zmm17, %k2
+# CHECK-NEXT: 4 10 4.00 vpshufbitqmb %zmm16, %zmm17, %k2 {%k1}
+# CHECK-NEXT: 3 17 4.00 * vpshufbitqmb (%rdi), %zmm17, %k2 {%k1}
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 2.67 2.67 2.67 - - - - - 16.00 14.00 16.00 14.00 2.00 2.00 2.00 2.00 2.67 2.67 2.67 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpopcntb %zmm1, %zmm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntb (%rdi), %zmm0
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpopcntb %zmm1, %zmm0 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntb (%rdi), %zmm0 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpopcntb %zmm1, %zmm0 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntb (%rdi), %zmm0 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpopcntw %zmm1, %zmm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntw (%rdi), %zmm0
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpopcntw %zmm1, %zmm0 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntw (%rdi), %zmm0 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpopcntw %zmm1, %zmm0 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntw (%rdi), %zmm0 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshufbitqmb %zmm16, %zmm17, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufbitqmb (%rdi), %zmm17, %k2
+# CHECK-NEXT: - - - - - - - - 4.00 4.00 4.00 4.00 - - - - - - - - - - - vpshufbitqmb %zmm16, %zmm17, %k2 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 4.00 4.00 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufbitqmb (%rdi), %zmm17, %k2 {%k1}
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bitalgvl.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bitalgvl.s
new file mode 100644
index 0000000000000..313ddcd4328fc
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bitalgvl.s
@@ -0,0 +1,146 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+vpopcntb %xmm1, %xmm0
+vpopcntb (%rdi), %xmm0
+vpopcntb %xmm1, %xmm0 {%k1}
+vpopcntb (%rdi), %xmm0 {%k1}
+vpopcntb %xmm1, %xmm0 {%k1} {z}
+vpopcntb (%rdi), %xmm0 {%k1} {z}
+
+vpopcntb %ymm1, %ymm0
+vpopcntb (%rdi), %ymm0
+vpopcntb %ymm1, %ymm0 {%k1}
+vpopcntb (%rdi), %ymm0 {%k1}
+vpopcntb %ymm1, %ymm0 {%k1} {z}
+vpopcntb (%rdi), %ymm0 {%k1} {z}
+
+vpopcntw %xmm1, %xmm0
+vpopcntw (%rdi), %xmm0
+vpopcntw %xmm1, %xmm0 {%k1}
+vpopcntw (%rdi), %xmm0 {%k1}
+vpopcntw %xmm1, %xmm0 {%k1} {z}
+vpopcntw (%rdi), %xmm0 {%k1} {z}
+
+vpopcntw %ymm1, %ymm0
+vpopcntw (%rdi), %ymm0
+vpopcntw %ymm1, %ymm0 {%k1}
+vpopcntw (%rdi), %ymm0 {%k1}
+vpopcntw %ymm1, %ymm0 {%k1} {z}
+vpopcntw (%rdi), %ymm0 {%k1} {z}
+
+vpshufbitqmb %xmm16, %xmm17, %k2
+vpshufbitqmb (%rdi), %xmm17, %k2
+vpshufbitqmb %xmm16, %xmm17, %k2 {%k1}
+vpshufbitqmb (%rdi), %xmm17, %k2 {%k1}
+
+vpshufbitqmb %ymm16, %ymm17, %k2
+vpshufbitqmb (%rdi), %ymm17, %k2
+vpshufbitqmb %ymm16, %ymm17, %k2 {%k1}
+vpshufbitqmb (%rdi), %ymm17, %k2 {%k1}
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.25 vpopcntb %xmm1, %xmm0
+# CHECK-NEXT: 1 8 0.33 * vpopcntb (%rdi), %xmm0
+# CHECK-NEXT: 1 2 0.50 vpopcntb %xmm1, %xmm0 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpopcntb (%rdi), %xmm0 {%k1}
+# CHECK-NEXT: 1 2 0.50 vpopcntb %xmm1, %xmm0 {%k1} {z}
+# CHECK-NEXT: 1 9 0.50 * vpopcntb (%rdi), %xmm0 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpopcntb %ymm1, %ymm0
+# CHECK-NEXT: 1 8 0.33 * vpopcntb (%rdi), %ymm0
+# CHECK-NEXT: 1 2 0.50 vpopcntb %ymm1, %ymm0 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpopcntb (%rdi), %ymm0 {%k1}
+# CHECK-NEXT: 1 2 0.50 vpopcntb %ymm1, %ymm0 {%k1} {z}
+# CHECK-NEXT: 1 9 0.50 * vpopcntb (%rdi), %ymm0 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpopcntw %xmm1, %xmm0
+# CHECK-NEXT: 1 8 0.33 * vpopcntw (%rdi), %xmm0
+# CHECK-NEXT: 1 2 0.50 vpopcntw %xmm1, %xmm0 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpopcntw (%rdi), %xmm0 {%k1}
+# CHECK-NEXT: 1 2 0.50 vpopcntw %xmm1, %xmm0 {%k1} {z}
+# CHECK-NEXT: 1 9 0.50 * vpopcntw (%rdi), %xmm0 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpopcntw %ymm1, %ymm0
+# CHECK-NEXT: 1 8 0.33 * vpopcntw (%rdi), %ymm0
+# CHECK-NEXT: 1 2 0.50 vpopcntw %ymm1, %ymm0 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpopcntw (%rdi), %ymm0 {%k1}
+# CHECK-NEXT: 1 2 0.50 vpopcntw %ymm1, %ymm0 {%k1} {z}
+# CHECK-NEXT: 1 9 0.50 * vpopcntw (%rdi), %ymm0 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpshufbitqmb %xmm16, %xmm17, %k2
+# CHECK-NEXT: 1 10 0.50 * vpshufbitqmb (%rdi), %xmm17, %k2
+# CHECK-NEXT: 2 8 2.00 vpshufbitqmb %xmm16, %xmm17, %k2 {%k1}
+# CHECK-NEXT: 2 15 2.00 * vpshufbitqmb (%rdi), %xmm17, %k2 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpshufbitqmb %ymm16, %ymm17, %k2
+# CHECK-NEXT: 1 10 0.50 * vpshufbitqmb (%rdi), %ymm17, %k2
+# CHECK-NEXT: 2 8 2.00 vpshufbitqmb %ymm16, %ymm17, %k2 {%k1}
+# CHECK-NEXT: 2 15 2.00 * vpshufbitqmb (%rdi), %ymm17, %k2 {%k1}
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 5.33 5.33 5.33 - - - - - 20.00 18.00 20.00 18.00 4.00 4.00 4.00 4.00 5.33 5.33 5.33 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpopcntb %xmm1, %xmm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntb (%rdi), %xmm0
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpopcntb %xmm1, %xmm0 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntb (%rdi), %xmm0 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpopcntb %xmm1, %xmm0 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntb (%rdi), %xmm0 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpopcntb %ymm1, %ymm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntb (%rdi), %ymm0
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpopcntb %ymm1, %ymm0 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntb (%rdi), %ymm0 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpopcntb %ymm1, %ymm0 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntb (%rdi), %ymm0 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpopcntw %xmm1, %xmm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntw (%rdi), %xmm0
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpopcntw %xmm1, %xmm0 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntw (%rdi), %xmm0 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpopcntw %xmm1, %xmm0 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntw (%rdi), %xmm0 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpopcntw %ymm1, %ymm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntw (%rdi), %ymm0
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpopcntw %ymm1, %ymm0 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntw (%rdi), %ymm0 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpopcntw %ymm1, %ymm0 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntw (%rdi), %ymm0 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshufbitqmb %xmm16, %xmm17, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufbitqmb (%rdi), %xmm17, %k2
+# CHECK-NEXT: - - - - - - - - 2.00 2.00 2.00 2.00 - - - - - - - - - - - vpshufbitqmb %xmm16, %xmm17, %k2 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 2.00 2.00 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufbitqmb (%rdi), %xmm17, %k2 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshufbitqmb %ymm16, %ymm17, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufbitqmb (%rdi), %ymm17, %k2
+# CHECK-NEXT: - - - - - - - - 2.00 2.00 2.00 2.00 - - - - - - - - - - - vpshufbitqmb %ymm16, %ymm17, %k2 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 2.00 2.00 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufbitqmb (%rdi), %ymm17, %k2 {%k1}
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bw.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bw.s
new file mode 100644
index 0000000000000..04cca64162749
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bw.s
@@ -0,0 +1,1654 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+kaddd %k0, %k1, %k2
+kaddq %k0, %k1, %k2
+
+kandd %k0, %k1, %k2
+kandq %k0, %k1, %k2
+
+kandnd %k0, %k1, %k2
+kandnq %k0, %k1, %k2
+
+kmovd %k0, %k2
+kmovd (%rax), %k2
+kmovd %k0, (%rax)
+kmovd %eax, %k2
+kmovd %k0, %eax
+
+kmovq %k0, %k2
+kmovq (%rax), %k2
+kmovq %k0, (%rax)
+kmovq %rax, %k2
+kmovq %k0, %rax
+
+knotd %k0, %k2
+knotq %k0, %k2
+
+kord %k0, %k1, %k2
+korq %k0, %k1, %k2
+
+kortestd %k0, %k2
+kortestq %k0, %k2
+
+kshiftld $2, %k1, %k2
+kshiftlq $2, %k1, %k2
+
+kshiftrd $2, %k1, %k2
+kshiftrq $2, %k1, %k2
+
+ktestd %k0, %k2
+ktestq %k0, %k2
+
+kunpckdq %k0, %k1, %k2
+kunpckwd %k0, %k1, %k2
+
+kxnord %k0, %k1, %k2
+kxnorq %k0, %k1, %k2
+
+kxord %k0, %k1, %k2
+kxorq %k0, %k1, %k2
+
+vdbpsadbw $0, %zmm16, %zmm17, %zmm19
+vdbpsadbw $0, (%rax), %zmm17, %zmm19
+vdbpsadbw $0, %zmm16, %zmm17, %zmm19 {k1}
+vdbpsadbw $0, (%rax), %zmm17, %zmm19 {k1}
+vdbpsadbw $0, %zmm16, %zmm17, %zmm19 {z}{k1}
+vdbpsadbw $0, (%rax), %zmm17, %zmm19 {z}{k1}
+
+vmovdqu8 %zmm16, %zmm19
+vmovdqu8 (%rax), %zmm19
+vmovdqu8 %zmm16, (%rax)
+vmovdqu8 %zmm16, %zmm19 {k1}
+vmovdqu8 (%rax), %zmm19 {k1}
+vmovdqu8 %zmm16, (%rax) {k1}
+vmovdqu8 %zmm16, %zmm19 {z}{k1}
+vmovdqu8 (%rax), %zmm19 {z}{k1}
+
+vmovdqu16 %zmm16, %zmm19
+vmovdqu16 (%rax), %zmm19
+vmovdqu16 %zmm16, (%rax)
+vmovdqu16 %zmm16, %zmm19 {k1}
+vmovdqu16 (%rax), %zmm19 {k1}
+vmovdqu16 %zmm16, (%rax) {k1}
+vmovdqu16 %zmm16, %zmm19 {z}{k1}
+vmovdqu16 (%rax), %zmm19 {z}{k1}
+
+vpabsb %zmm16, %zmm19
+vpabsb (%rax), %zmm19
+vpabsb %zmm16, %zmm19 {k1}
+vpabsb (%rax), %zmm19 {k1}
+vpabsb %zmm16, %zmm19 {z}{k1}
+vpabsb (%rax), %zmm19 {z}{k1}
+
+vpabsw %zmm16, %zmm19
+vpabsw (%rax), %zmm19
+vpabsw %zmm16, %zmm19 {k1}
+vpabsw (%rax), %zmm19 {k1}
+vpabsw %zmm16, %zmm19 {z}{k1}
+vpabsw (%rax), %zmm19 {z}{k1}
+
+vpackssdw %zmm16, %zmm17, %zmm19
+vpackssdw (%rax), %zmm17, %zmm19
+vpackssdw %zmm16, %zmm17, %zmm19 {k1}
+vpackssdw (%rax), %zmm17, %zmm19 {k1}
+vpackssdw %zmm16, %zmm17, %zmm19 {z}{k1}
+vpackssdw (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpacksswb %zmm16, %zmm17, %zmm19
+vpacksswb (%rax), %zmm17, %zmm19
+vpacksswb %zmm16, %zmm17, %zmm19 {k1}
+vpacksswb (%rax), %zmm17, %zmm19 {k1}
+vpacksswb %zmm16, %zmm17, %zmm19 {z}{k1}
+vpacksswb (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpackusdw %zmm16, %zmm17, %zmm19
+vpackusdw (%rax), %zmm17, %zmm19
+vpackusdw %zmm16, %zmm17, %zmm19 {k1}
+vpackusdw (%rax), %zmm17, %zmm19 {k1}
+vpackusdw %zmm16, %zmm17, %zmm19 {z}{k1}
+vpackusdw (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpackuswb %zmm16, %zmm17, %zmm19
+vpackuswb (%rax), %zmm17, %zmm19
+vpackuswb %zmm16, %zmm17, %zmm19 {k1}
+vpackuswb (%rax), %zmm17, %zmm19 {k1}
+vpackuswb %zmm16, %zmm17, %zmm19 {z}{k1}
+vpackuswb (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpaddb %zmm16, %zmm17, %zmm19
+vpaddb (%rax), %zmm17, %zmm19
+vpaddb %zmm16, %zmm17, %zmm19 {k1}
+vpaddb (%rax), %zmm17, %zmm19 {k1}
+vpaddb %zmm16, %zmm17, %zmm19 {z}{k1}
+vpaddb (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpaddsb %zmm16, %zmm17, %zmm19
+vpaddsb (%rax), %zmm17, %zmm19
+vpaddsb %zmm16, %zmm17, %zmm19 {k1}
+vpaddsb (%rax), %zmm17, %zmm19 {k1}
+vpaddsb %zmm16, %zmm17, %zmm19 {z}{k1}
+vpaddsb (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpaddsw %zmm16, %zmm17, %zmm19
+vpaddsw (%rax), %zmm17, %zmm19
+vpaddsw %zmm16, %zmm17, %zmm19 {k1}
+vpaddsw (%rax), %zmm17, %zmm19 {k1}
+vpaddsw %zmm16, %zmm17, %zmm19 {z}{k1}
+vpaddsw (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpaddusb %zmm16, %zmm17, %zmm19
+vpaddusb (%rax), %zmm17, %zmm19
+vpaddusb %zmm16, %zmm17, %zmm19 {k1}
+vpaddusb (%rax), %zmm17, %zmm19 {k1}
+vpaddusb %zmm16, %zmm17, %zmm19 {z}{k1}
+vpaddusb (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpaddusw %zmm16, %zmm17, %zmm19
+vpaddusw (%rax), %zmm17, %zmm19
+vpaddusw %zmm16, %zmm17, %zmm19 {k1}
+vpaddusw (%rax), %zmm17, %zmm19 {k1}
+vpaddusw %zmm16, %zmm17, %zmm19 {z}{k1}
+vpaddusw (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpaddw %zmm16, %zmm17, %zmm19
+vpaddw (%rax), %zmm17, %zmm19
+vpaddw %zmm16, %zmm17, %zmm19 {k1}
+vpaddw (%rax), %zmm17, %zmm19 {k1}
+vpaddw %zmm16, %zmm17, %zmm19 {z}{k1}
+vpaddw (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpalignr $1, %zmm16, %zmm17, %zmm19
+vpalignr $1, (%rax), %zmm17, %zmm19
+vpalignr $1, %zmm16, %zmm17, %zmm19 {k1}
+vpalignr $1, (%rax), %zmm17, %zmm19 {k1}
+vpalignr $1, %zmm16, %zmm17, %zmm19 {z}{k1}
+vpalignr $1, (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpavgb %zmm16, %zmm17, %zmm19
+vpavgb (%rax), %zmm17, %zmm19
+vpavgb %zmm16, %zmm17, %zmm19 {k1}
+vpavgb (%rax), %zmm17, %zmm19 {k1}
+vpavgb %zmm16, %zmm17, %zmm19 {z}{k1}
+vpavgb (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpavgw %zmm16, %zmm17, %zmm19
+vpavgw (%rax), %zmm17, %zmm19
+vpavgw %zmm16, %zmm17, %zmm19 {k1}
+vpavgw (%rax), %zmm17, %zmm19 {k1}
+vpavgw %zmm16, %zmm17, %zmm19 {z}{k1}
+vpavgw (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpblendmb %zmm16, %zmm17, %zmm19
+vpblendmb (%rax), %zmm17, %zmm19
+vpblendmb %zmm16, %zmm17, %zmm19 {k1}
+vpblendmb (%rax), %zmm17, %zmm19 {k1}
+vpblendmb %zmm16, %zmm17, %zmm19 {z}{k1}
+vpblendmb (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpblendmw %zmm16, %zmm17, %zmm19
+vpblendmw (%rax), %zmm17, %zmm19
+vpblendmw %zmm16, %zmm17, %zmm19 {k1}
+vpblendmw (%rax), %zmm17, %zmm19 {k1}
+vpblendmw %zmm16, %zmm17, %zmm19 {z}{k1}
+vpblendmw (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpbroadcastb %xmm16, %zmm19
+vpbroadcastb (%rax), %zmm19
+vpbroadcastb %eax, %zmm19
+vpbroadcastb %xmm16, %zmm19 {k1}
+vpbroadcastb (%rax), %zmm19 {k1}
+vpbroadcastb %eax, %zmm19 {k1}
+vpbroadcastb %xmm16, %zmm19 {z}{k1}
+vpbroadcastb (%rax), %zmm19 {z}{k1}
+vpbroadcastb %eax, %zmm19 {z}{k1}
+
+vpbroadcastw %xmm16, %zmm19
+vpbroadcastw (%rax), %zmm19
+vpbroadcastw %eax, %zmm19
+vpbroadcastw %xmm16, %zmm19 {k1}
+vpbroadcastw (%rax), %zmm19 {k1}
+vpbroadcastw %eax, %zmm19 {k1}
+vpbroadcastw %xmm16, %zmm19 {z}{k1}
+vpbroadcastw (%rax), %zmm19 {z}{k1}
+vpbroadcastw %eax, %zmm19 {z}{k1}
+
+vpcmpb $0, %zmm0, %zmm1, %k2
+vpcmpb $0, (%rax), %zmm1, %k2
+vpcmpb $0, %zmm0, %zmm1, %k2 {k3}
+vpcmpb $0, (%rax), %zmm1, %k2 {k3}
+
+vpcmpeqb %zmm0, %zmm1, %k2
+vpcmpeqb (%rax), %zmm1, %k2
+vpcmpeqb %zmm0, %zmm1, %k2 {k3}
+vpcmpeqb (%rax), %zmm1, %k2 {k3}
+
+vpcmpeqw %zmm0, %zmm1, %k2
+vpcmpeqw (%rax), %zmm1, %k2
+vpcmpeqw %zmm0, %zmm1, %k2 {k3}
+vpcmpeqw (%rax), %zmm1, %k2 {k3}
+
+vpcmpgtb %zmm0, %zmm1, %k2
+vpcmpgtb (%rax), %zmm1, %k2
+vpcmpgtb %zmm0, %zmm1, %k2 {k3}
+vpcmpgtb (%rax), %zmm1, %k2 {k3}
+
+vpcmpgtw %zmm0, %zmm1, %k2
+vpcmpgtw (%rax), %zmm1, %k2
+vpcmpgtw %zmm0, %zmm1, %k2 {k3}
+vpcmpgtw (%rax), %zmm1, %k2 {k3}
+
+vpcmpub $0, %zmm0, %zmm1, %k2
+vpcmpub $0, (%rax), %zmm1, %k2
+vpcmpub $0, %zmm0, %zmm1, %k2 {k3}
+vpcmpub $0, (%rax), %zmm1, %k2 {k3}
+
+vpcmpuw $0, %zmm0, %zmm1, %k2
+vpcmpuw $0, (%rax), %zmm1, %k2
+vpcmpuw $0, %zmm0, %zmm1, %k2 {k3}
+vpcmpuw $0, (%rax), %zmm1, %k2 {k3}
+
+vpcmpw $0, %zmm0, %zmm1, %k2
+vpcmpw $0, (%rax), %zmm1, %k2
+vpcmpw $0, %zmm0, %zmm1, %k2 {k3}
+vpcmpw $0, (%rax), %zmm1, %k2 {k3}
+
+vpextrb $0, %xmm16, %rax
+vpextrb $0, %xmm16, (%rax)
+
+vpextrw $0, %xmm16, %rax
+vpextrw $0, %xmm16, (%rax)
+
+vpinsrb $0, %rax, %xmm16, %xmm19
+vpinsrb $0, (%rax), %xmm16, %xmm19
+
+vpinsrw $0, %rax, %xmm16, %xmm19
+vpinsrw $0, (%rax), %xmm16, %xmm19
+
+vpermw %zmm16, %zmm17, %zmm19
+vpermw (%rax), %zmm17, %zmm19
+vpermw %zmm16, %zmm17, %zmm19 {k1}
+vpermw (%rax), %zmm17, %zmm19 {k1}
+vpermw %zmm16, %zmm17, %zmm19 {z}{k1}
+vpermw (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpermi2w %zmm16, %zmm17, %zmm19
+vpermi2w (%rax), %zmm17, %zmm19
+vpermi2w %zmm16, %zmm17, %zmm19 {k1}
+vpermi2w (%rax), %zmm17, %zmm19 {k1}
+vpermi2w %zmm16, %zmm17, %zmm19 {z}{k1}
+vpermi2w (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpermt2w %zmm16, %zmm17, %zmm19
+vpermt2w (%rax), %zmm17, %zmm19
+vpermt2w %zmm16, %zmm17, %zmm19 {k1}
+vpermt2w (%rax), %zmm17, %zmm19 {k1}
+vpermt2w %zmm16, %zmm17, %zmm19 {z}{k1}
+vpermt2w (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpmaddubsw %zmm16, %zmm17, %zmm19
+vpmaddubsw (%rax), %zmm17, %zmm19
+vpmaddubsw %zmm16, %zmm17, %zmm19 {k1}
+vpmaddubsw (%rax), %zmm17, %zmm19 {k1}
+vpmaddubsw %zmm16, %zmm17, %zmm19 {z}{k1}
+vpmaddubsw (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpmaddwd %zmm16, %zmm17, %zmm19
+vpmaddwd (%rax), %zmm17, %zmm19
+vpmaddwd %zmm16, %zmm17, %zmm19 {k1}
+vpmaddwd (%rax), %zmm17, %zmm19 {k1}
+vpmaddwd %zmm16, %zmm17, %zmm19 {z}{k1}
+vpmaddwd (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpmaxsb %zmm16, %zmm17, %zmm19
+vpmaxsb (%rax), %zmm17, %zmm19
+vpmaxsb %zmm16, %zmm17, %zmm19 {k1}
+vpmaxsb (%rax), %zmm17, %zmm19 {k1}
+vpmaxsb %zmm16, %zmm17, %zmm19 {z}{k1}
+vpmaxsb (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpmaxsw %zmm16, %zmm17, %zmm19
+vpmaxsw (%rax), %zmm17, %zmm19
+vpmaxsw %zmm16, %zmm17, %zmm19 {k1}
+vpmaxsw (%rax), %zmm17, %zmm19 {k1}
+vpmaxsw %zmm16, %zmm17, %zmm19 {z}{k1}
+vpmaxsw (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpmaxub %zmm16, %zmm17, %zmm19
+vpmaxub (%rax), %zmm17, %zmm19
+vpmaxub %zmm16, %zmm17, %zmm19 {k1}
+vpmaxub (%rax), %zmm17, %zmm19 {k1}
+vpmaxub %zmm16, %zmm17, %zmm19 {z}{k1}
+vpmaxub (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpmaxuw %zmm16, %zmm17, %zmm19
+vpmaxuw (%rax), %zmm17, %zmm19
+vpmaxuw %zmm16, %zmm17, %zmm19 {k1}
+vpmaxuw (%rax), %zmm17, %zmm19 {k1}
+vpmaxuw %zmm16, %zmm17, %zmm19 {z}{k1}
+vpmaxuw (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpminsb %zmm16, %zmm17, %zmm19
+vpminsb (%rax), %zmm17, %zmm19
+vpminsb %zmm16, %zmm17, %zmm19 {k1}
+vpminsb (%rax), %zmm17, %zmm19 {k1}
+vpminsb %zmm16, %zmm17, %zmm19 {z}{k1}
+vpminsb (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpminsw %zmm16, %zmm17, %zmm19
+vpminsw (%rax), %zmm17, %zmm19
+vpminsw %zmm16, %zmm17, %zmm19 {k1}
+vpminsw (%rax), %zmm17, %zmm19 {k1}
+vpminsw %zmm16, %zmm17, %zmm19 {z}{k1}
+vpminsw (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpminub %zmm16, %zmm17, %zmm19
+vpminub (%rax), %zmm17, %zmm19
+vpminub %zmm16, %zmm17, %zmm19 {k1}
+vpminub (%rax), %zmm17, %zmm19 {k1}
+vpminub %zmm16, %zmm17, %zmm19 {z}{k1}
+vpminub (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpminuw %zmm16, %zmm17, %zmm19
+vpminuw (%rax), %zmm17, %zmm19
+vpminuw %zmm16, %zmm17, %zmm19 {k1}
+vpminuw (%rax), %zmm17, %zmm19 {k1}
+vpminuw %zmm16, %zmm17, %zmm19 {z}{k1}
+vpminuw (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpmovb2m %zmm0, %k0
+vpmovw2m %zmm0, %k0
+
+vpmovm2b %k0, %zmm0
+vpmovm2w %k0, %zmm0
+
+vpmovsxbw %ymm16, %zmm19
+vpmovsxbw (%rax), %zmm19
+vpmovsxbw %ymm16, %zmm19 {k1}
+vpmovsxbw (%rax), %zmm19 {k1}
+vpmovsxbw %ymm16, %zmm19 {z}{k1}
+vpmovsxbw (%rax), %zmm19 {z}{k1}
+
+vpmovswb %zmm16, %ymm19
+vpmovswb %zmm16, (%rax)
+vpmovswb %zmm16, %ymm19 {k1}
+vpmovswb %zmm16, (%rax) {k1}
+vpmovswb %zmm16, %ymm19 {z}{k1}
+
+vpmovuswb %zmm16, %ymm19
+vpmovuswb %zmm16, (%rax)
+vpmovuswb %zmm16, %ymm19 {k1}
+vpmovuswb %zmm16, (%rax) {k1}
+vpmovuswb %zmm16, %ymm19 {z}{k1}
+
+vpmovwb %zmm16, %ymm19
+vpmovwb %zmm16, (%rax)
+vpmovwb %zmm16, %ymm19 {k1}
+vpmovwb %zmm16, (%rax) {k1}
+vpmovwb %zmm16, %ymm19 {z}{k1}
+
+vpmovzxbw %ymm16, %zmm19
+vpmovzxbw (%rax), %zmm19
+vpmovzxbw %ymm16, %zmm19 {k1}
+vpmovzxbw (%rax), %zmm19 {k1}
+vpmovzxbw %ymm16, %zmm19 {z}{k1}
+vpmovzxbw (%rax), %zmm19 {z}{k1}
+
+vpmulhrsw %zmm16, %zmm17, %zmm19
+vpmulhrsw (%rax), %zmm17, %zmm19
+vpmulhrsw %zmm16, %zmm17, %zmm19 {k1}
+vpmulhrsw (%rax), %zmm17, %zmm19 {k1}
+vpmulhrsw %zmm16, %zmm17, %zmm19 {z}{k1}
+vpmulhrsw (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpmulhuw %zmm16, %zmm17, %zmm19
+vpmulhuw (%rax), %zmm17, %zmm19
+vpmulhuw %zmm16, %zmm17, %zmm19 {k1}
+vpmulhuw (%rax), %zmm17, %zmm19 {k1}
+vpmulhuw %zmm16, %zmm17, %zmm19 {z}{k1}
+vpmulhuw (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpmulhw %zmm16, %zmm17, %zmm19
+vpmulhw (%rax), %zmm17, %zmm19
+vpmulhw %zmm16, %zmm17, %zmm19 {k1}
+vpmulhw (%rax), %zmm17, %zmm19 {k1}
+vpmulhw %zmm16, %zmm17, %zmm19 {z}{k1}
+vpmulhw (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpmullw %zmm16, %zmm17, %zmm19
+vpmullw (%rax), %zmm17, %zmm19
+vpmullw %zmm16, %zmm17, %zmm19 {k1}
+vpmullw (%rax), %zmm17, %zmm19 {k1}
+vpmullw %zmm16, %zmm17, %zmm19 {z}{k1}
+vpmullw (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpsadbw %zmm16, %zmm17, %zmm19
+vpsadbw (%rax), %zmm17, %zmm19
+
+vpshufb %zmm16, %zmm17, %zmm19
+vpshufb (%rax), %zmm17, %zmm19
+vpshufb %zmm16, %zmm17, %zmm19 {k1}
+vpshufb (%rax), %zmm17, %zmm19 {k1}
+vpshufb %zmm16, %zmm17, %zmm19 {z}{k1}
+vpshufb (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpshufhw $0, %zmm16, %zmm19
+vpshufhw $0, (%rax), %zmm19
+vpshufhw $0, %zmm16, %zmm19 {k1}
+vpshufhw $0, (%rax), %zmm19 {k1}
+vpshufhw $0, %zmm16, %zmm19 {z}{k1}
+vpshufhw $0, (%rax), %zmm19 {z}{k1}
+
+vpshuflw $0, %zmm16, %zmm19
+vpshuflw $0, (%rax), %zmm19
+vpshuflw $0, %zmm16, %zmm19 {k1}
+vpshuflw $0, (%rax), %zmm19 {k1}
+vpshuflw $0, %zmm16, %zmm19 {z}{k1}
+vpshuflw $0, (%rax), %zmm19 {z}{k1}
+
+vpslldq $1, %zmm16, %zmm19
+vpslldq $1, (%rax), %zmm19
+
+vpsllvw %zmm16, %zmm17, %zmm19
+vpsllvw (%rax), %zmm17, %zmm19
+vpsllvw %zmm16, %zmm17, %zmm19 {k1}
+vpsllvw (%rax), %zmm17, %zmm19 {k1}
+vpsllvw %zmm16, %zmm17, %zmm19 {z}{k1}
+vpsllvw (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpsllw $0, %zmm16, %zmm19
+vpsllw $0, (%rax), %zmm19
+vpsllw $0, %zmm16, %zmm19 {k1}
+vpsllw $0, (%rax), %zmm19 {k1}
+vpsllw $0, %zmm16, %zmm19 {z}{k1}
+vpsllw $0, (%rax), %zmm19 {z}{k1}
+
+vpsllw %xmm16, %zmm17, %zmm19
+vpsllw (%rax), %zmm17, %zmm19
+vpsllw %xmm16, %zmm17, %zmm19 {k1}
+vpsllw (%rax), %zmm17, %zmm19 {k1}
+vpsllw %xmm16, %zmm17, %zmm19 {z}{k1}
+vpsllw (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpsravw %zmm16, %zmm17, %zmm19
+vpsravw (%rax), %zmm17, %zmm19
+vpsravw %zmm16, %zmm17, %zmm19 {k1}
+vpsravw (%rax), %zmm17, %zmm19 {k1}
+vpsravw %zmm16, %zmm17, %zmm19 {z}{k1}
+vpsravw (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpsraw $0, %zmm16, %zmm19
+vpsraw $0, (%rax), %zmm19
+vpsraw $0, %zmm16, %zmm19 {k1}
+vpsraw $0, (%rax), %zmm19 {k1}
+vpsraw $0, %zmm16, %zmm19 {z}{k1}
+vpsraw $0, (%rax), %zmm19 {z}{k1}
+
+vpsraw %xmm16, %zmm17, %zmm19
+vpsraw (%rax), %zmm17, %zmm19
+vpsraw %xmm16, %zmm17, %zmm19 {k1}
+vpsraw (%rax), %zmm17, %zmm19 {k1}
+vpsraw %xmm16, %zmm17, %zmm19 {z}{k1}
+vpsraw (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpsrldq $1, %zmm16, %zmm19
+vpsrldq $1, (%rax), %zmm19
+
+vpsrlvw %zmm16, %zmm17, %zmm19
+vpsrlvw (%rax), %zmm17, %zmm19
+vpsrlvw %zmm16, %zmm17, %zmm19 {k1}
+vpsrlvw (%rax), %zmm17, %zmm19 {k1}
+vpsrlvw %zmm16, %zmm17, %zmm19 {z}{k1}
+vpsrlvw (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpsrlw $0, %zmm16, %zmm19
+vpsrlw $0, (%rax), %zmm19
+vpsrlw $0, %zmm16, %zmm19 {k1}
+vpsrlw $0, (%rax), %zmm19 {k1}
+vpsrlw $0, %zmm16, %zmm19 {z}{k1}
+vpsrlw $0, (%rax), %zmm19 {z}{k1}
+
+vpsrlw %xmm16, %zmm17, %zmm19
+vpsrlw (%rax), %zmm17, %zmm19
+vpsrlw %xmm16, %zmm17, %zmm19 {k1}
+vpsrlw (%rax), %zmm17, %zmm19 {k1}
+vpsrlw %xmm16, %zmm17, %zmm19 {z}{k1}
+vpsrlw (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpsubb %zmm16, %zmm17, %zmm19
+vpsubb (%rax), %zmm17, %zmm19
+vpsubb %zmm16, %zmm17, %zmm19 {k1}
+vpsubb (%rax), %zmm17, %zmm19 {k1}
+vpsubb %zmm16, %zmm17, %zmm19 {z}{k1}
+vpsubb (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpsubsb %zmm16, %zmm17, %zmm19
+vpsubsb (%rax), %zmm17, %zmm19
+vpsubsb %zmm16, %zmm17, %zmm19 {k1}
+vpsubsb (%rax), %zmm17, %zmm19 {k1}
+vpsubsb %zmm16, %zmm17, %zmm19 {z}{k1}
+vpsubsb (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpsubsw %zmm16, %zmm17, %zmm19
+vpsubsw (%rax), %zmm17, %zmm19
+vpsubsw %zmm16, %zmm17, %zmm19 {k1}
+vpsubsw (%rax), %zmm17, %zmm19 {k1}
+vpsubsw %zmm16, %zmm17, %zmm19 {z}{k1}
+vpsubsw (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpsubusb %zmm16, %zmm17, %zmm19
+vpsubusb (%rax), %zmm17, %zmm19
+vpsubusb %zmm16, %zmm17, %zmm19 {k1}
+vpsubusb (%rax), %zmm17, %zmm19 {k1}
+vpsubusb %zmm16, %zmm17, %zmm19 {z}{k1}
+vpsubusb (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpsubusw %zmm16, %zmm17, %zmm19
+vpsubusw (%rax), %zmm17, %zmm19
+vpsubusw %zmm16, %zmm17, %zmm19 {k1}
+vpsubusw (%rax), %zmm17, %zmm19 {k1}
+vpsubusw %zmm16, %zmm17, %zmm19 {z}{k1}
+vpsubusw (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpsubw %zmm16, %zmm17, %zmm19
+vpsubw (%rax), %zmm17, %zmm19
+vpsubw %zmm16, %zmm17, %zmm19 {k1}
+vpsubw (%rax), %zmm17, %zmm19 {k1}
+vpsubw %zmm16, %zmm17, %zmm19 {z}{k1}
+vpsubw (%rax), %zmm17, %zmm19 {z}{k1}
+
+vptestmb %zmm0, %zmm1, %k2
+vptestmb (%rax), %zmm1, %k2
+vptestmb %zmm0, %zmm1, %k2 {k3}
+vptestmb (%rax), %zmm1, %k2 {k3}
+
+vptestmw %zmm0, %zmm1, %k2
+vptestmw (%rax), %zmm1, %k2
+vptestmw %zmm0, %zmm1, %k2 {k3}
+vptestmw (%rax), %zmm1, %k2 {k3}
+
+vptestnmb %zmm0, %zmm1, %k2
+vptestnmb (%rax), %zmm1, %k2
+vptestnmb %zmm0, %zmm1, %k2 {k3}
+vptestnmb (%rax), %zmm1, %k2 {k3}
+
+vptestnmw %zmm0, %zmm1, %k2
+vptestnmw (%rax), %zmm1, %k2
+vptestnmw %zmm0, %zmm1, %k2 {k3}
+vptestnmw (%rax), %zmm1, %k2 {k3}
+
+vpunpckhbw %zmm16, %zmm17, %zmm19
+vpunpckhbw (%rax), %zmm17, %zmm19
+vpunpckhbw %zmm16, %zmm17, %zmm19 {k1}
+vpunpckhbw (%rax), %zmm17, %zmm19 {k1}
+vpunpckhbw %zmm16, %zmm17, %zmm19 {z}{k1}
+vpunpckhbw (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpunpckhwd %zmm16, %zmm17, %zmm19
+vpunpckhwd (%rax), %zmm17, %zmm19
+vpunpckhwd %zmm16, %zmm17, %zmm19 {k1}
+vpunpckhwd (%rax), %zmm17, %zmm19 {k1}
+vpunpckhwd %zmm16, %zmm17, %zmm19 {z}{k1}
+vpunpckhwd (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpunpcklbw %zmm16, %zmm17, %zmm19
+vpunpcklbw (%rax), %zmm17, %zmm19
+vpunpcklbw %zmm16, %zmm17, %zmm19 {k1}
+vpunpcklbw (%rax), %zmm17, %zmm19 {k1}
+vpunpcklbw %zmm16, %zmm17, %zmm19 {z}{k1}
+vpunpcklbw (%rax), %zmm17, %zmm19 {z}{k1}
+
+vpunpcklwd %zmm16, %zmm17, %zmm19
+vpunpcklwd (%rax), %zmm17, %zmm19
+vpunpcklwd %zmm16, %zmm17, %zmm19 {k1}
+vpunpcklwd (%rax), %zmm17, %zmm19 {k1}
+vpunpcklwd %zmm16, %zmm17, %zmm19 {z}{k1}
+vpunpcklwd (%rax), %zmm17, %zmm19 {z}{k1}
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.25 kaddd %k0, %k1, %k2
+# CHECK-NEXT: 1 1 0.25 kaddq %k0, %k1, %k2
+# CHECK-NEXT: 1 1 0.25 kandd %k0, %k1, %k2
+# CHECK-NEXT: 1 1 0.25 kandq %k0, %k1, %k2
+# CHECK-NEXT: 1 1 0.25 kandnd %k0, %k1, %k2
+# CHECK-NEXT: 1 1 0.25 kandnq %k0, %k1, %k2
+# CHECK-NEXT: 1 1 1.00 kmovd %k0, %k2
+# CHECK-NEXT: 1 5 0.33 * kmovd (%rax), %k2
+# CHECK-NEXT: 1 1 0.50 * kmovd %k0, (%rax)
+# CHECK-NEXT: 1 1 1.00 kmovd %eax, %k2
+# CHECK-NEXT: 1 1 1.00 kmovd %k0, %eax
+# CHECK-NEXT: 1 1 1.00 kmovq %k0, %k2
+# CHECK-NEXT: 1 5 0.33 * kmovq (%rax), %k2
+# CHECK-NEXT: 1 1 0.50 * kmovq %k0, (%rax)
+# CHECK-NEXT: 1 1 1.00 kmovq %rax, %k2
+# CHECK-NEXT: 1 1 1.00 kmovq %k0, %rax
+# CHECK-NEXT: 1 1 0.25 knotd %k0, %k2
+# CHECK-NEXT: 1 1 0.25 knotq %k0, %k2
+# CHECK-NEXT: 1 1 0.25 kord %k0, %k1, %k2
+# CHECK-NEXT: 1 1 0.25 korq %k0, %k1, %k2
+# CHECK-NEXT: 1 1 0.25 kortestd %k0, %k2
+# CHECK-NEXT: 1 1 0.25 kortestq %k0, %k2
+# CHECK-NEXT: 1 1 0.50 kshiftld $2, %k1, %k2
+# CHECK-NEXT: 1 1 0.50 kshiftlq $2, %k1, %k2
+# CHECK-NEXT: 1 1 0.50 kshiftrd $2, %k1, %k2
+# CHECK-NEXT: 1 1 0.50 kshiftrq $2, %k1, %k2
+# CHECK-NEXT: 1 1 0.25 ktestd %k0, %k2
+# CHECK-NEXT: 1 1 0.25 ktestq %k0, %k2
+# CHECK-NEXT: 1 1 0.50 kunpckdq %k0, %k1, %k2
+# CHECK-NEXT: 1 1 0.50 kunpckwd %k0, %k1, %k2
+# CHECK-NEXT: 1 1 0.25 kxnord %k0, %k1, %k2
+# CHECK-NEXT: 1 1 0.25 kxnorq %k0, %k1, %k2
+# CHECK-NEXT: 1 1 0.25 kxord %k0, %k1, %k2
+# CHECK-NEXT: 1 1 0.25 kxorq %k0, %k1, %k2
+# CHECK-NEXT: 5 3 3.00 vdbpsadbw $0, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 5 10 3.00 * vdbpsadbw $0, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 5 4 3.00 vdbpsadbw $0, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 5 11 3.00 * vdbpsadbw $0, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 5 3 3.00 vdbpsadbw $0, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 5 10 3.00 * vdbpsadbw $0, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 0 0.25 vmovdqu8 %zmm16, %zmm19
+# CHECK-NEXT: 1 8 0.33 * vmovdqu8 (%rax), %zmm19
+# CHECK-NEXT: 1 1 0.33 * vmovdqu8 %zmm16, (%rax)
+# CHECK-NEXT: 1 0 0.25 vmovdqu8 %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vmovdqu8 (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.33 * vmovdqu8 %zmm16, (%rax) {%k1}
+# CHECK-NEXT: 1 0 0.25 vmovdqu8 %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vmovdqu8 (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 0 0.25 vmovdqu16 %zmm16, %zmm19
+# CHECK-NEXT: 1 8 0.33 * vmovdqu16 (%rax), %zmm19
+# CHECK-NEXT: 1 1 0.33 * vmovdqu16 %zmm16, (%rax)
+# CHECK-NEXT: 1 0 0.25 vmovdqu16 %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vmovdqu16 (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.33 * vmovdqu16 %zmm16, (%rax) {%k1}
+# CHECK-NEXT: 1 0 0.25 vmovdqu16 %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vmovdqu16 (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpabsb %zmm16, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpabsb (%rax), %zmm19
+# CHECK-NEXT: 1 2 0.50 vpabsb %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpabsb (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpabsb %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpabsb (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpabsw %zmm16, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpabsw (%rax), %zmm19
+# CHECK-NEXT: 1 2 0.50 vpabsw %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpabsw (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpabsw %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpabsw (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 1.00 vpackssdw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vpackssdw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 1.00 vpackssdw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpackssdw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 1.00 vpackssdw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 1.00 * vpackssdw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 1.00 vpacksswb %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vpacksswb (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 1.00 vpacksswb %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpacksswb (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 1.00 vpacksswb %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 1.00 * vpacksswb (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 1.00 vpackusdw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vpackusdw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 1.00 vpackusdw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpackusdw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 1.00 vpackusdw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 1.00 * vpackusdw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 1.00 vpackuswb %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vpackuswb (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 1.00 vpackuswb %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpackuswb (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 1.00 vpackuswb %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 1.00 * vpackuswb (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpaddb %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpaddb (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 0.50 vpaddb %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpaddb (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpaddb %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpaddb (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpaddsb %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpaddsb (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 0.50 vpaddsb %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpaddsb (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpaddsb %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpaddsb (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpaddsw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpaddsw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 0.50 vpaddsw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpaddsw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpaddsw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpaddsw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpaddusb %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpaddusb (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 0.50 vpaddusb %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpaddusb (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpaddusb %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpaddusb (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpaddusw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpaddusw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 0.50 vpaddusw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpaddusw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpaddusw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpaddusw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpaddw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpaddw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 0.50 vpaddw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpaddw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpaddw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpaddw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 1.00 vpalignr $1, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vpalignr $1, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 0.50 vpalignr $1, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpalignr $1, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 2 0.50 vpalignr $1, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 0.50 * vpalignr $1, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpavgb %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpavgb (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 0.50 vpavgb %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpavgb (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpavgb %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpavgb (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpavgw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpavgw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 0.50 vpavgw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpavgw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpavgw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpavgw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpblendmb %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpblendmb (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 0.25 vpblendmb %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpblendmb (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpblendmb %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpblendmb (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpblendmw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpblendmw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 0.25 vpblendmw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpblendmw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpblendmw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpblendmw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 5 4.00 vpbroadcastb %xmm16, %zmm19
+# CHECK-NEXT: 2 12 4.00 * vpbroadcastb (%rax), %zmm19
+# CHECK-NEXT: 1 3 0.50 vpbroadcastb %eax, %zmm19
+# CHECK-NEXT: 2 4 4.00 vpbroadcastb %xmm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 11 4.00 * vpbroadcastb (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 2 4 4.00 vpbroadcastb %eax, %zmm19 {%k1}
+# CHECK-NEXT: 2 5 4.00 vpbroadcastb %xmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 12 4.00 * vpbroadcastb (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpbroadcastb %eax, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 5 4.00 vpbroadcastw %xmm16, %zmm19
+# CHECK-NEXT: 2 12 4.00 * vpbroadcastw (%rax), %zmm19
+# CHECK-NEXT: 1 3 0.50 vpbroadcastw %eax, %zmm19
+# CHECK-NEXT: 2 4 4.00 vpbroadcastw %xmm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 11 4.00 * vpbroadcastw (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 2 4 4.00 vpbroadcastw %eax, %zmm19 {%k1}
+# CHECK-NEXT: 2 5 4.00 vpbroadcastw %xmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 12 4.00 * vpbroadcastw (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpbroadcastw %eax, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpcmpeqb %zmm0, %zmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vpcmpeqb (%rax), %zmm1, %k2
+# CHECK-NEXT: 4 4 4.50 vpcmpeqb %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 4 11 4.50 * vpcmpeqb (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.50 vpcmpeqb %zmm0, %zmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vpcmpeqb (%rax), %zmm1, %k2
+# CHECK-NEXT: 4 4 4.50 vpcmpeqb %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 4 11 4.50 * vpcmpeqb (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.50 vpcmpeqw %zmm0, %zmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vpcmpeqw (%rax), %zmm1, %k2
+# CHECK-NEXT: 4 4 4.50 vpcmpeqw %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 4 11 4.50 * vpcmpeqw (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpgtb %zmm0, %zmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vpcmpgtb (%rax), %zmm1, %k2
+# CHECK-NEXT: 4 4 4.50 vpcmpgtb %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 4 11 4.50 * vpcmpgtb (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpgtw %zmm0, %zmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vpcmpgtw (%rax), %zmm1, %k2
+# CHECK-NEXT: 4 4 4.50 vpcmpgtw %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 4 11 4.50 * vpcmpgtw (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.50 vpcmpequb %zmm0, %zmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vpcmpequb (%rax), %zmm1, %k2
+# CHECK-NEXT: 4 4 4.50 vpcmpequb %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 4 11 4.50 * vpcmpequb (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.50 vpcmpequw %zmm0, %zmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vpcmpequw (%rax), %zmm1, %k2
+# CHECK-NEXT: 4 4 4.50 vpcmpequw %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 4 11 4.50 * vpcmpequw (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.50 vpcmpeqw %zmm0, %zmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vpcmpeqw (%rax), %zmm1, %k2
+# CHECK-NEXT: 4 4 4.50 vpcmpeqw %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 4 11 4.50 * vpcmpeqw (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 2.00 vpextrb $0, %xmm16, %eax
+# CHECK-NEXT: 1 3 2.00 * vpextrb $0, %xmm16, (%rax)
+# CHECK-NEXT: 1 1 2.00 vpextrw $0, %xmm16, %eax
+# CHECK-NEXT: 1 3 2.00 * vpextrw $0, %xmm16, (%rax)
+# CHECK-NEXT: 1 2 0.50 vpinsrb $0, %eax, %xmm16, %xmm19
+# CHECK-NEXT: 1 9 0.50 * vpinsrb $0, (%rax), %xmm16, %xmm19
+# CHECK-NEXT: 1 2 0.50 vpinsrw $0, %eax, %xmm16, %xmm19
+# CHECK-NEXT: 1 9 0.50 * vpinsrw $0, (%rax), %xmm16, %xmm19
+# CHECK-NEXT: 8 8 8.00 vpermw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 8 15 8.00 * vpermw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 8 8 8.00 vpermw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 8 15 8.00 * vpermw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 8 8 8.00 vpermw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 8 15 8.00 * vpermw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 16 16 16.00 vpermi2w %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 16 23 16.00 * vpermi2w (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 16 16 16.00 vpermi2w %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 16 23 16.00 * vpermi2w (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 16 16 16.00 vpermi2w %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 16 23 16.00 * vpermi2w (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 16 16 16.00 vpermt2w %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 16 23 16.00 * vpermt2w (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 16 16 16.00 vpermt2w %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 16 23 16.00 * vpermt2w (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 16 16 16.00 vpermt2w %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 16 23 16.00 * vpermt2w (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 1.00 vpmaddubsw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vpmaddubsw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 4 1.00 vpmaddubsw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vpmaddubsw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 3 1.00 vpmaddubsw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vpmaddubsw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 1.00 vpmaddwd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vpmaddwd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 4 0.50 vpmaddwd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vpmaddwd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 3 1.00 vpmaddwd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vpmaddwd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpmaxsb %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpmaxsb (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 0.50 vpmaxsb %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpmaxsb (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpmaxsb %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpmaxsb (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpmaxsw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpmaxsw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 0.50 vpmaxsw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpmaxsw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpmaxsw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpmaxsw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpmaxub %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpmaxub (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 0.50 vpmaxub %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpmaxub (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpmaxub %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpmaxub (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpmaxuw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpmaxuw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 0.50 vpmaxuw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpmaxuw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpmaxuw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpmaxuw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpminsb %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpminsb (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 0.50 vpminsb %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpminsb (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpminsb %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpminsb (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpminsw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpminsw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 0.50 vpminsw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpminsw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpminsw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpminsw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpminub %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpminub (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 0.50 vpminub %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpminub (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpminub %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpminub (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpminuw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpminuw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 0.50 vpminuw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpminuw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpminuw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpminuw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 1.00 vpmovb2m %zmm0, %k0
+# CHECK-NEXT: 1 1 1.00 vpmovw2m %zmm0, %k0
+# CHECK-NEXT: 1 0 0.25 vpmovm2b %k0, %zmm0
+# CHECK-NEXT: 1 0 0.25 vpmovm2w %k0, %zmm0
+# CHECK-NEXT: 1 3 0.50 vpmovsxbw %ymm16, %zmm19
+# CHECK-NEXT: 1 10 0.50 * vpmovsxbw (%rax), %zmm19
+# CHECK-NEXT: 1 3 0.50 vpmovsxbw %ymm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovsxbw (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovsxbw %ymm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmovsxbw (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovswb %zmm16, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpmovswb %zmm16, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovswb %zmm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovswb %zmm16, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovswb %zmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovuswb %zmm16, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpmovuswb %zmm16, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovuswb %zmm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovuswb %zmm16, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovuswb %zmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovwb %zmm16, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpmovwb %zmm16, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovwb %zmm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovwb %zmm16, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovwb %zmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovzxbw %ymm16, %zmm19
+# CHECK-NEXT: 1 10 0.50 * vpmovzxbw (%rax), %zmm19
+# CHECK-NEXT: 1 3 0.50 vpmovzxbw %ymm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovzxbw (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovzxbw %ymm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmovzxbw (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 1.00 vpmulhrsw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vpmulhrsw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 4 1.00 vpmulhrsw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vpmulhrsw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 3 1.00 vpmulhrsw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vpmulhrsw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 1.00 vpmulhuw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vpmulhuw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 4 1.00 vpmulhuw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vpmulhuw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 3 1.00 vpmulhuw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vpmulhuw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 1.00 vpmulhw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vpmulhw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 4 1.00 vpmulhw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vpmulhw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 3 1.00 vpmulhw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vpmulhw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 1.00 vpmullw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vpmullw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 4 1.00 vpmullw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vpmullw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 3 1.00 vpmullw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vpmullw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 2.00 vpsadbw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 10 2.00 * vpsadbw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 1 1.00 vpshufb %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vpshufb (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 1.00 vpshufb %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpshufb (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpshufb %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpshufb (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 1.00 vpshufhw $0, %zmm16, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vpshufhw $0, (%rax), %zmm19
+# CHECK-NEXT: 1 2 1.00 vpshufhw $0, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpshufhw $0, (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpshufhw $0, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpshufhw $0, (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 1.00 vpshuflw $0, %zmm16, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vpshuflw $0, (%rax), %zmm19
+# CHECK-NEXT: 1 2 1.00 vpshuflw $0, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpshuflw $0, (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpshuflw $0, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpshuflw $0, (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 1.00 vpslldq $1, %zmm16, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vpslldq $1, (%rax), %zmm19
+# CHECK-NEXT: 1 1 4.00 vpsllvw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 4.00 * vpsllvw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 1.00 vpsllvw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpsllvw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpsllvw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpsllvw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 1.00 vpsllw $0, %zmm16, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vpsllw $0, (%rax), %zmm19
+# CHECK-NEXT: 1 2 1.00 vpsllw $0, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpsllw $0, (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpsllw $0, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpsllw $0, (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 1.00 vpsllw %xmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vpsllw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 4 1.00 vpsllw %xmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vpsllw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 3 1.00 vpsllw %xmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vpsllw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 4.00 vpsravw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 4.00 * vpsravw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 1.00 vpsravw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpsravw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpsravw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpsravw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 1.00 vpsraw $0, %zmm16, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vpsraw $0, (%rax), %zmm19
+# CHECK-NEXT: 1 2 1.00 vpsraw $0, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpsraw $0, (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpsraw $0, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpsraw $0, (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 1.00 vpsraw %xmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vpsraw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 4 1.00 vpsraw %xmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vpsraw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 3 1.00 vpsraw %xmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vpsraw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 1.00 vpsrldq $1, %zmm16, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vpsrldq $1, (%rax), %zmm19
+# CHECK-NEXT: 1 1 4.00 vpsrlvw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 4.00 * vpsrlvw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 1.00 vpsrlvw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpsrlvw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpsrlvw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpsrlvw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 1.00 vpsrlw $0, %zmm16, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vpsrlw $0, (%rax), %zmm19
+# CHECK-NEXT: 1 2 1.00 vpsrlw $0, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpsrlw $0, (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpsrlw $0, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpsrlw $0, (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 1.00 vpsrlw %xmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vpsrlw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 4 1.00 vpsrlw %xmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vpsrlw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 3 1.00 vpsrlw %xmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vpsrlw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpsubb %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpsubb (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 0.50 vpsubb %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpsubb (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpsubb %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpsubb (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpsubsb %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpsubsb (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 0.50 vpsubsb %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpsubsb (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpsubsb %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpsubsb (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpsubsw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpsubsw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 0.50 vpsubsw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpsubsw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpsubsw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpsubsw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpsubusb %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpsubusb (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 0.50 vpsubusb %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpsubusb (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpsubusb %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpsubusb (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpsubusw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpsubusw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 0.50 vpsubusw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpsubusw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpsubusw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpsubusw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpsubw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpsubw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 0.50 vpsubw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpsubw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpsubw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpsubw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vptestmb %zmm0, %zmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestmb (%rax), %zmm1, %k2
+# CHECK-NEXT: 4 4 3.00 vptestmb %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 3 11 4.50 * vptestmb (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vptestmw %zmm0, %zmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestmw (%rax), %zmm1, %k2
+# CHECK-NEXT: 4 4 3.00 vptestmw %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 3 11 4.50 * vptestmw (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vptestnmb %zmm0, %zmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestnmb (%rax), %zmm1, %k2
+# CHECK-NEXT: 4 4 3.00 vptestnmb %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 3 11 4.50 * vptestnmb (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vptestnmw %zmm0, %zmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestnmw (%rax), %zmm1, %k2
+# CHECK-NEXT: 4 4 3.00 vptestnmw %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 3 11 4.50 * vptestnmw (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 1.00 vpunpckhbw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vpunpckhbw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 1.00 vpunpckhbw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpunpckhbw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpunpckhbw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpunpckhbw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 1.00 vpunpckhwd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vpunpckhwd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 1.00 vpunpckhwd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpunpckhwd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpunpckhwd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpunpckhwd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 1.00 vpunpcklbw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vpunpcklbw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 1.00 vpunpcklbw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpunpcklbw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpunpcklbw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpunpcklbw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 1.00 vpunpcklwd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vpunpcklwd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 1.00 vpunpcklwd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpunpcklwd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpunpcklwd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpunpcklwd (%rax), %zmm17, %zmm19 {%k1} {z}
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 78.00 78.00 78.00 8.00 8.00 8.00 8.00 - 607.50 566.00 605.50 564.00 59.00 59.00 59.00 59.00 75.33 75.33 75.33 2.50 2.50 2.50 2.50
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - kaddd %k0, %k1, %k2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - kaddq %k0, %k1, %k2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - kandd %k0, %k1, %k2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - kandq %k0, %k1, %k2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - kandnd %k0, %k1, %k2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - kandnq %k0, %k1, %k2
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - kmovd %k0, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - kmovd (%rax), %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 kmovd %k0, (%rax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - kmovd %eax, %k2
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - kmovd %k0, %eax
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - kmovq %k0, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - kmovq (%rax), %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 kmovq %k0, (%rax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - kmovq %rax, %k2
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - kmovq %k0, %rax
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - knotd %k0, %k2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - knotq %k0, %k2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - kord %k0, %k1, %k2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - korq %k0, %k1, %k2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - kortestd %k0, %k2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - kortestq %k0, %k2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - kshiftld $2, %k1, %k2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - kshiftlq $2, %k1, %k2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - kshiftrd $2, %k1, %k2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - kshiftrq $2, %k1, %k2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - ktestd %k0, %k2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - ktestq %k0, %k2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - kunpckdq %k0, %k1, %k2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - kunpckwd %k0, %k1, %k2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - kxnord %k0, %k1, %k2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - kxnorq %k0, %k1, %k2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - kxord %k0, %k1, %k2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - kxorq %k0, %k1, %k2
+# CHECK-NEXT: - - - - - - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - vdbpsadbw $0, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 3.00 3.00 3.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdbpsadbw $0, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - vdbpsadbw $0, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 3.00 3.00 3.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdbpsadbw $0, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - vdbpsadbw $0, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 3.00 3.00 3.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdbpsadbw $0, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu8 %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu8 (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqu8 %zmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu8 %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu8 (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqu8 %zmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu8 %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu8 (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu16 %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu16 (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqu16 %zmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu16 %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu16 (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqu16 %zmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu16 %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu16 (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpabsb %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsb (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpabsb %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsb (%rax), %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpabsb %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsb (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpabsw %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsw (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpabsw %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsw (%rax), %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpabsw %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsw (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpackssdw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackssdw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpackssdw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackssdw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpackssdw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackssdw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpacksswb %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpacksswb (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpacksswb %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpacksswb (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpacksswb %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpacksswb (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpackusdw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackusdw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpackusdw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackusdw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpackusdw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackusdw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpackuswb %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackuswb (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpackuswb %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackuswb (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpackuswb %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackuswb (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddb %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddb (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddb %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddb (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddb %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddb (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddsb %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddsb (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddsb %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddsb (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddsb %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddsb (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddsw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddsw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddsw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddsw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddsw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddsw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddusb %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddusb (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddusb %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddusb (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddusb %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddusb (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddusw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddusw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddusw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddusw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddusw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddusw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpalignr $1, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpalignr $1, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpalignr $1, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpalignr $1, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpalignr $1, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpalignr $1, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpavgb %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpavgb (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpavgb %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpavgb (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpavgb %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpavgb (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpavgw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpavgw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpavgw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpavgw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpavgw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpavgw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpblendmb %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpblendmb (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpblendmb %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpblendmb (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpblendmb %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpblendmb (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpblendmw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpblendmw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpblendmw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpblendmw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpblendmw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpblendmw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpbroadcastb %xmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastb (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpbroadcastb %eax, %zmm19
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpbroadcastb %xmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastb (%rax), %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpbroadcastb %eax, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpbroadcastb %xmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastb (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpbroadcastb %eax, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpbroadcastw %xmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastw (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpbroadcastw %eax, %zmm19
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpbroadcastw %xmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastw (%rax), %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpbroadcastw %eax, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpbroadcastw %xmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastw (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpbroadcastw %eax, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpcmpeqb %zmm0, %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqb (%rax), %zmm1, %k2
+# CHECK-NEXT: - - - - - - - - 3.00 6.00 3.00 6.00 - - - - - - - - - - - vpcmpeqb %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 6.00 3.00 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqb (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpcmpeqb %zmm0, %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqb (%rax), %zmm1, %k2
+# CHECK-NEXT: - - - - - - - - 3.00 6.00 3.00 6.00 - - - - - - - - - - - vpcmpeqb %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 6.00 3.00 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqb (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpcmpeqw %zmm0, %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqw (%rax), %zmm1, %k2
+# CHECK-NEXT: - - - - - - - - 3.00 6.00 3.00 6.00 - - - - - - - - - - - vpcmpeqw %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 6.00 3.00 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqw (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpgtb %zmm0, %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtb (%rax), %zmm1, %k2
+# CHECK-NEXT: - - - - - - - - 3.00 6.00 3.00 6.00 - - - - - - - - - - - vpcmpgtb %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 6.00 3.00 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtb (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpgtw %zmm0, %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtw (%rax), %zmm1, %k2
+# CHECK-NEXT: - - - - - - - - 3.00 6.00 3.00 6.00 - - - - - - - - - - - vpcmpgtw %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 6.00 3.00 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtw (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpcmpequb %zmm0, %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequb (%rax), %zmm1, %k2
+# CHECK-NEXT: - - - - - - - - 3.00 6.00 3.00 6.00 - - - - - - - - - - - vpcmpequb %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 6.00 3.00 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequb (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpcmpequw %zmm0, %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequw (%rax), %zmm1, %k2
+# CHECK-NEXT: - - - - - - - - 3.00 6.00 3.00 6.00 - - - - - - - - - - - vpcmpequw %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 6.00 3.00 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequw (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpcmpeqw %zmm0, %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqw (%rax), %zmm1, %k2
+# CHECK-NEXT: - - - - - - - - 3.00 6.00 3.00 6.00 - - - - - - - - - - - vpcmpeqw %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 6.00 3.00 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqw (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpextrb $0, %xmm16, %eax
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vpextrb $0, %xmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpextrw $0, %xmm16, %eax
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vpextrw $0, %xmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpinsrb $0, %eax, %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpinsrb $0, (%rax), %xmm16, %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpinsrw $0, %eax, %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpinsrw $0, (%rax), %xmm16, %xmm19
+# CHECK-NEXT: - - - - - - - - 8.00 8.00 8.00 8.00 - - - - - - - - - - - vpermw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 8.00 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 8.00 8.00 8.00 8.00 - - - - - - - - - - - vpermw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 8.00 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 8.00 8.00 8.00 8.00 - - - - - - - - - - - vpermw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 8.00 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 16.00 16.00 16.00 16.00 - - - - - - - - - - - vpermi2w %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 16.00 16.00 16.00 16.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermi2w (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 16.00 16.00 16.00 16.00 - - - - - - - - - - - vpermi2w %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 16.00 16.00 16.00 16.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermi2w (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 16.00 16.00 16.00 16.00 - - - - - - - - - - - vpermi2w %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 16.00 16.00 16.00 16.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermi2w (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 16.00 16.00 16.00 16.00 - - - - - - - - - - - vpermt2w %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 16.00 16.00 16.00 16.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermt2w (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 16.00 16.00 16.00 16.00 - - - - - - - - - - - vpermt2w %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 16.00 16.00 16.00 16.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermt2w (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 16.00 16.00 16.00 16.00 - - - - - - - - - - - vpermt2w %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 16.00 16.00 16.00 16.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermt2w (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmaddubsw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaddubsw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmaddubsw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaddubsw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmaddubsw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaddubsw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmaddwd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaddwd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmaddwd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaddwd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmaddwd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaddwd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpmaxsb %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxsb (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpmaxsb %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxsb (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpmaxsb %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxsb (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpmaxsw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxsw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpmaxsw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxsw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpmaxsw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxsw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpmaxub %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxub (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpmaxub %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxub (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpmaxub %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxub (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpmaxuw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxuw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpmaxuw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxuw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpmaxuw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxuw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpminsb %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminsb (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpminsb %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminsb (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpminsb %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminsb (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpminsw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminsw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpminsw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminsw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpminsw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminsw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpminub %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminub (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpminub %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminub (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpminub %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminub (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpminuw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminuw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpminuw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminuw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpminuw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminuw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - vpmovb2m %zmm0, %k0
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - vpmovw2m %zmm0, %k0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpmovm2b %k0, %zmm0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpmovm2w %k0, %zmm0
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxbw %ymm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbw (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxbw %ymm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbw (%rax), %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxbw %ymm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbw (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovswb %zmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovswb %zmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovswb %zmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovswb %zmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovswb %zmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovuswb %zmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovuswb %zmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovuswb %zmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovuswb %zmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovuswb %zmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovwb %zmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovwb %zmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovwb %zmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovwb %zmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovwb %zmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxbw %ymm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbw (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxbw %ymm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbw (%rax), %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxbw %ymm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbw (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmulhrsw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhrsw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmulhrsw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhrsw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmulhrsw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhrsw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmulhuw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhuw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmulhuw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhuw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmulhuw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhuw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmulhw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmulhw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmulhw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmullw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmullw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmullw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmullw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmullw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmullw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpsadbw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsadbw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpshufb %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufb (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpshufb %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufb (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpshufb %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufb (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpshufhw $0, %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufhw $0, (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpshufhw $0, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufhw $0, (%rax), %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpshufhw $0, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufhw $0, (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpshuflw $0, %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshuflw $0, (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpshuflw $0, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshuflw $0, (%rax), %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpshuflw $0, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshuflw $0, (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpslldq $1, %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpslldq $1, (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpsllvw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllvw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsllvw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllvw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsllvw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllvw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsllw $0, %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllw $0, (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsllw $0, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllw $0, (%rax), %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsllw $0, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllw $0, (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsllw %xmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsllw %xmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsllw %xmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpsravw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsravw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsravw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsravw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsravw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsravw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsraw $0, %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsraw $0, (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsraw $0, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsraw $0, (%rax), %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsraw $0, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsraw $0, (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsraw %xmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsraw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsraw %xmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsraw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsraw %xmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsraw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpsrldq $1, %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrldq $1, (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpsrlvw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlvw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsrlvw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlvw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsrlvw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlvw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsrlw $0, %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlw $0, (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsrlw $0, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlw $0, (%rax), %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsrlw $0, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlw $0, (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsrlw %xmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsrlw %xmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsrlw %xmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubb %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubb (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubb %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubb (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubb %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubb (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubsb %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubsb (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubsb %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubsb (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubsb %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubsb (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubsw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubsw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubsw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubsw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubsw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubsw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubusb %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubusb (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubusb %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubusb (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubusb %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubusb (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubusw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubusw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubusw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubusw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubusw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubusw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vptestmb %zmm0, %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmb (%rax), %zmm1, %k2
+# CHECK-NEXT: - - - - - - - - 2.00 4.00 2.00 4.00 - - - - - - - - - - - vptestmb %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 6.00 3.00 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmb (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vptestmw %zmm0, %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmw (%rax), %zmm1, %k2
+# CHECK-NEXT: - - - - - - - - 2.00 4.00 2.00 4.00 - - - - - - - - - - - vptestmw %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 6.00 3.00 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmw (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vptestnmb %zmm0, %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmb (%rax), %zmm1, %k2
+# CHECK-NEXT: - - - - - - - - 2.00 4.00 2.00 4.00 - - - - - - - - - - - vptestnmb %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 6.00 3.00 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmb (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vptestnmw %zmm0, %zmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmw (%rax), %zmm1, %k2
+# CHECK-NEXT: - - - - - - - - 2.00 4.00 2.00 4.00 - - - - - - - - - - - vptestnmw %zmm0, %zmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 6.00 3.00 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmw (%rax), %zmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpunpckhbw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhbw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpunpckhbw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhbw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpunpckhbw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhbw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpunpckhwd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhwd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpunpckhwd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhwd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpunpckhwd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhwd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpunpcklbw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpcklbw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpunpcklbw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpcklbw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpunpcklbw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpcklbw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpunpcklwd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpcklwd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpunpcklwd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpcklwd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpunpcklwd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpcklwd (%rax), %zmm17, %zmm19 {%k1} {z}
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bwvl.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bwvl.s
new file mode 100644
index 0000000000000..befca44e4e112
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bwvl.s
@@ -0,0 +1,2976 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+vdbpsadbw $0, %xmm16, %xmm17, %xmm19
+vdbpsadbw $0, (%rax), %xmm17, %xmm19
+vdbpsadbw $0, %xmm16, %xmm17, %xmm19 {k1}
+vdbpsadbw $0, (%rax), %xmm17, %xmm19 {k1}
+vdbpsadbw $0, %xmm16, %xmm17, %xmm19 {z}{k1}
+vdbpsadbw $0, (%rax), %xmm17, %xmm19 {z}{k1}
+
+vdbpsadbw $0, %ymm16, %ymm17, %ymm19
+vdbpsadbw $0, (%rax), %ymm17, %ymm19
+vdbpsadbw $0, %ymm16, %ymm17, %ymm19 {k1}
+vdbpsadbw $0, (%rax), %ymm17, %ymm19 {k1}
+vdbpsadbw $0, %ymm16, %ymm17, %ymm19 {z}{k1}
+vdbpsadbw $0, (%rax), %ymm17, %ymm19 {z}{k1}
+
+vmovdqu8 %xmm16, %xmm19
+vmovdqu8 (%rax), %xmm19
+vmovdqu8 %xmm16, (%rax)
+vmovdqu8 %xmm16, %xmm19 {k1}
+vmovdqu8 (%rax), %xmm19 {k1}
+vmovdqu8 %xmm16, (%rax) {k1}
+vmovdqu8 %xmm16, %xmm19 {z}{k1}
+vmovdqu8 (%rax), %xmm19 {z}{k1}
+
+vmovdqu8 %ymm16, %ymm19
+vmovdqu8 (%rax), %ymm19
+vmovdqu8 %ymm16, (%rax)
+vmovdqu8 %ymm16, %ymm19 {k1}
+vmovdqu8 (%rax), %ymm19 {k1}
+vmovdqu8 %ymm16, (%rax) {k1}
+vmovdqu8 %ymm16, %ymm19 {z}{k1}
+vmovdqu8 (%rax), %ymm19 {z}{k1}
+
+vmovdqu16 %xmm16, %xmm19
+vmovdqu16 (%rax), %xmm19
+vmovdqu16 %xmm16, (%rax)
+vmovdqu16 %xmm16, %xmm19 {k1}
+vmovdqu16 (%rax), %xmm19 {k1}
+vmovdqu16 %xmm16, (%rax) {k1}
+vmovdqu16 %xmm16, %xmm19 {z}{k1}
+vmovdqu16 (%rax), %xmm19 {z}{k1}
+
+vmovdqu16 %ymm16, %ymm19
+vmovdqu16 (%rax), %ymm19
+vmovdqu16 %ymm16, (%rax)
+vmovdqu16 %ymm16, %ymm19 {k1}
+vmovdqu16 (%rax), %ymm19 {k1}
+vmovdqu16 %ymm16, (%rax) {k1}
+vmovdqu16 %ymm16, %ymm19 {z}{k1}
+vmovdqu16 (%rax), %ymm19 {z}{k1}
+
+vpabsb %xmm16, %xmm19
+vpabsb (%rax), %xmm19
+vpabsb %xmm16, %xmm19 {k1}
+vpabsb (%rax), %xmm19 {k1}
+vpabsb %xmm16, %xmm19 {z}{k1}
+vpabsb (%rax), %xmm19 {z}{k1}
+
+vpabsb %ymm16, %ymm19
+vpabsb (%rax), %ymm19
+vpabsb %ymm16, %ymm19 {k1}
+vpabsb (%rax), %ymm19 {k1}
+vpabsb %ymm16, %ymm19 {z}{k1}
+vpabsb (%rax), %ymm19 {z}{k1}
+
+vpabsw %xmm16, %xmm19
+vpabsw (%rax), %xmm19
+vpabsw %xmm16, %xmm19 {k1}
+vpabsw (%rax), %xmm19 {k1}
+vpabsw %xmm16, %xmm19 {z}{k1}
+vpabsw (%rax), %xmm19 {z}{k1}
+
+vpabsw %ymm16, %ymm19
+vpabsw (%rax), %ymm19
+vpabsw %ymm16, %ymm19 {k1}
+vpabsw (%rax), %ymm19 {k1}
+vpabsw %ymm16, %ymm19 {z}{k1}
+vpabsw (%rax), %ymm19 {z}{k1}
+
+vpackssdw %xmm16, %xmm17, %xmm19
+vpackssdw (%rax), %xmm17, %xmm19
+vpackssdw %xmm16, %xmm17, %xmm19 {k1}
+vpackssdw (%rax), %xmm17, %xmm19 {k1}
+vpackssdw %xmm16, %xmm17, %xmm19 {z}{k1}
+vpackssdw (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpackssdw %ymm16, %ymm17, %ymm19
+vpackssdw (%rax), %ymm17, %ymm19
+vpackssdw %ymm16, %ymm17, %ymm19 {k1}
+vpackssdw (%rax), %ymm17, %ymm19 {k1}
+vpackssdw %ymm16, %ymm17, %ymm19 {z}{k1}
+vpackssdw (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpacksswb %xmm16, %xmm17, %xmm19
+vpacksswb (%rax), %xmm17, %xmm19
+vpacksswb %xmm16, %xmm17, %xmm19 {k1}
+vpacksswb (%rax), %xmm17, %xmm19 {k1}
+vpacksswb %xmm16, %xmm17, %xmm19 {z}{k1}
+vpacksswb (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpacksswb %ymm16, %ymm17, %ymm19
+vpacksswb (%rax), %ymm17, %ymm19
+vpacksswb %ymm16, %ymm17, %ymm19 {k1}
+vpacksswb (%rax), %ymm17, %ymm19 {k1}
+vpacksswb %ymm16, %ymm17, %ymm19 {z}{k1}
+vpacksswb (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpackusdw %xmm16, %xmm17, %xmm19
+vpackusdw (%rax), %xmm17, %xmm19
+vpackusdw %xmm16, %xmm17, %xmm19 {k1}
+vpackusdw (%rax), %xmm17, %xmm19 {k1}
+vpackusdw %xmm16, %xmm17, %xmm19 {z}{k1}
+vpackusdw (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpackusdw %ymm16, %ymm17, %ymm19
+vpackusdw (%rax), %ymm17, %ymm19
+vpackusdw %ymm16, %ymm17, %ymm19 {k1}
+vpackusdw (%rax), %ymm17, %ymm19 {k1}
+vpackusdw %ymm16, %ymm17, %ymm19 {z}{k1}
+vpackusdw (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpackuswb %xmm16, %xmm17, %xmm19
+vpackuswb (%rax), %xmm17, %xmm19
+vpackuswb %xmm16, %xmm17, %xmm19 {k1}
+vpackuswb (%rax), %xmm17, %xmm19 {k1}
+vpackuswb %xmm16, %xmm17, %xmm19 {z}{k1}
+vpackuswb (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpackuswb %ymm16, %ymm17, %ymm19
+vpackuswb (%rax), %ymm17, %ymm19
+vpackuswb %ymm16, %ymm17, %ymm19 {k1}
+vpackuswb (%rax), %ymm17, %ymm19 {k1}
+vpackuswb %ymm16, %ymm17, %ymm19 {z}{k1}
+vpackuswb (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpaddb %xmm16, %xmm17, %xmm19
+vpaddb (%rax), %xmm17, %xmm19
+vpaddb %xmm16, %xmm17, %xmm19 {k1}
+vpaddb (%rax), %xmm17, %xmm19 {k1}
+vpaddb %xmm16, %xmm17, %xmm19 {z}{k1}
+vpaddb (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpaddb %ymm16, %ymm17, %ymm19
+vpaddb (%rax), %ymm17, %ymm19
+vpaddb %ymm16, %ymm17, %ymm19 {k1}
+vpaddb (%rax), %ymm17, %ymm19 {k1}
+vpaddb %ymm16, %ymm17, %ymm19 {z}{k1}
+vpaddb (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpaddsb %xmm16, %xmm17, %xmm19
+vpaddsb (%rax), %xmm17, %xmm19
+vpaddsb %xmm16, %xmm17, %xmm19 {k1}
+vpaddsb (%rax), %xmm17, %xmm19 {k1}
+vpaddsb %xmm16, %xmm17, %xmm19 {z}{k1}
+vpaddsb (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpaddsb %ymm16, %ymm17, %ymm19
+vpaddsb (%rax), %ymm17, %ymm19
+vpaddsb %ymm16, %ymm17, %ymm19 {k1}
+vpaddsb (%rax), %ymm17, %ymm19 {k1}
+vpaddsb %ymm16, %ymm17, %ymm19 {z}{k1}
+vpaddsb (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpaddsw %xmm16, %xmm17, %xmm19
+vpaddsw (%rax), %xmm17, %xmm19
+vpaddsw %xmm16, %xmm17, %xmm19 {k1}
+vpaddsw (%rax), %xmm17, %xmm19 {k1}
+vpaddsw %xmm16, %xmm17, %xmm19 {z}{k1}
+vpaddsw (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpaddsw %ymm16, %ymm17, %ymm19
+vpaddsw (%rax), %ymm17, %ymm19
+vpaddsw %ymm16, %ymm17, %ymm19 {k1}
+vpaddsw (%rax), %ymm17, %ymm19 {k1}
+vpaddsw %ymm16, %ymm17, %ymm19 {z}{k1}
+vpaddsw (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpaddusb %xmm16, %xmm17, %xmm19
+vpaddusb (%rax), %xmm17, %xmm19
+vpaddusb %xmm16, %xmm17, %xmm19 {k1}
+vpaddusb (%rax), %xmm17, %xmm19 {k1}
+vpaddusb %xmm16, %xmm17, %xmm19 {z}{k1}
+vpaddusb (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpaddusb %ymm16, %ymm17, %ymm19
+vpaddusb (%rax), %ymm17, %ymm19
+vpaddusb %ymm16, %ymm17, %ymm19 {k1}
+vpaddusb (%rax), %ymm17, %ymm19 {k1}
+vpaddusb %ymm16, %ymm17, %ymm19 {z}{k1}
+vpaddusb (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpaddusw %xmm16, %xmm17, %xmm19
+vpaddusw (%rax), %xmm17, %xmm19
+vpaddusw %xmm16, %xmm17, %xmm19 {k1}
+vpaddusw (%rax), %xmm17, %xmm19 {k1}
+vpaddusw %xmm16, %xmm17, %xmm19 {z}{k1}
+vpaddusw (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpaddusw %ymm16, %ymm17, %ymm19
+vpaddusw (%rax), %ymm17, %ymm19
+vpaddusw %ymm16, %ymm17, %ymm19 {k1}
+vpaddusw (%rax), %ymm17, %ymm19 {k1}
+vpaddusw %ymm16, %ymm17, %ymm19 {z}{k1}
+vpaddusw (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpaddw %xmm16, %xmm17, %xmm19
+vpaddw (%rax), %xmm17, %xmm19
+vpaddw %xmm16, %xmm17, %xmm19 {k1}
+vpaddw (%rax), %xmm17, %xmm19 {k1}
+vpaddw %xmm16, %xmm17, %xmm19 {z}{k1}
+vpaddw (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpaddw %ymm16, %ymm17, %ymm19
+vpaddw (%rax), %ymm17, %ymm19
+vpaddw %ymm16, %ymm17, %ymm19 {k1}
+vpaddw (%rax), %ymm17, %ymm19 {k1}
+vpaddw %ymm16, %ymm17, %ymm19 {z}{k1}
+vpaddw (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpalignr $1, %xmm16, %xmm17, %xmm19
+vpalignr $1, (%rax), %xmm17, %xmm19
+vpalignr $1, %xmm16, %xmm17, %xmm19 {k1}
+vpalignr $1, (%rax), %xmm17, %xmm19 {k1}
+vpalignr $1, %xmm16, %xmm17, %xmm19 {z}{k1}
+vpalignr $1, (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpalignr $1, %ymm16, %ymm17, %ymm19
+vpalignr $1, (%rax), %ymm17, %ymm19
+vpalignr $1, %ymm16, %ymm17, %ymm19 {k1}
+vpalignr $1, (%rax), %ymm17, %ymm19 {k1}
+vpalignr $1, %ymm16, %ymm17, %ymm19 {z}{k1}
+vpalignr $1, (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpavgb %xmm16, %xmm17, %xmm19
+vpavgb (%rax), %xmm17, %xmm19
+vpavgb %xmm16, %xmm17, %xmm19 {k1}
+vpavgb (%rax), %xmm17, %xmm19 {k1}
+vpavgb %xmm16, %xmm17, %xmm19 {z}{k1}
+vpavgb (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpavgb %ymm16, %ymm17, %ymm19
+vpavgb (%rax), %ymm17, %ymm19
+vpavgb %ymm16, %ymm17, %ymm19 {k1}
+vpavgb (%rax), %ymm17, %ymm19 {k1}
+vpavgb %ymm16, %ymm17, %ymm19 {z}{k1}
+vpavgb (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpavgw %xmm16, %xmm17, %xmm19
+vpavgw (%rax), %xmm17, %xmm19
+vpavgw %xmm16, %xmm17, %xmm19 {k1}
+vpavgw (%rax), %xmm17, %xmm19 {k1}
+vpavgw %xmm16, %xmm17, %xmm19 {z}{k1}
+vpavgw (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpavgw %ymm16, %ymm17, %ymm19
+vpavgw (%rax), %ymm17, %ymm19
+vpavgw %ymm16, %ymm17, %ymm19 {k1}
+vpavgw (%rax), %ymm17, %ymm19 {k1}
+vpavgw %ymm16, %ymm17, %ymm19 {z}{k1}
+vpavgw (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpblendmb %xmm16, %xmm17, %xmm19
+vpblendmb (%rax), %xmm17, %xmm19
+vpblendmb %xmm16, %xmm17, %xmm19 {k1}
+vpblendmb (%rax), %xmm17, %xmm19 {k1}
+vpblendmb %xmm16, %xmm17, %xmm19 {z}{k1}
+vpblendmb (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpblendmb %ymm16, %ymm17, %ymm19
+vpblendmb (%rax), %ymm17, %ymm19
+vpblendmb %ymm16, %ymm17, %ymm19 {k1}
+vpblendmb (%rax), %ymm17, %ymm19 {k1}
+vpblendmb %ymm16, %ymm17, %ymm19 {z}{k1}
+vpblendmb (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpblendmw %xmm16, %xmm17, %xmm19
+vpblendmw (%rax), %xmm17, %xmm19
+vpblendmw %xmm16, %xmm17, %xmm19 {k1}
+vpblendmw (%rax), %xmm17, %xmm19 {k1}
+vpblendmw %xmm16, %xmm17, %xmm19 {z}{k1}
+vpblendmw (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpblendmw %ymm16, %ymm17, %ymm19
+vpblendmw (%rax), %ymm17, %ymm19
+vpblendmw %ymm16, %ymm17, %ymm19 {k1}
+vpblendmw (%rax), %ymm17, %ymm19 {k1}
+vpblendmw %ymm16, %ymm17, %ymm19 {z}{k1}
+vpblendmw (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpbroadcastb %xmm16, %xmm19
+vpbroadcastb (%rax), %xmm19
+vpbroadcastb %eax, %xmm19
+vpbroadcastb %xmm16, %xmm19 {k1}
+vpbroadcastb (%rax), %xmm19 {k1}
+vpbroadcastb %eax, %xmm19 {k1}
+vpbroadcastb %xmm16, %xmm19 {z}{k1}
+vpbroadcastb (%rax), %xmm19 {z}{k1}
+vpbroadcastb %eax, %xmm19 {z}{k1}
+
+vpbroadcastb %xmm16, %ymm19
+vpbroadcastb (%rax), %ymm19
+vpbroadcastb %eax, %ymm19
+vpbroadcastb %xmm16, %ymm19 {k1}
+vpbroadcastb (%rax), %ymm19 {k1}
+vpbroadcastb %eax, %ymm19 {k1}
+vpbroadcastb %xmm16, %ymm19 {z}{k1}
+vpbroadcastb (%rax), %ymm19 {z}{k1}
+vpbroadcastb %eax, %ymm19 {z}{k1}
+
+vpbroadcastw %xmm16, %xmm19
+vpbroadcastw (%rax), %xmm19
+vpbroadcastw %eax, %xmm19
+vpbroadcastw %xmm16, %xmm19 {k1}
+vpbroadcastw (%rax), %xmm19 {k1}
+vpbroadcastw %eax, %xmm19 {k1}
+vpbroadcastw %xmm16, %xmm19 {z}{k1}
+vpbroadcastw (%rax), %xmm19 {z}{k1}
+vpbroadcastw %eax, %xmm19 {z}{k1}
+
+vpbroadcastw %xmm16, %ymm19
+vpbroadcastw (%rax), %ymm19
+vpbroadcastw %eax, %ymm19
+vpbroadcastw %xmm16, %ymm19 {k1}
+vpbroadcastw (%rax), %ymm19 {k1}
+vpbroadcastw %eax, %ymm19 {k1}
+vpbroadcastw %xmm16, %ymm19 {z}{k1}
+vpbroadcastw (%rax), %ymm19 {z}{k1}
+vpbroadcastw %eax, %ymm19 {z}{k1}
+
+vpcmpb $0, %xmm0, %xmm1, %k2
+vpcmpb $0, (%rax), %xmm1, %k2
+vpcmpb $0, %xmm0, %xmm1, %k2 {k3}
+vpcmpb $0, (%rax), %xmm1, %k2 {k3}
+
+vpcmpb $0, %ymm0, %ymm1, %k2
+vpcmpb $0, (%rax), %ymm1, %k2
+vpcmpb $0, %ymm0, %ymm1, %k2 {k3}
+vpcmpb $0, (%rax), %ymm1, %k2 {k3}
+
+vpcmpeqb %xmm0, %xmm1, %k2
+vpcmpeqb (%rax), %xmm1, %k2
+vpcmpeqb %xmm0, %xmm1, %k2 {k3}
+vpcmpeqb (%rax), %xmm1, %k2 {k3}
+
+vpcmpeqb %ymm0, %ymm1, %k2
+vpcmpeqb (%rax), %ymm1, %k2
+vpcmpeqb %ymm0, %ymm1, %k2 {k3}
+vpcmpeqb (%rax), %ymm1, %k2 {k3}
+
+vpcmpeqw %xmm0, %xmm1, %k2
+vpcmpeqw (%rax), %xmm1, %k2
+vpcmpeqw %xmm0, %xmm1, %k2 {k3}
+vpcmpeqw (%rax), %xmm1, %k2 {k3}
+
+vpcmpeqw %ymm0, %ymm1, %k2
+vpcmpeqw (%rax), %ymm1, %k2
+vpcmpeqw %ymm0, %ymm1, %k2 {k3}
+vpcmpeqw (%rax), %ymm1, %k2 {k3}
+
+vpcmpgtb %xmm0, %xmm1, %k2
+vpcmpgtb (%rax), %xmm1, %k2
+vpcmpgtb %xmm0, %xmm1, %k2 {k3}
+vpcmpgtb (%rax), %xmm1, %k2 {k3}
+
+vpcmpgtb %ymm0, %ymm1, %k2
+vpcmpgtb (%rax), %ymm1, %k2
+vpcmpgtb %ymm0, %ymm1, %k2 {k3}
+vpcmpgtb (%rax), %ymm1, %k2 {k3}
+
+vpcmpgtw %xmm0, %xmm1, %k2
+vpcmpgtw (%rax), %xmm1, %k2
+vpcmpgtw %xmm0, %xmm1, %k2 {k3}
+vpcmpgtw (%rax), %xmm1, %k2 {k3}
+
+vpcmpgtw %ymm0, %ymm1, %k2
+vpcmpgtw (%rax), %ymm1, %k2
+vpcmpgtw %ymm0, %ymm1, %k2 {k3}
+vpcmpgtw (%rax), %ymm1, %k2 {k3}
+
+vpcmpub $0, %xmm0, %xmm1, %k2
+vpcmpub $0, (%rax), %xmm1, %k2
+vpcmpub $0, %xmm0, %xmm1, %k2 {k3}
+vpcmpub $0, (%rax), %xmm1, %k2 {k3}
+
+vpcmpub $0, %ymm0, %ymm1, %k2
+vpcmpub $0, (%rax), %ymm1, %k2
+vpcmpub $0, %ymm0, %ymm1, %k2 {k3}
+vpcmpub $0, (%rax), %ymm1, %k2 {k3}
+
+vpcmpuw $0, %xmm0, %xmm1, %k2
+vpcmpuw $0, (%rax), %xmm1, %k2
+vpcmpuw $0, %xmm0, %xmm1, %k2 {k3}
+vpcmpuw $0, (%rax), %xmm1, %k2 {k3}
+
+vpcmpuw $0, %ymm0, %ymm1, %k2
+vpcmpuw $0, (%rax), %ymm1, %k2
+vpcmpuw $0, %ymm0, %ymm1, %k2 {k3}
+vpcmpuw $0, (%rax), %ymm1, %k2 {k3}
+
+vpcmpw $0, %xmm0, %xmm1, %k2
+vpcmpw $0, (%rax), %xmm1, %k2
+vpcmpw $0, %xmm0, %xmm1, %k2 {k3}
+vpcmpw $0, (%rax), %xmm1, %k2 {k3}
+
+vpcmpw $0, %ymm0, %ymm1, %k2
+vpcmpw $0, (%rax), %ymm1, %k2
+vpcmpw $0, %ymm0, %ymm1, %k2 {k3}
+vpcmpw $0, (%rax), %ymm1, %k2 {k3}
+
+vpermw %xmm16, %xmm17, %xmm19
+vpermw (%rax), %xmm17, %xmm19
+vpermw %xmm16, %xmm17, %xmm19 {k1}
+vpermw (%rax), %xmm17, %xmm19 {k1}
+vpermw %xmm16, %xmm17, %xmm19 {z}{k1}
+vpermw (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpermw %ymm16, %ymm17, %ymm19
+vpermw (%rax), %ymm17, %ymm19
+vpermw %ymm16, %ymm17, %ymm19 {k1}
+vpermw (%rax), %ymm17, %ymm19 {k1}
+vpermw %ymm16, %ymm17, %ymm19 {z}{k1}
+vpermw (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpermi2w %xmm16, %xmm17, %xmm19
+vpermi2w (%rax), %xmm17, %xmm19
+vpermi2w %xmm16, %xmm17, %xmm19 {k1}
+vpermi2w (%rax), %xmm17, %xmm19 {k1}
+vpermi2w %xmm16, %xmm17, %xmm19 {z}{k1}
+vpermi2w (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpermi2w %ymm16, %ymm17, %ymm19
+vpermi2w (%rax), %ymm17, %ymm19
+vpermi2w %ymm16, %ymm17, %ymm19 {k1}
+vpermi2w (%rax), %ymm17, %ymm19 {k1}
+vpermi2w %ymm16, %ymm17, %ymm19 {z}{k1}
+vpermi2w (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpermt2w %xmm16, %xmm17, %xmm19
+vpermt2w (%rax), %xmm17, %xmm19
+vpermt2w %xmm16, %xmm17, %xmm19 {k1}
+vpermt2w (%rax), %xmm17, %xmm19 {k1}
+vpermt2w %xmm16, %xmm17, %xmm19 {z}{k1}
+vpermt2w (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpermt2w %ymm16, %ymm17, %ymm19
+vpermt2w (%rax), %ymm17, %ymm19
+vpermt2w %ymm16, %ymm17, %ymm19 {k1}
+vpermt2w (%rax), %ymm17, %ymm19 {k1}
+vpermt2w %ymm16, %ymm17, %ymm19 {z}{k1}
+vpermt2w (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpmaddubsw %xmm16, %xmm17, %xmm19
+vpmaddubsw (%rax), %xmm17, %xmm19
+vpmaddubsw %xmm16, %xmm17, %xmm19 {k1}
+vpmaddubsw (%rax), %xmm17, %xmm19 {k1}
+vpmaddubsw %xmm16, %xmm17, %xmm19 {z}{k1}
+vpmaddubsw (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpmaddubsw %ymm16, %ymm17, %ymm19
+vpmaddubsw (%rax), %ymm17, %ymm19
+vpmaddubsw %ymm16, %ymm17, %ymm19 {k1}
+vpmaddubsw (%rax), %ymm17, %ymm19 {k1}
+vpmaddubsw %ymm16, %ymm17, %ymm19 {z}{k1}
+vpmaddubsw (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpmaddwd %xmm16, %xmm17, %xmm19
+vpmaddwd (%rax), %xmm17, %xmm19
+vpmaddwd %xmm16, %xmm17, %xmm19 {k1}
+vpmaddwd (%rax), %xmm17, %xmm19 {k1}
+vpmaddwd %xmm16, %xmm17, %xmm19 {z}{k1}
+vpmaddwd (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpmaddwd %ymm16, %ymm17, %ymm19
+vpmaddwd (%rax), %ymm17, %ymm19
+vpmaddwd %ymm16, %ymm17, %ymm19 {k1}
+vpmaddwd (%rax), %ymm17, %ymm19 {k1}
+vpmaddwd %ymm16, %ymm17, %ymm19 {z}{k1}
+vpmaddwd (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpmaxsb %xmm16, %xmm17, %xmm19
+vpmaxsb (%rax), %xmm17, %xmm19
+vpmaxsb %xmm16, %xmm17, %xmm19 {k1}
+vpmaxsb (%rax), %xmm17, %xmm19 {k1}
+vpmaxsb %xmm16, %xmm17, %xmm19 {z}{k1}
+vpmaxsb (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpmaxsb %ymm16, %ymm17, %ymm19
+vpmaxsb (%rax), %ymm17, %ymm19
+vpmaxsb %ymm16, %ymm17, %ymm19 {k1}
+vpmaxsb (%rax), %ymm17, %ymm19 {k1}
+vpmaxsb %ymm16, %ymm17, %ymm19 {z}{k1}
+vpmaxsb (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpmaxsw %xmm16, %xmm17, %xmm19
+vpmaxsw (%rax), %xmm17, %xmm19
+vpmaxsw %xmm16, %xmm17, %xmm19 {k1}
+vpmaxsw (%rax), %xmm17, %xmm19 {k1}
+vpmaxsw %xmm16, %xmm17, %xmm19 {z}{k1}
+vpmaxsw (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpmaxsw %ymm16, %ymm17, %ymm19
+vpmaxsw (%rax), %ymm17, %ymm19
+vpmaxsw %ymm16, %ymm17, %ymm19 {k1}
+vpmaxsw (%rax), %ymm17, %ymm19 {k1}
+vpmaxsw %ymm16, %ymm17, %ymm19 {z}{k1}
+vpmaxsw (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpmaxub %xmm16, %xmm17, %xmm19
+vpmaxub (%rax), %xmm17, %xmm19
+vpmaxub %xmm16, %xmm17, %xmm19 {k1}
+vpmaxub (%rax), %xmm17, %xmm19 {k1}
+vpmaxub %xmm16, %xmm17, %xmm19 {z}{k1}
+vpmaxub (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpmaxub %ymm16, %ymm17, %ymm19
+vpmaxub (%rax), %ymm17, %ymm19
+vpmaxub %ymm16, %ymm17, %ymm19 {k1}
+vpmaxub (%rax), %ymm17, %ymm19 {k1}
+vpmaxub %ymm16, %ymm17, %ymm19 {z}{k1}
+vpmaxub (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpmaxuw %xmm16, %xmm17, %xmm19
+vpmaxuw (%rax), %xmm17, %xmm19
+vpmaxuw %xmm16, %xmm17, %xmm19 {k1}
+vpmaxuw (%rax), %xmm17, %xmm19 {k1}
+vpmaxuw %xmm16, %xmm17, %xmm19 {z}{k1}
+vpmaxuw (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpmaxuw %ymm16, %ymm17, %ymm19
+vpmaxuw (%rax), %ymm17, %ymm19
+vpmaxuw %ymm16, %ymm17, %ymm19 {k1}
+vpmaxuw (%rax), %ymm17, %ymm19 {k1}
+vpmaxuw %ymm16, %ymm17, %ymm19 {z}{k1}
+vpmaxuw (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpminsb %xmm16, %xmm17, %xmm19
+vpminsb (%rax), %xmm17, %xmm19
+vpminsb %xmm16, %xmm17, %xmm19 {k1}
+vpminsb (%rax), %xmm17, %xmm19 {k1}
+vpminsb %xmm16, %xmm17, %xmm19 {z}{k1}
+vpminsb (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpminsb %ymm16, %ymm17, %ymm19
+vpminsb (%rax), %ymm17, %ymm19
+vpminsb %ymm16, %ymm17, %ymm19 {k1}
+vpminsb (%rax), %ymm17, %ymm19 {k1}
+vpminsb %ymm16, %ymm17, %ymm19 {z}{k1}
+vpminsb (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpminsw %xmm16, %xmm17, %xmm19
+vpminsw (%rax), %xmm17, %xmm19
+vpminsw %xmm16, %xmm17, %xmm19 {k1}
+vpminsw (%rax), %xmm17, %xmm19 {k1}
+vpminsw %xmm16, %xmm17, %xmm19 {z}{k1}
+vpminsw (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpminsw %ymm16, %ymm17, %ymm19
+vpminsw (%rax), %ymm17, %ymm19
+vpminsw %ymm16, %ymm17, %ymm19 {k1}
+vpminsw (%rax), %ymm17, %ymm19 {k1}
+vpminsw %ymm16, %ymm17, %ymm19 {z}{k1}
+vpminsw (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpminub %xmm16, %xmm17, %xmm19
+vpminub (%rax), %xmm17, %xmm19
+vpminub %xmm16, %xmm17, %xmm19 {k1}
+vpminub (%rax), %xmm17, %xmm19 {k1}
+vpminub %xmm16, %xmm17, %xmm19 {z}{k1}
+vpminub (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpminub %ymm16, %ymm17, %ymm19
+vpminub (%rax), %ymm17, %ymm19
+vpminub %ymm16, %ymm17, %ymm19 {k1}
+vpminub (%rax), %ymm17, %ymm19 {k1}
+vpminub %ymm16, %ymm17, %ymm19 {z}{k1}
+vpminub (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpminuw %xmm16, %xmm17, %xmm19
+vpminuw (%rax), %xmm17, %xmm19
+vpminuw %xmm16, %xmm17, %xmm19 {k1}
+vpminuw (%rax), %xmm17, %xmm19 {k1}
+vpminuw %xmm16, %xmm17, %xmm19 {z}{k1}
+vpminuw (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpminuw %ymm16, %ymm17, %ymm19
+vpminuw (%rax), %ymm17, %ymm19
+vpminuw %ymm16, %ymm17, %ymm19 {k1}
+vpminuw (%rax), %ymm17, %ymm19 {k1}
+vpminuw %ymm16, %ymm17, %ymm19 {z}{k1}
+vpminuw (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpmovb2m %xmm0, %k0
+vpmovw2m %xmm0, %k0
+
+vpmovb2m %ymm0, %k0
+vpmovw2m %ymm0, %k0
+
+vpmovm2b %k0, %xmm0
+vpmovm2w %k0, %xmm0
+
+vpmovm2b %k0, %ymm0
+vpmovm2w %k0, %ymm0
+
+vpmovsxbw %xmm16, %xmm19
+vpmovsxbw (%rax), %xmm19
+vpmovsxbw %xmm16, %xmm19 {k1}
+vpmovsxbw (%rax), %xmm19 {k1}
+vpmovsxbw %xmm16, %xmm19 {z}{k1}
+vpmovsxbw (%rax), %xmm19 {z}{k1}
+
+vpmovsxbw %xmm16, %ymm19
+vpmovsxbw (%rax), %ymm19
+vpmovsxbw %xmm16, %ymm19 {k1}
+vpmovsxbw (%rax), %ymm19 {k1}
+vpmovsxbw %xmm16, %ymm19 {z}{k1}
+vpmovsxbw (%rax), %ymm19 {z}{k1}
+
+vpmovswb %xmm16, %xmm19
+vpmovswb %xmm16, (%rax)
+vpmovswb %xmm16, %xmm19 {k1}
+vpmovswb %xmm16, (%rax) {k1}
+vpmovswb %xmm16, %xmm19 {z}{k1}
+
+vpmovswb %ymm16, %xmm19
+vpmovswb %ymm16, (%rax)
+vpmovswb %ymm16, %xmm19 {k1}
+vpmovswb %ymm16, (%rax) {k1}
+vpmovswb %ymm16, %xmm19 {z}{k1}
+
+vpmovuswb %xmm16, %xmm19
+vpmovuswb %xmm16, (%rax)
+vpmovuswb %xmm16, %xmm19 {k1}
+vpmovuswb %xmm16, (%rax) {k1}
+vpmovuswb %xmm16, %xmm19 {z}{k1}
+
+vpmovuswb %ymm16, %xmm19
+vpmovuswb %ymm16, (%rax)
+vpmovuswb %ymm16, %xmm19 {k1}
+vpmovuswb %ymm16, (%rax) {k1}
+vpmovuswb %ymm16, %xmm19 {z}{k1}
+
+vpmovwb %xmm16, %xmm19
+vpmovwb %xmm16, (%rax)
+vpmovwb %xmm16, %xmm19 {k1}
+vpmovwb %xmm16, (%rax) {k1}
+vpmovwb %xmm16, %xmm19 {z}{k1}
+
+vpmovwb %ymm16, %xmm19
+vpmovwb %ymm16, (%rax)
+vpmovwb %ymm16, %xmm19 {k1}
+vpmovwb %ymm16, (%rax) {k1}
+vpmovwb %ymm16, %xmm19 {z}{k1}
+
+vpmovzxbw %xmm16, %xmm19
+vpmovzxbw (%rax), %xmm19
+vpmovzxbw %xmm16, %xmm19 {k1}
+vpmovzxbw (%rax), %xmm19 {k1}
+vpmovzxbw %xmm16, %xmm19 {z}{k1}
+vpmovzxbw (%rax), %xmm19 {z}{k1}
+
+vpmovzxbw %xmm16, %ymm19
+vpmovzxbw (%rax), %ymm19
+vpmovzxbw %xmm16, %ymm19 {k1}
+vpmovzxbw (%rax), %ymm19 {k1}
+vpmovzxbw %xmm16, %ymm19 {z}{k1}
+vpmovzxbw (%rax), %ymm19 {z}{k1}
+
+vpmulhrsw %xmm16, %xmm17, %xmm19
+vpmulhrsw (%rax), %xmm17, %xmm19
+vpmulhrsw %xmm16, %xmm17, %xmm19 {k1}
+vpmulhrsw (%rax), %xmm17, %xmm19 {k1}
+vpmulhrsw %xmm16, %xmm17, %xmm19 {z}{k1}
+vpmulhrsw (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpmulhrsw %ymm16, %ymm17, %ymm19
+vpmulhrsw (%rax), %ymm17, %ymm19
+vpmulhrsw %ymm16, %ymm17, %ymm19 {k1}
+vpmulhrsw (%rax), %ymm17, %ymm19 {k1}
+vpmulhrsw %ymm16, %ymm17, %ymm19 {z}{k1}
+vpmulhrsw (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpmulhuw %xmm16, %xmm17, %xmm19
+vpmulhuw (%rax), %xmm17, %xmm19
+vpmulhuw %xmm16, %xmm17, %xmm19 {k1}
+vpmulhuw (%rax), %xmm17, %xmm19 {k1}
+vpmulhuw %xmm16, %xmm17, %xmm19 {z}{k1}
+vpmulhuw (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpmulhuw %ymm16, %ymm17, %ymm19
+vpmulhuw (%rax), %ymm17, %ymm19
+vpmulhuw %ymm16, %ymm17, %ymm19 {k1}
+vpmulhuw (%rax), %ymm17, %ymm19 {k1}
+vpmulhuw %ymm16, %ymm17, %ymm19 {z}{k1}
+vpmulhuw (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpmulhw %xmm16, %xmm17, %xmm19
+vpmulhw (%rax), %xmm17, %xmm19
+vpmulhw %xmm16, %xmm17, %xmm19 {k1}
+vpmulhw (%rax), %xmm17, %xmm19 {k1}
+vpmulhw %xmm16, %xmm17, %xmm19 {z}{k1}
+vpmulhw (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpmulhw %ymm16, %ymm17, %ymm19
+vpmulhw (%rax), %ymm17, %ymm19
+vpmulhw %ymm16, %ymm17, %ymm19 {k1}
+vpmulhw (%rax), %ymm17, %ymm19 {k1}
+vpmulhw %ymm16, %ymm17, %ymm19 {z}{k1}
+vpmulhw (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpmullw %xmm16, %xmm17, %xmm19
+vpmullw (%rax), %xmm17, %xmm19
+vpmullw %xmm16, %xmm17, %xmm19 {k1}
+vpmullw (%rax), %xmm17, %xmm19 {k1}
+vpmullw %xmm16, %xmm17, %xmm19 {z}{k1}
+vpmullw (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpmullw %ymm16, %ymm17, %ymm19
+vpmullw (%rax), %ymm17, %ymm19
+vpmullw %ymm16, %ymm17, %ymm19 {k1}
+vpmullw (%rax), %ymm17, %ymm19 {k1}
+vpmullw %ymm16, %ymm17, %ymm19 {z}{k1}
+vpmullw (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpsadbw %xmm16, %xmm17, %xmm19
+vpsadbw (%rax), %xmm17, %xmm19
+
+vpsadbw %ymm16, %ymm17, %ymm19
+vpsadbw (%rax), %ymm17, %ymm19
+
+vpshufb %xmm16, %xmm17, %xmm19
+vpshufb (%rax), %xmm17, %xmm19
+vpshufb %xmm16, %xmm17, %xmm19 {k1}
+vpshufb (%rax), %xmm17, %xmm19 {k1}
+vpshufb %xmm16, %xmm17, %xmm19 {z}{k1}
+vpshufb (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpshufb %ymm16, %ymm17, %ymm19
+vpshufb (%rax), %ymm17, %ymm19
+vpshufb %ymm16, %ymm17, %ymm19 {k1}
+vpshufb (%rax), %ymm17, %ymm19 {k1}
+vpshufb %ymm16, %ymm17, %ymm19 {z}{k1}
+vpshufb (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpshufhw $0, %xmm16, %xmm19
+vpshufhw $0, (%rax), %xmm19
+vpshufhw $0, %xmm16, %xmm19 {k1}
+vpshufhw $0, (%rax), %xmm19 {k1}
+vpshufhw $0, %xmm16, %xmm19 {z}{k1}
+vpshufhw $0, (%rax), %xmm19 {z}{k1}
+
+vpshufhw $0, %ymm16, %ymm19
+vpshufhw $0, (%rax), %ymm19
+vpshufhw $0, %ymm16, %ymm19 {k1}
+vpshufhw $0, (%rax), %ymm19 {k1}
+vpshufhw $0, %ymm16, %ymm19 {z}{k1}
+vpshufhw $0, (%rax), %ymm19 {z}{k1}
+
+vpshuflw $0, %xmm16, %xmm19
+vpshuflw $0, (%rax), %xmm19
+vpshuflw $0, %xmm16, %xmm19 {k1}
+vpshuflw $0, (%rax), %xmm19 {k1}
+vpshuflw $0, %xmm16, %xmm19 {z}{k1}
+vpshuflw $0, (%rax), %xmm19 {z}{k1}
+
+vpshuflw $0, %ymm16, %ymm19
+vpshuflw $0, (%rax), %ymm19
+vpshuflw $0, %ymm16, %ymm19 {k1}
+vpshuflw $0, (%rax), %ymm19 {k1}
+vpshuflw $0, %ymm16, %ymm19 {z}{k1}
+vpshuflw $0, (%rax), %ymm19 {z}{k1}
+
+vpslldq $1, %xmm16, %xmm19
+vpslldq $1, (%rax), %xmm19
+
+vpslldq $1, %ymm16, %ymm19
+vpslldq $1, (%rax), %ymm19
+
+vpsllvw %xmm16, %xmm17, %xmm19
+vpsllvw (%rax), %xmm17, %xmm19
+vpsllvw %xmm16, %xmm17, %xmm19 {k1}
+vpsllvw (%rax), %xmm17, %xmm19 {k1}
+vpsllvw %xmm16, %xmm17, %xmm19 {z}{k1}
+vpsllvw (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpsllvw %ymm16, %ymm17, %ymm19
+vpsllvw (%rax), %ymm17, %ymm19
+vpsllvw %ymm16, %ymm17, %ymm19 {k1}
+vpsllvw (%rax), %ymm17, %ymm19 {k1}
+vpsllvw %ymm16, %ymm17, %ymm19 {z}{k1}
+vpsllvw (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpsllw $0, %xmm16, %xmm19
+vpsllw $0, (%rax), %xmm19
+vpsllw $0, %xmm16, %xmm19 {k1}
+vpsllw $0, (%rax), %xmm19 {k1}
+vpsllw $0, %xmm16, %xmm19 {z}{k1}
+vpsllw $0, (%rax), %xmm19 {z}{k1}
+
+vpsllw $0, %ymm16, %ymm19
+vpsllw $0, (%rax), %ymm19
+vpsllw $0, %ymm16, %ymm19 {k1}
+vpsllw $0, (%rax), %ymm19 {k1}
+vpsllw $0, %ymm16, %ymm19 {z}{k1}
+vpsllw $0, (%rax), %ymm19 {z}{k1}
+
+vpsllw %xmm16, %xmm17, %xmm19
+vpsllw (%rax), %xmm17, %xmm19
+vpsllw %xmm16, %xmm17, %xmm19 {k1}
+vpsllw (%rax), %xmm17, %xmm19 {k1}
+vpsllw %xmm16, %xmm17, %xmm19 {z}{k1}
+vpsllw (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpsllw %xmm16, %ymm17, %ymm19
+vpsllw (%rax), %ymm17, %ymm19
+vpsllw %xmm16, %ymm17, %ymm19 {k1}
+vpsllw (%rax), %ymm17, %ymm19 {k1}
+vpsllw %xmm16, %ymm17, %ymm19 {z}{k1}
+vpsllw (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpsravw %xmm16, %xmm17, %xmm19
+vpsravw (%rax), %xmm17, %xmm19
+vpsravw %xmm16, %xmm17, %xmm19 {k1}
+vpsravw (%rax), %xmm17, %xmm19 {k1}
+vpsravw %xmm16, %xmm17, %xmm19 {z}{k1}
+vpsravw (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpsravw %ymm16, %ymm17, %ymm19
+vpsravw (%rax), %ymm17, %ymm19
+vpsravw %ymm16, %ymm17, %ymm19 {k1}
+vpsravw (%rax), %ymm17, %ymm19 {k1}
+vpsravw %ymm16, %ymm17, %ymm19 {z}{k1}
+vpsravw (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpsraw $0, %xmm16, %xmm19
+vpsraw $0, (%rax), %xmm19
+vpsraw $0, %xmm16, %xmm19 {k1}
+vpsraw $0, (%rax), %xmm19 {k1}
+vpsraw $0, %xmm16, %xmm19 {z}{k1}
+vpsraw $0, (%rax), %xmm19 {z}{k1}
+
+vpsraw $0, %ymm16, %ymm19
+vpsraw $0, (%rax), %ymm19
+vpsraw $0, %ymm16, %ymm19 {k1}
+vpsraw $0, (%rax), %ymm19 {k1}
+vpsraw $0, %ymm16, %ymm19 {z}{k1}
+vpsraw $0, (%rax), %ymm19 {z}{k1}
+
+vpsraw %xmm16, %xmm17, %xmm19
+vpsraw (%rax), %xmm17, %xmm19
+vpsraw %xmm16, %xmm17, %xmm19 {k1}
+vpsraw (%rax), %xmm17, %xmm19 {k1}
+vpsraw %xmm16, %xmm17, %xmm19 {z}{k1}
+vpsraw (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpsraw %xmm16, %ymm17, %ymm19
+vpsraw (%rax), %ymm17, %ymm19
+vpsraw %xmm16, %ymm17, %ymm19 {k1}
+vpsraw (%rax), %ymm17, %ymm19 {k1}
+vpsraw %xmm16, %ymm17, %ymm19 {z}{k1}
+vpsraw (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpsrldq $1, %xmm16, %xmm19
+vpsrldq $1, (%rax), %xmm19
+
+vpsrldq $1, %ymm16, %ymm19
+vpsrldq $1, (%rax), %ymm19
+
+vpsrlvw %xmm16, %xmm17, %xmm19
+vpsrlvw (%rax), %xmm17, %xmm19
+vpsrlvw %xmm16, %xmm17, %xmm19 {k1}
+vpsrlvw (%rax), %xmm17, %xmm19 {k1}
+vpsrlvw %xmm16, %xmm17, %xmm19 {z}{k1}
+vpsrlvw (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpsrlvw %ymm16, %ymm17, %ymm19
+vpsrlvw (%rax), %ymm17, %ymm19
+vpsrlvw %ymm16, %ymm17, %ymm19 {k1}
+vpsrlvw (%rax), %ymm17, %ymm19 {k1}
+vpsrlvw %ymm16, %ymm17, %ymm19 {z}{k1}
+vpsrlvw (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpsrlw $0, %xmm16, %xmm19
+vpsrlw $0, (%rax), %xmm19
+vpsrlw $0, %xmm16, %xmm19 {k1}
+vpsrlw $0, (%rax), %xmm19 {k1}
+vpsrlw $0, %xmm16, %xmm19 {z}{k1}
+vpsrlw $0, (%rax), %xmm19 {z}{k1}
+
+vpsrlw $0, %ymm16, %ymm19
+vpsrlw $0, (%rax), %ymm19
+vpsrlw $0, %ymm16, %ymm19 {k1}
+vpsrlw $0, (%rax), %ymm19 {k1}
+vpsrlw $0, %ymm16, %ymm19 {z}{k1}
+vpsrlw $0, (%rax), %ymm19 {z}{k1}
+
+vpsrlw %xmm16, %xmm17, %xmm19
+vpsrlw (%rax), %xmm17, %xmm19
+vpsrlw %xmm16, %xmm17, %xmm19 {k1}
+vpsrlw (%rax), %xmm17, %xmm19 {k1}
+vpsrlw %xmm16, %xmm17, %xmm19 {z}{k1}
+vpsrlw (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpsrlw %xmm16, %ymm17, %ymm19
+vpsrlw (%rax), %ymm17, %ymm19
+vpsrlw %xmm16, %ymm17, %ymm19 {k1}
+vpsrlw (%rax), %ymm17, %ymm19 {k1}
+vpsrlw %xmm16, %ymm17, %ymm19 {z}{k1}
+vpsrlw (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpsubb %xmm16, %xmm17, %xmm19
+vpsubb (%rax), %xmm17, %xmm19
+vpsubb %xmm16, %xmm17, %xmm19 {k1}
+vpsubb (%rax), %xmm17, %xmm19 {k1}
+vpsubb %xmm16, %xmm17, %xmm19 {z}{k1}
+vpsubb (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpsubb %ymm16, %ymm17, %ymm19
+vpsubb (%rax), %ymm17, %ymm19
+vpsubb %ymm16, %ymm17, %ymm19 {k1}
+vpsubb (%rax), %ymm17, %ymm19 {k1}
+vpsubb %ymm16, %ymm17, %ymm19 {z}{k1}
+vpsubb (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpsubsb %xmm16, %xmm17, %xmm19
+vpsubsb (%rax), %xmm17, %xmm19
+vpsubsb %xmm16, %xmm17, %xmm19 {k1}
+vpsubsb (%rax), %xmm17, %xmm19 {k1}
+vpsubsb %xmm16, %xmm17, %xmm19 {z}{k1}
+vpsubsb (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpsubsb %ymm16, %ymm17, %ymm19
+vpsubsb (%rax), %ymm17, %ymm19
+vpsubsb %ymm16, %ymm17, %ymm19 {k1}
+vpsubsb (%rax), %ymm17, %ymm19 {k1}
+vpsubsb %ymm16, %ymm17, %ymm19 {z}{k1}
+vpsubsb (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpsubsw %xmm16, %xmm17, %xmm19
+vpsubsw (%rax), %xmm17, %xmm19
+vpsubsw %xmm16, %xmm17, %xmm19 {k1}
+vpsubsw (%rax), %xmm17, %xmm19 {k1}
+vpsubsw %xmm16, %xmm17, %xmm19 {z}{k1}
+vpsubsw (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpsubsw %ymm16, %ymm17, %ymm19
+vpsubsw (%rax), %ymm17, %ymm19
+vpsubsw %ymm16, %ymm17, %ymm19 {k1}
+vpsubsw (%rax), %ymm17, %ymm19 {k1}
+vpsubsw %ymm16, %ymm17, %ymm19 {z}{k1}
+vpsubsw (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpsubusb %xmm16, %xmm17, %xmm19
+vpsubusb (%rax), %xmm17, %xmm19
+vpsubusb %xmm16, %xmm17, %xmm19 {k1}
+vpsubusb (%rax), %xmm17, %xmm19 {k1}
+vpsubusb %xmm16, %xmm17, %xmm19 {z}{k1}
+vpsubusb (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpsubusb %ymm16, %ymm17, %ymm19
+vpsubusb (%rax), %ymm17, %ymm19
+vpsubusb %ymm16, %ymm17, %ymm19 {k1}
+vpsubusb (%rax), %ymm17, %ymm19 {k1}
+vpsubusb %ymm16, %ymm17, %ymm19 {z}{k1}
+vpsubusb (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpsubusw %xmm16, %xmm17, %xmm19
+vpsubusw (%rax), %xmm17, %xmm19
+vpsubusw %xmm16, %xmm17, %xmm19 {k1}
+vpsubusw (%rax), %xmm17, %xmm19 {k1}
+vpsubusw %xmm16, %xmm17, %xmm19 {z}{k1}
+vpsubusw (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpsubusw %ymm16, %ymm17, %ymm19
+vpsubusw (%rax), %ymm17, %ymm19
+vpsubusw %ymm16, %ymm17, %ymm19 {k1}
+vpsubusw (%rax), %ymm17, %ymm19 {k1}
+vpsubusw %ymm16, %ymm17, %ymm19 {z}{k1}
+vpsubusw (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpsubw %xmm16, %xmm17, %xmm19
+vpsubw (%rax), %xmm17, %xmm19
+vpsubw %xmm16, %xmm17, %xmm19 {k1}
+vpsubw (%rax), %xmm17, %xmm19 {k1}
+vpsubw %xmm16, %xmm17, %xmm19 {z}{k1}
+vpsubw (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpsubw %ymm16, %ymm17, %ymm19
+vpsubw (%rax), %ymm17, %ymm19
+vpsubw %ymm16, %ymm17, %ymm19 {k1}
+vpsubw (%rax), %ymm17, %ymm19 {k1}
+vpsubw %ymm16, %ymm17, %ymm19 {z}{k1}
+vpsubw (%rax), %ymm17, %ymm19 {z}{k1}
+
+vptestmb %xmm0, %xmm1, %k2
+vptestmb (%rax), %xmm1, %k2
+vptestmb %xmm0, %xmm1, %k2 {k3}
+vptestmb (%rax), %xmm1, %k2 {k3}
+
+vptestmb %ymm0, %ymm1, %k2
+vptestmb (%rax), %ymm1, %k2
+vptestmb %ymm0, %ymm1, %k2 {k3}
+vptestmb (%rax), %ymm1, %k2 {k3}
+
+vptestmw %xmm0, %xmm1, %k2
+vptestmw (%rax), %xmm1, %k2
+vptestmw %xmm0, %xmm1, %k2 {k3}
+vptestmw (%rax), %xmm1, %k2 {k3}
+
+vptestmw %ymm0, %ymm1, %k2
+vptestmw (%rax), %ymm1, %k2
+vptestmw %ymm0, %ymm1, %k2 {k3}
+vptestmw (%rax), %ymm1, %k2 {k3}
+
+vptestnmb %xmm0, %xmm1, %k2
+vptestnmb (%rax), %xmm1, %k2
+vptestnmb %xmm0, %xmm1, %k2 {k3}
+vptestnmb (%rax), %xmm1, %k2 {k3}
+
+vptestnmb %ymm0, %ymm1, %k2
+vptestnmb (%rax), %ymm1, %k2
+vptestnmb %ymm0, %ymm1, %k2 {k3}
+vptestnmb (%rax), %ymm1, %k2 {k3}
+
+vptestnmw %xmm0, %xmm1, %k2
+vptestnmw (%rax), %xmm1, %k2
+vptestnmw %xmm0, %xmm1, %k2 {k3}
+vptestnmw (%rax), %xmm1, %k2 {k3}
+
+vptestnmw %ymm0, %ymm1, %k2
+vptestnmw (%rax), %ymm1, %k2
+vptestnmw %ymm0, %ymm1, %k2 {k3}
+vptestnmw (%rax), %ymm1, %k2 {k3}
+
+vpunpckhbw %xmm16, %xmm17, %xmm19
+vpunpckhbw (%rax), %xmm17, %xmm19
+vpunpckhbw %xmm16, %xmm17, %xmm19 {k1}
+vpunpckhbw (%rax), %xmm17, %xmm19 {k1}
+vpunpckhbw %xmm16, %xmm17, %xmm19 {z}{k1}
+vpunpckhbw (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpunpckhbw %ymm16, %ymm17, %ymm19
+vpunpckhbw (%rax), %ymm17, %ymm19
+vpunpckhbw %ymm16, %ymm17, %ymm19 {k1}
+vpunpckhbw (%rax), %ymm17, %ymm19 {k1}
+vpunpckhbw %ymm16, %ymm17, %ymm19 {z}{k1}
+vpunpckhbw (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpunpckhwd %xmm16, %xmm17, %xmm19
+vpunpckhwd (%rax), %xmm17, %xmm19
+vpunpckhwd %xmm16, %xmm17, %xmm19 {k1}
+vpunpckhwd (%rax), %xmm17, %xmm19 {k1}
+vpunpckhwd %xmm16, %xmm17, %xmm19 {z}{k1}
+vpunpckhwd (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpunpckhwd %ymm16, %ymm17, %ymm19
+vpunpckhwd (%rax), %ymm17, %ymm19
+vpunpckhwd %ymm16, %ymm17, %ymm19 {k1}
+vpunpckhwd (%rax), %ymm17, %ymm19 {k1}
+vpunpckhwd %ymm16, %ymm17, %ymm19 {z}{k1}
+vpunpckhwd (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpunpcklbw %xmm16, %xmm17, %xmm19
+vpunpcklbw (%rax), %xmm17, %xmm19
+vpunpcklbw %xmm16, %xmm17, %xmm19 {k1}
+vpunpcklbw (%rax), %xmm17, %xmm19 {k1}
+vpunpcklbw %xmm16, %xmm17, %xmm19 {z}{k1}
+vpunpcklbw (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpunpcklbw %ymm16, %ymm17, %ymm19
+vpunpcklbw (%rax), %ymm17, %ymm19
+vpunpcklbw %ymm16, %ymm17, %ymm19 {k1}
+vpunpcklbw (%rax), %ymm17, %ymm19 {k1}
+vpunpcklbw %ymm16, %ymm17, %ymm19 {z}{k1}
+vpunpcklbw (%rax), %ymm17, %ymm19 {z}{k1}
+
+vpunpcklwd %xmm16, %xmm17, %xmm19
+vpunpcklwd (%rax), %xmm17, %xmm19
+vpunpcklwd %xmm16, %xmm17, %xmm19 {k1}
+vpunpcklwd (%rax), %xmm17, %xmm19 {k1}
+vpunpcklwd %xmm16, %xmm17, %xmm19 {z}{k1}
+vpunpcklwd (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpunpcklwd %ymm16, %ymm17, %ymm19
+vpunpcklwd (%rax), %ymm17, %ymm19
+vpunpcklwd %ymm16, %ymm17, %ymm19 {k1}
+vpunpcklwd (%rax), %ymm17, %ymm19 {k1}
+vpunpcklwd %ymm16, %ymm17, %ymm19 {z}{k1}
+vpunpcklwd (%rax), %ymm17, %ymm19 {z}{k1}
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 5 3 3.00 vdbpsadbw $0, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 5 10 3.00 * vdbpsadbw $0, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 5 4 3.00 vdbpsadbw $0, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 5 11 3.00 * vdbpsadbw $0, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 5 3 3.00 vdbpsadbw $0, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 5 10 3.00 * vdbpsadbw $0, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 5 3 3.00 vdbpsadbw $0, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 5 10 3.00 * vdbpsadbw $0, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 5 4 3.00 vdbpsadbw $0, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 5 11 3.00 * vdbpsadbw $0, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 5 3 3.00 vdbpsadbw $0, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 5 10 3.00 * vdbpsadbw $0, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 0 0.25 vmovdqu8 %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vmovdqu8 (%rax), %xmm19
+# CHECK-NEXT: 1 1 0.33 * vmovdqu8 %xmm16, (%rax)
+# CHECK-NEXT: 1 0 0.25 vmovdqu8 %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vmovdqu8 (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.33 * vmovdqu8 %xmm16, (%rax) {%k1}
+# CHECK-NEXT: 1 0 0.25 vmovdqu8 %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vmovdqu8 (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 0 0.25 vmovdqu8 %ymm16, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vmovdqu8 (%rax), %ymm19
+# CHECK-NEXT: 1 1 0.33 * vmovdqu8 %ymm16, (%rax)
+# CHECK-NEXT: 1 0 0.25 vmovdqu8 %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vmovdqu8 (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.33 * vmovdqu8 %ymm16, (%rax) {%k1}
+# CHECK-NEXT: 1 0 0.25 vmovdqu8 %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vmovdqu8 (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 0 0.25 vmovdqu16 %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vmovdqu16 (%rax), %xmm19
+# CHECK-NEXT: 1 1 0.33 * vmovdqu16 %xmm16, (%rax)
+# CHECK-NEXT: 1 0 0.25 vmovdqu16 %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vmovdqu16 (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.33 * vmovdqu16 %xmm16, (%rax) {%k1}
+# CHECK-NEXT: 1 0 0.25 vmovdqu16 %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vmovdqu16 (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 0 0.25 vmovdqu16 %ymm16, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vmovdqu16 (%rax), %ymm19
+# CHECK-NEXT: 1 1 0.33 * vmovdqu16 %ymm16, (%rax)
+# CHECK-NEXT: 1 0 0.25 vmovdqu16 %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vmovdqu16 (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.33 * vmovdqu16 %ymm16, (%rax) {%k1}
+# CHECK-NEXT: 1 0 0.25 vmovdqu16 %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vmovdqu16 (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpabsb %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpabsb (%rax), %xmm19
+# CHECK-NEXT: 1 2 0.50 vpabsb %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpabsb (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpabsb %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpabsb (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpabsb %ymm16, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpabsb (%rax), %ymm19
+# CHECK-NEXT: 1 2 0.50 vpabsb %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpabsb (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpabsb %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpabsb (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpabsw %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpabsw (%rax), %xmm19
+# CHECK-NEXT: 1 2 0.50 vpabsw %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpabsw (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpabsw %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpabsw (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpabsw %ymm16, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpabsw (%rax), %ymm19
+# CHECK-NEXT: 1 2 0.50 vpabsw %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpabsw (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpabsw %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpabsw (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpackssdw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpackssdw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vpackssdw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpackssdw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpackssdw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpackssdw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpackssdw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpackssdw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vpackssdw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpackssdw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpackssdw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpackssdw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpacksswb %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpacksswb (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vpacksswb %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpacksswb (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpacksswb %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpacksswb (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpacksswb %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpacksswb (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vpacksswb %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpacksswb (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpacksswb %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpacksswb (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpackusdw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpackusdw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vpackusdw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpackusdw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpackusdw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpackusdw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpackusdw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpackusdw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vpackusdw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpackusdw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpackusdw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpackusdw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpackuswb %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpackuswb (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vpackuswb %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpackuswb (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpackuswb %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpackuswb (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpackuswb %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpackuswb (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vpackuswb %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpackuswb (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpackuswb %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpackuswb (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpaddb %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpaddb (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vpaddb %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpaddb (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpaddb %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpaddb (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpaddb %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpaddb (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 1 0.25 vpaddb %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpaddb (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpaddb %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpaddb (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpaddsb %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpaddsb (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vpaddsb %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpaddsb (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpaddsb %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpaddsb (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpaddsb %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpaddsb (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vpaddsb %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpaddsb (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpaddsb %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpaddsb (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpaddsw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpaddsw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vpaddsw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpaddsw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpaddsw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpaddsw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpaddsw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpaddsw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vpaddsw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpaddsw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpaddsw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpaddsw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpaddusb %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpaddusb (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vpaddusb %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpaddusb (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpaddusb %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpaddusb (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpaddusb %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpaddusb (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vpaddusb %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpaddusb (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpaddusb %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpaddusb (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpaddusw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpaddusw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vpaddusw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpaddusw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpaddusw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpaddusw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpaddusw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpaddusw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vpaddusw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpaddusw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpaddusw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpaddusw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpaddw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpaddw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vpaddw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpaddw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpaddw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpaddw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpaddw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpaddw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 1 0.25 vpaddw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpaddw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpaddw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpaddw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpalignr $1, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpalignr $1, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vpalignr $1, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpalignr $1, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 2 0.50 vpalignr $1, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 0.50 * vpalignr $1, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpalignr $1, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpalignr $1, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 1.00 vpalignr $1, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpalignr $1, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpalignr $1, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpalignr $1, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpavgb %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpavgb (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vpavgb %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpavgb (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpavgb %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpavgb (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpavgb %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpavgb (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vpavgb %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpavgb (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpavgb %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpavgb (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpavgw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpavgw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vpavgw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpavgw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpavgw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpavgw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpavgw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpavgw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vpavgw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpavgw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpavgw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpavgw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpblendmb %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpblendmb (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.25 vpblendmb %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpblendmb (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpblendmb %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpblendmb (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpblendmb %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpblendmb (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.25 vpblendmb %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpblendmb (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpblendmb %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpblendmb (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpblendmw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpblendmw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.25 vpblendmw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpblendmw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpblendmw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpblendmw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpblendmw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpblendmw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.25 vpblendmw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpblendmw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpblendmw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpblendmw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpbroadcastb %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpbroadcastb (%rax), %xmm19
+# CHECK-NEXT: 1 1 0.50 vpbroadcastb %eax, %xmm19
+# CHECK-NEXT: 1 2 0.50 vpbroadcastb %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpbroadcastb (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 2 0.50 vpbroadcastb %eax, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpbroadcastb %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpbroadcastb (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpbroadcastb %eax, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpbroadcastb %xmm16, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpbroadcastb (%rax), %ymm19
+# CHECK-NEXT: 1 3 0.50 vpbroadcastb %eax, %ymm19
+# CHECK-NEXT: 1 4 2.00 vpbroadcastb %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 2.00 * vpbroadcastb (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 4 2.00 vpbroadcastb %eax, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpbroadcastb %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpbroadcastb (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpbroadcastb %eax, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpbroadcastw %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpbroadcastw (%rax), %xmm19
+# CHECK-NEXT: 1 1 0.50 vpbroadcastw %eax, %xmm19
+# CHECK-NEXT: 1 2 0.50 vpbroadcastw %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpbroadcastw (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 2 0.50 vpbroadcastw %eax, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpbroadcastw %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpbroadcastw (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpbroadcastw %eax, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpbroadcastw %xmm16, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpbroadcastw (%rax), %ymm19
+# CHECK-NEXT: 1 3 0.50 vpbroadcastw %eax, %ymm19
+# CHECK-NEXT: 1 4 2.00 vpbroadcastw %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 2.00 * vpbroadcastw (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 4 2.00 vpbroadcastw %eax, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpbroadcastw %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpbroadcastw (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpbroadcastw %eax, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpcmpeqb %xmm0, %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqb (%rax), %xmm1, %k2
+# CHECK-NEXT: 2 6 0.75 vpcmpeqb %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 0.75 * vpcmpeqb (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpeqb %ymm0, %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqb (%rax), %ymm1, %k2
+# CHECK-NEXT: 2 6 0.75 vpcmpeqb %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 0.75 * vpcmpeqb (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpeqb %xmm0, %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqb (%rax), %xmm1, %k2
+# CHECK-NEXT: 2 6 0.75 vpcmpeqb %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 0.75 * vpcmpeqb (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpeqb %ymm0, %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqb (%rax), %ymm1, %k2
+# CHECK-NEXT: 2 6 0.75 vpcmpeqb %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 0.75 * vpcmpeqb (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpeqw %xmm0, %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqw (%rax), %xmm1, %k2
+# CHECK-NEXT: 2 6 0.75 vpcmpeqw %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 0.75 * vpcmpeqw (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpeqw %ymm0, %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqw (%rax), %ymm1, %k2
+# CHECK-NEXT: 2 6 0.75 vpcmpeqw %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 0.75 * vpcmpeqw (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpgtb %xmm0, %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpgtb (%rax), %xmm1, %k2
+# CHECK-NEXT: 2 6 0.75 vpcmpgtb %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 0.75 * vpcmpgtb (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpgtb %ymm0, %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpgtb (%rax), %ymm1, %k2
+# CHECK-NEXT: 2 6 0.75 vpcmpgtb %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 0.75 * vpcmpgtb (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpgtw %xmm0, %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpgtw (%rax), %xmm1, %k2
+# CHECK-NEXT: 2 6 0.75 vpcmpgtw %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 0.75 * vpcmpgtw (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpgtw %ymm0, %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpgtw (%rax), %ymm1, %k2
+# CHECK-NEXT: 2 6 0.75 vpcmpgtw %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 0.75 * vpcmpgtw (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpequb %xmm0, %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpequb (%rax), %xmm1, %k2
+# CHECK-NEXT: 2 6 0.75 vpcmpequb %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 0.75 * vpcmpequb (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpequb %ymm0, %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpequb (%rax), %ymm1, %k2
+# CHECK-NEXT: 2 6 0.75 vpcmpequb %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 0.75 * vpcmpequb (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpequw %xmm0, %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpequw (%rax), %xmm1, %k2
+# CHECK-NEXT: 2 6 0.75 vpcmpequw %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 0.75 * vpcmpequw (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpequw %ymm0, %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpequw (%rax), %ymm1, %k2
+# CHECK-NEXT: 2 6 0.75 vpcmpequw %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 0.75 * vpcmpequw (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpeqw %xmm0, %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqw (%rax), %xmm1, %k2
+# CHECK-NEXT: 2 6 0.75 vpcmpeqw %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 0.75 * vpcmpeqw (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpeqw %ymm0, %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqw (%rax), %ymm1, %k2
+# CHECK-NEXT: 2 6 0.75 vpcmpeqw %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 0.75 * vpcmpeqw (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 3 2.00 vpermw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 2.00 * vpermw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 4 2.00 vpermw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 11 2.00 * vpermw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 3 2.00 vpermw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 2.00 * vpermw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 2.00 vpermw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 2.00 * vpermw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 4 2.00 vpermw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 2.00 * vpermw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 2.00 vpermw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 2.00 * vpermw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 2.00 vpermi2w %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 2.00 * vpermi2w (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 4 2.00 vpermi2w %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 11 2.00 * vpermi2w (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 3 2.00 vpermi2w %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 2.00 * vpermi2w (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 4 6 4.00 vpermi2w %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 4 13 4.00 * vpermi2w (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 4 6 4.00 vpermi2w %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 4 13 4.00 * vpermi2w (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 4 6 4.00 vpermi2w %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 4 13 4.00 * vpermi2w (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 2.00 vpermt2w %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 2.00 * vpermt2w (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 4 2.00 vpermt2w %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 11 2.00 * vpermt2w (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 3 2.00 vpermt2w %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 2.00 * vpermt2w (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 4 4 4.00 vpermt2w %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 4 11 4.00 * vpermt2w (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 4 4 4.00 vpermt2w %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 4 11 4.00 * vpermt2w (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 4 4 4.00 vpermt2w %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 4 11 4.00 * vpermt2w (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmaddubsw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpmaddubsw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 4 1.00 vpmaddubsw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vpmaddubsw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmaddubsw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmaddubsw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmaddubsw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpmaddubsw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 4 1.00 vpmaddubsw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vpmaddubsw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmaddubsw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmaddubsw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmaddwd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpmaddwd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 4 0.50 vpmaddwd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vpmaddwd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmaddwd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmaddwd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmaddwd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpmaddwd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 4 0.50 vpmaddwd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vpmaddwd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmaddwd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmaddwd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpmaxsb %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpmaxsb (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 1 0.25 vpmaxsb %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpmaxsb (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpmaxsb %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpmaxsb (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpmaxsb %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpmaxsb (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vpmaxsb %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpmaxsb (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpmaxsb %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpmaxsb (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpmaxsw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpmaxsw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 1 0.25 vpmaxsw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpmaxsw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpmaxsw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpmaxsw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpmaxsw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpmaxsw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vpmaxsw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpmaxsw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpmaxsw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpmaxsw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpmaxub %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpmaxub (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 1 0.25 vpmaxub %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpmaxub (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpmaxub %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpmaxub (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpmaxub %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpmaxub (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vpmaxub %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpmaxub (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpmaxub %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpmaxub (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpmaxuw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpmaxuw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 1 0.25 vpmaxuw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpmaxuw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpmaxuw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpmaxuw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpmaxuw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpmaxuw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vpmaxuw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpmaxuw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpmaxuw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpmaxuw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpminsb %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpminsb (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 1 0.25 vpminsb %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpminsb (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpminsb %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpminsb (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpminsb %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpminsb (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vpminsb %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpminsb (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpminsb %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpminsb (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpminsw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpminsw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 1 0.25 vpminsw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpminsw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpminsw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpminsw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpminsw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpminsw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vpminsw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpminsw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpminsw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpminsw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpminub %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpminub (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 1 0.25 vpminub %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpminub (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpminub %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpminub (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpminub %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpminub (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vpminub %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpminub (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpminub %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpminub (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpminuw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpminuw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 1 0.25 vpminuw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpminuw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpminuw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpminuw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpminuw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpminuw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vpminuw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpminuw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpminuw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpminuw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 1.00 vpmovb2m %xmm0, %k0
+# CHECK-NEXT: 1 1 1.00 vpmovw2m %xmm0, %k0
+# CHECK-NEXT: 1 1 1.00 vpmovb2m %ymm0, %k0
+# CHECK-NEXT: 1 1 1.00 vpmovw2m %ymm0, %k0
+# CHECK-NEXT: 1 0 0.25 vpmovm2b %k0, %xmm0
+# CHECK-NEXT: 1 0 0.25 vpmovm2w %k0, %xmm0
+# CHECK-NEXT: 1 0 0.25 vpmovm2b %k0, %ymm0
+# CHECK-NEXT: 1 0 0.25 vpmovm2w %k0, %ymm0
+# CHECK-NEXT: 1 1 0.50 vpmovsxbw %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpmovsxbw (%rax), %xmm19
+# CHECK-NEXT: 1 1 0.50 vpmovsxbw %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpmovsxbw (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpmovsxbw %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpmovsxbw (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovsxbw %xmm16, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpmovsxbw (%rax), %ymm19
+# CHECK-NEXT: 1 3 0.50 vpmovsxbw %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovsxbw (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovsxbw %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmovsxbw (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovswb %xmm16, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpmovswb %xmm16, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovswb %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovswb %xmm16, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovswb %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovswb %ymm16, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpmovswb %ymm16, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovswb %ymm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovswb %ymm16, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovswb %ymm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovuswb %xmm16, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpmovuswb %xmm16, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovuswb %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovuswb %xmm16, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovuswb %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovuswb %ymm16, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpmovuswb %ymm16, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovuswb %ymm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovuswb %ymm16, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovuswb %ymm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovwb %xmm16, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpmovwb %xmm16, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovwb %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovwb %xmm16, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovwb %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovwb %ymm16, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpmovwb %ymm16, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovwb %ymm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovwb %ymm16, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovwb %ymm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpmovzxbw %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpmovzxbw (%rax), %xmm19
+# CHECK-NEXT: 1 1 0.50 vpmovzxbw %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpmovzxbw (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpmovzxbw %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpmovzxbw (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovzxbw %xmm16, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpmovzxbw (%rax), %ymm19
+# CHECK-NEXT: 1 3 0.50 vpmovzxbw %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovzxbw (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovzxbw %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmovzxbw (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmulhrsw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpmulhrsw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 4 1.00 vpmulhrsw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vpmulhrsw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmulhrsw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmulhrsw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmulhrsw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpmulhrsw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 4 1.00 vpmulhrsw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vpmulhrsw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmulhrsw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmulhrsw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmulhuw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpmulhuw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 4 1.00 vpmulhuw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vpmulhuw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmulhuw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmulhuw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmulhuw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpmulhuw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 4 1.00 vpmulhuw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vpmulhuw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmulhuw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmulhuw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmulhw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpmulhw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 4 1.00 vpmulhw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vpmulhw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmulhw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmulhw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmulhw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpmulhw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 4 1.00 vpmulhw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vpmulhw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmulhw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmulhw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmullw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpmullw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 4 1.00 vpmullw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vpmullw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmullw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmullw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmullw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpmullw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 4 1.00 vpmullw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vpmullw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmullw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmullw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 1.00 vpsadbw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 1.00 * vpsadbw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 3 1.00 vpsadbw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 1.00 * vpsadbw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 1 0.50 vpshufb %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpshufb (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vpshufb %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpshufb (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 2 0.50 vpshufb %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 0.50 * vpshufb (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshufb %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpshufb (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vpshufb %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpshufb (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 2 0.50 vpshufb %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 9 0.50 * vpshufb (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshufhw $0, %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpshufhw $0, (%rax), %xmm19
+# CHECK-NEXT: 1 2 0.50 vpshufhw $0, %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpshufhw $0, (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 2 0.50 vpshufhw $0, %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 0.50 * vpshufhw $0, (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshufhw $0, %ymm16, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpshufhw $0, (%rax), %ymm19
+# CHECK-NEXT: 1 2 0.50 vpshufhw $0, %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpshufhw $0, (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 2 0.50 vpshufhw $0, %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 9 0.50 * vpshufhw $0, (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshuflw $0, %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpshuflw $0, (%rax), %xmm19
+# CHECK-NEXT: 1 2 0.50 vpshuflw $0, %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpshuflw $0, (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 2 0.50 vpshuflw $0, %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 0.50 * vpshuflw $0, (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshuflw $0, %ymm16, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpshuflw $0, (%rax), %ymm19
+# CHECK-NEXT: 1 2 0.50 vpshuflw $0, %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpshuflw $0, (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 2 0.50 vpshuflw $0, %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 9 0.50 * vpshuflw $0, (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpslldq $1, %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpslldq $1, (%rax), %xmm19
+# CHECK-NEXT: 1 1 0.50 vpslldq $1, %ymm16, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpslldq $1, (%rax), %ymm19
+# CHECK-NEXT: 1 1 2.00 vpsllvw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 2.00 * vpsllvw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 1.00 vpsllvw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpsllvw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpsllvw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpsllvw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 2.00 vpsllvw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 2.00 * vpsllvw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 1.00 vpsllvw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpsllvw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpsllvw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpsllvw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpsllw $0, %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpsllw $0, (%rax), %xmm19
+# CHECK-NEXT: 1 2 1.00 vpsllw $0, %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpsllw $0, (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpsllw $0, %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpsllw $0, (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpsllw $0, %ymm16, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpsllw $0, (%rax), %ymm19
+# CHECK-NEXT: 1 2 1.00 vpsllw $0, %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpsllw $0, (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpsllw $0, %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpsllw $0, (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpsllw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpsllw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 1.00 vpsllw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpsllw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpsllw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpsllw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpsllw %xmm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpsllw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 4 1.00 vpsllw %xmm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vpsllw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpsllw %xmm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpsllw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 2.00 vpsravw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 2.00 * vpsravw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 1.00 vpsravw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpsravw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpsravw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpsravw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 2.00 vpsravw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 2.00 * vpsravw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 1.00 vpsravw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpsravw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpsravw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpsravw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpsraw $0, %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpsraw $0, (%rax), %xmm19
+# CHECK-NEXT: 1 2 1.00 vpsraw $0, %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpsraw $0, (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpsraw $0, %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpsraw $0, (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpsraw $0, %ymm16, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpsraw $0, (%rax), %ymm19
+# CHECK-NEXT: 1 2 1.00 vpsraw $0, %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpsraw $0, (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpsraw $0, %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpsraw $0, (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpsraw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpsraw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 1.00 vpsraw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpsraw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpsraw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpsraw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpsraw %xmm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpsraw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 4 1.00 vpsraw %xmm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vpsraw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpsraw %xmm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpsraw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpsrldq $1, %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpsrldq $1, (%rax), %xmm19
+# CHECK-NEXT: 1 1 0.50 vpsrldq $1, %ymm16, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpsrldq $1, (%rax), %ymm19
+# CHECK-NEXT: 1 1 2.00 vpsrlvw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 2.00 * vpsrlvw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 1.00 vpsrlvw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpsrlvw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpsrlvw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpsrlvw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 2.00 vpsrlvw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 2.00 * vpsrlvw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 1.00 vpsrlvw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpsrlvw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpsrlvw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpsrlvw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpsrlw $0, %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpsrlw $0, (%rax), %xmm19
+# CHECK-NEXT: 1 2 1.00 vpsrlw $0, %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpsrlw $0, (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpsrlw $0, %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpsrlw $0, (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpsrlw $0, %ymm16, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpsrlw $0, (%rax), %ymm19
+# CHECK-NEXT: 1 2 1.00 vpsrlw $0, %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpsrlw $0, (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpsrlw $0, %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpsrlw $0, (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpsrlw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpsrlw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 1.00 vpsrlw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpsrlw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpsrlw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpsrlw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpsrlw %xmm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpsrlw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 4 1.00 vpsrlw %xmm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vpsrlw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpsrlw %xmm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpsrlw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpsubb %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpsubb (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vpsubb %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpsubb (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpsubb %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpsubb (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpsubb %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpsubb (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 1 0.25 vpsubb %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpsubb (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpsubb %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpsubb (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpsubsb %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpsubsb (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vpsubsb %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpsubsb (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpsubsb %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpsubsb (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpsubsb %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpsubsb (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vpsubsb %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpsubsb (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpsubsb %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpsubsb (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpsubsw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpsubsw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vpsubsw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpsubsw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpsubsw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpsubsw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpsubsw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpsubsw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vpsubsw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpsubsw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpsubsw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpsubsw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpsubusb %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpsubusb (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vpsubusb %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpsubusb (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpsubusb %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpsubusb (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpsubusb %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpsubusb (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vpsubusb %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpsubusb (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpsubusb %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpsubusb (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpsubusw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpsubusw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vpsubusw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpsubusw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpsubusw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpsubusw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpsubusw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpsubusw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vpsubusw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpsubusw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpsubusw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpsubusw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpsubw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpsubw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vpsubw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpsubw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpsubw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpsubw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpsubw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpsubw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 1 0.25 vpsubw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpsubw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpsubw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpsubw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vptestmb %xmm0, %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestmb (%rax), %xmm1, %k2
+# CHECK-NEXT: 2 6 1.00 vptestmb %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 1.00 * vptestmb (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vptestmb %ymm0, %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestmb (%rax), %ymm1, %k2
+# CHECK-NEXT: 2 6 1.00 vptestmb %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 1.00 * vptestmb (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vptestmw %xmm0, %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestmw (%rax), %xmm1, %k2
+# CHECK-NEXT: 2 6 1.00 vptestmw %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 1.00 * vptestmw (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vptestmw %ymm0, %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestmw (%rax), %ymm1, %k2
+# CHECK-NEXT: 2 6 1.00 vptestmw %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 1.00 * vptestmw (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vptestnmb %xmm0, %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestnmb (%rax), %xmm1, %k2
+# CHECK-NEXT: 2 6 1.00 vptestnmb %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 1.00 * vptestnmb (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vptestnmb %ymm0, %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestnmb (%rax), %ymm1, %k2
+# CHECK-NEXT: 2 6 1.00 vptestnmb %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 1.00 * vptestnmb (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vptestnmw %xmm0, %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestnmw (%rax), %xmm1, %k2
+# CHECK-NEXT: 2 6 1.00 vptestnmw %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 1.00 * vptestnmw (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vptestnmw %ymm0, %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestnmw (%rax), %ymm1, %k2
+# CHECK-NEXT: 2 6 1.00 vptestnmw %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 1.00 * vptestnmw (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.50 vpunpckhbw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpunpckhbw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vpunpckhbw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpunpckhbw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 2 0.50 vpunpckhbw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 0.50 * vpunpckhbw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpunpckhbw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpunpckhbw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vpunpckhbw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpunpckhbw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 2 0.50 vpunpckhbw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 9 0.50 * vpunpckhbw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpunpckhwd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpunpckhwd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vpunpckhwd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpunpckhwd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 2 0.50 vpunpckhwd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 0.50 * vpunpckhwd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpunpckhwd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpunpckhwd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vpunpckhwd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpunpckhwd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 2 0.50 vpunpckhwd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 9 0.50 * vpunpckhwd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpunpcklbw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpunpcklbw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vpunpcklbw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpunpcklbw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 2 0.50 vpunpcklbw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 0.50 * vpunpcklbw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpunpcklbw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpunpcklbw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vpunpcklbw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpunpcklbw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 2 0.50 vpunpcklbw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 9 0.50 * vpunpcklbw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpunpcklwd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpunpcklwd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vpunpcklwd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpunpcklwd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 2 0.50 vpunpcklwd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 0.50 * vpunpcklwd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpunpcklwd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpunpcklwd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vpunpcklwd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpunpcklwd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 2 0.50 vpunpcklwd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 9 0.50 * vpunpcklwd (%rax), %ymm17, %ymm19 {%k1} {z}
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 150.67 150.67 150.67 4.00 4.00 4.00 4.00 - 463.00 344.00 457.00 338.00 113.00 113.00 113.00 113.00 148.00 148.00 148.00 2.00 2.00 2.00 2.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - vdbpsadbw $0, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 3.00 3.00 3.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdbpsadbw $0, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - vdbpsadbw $0, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 3.00 3.00 3.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdbpsadbw $0, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - vdbpsadbw $0, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 3.00 3.00 3.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdbpsadbw $0, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - vdbpsadbw $0, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 3.00 3.00 3.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdbpsadbw $0, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - vdbpsadbw $0, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 3.00 3.00 3.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdbpsadbw $0, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - vdbpsadbw $0, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.00 3.00 3.00 3.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdbpsadbw $0, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu8 %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu8 (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqu8 %xmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu8 %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu8 (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqu8 %xmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu8 %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu8 (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu8 %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu8 (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqu8 %ymm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu8 %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu8 (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqu8 %ymm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu8 %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu8 (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu16 %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu16 (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqu16 %xmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu16 %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu16 (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqu16 %xmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu16 %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu16 (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu16 %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu16 (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqu16 %ymm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu16 %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu16 (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqu16 %ymm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu16 %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu16 (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpabsb %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsb (%rax), %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpabsb %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsb (%rax), %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpabsb %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsb (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpabsb %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsb (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpabsb %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsb (%rax), %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpabsb %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsb (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpabsw %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsw (%rax), %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpabsw %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsw (%rax), %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpabsw %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsw (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpabsw %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsw (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpabsw %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsw (%rax), %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpabsw %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpabsw (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpackssdw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackssdw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpackssdw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackssdw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpackssdw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackssdw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpackssdw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackssdw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpackssdw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackssdw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpackssdw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackssdw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpacksswb %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpacksswb (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpacksswb %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpacksswb (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpacksswb %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpacksswb (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpacksswb %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpacksswb (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpacksswb %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpacksswb (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpacksswb %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpacksswb (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpackusdw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackusdw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpackusdw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackusdw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpackusdw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackusdw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpackusdw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackusdw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpackusdw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackusdw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpackusdw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackusdw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpackuswb %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackuswb (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpackuswb %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackuswb (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpackuswb %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackuswb (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpackuswb %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackuswb (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpackuswb %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackuswb (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpackuswb %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpackuswb (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddb %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddb (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddb %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddb (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddb %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddb (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddb %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddb (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddb %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddb (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddb %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddb (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddsb %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddsb (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddsb %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddsb (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddsb %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddsb (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddsb %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddsb (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddsb %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddsb (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddsb %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddsb (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddsw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddsw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddsw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddsw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddsw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddsw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddsw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddsw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddsw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddsw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddsw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddsw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddusb %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddusb (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddusb %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddusb (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddusb %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddusb (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddusb %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddusb (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddusb %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddusb (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddusb %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddusb (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddusw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddusw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddusw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddusw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddusw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddusw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddusw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddusw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddusw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddusw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddusw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddusw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpaddw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpalignr $1, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpalignr $1, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpalignr $1, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpalignr $1, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpalignr $1, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpalignr $1, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpalignr $1, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpalignr $1, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpalignr $1, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpalignr $1, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vpalignr $1, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpalignr $1, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpavgb %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpavgb (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpavgb %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpavgb (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpavgb %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpavgb (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpavgb %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpavgb (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpavgb %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpavgb (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpavgb %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpavgb (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpavgw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpavgw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpavgw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpavgw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpavgw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpavgw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpavgw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpavgw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpavgw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpavgw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpavgw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpavgw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpblendmb %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpblendmb (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpblendmb %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpblendmb (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpblendmb %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpblendmb (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpblendmb %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpblendmb (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpblendmb %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpblendmb (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpblendmb %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpblendmb (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpblendmw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpblendmw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpblendmw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpblendmw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpblendmw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpblendmw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpblendmw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpblendmw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpblendmw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpblendmw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpblendmw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpblendmw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpbroadcastb %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastb (%rax), %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpbroadcastb %eax, %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpbroadcastb %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastb (%rax), %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpbroadcastb %eax, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpbroadcastb %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastb (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpbroadcastb %eax, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpbroadcastb %xmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastb (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpbroadcastb %eax, %ymm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpbroadcastb %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastb (%rax), %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpbroadcastb %eax, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpbroadcastb %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastb (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpbroadcastb %eax, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpbroadcastw %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastw (%rax), %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpbroadcastw %eax, %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpbroadcastw %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastw (%rax), %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpbroadcastw %eax, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpbroadcastw %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastw (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpbroadcastw %eax, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpbroadcastw %xmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastw (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpbroadcastw %eax, %ymm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpbroadcastw %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastw (%rax), %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpbroadcastw %eax, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpbroadcastw %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastw (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpbroadcastw %eax, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpeqb %xmm0, %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqb (%rax), %xmm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 1.00 0.50 1.00 - - - - - - - - - - - vpcmpeqb %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 1.00 0.50 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqb (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpeqb %ymm0, %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqb (%rax), %ymm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 1.00 0.50 1.00 - - - - - - - - - - - vpcmpeqb %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 1.00 0.50 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqb (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpeqb %xmm0, %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqb (%rax), %xmm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 1.00 0.50 1.00 - - - - - - - - - - - vpcmpeqb %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 1.00 0.50 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqb (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpeqb %ymm0, %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqb (%rax), %ymm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 1.00 0.50 1.00 - - - - - - - - - - - vpcmpeqb %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 1.00 0.50 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqb (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpeqw %xmm0, %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqw (%rax), %xmm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 1.00 0.50 1.00 - - - - - - - - - - - vpcmpeqw %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 1.00 0.50 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqw (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpeqw %ymm0, %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqw (%rax), %ymm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 1.00 0.50 1.00 - - - - - - - - - - - vpcmpeqw %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 1.00 0.50 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqw (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpgtb %xmm0, %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtb (%rax), %xmm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 1.00 0.50 1.00 - - - - - - - - - - - vpcmpgtb %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 1.00 0.50 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtb (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpgtb %ymm0, %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtb (%rax), %ymm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 1.00 0.50 1.00 - - - - - - - - - - - vpcmpgtb %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 1.00 0.50 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtb (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpgtw %xmm0, %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtw (%rax), %xmm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 1.00 0.50 1.00 - - - - - - - - - - - vpcmpgtw %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 1.00 0.50 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtw (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpgtw %ymm0, %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtw (%rax), %ymm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 1.00 0.50 1.00 - - - - - - - - - - - vpcmpgtw %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 1.00 0.50 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtw (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpequb %xmm0, %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequb (%rax), %xmm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 1.00 0.50 1.00 - - - - - - - - - - - vpcmpequb %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 1.00 0.50 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequb (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpequb %ymm0, %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequb (%rax), %ymm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 1.00 0.50 1.00 - - - - - - - - - - - vpcmpequb %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 1.00 0.50 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequb (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpequw %xmm0, %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequw (%rax), %xmm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 1.00 0.50 1.00 - - - - - - - - - - - vpcmpequw %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 1.00 0.50 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequw (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpequw %ymm0, %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequw (%rax), %ymm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 1.00 0.50 1.00 - - - - - - - - - - - vpcmpequw %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 1.00 0.50 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequw (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpeqw %xmm0, %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqw (%rax), %xmm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 1.00 0.50 1.00 - - - - - - - - - - - vpcmpeqw %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 1.00 0.50 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqw (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpeqw %ymm0, %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqw (%rax), %ymm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 1.00 0.50 1.00 - - - - - - - - - - - vpcmpeqw %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 1.00 0.50 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqw (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermi2w %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermi2w (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermi2w %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermi2w (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermi2w %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermi2w (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 4.00 4.00 4.00 4.00 - - - - - - - - - - - vpermi2w %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 4.00 4.00 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermi2w (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 4.00 4.00 4.00 4.00 - - - - - - - - - - - vpermi2w %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 4.00 4.00 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermi2w (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 4.00 4.00 4.00 4.00 - - - - - - - - - - - vpermi2w %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 4.00 4.00 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermi2w (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermt2w %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermt2w (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermt2w %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermt2w (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermt2w %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermt2w (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 4.00 4.00 4.00 4.00 - - - - - - - - - - - vpermt2w %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 4.00 4.00 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermt2w (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 4.00 4.00 4.00 4.00 - - - - - - - - - - - vpermt2w %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 4.00 4.00 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermt2w (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 4.00 4.00 4.00 4.00 - - - - - - - - - - - vpermt2w %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 4.00 4.00 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermt2w (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmaddubsw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaddubsw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmaddubsw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaddubsw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmaddubsw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaddubsw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmaddubsw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaddubsw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmaddubsw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaddubsw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmaddubsw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaddubsw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmaddwd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaddwd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmaddwd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaddwd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmaddwd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaddwd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmaddwd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaddwd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmaddwd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaddwd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmaddwd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaddwd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxsb %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxsb (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxsb %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxsb (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxsb %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxsb (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxsb %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxsb (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpmaxsb %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxsb (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxsb %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxsb (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxsw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxsw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxsw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxsw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxsw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxsw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxsw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxsw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpmaxsw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxsw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxsw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxsw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxub %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxub (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxub %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxub (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxub %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxub (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxub %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxub (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpmaxub %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxub (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxub %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxub (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxuw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxuw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxuw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxuw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxuw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxuw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxuw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxuw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpmaxuw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxuw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpmaxuw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmaxuw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminsb %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminsb (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminsb %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminsb (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminsb %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminsb (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminsb %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminsb (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpminsb %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminsb (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminsb %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminsb (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminsw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminsw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminsw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminsw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminsw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminsw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminsw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminsw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpminsw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminsw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminsw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminsw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminub %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminub (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminub %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminub (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminub %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminub (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminub %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminub (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpminub %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminub (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminub %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminub (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminuw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminuw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminuw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminuw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminuw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminuw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminuw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminuw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpminuw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminuw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpminuw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpminuw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - vpmovb2m %xmm0, %k0
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - vpmovw2m %xmm0, %k0
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - vpmovb2m %ymm0, %k0
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - vpmovw2m %ymm0, %k0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpmovm2b %k0, %xmm0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpmovm2w %k0, %xmm0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpmovm2b %k0, %ymm0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpmovm2w %k0, %ymm0
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovsxbw %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbw (%rax), %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovsxbw %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbw (%rax), %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovsxbw %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbw (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxbw %xmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbw (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxbw %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbw (%rax), %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxbw %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbw (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovswb %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovswb %xmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovswb %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovswb %xmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovswb %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovswb %ymm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovswb %ymm16, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovswb %ymm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovswb %ymm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovswb %ymm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovuswb %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovuswb %xmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovuswb %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovuswb %xmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovuswb %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovuswb %ymm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovuswb %ymm16, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovuswb %ymm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovuswb %ymm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovuswb %ymm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovwb %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovwb %xmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovwb %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovwb %xmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovwb %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovwb %ymm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovwb %ymm16, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovwb %ymm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovwb %ymm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovwb %ymm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovzxbw %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbw (%rax), %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovzxbw %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbw (%rax), %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovzxbw %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbw (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxbw %xmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbw (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxbw %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbw (%rax), %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxbw %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbw (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmulhrsw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhrsw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmulhrsw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhrsw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmulhrsw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhrsw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmulhrsw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhrsw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmulhrsw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhrsw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmulhrsw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhrsw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmulhuw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhuw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmulhuw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhuw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmulhuw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhuw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmulhuw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhuw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmulhuw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhuw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmulhuw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhuw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmulhw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmulhw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmulhw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmulhw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmulhw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmulhw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulhw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmullw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmullw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmullw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmullw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmullw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmullw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmullw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmullw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmullw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmullw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmullw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmullw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsadbw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsadbw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsadbw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsadbw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpshufb %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufb (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpshufb %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufb (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpshufb %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufb (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpshufb %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufb (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpshufb %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufb (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpshufb %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufb (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpshufhw $0, %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufhw $0, (%rax), %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpshufhw $0, %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufhw $0, (%rax), %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpshufhw $0, %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufhw $0, (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpshufhw $0, %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufhw $0, (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpshufhw $0, %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufhw $0, (%rax), %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpshufhw $0, %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufhw $0, (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpshuflw $0, %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshuflw $0, (%rax), %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpshuflw $0, %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshuflw $0, (%rax), %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpshuflw $0, %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshuflw $0, (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpshuflw $0, %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshuflw $0, (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpshuflw $0, %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshuflw $0, (%rax), %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpshuflw $0, %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshuflw $0, (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpslldq $1, %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpslldq $1, (%rax), %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpslldq $1, %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpslldq $1, (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpsllvw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllvw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsllvw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllvw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsllvw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllvw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpsllvw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllvw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsllvw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllvw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsllvw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllvw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsllw $0, %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllw $0, (%rax), %xmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsllw $0, %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllw $0, (%rax), %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsllw $0, %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllw $0, (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsllw $0, %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllw $0, (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsllw $0, %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllw $0, (%rax), %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsllw $0, %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllw $0, (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsllw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsllw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsllw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsllw %xmm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsllw %xmm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsllw %xmm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsllw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpsravw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsravw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsravw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsravw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsravw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsravw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpsravw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsravw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsravw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsravw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsravw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsravw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsraw $0, %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsraw $0, (%rax), %xmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsraw $0, %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsraw $0, (%rax), %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsraw $0, %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsraw $0, (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsraw $0, %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsraw $0, (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsraw $0, %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsraw $0, (%rax), %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsraw $0, %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsraw $0, (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsraw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsraw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsraw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsraw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsraw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsraw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsraw %xmm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsraw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsraw %xmm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsraw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsraw %xmm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsraw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpsrldq $1, %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrldq $1, (%rax), %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpsrldq $1, %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrldq $1, (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpsrlvw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlvw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsrlvw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlvw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsrlvw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlvw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpsrlvw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlvw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsrlvw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlvw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsrlvw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlvw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsrlw $0, %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlw $0, (%rax), %xmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsrlw $0, %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlw $0, (%rax), %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsrlw $0, %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlw $0, (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsrlw $0, %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlw $0, (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsrlw $0, %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlw $0, (%rax), %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsrlw $0, %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlw $0, (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsrlw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsrlw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsrlw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsrlw %xmm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpsrlw %xmm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpsrlw %xmm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsrlw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubb %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubb (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubb %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubb (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubb %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubb (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubb %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubb (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubb %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubb (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubb %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubb (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubsb %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubsb (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubsb %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubsb (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubsb %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubsb (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubsb %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubsb (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubsb %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubsb (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubsb %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubsb (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubsw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubsw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubsw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubsw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubsw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubsw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubsw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubsw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubsw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubsw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubsw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubsw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubusb %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubusb (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubusb %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubusb (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubusb %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubusb (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubusb %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubusb (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubusb %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubusb (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubusb %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubusb (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubusw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubusw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubusw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubusw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubusw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubusw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubusw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubusw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubusw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubusw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubusw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubusw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpsubw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vptestmb %xmm0, %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmb (%rax), %xmm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.75 1.25 0.75 1.25 - - - - - - - - - - - vptestmb %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.75 1.25 0.75 1.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmb (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vptestmb %ymm0, %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmb (%rax), %ymm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.75 1.25 0.75 1.25 - - - - - - - - - - - vptestmb %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.75 1.25 0.75 1.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmb (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vptestmw %xmm0, %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmw (%rax), %xmm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.75 1.25 0.75 1.25 - - - - - - - - - - - vptestmw %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.75 1.25 0.75 1.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmw (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vptestmw %ymm0, %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmw (%rax), %ymm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.75 1.25 0.75 1.25 - - - - - - - - - - - vptestmw %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.75 1.25 0.75 1.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmw (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vptestnmb %xmm0, %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmb (%rax), %xmm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.75 1.25 0.75 1.25 - - - - - - - - - - - vptestnmb %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.75 1.25 0.75 1.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmb (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vptestnmb %ymm0, %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmb (%rax), %ymm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.75 1.25 0.75 1.25 - - - - - - - - - - - vptestnmb %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.75 1.25 0.75 1.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmb (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vptestnmw %xmm0, %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmw (%rax), %xmm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.75 1.25 0.75 1.25 - - - - - - - - - - - vptestnmw %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.75 1.25 0.75 1.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmw (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vptestnmw %ymm0, %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmw (%rax), %ymm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.75 1.25 0.75 1.25 - - - - - - - - - - - vptestnmw %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.75 1.25 0.75 1.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmw (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckhbw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhbw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckhbw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhbw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckhbw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhbw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckhbw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhbw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckhbw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhbw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckhbw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhbw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckhwd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhwd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckhwd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhwd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckhwd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhwd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckhwd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhwd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckhwd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhwd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckhwd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhwd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpcklbw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpcklbw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpcklbw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpcklbw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpcklbw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpcklbw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpcklbw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpcklbw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpcklbw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpcklbw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpcklbw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpcklbw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpcklwd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpcklwd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpcklwd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpcklwd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpcklwd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpcklwd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpcklwd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpcklwd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpcklwd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpcklwd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpcklwd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpcklwd (%rax), %ymm17, %ymm19 {%k1} {z}
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512cd.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512cd.s
new file mode 100644
index 0000000000000..e87aad4ba99ad
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512cd.s
@@ -0,0 +1,164 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+vpbroadcastmb2q %k0, %zmm16
+
+vpbroadcastmw2d %k0, %zmm16
+
+vpconflictd %zmm16, %zmm19
+vpconflictd (%rax), %zmm19
+vpconflictd (%rax){1to16}, %zmm19
+vpconflictd %zmm16, %zmm19 {k1}
+vpconflictd (%rax), %zmm19 {k1}
+vpconflictd (%rax){1to16}, %zmm19 {k1}
+vpconflictd %zmm16, %zmm19 {z}{k1}
+vpconflictd (%rax), %zmm19 {z}{k1}
+vpconflictd (%rax){1to16}, %zmm19 {z}{k1}
+
+vpconflictq %zmm16, %zmm19
+vpconflictq (%rax), %zmm19
+vpconflictq (%rax){1to8}, %zmm19
+vpconflictq %zmm16, %zmm19 {k1}
+vpconflictq (%rax), %zmm19 {k1}
+vpconflictq (%rax){1to8}, %zmm19 {k1}
+vpconflictq %zmm16, %zmm19 {z}{k1}
+vpconflictq (%rax), %zmm19 {z}{k1}
+vpconflictq (%rax){1to8}, %zmm19 {z}{k1}
+
+vplzcntd %zmm16, %zmm19
+vplzcntd (%rax), %zmm19
+vplzcntd (%rax){1to16}, %zmm19
+vplzcntd %zmm16, %zmm19 {k1}
+vplzcntd (%rax), %zmm19 {k1}
+vplzcntd (%rax){1to16}, %zmm19 {k1}
+vplzcntd %zmm16, %zmm19 {z}{k1}
+vplzcntd (%rax), %zmm19 {z}{k1}
+vplzcntd (%rax){1to16}, %zmm19 {z}{k1}
+
+vplzcntq %zmm16, %zmm19
+vplzcntq (%rax), %zmm19
+vplzcntq (%rax){1to8}, %zmm19
+vplzcntq %zmm16, %zmm19 {k1}
+vplzcntq (%rax), %zmm19 {k1}
+vplzcntq (%rax){1to8}, %zmm19 {k1}
+vplzcntq %zmm16, %zmm19 {z}{k1}
+vplzcntq (%rax), %zmm19 {z}{k1}
+vplzcntq (%rax){1to8}, %zmm19 {z}{k1}
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.50 vpbroadcastmb2q %k0, %zmm16
+# CHECK-NEXT: 1 1 0.50 vpbroadcastmw2d %k0, %zmm16
+# CHECK-NEXT: 16 7 6.00 vpconflictd %zmm16, %zmm19
+# CHECK-NEXT: 16 14 6.00 * vpconflictd (%rax), %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpconflictd (%rax){1to16}, %zmm19
+# CHECK-NEXT: 16 6 6.00 vpconflictd %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 16 13 6.00 * vpconflictd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpconflictd (%rax){1to16}, %zmm19 {%k1}
+# CHECK-NEXT: 16 7 6.00 vpconflictd %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 16 14 6.00 * vpconflictd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpconflictd (%rax){1to16}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 16 7 6.00 vpconflictq %zmm16, %zmm19
+# CHECK-NEXT: 16 14 6.00 * vpconflictq (%rax), %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpconflictq (%rax){1to8}, %zmm19
+# CHECK-NEXT: 16 6 6.00 vpconflictq %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 16 13 6.00 * vpconflictq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpconflictq (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: 16 7 6.00 vpconflictq %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 16 14 6.00 * vpconflictq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpconflictq (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 1.00 vplzcntd %zmm16, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vplzcntd (%rax), %zmm19
+# CHECK-NEXT: 1 10 1.00 * vplzcntd (%rax){1to16}, %zmm19
+# CHECK-NEXT: 1 1 0.50 vplzcntd %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vplzcntd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 10 1.00 * vplzcntd (%rax){1to16}, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vplzcntd %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vplzcntd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vplzcntd (%rax){1to16}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 1.00 vplzcntq %zmm16, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vplzcntq (%rax), %zmm19
+# CHECK-NEXT: 1 10 1.00 * vplzcntq (%rax){1to8}, %zmm19
+# CHECK-NEXT: 1 1 0.50 vplzcntq %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vplzcntq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 10 1.00 * vplzcntq (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vplzcntq %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vplzcntq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vplzcntq (%rax){1to8}, %zmm19 {%k1} {z}
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 8.00 8.00 8.00 - - - - - 17.00 80.00 17.00 80.00 6.00 6.00 6.00 6.00 8.00 8.00 8.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpbroadcastmb2q %k0, %zmm16
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpbroadcastmw2d %k0, %zmm16
+# CHECK-NEXT: - - - - - - - - - 6.00 - 6.00 - - - - - - - - - - - vpconflictd %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.00 - 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictd (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictd (%rax){1to16}, %zmm19
+# CHECK-NEXT: - - - - - - - - - 6.00 - 6.00 - - - - - - - - - - - vpconflictd %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.00 - 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictd (%rax){1to16}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 6.00 - 6.00 - - - - - - - - - - - vpconflictd %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.00 - 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictd (%rax){1to16}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 6.00 - 6.00 - - - - - - - - - - - vpconflictq %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.00 - 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictq (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictq (%rax){1to8}, %zmm19
+# CHECK-NEXT: - - - - - - - - - 6.00 - 6.00 - - - - - - - - - - - vpconflictq %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.00 - 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictq (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 6.00 - 6.00 - - - - - - - - - - - vpconflictq %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.00 - 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictq (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vplzcntd %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntd (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntd (%rax){1to16}, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vplzcntd %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntd (%rax){1to16}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vplzcntd %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntd (%rax){1to16}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vplzcntq %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntq (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntq (%rax){1to8}, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vplzcntq %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntq (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vplzcntq %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntq (%rax){1to8}, %zmm19 {%k1} {z}
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512cdvl.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512cdvl.s
new file mode 100644
index 0000000000000..05198c2143416
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512cdvl.s
@@ -0,0 +1,282 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+vpbroadcastmb2q %k0, %xmm16
+vpbroadcastmb2q %k0, %ymm16
+
+vpbroadcastmw2d %k0, %xmm16
+vpbroadcastmw2d %k0, %ymm16
+
+vpconflictd %xmm16, %xmm19
+vpconflictd (%rax), %xmm19
+vpconflictd (%rax){1to4}, %xmm19
+vpconflictd %xmm16, %xmm19 {k1}
+vpconflictd (%rax), %xmm19 {k1}
+vpconflictd (%rax){1to4}, %xmm19 {k1}
+vpconflictd %xmm16, %xmm19 {z}{k1}
+vpconflictd (%rax), %xmm19 {z}{k1}
+vpconflictd (%rax){1to4}, %xmm19 {z}{k1}
+
+vpconflictd %ymm16, %ymm19
+vpconflictd (%rax), %ymm19
+vpconflictd (%rax){1to8}, %ymm19
+vpconflictd %ymm16, %ymm19 {k1}
+vpconflictd (%rax), %ymm19 {k1}
+vpconflictd (%rax){1to8}, %ymm19 {k1}
+vpconflictd %ymm16, %ymm19 {z}{k1}
+vpconflictd (%rax), %ymm19 {z}{k1}
+vpconflictd (%rax){1to8}, %ymm19 {z}{k1}
+
+vpconflictq %xmm16, %xmm19
+vpconflictq (%rax), %xmm19
+vpconflictq (%rax){1to2}, %xmm19
+vpconflictq %xmm16, %xmm19 {k1}
+vpconflictq (%rax), %xmm19 {k1}
+vpconflictq (%rax){1to2}, %xmm19 {k1}
+vpconflictq %xmm16, %xmm19 {z}{k1}
+vpconflictq (%rax), %xmm19 {z}{k1}
+vpconflictq (%rax){1to2}, %xmm19 {z}{k1}
+
+vpconflictq %ymm16, %ymm19
+vpconflictq (%rax), %ymm19
+vpconflictq (%rax){1to4}, %ymm19
+vpconflictq %ymm16, %ymm19 {k1}
+vpconflictq (%rax), %ymm19 {k1}
+vpconflictq (%rax){1to4}, %ymm19 {k1}
+vpconflictq %ymm16, %ymm19 {z}{k1}
+vpconflictq (%rax), %ymm19 {z}{k1}
+vpconflictq (%rax){1to4}, %ymm19 {z}{k1}
+
+vplzcntd %xmm16, %xmm19
+vplzcntd (%rax), %xmm19
+vplzcntd (%rax){1to4}, %xmm19
+vplzcntd %xmm16, %xmm19 {k1}
+vplzcntd (%rax), %xmm19 {k1}
+vplzcntd (%rax){1to4}, %xmm19 {k1}
+vplzcntd %xmm16, %xmm19 {z}{k1}
+vplzcntd (%rax), %xmm19 {z}{k1}
+vplzcntd (%rax){1to4}, %xmm19 {z}{k1}
+
+vplzcntd %ymm16, %ymm19
+vplzcntd (%rax), %ymm19
+vplzcntd (%rax){1to8}, %ymm19
+vplzcntd %ymm16, %ymm19 {k1}
+vplzcntd (%rax), %ymm19 {k1}
+vplzcntd (%rax){1to8}, %ymm19 {k1}
+vplzcntd %ymm16, %ymm19 {z}{k1}
+vplzcntd (%rax), %ymm19 {z}{k1}
+vplzcntd (%rax){1to8}, %ymm19 {z}{k1}
+
+vplzcntq %xmm16, %xmm19
+vplzcntq (%rax), %xmm19
+vplzcntq (%rax){1to2}, %xmm19
+vplzcntq %xmm16, %xmm19 {k1}
+vplzcntq (%rax), %xmm19 {k1}
+vplzcntq (%rax){1to2}, %xmm19 {k1}
+vplzcntq %xmm16, %xmm19 {z}{k1}
+vplzcntq (%rax), %xmm19 {z}{k1}
+vplzcntq (%rax){1to2}, %xmm19 {z}{k1}
+
+vplzcntq %ymm16, %ymm19
+vplzcntq (%rax), %ymm19
+vplzcntq (%rax){1to4}, %ymm19
+vplzcntq %ymm16, %ymm19 {k1}
+vplzcntq (%rax), %ymm19 {k1}
+vplzcntq (%rax){1to4}, %ymm19 {k1}
+vplzcntq %ymm16, %ymm19 {z}{k1}
+vplzcntq (%rax), %ymm19 {z}{k1}
+vplzcntq (%rax){1to4}, %ymm19 {z}{k1}
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.50 vpbroadcastmb2q %k0, %xmm16
+# CHECK-NEXT: 1 1 0.50 vpbroadcastmb2q %k0, %ymm16
+# CHECK-NEXT: 1 1 0.50 vpbroadcastmw2d %k0, %xmm16
+# CHECK-NEXT: 1 1 0.50 vpbroadcastmw2d %k0, %ymm16
+# CHECK-NEXT: 4 2 2.00 vpconflictd %xmm16, %xmm19
+# CHECK-NEXT: 4 9 2.00 * vpconflictd (%rax), %xmm19
+# CHECK-NEXT: 4 9 2.00 * vpconflictd (%rax){1to4}, %xmm19
+# CHECK-NEXT: 4 2 2.00 vpconflictd %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 4 9 2.00 * vpconflictd (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 4 9 2.00 * vpconflictd (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: 4 2 2.00 vpconflictd %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 4 9 2.00 * vpconflictd (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 4 9 2.00 * vpconflictd (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 5 5 3.00 vpconflictd %ymm16, %ymm19
+# CHECK-NEXT: 8 12 3.00 * vpconflictd (%rax), %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpconflictd (%rax){1to8}, %ymm19
+# CHECK-NEXT: 4 3 3.00 vpconflictd %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 4 10 3.00 * vpconflictd (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpconflictd (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: 5 5 3.00 vpconflictd %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 8 12 3.00 * vpconflictd (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpconflictd (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 4 2 2.00 vpconflictq %xmm16, %xmm19
+# CHECK-NEXT: 4 9 2.00 * vpconflictq (%rax), %xmm19
+# CHECK-NEXT: 4 9 2.00 * vpconflictq (%rax){1to2}, %xmm19
+# CHECK-NEXT: 4 2 2.00 vpconflictq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 4 9 2.00 * vpconflictq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 4 9 2.00 * vpconflictq (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: 4 2 2.00 vpconflictq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 4 9 2.00 * vpconflictq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 4 9 2.00 * vpconflictq (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 5 5 3.00 vpconflictq %ymm16, %ymm19
+# CHECK-NEXT: 8 12 3.00 * vpconflictq (%rax), %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpconflictq (%rax){1to4}, %ymm19
+# CHECK-NEXT: 4 3 3.00 vpconflictq %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 4 10 3.00 * vpconflictq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpconflictq (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: 5 5 3.00 vpconflictq %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 8 12 3.00 * vpconflictq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpconflictq (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vplzcntd %xmm16, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vplzcntd (%rax), %xmm19
+# CHECK-NEXT: 1 10 0.50 * vplzcntd (%rax){1to4}, %xmm19
+# CHECK-NEXT: 1 1 0.25 vplzcntd %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vplzcntd (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vplzcntd (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vplzcntd %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vplzcntd (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vplzcntd (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vplzcntd %ymm16, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vplzcntd (%rax), %ymm19
+# CHECK-NEXT: 1 10 0.50 * vplzcntd (%rax){1to8}, %ymm19
+# CHECK-NEXT: 1 1 0.25 vplzcntd %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vplzcntd (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vplzcntd (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vplzcntd %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vplzcntd (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vplzcntd (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vplzcntq %xmm16, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vplzcntq (%rax), %xmm19
+# CHECK-NEXT: 1 10 0.50 * vplzcntq (%rax){1to2}, %xmm19
+# CHECK-NEXT: 1 1 0.25 vplzcntq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vplzcntq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vplzcntq (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vplzcntq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vplzcntq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vplzcntq (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vplzcntq %ymm16, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vplzcntq (%rax), %ymm19
+# CHECK-NEXT: 1 10 0.50 * vplzcntq (%rax){1to4}, %ymm19
+# CHECK-NEXT: 1 1 0.25 vplzcntq %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vplzcntq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vplzcntq (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vplzcntq %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vplzcntq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vplzcntq (%rax){1to4}, %ymm19 {%k1} {z}
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 16.00 16.00 16.00 - - - - - 15.50 79.50 15.50 79.50 12.00 12.00 12.00 12.00 16.00 16.00 16.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpbroadcastmb2q %k0, %xmm16
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpbroadcastmb2q %k0, %ymm16
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpbroadcastmw2d %k0, %xmm16
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpbroadcastmw2d %k0, %ymm16
+# CHECK-NEXT: - - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - vpconflictd %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 2.00 - 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictd (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 2.00 - 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictd (%rax){1to4}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - vpconflictd %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 2.00 - 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictd (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 2.00 - 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictd (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - vpconflictd %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 2.00 - 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictd (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 2.00 - 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictd (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 3.00 - 3.00 - - - - - - - - - - - vpconflictd %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 3.00 - 3.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictd (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictd (%rax){1to8}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 3.00 - 3.00 - - - - - - - - - - - vpconflictd %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 3.00 - 3.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictd (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictd (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 3.00 - 3.00 - - - - - - - - - - - vpconflictd %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 3.00 - 3.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictd (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictd (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - vpconflictq %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 2.00 - 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictq (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 2.00 - 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictq (%rax){1to2}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - vpconflictq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 2.00 - 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 2.00 - 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictq (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - vpconflictq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 2.00 - 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 2.00 - 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictq (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 3.00 - 3.00 - - - - - - - - - - - vpconflictq %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 3.00 - 3.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictq (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictq (%rax){1to4}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 3.00 - 3.00 - - - - - - - - - - - vpconflictq %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 3.00 - 3.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictq (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 3.00 - 3.00 - - - - - - - - - - - vpconflictq %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 3.00 - 3.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpconflictq (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vplzcntd %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntd (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntd (%rax){1to4}, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vplzcntd %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntd (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntd (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vplzcntd %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntd (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntd (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vplzcntd %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntd (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntd (%rax){1to8}, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vplzcntd %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntd (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntd (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vplzcntd %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntd (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntd (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vplzcntq %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntq (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntq (%rax){1to2}, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vplzcntq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntq (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vplzcntq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntq (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vplzcntq %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntq (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntq (%rax){1to4}, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vplzcntq %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntq (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vplzcntq %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vplzcntq (%rax){1to4}, %ymm19 {%k1} {z}
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512dq.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512dq.s
new file mode 100644
index 0000000000000..05f181620aa46
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512dq.s
@@ -0,0 +1,1277 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+kaddb %k0, %k1, %k2
+kaddw %k0, %k1, %k2
+kandb %k0, %k1, %k2
+kandnb %k0, %k1, %k2
+
+kmovb %k0, %k2
+kmovb (%rax), %k2
+kmovb %k0, (%rax)
+kmovb %eax, %k2
+kmovb %k0, %eax
+
+knotb %k0, %k2
+
+korb %k0, %k1, %k2
+
+kortestb %k0, %k2
+
+kshiftlb $2, %k1, %k2
+kshiftrb $2, %k1, %k2
+
+ktestb %k0, %k2
+ktestw %k0, %k2
+
+kxnorb %k0, %k1, %k2
+kxorb %k0, %k1, %k2
+
+vandnpd %zmm16, %zmm17, %zmm19
+vandnpd (%rax), %zmm17, %zmm19
+vandnpd (%rax){1to8}, %zmm17, %zmm19
+vandnpd %zmm16, %zmm17, %zmm19 {k1}
+vandnpd (%rax), %zmm17, %zmm19 {k1}
+vandnpd (%rax){1to8}, %zmm17, %zmm19 {k1}
+vandnpd %zmm16, %zmm17, %zmm19 {z}{k1}
+vandnpd (%rax), %zmm17, %zmm19 {z}{k1}
+vandnpd (%rax){1to8}, %zmm17, %zmm19 {z}{k1}
+
+vandnps %zmm16, %zmm17, %zmm19
+vandnps (%rax), %zmm17, %zmm19
+vandnps (%rax){1to16}, %zmm17, %zmm19
+vandnps %zmm16, %zmm17, %zmm19 {k1}
+vandnps (%rax), %zmm17, %zmm19 {k1}
+vandnps (%rax){1to16}, %zmm17, %zmm19 {k1}
+vandnps %zmm16, %zmm17, %zmm19 {z}{k1}
+vandnps (%rax), %zmm17, %zmm19 {z}{k1}
+vandnps (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
+
+vandpd %zmm16, %zmm17, %zmm19
+vandpd (%rax), %zmm17, %zmm19
+vandpd (%rax){1to8}, %zmm17, %zmm19
+vandpd %zmm16, %zmm17, %zmm19 {k1}
+vandpd (%rax), %zmm17, %zmm19 {k1}
+vandpd (%rax){1to8}, %zmm17, %zmm19 {k1}
+vandpd %zmm16, %zmm17, %zmm19 {z}{k1}
+vandpd (%rax), %zmm17, %zmm19 {z}{k1}
+vandpd (%rax){1to8}, %zmm17, %zmm19 {z}{k1}
+
+vandps %zmm16, %zmm17, %zmm19
+vandps (%rax), %zmm17, %zmm19
+vandps (%rax){1to16}, %zmm17, %zmm19
+vandps %zmm16, %zmm17, %zmm19 {k1}
+vandps (%rax), %zmm17, %zmm19 {k1}
+vandps (%rax){1to16}, %zmm17, %zmm19 {k1}
+vandps %zmm16, %zmm17, %zmm19 {z}{k1}
+vandps (%rax), %zmm17, %zmm19 {z}{k1}
+vandps (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
+
+vbroadcastf32x2 %xmm16, %zmm19
+vbroadcastf32x2 (%rax), %zmm19
+vbroadcastf32x2 %xmm16, %zmm19 {k1}
+vbroadcastf32x2 (%rax), %zmm19 {k1}
+vbroadcastf32x2 %xmm16, %zmm19 {z}{k1}
+vbroadcastf32x2 (%rax), %zmm19 {z}{k1}
+
+vbroadcastf32x8 (%rax), %zmm19
+vbroadcastf32x8 (%rax), %zmm19 {k1}
+vbroadcastf32x8 (%rax), %zmm19 {z}{k1}
+
+vbroadcastf64x2 (%rax), %zmm19
+vbroadcastf64x2 (%rax), %zmm19 {k1}
+vbroadcastf64x2 (%rax), %zmm19 {z}{k1}
+
+vbroadcasti32x2 %xmm16, %zmm19
+vbroadcasti32x2 (%rax), %zmm19
+vbroadcasti32x2 %xmm16, %zmm19 {k1}
+vbroadcasti32x2 (%rax), %zmm19 {k1}
+vbroadcasti32x2 %xmm16, %zmm19 {z}{k1}
+vbroadcasti32x2 (%rax), %zmm19 {z}{k1}
+
+vbroadcasti32x8 (%rax), %zmm19
+vbroadcasti32x8 (%rax), %zmm19 {k1}
+vbroadcasti32x8 (%rax), %zmm19 {z}{k1}
+
+vbroadcasti64x2 (%rax), %zmm19
+vbroadcasti64x2 (%rax), %zmm19 {k1}
+vbroadcasti64x2 (%rax), %zmm19 {z}{k1}
+
+vcvtpd2qq %zmm16, %zmm19
+vcvtpd2qq (%rax), %zmm19
+vcvtpd2qq (%rax){1to8}, %zmm19
+vcvtpd2qq %zmm16, %zmm19 {k1}
+vcvtpd2qq (%rax), %zmm19 {k1}
+vcvtpd2qq (%rax){1to8}, %zmm19 {k1}
+vcvtpd2qq %zmm16, %zmm19 {z}{k1}
+vcvtpd2qq (%rax), %zmm19 {z}{k1}
+vcvtpd2qq (%rax){1to8}, %zmm19 {z}{k1}
+
+vcvtpd2uqq %zmm16, %zmm19
+vcvtpd2uqq (%rax), %zmm19
+vcvtpd2uqq (%rax){1to8}, %zmm19
+vcvtpd2uqq %zmm16, %zmm19 {k1}
+vcvtpd2uqq (%rax), %zmm19 {k1}
+vcvtpd2uqq (%rax){1to8}, %zmm19 {k1}
+vcvtpd2uqq %zmm16, %zmm19 {z}{k1}
+vcvtpd2uqq (%rax), %zmm19 {z}{k1}
+vcvtpd2uqq (%rax){1to8}, %zmm19 {z}{k1}
+
+vcvtps2qq %ymm16, %zmm19
+vcvtps2qq (%rax), %zmm19
+vcvtps2qq (%rax){1to8}, %zmm19
+vcvtps2qq %ymm16, %zmm19 {k1}
+vcvtps2qq (%rax), %zmm19 {k1}
+vcvtps2qq (%rax){1to8}, %zmm19 {k1}
+vcvtps2qq %ymm16, %zmm19 {z}{k1}
+vcvtps2qq (%rax), %zmm19 {z}{k1}
+vcvtps2qq (%rax){1to8}, %zmm19 {z}{k1}
+
+vcvtps2uqq %ymm16, %zmm19
+vcvtps2uqq (%rax), %zmm19
+vcvtps2uqq (%rax){1to8}, %zmm19
+vcvtps2uqq %ymm16, %zmm19 {k1}
+vcvtps2uqq (%rax), %zmm19 {k1}
+vcvtps2uqq (%rax){1to8}, %zmm19 {k1}
+vcvtps2uqq %ymm16, %zmm19 {z}{k1}
+vcvtps2uqq (%rax), %zmm19 {z}{k1}
+vcvtps2uqq (%rax){1to8}, %zmm19 {z}{k1}
+
+vcvtqq2pd %zmm16, %zmm19
+vcvtqq2pd (%rax), %zmm19
+vcvtqq2pd (%rax){1to8}, %zmm19
+vcvtqq2pd %zmm16, %zmm19 {k1}
+vcvtqq2pd (%rax), %zmm19 {k1}
+vcvtqq2pd (%rax){1to8}, %zmm19 {k1}
+vcvtqq2pd %zmm16, %zmm19 {z}{k1}
+vcvtqq2pd (%rax), %zmm19 {z}{k1}
+vcvtqq2pd (%rax){1to8}, %zmm19 {z}{k1}
+
+vcvtqq2ps %zmm16, %ymm19
+vcvtqq2ps (%rax), %ymm19
+vcvtqq2ps (%rax){1to8}, %ymm19
+vcvtqq2ps %zmm16, %ymm19 {k1}
+vcvtqq2ps (%rax), %ymm19 {k1}
+vcvtqq2ps (%rax){1to8}, %ymm19 {k1}
+vcvtqq2ps %zmm16, %ymm19 {z}{k1}
+vcvtqq2ps (%rax), %ymm19 {z}{k1}
+vcvtqq2ps (%rax){1to8}, %ymm19 {z}{k1}
+
+vcvttpd2qq %zmm16, %zmm19
+vcvttpd2qq (%rax), %zmm19
+vcvttpd2qq (%rax){1to8}, %zmm19
+vcvttpd2qq %zmm16, %zmm19 {k1}
+vcvttpd2qq (%rax), %zmm19 {k1}
+vcvttpd2qq (%rax){1to8}, %zmm19 {k1}
+vcvttpd2qq %zmm16, %zmm19 {z}{k1}
+vcvttpd2qq (%rax), %zmm19 {z}{k1}
+vcvttpd2qq (%rax){1to8}, %zmm19 {z}{k1}
+
+vcvttpd2uqq %zmm16, %zmm19
+vcvttpd2uqq (%rax), %zmm19
+vcvttpd2uqq (%rax){1to8}, %zmm19
+vcvttpd2uqq %zmm16, %zmm19 {k1}
+vcvttpd2uqq (%rax), %zmm19 {k1}
+vcvttpd2uqq (%rax){1to8}, %zmm19 {k1}
+vcvttpd2uqq %zmm16, %zmm19 {z}{k1}
+vcvttpd2uqq (%rax), %zmm19 {z}{k1}
+vcvttpd2uqq (%rax){1to8}, %zmm19 {z}{k1}
+
+vcvttps2qq %ymm16, %zmm19
+vcvttps2qq (%rax), %zmm19
+vcvttps2qq (%rax){1to8}, %zmm19
+vcvttps2qq %ymm16, %zmm19 {k1}
+vcvttps2qq (%rax), %zmm19 {k1}
+vcvttps2qq (%rax){1to8}, %zmm19 {k1}
+vcvttps2qq %ymm16, %zmm19 {z}{k1}
+vcvttps2qq (%rax), %zmm19 {z}{k1}
+vcvttps2qq (%rax){1to8}, %zmm19 {z}{k1}
+
+vcvttps2uqq %ymm16, %zmm19
+vcvttps2uqq (%rax), %zmm19
+vcvttps2uqq (%rax){1to8}, %zmm19
+vcvttps2uqq %ymm16, %zmm19 {k1}
+vcvttps2uqq (%rax), %zmm19 {k1}
+vcvttps2uqq (%rax){1to8}, %zmm19 {k1}
+vcvttps2uqq %ymm16, %zmm19 {z}{k1}
+vcvttps2uqq (%rax), %zmm19 {z}{k1}
+vcvttps2uqq (%rax){1to8}, %zmm19 {z}{k1}
+
+vcvtuqq2pd %zmm16, %zmm19
+vcvtuqq2pd (%rax), %zmm19
+vcvtuqq2pd (%rax){1to8}, %zmm19
+vcvtuqq2pd %zmm16, %zmm19 {k1}
+vcvtuqq2pd (%rax), %zmm19 {k1}
+vcvtuqq2pd (%rax){1to8}, %zmm19 {k1}
+vcvtuqq2pd %zmm16, %zmm19 {z}{k1}
+vcvtuqq2pd (%rax), %zmm19 {z}{k1}
+vcvtuqq2pd (%rax){1to8}, %zmm19 {z}{k1}
+
+vcvtuqq2ps %zmm16, %ymm19
+vcvtuqq2ps (%rax), %ymm19
+vcvtuqq2ps (%rax){1to8}, %ymm19
+vcvtuqq2ps %zmm16, %ymm19 {k1}
+vcvtuqq2ps (%rax), %ymm19 {k1}
+vcvtuqq2ps (%rax){1to8}, %ymm19 {k1}
+vcvtuqq2ps %zmm16, %ymm19 {z}{k1}
+vcvtuqq2ps (%rax), %ymm19 {z}{k1}
+vcvtuqq2ps (%rax){1to8}, %ymm19 {z}{k1}
+
+vextractf32x8 $1, %zmm16, %ymm19
+vextractf32x8 $1, %zmm16, (%rax)
+vextractf32x8 $1, %zmm16, %ymm19 {k1}
+vextractf32x8 $1, %zmm16, (%rax) {k1}
+vextractf32x8 $1, %zmm16, %ymm19 {z}{k1}
+
+vextractf64x2 $1, %zmm16, %xmm19
+vextractf64x2 $1, %zmm16, (%rax)
+vextractf64x2 $1, %zmm16, %xmm19 {k1}
+vextractf64x2 $1, %zmm16, (%rax) {k1}
+vextractf64x2 $1, %zmm16, %xmm19 {z}{k1}
+
+vextracti32x8 $1, %zmm16, %ymm19
+vextracti32x8 $1, %zmm16, (%rax)
+vextracti32x8 $1, %zmm16, %ymm19 {k1}
+vextracti32x8 $1, %zmm16, (%rax) {k1}
+vextracti32x8 $1, %zmm16, %ymm19 {z}{k1}
+
+vextracti64x2 $1, %zmm16, %xmm19
+vextracti64x2 $1, %zmm16, (%rax)
+vextracti64x2 $1, %zmm16, %xmm19 {k1}
+vextracti64x2 $1, %zmm16, (%rax) {k1}
+vextracti64x2 $1, %zmm16, %xmm19 {z}{k1}
+
+vfpclasspd $0xab, %zmm16, %k1
+vfpclasspdz $0xab, (%rax), %k1
+vfpclasspdz $0xab, (%rax){1to8}, %k1
+vfpclasspd $0xab, %zmm16, %k1 {k2}
+vfpclasspdz $0xab, (%rax), %k1 {k2}
+vfpclasspdz $0xab, (%rax){1to8}, %k1 {k2}
+
+vfpclassps $0xab, %zmm16, %k1
+vfpclasspsz $0xab, (%rax), %k1
+vfpclasspsz $0xab, (%rax){1to16}, %k1
+vfpclassps $0xab, %zmm16, %k1 {k2}
+vfpclasspsz $0xab, (%rax), %k1 {k2}
+vfpclasspsz $0xab, (%rax){1to16}, %k1 {k2}
+
+vfpclasssd $0xab, %xmm16, %k1
+vfpclasssd $0xab, (%rax), %k1
+vfpclasssd $0xab, %xmm16, %k1 {k2}
+vfpclasssd $0xab, (%rax), %k1 {k2}
+
+vfpclassss $0xab, %xmm16, %k1
+vfpclassss $0xab, (%rax), %k1
+vfpclassss $0xab, %xmm16, %k1 {k2}
+vfpclassss $0xab, (%rax), %k1 {k2}
+
+vinsertf32x8 $1, %ymm16, %zmm16, %zmm19
+vinsertf32x8 $1, (%rax), %zmm16, %zmm19
+vinsertf32x8 $1, %ymm16, %zmm16, %zmm19 {k1}
+vinsertf32x8 $1, (%rax), %zmm16, %zmm19 {k1}
+vinsertf32x8 $1, %ymm16, %zmm16, %zmm19 {z}{k1}
+vinsertf32x8 $1, (%rax), %zmm16, %zmm19 {z}{k1}
+
+vinsertf64x2 $1, %xmm16, %zmm16, %zmm19
+vinsertf64x2 $1, (%rax), %zmm16, %zmm19
+vinsertf64x2 $1, %xmm16, %zmm16, %zmm19 {k1}
+vinsertf64x2 $1, (%rax), %zmm16, %zmm19 {k1}
+vinsertf64x2 $1, %xmm16, %zmm16, %zmm19 {z}{k1}
+vinsertf64x2 $1, (%rax), %zmm16, %zmm19 {z}{k1}
+
+vinserti32x8 $1, %ymm16, %zmm16, %zmm19
+vinserti32x8 $1, (%rax), %zmm16, %zmm19
+vinserti32x8 $1, %ymm16, %zmm16, %zmm19 {k1}
+vinserti32x8 $1, (%rax), %zmm16, %zmm19 {k1}
+vinserti32x8 $1, %ymm16, %zmm16, %zmm19 {z}{k1}
+vinserti32x8 $1, (%rax), %zmm16, %zmm19 {z}{k1}
+
+vinserti64x2 $1, %xmm16, %zmm16, %zmm19
+vinserti64x2 $1, (%rax), %zmm16, %zmm19
+vinserti64x2 $1, %xmm16, %zmm16, %zmm19 {k1}
+vinserti64x2 $1, (%rax), %zmm16, %zmm19 {k1}
+vinserti64x2 $1, %xmm16, %zmm16, %zmm19 {z}{k1}
+vinserti64x2 $1, (%rax), %zmm16, %zmm19 {z}{k1}
+
+vorpd %zmm16, %zmm17, %zmm19
+vorpd (%rax), %zmm17, %zmm19
+vorpd (%rax){1to8}, %zmm17, %zmm19
+vorpd %zmm16, %zmm17, %zmm19 {k1}
+vorpd (%rax), %zmm17, %zmm19 {k1}
+vorpd (%rax){1to8}, %zmm17, %zmm19 {k1}
+vorpd %zmm16, %zmm17, %zmm19 {z}{k1}
+vorpd (%rax), %zmm17, %zmm19 {z}{k1}
+vorpd (%rax){1to8}, %zmm17, %zmm19 {z}{k1}
+
+vorps %zmm16, %zmm17, %zmm19
+vorps (%rax), %zmm17, %zmm19
+vorps (%rax){1to16}, %zmm17, %zmm19
+vorps %zmm16, %zmm17, %zmm19 {k1}
+vorps (%rax), %zmm17, %zmm19 {k1}
+vorps (%rax){1to16}, %zmm17, %zmm19 {k1}
+vorps %zmm16, %zmm17, %zmm19 {z}{k1}
+vorps (%rax), %zmm17, %zmm19 {z}{k1}
+vorps (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
+
+vpextrd $1, %xmm16, %ecx
+vpextrd $1, %xmm16, (%rax)
+
+vpextrq $1, %xmm16, %rcx
+vpextrq $1, %xmm16, (%rax)
+
+vpinsrd $1, %ecx, %xmm16, %xmm19
+vpinsrd $1, (%rax), %xmm16, %xmm19
+
+vpinsrq $1, %rcx, %xmm16, %xmm19
+vpinsrq $1, (%rax), %xmm16, %xmm19
+
+vpmovm2d %k0, %zmm0
+vpmovm2q %k0, %zmm0
+
+vpmovd2m %zmm0, %k0
+vpmovq2m %zmm0, %k0
+
+vpmullq %zmm16, %zmm17, %zmm19
+vpmullq (%rax), %zmm17, %zmm19
+vpmullq %zmm16, %zmm17, %zmm19 {k1}
+vpmullq (%rax), %zmm17, %zmm19 {k1}
+vpmullq %zmm16, %zmm17, %zmm19 {z}{k1}
+vpmullq (%rax), %zmm17, %zmm19 {z}{k1}
+
+vrangepd $ab, %zmm16, %zmm17, %zmm19
+vrangepd $ab, (%rax), %zmm17, %zmm19
+vrangepd $ab, (%rax){1to8}, %zmm17, %zmm19
+vrangepd $ab, %zmm16, %zmm17, %zmm19 {k1}
+vrangepd $ab, (%rax), %zmm17, %zmm19 {k1}
+vrangepd $ab, (%rax){1to8}, %zmm17, %zmm19 {k1}
+vrangepd $ab, %zmm16, %zmm17, %zmm19 {z}{k1}
+vrangepd $ab, (%rax), %zmm17, %zmm19 {z}{k1}
+vrangepd $ab, (%rax){1to8}, %zmm17, %zmm19 {z}{k1}
+
+vrangepd $ab, {sae}, %zmm16, %zmm17, %zmm19
+vrangepd $ab, {sae}, %zmm16, %zmm17, %zmm19 {k1}
+vrangepd $ab, {sae}, %zmm16, %zmm17, %zmm19 {z}{k1}
+
+vrangeps $ab, %zmm16, %zmm17, %zmm19
+vrangeps $ab, (%rax), %zmm17, %zmm19
+vrangeps $ab, (%rax){1to16}, %zmm17, %zmm19
+vrangeps $ab, %zmm16, %zmm17, %zmm19 {k1}
+vrangeps $ab, (%rax), %zmm17, %zmm19 {k1}
+vrangeps $ab, (%rax){1to16}, %zmm17, %zmm19 {k1}
+vrangeps $ab, %zmm16, %zmm17, %zmm19 {z}{k1}
+vrangeps $ab, (%rax), %zmm17, %zmm19 {z}{k1}
+vrangeps $ab, (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
+
+vrangeps $ab, {sae}, %zmm16, %zmm17, %zmm19
+vrangeps $ab, {sae}, %zmm16, %zmm17, %zmm19 {k1}
+vrangeps $ab, {sae}, %zmm16, %zmm17, %zmm19 {z}{k1}
+
+vrangesd $ab, %xmm16, %xmm17, %xmm19
+vrangesd $ab, (%rax), %xmm17, %xmm19
+vrangesd $ab, %xmm16, %xmm17, %xmm19 {k1}
+vrangesd $ab, (%rax), %xmm17, %xmm19 {k1}
+vrangesd $ab, %xmm16, %xmm17, %xmm19 {z}{k1}
+vrangesd $ab, (%rax), %xmm17, %xmm19 {z}{k1}
+
+vrangesd $ab, {sae}, %xmm16, %xmm17, %xmm19
+vrangesd $ab, {sae}, %xmm16, %xmm17, %xmm19 {k1}
+vrangesd $ab, {sae}, %xmm16, %xmm17, %xmm19 {z}{k1}
+
+vrangess $ab, %xmm16, %xmm17, %xmm19
+vrangess $ab, (%rax), %xmm17, %xmm19
+vrangess $ab, %xmm16, %xmm17, %xmm19 {k1}
+vrangess $ab, (%rax), %xmm17, %xmm19 {k1}
+vrangess $ab, %xmm16, %xmm17, %xmm19 {z}{k1}
+vrangess $ab, (%rax), %xmm17, %xmm19 {z}{k1}
+
+vrangess $ab, {sae}, %xmm16, %xmm17, %xmm19
+vrangess $ab, {sae}, %xmm16, %xmm17, %xmm19 {k1}
+vrangess $ab, {sae}, %xmm16, %xmm17, %xmm19 {z}{k1}
+
+vreducepd $ab, %zmm16, %zmm19
+vreducepd $ab, (%rax), %zmm19
+vreducepd $ab, (%rax){1to8}, %zmm19
+vreducepd $ab, %zmm16, %zmm19 {k1}
+vreducepd $ab, (%rax), %zmm19 {k1}
+vreducepd $ab, (%rax){1to8}, %zmm19 {k1}
+vreducepd $ab, %zmm16, %zmm19 {z}{k1}
+vreducepd $ab, (%rax), %zmm19 {z}{k1}
+vreducepd $ab, (%rax){1to8}, %zmm19 {z}{k1}
+
+vreducepd $ab, {sae}, %zmm16, %zmm19
+vreducepd $ab, {sae}, %zmm16, %zmm19 {k1}
+vreducepd $ab, {sae}, %zmm16, %zmm19 {z}{k1}
+
+vreduceps $ab, %zmm16, %zmm19
+vreduceps $ab, (%rax), %zmm19
+vreduceps $ab, (%rax){1to16}, %zmm19
+vreduceps $ab, %zmm16, %zmm19 {k1}
+vreduceps $ab, (%rax), %zmm19 {k1}
+vreduceps $ab, (%rax){1to16}, %zmm19 {k1}
+vreduceps $ab, %zmm16, %zmm19 {z}{k1}
+vreduceps $ab, (%rax), %zmm19 {z}{k1}
+vreduceps $ab, (%rax){1to16}, %zmm19 {z}{k1}
+
+vreduceps $ab, {sae}, %zmm16, %zmm19
+vreduceps $ab, {sae}, %zmm16, %zmm19 {k1}
+vreduceps $ab, {sae}, %zmm16, %zmm19 {z}{k1}
+
+vreducesd $ab, %xmm16, %xmm17, %xmm19
+vreducesd $ab, (%rax), %xmm17, %xmm19
+vreducesd $ab, %xmm16, %xmm17, %xmm19 {k1}
+vreducesd $ab, (%rax), %xmm17, %xmm19 {k1}
+vreducesd $ab, %xmm16, %xmm17, %xmm19 {z}{k1}
+vreducesd $ab, (%rax), %xmm17, %xmm19 {z}{k1}
+
+vreducesd $ab, {sae}, %xmm16, %xmm17, %xmm19
+vreducesd $ab, {sae}, %xmm16, %xmm17, %xmm19 {k1}
+vreducesd $ab, {sae}, %xmm16, %xmm17, %xmm19 {z}{k1}
+
+vreducess $ab, %xmm16, %xmm17, %xmm19
+vreducess $ab, (%rax), %xmm17, %xmm19
+vreducess $ab, %xmm16, %xmm17, %xmm19 {k1}
+vreducess $ab, (%rax), %xmm17, %xmm19 {k1}
+vreducess $ab, %xmm16, %xmm17, %xmm19 {z}{k1}
+vreducess $ab, (%rax), %xmm17, %xmm19 {z}{k1}
+
+vreducess $ab, {sae}, %xmm16, %xmm17, %xmm19
+vreducess $ab, {sae}, %xmm16, %xmm17, %xmm19 {k1}
+vreducess $ab, {sae}, %xmm16, %xmm17, %xmm19 {z}{k1}
+
+vxorpd %zmm16, %zmm17, %zmm19
+vxorpd (%rax), %zmm17, %zmm19
+vxorpd (%rax){1to8}, %zmm17, %zmm19
+vxorpd %zmm16, %zmm17, %zmm19 {k1}
+vxorpd (%rax), %zmm17, %zmm19 {k1}
+vxorpd (%rax){1to8}, %zmm17, %zmm19 {k1}
+vxorpd %zmm16, %zmm17, %zmm19 {z}{k1}
+vxorpd (%rax), %zmm17, %zmm19 {z}{k1}
+vxorpd (%rax){1to8}, %zmm17, %zmm19 {z}{k1}
+
+vxorps %zmm16, %zmm17, %zmm19
+vxorps (%rax), %zmm17, %zmm19
+vxorps (%rax){1to16}, %zmm17, %zmm19
+vxorps %zmm16, %zmm17, %zmm19 {k1}
+vxorps (%rax), %zmm17, %zmm19 {k1}
+vxorps (%rax){1to16}, %zmm17, %zmm19 {k1}
+vxorps %zmm16, %zmm17, %zmm19 {z}{k1}
+vxorps (%rax), %zmm17, %zmm19 {z}{k1}
+vxorps (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.25 kaddb %k0, %k1, %k2
+# CHECK-NEXT: 1 1 0.25 kaddw %k0, %k1, %k2
+# CHECK-NEXT: 1 1 0.25 kandb %k0, %k1, %k2
+# CHECK-NEXT: 1 1 0.25 kandnb %k0, %k1, %k2
+# CHECK-NEXT: 1 1 1.00 kmovb %k0, %k2
+# CHECK-NEXT: 1 5 0.33 * kmovb (%rax), %k2
+# CHECK-NEXT: 1 1 0.50 * kmovb %k0, (%rax)
+# CHECK-NEXT: 1 1 1.00 kmovb %eax, %k2
+# CHECK-NEXT: 1 1 1.00 kmovb %k0, %eax
+# CHECK-NEXT: 1 1 0.25 knotb %k0, %k2
+# CHECK-NEXT: 1 1 0.25 korb %k0, %k1, %k2
+# CHECK-NEXT: 1 1 0.25 kortestb %k0, %k2
+# CHECK-NEXT: 1 1 0.50 kshiftlb $2, %k1, %k2
+# CHECK-NEXT: 1 1 0.50 kshiftrb $2, %k1, %k2
+# CHECK-NEXT: 1 1 0.25 ktestb %k0, %k2
+# CHECK-NEXT: 1 1 0.25 ktestw %k0, %k2
+# CHECK-NEXT: 1 1 0.25 kxnorb %k0, %k1, %k2
+# CHECK-NEXT: 1 1 0.25 kxorb %k0, %k1, %k2
+# CHECK-NEXT: 1 1 0.25 vandnpd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.33 * vandnpd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.33 * vandnpd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 2 2 0.50 vandnpd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 9 0.50 * vandnpd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vandnpd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vandnpd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vandnpd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vandnpd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vandnps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.33 * vandnps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.33 * vandnps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 2 2 0.50 vandnps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 9 0.50 * vandnps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vandnps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vandnps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vandnps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vandnps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vandpd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.33 * vandpd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.33 * vandpd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 2 2 0.50 vandpd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 9 0.50 * vandpd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vandpd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vandpd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vandpd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vandpd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vandps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.33 * vandps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.33 * vandps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 2 2 0.50 vandps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 9 0.50 * vandps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vandps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vandps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vandps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vandps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 5 4.00 vbroadcastf32x2 %xmm16, %zmm19
+# CHECK-NEXT: 2 12 4.00 * vbroadcastf32x2 (%rax), %zmm19
+# CHECK-NEXT: 2 4 4.00 vbroadcastf32x2 %xmm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 11 4.00 * vbroadcastf32x2 (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 2 5 4.00 vbroadcastf32x2 %xmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 12 4.00 * vbroadcastf32x2 (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vbroadcastf32x8 (%rax), %zmm19
+# CHECK-NEXT: 1 8 0.50 * vbroadcastf32x8 (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vbroadcastf32x8 (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vbroadcastf64x2 (%rax), %zmm19
+# CHECK-NEXT: 1 8 0.50 * vbroadcastf64x2 (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vbroadcastf64x2 (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 5 4.00 vbroadcasti32x2 %xmm16, %zmm19
+# CHECK-NEXT: 2 12 4.00 * vbroadcasti32x2 (%rax), %zmm19
+# CHECK-NEXT: 2 4 4.00 vbroadcasti32x2 %xmm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 11 4.00 * vbroadcasti32x2 (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 2 5 4.00 vbroadcasti32x2 %xmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 12 4.00 * vbroadcasti32x2 (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vbroadcasti32x8 (%rax), %zmm19
+# CHECK-NEXT: 1 8 0.50 * vbroadcasti32x8 (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vbroadcasti32x8 (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vbroadcasti64x2 (%rax), %zmm19
+# CHECK-NEXT: 1 8 0.50 * vbroadcasti64x2 (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vbroadcasti64x2 (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 4 1.00 vcvtpd2qq %zmm16, %zmm19
+# CHECK-NEXT: 2 11 1.00 * vcvtpd2qq (%rax), %zmm19
+# CHECK-NEXT: 2 11 1.00 * vcvtpd2qq (%rax){1to8}, %zmm19
+# CHECK-NEXT: 2 5 1.00 vcvtpd2qq %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtpd2qq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtpd2qq (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: 2 4 1.00 vcvtpd2qq %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vcvtpd2qq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vcvtpd2qq (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 4 1.00 vcvtpd2uqq %zmm16, %zmm19
+# CHECK-NEXT: 2 11 1.00 * vcvtpd2uqq (%rax), %zmm19
+# CHECK-NEXT: 2 11 1.00 * vcvtpd2uqq (%rax){1to8}, %zmm19
+# CHECK-NEXT: 2 5 1.00 vcvtpd2uqq %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtpd2uqq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtpd2uqq (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: 2 4 1.00 vcvtpd2uqq %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vcvtpd2uqq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vcvtpd2uqq (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 5 1.00 vcvtps2qq %ymm16, %zmm19
+# CHECK-NEXT: 2 12 1.00 * vcvtps2qq (%rax), %zmm19
+# CHECK-NEXT: 2 12 1.00 * vcvtps2qq (%rax){1to8}, %zmm19
+# CHECK-NEXT: 2 5 1.00 vcvtps2qq %ymm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtps2qq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtps2qq (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: 2 5 1.00 vcvtps2qq %ymm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 12 1.00 * vcvtps2qq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 12 1.00 * vcvtps2qq (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 5 1.00 vcvtps2uqq %ymm16, %zmm19
+# CHECK-NEXT: 2 12 1.00 * vcvtps2uqq (%rax), %zmm19
+# CHECK-NEXT: 2 12 1.00 * vcvtps2uqq (%rax){1to8}, %zmm19
+# CHECK-NEXT: 2 5 1.00 vcvtps2uqq %ymm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtps2uqq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtps2uqq (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: 2 5 1.00 vcvtps2uqq %ymm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 12 1.00 * vcvtps2uqq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 12 1.00 * vcvtps2uqq (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 4 1.00 vcvtqq2pd %zmm16, %zmm19
+# CHECK-NEXT: 2 11 1.00 * vcvtqq2pd (%rax), %zmm19
+# CHECK-NEXT: 2 11 1.00 * vcvtqq2pd (%rax){1to8}, %zmm19
+# CHECK-NEXT: 2 5 1.00 vcvtqq2pd %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtqq2pd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtqq2pd (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: 2 4 1.00 vcvtqq2pd %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vcvtqq2pd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vcvtqq2pd (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 8 1.00 vcvtqq2ps %zmm16, %ymm19
+# CHECK-NEXT: 2 15 1.00 * vcvtqq2ps (%rax), %ymm19
+# CHECK-NEXT: 2 15 1.00 * vcvtqq2ps (%rax){1to8}, %ymm19
+# CHECK-NEXT: 2 5 1.00 vcvtqq2ps %zmm16, %ymm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtqq2ps (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtqq2ps (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: 2 8 1.00 vcvtqq2ps %zmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 15 1.00 * vcvtqq2ps (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 15 1.00 * vcvtqq2ps (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 4 1.00 vcvttpd2qq %zmm16, %zmm19
+# CHECK-NEXT: 2 11 1.00 * vcvttpd2qq (%rax), %zmm19
+# CHECK-NEXT: 2 11 1.00 * vcvttpd2qq (%rax){1to8}, %zmm19
+# CHECK-NEXT: 2 5 1.00 vcvttpd2qq %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvttpd2qq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvttpd2qq (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: 2 4 1.00 vcvttpd2qq %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vcvttpd2qq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vcvttpd2qq (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 4 1.00 vcvttpd2uqq %zmm16, %zmm19
+# CHECK-NEXT: 2 11 1.00 * vcvttpd2uqq (%rax), %zmm19
+# CHECK-NEXT: 2 11 1.00 * vcvttpd2uqq (%rax){1to8}, %zmm19
+# CHECK-NEXT: 2 5 1.00 vcvttpd2uqq %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvttpd2uqq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvttpd2uqq (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: 2 4 1.00 vcvttpd2uqq %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vcvttpd2uqq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vcvttpd2uqq (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 5 1.00 vcvttps2qq %ymm16, %zmm19
+# CHECK-NEXT: 2 12 1.00 * vcvttps2qq (%rax), %zmm19
+# CHECK-NEXT: 2 12 1.00 * vcvttps2qq (%rax){1to8}, %zmm19
+# CHECK-NEXT: 2 5 1.00 vcvttps2qq %ymm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvttps2qq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvttps2qq (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: 2 5 1.00 vcvttps2qq %ymm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 12 1.00 * vcvttps2qq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 12 1.00 * vcvttps2qq (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 5 1.00 vcvttps2uqq %ymm16, %zmm19
+# CHECK-NEXT: 2 12 1.00 * vcvttps2uqq (%rax), %zmm19
+# CHECK-NEXT: 2 12 1.00 * vcvttps2uqq (%rax){1to8}, %zmm19
+# CHECK-NEXT: 2 5 1.00 vcvttps2uqq %ymm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvttps2uqq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvttps2uqq (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: 2 5 1.00 vcvttps2uqq %ymm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 12 1.00 * vcvttps2uqq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 12 1.00 * vcvttps2uqq (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 4 1.00 vcvtuqq2pd %zmm16, %zmm19
+# CHECK-NEXT: 2 11 1.00 * vcvtuqq2pd (%rax), %zmm19
+# CHECK-NEXT: 2 11 1.00 * vcvtuqq2pd (%rax){1to8}, %zmm19
+# CHECK-NEXT: 2 5 1.00 vcvtuqq2pd %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtuqq2pd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtuqq2pd (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: 2 4 1.00 vcvtuqq2pd %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vcvtuqq2pd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vcvtuqq2pd (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 8 1.00 vcvtuqq2ps %zmm16, %ymm19
+# CHECK-NEXT: 2 15 1.00 * vcvtuqq2ps (%rax), %ymm19
+# CHECK-NEXT: 2 15 1.00 * vcvtuqq2ps (%rax){1to8}, %ymm19
+# CHECK-NEXT: 2 5 1.00 vcvtuqq2ps %zmm16, %ymm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtuqq2ps (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtuqq2ps (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: 2 8 1.00 vcvtuqq2ps %zmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 15 1.00 * vcvtuqq2ps (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 15 1.00 * vcvtuqq2ps (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 1 0.50 vextractf32x8 $1, %zmm16, %ymm19
+# CHECK-NEXT: 2 2 0.50 vextractf32x8 $1, %zmm16, (%rax)
+# CHECK-NEXT: 2 2 0.50 vextractf32x8 $1, %zmm16, %ymm19 {%k1}
+# CHECK-NEXT: 2 3 0.50 * vextractf32x8 $1, %zmm16, (%rax) {%k1}
+# CHECK-NEXT: 2 1 0.50 vextractf32x8 $1, %zmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vextractf64x2 $1, %zmm16, %xmm19
+# CHECK-NEXT: 1 1 0.33 vextractf64x2 $1, %zmm16, (%rax)
+# CHECK-NEXT: 1 4 2.00 vextractf64x2 $1, %zmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 5 2.00 * vextractf64x2 $1, %zmm16, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vextractf64x2 $1, %zmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 2 1 0.50 vextracti32x8 $1, %zmm16, %ymm19
+# CHECK-NEXT: 2 2 0.50 vextracti32x8 $1, %zmm16, (%rax)
+# CHECK-NEXT: 2 2 0.50 vextracti32x8 $1, %zmm16, %ymm19 {%k1}
+# CHECK-NEXT: 2 3 0.50 * vextracti32x8 $1, %zmm16, (%rax) {%k1}
+# CHECK-NEXT: 2 1 0.50 vextracti32x8 $1, %zmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vextracti64x2 $1, %zmm16, %xmm19
+# CHECK-NEXT: 1 1 0.33 vextracti64x2 $1, %zmm16, (%rax)
+# CHECK-NEXT: 1 4 2.00 vextracti64x2 $1, %zmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 5 2.00 * vextracti64x2 $1, %zmm16, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vextracti64x2 $1, %zmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vfpclasspd $171, %zmm16, %k1
+# CHECK-NEXT: 1 8 0.50 * vfpclasspdz $171, (%rax), %k1
+# CHECK-NEXT: 1 8 0.50 * vfpclasspd $171, (%rax){1to8}, %k1
+# CHECK-NEXT: 4 4 4.00 vfpclasspd $171, %zmm16, %k1 {%k2}
+# CHECK-NEXT: 4 11 4.00 * vfpclasspdz $171, (%rax), %k1 {%k2}
+# CHECK-NEXT: 1 8 0.50 * vfpclasspd $171, (%rax){1to8}, %k1 {%k2}
+# CHECK-NEXT: 1 1 0.50 vfpclassps $171, %zmm16, %k1
+# CHECK-NEXT: 1 8 0.50 * vfpclasspsz $171, (%rax), %k1
+# CHECK-NEXT: 1 8 0.50 * vfpclassps $171, (%rax){1to16}, %k1
+# CHECK-NEXT: 4 4 4.00 vfpclassps $171, %zmm16, %k1 {%k2}
+# CHECK-NEXT: 4 11 4.00 * vfpclasspsz $171, (%rax), %k1 {%k2}
+# CHECK-NEXT: 1 8 0.50 * vfpclassps $171, (%rax){1to16}, %k1 {%k2}
+# CHECK-NEXT: 1 1 0.50 vfpclasssd $171, %xmm16, %k1
+# CHECK-NEXT: 1 8 0.50 * vfpclasssd $171, (%rax), %k1
+# CHECK-NEXT: 4 5 4.00 vfpclasssd $171, %xmm16, %k1 {%k2}
+# CHECK-NEXT: 4 12 4.00 * vfpclasssd $171, (%rax), %k1 {%k2}
+# CHECK-NEXT: 1 1 0.50 vfpclassss $171, %xmm16, %k1
+# CHECK-NEXT: 1 8 0.50 * vfpclassss $171, (%rax), %k1
+# CHECK-NEXT: 4 5 4.00 vfpclassss $171, %xmm16, %k1 {%k2}
+# CHECK-NEXT: 4 12 4.00 * vfpclassss $171, (%rax), %k1 {%k2}
+# CHECK-NEXT: 2 2 1.00 vinsertf32x8 $1, %ymm16, %zmm16, %zmm19
+# CHECK-NEXT: 2 9 1.00 * vinsertf32x8 $1, (%rax), %zmm16, %zmm19
+# CHECK-NEXT: 2 2 1.00 vinsertf32x8 $1, %ymm16, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 9 1.00 * vinsertf32x8 $1, (%rax), %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 2 1.00 vinsertf32x8 $1, %ymm16, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 9 1.00 * vinsertf32x8 $1, (%rax), %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 5 8.00 vinsertf64x2 $1, %xmm16, %zmm16, %zmm19
+# CHECK-NEXT: 2 12 8.00 * vinsertf64x2 $1, (%rax), %zmm16, %zmm19
+# CHECK-NEXT: 2 4 8.00 vinsertf64x2 $1, %xmm16, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 11 8.00 * vinsertf64x2 $1, (%rax), %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 4 8.00 vinsertf64x2 $1, %xmm16, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 8.00 * vinsertf64x2 $1, (%rax), %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 2 1.00 vinserti32x8 $1, %ymm16, %zmm16, %zmm19
+# CHECK-NEXT: 2 9 1.00 * vinserti32x8 $1, (%rax), %zmm16, %zmm19
+# CHECK-NEXT: 2 2 1.00 vinserti32x8 $1, %ymm16, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 9 1.00 * vinserti32x8 $1, (%rax), %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 2 1.00 vinserti32x8 $1, %ymm16, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 9 1.00 * vinserti32x8 $1, (%rax), %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 5 8.00 vinserti64x2 $1, %xmm16, %zmm16, %zmm19
+# CHECK-NEXT: 2 12 8.00 * vinserti64x2 $1, (%rax), %zmm16, %zmm19
+# CHECK-NEXT: 2 4 8.00 vinserti64x2 $1, %xmm16, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 11 8.00 * vinserti64x2 $1, (%rax), %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 4 8.00 vinserti64x2 $1, %xmm16, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 8.00 * vinserti64x2 $1, (%rax), %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vorpd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.33 * vorpd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.33 * vorpd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 2 2 0.50 vorpd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 9 0.50 * vorpd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vorpd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vorpd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vorpd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vorpd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vorps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.33 * vorps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.33 * vorps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 2 2 0.50 vorps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 9 0.50 * vorps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vorps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vorps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vorps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vorps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 2.00 vpextrd $1, %xmm16, %ecx
+# CHECK-NEXT: 1 3 2.00 * vpextrd $1, %xmm16, (%rax)
+# CHECK-NEXT: 1 1 2.00 vpextrq $1, %xmm16, %rcx
+# CHECK-NEXT: 1 3 2.00 * vpextrq $1, %xmm16, (%rax)
+# CHECK-NEXT: 1 2 0.50 vpinsrd $1, %ecx, %xmm16, %xmm19
+# CHECK-NEXT: 1 9 0.50 * vpinsrd $1, (%rax), %xmm16, %xmm19
+# CHECK-NEXT: 1 2 0.50 vpinsrq $1, %rcx, %xmm16, %xmm19
+# CHECK-NEXT: 1 9 0.50 * vpinsrq $1, (%rax), %xmm16, %xmm19
+# CHECK-NEXT: 1 0 0.25 vpmovm2d %k0, %zmm0
+# CHECK-NEXT: 1 0 0.25 vpmovm2q %k0, %zmm0
+# CHECK-NEXT: 1 1 1.00 vpmovd2m %zmm0, %k0
+# CHECK-NEXT: 1 1 1.00 vpmovq2m %zmm0, %k0
+# CHECK-NEXT: 1 4 1.00 vpmullq %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 11 1.00 * vpmullq (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 5 1.00 vpmullq %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 12 1.00 * vpmullq (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 4 1.00 vpmullq %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 1.00 * vpmullq (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 1.00 vrangepd $ab, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vrangepd $ab, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vrangepd $ab, (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 1 2 1.00 vrangepd $ab, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vrangepd $ab, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 1.00 * vrangepd $ab, (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 1.00 vrangepd $ab, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 1.00 * vrangepd $ab, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vrangepd $ab, (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 1.00 vrangepd $ab, {sae}, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 2 1.00 vrangepd $ab, {sae}, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 1.00 vrangepd $ab, {sae}, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 1.00 vrangeps $ab, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 1.00 * vrangeps $ab, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vrangeps $ab, (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 1 2 1.00 vrangeps $ab, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vrangeps $ab, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 1.00 * vrangeps $ab, (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 1.00 vrangeps $ab, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 1.00 * vrangeps $ab, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vrangeps $ab, (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 1.00 vrangeps $ab, {sae}, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 2 1.00 vrangeps $ab, {sae}, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 1.00 vrangeps $ab, {sae}, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vrangesd $ab, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vrangesd $ab, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vrangesd $ab, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vrangesd $ab, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vrangesd $ab, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vrangesd $ab, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vrangesd $ab, {sae}, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vrangesd $ab, {sae}, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vrangesd $ab, {sae}, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vrangess $ab, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vrangess $ab, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vrangess $ab, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vrangess $ab, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vrangess $ab, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vrangess $ab, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vrangess $ab, {sae}, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vrangess $ab, {sae}, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vrangess $ab, {sae}, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 2 4 1.00 vreducepd $ab, %zmm16, %zmm19
+# CHECK-NEXT: 2 11 1.00 * vreducepd $ab, (%rax), %zmm19
+# CHECK-NEXT: 2 11 1.00 * vreducepd $ab, (%rax){1to8}, %zmm19
+# CHECK-NEXT: 1 5 1.00 vreducepd $ab, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 12 1.00 * vreducepd $ab, (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 2 11 1.00 * vreducepd $ab, (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: 2 4 1.00 vreducepd $ab, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vreducepd $ab, (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vreducepd $ab, (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 4 1.00 vreducepd $ab, {sae}, %zmm16, %zmm19
+# CHECK-NEXT: 1 5 1.00 vreducepd $ab, {sae}, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 4 1.00 vreducepd $ab, {sae}, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 4 1.00 vreduceps $ab, %zmm16, %zmm19
+# CHECK-NEXT: 2 11 1.00 * vreduceps $ab, (%rax), %zmm19
+# CHECK-NEXT: 2 11 1.00 * vreduceps $ab, (%rax){1to16}, %zmm19
+# CHECK-NEXT: 1 5 1.00 vreduceps $ab, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 1 12 1.00 * vreduceps $ab, (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 2 11 1.00 * vreduceps $ab, (%rax){1to16}, %zmm19 {%k1}
+# CHECK-NEXT: 2 4 1.00 vreduceps $ab, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vreduceps $ab, (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vreduceps $ab, (%rax){1to16}, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 4 1.00 vreduceps $ab, {sae}, %zmm16, %zmm19
+# CHECK-NEXT: 1 5 1.00 vreduceps $ab, {sae}, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 2 4 1.00 vreduceps $ab, {sae}, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vreducesd $ab, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vreducesd $ab, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 5 1.00 vreducesd $ab, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 12 1.00 * vreducesd $ab, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vreducesd $ab, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vreducesd $ab, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vreducesd $ab, {sae}, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 5 1.00 vreducesd $ab, {sae}, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vreducesd $ab, {sae}, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vreducess $ab, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vreducess $ab, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 5 1.00 vreducess $ab, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 12 1.00 * vreducess $ab, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vreducess $ab, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vreducess $ab, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vreducess $ab, {sae}, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 5 1.00 vreducess $ab, {sae}, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vreducess $ab, {sae}, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vxorpd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.33 * vxorpd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.33 * vxorpd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 2 2 0.50 vxorpd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 9 0.50 * vxorpd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vxorpd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vxorpd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vxorpd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vxorpd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vxorps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.33 * vxorps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.33 * vxorps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 2 2 0.50 vxorps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 9 0.50 * vxorps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vxorps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vxorps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vxorps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vxorps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 71.67 71.67 71.67 5.00 5.00 5.00 5.00 - 225.75 233.75 224.75 232.75 54.00 54.00 54.00 54.00 68.00 68.00 68.00 3.00 3.00 3.00 3.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - kaddb %k0, %k1, %k2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - kaddw %k0, %k1, %k2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - kandb %k0, %k1, %k2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - kandnb %k0, %k1, %k2
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - kmovb %k0, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - kmovb (%rax), %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 kmovb %k0, (%rax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - kmovb %eax, %k2
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - kmovb %k0, %eax
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - knotb %k0, %k2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - korb %k0, %k1, %k2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - kortestb %k0, %k2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - kshiftlb $2, %k1, %k2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - kshiftrb $2, %k1, %k2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - ktestb %k0, %k2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - ktestw %k0, %k2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - kxnorb %k0, %k1, %k2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - kxorb %k0, %k1, %k2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandnpd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnpd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnpd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vandnpd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnpd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnpd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandnpd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnpd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnpd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandnps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vandnps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandnps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandpd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandpd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandpd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vandpd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandpd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandpd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandpd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandpd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandpd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vandps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vbroadcastf32x2 %xmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastf32x2 (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vbroadcastf32x2 %xmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastf32x2 (%rax), %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vbroadcastf32x2 %xmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastf32x2 (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastf32x8 (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastf32x8 (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastf32x8 (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastf64x2 (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastf64x2 (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastf64x2 (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vbroadcasti32x2 %xmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcasti32x2 (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vbroadcasti32x2 %xmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcasti32x2 (%rax), %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vbroadcasti32x2 %xmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcasti32x2 (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcasti32x8 (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcasti32x8 (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcasti32x8 (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcasti64x2 (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcasti64x2 (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcasti64x2 (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2qq %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2qq (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2qq (%rax){1to8}, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2qq %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2qq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2qq (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2qq %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2qq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2qq (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2uqq %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2uqq (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2uqq (%rax){1to8}, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2uqq %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2uqq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2uqq (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2uqq %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2uqq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2uqq (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtps2qq %ymm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2qq (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2qq (%rax){1to8}, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtps2qq %ymm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2qq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2qq (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtps2qq %ymm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2qq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2qq (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtps2uqq %ymm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2uqq (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2uqq (%rax){1to8}, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtps2uqq %ymm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2uqq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2uqq (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtps2uqq %ymm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2uqq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2uqq (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtqq2pd %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2pd (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2pd (%rax){1to8}, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtqq2pd %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2pd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2pd (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtqq2pd %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2pd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2pd (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtqq2ps %zmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2ps (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2ps (%rax){1to8}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtqq2ps %zmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2ps (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2ps (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtqq2ps %zmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2ps (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2ps (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttpd2qq %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2qq (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2qq (%rax){1to8}, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttpd2qq %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2qq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2qq (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttpd2qq %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2qq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2qq (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttpd2uqq %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2uqq (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2uqq (%rax){1to8}, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttpd2uqq %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2uqq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2uqq (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttpd2uqq %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2uqq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2uqq (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttps2qq %ymm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2qq (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2qq (%rax){1to8}, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttps2qq %ymm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2qq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2qq (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttps2qq %ymm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2qq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2qq (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttps2uqq %ymm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2uqq (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2uqq (%rax){1to8}, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttps2uqq %ymm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2uqq (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2uqq (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttps2uqq %ymm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2uqq (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2uqq (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtuqq2pd %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2pd (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2pd (%rax){1to8}, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtuqq2pd %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2pd (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2pd (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtuqq2pd %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2pd (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2pd (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtuqq2ps %zmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2ps (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2ps (%rax){1to8}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtuqq2ps %zmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2ps (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2ps (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtuqq2ps %zmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2ps (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2ps (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vextractf32x8 $1, %zmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vextractf32x8 $1, %zmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vextractf32x8 $1, %zmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vextractf32x8 $1, %zmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vextractf32x8 $1, %zmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vextractf64x2 $1, %zmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vextractf64x2 $1, %zmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vextractf64x2 $1, %zmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vextractf64x2 $1, %zmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vextractf64x2 $1, %zmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vextracti32x8 $1, %zmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vextracti32x8 $1, %zmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vextracti32x8 $1, %zmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vextracti32x8 $1, %zmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vextracti32x8 $1, %zmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vextracti64x2 $1, %zmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vextracti64x2 $1, %zmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vextracti64x2 $1, %zmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vextracti64x2 $1, %zmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vextracti64x2 $1, %zmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfpclasspd $171, %zmm16, %k1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfpclasspdz $171, (%rax), %k1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfpclasspd $171, (%rax){1to8}, %k1
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - vfpclasspd $171, %zmm16, %k1 {%k2}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfpclasspdz $171, (%rax), %k1 {%k2}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfpclasspd $171, (%rax){1to8}, %k1 {%k2}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfpclassps $171, %zmm16, %k1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfpclasspsz $171, (%rax), %k1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfpclassps $171, (%rax){1to16}, %k1
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - vfpclassps $171, %zmm16, %k1 {%k2}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfpclasspsz $171, (%rax), %k1 {%k2}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfpclassps $171, (%rax){1to16}, %k1 {%k2}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfpclasssd $171, %xmm16, %k1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfpclasssd $171, (%rax), %k1
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - vfpclasssd $171, %xmm16, %k1 {%k2}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfpclasssd $171, (%rax), %k1 {%k2}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfpclassss $171, %xmm16, %k1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfpclassss $171, (%rax), %k1
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - vfpclassss $171, %xmm16, %k1 {%k2}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfpclassss $171, (%rax), %k1 {%k2}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vinsertf32x8 $1, %ymm16, %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vinsertf32x8 $1, (%rax), %zmm16, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vinsertf32x8 $1, %ymm16, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vinsertf32x8 $1, (%rax), %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vinsertf32x8 $1, %ymm16, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vinsertf32x8 $1, (%rax), %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 8.00 - 8.00 - - - - - - - - - - - - vinsertf64x2 $1, %xmm16, %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 - 8.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vinsertf64x2 $1, (%rax), %zmm16, %zmm19
+# CHECK-NEXT: - - - - - - - - 8.00 - 8.00 - - - - - - - - - - - - vinsertf64x2 $1, %xmm16, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 - 8.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vinsertf64x2 $1, (%rax), %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 8.00 - 8.00 - - - - - - - - - - - - vinsertf64x2 $1, %xmm16, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 - 8.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vinsertf64x2 $1, (%rax), %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vinserti32x8 $1, %ymm16, %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vinserti32x8 $1, (%rax), %zmm16, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vinserti32x8 $1, %ymm16, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vinserti32x8 $1, (%rax), %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vinserti32x8 $1, %ymm16, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vinserti32x8 $1, (%rax), %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 8.00 - 8.00 - - - - - - - - - - - - vinserti64x2 $1, %xmm16, %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 - 8.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vinserti64x2 $1, (%rax), %zmm16, %zmm19
+# CHECK-NEXT: - - - - - - - - 8.00 - 8.00 - - - - - - - - - - - - vinserti64x2 $1, %xmm16, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 - 8.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vinserti64x2 $1, (%rax), %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 8.00 - 8.00 - - - - - - - - - - - - vinserti64x2 $1, %xmm16, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 - 8.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vinserti64x2 $1, (%rax), %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vorpd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorpd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorpd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vorpd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorpd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorpd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vorpd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorpd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorpd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vorps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vorps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vorps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpextrd $1, %xmm16, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vpextrd $1, %xmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpextrq $1, %xmm16, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vpextrq $1, %xmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpinsrd $1, %ecx, %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpinsrd $1, (%rax), %xmm16, %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpinsrq $1, %rcx, %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpinsrq $1, (%rax), %xmm16, %xmm19
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpmovm2d %k0, %zmm0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpmovm2q %k0, %zmm0
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - vpmovd2m %zmm0, %k0
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - vpmovq2m %zmm0, %k0
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmullq %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmullq (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmullq %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmullq (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmullq %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmullq (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vrangepd $ab, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangepd $ab, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangepd $ab, (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vrangepd $ab, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangepd $ab, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangepd $ab, (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vrangepd $ab, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangepd $ab, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangepd $ab, (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vrangepd $ab, {sae}, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vrangepd $ab, {sae}, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vrangepd $ab, {sae}, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vrangeps $ab, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangeps $ab, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangeps $ab, (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vrangeps $ab, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangeps $ab, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangeps $ab, (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vrangeps $ab, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangeps $ab, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangeps $ab, (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vrangeps $ab, {sae}, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vrangeps $ab, {sae}, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vrangeps $ab, {sae}, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vrangesd $ab, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangesd $ab, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vrangesd $ab, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangesd $ab, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vrangesd $ab, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangesd $ab, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vrangesd $ab, {sae}, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vrangesd $ab, {sae}, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vrangesd $ab, {sae}, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vrangess $ab, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangess $ab, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vrangess $ab, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangess $ab, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vrangess $ab, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangess $ab, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vrangess $ab, {sae}, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vrangess $ab, {sae}, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vrangess $ab, {sae}, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vreducepd $ab, %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreducepd $ab, (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreducepd $ab, (%rax){1to8}, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vreducepd $ab, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreducepd $ab, (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreducepd $ab, (%rax){1to8}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vreducepd $ab, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreducepd $ab, (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreducepd $ab, (%rax){1to8}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vreducepd $ab, {sae}, %zmm16, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vreducepd $ab, {sae}, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vreducepd $ab, {sae}, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vreduceps $ab, %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreduceps $ab, (%rax), %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreduceps $ab, (%rax){1to16}, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vreduceps $ab, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreduceps $ab, (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreduceps $ab, (%rax){1to16}, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vreduceps $ab, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreduceps $ab, (%rax), %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreduceps $ab, (%rax){1to16}, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vreduceps $ab, {sae}, %zmm16, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vreduceps $ab, {sae}, %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vreduceps $ab, {sae}, %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vreducesd $ab, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreducesd $ab, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vreducesd $ab, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreducesd $ab, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vreducesd $ab, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreducesd $ab, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vreducesd $ab, {sae}, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vreducesd $ab, {sae}, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vreducesd $ab, {sae}, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vreducess $ab, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreducess $ab, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vreducess $ab, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreducess $ab, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vreducess $ab, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreducess $ab, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vreducess $ab, {sae}, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vreducess $ab, {sae}, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vreducess $ab, {sae}, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vxorpd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorpd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorpd (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vxorpd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorpd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorpd (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vxorpd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorpd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorpd (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vxorps %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorps (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorps (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vxorps %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorps (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorps (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vxorps %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorps (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512dqvl.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512dqvl.s
new file mode 100644
index 0000000000000..c126778216035
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512dqvl.s
@@ -0,0 +1,1677 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+vandnpd %xmm16, %xmm17, %xmm19
+vandnpd (%rax), %xmm17, %xmm19
+vandnpd (%rax){1to2}, %xmm17, %xmm19
+vandnpd %xmm16, %xmm17, %xmm19 {k1}
+vandnpd (%rax), %xmm17, %xmm19 {k1}
+vandnpd (%rax){1to2}, %xmm17, %xmm19 {k1}
+vandnpd %xmm16, %xmm17, %xmm19 {z}{k1}
+vandnpd (%rax), %xmm17, %xmm19 {z}{k1}
+vandnpd (%rax){1to2}, %xmm17, %xmm19 {z}{k1}
+
+vandnpd %ymm16, %ymm17, %ymm19
+vandnpd (%rax), %ymm17, %ymm19
+vandnpd (%rax){1to4}, %ymm17, %ymm19
+vandnpd %ymm16, %ymm17, %ymm19 {k1}
+vandnpd (%rax), %ymm17, %ymm19 {k1}
+vandnpd (%rax){1to4}, %ymm17, %ymm19 {k1}
+vandnpd %ymm16, %ymm17, %ymm19 {z}{k1}
+vandnpd (%rax), %ymm17, %ymm19 {z}{k1}
+vandnpd (%rax){1to4}, %ymm17, %ymm19 {z}{k1}
+
+vandnps %xmm16, %xmm17, %xmm19
+vandnps (%rax), %xmm17, %xmm19
+vandnps (%rax){1to4}, %xmm17, %xmm19
+vandnps %xmm16, %xmm17, %xmm19 {k1}
+vandnps (%rax), %xmm17, %xmm19 {k1}
+vandnps (%rax){1to4}, %xmm17, %xmm19 {k1}
+vandnps %xmm16, %xmm17, %xmm19 {z}{k1}
+vandnps (%rax), %xmm17, %xmm19 {z}{k1}
+vandnps (%rax){1to4}, %xmm17, %xmm19 {z}{k1}
+
+vandnps %ymm16, %ymm17, %ymm19
+vandnps (%rax), %ymm17, %ymm19
+vandnps (%rax){1to8}, %ymm17, %ymm19
+vandnps %ymm16, %ymm17, %ymm19 {k1}
+vandnps (%rax), %ymm17, %ymm19 {k1}
+vandnps (%rax){1to8}, %ymm17, %ymm19 {k1}
+vandnps %ymm16, %ymm17, %ymm19 {z}{k1}
+vandnps (%rax), %ymm17, %ymm19 {z}{k1}
+vandnps (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
+
+vandpd %xmm16, %xmm17, %xmm19
+vandpd (%rax), %xmm17, %xmm19
+vandpd (%rax){1to2}, %xmm17, %xmm19
+vandpd %xmm16, %xmm17, %xmm19 {k1}
+vandpd (%rax), %xmm17, %xmm19 {k1}
+vandpd (%rax){1to2}, %xmm17, %xmm19 {k1}
+vandpd %xmm16, %xmm17, %xmm19 {z}{k1}
+vandpd (%rax), %xmm17, %xmm19 {z}{k1}
+vandpd (%rax){1to2}, %xmm17, %xmm19 {z}{k1}
+
+vandpd %ymm16, %ymm17, %ymm19
+vandpd (%rax), %ymm17, %ymm19
+vandpd (%rax){1to4}, %ymm17, %ymm19
+vandpd %ymm16, %ymm17, %ymm19 {k1}
+vandpd (%rax), %ymm17, %ymm19 {k1}
+vandpd (%rax){1to4}, %ymm17, %ymm19 {k1}
+vandpd %ymm16, %ymm17, %ymm19 {z}{k1}
+vandpd (%rax), %ymm17, %ymm19 {z}{k1}
+vandpd (%rax){1to4}, %ymm17, %ymm19 {z}{k1}
+
+vandps %xmm16, %xmm17, %xmm19
+vandps (%rax), %xmm17, %xmm19
+vandps (%rax){1to4}, %xmm17, %xmm19
+vandps %xmm16, %xmm17, %xmm19 {k1}
+vandps (%rax), %xmm17, %xmm19 {k1}
+vandps (%rax){1to4}, %xmm17, %xmm19 {k1}
+vandps %xmm16, %xmm17, %xmm19 {z}{k1}
+vandps (%rax), %xmm17, %xmm19 {z}{k1}
+vandps (%rax){1to4}, %xmm17, %xmm19 {z}{k1}
+
+vandps %ymm16, %ymm17, %ymm19
+vandps (%rax), %ymm17, %ymm19
+vandps (%rax){1to8}, %ymm17, %ymm19
+vandps %ymm16, %ymm17, %ymm19 {k1}
+vandps (%rax), %ymm17, %ymm19 {k1}
+vandps (%rax){1to8}, %ymm17, %ymm19 {k1}
+vandps %ymm16, %ymm17, %ymm19 {z}{k1}
+vandps (%rax), %ymm17, %ymm19 {z}{k1}
+vandps (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
+
+vbroadcastf32x2 %xmm16, %ymm19
+vbroadcastf32x2 (%rax), %ymm19
+vbroadcastf32x2 %xmm16, %ymm19 {k1}
+vbroadcastf32x2 (%rax), %ymm19 {k1}
+vbroadcastf32x2 %xmm16, %ymm19 {z}{k1}
+vbroadcastf32x2 (%rax), %ymm19 {z}{k1}
+
+vbroadcastf64x2 (%rax), %ymm19
+vbroadcastf64x2 (%rax), %ymm19 {k1}
+vbroadcastf64x2 (%rax), %ymm19 {z}{k1}
+
+vbroadcasti32x2 %xmm16, %xmm19
+vbroadcasti32x2 (%rax), %xmm19
+vbroadcasti32x2 %xmm16, %xmm19 {k1}
+vbroadcasti32x2 (%rax), %xmm19 {k1}
+vbroadcasti32x2 %xmm16, %xmm19 {z}{k1}
+vbroadcasti32x2 (%rax), %xmm19 {z}{k1}
+
+vbroadcasti32x2 %xmm16, %ymm19
+vbroadcasti32x2 (%rax), %ymm19
+vbroadcasti32x2 %xmm16, %ymm19 {k1}
+vbroadcasti32x2 (%rax), %ymm19 {k1}
+vbroadcasti32x2 %xmm16, %ymm19 {z}{k1}
+vbroadcasti32x2 (%rax), %ymm19 {z}{k1}
+
+vbroadcasti64x2 (%rax), %ymm19
+vbroadcasti64x2 (%rax), %ymm19 {k1}
+vbroadcasti64x2 (%rax), %ymm19 {z}{k1}
+
+vcvtpd2qq %xmm16, %xmm19
+vcvtpd2qq (%rax), %xmm19
+vcvtpd2qq (%rax){1to2}, %xmm19
+vcvtpd2qq %xmm16, %xmm19 {k1}
+vcvtpd2qq (%rax), %xmm19 {k1}
+vcvtpd2qq (%rax){1to2}, %xmm19 {k1}
+vcvtpd2qq %xmm16, %xmm19 {z}{k1}
+vcvtpd2qq (%rax), %xmm19 {z}{k1}
+vcvtpd2qq (%rax){1to2}, %xmm19 {z}{k1}
+
+vcvtpd2qq %ymm16, %ymm19
+vcvtpd2qq (%rax), %ymm19
+vcvtpd2qq (%rax){1to4}, %ymm19
+vcvtpd2qq %ymm16, %ymm19 {k1}
+vcvtpd2qq (%rax), %ymm19 {k1}
+vcvtpd2qq (%rax){1to4}, %ymm19 {k1}
+vcvtpd2qq %ymm16, %ymm19 {z}{k1}
+vcvtpd2qq (%rax), %ymm19 {z}{k1}
+vcvtpd2qq (%rax){1to4}, %ymm19 {z}{k1}
+
+vcvtpd2uqq %xmm16, %xmm19
+vcvtpd2uqq (%rax), %xmm19
+vcvtpd2uqq (%rax){1to2}, %xmm19
+vcvtpd2uqq %xmm16, %xmm19 {k1}
+vcvtpd2uqq (%rax), %xmm19 {k1}
+vcvtpd2uqq (%rax){1to2}, %xmm19 {k1}
+vcvtpd2uqq %xmm16, %xmm19 {z}{k1}
+vcvtpd2uqq (%rax), %xmm19 {z}{k1}
+vcvtpd2uqq (%rax){1to2}, %xmm19 {z}{k1}
+
+vcvtpd2uqq %ymm16, %ymm19
+vcvtpd2uqq (%rax), %ymm19
+vcvtpd2uqq (%rax){1to4}, %ymm19
+vcvtpd2uqq %ymm16, %ymm19 {k1}
+vcvtpd2uqq (%rax), %ymm19 {k1}
+vcvtpd2uqq (%rax){1to4}, %ymm19 {k1}
+vcvtpd2uqq %ymm16, %ymm19 {z}{k1}
+vcvtpd2uqq (%rax), %ymm19 {z}{k1}
+vcvtpd2uqq (%rax){1to4}, %ymm19 {z}{k1}
+
+vcvtps2qq %xmm16, %xmm19
+vcvtps2qq (%rax), %xmm19
+vcvtps2qq (%rax){1to2}, %xmm19
+vcvtps2qq %xmm16, %xmm19 {k1}
+vcvtps2qq (%rax), %xmm19 {k1}
+vcvtps2qq (%rax){1to2}, %xmm19 {k1}
+vcvtps2qq %xmm16, %xmm19 {z}{k1}
+vcvtps2qq (%rax), %xmm19 {z}{k1}
+vcvtps2qq (%rax){1to2}, %xmm19 {z}{k1}
+
+vcvtps2qq %xmm16, %ymm19
+vcvtps2qq (%rax), %ymm19
+vcvtps2qq (%rax){1to4}, %ymm19
+vcvtps2qq %xmm16, %ymm19 {k1}
+vcvtps2qq (%rax), %ymm19 {k1}
+vcvtps2qq (%rax){1to4}, %ymm19 {k1}
+vcvtps2qq %xmm16, %ymm19 {z}{k1}
+vcvtps2qq (%rax), %ymm19 {z}{k1}
+vcvtps2qq (%rax){1to4}, %ymm19 {z}{k1}
+
+vcvtps2uqq %xmm16, %xmm19
+vcvtps2uqq (%rax), %xmm19
+vcvtps2uqq (%rax){1to2}, %xmm19
+vcvtps2uqq %xmm16, %xmm19 {k1}
+vcvtps2uqq (%rax), %xmm19 {k1}
+vcvtps2uqq (%rax){1to2}, %xmm19 {k1}
+vcvtps2uqq %xmm16, %xmm19 {z}{k1}
+vcvtps2uqq (%rax), %xmm19 {z}{k1}
+vcvtps2uqq (%rax){1to2}, %xmm19 {z}{k1}
+
+vcvtps2uqq %xmm16, %ymm19
+vcvtps2uqq (%rax), %ymm19
+vcvtps2uqq (%rax){1to4}, %ymm19
+vcvtps2uqq %xmm16, %ymm19 {k1}
+vcvtps2uqq (%rax), %ymm19 {k1}
+vcvtps2uqq (%rax){1to4}, %ymm19 {k1}
+vcvtps2uqq %xmm16, %ymm19 {z}{k1}
+vcvtps2uqq (%rax), %ymm19 {z}{k1}
+vcvtps2uqq (%rax){1to4}, %ymm19 {z}{k1}
+
+vcvtqq2pd %xmm16, %xmm19
+vcvtqq2pd (%rax), %xmm19
+vcvtqq2pd (%rax){1to2}, %xmm19
+vcvtqq2pd %xmm16, %xmm19 {k1}
+vcvtqq2pd (%rax), %xmm19 {k1}
+vcvtqq2pd (%rax){1to2}, %xmm19 {k1}
+vcvtqq2pd %xmm16, %xmm19 {z}{k1}
+vcvtqq2pd (%rax), %xmm19 {z}{k1}
+vcvtqq2pd (%rax){1to2}, %xmm19 {z}{k1}
+
+vcvtqq2pd %ymm16, %ymm19
+vcvtqq2pd (%rax), %ymm19
+vcvtqq2pd (%rax){1to4}, %ymm19
+vcvtqq2pd %ymm16, %ymm19 {k1}
+vcvtqq2pd (%rax), %ymm19 {k1}
+vcvtqq2pd (%rax){1to4}, %ymm19 {k1}
+vcvtqq2pd %ymm16, %ymm19 {z}{k1}
+vcvtqq2pd (%rax), %ymm19 {z}{k1}
+vcvtqq2pd (%rax){1to4}, %ymm19 {z}{k1}
+
+vcvtqq2ps %xmm16, %xmm19
+vcvtqq2psx (%rax), %xmm19
+vcvtqq2ps (%rax){1to2}, %xmm19
+vcvtqq2ps %xmm16, %xmm19 {k1}
+vcvtqq2psx (%rax), %xmm19 {k1}
+vcvtqq2ps (%rax){1to2}, %xmm19 {k1}
+vcvtqq2ps %xmm16, %xmm19 {z}{k1}
+vcvtqq2psx (%rax), %xmm19 {z}{k1}
+vcvtqq2ps (%rax){1to2}, %xmm19 {z}{k1}
+
+vcvtqq2ps %ymm16, %xmm19
+vcvtqq2psx (%rax), %xmm19
+vcvtqq2ps (%rax){1to4}, %xmm19
+vcvtqq2ps %ymm16, %xmm19 {k1}
+vcvtqq2psx (%rax), %xmm19 {k1}
+vcvtqq2ps (%rax){1to4}, %xmm19 {k1}
+vcvtqq2ps %ymm16, %xmm19 {z}{k1}
+vcvtqq2psx (%rax), %xmm19 {z}{k1}
+vcvtqq2ps (%rax){1to4}, %xmm19 {z}{k1}
+
+vcvttpd2qq %xmm16, %xmm19
+vcvttpd2qq (%rax), %xmm19
+vcvttpd2qq (%rax){1to2}, %xmm19
+vcvttpd2qq %xmm16, %xmm19 {k1}
+vcvttpd2qq (%rax), %xmm19 {k1}
+vcvttpd2qq (%rax){1to2}, %xmm19 {k1}
+vcvttpd2qq %xmm16, %xmm19 {z}{k1}
+vcvttpd2qq (%rax), %xmm19 {z}{k1}
+vcvttpd2qq (%rax){1to2}, %xmm19 {z}{k1}
+
+vcvttpd2qq %ymm16, %ymm19
+vcvttpd2qq (%rax), %ymm19
+vcvttpd2qq (%rax){1to4}, %ymm19
+vcvttpd2qq %ymm16, %ymm19 {k1}
+vcvttpd2qq (%rax), %ymm19 {k1}
+vcvttpd2qq (%rax){1to4}, %ymm19 {k1}
+vcvttpd2qq %ymm16, %ymm19 {z}{k1}
+vcvttpd2qq (%rax), %ymm19 {z}{k1}
+vcvttpd2qq (%rax){1to4}, %ymm19 {z}{k1}
+
+vcvttpd2uqq %xmm16, %xmm19
+vcvttpd2uqq (%rax), %xmm19
+vcvttpd2uqq (%rax){1to2}, %xmm19
+vcvttpd2uqq %xmm16, %xmm19 {k1}
+vcvttpd2uqq (%rax), %xmm19 {k1}
+vcvttpd2uqq (%rax){1to2}, %xmm19 {k1}
+vcvttpd2uqq %xmm16, %xmm19 {z}{k1}
+vcvttpd2uqq (%rax), %xmm19 {z}{k1}
+vcvttpd2uqq (%rax){1to2}, %xmm19 {z}{k1}
+
+vcvttpd2uqq %ymm16, %ymm19
+vcvttpd2uqq (%rax), %ymm19
+vcvttpd2uqq (%rax){1to4}, %ymm19
+vcvttpd2uqq %ymm16, %ymm19 {k1}
+vcvttpd2uqq (%rax), %ymm19 {k1}
+vcvttpd2uqq (%rax){1to4}, %ymm19 {k1}
+vcvttpd2uqq %ymm16, %ymm19 {z}{k1}
+vcvttpd2uqq (%rax), %ymm19 {z}{k1}
+vcvttpd2uqq (%rax){1to4}, %ymm19 {z}{k1}
+
+vcvttps2qq %xmm16, %xmm19
+vcvttps2qq (%rax), %xmm19
+vcvttps2qq (%rax){1to2}, %xmm19
+vcvttps2qq %xmm16, %xmm19 {k1}
+vcvttps2qq (%rax), %xmm19 {k1}
+vcvttps2qq (%rax){1to2}, %xmm19 {k1}
+vcvttps2qq %xmm16, %xmm19 {z}{k1}
+vcvttps2qq (%rax), %xmm19 {z}{k1}
+vcvttps2qq (%rax){1to2}, %xmm19 {z}{k1}
+
+vcvttps2qq %xmm16, %ymm19
+vcvttps2qq (%rax), %ymm19
+vcvttps2qq (%rax){1to4}, %ymm19
+vcvttps2qq %xmm16, %ymm19 {k1}
+vcvttps2qq (%rax), %ymm19 {k1}
+vcvttps2qq (%rax){1to4}, %ymm19 {k1}
+vcvttps2qq %xmm16, %ymm19 {z}{k1}
+vcvttps2qq (%rax), %ymm19 {z}{k1}
+vcvttps2qq (%rax){1to4}, %ymm19 {z}{k1}
+
+vcvttps2uqq %xmm16, %xmm19
+vcvttps2uqq (%rax), %xmm19
+vcvttps2uqq (%rax){1to2}, %xmm19
+vcvttps2uqq %xmm16, %xmm19 {k1}
+vcvttps2uqq (%rax), %xmm19 {k1}
+vcvttps2uqq (%rax){1to2}, %xmm19 {k1}
+vcvttps2uqq %xmm16, %xmm19 {z}{k1}
+vcvttps2uqq (%rax), %xmm19 {z}{k1}
+vcvttps2uqq (%rax){1to2}, %xmm19 {z}{k1}
+
+vcvttps2uqq %xmm16, %ymm19
+vcvttps2uqq (%rax), %ymm19
+vcvttps2uqq (%rax){1to4}, %ymm19
+vcvttps2uqq %xmm16, %ymm19 {k1}
+vcvttps2uqq (%rax), %ymm19 {k1}
+vcvttps2uqq (%rax){1to4}, %ymm19 {k1}
+vcvttps2uqq %xmm16, %ymm19 {z}{k1}
+vcvttps2uqq (%rax), %ymm19 {z}{k1}
+vcvttps2uqq (%rax){1to4}, %ymm19 {z}{k1}
+
+vcvtuqq2pd %xmm16, %xmm19
+vcvtuqq2pd (%rax), %xmm19
+vcvtuqq2pd (%rax){1to2}, %xmm19
+vcvtuqq2pd %xmm16, %xmm19 {k1}
+vcvtuqq2pd (%rax), %xmm19 {k1}
+vcvtuqq2pd (%rax){1to2}, %xmm19 {k1}
+vcvtuqq2pd %xmm16, %xmm19 {z}{k1}
+vcvtuqq2pd (%rax), %xmm19 {z}{k1}
+vcvtuqq2pd (%rax){1to2}, %xmm19 {z}{k1}
+
+vcvtuqq2pd %ymm16, %ymm19
+vcvtuqq2pd (%rax), %ymm19
+vcvtuqq2pd (%rax){1to4}, %ymm19
+vcvtuqq2pd %ymm16, %ymm19 {k1}
+vcvtuqq2pd (%rax), %ymm19 {k1}
+vcvtuqq2pd (%rax){1to4}, %ymm19 {k1}
+vcvtuqq2pd %ymm16, %ymm19 {z}{k1}
+vcvtuqq2pd (%rax), %ymm19 {z}{k1}
+vcvtuqq2pd (%rax){1to4}, %ymm19 {z}{k1}
+
+vcvtuqq2ps %xmm16, %xmm19
+vcvtuqq2psx (%rax), %xmm19
+vcvtuqq2ps (%rax){1to2}, %xmm19
+vcvtuqq2ps %xmm16, %xmm19 {k1}
+vcvtuqq2psx (%rax), %xmm19 {k1}
+vcvtuqq2ps (%rax){1to2}, %xmm19 {k1}
+vcvtuqq2ps %xmm16, %xmm19 {z}{k1}
+vcvtuqq2psx (%rax), %xmm19 {z}{k1}
+vcvtuqq2ps (%rax){1to2}, %xmm19 {z}{k1}
+
+vcvtuqq2ps %ymm16, %xmm19
+vcvtuqq2psx (%rax), %xmm19
+vcvtuqq2ps (%rax){1to4}, %xmm19
+vcvtuqq2ps %ymm16, %xmm19 {k1}
+vcvtuqq2psx (%rax), %xmm19 {k1}
+vcvtuqq2ps (%rax){1to4}, %xmm19 {k1}
+vcvtuqq2ps %ymm16, %xmm19 {z}{k1}
+vcvtuqq2psx (%rax), %xmm19 {z}{k1}
+vcvtuqq2ps (%rax){1to4}, %xmm19 {z}{k1}
+
+vextractf64x2 $1, %ymm16, %xmm19
+vextractf64x2 $1, %ymm16, (%rax)
+vextractf64x2 $1, %ymm16, %xmm19 {k1}
+vextractf64x2 $1, %ymm16, (%rax) {k1}
+vextractf64x2 $1, %ymm16, %xmm19 {z}{k1}
+
+vextracti64x2 $1, %ymm16, %xmm19
+vextracti64x2 $1, %ymm16, (%rax)
+vextracti64x2 $1, %ymm16, %xmm19 {k1}
+vextracti64x2 $1, %ymm16, (%rax) {k1}
+vextracti64x2 $1, %ymm16, %xmm19 {z}{k1}
+
+vfpclasspd $0xab, %xmm16, %k1
+vfpclasspdx $0xab, (%rax), %k1
+vfpclasspdx $0xab, (%rax){1to2}, %k1
+vfpclasspd $0xab, %xmm16, %k1 {k2}
+vfpclasspdx $0xab, (%rax), %k1 {k2}
+vfpclasspdx $0xab, (%rax){1to2}, %k1 {k2}
+
+vfpclasspd $0xab, %ymm16, %k1
+vfpclasspdy $0xab, (%rax), %k1
+vfpclasspdy $0xab, (%rax){1to4}, %k1
+vfpclasspd $0xab, %ymm16, %k1 {k2}
+vfpclasspdy $0xab, (%rax), %k1 {k2}
+vfpclasspdy $0xab, (%rax){1to4}, %k1 {k2}
+
+vfpclassps $0xab, %xmm16, %k1
+vfpclasspsx $0xab, (%rax), %k1
+vfpclasspsx $0xab, (%rax){1to4}, %k1
+vfpclassps $0xab, %xmm16, %k1 {k2}
+vfpclasspsx $0xab, (%rax), %k1 {k2}
+vfpclasspsx $0xab, (%rax){1to4}, %k1 {k2}
+
+vfpclassps $0xab, %ymm16, %k1
+vfpclasspsy $0xab, (%rax), %k1
+vfpclasspsy $0xab, (%rax){1to8}, %k1
+vfpclassps $0xab, %ymm16, %k1 {k2}
+vfpclasspsy $0xab, (%rax), %k1 {k2}
+vfpclasspsy $0xab, (%rax){1to8}, %k1 {k2}
+
+vinsertf64x2 $1, %xmm16, %ymm16, %ymm19
+vinsertf64x2 $1, (%rax), %ymm16, %ymm19
+vinsertf64x2 $1, %xmm16, %ymm16, %ymm19 {k1}
+vinsertf64x2 $1, (%rax), %ymm16, %ymm19 {k1}
+vinsertf64x2 $1, %xmm16, %ymm16, %ymm19 {z}{k1}
+vinsertf64x2 $1, (%rax), %ymm16, %ymm19 {z}{k1}
+
+vinserti64x2 $1, %xmm16, %ymm16, %ymm19
+vinserti64x2 $1, (%rax), %ymm16, %ymm19
+vinserti64x2 $1, %xmm16, %ymm16, %ymm19 {k1}
+vinserti64x2 $1, (%rax), %ymm16, %ymm19 {k1}
+vinserti64x2 $1, %xmm16, %ymm16, %ymm19 {z}{k1}
+vinserti64x2 $1, (%rax), %ymm16, %ymm19 {z}{k1}
+
+vpmovm2d %k0, %xmm0
+vpmovm2q %k0, %xmm0
+
+vpmovm2d %k0, %ymm0
+vpmovm2q %k0, %ymm0
+
+vpmovd2m %xmm0, %k0
+vpmovq2m %xmm0, %k0
+
+vpmovd2m %ymm0, %k0
+vpmovq2m %ymm0, %k0
+
+vorpd %xmm16, %xmm17, %xmm19
+vorpd (%rax), %xmm17, %xmm19
+vorpd (%rax){1to2}, %xmm17, %xmm19
+vorpd %xmm16, %xmm17, %xmm19 {k1}
+vorpd (%rax), %xmm17, %xmm19 {k1}
+vorpd (%rax){1to2}, %xmm17, %xmm19 {k1}
+vorpd %xmm16, %xmm17, %xmm19 {z}{k1}
+vorpd (%rax), %xmm17, %xmm19 {z}{k1}
+vorpd (%rax){1to2}, %xmm17, %xmm19 {z}{k1}
+
+vorpd %ymm16, %ymm17, %ymm19
+vorpd (%rax), %ymm17, %ymm19
+vorpd (%rax){1to4}, %ymm17, %ymm19
+vorpd %ymm16, %ymm17, %ymm19 {k1}
+vorpd (%rax), %ymm17, %ymm19 {k1}
+vorpd (%rax){1to4}, %ymm17, %ymm19 {k1}
+vorpd %ymm16, %ymm17, %ymm19 {z}{k1}
+vorpd (%rax), %ymm17, %ymm19 {z}{k1}
+vorpd (%rax){1to4}, %ymm17, %ymm19 {z}{k1}
+
+vorps %xmm16, %xmm17, %xmm19
+vorps (%rax), %xmm17, %xmm19
+vorps (%rax){1to4}, %xmm17, %xmm19
+vorps %xmm16, %xmm17, %xmm19 {k1}
+vorps (%rax), %xmm17, %xmm19 {k1}
+vorps (%rax){1to4}, %xmm17, %xmm19 {k1}
+vorps %xmm16, %xmm17, %xmm19 {z}{k1}
+vorps (%rax), %xmm17, %xmm19 {z}{k1}
+vorps (%rax){1to4}, %xmm17, %xmm19 {z}{k1}
+
+vorps %ymm16, %ymm17, %ymm19
+vorps (%rax), %ymm17, %ymm19
+vorps (%rax){1to8}, %ymm17, %ymm19
+vorps %ymm16, %ymm17, %ymm19 {k1}
+vorps (%rax), %ymm17, %ymm19 {k1}
+vorps (%rax){1to8}, %ymm17, %ymm19 {k1}
+vorps %ymm16, %ymm17, %ymm19 {z}{k1}
+vorps (%rax), %ymm17, %ymm19 {z}{k1}
+vorps (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
+
+vpmullq %xmm16, %xmm17, %xmm19
+vpmullq (%rax), %xmm17, %xmm19
+vpmullq %xmm16, %xmm17, %xmm19 {k1}
+vpmullq (%rax), %xmm17, %xmm19 {k1}
+vpmullq %xmm16, %xmm17, %xmm19 {z}{k1}
+vpmullq (%rax), %xmm17, %xmm19 {z}{k1}
+
+vpmullq %ymm16, %ymm17, %ymm19
+vpmullq (%rax), %ymm17, %ymm19
+vpmullq %ymm16, %ymm17, %ymm19 {k1}
+vpmullq (%rax), %ymm17, %ymm19 {k1}
+vpmullq %ymm16, %ymm17, %ymm19 {z}{k1}
+vpmullq (%rax), %ymm17, %ymm19 {z}{k1}
+
+vrangepd $ab, %xmm16, %xmm17, %xmm19
+vrangepd $ab, (%rax), %xmm17, %xmm19
+vrangepd $ab, (%rax){1to2}, %xmm17, %xmm19
+vrangepd $ab, %xmm16, %xmm17, %xmm19 {k1}
+vrangepd $ab, (%rax), %xmm17, %xmm19 {k1}
+vrangepd $ab, (%rax){1to2}, %xmm17, %xmm19 {k1}
+vrangepd $ab, %xmm16, %xmm17, %xmm19 {z}{k1}
+vrangepd $ab, (%rax), %xmm17, %xmm19 {z}{k1}
+vrangepd $ab, (%rax){1to2}, %xmm17, %xmm19 {z}{k1}
+
+vrangepd $ab, %ymm16, %ymm17, %ymm19
+vrangepd $ab, (%rax), %ymm17, %ymm19
+vrangepd $ab, (%rax){1to4}, %ymm17, %ymm19
+vrangepd $ab, %ymm16, %ymm17, %ymm19 {k1}
+vrangepd $ab, (%rax), %ymm17, %ymm19 {k1}
+vrangepd $ab, (%rax){1to4}, %ymm17, %ymm19 {k1}
+vrangepd $ab, %ymm16, %ymm17, %ymm19 {z}{k1}
+vrangepd $ab, (%rax), %ymm17, %ymm19 {z}{k1}
+vrangepd $ab, (%rax){1to4}, %ymm17, %ymm19 {z}{k1}
+
+vrangeps $ab, %xmm16, %xmm17, %xmm19
+vrangeps $ab, (%rax), %xmm17, %xmm19
+vrangeps $ab, (%rax){1to4}, %xmm17, %xmm19
+vrangeps $ab, %xmm16, %xmm17, %xmm19 {k1}
+vrangeps $ab, (%rax), %xmm17, %xmm19 {k1}
+vrangeps $ab, (%rax){1to4}, %xmm17, %xmm19 {k1}
+vrangeps $ab, %xmm16, %xmm17, %xmm19 {z}{k1}
+vrangeps $ab, (%rax), %xmm17, %xmm19 {z}{k1}
+vrangeps $ab, (%rax){1to4}, %xmm17, %xmm19 {z}{k1}
+
+vrangeps $ab, %ymm16, %ymm17, %ymm19
+vrangeps $ab, (%rax), %ymm17, %ymm19
+vrangeps $ab, (%rax){1to8}, %ymm17, %ymm19
+vrangeps $ab, %ymm16, %ymm17, %ymm19 {k1}
+vrangeps $ab, (%rax), %ymm17, %ymm19 {k1}
+vrangeps $ab, (%rax){1to8}, %ymm17, %ymm19 {k1}
+vrangeps $ab, %ymm16, %ymm17, %ymm19 {z}{k1}
+vrangeps $ab, (%rax), %ymm17, %ymm19 {z}{k1}
+vrangeps $ab, (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
+
+vreducepd $ab, %xmm16, %xmm19
+vreducepd $ab, (%rax), %xmm19
+vreducepd $ab, (%rax){1to2}, %xmm19
+vreducepd $ab, %xmm16, %xmm19 {k1}
+vreducepd $ab, (%rax), %xmm19 {k1}
+vreducepd $ab, (%rax){1to2}, %xmm19 {k1}
+vreducepd $ab, %xmm16, %xmm19 {z}{k1}
+vreducepd $ab, (%rax), %xmm19 {z}{k1}
+vreducepd $ab, (%rax){1to2}, %xmm19 {z}{k1}
+
+vreducepd $ab, %ymm16, %ymm19
+vreducepd $ab, (%rax), %ymm19
+vreducepd $ab, (%rax){1to4}, %ymm19
+vreducepd $ab, %ymm16, %ymm19 {k1}
+vreducepd $ab, (%rax), %ymm19 {k1}
+vreducepd $ab, (%rax){1to4}, %ymm19 {k1}
+vreducepd $ab, %ymm16, %ymm19 {z}{k1}
+vreducepd $ab, (%rax), %ymm19 {z}{k1}
+vreducepd $ab, (%rax){1to4}, %ymm19 {z}{k1}
+
+vreduceps $ab, %xmm16, %xmm19
+vreduceps $ab, (%rax), %xmm19
+vreduceps $ab, (%rax){1to4}, %xmm19
+vreduceps $ab, %xmm16, %xmm19 {k1}
+vreduceps $ab, (%rax), %xmm19 {k1}
+vreduceps $ab, (%rax){1to4}, %xmm19 {k1}
+vreduceps $ab, %xmm16, %xmm19 {z}{k1}
+vreduceps $ab, (%rax), %xmm19 {z}{k1}
+vreduceps $ab, (%rax){1to4}, %xmm19 {z}{k1}
+
+vreduceps $ab, %ymm16, %ymm19
+vreduceps $ab, (%rax), %ymm19
+vreduceps $ab, (%rax){1to8}, %ymm19
+vreduceps $ab, %ymm16, %ymm19 {k1}
+vreduceps $ab, (%rax), %ymm19 {k1}
+vreduceps $ab, (%rax){1to8}, %ymm19 {k1}
+vreduceps $ab, %ymm16, %ymm19 {z}{k1}
+vreduceps $ab, (%rax), %ymm19 {z}{k1}
+vreduceps $ab, (%rax){1to8}, %ymm19 {z}{k1}
+
+vxorpd %xmm16, %xmm17, %xmm19
+vxorpd (%rax), %xmm17, %xmm19
+vxorpd (%rax){1to2}, %xmm17, %xmm19
+vxorpd %xmm16, %xmm17, %xmm19 {k1}
+vxorpd (%rax), %xmm17, %xmm19 {k1}
+vxorpd (%rax){1to2}, %xmm17, %xmm19 {k1}
+vxorpd %xmm16, %xmm17, %xmm19 {z}{k1}
+vxorpd (%rax), %xmm17, %xmm19 {z}{k1}
+vxorpd (%rax){1to2}, %xmm17, %xmm19 {z}{k1}
+
+vxorpd %ymm16, %ymm17, %ymm19
+vxorpd (%rax), %ymm17, %ymm19
+vxorpd (%rax){1to4}, %ymm17, %ymm19
+vxorpd %ymm16, %ymm17, %ymm19 {k1}
+vxorpd (%rax), %ymm17, %ymm19 {k1}
+vxorpd (%rax){1to4}, %ymm17, %ymm19 {k1}
+vxorpd %ymm16, %ymm17, %ymm19 {z}{k1}
+vxorpd (%rax), %ymm17, %ymm19 {z}{k1}
+vxorpd (%rax){1to4}, %ymm17, %ymm19 {z}{k1}
+
+vxorps %xmm16, %xmm17, %xmm19
+vxorps (%rax), %xmm17, %xmm19
+vxorps (%rax){1to4}, %xmm17, %xmm19
+vxorps %xmm16, %xmm17, %xmm19 {k1}
+vxorps (%rax), %xmm17, %xmm19 {k1}
+vxorps (%rax){1to4}, %xmm17, %xmm19 {k1}
+vxorps %xmm16, %xmm17, %xmm19 {z}{k1}
+vxorps (%rax), %xmm17, %xmm19 {z}{k1}
+vxorps (%rax){1to4}, %xmm17, %xmm19 {z}{k1}
+
+vxorps %ymm16, %ymm17, %ymm19
+vxorps (%rax), %ymm17, %ymm19
+vxorps (%rax){1to8}, %ymm17, %ymm19
+vxorps %ymm16, %ymm17, %ymm19 {k1}
+vxorps (%rax), %ymm17, %ymm19 {k1}
+vxorps (%rax){1to8}, %ymm17, %ymm19 {k1}
+vxorps %ymm16, %ymm17, %ymm19 {z}{k1}
+vxorps (%rax), %ymm17, %ymm19 {z}{k1}
+vxorps (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.25 vandnpd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vandnpd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vandnpd (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: 2 2 0.50 vandnpd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 2 9 0.50 * vandnpd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vandnpd (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vandnpd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vandnpd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vandnpd (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vandnpd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vandnpd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vandnpd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 2 2 0.50 vandnpd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 2 9 0.50 * vandnpd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vandnpd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vandnpd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vandnpd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vandnpd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vandnps %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vandnps (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vandnps (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: 2 2 0.50 vandnps %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 2 9 0.50 * vandnps (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vandnps (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vandnps %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vandnps (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vandnps (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vandnps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vandnps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vandnps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 2 2 0.50 vandnps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 2 9 0.50 * vandnps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vandnps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vandnps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vandnps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vandnps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vandpd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vandpd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vandpd (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: 2 2 0.50 vandpd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 2 9 0.50 * vandpd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vandpd (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vandpd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vandpd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vandpd (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vandpd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vandpd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vandpd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 2 2 0.50 vandpd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 2 9 0.50 * vandpd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vandpd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vandpd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vandpd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vandpd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vandps %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vandps (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vandps (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: 2 2 0.50 vandps %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 2 9 0.50 * vandps (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vandps (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vandps %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vandps (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vandps (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vandps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vandps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vandps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 2 2 0.50 vandps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 2 9 0.50 * vandps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vandps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vandps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vandps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vandps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vbroadcastf32x2 %xmm16, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vbroadcastf32x2 (%rax), %ymm19
+# CHECK-NEXT: 1 4 2.00 vbroadcastf32x2 %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 2.00 * vbroadcastf32x2 (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vbroadcastf32x2 %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vbroadcastf32x2 (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vbroadcastf64x2 (%rax), %ymm19
+# CHECK-NEXT: 1 8 0.50 * vbroadcastf64x2 (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vbroadcastf64x2 (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vbroadcasti32x2 %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vbroadcasti32x2 (%rax), %xmm19
+# CHECK-NEXT: 1 2 0.50 vbroadcasti32x2 %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vbroadcasti32x2 (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vbroadcasti32x2 %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vbroadcasti32x2 (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vbroadcasti32x2 %xmm16, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vbroadcasti32x2 (%rax), %ymm19
+# CHECK-NEXT: 1 4 2.00 vbroadcasti32x2 %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 2.00 * vbroadcasti32x2 (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vbroadcasti32x2 %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vbroadcasti32x2 (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vbroadcasti64x2 (%rax), %ymm19
+# CHECK-NEXT: 1 8 0.50 * vbroadcasti64x2 (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vbroadcasti64x2 (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 4 1.00 vcvtpd2qq %xmm16, %xmm19
+# CHECK-NEXT: 2 11 1.00 * vcvtpd2qq (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2qq (%rax){1to2}, %xmm19
+# CHECK-NEXT: 2 5 1.00 vcvtpd2qq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtpd2qq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2qq (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: 2 4 1.00 vcvtpd2qq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vcvtpd2qq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2qq (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 2 4 1.00 vcvtpd2qq %ymm16, %ymm19
+# CHECK-NEXT: 2 11 1.00 * vcvtpd2qq (%rax), %ymm19
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2qq (%rax){1to4}, %ymm19
+# CHECK-NEXT: 2 5 1.00 vcvtpd2qq %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtpd2qq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2qq (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: 2 4 1.00 vcvtpd2qq %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vcvtpd2qq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2qq (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 4 1.00 vcvtpd2uqq %xmm16, %xmm19
+# CHECK-NEXT: 2 11 1.00 * vcvtpd2uqq (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2uqq (%rax){1to2}, %xmm19
+# CHECK-NEXT: 2 5 1.00 vcvtpd2uqq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtpd2uqq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2uqq (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: 2 4 1.00 vcvtpd2uqq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vcvtpd2uqq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2uqq (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 2 4 1.00 vcvtpd2uqq %ymm16, %ymm19
+# CHECK-NEXT: 2 11 1.00 * vcvtpd2uqq (%rax), %ymm19
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2uqq (%rax){1to4}, %ymm19
+# CHECK-NEXT: 2 5 1.00 vcvtpd2uqq %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtpd2uqq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2uqq (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: 2 4 1.00 vcvtpd2uqq %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vcvtpd2uqq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2uqq (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvtps2qq %xmm16, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtps2qq (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtps2qq (%rax){1to2}, %xmm19
+# CHECK-NEXT: 2 5 1.00 vcvtps2qq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtps2qq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvtps2qq (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvtps2qq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtps2qq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtps2qq (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvtps2qq %xmm16, %ymm19
+# CHECK-NEXT: 1 11 0.50 * vcvtps2qq (%rax), %ymm19
+# CHECK-NEXT: 1 11 0.50 * vcvtps2qq (%rax){1to4}, %ymm19
+# CHECK-NEXT: 2 5 1.00 vcvtps2qq %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtps2qq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvtps2qq (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvtps2qq %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtps2qq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtps2qq (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvtps2uqq %xmm16, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtps2uqq (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtps2uqq (%rax){1to2}, %xmm19
+# CHECK-NEXT: 2 5 1.00 vcvtps2uqq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtps2uqq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvtps2uqq (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvtps2uqq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtps2uqq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtps2uqq (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvtps2uqq %xmm16, %ymm19
+# CHECK-NEXT: 1 11 0.50 * vcvtps2uqq (%rax), %ymm19
+# CHECK-NEXT: 1 11 0.50 * vcvtps2uqq (%rax){1to4}, %ymm19
+# CHECK-NEXT: 2 5 1.00 vcvtps2uqq %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtps2uqq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvtps2uqq (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvtps2uqq %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtps2uqq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtps2uqq (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvtqq2pd %xmm16, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtqq2pd (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtqq2pd (%rax){1to2}, %xmm19
+# CHECK-NEXT: 2 5 1.00 vcvtqq2pd %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtqq2pd (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvtqq2pd (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvtqq2pd %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtqq2pd (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtqq2pd (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvtqq2pd %ymm16, %ymm19
+# CHECK-NEXT: 1 11 0.50 * vcvtqq2pd (%rax), %ymm19
+# CHECK-NEXT: 1 11 0.50 * vcvtqq2pd (%rax){1to4}, %ymm19
+# CHECK-NEXT: 2 5 1.00 vcvtqq2pd %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtqq2pd (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvtqq2pd (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvtqq2pd %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtqq2pd (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtqq2pd (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvtqq2ps %xmm16, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtqq2psx (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtqq2ps (%rax){1to2}, %xmm19
+# CHECK-NEXT: 2 5 1.00 vcvtqq2ps %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtqq2psx (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvtqq2ps (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvtqq2ps %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtqq2psx (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtqq2ps (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvtqq2ps %ymm16, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtqq2psx (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtqq2ps (%rax){1to4}, %xmm19
+# CHECK-NEXT: 2 5 1.00 vcvtqq2ps %ymm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtqq2psx (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvtqq2ps (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvtqq2ps %ymm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtqq2psx (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtqq2ps (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 2 4 1.00 vcvttpd2qq %xmm16, %xmm19
+# CHECK-NEXT: 2 11 1.00 * vcvttpd2qq (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2qq (%rax){1to2}, %xmm19
+# CHECK-NEXT: 2 5 1.00 vcvttpd2qq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvttpd2qq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2qq (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: 2 4 1.00 vcvttpd2qq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vcvttpd2qq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2qq (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 2 4 1.00 vcvttpd2qq %ymm16, %ymm19
+# CHECK-NEXT: 2 11 1.00 * vcvttpd2qq (%rax), %ymm19
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2qq (%rax){1to4}, %ymm19
+# CHECK-NEXT: 2 5 1.00 vcvttpd2qq %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvttpd2qq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2qq (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: 2 4 1.00 vcvttpd2qq %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vcvttpd2qq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2qq (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 4 1.00 vcvttpd2uqq %xmm16, %xmm19
+# CHECK-NEXT: 2 11 1.00 * vcvttpd2uqq (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2uqq (%rax){1to2}, %xmm19
+# CHECK-NEXT: 2 5 1.00 vcvttpd2uqq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvttpd2uqq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2uqq (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: 2 4 1.00 vcvttpd2uqq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vcvttpd2uqq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2uqq (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 2 4 1.00 vcvttpd2uqq %ymm16, %ymm19
+# CHECK-NEXT: 2 11 1.00 * vcvttpd2uqq (%rax), %ymm19
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2uqq (%rax){1to4}, %ymm19
+# CHECK-NEXT: 2 5 1.00 vcvttpd2uqq %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvttpd2uqq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2uqq (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: 2 4 1.00 vcvttpd2uqq %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 11 1.00 * vcvttpd2uqq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2uqq (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvttps2qq %xmm16, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvttps2qq (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvttps2qq (%rax){1to2}, %xmm19
+# CHECK-NEXT: 2 5 1.00 vcvttps2qq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvttps2qq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvttps2qq (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvttps2qq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvttps2qq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvttps2qq (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvttps2qq %xmm16, %ymm19
+# CHECK-NEXT: 1 11 0.50 * vcvttps2qq (%rax), %ymm19
+# CHECK-NEXT: 1 11 0.50 * vcvttps2qq (%rax){1to4}, %ymm19
+# CHECK-NEXT: 2 5 1.00 vcvttps2qq %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvttps2qq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvttps2qq (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvttps2qq %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvttps2qq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvttps2qq (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvttps2uqq %xmm16, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvttps2uqq (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvttps2uqq (%rax){1to2}, %xmm19
+# CHECK-NEXT: 2 5 1.00 vcvttps2uqq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvttps2uqq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvttps2uqq (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvttps2uqq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvttps2uqq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvttps2uqq (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvttps2uqq %xmm16, %ymm19
+# CHECK-NEXT: 1 11 0.50 * vcvttps2uqq (%rax), %ymm19
+# CHECK-NEXT: 1 11 0.50 * vcvttps2uqq (%rax){1to4}, %ymm19
+# CHECK-NEXT: 2 5 1.00 vcvttps2uqq %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvttps2uqq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvttps2uqq (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvttps2uqq %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvttps2uqq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvttps2uqq (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvtuqq2pd %xmm16, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtuqq2pd (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtuqq2pd (%rax){1to2}, %xmm19
+# CHECK-NEXT: 2 5 1.00 vcvtuqq2pd %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtuqq2pd (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvtuqq2pd (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvtuqq2pd %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtuqq2pd (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtuqq2pd (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvtuqq2pd %ymm16, %ymm19
+# CHECK-NEXT: 1 11 0.50 * vcvtuqq2pd (%rax), %ymm19
+# CHECK-NEXT: 1 11 0.50 * vcvtuqq2pd (%rax){1to4}, %ymm19
+# CHECK-NEXT: 2 5 1.00 vcvtuqq2pd %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtuqq2pd (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvtuqq2pd (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvtuqq2pd %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtuqq2pd (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtuqq2pd (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvtuqq2ps %xmm16, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtuqq2psx (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtuqq2ps (%rax){1to2}, %xmm19
+# CHECK-NEXT: 2 5 1.00 vcvtuqq2ps %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtuqq2psx (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvtuqq2ps (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvtuqq2ps %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtuqq2psx (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtuqq2ps (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvtuqq2ps %ymm16, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtuqq2psx (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtuqq2ps (%rax){1to4}, %xmm19
+# CHECK-NEXT: 2 5 1.00 vcvtuqq2ps %ymm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtuqq2psx (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvtuqq2ps (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvtuqq2ps %ymm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtuqq2psx (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtuqq2ps (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vextractf64x2 $1, %ymm16, %xmm19
+# CHECK-NEXT: 1 1 0.33 vextractf64x2 $1, %ymm16, (%rax)
+# CHECK-NEXT: 1 4 2.00 vextractf64x2 $1, %ymm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 5 2.00 * vextractf64x2 $1, %ymm16, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vextractf64x2 $1, %ymm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vextracti64x2 $1, %ymm16, %xmm19
+# CHECK-NEXT: 1 1 0.33 vextracti64x2 $1, %ymm16, (%rax)
+# CHECK-NEXT: 1 4 2.00 vextracti64x2 $1, %ymm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 5 2.00 * vextracti64x2 $1, %ymm16, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vextracti64x2 $1, %ymm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vfpclasspd $171, %xmm16, %k1
+# CHECK-NEXT: 1 8 0.50 * vfpclasspdx $171, (%rax), %k1
+# CHECK-NEXT: 1 8 0.50 * vfpclasspd $171, (%rax){1to2}, %k1
+# CHECK-NEXT: 2 5 2.00 vfpclasspd $171, %xmm16, %k1 {%k2}
+# CHECK-NEXT: 2 12 2.00 * vfpclasspdx $171, (%rax), %k1 {%k2}
+# CHECK-NEXT: 1 8 0.50 * vfpclasspd $171, (%rax){1to2}, %k1 {%k2}
+# CHECK-NEXT: 1 1 0.50 vfpclasspd $171, %ymm16, %k1
+# CHECK-NEXT: 1 8 0.50 * vfpclasspdy $171, (%rax), %k1
+# CHECK-NEXT: 1 8 0.50 * vfpclasspd $171, (%rax){1to4}, %k1
+# CHECK-NEXT: 2 5 2.00 vfpclasspd $171, %ymm16, %k1 {%k2}
+# CHECK-NEXT: 2 12 2.00 * vfpclasspdy $171, (%rax), %k1 {%k2}
+# CHECK-NEXT: 1 8 0.50 * vfpclasspd $171, (%rax){1to4}, %k1 {%k2}
+# CHECK-NEXT: 1 1 0.50 vfpclassps $171, %xmm16, %k1
+# CHECK-NEXT: 1 8 0.50 * vfpclasspsx $171, (%rax), %k1
+# CHECK-NEXT: 1 8 0.50 * vfpclassps $171, (%rax){1to4}, %k1
+# CHECK-NEXT: 2 5 2.00 vfpclassps $171, %xmm16, %k1 {%k2}
+# CHECK-NEXT: 2 12 2.00 * vfpclasspsx $171, (%rax), %k1 {%k2}
+# CHECK-NEXT: 1 8 0.50 * vfpclassps $171, (%rax){1to4}, %k1 {%k2}
+# CHECK-NEXT: 1 1 0.50 vfpclassps $171, %ymm16, %k1
+# CHECK-NEXT: 1 8 0.50 * vfpclasspsy $171, (%rax), %k1
+# CHECK-NEXT: 1 8 0.50 * vfpclassps $171, (%rax){1to8}, %k1
+# CHECK-NEXT: 2 5 2.00 vfpclassps $171, %ymm16, %k1 {%k2}
+# CHECK-NEXT: 2 12 2.00 * vfpclasspsy $171, (%rax), %k1 {%k2}
+# CHECK-NEXT: 1 8 0.50 * vfpclassps $171, (%rax){1to8}, %k1 {%k2}
+# CHECK-NEXT: 1 3 0.50 vinsertf64x2 $1, %xmm16, %ymm16, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vinsertf64x2 $1, (%rax), %ymm16, %ymm19
+# CHECK-NEXT: 1 4 4.00 vinsertf64x2 $1, %xmm16, %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 4.00 * vinsertf64x2 $1, (%rax), %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 4 4.00 vinsertf64x2 $1, %xmm16, %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 4.00 * vinsertf64x2 $1, (%rax), %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vinserti64x2 $1, %xmm16, %ymm16, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vinserti64x2 $1, (%rax), %ymm16, %ymm19
+# CHECK-NEXT: 1 4 4.00 vinserti64x2 $1, %xmm16, %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 4.00 * vinserti64x2 $1, (%rax), %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 4 4.00 vinserti64x2 $1, %xmm16, %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 4.00 * vinserti64x2 $1, (%rax), %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 0 0.25 vpmovm2d %k0, %xmm0
+# CHECK-NEXT: 1 0 0.25 vpmovm2q %k0, %xmm0
+# CHECK-NEXT: 1 0 0.25 vpmovm2d %k0, %ymm0
+# CHECK-NEXT: 1 0 0.25 vpmovm2q %k0, %ymm0
+# CHECK-NEXT: 1 1 1.00 vpmovd2m %xmm0, %k0
+# CHECK-NEXT: 1 1 1.00 vpmovq2m %xmm0, %k0
+# CHECK-NEXT: 1 1 1.00 vpmovd2m %ymm0, %k0
+# CHECK-NEXT: 1 1 1.00 vpmovq2m %ymm0, %k0
+# CHECK-NEXT: 1 1 0.25 vorpd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vorpd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vorpd (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: 2 2 0.50 vorpd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 2 9 0.50 * vorpd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vorpd (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vorpd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vorpd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vorpd (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vorpd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vorpd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vorpd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 2 2 0.50 vorpd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 2 9 0.50 * vorpd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vorpd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vorpd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vorpd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vorpd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vorps %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vorps (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vorps (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: 2 2 0.50 vorps %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 2 9 0.50 * vorps (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vorps (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vorps %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vorps (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vorps (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vorps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vorps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vorps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 2 2 0.50 vorps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 2 9 0.50 * vorps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vorps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vorps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vorps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vorps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 4 1.00 vpmullq %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 11 1.00 * vpmullq (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 5 1.00 vpmullq %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 12 1.00 * vpmullq (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 1.00 vpmullq %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 1.00 * vpmullq (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 1.00 vpmullq %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 11 1.00 * vpmullq (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 5 1.00 vpmullq %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 12 1.00 * vpmullq (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 4 1.00 vpmullq %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 1.00 * vpmullq (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vrangepd $ab, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vrangepd $ab, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vrangepd $ab, (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vrangepd $ab, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vrangepd $ab, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vrangepd $ab, (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vrangepd $ab, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vrangepd $ab, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vrangepd $ab, (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vrangepd $ab, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vrangepd $ab, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vrangepd $ab, (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vrangepd $ab, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vrangepd $ab, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vrangepd $ab, (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vrangepd $ab, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vrangepd $ab, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vrangepd $ab, (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vrangeps $ab, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vrangeps $ab, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vrangeps $ab, (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vrangeps $ab, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vrangeps $ab, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vrangeps $ab, (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vrangeps $ab, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vrangeps $ab, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vrangeps $ab, (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vrangeps $ab, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vrangeps $ab, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vrangeps $ab, (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vrangeps $ab, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vrangeps $ab, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vrangeps $ab, (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vrangeps $ab, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vrangeps $ab, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vrangeps $ab, (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vreducepd $ab, %xmm16, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vreducepd $ab, (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vreducepd $ab, (%rax){1to2}, %xmm19
+# CHECK-NEXT: 1 5 0.50 vreducepd $ab, %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 12 0.50 * vreducepd $ab, (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vreducepd $ab, (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vreducepd $ab, %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vreducepd $ab, (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vreducepd $ab, (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vreducepd $ab, %ymm16, %ymm19
+# CHECK-NEXT: 1 11 0.50 * vreducepd $ab, (%rax), %ymm19
+# CHECK-NEXT: 1 11 0.50 * vreducepd $ab, (%rax){1to4}, %ymm19
+# CHECK-NEXT: 1 5 0.50 vreducepd $ab, %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 12 0.50 * vreducepd $ab, (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vreducepd $ab, (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vreducepd $ab, %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vreducepd $ab, (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vreducepd $ab, (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vreduceps $ab, %xmm16, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vreduceps $ab, (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vreduceps $ab, (%rax){1to4}, %xmm19
+# CHECK-NEXT: 1 5 0.50 vreduceps $ab, %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 12 0.50 * vreduceps $ab, (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vreduceps $ab, (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vreduceps $ab, %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vreduceps $ab, (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vreduceps $ab, (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vreduceps $ab, %ymm16, %ymm19
+# CHECK-NEXT: 1 11 0.50 * vreduceps $ab, (%rax), %ymm19
+# CHECK-NEXT: 1 11 0.50 * vreduceps $ab, (%rax){1to8}, %ymm19
+# CHECK-NEXT: 1 5 0.50 vreduceps $ab, %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 12 0.50 * vreduceps $ab, (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vreduceps $ab, (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vreduceps $ab, %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vreduceps $ab, (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vreduceps $ab, (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vxorpd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vxorpd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vxorpd (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: 2 2 0.50 vxorpd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 2 9 0.50 * vxorpd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vxorpd (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vxorpd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vxorpd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vxorpd (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vxorpd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vxorpd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vxorpd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 2 2 0.50 vxorpd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 2 9 0.50 * vxorpd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vxorpd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vxorpd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vxorpd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vxorpd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vxorps %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vxorps (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vxorps (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: 2 2 0.50 vxorps %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 2 9 0.50 * vxorps (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vxorps (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vxorps %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vxorps (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vxorps (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vxorps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vxorps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vxorps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 2 2 0.50 vxorps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 2 9 0.50 * vxorps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vxorps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vxorps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vxorps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vxorps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 111.67 111.67 111.67 4.00 4.00 4.00 4.00 - 132.00 244.00 126.00 238.00 83.75 83.75 83.75 83.75 110.33 110.33 110.33 1.00 1.00 1.00 1.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandnpd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnpd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnpd (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vandnpd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnpd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnpd (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandnpd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnpd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnpd (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandnpd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnpd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnpd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vandnpd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnpd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnpd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandnpd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnpd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnpd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandnps %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnps (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnps (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vandnps %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnps (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnps (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandnps %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnps (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnps (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandnps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vandnps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandnps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandnps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandpd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandpd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandpd (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vandpd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandpd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandpd (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandpd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandpd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandpd (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandpd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandpd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandpd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vandpd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandpd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandpd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandpd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandpd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandpd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandps %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandps (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandps (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vandps %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandps (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandps (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandps %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandps (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandps (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vandps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vandps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vandps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vbroadcastf32x2 %xmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastf32x2 (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vbroadcastf32x2 %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastf32x2 (%rax), %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vbroadcastf32x2 %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastf32x2 (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastf64x2 (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastf64x2 (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastf64x2 (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vbroadcasti32x2 %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcasti32x2 (%rax), %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vbroadcasti32x2 %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcasti32x2 (%rax), %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vbroadcasti32x2 %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcasti32x2 (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vbroadcasti32x2 %xmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcasti32x2 (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vbroadcasti32x2 %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcasti32x2 (%rax), %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vbroadcasti32x2 %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcasti32x2 (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcasti64x2 (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcasti64x2 (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcasti64x2 (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2qq %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2qq (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2qq (%rax){1to2}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2qq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2qq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2qq (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2qq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2qq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2qq (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2qq %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2qq (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2qq (%rax){1to4}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2qq %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2qq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2qq (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2qq %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2qq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2qq (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2uqq %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2uqq (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2uqq (%rax){1to2}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2uqq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2uqq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2uqq (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2uqq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2uqq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2uqq (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2uqq %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2uqq (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2uqq (%rax){1to4}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2uqq %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2uqq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2uqq (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2uqq %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2uqq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2uqq (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtps2qq %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2qq (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2qq (%rax){1to2}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtps2qq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2qq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2qq (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtps2qq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2qq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2qq (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtps2qq %xmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2qq (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2qq (%rax){1to4}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtps2qq %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2qq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2qq (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtps2qq %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2qq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2qq (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtps2uqq %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2uqq (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2uqq (%rax){1to2}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtps2uqq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2uqq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2uqq (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtps2uqq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2uqq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2uqq (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtps2uqq %xmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2uqq (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2uqq (%rax){1to4}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtps2uqq %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2uqq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2uqq (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtps2uqq %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2uqq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2uqq (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtqq2pd %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2pd (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2pd (%rax){1to2}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtqq2pd %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2pd (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2pd (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtqq2pd %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2pd (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2pd (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtqq2pd %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2pd (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2pd (%rax){1to4}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtqq2pd %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2pd (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2pd (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtqq2pd %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2pd (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2pd (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtqq2ps %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2psx (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2ps (%rax){1to2}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtqq2ps %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2psx (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2ps (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtqq2ps %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2psx (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2ps (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtqq2ps %ymm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2psx (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2ps (%rax){1to4}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtqq2ps %ymm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2psx (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2ps (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtqq2ps %ymm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2psx (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtqq2ps (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttpd2qq %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2qq (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2qq (%rax){1to2}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttpd2qq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2qq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2qq (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttpd2qq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2qq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2qq (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttpd2qq %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2qq (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2qq (%rax){1to4}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttpd2qq %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2qq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2qq (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttpd2qq %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2qq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2qq (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttpd2uqq %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2uqq (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2uqq (%rax){1to2}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttpd2uqq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2uqq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2uqq (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttpd2uqq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2uqq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2uqq (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttpd2uqq %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2uqq (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2uqq (%rax){1to4}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttpd2uqq %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2uqq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2uqq (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttpd2uqq %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2uqq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2uqq (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvttps2qq %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2qq (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2qq (%rax){1to2}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttps2qq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2qq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2qq (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvttps2qq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2qq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2qq (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvttps2qq %xmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2qq (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2qq (%rax){1to4}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttps2qq %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2qq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2qq (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvttps2qq %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2qq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2qq (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvttps2uqq %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2uqq (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2uqq (%rax){1to2}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttps2uqq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2uqq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2uqq (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvttps2uqq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2uqq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2uqq (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvttps2uqq %xmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2uqq (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2uqq (%rax){1to4}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttps2uqq %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2uqq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2uqq (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvttps2uqq %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2uqq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2uqq (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtuqq2pd %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2pd (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2pd (%rax){1to2}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtuqq2pd %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2pd (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2pd (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtuqq2pd %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2pd (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2pd (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtuqq2pd %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2pd (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2pd (%rax){1to4}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtuqq2pd %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2pd (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2pd (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtuqq2pd %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2pd (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2pd (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtuqq2ps %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2psx (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2ps (%rax){1to2}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtuqq2ps %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2psx (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2ps (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtuqq2ps %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2psx (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2ps (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtuqq2ps %ymm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2psx (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2ps (%rax){1to4}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtuqq2ps %ymm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2psx (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2ps (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtuqq2ps %ymm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2psx (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtuqq2ps (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vextractf64x2 $1, %ymm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vextractf64x2 $1, %ymm16, (%rax)
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vextractf64x2 $1, %ymm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vextractf64x2 $1, %ymm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vextractf64x2 $1, %ymm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vextracti64x2 $1, %ymm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vextracti64x2 $1, %ymm16, (%rax)
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vextracti64x2 $1, %ymm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vextracti64x2 $1, %ymm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vextracti64x2 $1, %ymm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfpclasspd $171, %xmm16, %k1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfpclasspdx $171, (%rax), %k1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfpclasspd $171, (%rax){1to2}, %k1
+# CHECK-NEXT: - - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - vfpclasspd $171, %xmm16, %k1 {%k2}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 2.00 - 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfpclasspdx $171, (%rax), %k1 {%k2}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfpclasspd $171, (%rax){1to2}, %k1 {%k2}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfpclasspd $171, %ymm16, %k1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfpclasspdy $171, (%rax), %k1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfpclasspd $171, (%rax){1to4}, %k1
+# CHECK-NEXT: - - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - vfpclasspd $171, %ymm16, %k1 {%k2}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 2.00 - 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfpclasspdy $171, (%rax), %k1 {%k2}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfpclasspd $171, (%rax){1to4}, %k1 {%k2}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfpclassps $171, %xmm16, %k1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfpclasspsx $171, (%rax), %k1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfpclassps $171, (%rax){1to4}, %k1
+# CHECK-NEXT: - - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - vfpclassps $171, %xmm16, %k1 {%k2}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 2.00 - 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfpclasspsx $171, (%rax), %k1 {%k2}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfpclassps $171, (%rax){1to4}, %k1 {%k2}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfpclassps $171, %ymm16, %k1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfpclasspsy $171, (%rax), %k1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfpclassps $171, (%rax){1to8}, %k1
+# CHECK-NEXT: - - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - vfpclassps $171, %ymm16, %k1 {%k2}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 2.00 - 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfpclasspsy $171, (%rax), %k1 {%k2}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfpclassps $171, (%rax){1to8}, %k1 {%k2}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vinsertf64x2 $1, %xmm16, %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vinsertf64x2 $1, (%rax), %ymm16, %ymm19
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vinsertf64x2 $1, %xmm16, %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vinsertf64x2 $1, (%rax), %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vinsertf64x2 $1, %xmm16, %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vinsertf64x2 $1, (%rax), %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vinserti64x2 $1, %xmm16, %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vinserti64x2 $1, (%rax), %ymm16, %ymm19
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vinserti64x2 $1, %xmm16, %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vinserti64x2 $1, (%rax), %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vinserti64x2 $1, %xmm16, %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vinserti64x2 $1, (%rax), %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpmovm2d %k0, %xmm0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpmovm2q %k0, %xmm0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpmovm2d %k0, %ymm0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpmovm2q %k0, %ymm0
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - vpmovd2m %xmm0, %k0
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - vpmovq2m %xmm0, %k0
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - vpmovd2m %ymm0, %k0
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - vpmovq2m %ymm0, %k0
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vorpd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorpd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorpd (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vorpd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorpd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorpd (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vorpd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorpd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorpd (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vorpd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorpd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorpd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vorpd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorpd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorpd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vorpd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorpd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorpd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vorps %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorps (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorps (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vorps %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorps (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorps (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vorps %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorps (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorps (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vorps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vorps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vorps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vorps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmullq %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmullq (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmullq %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmullq (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmullq %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmullq (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmullq %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmullq (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmullq %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmullq (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmullq %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmullq (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vrangepd $ab, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangepd $ab, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangepd $ab, (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vrangepd $ab, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangepd $ab, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangepd $ab, (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vrangepd $ab, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangepd $ab, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangepd $ab, (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vrangepd $ab, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangepd $ab, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangepd $ab, (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vrangepd $ab, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangepd $ab, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangepd $ab, (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vrangepd $ab, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangepd $ab, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangepd $ab, (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vrangeps $ab, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangeps $ab, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangeps $ab, (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vrangeps $ab, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangeps $ab, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangeps $ab, (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vrangeps $ab, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangeps $ab, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangeps $ab, (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vrangeps $ab, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangeps $ab, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangeps $ab, (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vrangeps $ab, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangeps $ab, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangeps $ab, (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vrangeps $ab, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangeps $ab, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vrangeps $ab, (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vreducepd $ab, %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreducepd $ab, (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreducepd $ab, (%rax){1to2}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vreducepd $ab, %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreducepd $ab, (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreducepd $ab, (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vreducepd $ab, %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreducepd $ab, (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreducepd $ab, (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vreducepd $ab, %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreducepd $ab, (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreducepd $ab, (%rax){1to4}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vreducepd $ab, %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreducepd $ab, (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreducepd $ab, (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vreducepd $ab, %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreducepd $ab, (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreducepd $ab, (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vreduceps $ab, %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreduceps $ab, (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreduceps $ab, (%rax){1to4}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vreduceps $ab, %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreduceps $ab, (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreduceps $ab, (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vreduceps $ab, %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreduceps $ab, (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreduceps $ab, (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vreduceps $ab, %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreduceps $ab, (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreduceps $ab, (%rax){1to8}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vreduceps $ab, %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreduceps $ab, (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreduceps $ab, (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vreduceps $ab, %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreduceps $ab, (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vreduceps $ab, (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vxorpd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorpd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorpd (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vxorpd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorpd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorpd (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vxorpd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorpd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorpd (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vxorpd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorpd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorpd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vxorpd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorpd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorpd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vxorpd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorpd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorpd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vxorps %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorps (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorps (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vxorps %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorps (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorps (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vxorps %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorps (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorps (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vxorps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vxorps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vxorps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vxorps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512gfni.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512gfni.s
new file mode 100644
index 0000000000000..2e011ea7eb66e
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512gfni.s
@@ -0,0 +1,119 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+vgf2p8affineinvqb $0, %zmm16, %zmm17, %zmm19
+vgf2p8affineinvqb $0, (%rax), %zmm17, %zmm19
+vgf2p8affineinvqb $0, (%rax){1to8}, %zmm17, %zmm19
+vgf2p8affineinvqb $0, %zmm16, %zmm17, %zmm19 {k1}
+vgf2p8affineinvqb $0, (%rax), %zmm17, %zmm19 {k1}
+vgf2p8affineinvqb $0, (%rax){1to8}, %zmm17, %zmm19 {k1}
+vgf2p8affineinvqb $0, %zmm16, %zmm17, %zmm19 {z}{k1}
+vgf2p8affineinvqb $0, (%rax), %zmm17, %zmm19 {z}{k1}
+vgf2p8affineinvqb $0, (%rax){1to8}, %zmm17, %zmm19 {z}{k1}
+
+vgf2p8affineqb $0, %zmm16, %zmm17, %zmm19
+vgf2p8affineqb $0, (%rax), %zmm17, %zmm19
+vgf2p8affineqb $0, (%rax){1to8}, %zmm17, %zmm19
+vgf2p8affineqb $0, %zmm16, %zmm17, %zmm19
+vgf2p8affineqb $0, (%rax), %zmm17, %zmm19
+vgf2p8affineqb $0, (%rax){1to8}, %zmm17, %zmm19
+vgf2p8affineqb $0, %zmm16, %zmm17, %zmm19 {z}{k1}
+vgf2p8affineqb $0, (%rax), %zmm17, %zmm19 {z}{k1}
+vgf2p8affineqb $0, (%rax){1to8}, %zmm17, %zmm19 {z}{k1}
+
+vgf2p8mulb %zmm16, %zmm17, %zmm19
+vgf2p8mulb (%rax), %zmm17, %zmm19
+vgf2p8mulb %zmm16, %zmm17, %zmm19 {k1}
+vgf2p8mulb (%rax), %zmm17, %zmm19 {k1}
+vgf2p8mulb %zmm16, %zmm17, %zmm19 {z}{k1}
+vgf2p8mulb (%rax), %zmm17, %zmm19 {z}{k1}
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 1.00 vgf2p8affineinvqb $0, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vgf2p8affineinvqb $0, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vgf2p8affineinvqb $0, (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 2 4 1.00 vgf2p8affineinvqb $0, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 11 1.00 * vgf2p8affineinvqb $0, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 1.00 * vgf2p8affineinvqb $0, (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 3 1.00 vgf2p8affineinvqb $0, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vgf2p8affineinvqb $0, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vgf2p8affineinvqb $0, (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 1.00 vgf2p8affineqb $0, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vgf2p8affineqb $0, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vgf2p8affineqb $0, (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 1 3 1.00 vgf2p8affineqb $0, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vgf2p8affineqb $0, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vgf2p8affineqb $0, (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 1 3 1.00 vgf2p8affineqb $0, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vgf2p8affineqb $0, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vgf2p8affineqb $0, (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 3 1.00 vgf2p8mulb %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 2 10 1.00 * vgf2p8mulb (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 2 4 1.00 vgf2p8mulb %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 11 1.00 * vgf2p8mulb (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 2 3 1.00 vgf2p8mulb %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 2 10 1.00 * vgf2p8mulb (%rax), %zmm17, %zmm19 {%k1} {z}
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 5.00 5.00 5.00 - - - - - 16.00 8.00 16.00 8.00 3.75 3.75 3.75 3.75 5.00 5.00 5.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vgf2p8affineinvqb $0, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineinvqb $0, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineinvqb $0, (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vgf2p8affineinvqb $0, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineinvqb $0, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineinvqb $0, (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vgf2p8affineinvqb $0, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineinvqb $0, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineinvqb $0, (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vgf2p8affineqb $0, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineqb $0, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineqb $0, (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vgf2p8affineqb $0, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineqb $0, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineqb $0, (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vgf2p8affineqb $0, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineqb $0, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineqb $0, (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vgf2p8mulb %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8mulb (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vgf2p8mulb %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8mulb (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vgf2p8mulb %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8mulb (%rax), %zmm17, %zmm19 {%k1} {z}
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512gfnivl.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512gfnivl.s
new file mode 100644
index 0000000000000..35185f58fbb4f
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512gfnivl.s
@@ -0,0 +1,194 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+vgf2p8affineinvqb $0, %xmm16, %xmm17, %xmm19
+vgf2p8affineinvqb $0, (%rax), %xmm17, %xmm19
+vgf2p8affineinvqb $0, (%rax){1to2}, %xmm17, %xmm19
+vgf2p8affineinvqb $0, %xmm16, %xmm17, %xmm19 {k1}
+vgf2p8affineinvqb $0, (%rax), %xmm17, %xmm19 {k1}
+vgf2p8affineinvqb $0, (%rax){1to2}, %xmm17, %xmm19 {k1}
+vgf2p8affineinvqb $0, %xmm16, %xmm17, %xmm19 {z}{k1}
+vgf2p8affineinvqb $0, (%rax), %xmm17, %xmm19 {z}{k1}
+vgf2p8affineinvqb $0, (%rax){1to2}, %xmm17, %xmm19 {z}{k1}
+
+vgf2p8affineinvqb $0, %ymm16, %ymm17, %ymm19
+vgf2p8affineinvqb $0, (%rax), %ymm17, %ymm19
+vgf2p8affineinvqb $0, (%rax){1to4}, %ymm17, %ymm19
+vgf2p8affineinvqb $0, %ymm16, %ymm17, %ymm19 {k1}
+vgf2p8affineinvqb $0, (%rax), %ymm17, %ymm19 {k1}
+vgf2p8affineinvqb $0, (%rax){1to4}, %ymm17, %ymm19 {k1}
+vgf2p8affineinvqb $0, %ymm16, %ymm17, %ymm19 {z}{k1}
+vgf2p8affineinvqb $0, (%rax), %ymm17, %ymm19 {z}{k1}
+vgf2p8affineinvqb $0, (%rax){1to4}, %ymm17, %ymm19 {z}{k1}
+
+vgf2p8affineqb $0, %xmm16, %xmm17, %xmm19
+vgf2p8affineqb $0, (%rax), %xmm17, %xmm19
+vgf2p8affineqb $0, (%rax){1to2}, %xmm17, %xmm19
+vgf2p8affineqb $0, %xmm16, %xmm17, %xmm19
+vgf2p8affineqb $0, (%rax), %xmm17, %xmm19
+vgf2p8affineqb $0, (%rax){1to2}, %xmm17, %xmm19
+vgf2p8affineqb $0, %xmm16, %xmm17, %xmm19 {z}{k1}
+vgf2p8affineqb $0, (%rax), %xmm17, %xmm19 {z}{k1}
+vgf2p8affineqb $0, (%rax){1to2}, %xmm17, %xmm19 {z}{k1}
+
+vgf2p8affineqb $0, %ymm16, %ymm17, %ymm19
+vgf2p8affineqb $0, (%rax), %ymm17, %ymm19
+vgf2p8affineqb $0, (%rax){1to4}, %ymm17, %ymm19
+vgf2p8affineqb $0, %ymm16, %ymm17, %ymm19
+vgf2p8affineqb $0, (%rax), %ymm17, %ymm19
+vgf2p8affineqb $0, (%rax){1to4}, %ymm17, %ymm19
+vgf2p8affineqb $0, %ymm16, %ymm17, %ymm19 {z}{k1}
+vgf2p8affineqb $0, (%rax), %ymm17, %ymm19 {z}{k1}
+vgf2p8affineqb $0, (%rax){1to4}, %ymm17, %ymm19 {z}{k1}
+
+vgf2p8mulb %xmm16, %xmm17, %xmm19
+vgf2p8mulb (%rax), %xmm17, %xmm19
+vgf2p8mulb %xmm16, %xmm17, %xmm19 {k1}
+vgf2p8mulb (%rax), %xmm17, %xmm19 {k1}
+vgf2p8mulb %xmm16, %xmm17, %xmm19 {z}{k1}
+vgf2p8mulb (%rax), %xmm17, %xmm19 {z}{k1}
+
+vgf2p8mulb %ymm16, %ymm17, %ymm19
+vgf2p8mulb (%rax), %ymm17, %ymm19
+vgf2p8mulb %ymm16, %ymm17, %ymm19 {k1}
+vgf2p8mulb (%rax), %ymm17, %ymm19 {k1}
+vgf2p8mulb %ymm16, %ymm17, %ymm19 {z}{k1}
+vgf2p8mulb (%rax), %ymm17, %ymm19 {z}{k1}
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 vgf2p8affineinvqb $0, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vgf2p8affineinvqb $0, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vgf2p8affineinvqb $0, (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: 2 4 1.00 vgf2p8affineinvqb $0, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 2 11 1.00 * vgf2p8affineinvqb $0, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vgf2p8affineinvqb $0, (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vgf2p8affineinvqb $0, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vgf2p8affineinvqb $0, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vgf2p8affineinvqb $0, (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vgf2p8affineinvqb $0, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vgf2p8affineinvqb $0, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vgf2p8affineinvqb $0, (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 2 4 1.00 vgf2p8affineinvqb $0, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 2 11 1.00 * vgf2p8affineinvqb $0, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vgf2p8affineinvqb $0, (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vgf2p8affineinvqb $0, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vgf2p8affineinvqb $0, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vgf2p8affineinvqb $0, (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vgf2p8affineqb $0, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vgf2p8affineqb $0, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vgf2p8affineqb $0, (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: 1 3 0.50 vgf2p8affineqb $0, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vgf2p8affineqb $0, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vgf2p8affineqb $0, (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: 1 3 0.50 vgf2p8affineqb $0, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vgf2p8affineqb $0, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vgf2p8affineqb $0, (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vgf2p8affineqb $0, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vgf2p8affineqb $0, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vgf2p8affineqb $0, (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 1 3 0.50 vgf2p8affineqb $0, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vgf2p8affineqb $0, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vgf2p8affineqb $0, (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 1 3 0.50 vgf2p8affineqb $0, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vgf2p8affineqb $0, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vgf2p8affineqb $0, (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 3 1.00 vgf2p8mulb %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 2 10 1.00 * vgf2p8mulb (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 2 4 1.00 vgf2p8mulb %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 2 11 1.00 * vgf2p8mulb (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 2 3 1.00 vgf2p8mulb %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 2 10 1.00 * vgf2p8mulb (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 2 3 1.00 vgf2p8mulb %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 2 10 1.00 * vgf2p8mulb (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 2 4 1.00 vgf2p8mulb %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 2 11 1.00 * vgf2p8mulb (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 2 3 1.00 vgf2p8mulb %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 10 1.00 * vgf2p8mulb (%rax), %ymm17, %ymm19 {%k1} {z}
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 10.00 10.00 10.00 - - - - - 16.00 16.00 16.00 16.00 7.50 7.50 7.50 7.50 10.00 10.00 10.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vgf2p8affineinvqb $0, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineinvqb $0, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineinvqb $0, (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vgf2p8affineinvqb $0, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineinvqb $0, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineinvqb $0, (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vgf2p8affineinvqb $0, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineinvqb $0, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineinvqb $0, (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vgf2p8affineinvqb $0, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineinvqb $0, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineinvqb $0, (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vgf2p8affineinvqb $0, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineinvqb $0, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineinvqb $0, (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vgf2p8affineinvqb $0, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineinvqb $0, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineinvqb $0, (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vgf2p8affineqb $0, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineqb $0, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineqb $0, (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vgf2p8affineqb $0, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineqb $0, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineqb $0, (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vgf2p8affineqb $0, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineqb $0, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineqb $0, (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vgf2p8affineqb $0, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineqb $0, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineqb $0, (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vgf2p8affineqb $0, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineqb $0, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineqb $0, (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vgf2p8affineqb $0, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineqb $0, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineqb $0, (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vgf2p8mulb %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8mulb (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vgf2p8mulb %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8mulb (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vgf2p8mulb %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8mulb (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vgf2p8mulb %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8mulb (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vgf2p8mulb %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8mulb (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vgf2p8mulb %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8mulb (%rax), %ymm17, %ymm19 {%k1} {z}
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512ifma.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512ifma.s
new file mode 100644
index 0000000000000..94e562a6fae33
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512ifma.s
@@ -0,0 +1,100 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+vpmadd52huq %zmm16, %zmm17, %zmm19
+vpmadd52huq (%rdi), %zmm17, %zmm19
+vpmadd52huq (%rdi){1to8}, %zmm17, %zmm19
+vpmadd52huq %zmm16, %zmm17, %zmm19 {%k1}
+vpmadd52huq (%rdi), %zmm17, %zmm19 {%k1}
+vpmadd52huq (%rdi){1to8}, %zmm17, %zmm19 {%k1}
+vpmadd52huq %zmm16, %zmm17, %zmm19 {%k1} {z}
+vpmadd52huq (%rdi), %zmm17, %zmm19 {%k1} {z}
+vpmadd52huq (%rdi){1to8}, %zmm17, %zmm19 {%k1} {z}
+
+vpmadd52luq %zmm16, %zmm17, %zmm19
+vpmadd52luq (%rdi), %zmm17, %zmm19
+vpmadd52luq (%rdi){1to8}, %zmm17, %zmm19
+vpmadd52luq %zmm16, %zmm17, %zmm19 {%k1}
+vpmadd52luq (%rdi), %zmm17, %zmm19 {%k1}
+vpmadd52luq (%rdi){1to8}, %zmm17, %zmm19 {%k1}
+vpmadd52luq %zmm16, %zmm17, %zmm19 {%k1} {z}
+vpmadd52luq (%rdi), %zmm17, %zmm19 {%k1} {z}
+vpmadd52luq (%rdi){1to8}, %zmm17, %zmm19 {%k1} {z}
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 4 1.00 vpmadd52huq %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 11 1.00 * vpmadd52huq (%rdi), %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vpmadd52huq (%rdi){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 1 5 1.00 vpmadd52huq %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 12 1.00 * vpmadd52huq (%rdi), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 1.00 * vpmadd52huq (%rdi){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 4 1.00 vpmadd52huq %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 1.00 * vpmadd52huq (%rdi), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vpmadd52huq (%rdi){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 1.00 vpmadd52luq %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 11 1.00 * vpmadd52luq (%rdi), %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vpmadd52luq (%rdi){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 1 5 1.00 vpmadd52luq %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 12 1.00 * vpmadd52luq (%rdi), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 1.00 * vpmadd52luq (%rdi){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 4 1.00 vpmadd52luq %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 1.00 * vpmadd52luq (%rdi), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vpmadd52luq (%rdi){1to8}, %zmm17, %zmm19 {%k1} {z}
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 4.00 4.00 4.00 - - - - - 18.00 - 18.00 - 3.00 3.00 3.00 3.00 4.00 4.00 4.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmadd52huq %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52huq (%rdi), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52huq (%rdi){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmadd52huq %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52huq (%rdi), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52huq (%rdi){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmadd52huq %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52huq (%rdi), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52huq (%rdi){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmadd52luq %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52luq (%rdi), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52luq (%rdi){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmadd52luq %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52luq (%rdi), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52luq (%rdi){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmadd52luq %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52luq (%rdi), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52luq (%rdi){1to8}, %zmm17, %zmm19 {%k1} {z}
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512ifmavl.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512ifmavl.s
new file mode 100644
index 0000000000000..e906c7f7ab655
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512ifmavl.s
@@ -0,0 +1,156 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+vpmadd52huq %xmm16, %xmm17, %xmm19
+vpmadd52huq (%rdi), %xmm17, %xmm19
+vpmadd52huq (%rdi){1to2}, %xmm17, %xmm19
+vpmadd52huq %xmm16, %xmm17, %xmm19 {%k1}
+vpmadd52huq (%rdi), %xmm17, %xmm19 {%k1}
+vpmadd52huq (%rdi){1to2}, %xmm17, %xmm19 {%k1}
+vpmadd52huq %xmm16, %xmm17, %xmm19 {%k1} {z}
+vpmadd52huq (%rdi), %xmm17, %xmm19 {%k1} {z}
+vpmadd52huq (%rdi){1to2}, %xmm17, %xmm19 {%k1} {z}
+
+vpmadd52huq %ymm16, %ymm17, %ymm19
+vpmadd52huq (%rdi), %ymm17, %ymm19
+vpmadd52huq (%rdi){1to4}, %ymm17, %ymm19
+vpmadd52huq %ymm16, %ymm17, %ymm19 {%k1}
+vpmadd52huq (%rdi), %ymm17, %ymm19 {%k1}
+vpmadd52huq (%rdi){1to4}, %ymm17, %ymm19 {%k1}
+vpmadd52huq %ymm16, %ymm17, %ymm19 {%k1} {z}
+vpmadd52huq (%rdi), %ymm17, %ymm19 {%k1} {z}
+vpmadd52huq (%rdi){1to4}, %ymm17, %ymm19 {%k1} {z}
+
+vpmadd52luq %xmm16, %xmm17, %xmm19
+vpmadd52luq (%rdi), %xmm17, %xmm19
+vpmadd52luq (%rdi){1to2}, %xmm17, %xmm19
+vpmadd52luq %xmm16, %xmm17, %xmm19 {%k1}
+vpmadd52luq (%rdi), %xmm17, %xmm19 {%k1}
+vpmadd52luq (%rdi){1to2}, %xmm17, %xmm19 {%k1}
+vpmadd52luq %xmm16, %xmm17, %xmm19 {%k1} {z}
+vpmadd52luq (%rdi), %xmm17, %xmm19 {%k1} {z}
+vpmadd52luq (%rdi){1to2}, %xmm17, %xmm19 {%k1} {z}
+
+vpmadd52luq %ymm16, %ymm17, %ymm19
+vpmadd52luq (%rdi), %ymm17, %ymm19
+vpmadd52luq (%rdi){1to4}, %ymm17, %ymm19
+vpmadd52luq %ymm16, %ymm17, %ymm19 {%k1}
+vpmadd52luq (%rdi), %ymm17, %ymm19 {%k1}
+vpmadd52luq (%rdi){1to4}, %ymm17, %ymm19 {%k1}
+vpmadd52luq %ymm16, %ymm17, %ymm19 {%k1} {z}
+vpmadd52luq (%rdi), %ymm17, %ymm19 {%k1} {z}
+vpmadd52luq (%rdi){1to4}, %ymm17, %ymm19 {%k1} {z}
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 4 0.50 vpmadd52huq %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vpmadd52huq (%rdi), %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpmadd52huq (%rdi){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: 1 5 0.50 vpmadd52huq %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 12 0.50 * vpmadd52huq (%rdi), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmadd52huq (%rdi){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vpmadd52huq %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vpmadd52huq (%rdi), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmadd52huq (%rdi){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vpmadd52huq %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 11 0.50 * vpmadd52huq (%rdi), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpmadd52huq (%rdi){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 1 5 0.50 vpmadd52huq %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 12 0.50 * vpmadd52huq (%rdi), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmadd52huq (%rdi){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vpmadd52huq %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vpmadd52huq (%rdi), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmadd52huq (%rdi){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vpmadd52luq %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vpmadd52luq (%rdi), %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpmadd52luq (%rdi){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: 1 5 0.50 vpmadd52luq %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 12 0.50 * vpmadd52luq (%rdi), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmadd52luq (%rdi){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vpmadd52luq %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vpmadd52luq (%rdi), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmadd52luq (%rdi){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vpmadd52luq %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 11 0.50 * vpmadd52luq (%rdi), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpmadd52luq (%rdi){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 1 5 0.50 vpmadd52luq %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 12 0.50 * vpmadd52luq (%rdi), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmadd52luq (%rdi){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vpmadd52luq %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vpmadd52luq (%rdi), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmadd52luq (%rdi){1to4}, %ymm17, %ymm19 {%k1} {z}
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 8.00 8.00 8.00 - - - - - 18.00 - 18.00 - 6.00 6.00 6.00 6.00 8.00 8.00 8.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmadd52huq %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52huq (%rdi), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52huq (%rdi){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmadd52huq %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52huq (%rdi), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52huq (%rdi){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmadd52huq %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52huq (%rdi), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52huq (%rdi){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmadd52huq %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52huq (%rdi), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52huq (%rdi){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmadd52huq %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52huq (%rdi), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52huq (%rdi){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmadd52huq %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52huq (%rdi), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52huq (%rdi){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmadd52luq %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52luq (%rdi), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52luq (%rdi){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmadd52luq %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52luq (%rdi), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52luq (%rdi){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmadd52luq %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52luq (%rdi), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52luq (%rdi){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmadd52luq %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52luq (%rdi), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52luq (%rdi){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmadd52luq %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52luq (%rdi), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52luq (%rdi){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmadd52luq %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52luq (%rdi), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmadd52luq (%rdi){1to4}, %ymm17, %ymm19 {%k1} {z}
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vaes.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vaes.s
new file mode 100644
index 0000000000000..3a2e4fca0640e
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vaes.s
@@ -0,0 +1,72 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+vaesdec %zmm16, %zmm17, %zmm19
+vaesdec (%rax), %zmm17, %zmm19
+
+vaesdeclast %zmm16, %zmm17, %zmm19
+vaesdeclast (%rax), %zmm17, %zmm19
+
+vaesenc %zmm16, %zmm17, %zmm19
+vaesenc (%rax), %zmm17, %zmm19
+
+vaesenclast %zmm16, %zmm17, %zmm19
+vaesenclast (%rax), %zmm17, %zmm19
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 vaesdec %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 10 0.50 * vaesdec (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 3 0.50 vaesdeclast %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 10 0.50 * vaesdeclast (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 3 0.50 vaesenc %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 10 0.50 * vaesenc (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 3 0.50 vaesenclast %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 10 0.50 * vaesenclast (%rax), %zmm17, %zmm19
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 1.33 1.33 1.33 - - - - - - 4.00 - 4.00 1.00 1.00 1.00 1.00 1.33 1.33 1.33 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaesdec %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaesdec (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaesdeclast %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaesdeclast (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaesenc %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaesenc (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaesenclast %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaesenclast (%rax), %zmm17, %zmm19
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vaesvl.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vaesvl.s
new file mode 100644
index 0000000000000..2877300ccbf56
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vaesvl.s
@@ -0,0 +1,100 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+vaesdec %xmm16, %xmm17, %xmm19
+vaesdec (%rax), %xmm17, %xmm19
+
+vaesdec %ymm16, %ymm17, %ymm19
+vaesdec (%rax), %ymm17, %ymm19
+
+vaesdeclast %xmm16, %xmm17, %xmm19
+vaesdeclast (%rax), %xmm17, %xmm19
+
+vaesdeclast %ymm16, %ymm17, %ymm19
+vaesdeclast (%rax), %ymm17, %ymm19
+
+vaesenc %xmm16, %xmm17, %xmm19
+vaesenc (%rax), %xmm17, %xmm19
+
+vaesenc %ymm16, %ymm17, %ymm19
+vaesenc (%rax), %ymm17, %ymm19
+
+vaesenclast %xmm16, %xmm17, %xmm19
+vaesenclast (%rax), %xmm17, %xmm19
+
+vaesenclast %ymm16, %ymm17, %ymm19
+vaesenclast (%rax), %ymm17, %ymm19
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 vaesdec %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vaesdec (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 3 0.50 vaesdec %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vaesdec (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 3 0.50 vaesdeclast %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vaesdeclast (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 3 0.50 vaesdeclast %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vaesdeclast (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 3 0.50 vaesenc %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vaesenc (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 3 0.50 vaesenc %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vaesenc (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 3 0.50 vaesenclast %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vaesenclast (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 3 0.50 vaesenclast %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vaesenclast (%rax), %ymm17, %ymm19
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 2.67 2.67 2.67 - - - - - - 8.00 - 8.00 2.00 2.00 2.00 2.00 2.67 2.67 2.67 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaesdec %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaesdec (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaesdec %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaesdec (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaesdeclast %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaesdeclast (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaesdeclast %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaesdeclast (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaesenc %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaesenc (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaesenc %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaesenc (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaesenclast %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaesenclast (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaesenclast %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaesenclast (%rax), %ymm17, %ymm19
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmi.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmi.s
new file mode 100644
index 0000000000000..b4529c0b99e3c
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmi.s
@@ -0,0 +1,129 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+vpermb %zmm16, %zmm17, %zmm19
+vpermb (%rax), %zmm17, %zmm19
+vpermb %zmm16, %zmm17, %zmm19 {k1}
+vpermb (%rax), %zmm17, %zmm19 {k1}
+vpermb %zmm16, %zmm17, %zmm19 {k1}{z}
+vpermb (%rax), %zmm17, %zmm19 {k1}{z}
+
+vpermi2b %zmm16, %zmm17, %zmm19
+vpermi2b (%rax), %zmm17, %zmm19
+vpermi2b %zmm16, %zmm17, %zmm19 {k1}
+vpermi2b (%rax), %zmm17, %zmm19 {k1}
+vpermi2b %zmm16, %zmm17, %zmm19 {k1}{z}
+vpermi2b (%rax), %zmm17, %zmm19 {k1}{z}
+
+vpermt2b %zmm16, %zmm17, %zmm19
+vpermt2b (%rax), %zmm17, %zmm19
+vpermt2b %zmm16, %zmm17, %zmm19 {k1}
+vpermt2b (%rax), %zmm17, %zmm19 {k1}
+vpermt2b %zmm16, %zmm17, %zmm19 {k1}{z}
+vpermt2b (%rax), %zmm17, %zmm19 {k1}{z}
+
+vpmultishiftqb %zmm16, %zmm17, %zmm19
+vpmultishiftqb (%rax), %zmm17, %zmm19
+vpmultishiftqb (%rax){1to8}, %zmm17, %zmm19
+vpmultishiftqb %zmm16, %zmm17, %zmm19 {k1}
+vpmultishiftqb (%rax), %zmm17, %zmm19 {k1}
+vpmultishiftqb (%rax){1to8}, %zmm17, %zmm19 {k1}
+vpmultishiftqb %zmm16, %zmm17, %zmm19 {k1}{z}
+vpmultishiftqb (%rax), %zmm17, %zmm19 {k1}{z}
+vpmultishiftqb (%rax){1to8}, %zmm17, %zmm19 {k1}{z}
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 8 8 8.00 vpermb %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 8 15 8.00 * vpermb (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 8 8 8.00 vpermb %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 8 15 8.00 * vpermb (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 8 8 8.00 vpermb %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 8 15 8.00 * vpermb (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 16 16 16.00 vpermi2b %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 16 23 16.00 * vpermi2b (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 16 16 16.00 vpermi2b %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 16 23 16.00 * vpermi2b (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 16 16 16.00 vpermi2b %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 16 23 16.00 * vpermi2b (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 16 16 16.00 vpermt2b %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 16 23 16.00 * vpermt2b (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 16 16 16.00 vpermt2b %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 16 23 16.00 * vpermt2b (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 16 16 16.00 vpermt2b %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 16 23 16.00 * vpermt2b (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 4.00 vpmultishiftqb %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 11 4.00 * vpmultishiftqb (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpmultishiftqb (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 1 4 4.00 vpmultishiftqb %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 11 4.00 * vpmultishiftqb (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpmultishiftqb (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 4 4.00 vpmultishiftqb %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 4.00 * vpmultishiftqb (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpmultishiftqb (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 5.00 5.00 5.00 - - - - - 265.50 241.50 265.50 241.50 3.75 3.75 3.75 3.75 5.00 5.00 5.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - 8.00 8.00 8.00 8.00 - - - - - - - - - - - vpermb %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 8.00 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermb (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 8.00 8.00 8.00 8.00 - - - - - - - - - - - vpermb %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 8.00 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermb (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 8.00 8.00 8.00 8.00 - - - - - - - - - - - vpermb %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 8.00 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermb (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 16.00 16.00 16.00 16.00 - - - - - - - - - - - vpermi2b %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 16.00 16.00 16.00 16.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermi2b (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 16.00 16.00 16.00 16.00 - - - - - - - - - - - vpermi2b %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 16.00 16.00 16.00 16.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermi2b (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 16.00 16.00 16.00 16.00 - - - - - - - - - - - vpermi2b %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 16.00 16.00 16.00 16.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermi2b (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 16.00 16.00 16.00 16.00 - - - - - - - - - - - vpermt2b %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 16.00 16.00 16.00 16.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermt2b (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 16.00 16.00 16.00 16.00 - - - - - - - - - - - vpermt2b %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 16.00 16.00 16.00 16.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermt2b (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 16.00 16.00 16.00 16.00 - - - - - - - - - - - vpermt2b %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 16.00 16.00 16.00 16.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermt2b (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpmultishiftqb %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmultishiftqb (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmultishiftqb (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpmultishiftqb %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmultishiftqb (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmultishiftqb (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpmultishiftqb %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmultishiftqb (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmultishiftqb (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmi2.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmi2.s
new file mode 100644
index 0000000000000..6e04f81bd41a6
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmi2.s
@@ -0,0 +1,408 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+vpcompressb %zmm16, %zmm19
+vpcompressb %zmm16, (%rax)
+vpcompressb %zmm16, %zmm19 {k1}
+vpcompressb %zmm16, (%rax) {k1}
+vpcompressb %zmm16, %zmm19 {k1}{z}
+
+vpcompressw %zmm16, %zmm19
+vpcompressw %zmm16, (%rax)
+vpcompressw %zmm16, %zmm19 {k1}
+vpcompressw %zmm16, (%rax) {k1}
+vpcompressw %zmm16, %zmm19 {k1}{z}
+
+vpexpandb %zmm16, %zmm19
+vpexpandb (%rax), %zmm19
+vpexpandb %zmm16, %zmm19 {k1}
+vpexpandb (%rax), %zmm19 {k1}
+vpexpandb %zmm16, %zmm19 {k1}{z}
+
+vpexpandw %zmm16, %zmm19
+vpexpandw (%rax), %zmm19
+vpexpandw %zmm16, %zmm19 {k1}
+vpexpandw (%rax), %zmm19 {k1}
+vpexpandw %zmm16, %zmm19 {k1}{z}
+
+vpshldd $1, %zmm16, %zmm17, %zmm19
+vpshldd $1, (%rax), %zmm17, %zmm19
+vpshldd $1, (%rax){1to16}, %zmm17, %zmm19
+vpshldd $1, %zmm16, %zmm17, %zmm19 {k1}
+vpshldd $1, (%rax), %zmm17, %zmm19 {k1}
+vpshldd $1, (%rax){1to16}, %zmm17, %zmm19 {k1}
+vpshldd $1, %zmm16, %zmm17, %zmm19 {k1}{z}
+vpshldd $1, (%rax), %zmm17, %zmm19 {k1}{z}
+vpshldd $1, (%rax){1to16}, %zmm17, %zmm19 {k1}{z}
+
+vpshldq $1, %zmm16, %zmm17, %zmm19
+vpshldq $1, (%rax), %zmm17, %zmm19
+vpshldq $1, (%rax){1to8}, %zmm17, %zmm19
+vpshldq $1, %zmm16, %zmm17, %zmm19 {k1}
+vpshldq $1, (%rax), %zmm17, %zmm19 {k1}
+vpshldq $1, (%rax){1to8}, %zmm17, %zmm19 {k1}
+vpshldq $1, %zmm16, %zmm17, %zmm19 {k1}{z}
+vpshldq $1, (%rax), %zmm17, %zmm19 {k1}{z}
+vpshldq $1, (%rax){1to8}, %zmm17, %zmm19 {k1}{z}
+
+vpshldvd %zmm16, %zmm17, %zmm19
+vpshldvd (%rax), %zmm17, %zmm19
+vpshldvd (%rax){1to16}, %zmm17, %zmm19
+vpshldvd %zmm16, %zmm17, %zmm19 {k1}
+vpshldvd (%rax), %zmm17, %zmm19 {k1}
+vpshldvd (%rax){1to16}, %zmm17, %zmm19 {k1}
+vpshldvd %zmm16, %zmm17, %zmm19 {k1}{z}
+vpshldvd (%rax), %zmm17, %zmm19 {k1}{z}
+vpshldvd (%rax){1to16}, %zmm17, %zmm19 {k1}{z}
+
+vpshldvq %zmm16, %zmm17, %zmm19
+vpshldvq (%rax), %zmm17, %zmm19
+vpshldvq (%rax){1to8}, %zmm17, %zmm19
+vpshldvq %zmm16, %zmm17, %zmm19 {k1}
+vpshldvq (%rax), %zmm17, %zmm19 {k1}
+vpshldvq (%rax){1to8}, %zmm17, %zmm19 {k1}
+vpshldvq %zmm16, %zmm17, %zmm19 {k1}{z}
+vpshldvq (%rax), %zmm17, %zmm19 {k1}{z}
+vpshldvq (%rax){1to8}, %zmm17, %zmm19 {k1}{z}
+
+vpshldvw %zmm16, %zmm17, %zmm19
+vpshldvw (%rax), %zmm17, %zmm19
+vpshldvw %zmm16, %zmm17, %zmm19 {k1}
+vpshldvw (%rax), %zmm17, %zmm19 {k1}
+vpshldvw %zmm16, %zmm17, %zmm19 {k1}{z}
+vpshldvw (%rax), %zmm17, %zmm19 {k1}{z}
+
+vpshldw $1, %zmm16, %zmm17, %zmm19
+vpshldw $1, (%rax), %zmm17, %zmm19
+vpshldw $1, %zmm16, %zmm17, %zmm19 {k1}
+vpshldw $1, (%rax), %zmm17, %zmm19 {k1}
+vpshldw $1, %zmm16, %zmm17, %zmm19 {k1}{z}
+vpshldw $1, (%rax), %zmm17, %zmm19 {k1}{z}
+
+vpshrdd $1, %zmm16, %zmm17, %zmm19
+vpshrdd $1, (%rax), %zmm17, %zmm19
+vpshrdd $1, (%rax){1to16}, %zmm17, %zmm19
+vpshrdd $1, %zmm16, %zmm17, %zmm19 {k1}
+vpshrdd $1, (%rax), %zmm17, %zmm19 {k1}
+vpshrdd $1, (%rax){1to16}, %zmm17, %zmm19 {k1}
+vpshrdd $1, %zmm16, %zmm17, %zmm19 {k1}{z}
+vpshrdd $1, (%rax), %zmm17, %zmm19 {k1}{z}
+vpshrdd $1, (%rax){1to16}, %zmm17, %zmm19 {k1}{z}
+
+vpshrdq $1, %zmm16, %zmm17, %zmm19
+vpshrdq $1, (%rax), %zmm17, %zmm19
+vpshrdq $1, (%rax){1to8}, %zmm17, %zmm19
+vpshrdq $1, %zmm16, %zmm17, %zmm19 {k1}
+vpshrdq $1, (%rax), %zmm17, %zmm19 {k1}
+vpshrdq $1, (%rax){1to8}, %zmm17, %zmm19 {k1}
+vpshrdq $1, %zmm16, %zmm17, %zmm19 {k1}{z}
+vpshrdq $1, (%rax), %zmm17, %zmm19 {k1}{z}
+vpshrdq $1, (%rax){1to8}, %zmm17, %zmm19 {k1}{z}
+
+vpshrdvd %zmm16, %zmm17, %zmm19
+vpshrdvd (%rax), %zmm17, %zmm19
+vpshrdvd (%rax){1to16}, %zmm17, %zmm19
+vpshrdvd %zmm16, %zmm17, %zmm19 {k1}
+vpshrdvd (%rax), %zmm17, %zmm19 {k1}
+vpshrdvd (%rax){1to16}, %zmm17, %zmm19 {k1}
+vpshrdvd %zmm16, %zmm17, %zmm19 {k1}{z}
+vpshrdvd (%rax), %zmm17, %zmm19 {k1}{z}
+vpshrdvd (%rax){1to16}, %zmm17, %zmm19 {k1}{z}
+
+vpshrdvq %zmm16, %zmm17, %zmm19
+vpshrdvq (%rax), %zmm17, %zmm19
+vpshrdvq (%rax){1to8}, %zmm17, %zmm19
+vpshrdvq %zmm16, %zmm17, %zmm19 {k1}
+vpshrdvq (%rax), %zmm17, %zmm19 {k1}
+vpshrdvq (%rax){1to8}, %zmm17, %zmm19 {k1}
+vpshrdvq %zmm16, %zmm17, %zmm19 {k1}{z}
+vpshrdvq (%rax), %zmm17, %zmm19 {k1}{z}
+vpshrdvq (%rax){1to8}, %zmm17, %zmm19 {k1}{z}
+
+vpshrdvw %zmm16, %zmm17, %zmm19
+vpshrdvw (%rax), %zmm17, %zmm19
+vpshrdvw %zmm16, %zmm17, %zmm19 {k1}
+vpshrdvw (%rax), %zmm17, %zmm19 {k1}
+vpshrdvw %zmm16, %zmm17, %zmm19 {k1}{z}
+vpshrdvw (%rax), %zmm17, %zmm19 {k1}{z}
+
+vpshrdw $1, %zmm16, %zmm17, %zmm19
+vpshrdw $1, (%rax), %zmm17, %zmm19
+vpshrdw $1, %zmm16, %zmm17, %zmm19 {k1}
+vpshrdw $1, (%rax), %zmm17, %zmm19 {k1}
+vpshrdw $1, %zmm16, %zmm17, %zmm19 {k1}{z}
+vpshrdw $1, (%rax), %zmm17, %zmm19 {k1}{z}
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 4 1 6.00 U vpcompressb %zmm16, %zmm19
+# CHECK-NEXT: 4 2 6.00 * vpcompressb %zmm16, (%rax)
+# CHECK-NEXT: 4 7 6.00 vpcompressb %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 4 8 6.00 * vpcompressb %zmm16, (%rax) {%k1}
+# CHECK-NEXT: 4 10 6.00 vpcompressb %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 4 1 6.00 U vpcompressw %zmm16, %zmm19
+# CHECK-NEXT: 4 2 6.00 * vpcompressw %zmm16, (%rax)
+# CHECK-NEXT: 4 7 6.00 vpcompressw %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 4 8 6.00 * vpcompressw %zmm16, (%rax) {%k1}
+# CHECK-NEXT: 4 10 6.00 vpcompressw %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 10 1 8.00 U vpexpandb %zmm16, %zmm19
+# CHECK-NEXT: 10 8 8.00 * U vpexpandb (%rax), %zmm19
+# CHECK-NEXT: 10 8 8.00 vpexpandb %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 10 15 8.00 * vpexpandb (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 10 10 8.00 vpexpandb %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 10 1 8.00 U vpexpandw %zmm16, %zmm19
+# CHECK-NEXT: 10 8 8.00 * U vpexpandw (%rax), %zmm19
+# CHECK-NEXT: 10 8 8.00 vpexpandw %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 10 15 8.00 * vpexpandw (%rax), %zmm19 {%k1}
+# CHECK-NEXT: 10 10 8.00 vpexpandw %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshldd $1, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpshldd $1, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vpshldd $1, (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 1 2 1.00 vpshldd $1, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpshldd $1, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 1.00 * vpshldd $1, (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpshldd $1, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpshldd $1, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vpshldd $1, (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshldq $1, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpshldq $1, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vpshldq $1, (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 1 2 1.00 vpshldq $1, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpshldq $1, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 1.00 * vpshldq $1, (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpshldq $1, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpshldq $1, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vpshldq $1, (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshldvd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpshldvd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vpshldvd (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 1 1 0.50 vpshldvd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpshldvd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 1.00 * vpshldvd (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpshldvd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpshldvd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vpshldvd (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshldvq %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpshldvq (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vpshldvq (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 1 1 0.50 vpshldvq %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpshldvq (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 1.00 * vpshldvq (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpshldvq %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpshldvq (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vpshldvq (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshldvw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpshldvw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 1.00 vpshldvw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpshldvw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpshldvw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpshldvw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshldw $1, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpshldw $1, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 1.00 vpshldw $1, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpshldw $1, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpshldw $1, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpshldw $1, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshrdd $1, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpshrdd $1, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vpshrdd $1, (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 1 2 1.00 vpshrdd $1, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpshrdd $1, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 1.00 * vpshrdd $1, (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpshrdd $1, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpshrdd $1, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vpshrdd $1, (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshrdq $1, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpshrdq $1, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vpshrdq $1, (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 1 2 1.00 vpshrdq $1, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpshrdq $1, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 1.00 * vpshrdq $1, (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpshrdq $1, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpshrdq $1, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vpshrdq $1, (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshrdvd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpshrdvd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vpshrdvd (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 1 1 0.50 vpshrdvd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpshrdvd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 1.00 * vpshrdvd (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpshrdvd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpshrdvd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vpshrdvd (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshrdvq %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpshrdvq (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vpshrdvq (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: 1 1 0.50 vpshrdvq %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpshrdvq (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 1.00 * vpshrdvq (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpshrdvq %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpshrdvq (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vpshrdvq (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshrdvw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpshrdvw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 1.00 vpshrdvw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpshrdvw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpshrdvw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpshrdvw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshrdw $1, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 8 0.50 * vpshrdw $1, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 2 1.00 vpshrdw $1, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpshrdw $1, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpshrdw $1, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpshrdw $1, (%rax), %zmm17, %zmm19 {%k1} {z}
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 22.67 22.67 22.67 - - - - - 216.00 - 216.00 140.00 17.00 17.00 17.00 17.00 21.33 21.33 21.33 1.00 1.00 1.00 1.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - 6.00 - 6.00 6.00 - - - - - - - - - - - vpcompressb %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 6.00 - 6.00 6.00 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vpcompressb %zmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - 6.00 - 6.00 6.00 - - - - - - - - - - - vpcompressb %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 6.00 - 6.00 6.00 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vpcompressb %zmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 6.00 - 6.00 6.00 - - - - - - - - - - - vpcompressb %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 6.00 - 6.00 6.00 - - - - - - - - - - - vpcompressw %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 6.00 - 6.00 6.00 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vpcompressw %zmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - 6.00 - 6.00 6.00 - - - - - - - - - - - vpcompressw %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 6.00 - 6.00 6.00 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vpcompressw %zmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 6.00 - 6.00 6.00 - - - - - - - - - - - vpcompressw %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 8.00 - 8.00 8.00 - - - - - - - - - - - vpexpandb %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 - 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpexpandb (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - 8.00 - 8.00 8.00 - - - - - - - - - - - vpexpandb %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 - 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpexpandb (%rax), %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 8.00 - 8.00 8.00 - - - - - - - - - - - vpexpandb %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 8.00 - 8.00 8.00 - - - - - - - - - - - vpexpandw %zmm16, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 - 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpexpandw (%rax), %zmm19
+# CHECK-NEXT: - - - - - - - - 8.00 - 8.00 8.00 - - - - - - - - - - - vpexpandw %zmm16, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 8.00 - 8.00 8.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpexpandw (%rax), %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 8.00 - 8.00 8.00 - - - - - - - - - - - vpexpandw %zmm16, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshldd $1, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldd $1, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldd $1, (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshldd $1, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldd $1, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldd $1, (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshldd $1, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldd $1, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldd $1, (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshldq $1, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldq $1, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldq $1, (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshldq $1, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldq $1, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldq $1, (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshldq $1, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldq $1, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldq $1, (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshldvd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvd (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshldvd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvd (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshldvd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvd (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshldvq %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvq (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvq (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshldvq %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvq (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvq (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshldvq %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvq (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvq (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshldvw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshldvw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshldvw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshldw $1, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldw $1, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshldw $1, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldw $1, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshldw $1, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldw $1, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshrdd $1, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdd $1, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdd $1, (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshrdd $1, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdd $1, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdd $1, (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshrdd $1, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdd $1, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdd $1, (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshrdq $1, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdq $1, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdq $1, (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshrdq $1, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdq $1, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdq $1, (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshrdq $1, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdq $1, (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdq $1, (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshrdvd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvd (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshrdvd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvd (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshrdvd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvd (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshrdvq %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvq (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvq (%rax){1to8}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshrdvq %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvq (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvq (%rax){1to8}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshrdvq %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvq (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvq (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshrdvw %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvw (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshrdvw %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvw (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshrdvw %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvw (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshrdw $1, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdw $1, (%rax), %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshrdw $1, %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdw $1, (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshrdw $1, %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdw $1, (%rax), %zmm17, %zmm19 {%k1} {z}
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmi2vl.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmi2vl.s
new file mode 100644
index 0000000000000..910db11f7213e
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmi2vl.s
@@ -0,0 +1,772 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+vpcompressb %xmm16, %xmm19
+vpcompressb %xmm16, (%rax)
+vpcompressb %xmm16, %xmm19 {k1}
+vpcompressb %xmm16, (%rax) {k1}
+vpcompressb %xmm16, %xmm19 {k1}{z}
+
+vpcompressb %ymm16, %ymm19
+vpcompressb %ymm16, (%rax)
+vpcompressb %ymm16, %ymm19 {k1}
+vpcompressb %ymm16, (%rax) {k1}
+vpcompressb %ymm16, %ymm19 {k1}{z}
+
+vpcompressw %xmm16, %xmm19
+vpcompressw %xmm16, (%rax)
+vpcompressw %xmm16, %xmm19 {k1}
+vpcompressw %xmm16, (%rax) {k1}
+vpcompressw %xmm16, %xmm19 {k1}{z}
+
+vpcompressw %ymm16, %ymm19
+vpcompressw %ymm16, (%rax)
+vpcompressw %ymm16, %ymm19 {k1}
+vpcompressw %ymm16, (%rax) {k1}
+vpcompressw %ymm16, %ymm19 {k1}{z}
+
+vpexpandb %xmm16, %xmm19
+vpexpandb (%rax), %xmm19
+vpexpandb %xmm16, %xmm19 {k1}
+vpexpandb (%rax), %xmm19 {k1}
+vpexpandb %xmm16, %xmm19 {k1}{z}
+
+vpexpandb %ymm16, %ymm19
+vpexpandb (%rax), %ymm19
+vpexpandb %ymm16, %ymm19 {k1}
+vpexpandb (%rax), %ymm19 {k1}
+vpexpandb %ymm16, %ymm19 {k1}{z}
+
+vpexpandw %xmm16, %xmm19
+vpexpandw (%rax), %xmm19
+vpexpandw %xmm16, %xmm19 {k1}
+vpexpandw (%rax), %xmm19 {k1}
+vpexpandw %xmm16, %xmm19 {k1}{z}
+
+vpexpandw %ymm16, %ymm19
+vpexpandw (%rax), %ymm19
+vpexpandw %ymm16, %ymm19 {k1}
+vpexpandw (%rax), %ymm19 {k1}
+vpexpandw %ymm16, %ymm19 {k1}{z}
+
+vpshldd $1, %xmm16, %xmm17, %xmm19
+vpshldd $1, (%rax), %xmm17, %xmm19
+vpshldd $1, (%rax){1to4}, %xmm17, %xmm19
+vpshldd $1, %xmm16, %xmm17, %xmm19 {k1}
+vpshldd $1, (%rax), %xmm17, %xmm19 {k1}
+vpshldd $1, (%rax){1to4}, %xmm17, %xmm19 {k1}
+vpshldd $1, %xmm16, %xmm17, %xmm19 {k1}{z}
+vpshldd $1, (%rax), %xmm17, %xmm19 {k1}{z}
+vpshldd $1, (%rax){1to4}, %xmm17, %xmm19 {k1}{z}
+
+vpshldd $1, %ymm16, %ymm17, %ymm19
+vpshldd $1, (%rax), %ymm17, %ymm19
+vpshldd $1, (%rax){1to8}, %ymm17, %ymm19
+vpshldd $1, %ymm16, %ymm17, %ymm19 {k1}
+vpshldd $1, (%rax), %ymm17, %ymm19 {k1}
+vpshldd $1, (%rax){1to8}, %ymm17, %ymm19 {k1}
+vpshldd $1, %ymm16, %ymm17, %ymm19 {k1}{z}
+vpshldd $1, (%rax), %ymm17, %ymm19 {k1}{z}
+vpshldd $1, (%rax){1to8}, %ymm17, %ymm19 {k1}{z}
+
+vpshldq $1, %xmm16, %xmm17, %xmm19
+vpshldq $1, (%rax), %xmm17, %xmm19
+vpshldq $1, (%rax){1to2}, %xmm17, %xmm19
+vpshldq $1, %xmm16, %xmm17, %xmm19 {k1}
+vpshldq $1, (%rax), %xmm17, %xmm19 {k1}
+vpshldq $1, (%rax){1to2}, %xmm17, %xmm19 {k1}
+vpshldq $1, %xmm16, %xmm17, %xmm19 {k1}{z}
+vpshldq $1, (%rax), %xmm17, %xmm19 {k1}{z}
+vpshldq $1, (%rax){1to2}, %xmm17, %xmm19 {k1}{z}
+
+vpshldq $1, %ymm16, %ymm17, %ymm19
+vpshldq $1, (%rax), %ymm17, %ymm19
+vpshldq $1, (%rax){1to4}, %ymm17, %ymm19
+vpshldq $1, %ymm16, %ymm17, %ymm19 {k1}
+vpshldq $1, (%rax), %ymm17, %ymm19 {k1}
+vpshldq $1, (%rax){1to4}, %ymm17, %ymm19 {k1}
+vpshldq $1, %ymm16, %ymm17, %ymm19 {k1}{z}
+vpshldq $1, (%rax), %ymm17, %ymm19 {k1}{z}
+vpshldq $1, (%rax){1to4}, %ymm17, %ymm19 {k1}{z}
+
+vpshldvd %xmm16, %xmm17, %xmm19
+vpshldvd (%rax), %xmm17, %xmm19
+vpshldvd (%rax){1to4}, %xmm17, %xmm19
+vpshldvd %xmm16, %xmm17, %xmm19 {k1}
+vpshldvd (%rax), %xmm17, %xmm19 {k1}
+vpshldvd (%rax){1to4}, %xmm17, %xmm19 {k1}
+vpshldvd %xmm16, %xmm17, %xmm19 {k1}{z}
+vpshldvd (%rax), %xmm17, %xmm19 {k1}{z}
+vpshldvd (%rax){1to4}, %xmm17, %xmm19 {k1}{z}
+
+vpshldvd %ymm16, %ymm17, %ymm19
+vpshldvd (%rax), %ymm17, %ymm19
+vpshldvd (%rax){1to8}, %ymm17, %ymm19
+vpshldvd %ymm16, %ymm17, %ymm19 {k1}
+vpshldvd (%rax), %ymm17, %ymm19 {k1}
+vpshldvd (%rax){1to8}, %ymm17, %ymm19 {k1}
+vpshldvd %ymm16, %ymm17, %ymm19 {k1}{z}
+vpshldvd (%rax), %ymm17, %ymm19 {k1}{z}
+vpshldvd (%rax){1to8}, %ymm17, %ymm19 {k1}{z}
+
+vpshldvq %xmm16, %xmm17, %xmm19
+vpshldvq (%rax), %xmm17, %xmm19
+vpshldvq (%rax){1to2}, %xmm17, %xmm19
+vpshldvq %xmm16, %xmm17, %xmm19 {k1}
+vpshldvq (%rax), %xmm17, %xmm19 {k1}
+vpshldvq (%rax){1to2}, %xmm17, %xmm19 {k1}
+vpshldvq %xmm16, %xmm17, %xmm19 {k1}{z}
+vpshldvq (%rax), %xmm17, %xmm19 {k1}{z}
+vpshldvq (%rax){1to2}, %xmm17, %xmm19 {k1}{z}
+
+vpshldvq %ymm16, %ymm17, %ymm19
+vpshldvq (%rax), %ymm17, %ymm19
+vpshldvq (%rax){1to4}, %ymm17, %ymm19
+vpshldvq %ymm16, %ymm17, %ymm19 {k1}
+vpshldvq (%rax), %ymm17, %ymm19 {k1}
+vpshldvq (%rax){1to4}, %ymm17, %ymm19 {k1}
+vpshldvq %ymm16, %ymm17, %ymm19 {k1}{z}
+vpshldvq (%rax), %ymm17, %ymm19 {k1}{z}
+vpshldvq (%rax){1to4}, %ymm17, %ymm19 {k1}{z}
+
+vpshldvw %xmm16, %xmm17, %xmm19
+vpshldvw (%rax), %xmm17, %xmm19
+vpshldvw %xmm16, %xmm17, %xmm19 {k1}
+vpshldvw (%rax), %xmm17, %xmm19 {k1}
+vpshldvw %xmm16, %xmm17, %xmm19 {k1}{z}
+vpshldvw (%rax), %xmm17, %xmm19 {k1}{z}
+
+vpshldvw %ymm16, %ymm17, %ymm19
+vpshldvw (%rax), %ymm17, %ymm19
+vpshldvw %ymm16, %ymm17, %ymm19 {k1}
+vpshldvw (%rax), %ymm17, %ymm19 {k1}
+vpshldvw %ymm16, %ymm17, %ymm19 {k1}{z}
+vpshldvw (%rax), %ymm17, %ymm19 {k1}{z}
+
+vpshldw $1, %xmm16, %xmm17, %xmm19
+vpshldw $1, (%rax), %xmm17, %xmm19
+vpshldw $1, %xmm16, %xmm17, %xmm19 {k1}
+vpshldw $1, (%rax), %xmm17, %xmm19 {k1}
+vpshldw $1, %xmm16, %xmm17, %xmm19 {k1}{z}
+vpshldw $1, (%rax), %xmm17, %xmm19 {k1}{z}
+
+vpshldw $1, %ymm16, %ymm17, %ymm19
+vpshldw $1, (%rax), %ymm17, %ymm19
+vpshldw $1, %ymm16, %ymm17, %ymm19 {k1}
+vpshldw $1, (%rax), %ymm17, %ymm19 {k1}
+vpshldw $1, %ymm16, %ymm17, %ymm19 {k1}{z}
+vpshldw $1, (%rax), %ymm17, %ymm19 {k1}{z}
+
+vpshrdd $1, %xmm16, %xmm17, %xmm19
+vpshrdd $1, (%rax), %xmm17, %xmm19
+vpshrdd $1, (%rax){1to4}, %xmm17, %xmm19
+vpshrdd $1, %xmm16, %xmm17, %xmm19 {k1}
+vpshrdd $1, (%rax), %xmm17, %xmm19 {k1}
+vpshrdd $1, (%rax){1to4}, %xmm17, %xmm19 {k1}
+vpshrdd $1, %xmm16, %xmm17, %xmm19 {k1}{z}
+vpshrdd $1, (%rax), %xmm17, %xmm19 {k1}{z}
+vpshrdd $1, (%rax){1to4}, %xmm17, %xmm19 {k1}{z}
+
+vpshrdd $1, %ymm16, %ymm17, %ymm19
+vpshrdd $1, (%rax), %ymm17, %ymm19
+vpshrdd $1, (%rax){1to8}, %ymm17, %ymm19
+vpshrdd $1, %ymm16, %ymm17, %ymm19 {k1}
+vpshrdd $1, (%rax), %ymm17, %ymm19 {k1}
+vpshrdd $1, (%rax){1to8}, %ymm17, %ymm19 {k1}
+vpshrdd $1, %ymm16, %ymm17, %ymm19 {k1}{z}
+vpshrdd $1, (%rax), %ymm17, %ymm19 {k1}{z}
+vpshrdd $1, (%rax){1to8}, %ymm17, %ymm19 {k1}{z}
+
+vpshrdq $1, %xmm16, %xmm17, %xmm19
+vpshrdq $1, (%rax), %xmm17, %xmm19
+vpshrdq $1, (%rax){1to2}, %xmm17, %xmm19
+vpshrdq $1, %xmm16, %xmm17, %xmm19 {k1}
+vpshrdq $1, (%rax), %xmm17, %xmm19 {k1}
+vpshrdq $1, (%rax){1to2}, %xmm17, %xmm19 {k1}
+vpshrdq $1, %xmm16, %xmm17, %xmm19 {k1}{z}
+vpshrdq $1, (%rax), %xmm17, %xmm19 {k1}{z}
+vpshrdq $1, (%rax){1to2}, %xmm17, %xmm19 {k1}{z}
+
+vpshrdq $1, %ymm16, %ymm17, %ymm19
+vpshrdq $1, (%rax), %ymm17, %ymm19
+vpshrdq $1, (%rax){1to4}, %ymm17, %ymm19
+vpshrdq $1, %ymm16, %ymm17, %ymm19 {k1}
+vpshrdq $1, (%rax), %ymm17, %ymm19 {k1}
+vpshrdq $1, (%rax){1to4}, %ymm17, %ymm19 {k1}
+vpshrdq $1, %ymm16, %ymm17, %ymm19 {k1}{z}
+vpshrdq $1, (%rax), %ymm17, %ymm19 {k1}{z}
+vpshrdq $1, (%rax){1to4}, %ymm17, %ymm19 {k1}{z}
+
+vpshrdvd %xmm16, %xmm17, %xmm19
+vpshrdvd (%rax), %xmm17, %xmm19
+vpshrdvd (%rax){1to4}, %xmm17, %xmm19
+vpshrdvd %xmm16, %xmm17, %xmm19 {k1}
+vpshrdvd (%rax), %xmm17, %xmm19 {k1}
+vpshrdvd (%rax){1to4}, %xmm17, %xmm19 {k1}
+vpshrdvd %xmm16, %xmm17, %xmm19 {k1}{z}
+vpshrdvd (%rax), %xmm17, %xmm19 {k1}{z}
+vpshrdvd (%rax){1to4}, %xmm17, %xmm19 {k1}{z}
+
+vpshrdvd %ymm16, %ymm17, %ymm19
+vpshrdvd (%rax), %ymm17, %ymm19
+vpshrdvd (%rax){1to8}, %ymm17, %ymm19
+vpshrdvd %ymm16, %ymm17, %ymm19 {k1}
+vpshrdvd (%rax), %ymm17, %ymm19 {k1}
+vpshrdvd (%rax){1to8}, %ymm17, %ymm19 {k1}
+vpshrdvd %ymm16, %ymm17, %ymm19 {k1}{z}
+vpshrdvd (%rax), %ymm17, %ymm19 {k1}{z}
+vpshrdvd (%rax){1to8}, %ymm17, %ymm19 {k1}{z}
+
+vpshrdvq %xmm16, %xmm17, %xmm19
+vpshrdvq (%rax), %xmm17, %xmm19
+vpshrdvq (%rax){1to2}, %xmm17, %xmm19
+vpshrdvq %xmm16, %xmm17, %xmm19 {k1}
+vpshrdvq (%rax), %xmm17, %xmm19 {k1}
+vpshrdvq (%rax){1to2}, %xmm17, %xmm19 {k1}
+vpshrdvq %xmm16, %xmm17, %xmm19 {k1}{z}
+vpshrdvq (%rax), %xmm17, %xmm19 {k1}{z}
+vpshrdvq (%rax){1to2}, %xmm17, %xmm19 {k1}{z}
+
+vpshrdvq %ymm16, %ymm17, %ymm19
+vpshrdvq (%rax), %ymm17, %ymm19
+vpshrdvq (%rax){1to4}, %ymm17, %ymm19
+vpshrdvq %ymm16, %ymm17, %ymm19 {k1}
+vpshrdvq (%rax), %ymm17, %ymm19 {k1}
+vpshrdvq (%rax){1to4}, %ymm17, %ymm19 {k1}
+vpshrdvq %ymm16, %ymm17, %ymm19 {k1}{z}
+vpshrdvq (%rax), %ymm17, %ymm19 {k1}{z}
+vpshrdvq (%rax){1to4}, %ymm17, %ymm19 {k1}{z}
+
+vpshrdvw %xmm16, %xmm17, %xmm19
+vpshrdvw (%rax), %xmm17, %xmm19
+vpshrdvw %xmm16, %xmm17, %xmm19 {k1}
+vpshrdvw (%rax), %xmm17, %xmm19 {k1}
+vpshrdvw %xmm16, %xmm17, %xmm19 {k1}{z}
+vpshrdvw (%rax), %xmm17, %xmm19 {k1}{z}
+
+vpshrdvw %ymm16, %ymm17, %ymm19
+vpshrdvw (%rax), %ymm17, %ymm19
+vpshrdvw %ymm16, %ymm17, %ymm19 {k1}
+vpshrdvw (%rax), %ymm17, %ymm19 {k1}
+vpshrdvw %ymm16, %ymm17, %ymm19 {k1}{z}
+vpshrdvw (%rax), %ymm17, %ymm19 {k1}{z}
+
+vpshrdw $1, %xmm16, %xmm17, %xmm19
+vpshrdw $1, (%rax), %xmm17, %xmm19
+vpshrdw $1, %xmm16, %xmm17, %xmm19 {k1}
+vpshrdw $1, (%rax), %xmm17, %xmm19 {k1}
+vpshrdw $1, %xmm16, %xmm17, %xmm19 {k1}{z}
+vpshrdw $1, (%rax), %xmm17, %xmm19 {k1}{z}
+
+vpshrdw $1, %ymm16, %ymm17, %ymm19
+vpshrdw $1, (%rax), %ymm17, %ymm19
+vpshrdw $1, %ymm16, %ymm17, %ymm19 {k1}
+vpshrdw $1, (%rax), %ymm17, %ymm19 {k1}
+vpshrdw $1, %ymm16, %ymm17, %ymm19 {k1}{z}
+vpshrdw $1, (%rax), %ymm17, %ymm19 {k1}{z}
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 2 1 2.00 U vpcompressb %xmm16, %xmm19
+# CHECK-NEXT: 2 2 2.00 * vpcompressb %xmm16, (%rax)
+# CHECK-NEXT: 2 4 2.00 vpcompressb %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 5 2.00 * vpcompressb %xmm16, (%rax) {%k1}
+# CHECK-NEXT: 2 3 2.00 vpcompressb %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 2 1 2.00 U vpcompressb %ymm16, %ymm19
+# CHECK-NEXT: 2 2 2.00 * vpcompressb %ymm16, (%rax)
+# CHECK-NEXT: 2 4 2.00 vpcompressb %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 2 5 2.00 * vpcompressb %ymm16, (%rax) {%k1}
+# CHECK-NEXT: 2 3 2.00 vpcompressb %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 1 2.00 U vpcompressw %xmm16, %xmm19
+# CHECK-NEXT: 2 2 2.00 * vpcompressw %xmm16, (%rax)
+# CHECK-NEXT: 2 4 2.00 vpcompressw %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 5 2.00 * vpcompressw %xmm16, (%rax) {%k1}
+# CHECK-NEXT: 2 3 2.00 vpcompressw %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 2 1 2.00 U vpcompressw %ymm16, %ymm19
+# CHECK-NEXT: 2 2 2.00 * vpcompressw %ymm16, (%rax)
+# CHECK-NEXT: 2 4 2.00 vpcompressw %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 2 5 2.00 * vpcompressw %ymm16, (%rax) {%k1}
+# CHECK-NEXT: 2 3 2.00 vpcompressw %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 2.00 U vpexpandb %xmm16, %xmm19
+# CHECK-NEXT: 1 8 2.00 * U vpexpandb (%rax), %xmm19
+# CHECK-NEXT: 1 4 2.00 vpexpandb %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 11 2.00 * vpexpandb (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 3 2.00 vpexpandb %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 2.00 U vpexpandb %ymm16, %ymm19
+# CHECK-NEXT: 1 8 2.00 * U vpexpandb (%rax), %ymm19
+# CHECK-NEXT: 1 4 2.00 vpexpandb %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 2.00 * vpexpandb (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 3 2.00 vpexpandb %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 2.00 U vpexpandw %xmm16, %xmm19
+# CHECK-NEXT: 1 8 2.00 * U vpexpandw (%rax), %xmm19
+# CHECK-NEXT: 1 4 2.00 vpexpandw %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 11 2.00 * vpexpandw (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 3 2.00 vpexpandw %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 2.00 U vpexpandw %ymm16, %ymm19
+# CHECK-NEXT: 1 8 2.00 * U vpexpandw (%rax), %ymm19
+# CHECK-NEXT: 1 4 2.00 vpexpandw %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 2.00 * vpexpandw (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 3 2.00 vpexpandw %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshldd $1, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpshldd $1, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpshldd $1, (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: 1 2 1.00 vpshldd $1, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpshldd $1, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpshldd $1, (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpshldd $1, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpshldd $1, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpshldd $1, (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshldd $1, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpshldd $1, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpshldd $1, (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 1 2 1.00 vpshldd $1, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpshldd $1, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpshldd $1, (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpshldd $1, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpshldd $1, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpshldd $1, (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshldq $1, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpshldq $1, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpshldq $1, (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: 1 2 1.00 vpshldq $1, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpshldq $1, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpshldq $1, (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpshldq $1, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpshldq $1, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpshldq $1, (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshldq $1, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpshldq $1, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpshldq $1, (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 1 2 1.00 vpshldq $1, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpshldq $1, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpshldq $1, (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpshldq $1, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpshldq $1, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpshldq $1, (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshldvd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpshldvd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpshldvd (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: 1 1 0.50 vpshldvd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpshldvd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpshldvd (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpshldvd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpshldvd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpshldvd (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshldvd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpshldvd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpshldvd (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 1 1 0.50 vpshldvd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpshldvd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpshldvd (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpshldvd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpshldvd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpshldvd (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshldvq %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpshldvq (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpshldvq (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: 1 1 0.50 vpshldvq %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpshldvq (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpshldvq (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpshldvq %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpshldvq (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpshldvq (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshldvq %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpshldvq (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpshldvq (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 1 1 0.50 vpshldvq %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpshldvq (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpshldvq (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpshldvq %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpshldvq (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpshldvq (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshldvw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpshldvw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 1.00 vpshldvw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpshldvw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpshldvw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpshldvw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshldvw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpshldvw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 1.00 vpshldvw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpshldvw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpshldvw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpshldvw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshldw $1, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpshldw $1, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 1.00 vpshldw $1, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpshldw $1, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpshldw $1, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpshldw $1, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshldw $1, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpshldw $1, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 1.00 vpshldw $1, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpshldw $1, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpshldw $1, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpshldw $1, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshrdd $1, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpshrdd $1, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpshrdd $1, (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: 1 2 1.00 vpshrdd $1, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpshrdd $1, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpshrdd $1, (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpshrdd $1, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpshrdd $1, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpshrdd $1, (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshrdd $1, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpshrdd $1, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpshrdd $1, (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 1 2 1.00 vpshrdd $1, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpshrdd $1, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpshrdd $1, (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpshrdd $1, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpshrdd $1, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpshrdd $1, (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshrdq $1, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpshrdq $1, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpshrdq $1, (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: 1 2 1.00 vpshrdq $1, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpshrdq $1, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpshrdq $1, (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpshrdq $1, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpshrdq $1, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpshrdq $1, (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshrdq $1, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpshrdq $1, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpshrdq $1, (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 1 2 1.00 vpshrdq $1, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpshrdq $1, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpshrdq $1, (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpshrdq $1, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpshrdq $1, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpshrdq $1, (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshrdvd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpshrdvd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpshrdvd (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: 1 1 0.50 vpshrdvd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpshrdvd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpshrdvd (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpshrdvd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpshrdvd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpshrdvd (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshrdvd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpshrdvd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpshrdvd (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 1 1 0.50 vpshrdvd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpshrdvd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpshrdvd (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpshrdvd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpshrdvd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpshrdvd (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshrdvq %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpshrdvq (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpshrdvq (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: 1 1 0.50 vpshrdvq %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpshrdvq (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpshrdvq (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpshrdvq %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpshrdvq (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpshrdvq (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshrdvq %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpshrdvq (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpshrdvq (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 1 1 0.50 vpshrdvq %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpshrdvq (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpshrdvq (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpshrdvq %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpshrdvq (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpshrdvq (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshrdvw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpshrdvw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 1.00 vpshrdvw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpshrdvw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpshrdvw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpshrdvw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshrdvw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpshrdvw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 1.00 vpshrdvw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpshrdvw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpshrdvw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpshrdvw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshrdw $1, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpshrdw $1, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 2 1.00 vpshrdw $1, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpshrdw $1, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpshrdw $1, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpshrdw $1, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshrdw $1, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpshrdw $1, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 2 1.00 vpshrdw $1, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 1.00 * vpshrdw $1, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 2 1.00 vpshrdw $1, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 9 1.00 * vpshrdw $1, (%rax), %ymm17, %ymm19 {%k1} {z}
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 45.33 45.33 45.33 - - - - - 208.00 - 208.00 80.00 34.00 34.00 34.00 34.00 42.67 42.67 42.67 2.00 2.00 2.00 2.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 2.00 - - - - - - - - - - - vpcompressb %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 2.00 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vpcompressb %xmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 2.00 - - - - - - - - - - - vpcompressb %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 2.00 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vpcompressb %xmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 2.00 - - - - - - - - - - - vpcompressb %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 2.00 - - - - - - - - - - - vpcompressb %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 2.00 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vpcompressb %ymm16, (%rax)
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 2.00 - - - - - - - - - - - vpcompressb %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 2.00 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vpcompressb %ymm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 2.00 - - - - - - - - - - - vpcompressb %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 2.00 - - - - - - - - - - - vpcompressw %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 2.00 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vpcompressw %xmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 2.00 - - - - - - - - - - - vpcompressw %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 2.00 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vpcompressw %xmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 2.00 - - - - - - - - - - - vpcompressw %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 2.00 - - - - - - - - - - - vpcompressw %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 2.00 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vpcompressw %ymm16, (%rax)
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 2.00 - - - - - - - - - - - vpcompressw %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 2.00 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vpcompressw %ymm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 2.00 - - - - - - - - - - - vpcompressw %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 2.00 - - - - - - - - - - - vpexpandb %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpexpandb (%rax), %xmm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 2.00 - - - - - - - - - - - vpexpandb %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpexpandb (%rax), %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 2.00 - - - - - - - - - - - vpexpandb %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 2.00 - - - - - - - - - - - vpexpandb %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpexpandb (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 2.00 - - - - - - - - - - - vpexpandb %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpexpandb (%rax), %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 2.00 - - - - - - - - - - - vpexpandb %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 2.00 - - - - - - - - - - - vpexpandw %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpexpandw (%rax), %xmm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 2.00 - - - - - - - - - - - vpexpandw %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpexpandw (%rax), %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 2.00 - - - - - - - - - - - vpexpandw %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 2.00 - - - - - - - - - - - vpexpandw %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpexpandw (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 2.00 - - - - - - - - - - - vpexpandw %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpexpandw (%rax), %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 2.00 - - - - - - - - - - - vpexpandw %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshldd $1, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldd $1, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldd $1, (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshldd $1, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldd $1, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldd $1, (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshldd $1, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldd $1, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldd $1, (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshldd $1, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldd $1, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldd $1, (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshldd $1, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldd $1, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldd $1, (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshldd $1, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldd $1, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldd $1, (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshldq $1, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldq $1, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldq $1, (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshldq $1, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldq $1, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldq $1, (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshldq $1, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldq $1, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldq $1, (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshldq $1, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldq $1, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldq $1, (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshldq $1, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldq $1, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldq $1, (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshldq $1, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldq $1, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldq $1, (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshldvd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvd (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshldvd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvd (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshldvd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvd (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshldvd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvd (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshldvd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvd (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshldvd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvd (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshldvq %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvq (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvq (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshldvq %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvq (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvq (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshldvq %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvq (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvq (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshldvq %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvq (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvq (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshldvq %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvq (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvq (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshldvq %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvq (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvq (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshldvw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshldvw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshldvw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshldvw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshldvw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshldvw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldvw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshldw $1, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldw $1, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshldw $1, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldw $1, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshldw $1, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldw $1, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshldw $1, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldw $1, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshldw $1, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldw $1, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshldw $1, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshldw $1, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshrdd $1, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdd $1, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdd $1, (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshrdd $1, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdd $1, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdd $1, (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshrdd $1, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdd $1, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdd $1, (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshrdd $1, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdd $1, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdd $1, (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshrdd $1, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdd $1, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdd $1, (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshrdd $1, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdd $1, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdd $1, (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshrdq $1, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdq $1, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdq $1, (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshrdq $1, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdq $1, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdq $1, (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshrdq $1, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdq $1, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdq $1, (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshrdq $1, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdq $1, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdq $1, (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshrdq $1, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdq $1, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdq $1, (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshrdq $1, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdq $1, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdq $1, (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshrdvd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvd (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshrdvd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvd (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshrdvd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvd (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshrdvd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvd (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshrdvd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvd (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshrdvd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvd (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshrdvq %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvq (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvq (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshrdvq %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvq (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvq (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshrdvq %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvq (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvq (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshrdvq %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvq (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvq (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshrdvq %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvq (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvq (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshrdvq %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvq (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvq (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshrdvw %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvw (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshrdvw %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvw (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshrdvw %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvw (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshrdvw %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvw (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshrdvw %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvw (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshrdvw %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdvw (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshrdw $1, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdw $1, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshrdw $1, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdw $1, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshrdw $1, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdw $1, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpshrdw $1, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdw $1, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshrdw $1, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdw $1, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpshrdw $1, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshrdw $1, (%rax), %ymm17, %ymm19 {%k1} {z}
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmivl.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmivl.s
new file mode 100644
index 0000000000000..75947526d47a6
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmivl.s
@@ -0,0 +1,214 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+vpermb %xmm16, %xmm17, %xmm19
+vpermb (%rax), %xmm17, %xmm19
+vpermb %xmm16, %xmm17, %xmm19 {k1}
+vpermb (%rax), %xmm17, %xmm19 {k1}
+vpermb %xmm16, %xmm17, %xmm19 {k1}{z}
+vpermb (%rax), %xmm17, %xmm19 {k1}{z}
+
+vpermb %ymm16, %ymm17, %ymm19
+vpermb (%rax), %ymm17, %ymm19
+vpermb %ymm16, %ymm17, %ymm19 {k1}
+vpermb (%rax), %ymm17, %ymm19 {k1}
+vpermb %ymm16, %ymm17, %ymm19 {k1}{z}
+vpermb (%rax), %ymm17, %ymm19 {k1}{z}
+
+vpermi2b %xmm16, %xmm17, %xmm19
+vpermi2b (%rax), %xmm17, %xmm19
+vpermi2b %xmm16, %xmm17, %xmm19 {k1}
+vpermi2b (%rax), %xmm17, %xmm19 {k1}
+vpermi2b %xmm16, %xmm17, %xmm19 {k1}{z}
+vpermi2b (%rax), %xmm17, %xmm19 {k1}{z}
+
+vpermi2b %ymm16, %ymm17, %ymm19
+vpermi2b (%rax), %ymm17, %ymm19
+vpermi2b %ymm16, %ymm17, %ymm19 {k1}
+vpermi2b (%rax), %ymm17, %ymm19 {k1}
+vpermi2b %ymm16, %ymm17, %ymm19 {k1}{z}
+vpermi2b (%rax), %ymm17, %ymm19 {k1}{z}
+
+vpermt2b %xmm16, %xmm17, %xmm19
+vpermt2b (%rax), %xmm17, %xmm19
+vpermt2b %xmm16, %xmm17, %xmm19 {k1}
+vpermt2b (%rax), %xmm17, %xmm19 {k1}
+vpermt2b %xmm16, %xmm17, %xmm19 {k1}{z}
+vpermt2b (%rax), %xmm17, %xmm19 {k1}{z}
+
+vpermt2b %ymm16, %ymm17, %ymm19
+vpermt2b (%rax), %ymm17, %ymm19
+vpermt2b %ymm16, %ymm17, %ymm19 {k1}
+vpermt2b (%rax), %ymm17, %ymm19 {k1}
+vpermt2b %ymm16, %ymm17, %ymm19 {k1}{z}
+vpermt2b (%rax), %ymm17, %ymm19 {k1}{z}
+
+vpmultishiftqb %xmm16, %xmm17, %xmm19
+vpmultishiftqb (%rax), %xmm17, %xmm19
+vpmultishiftqb (%rax){1to2}, %xmm17, %xmm19
+vpmultishiftqb %xmm16, %xmm17, %xmm19 {k1}
+vpmultishiftqb (%rax), %xmm17, %xmm19 {k1}
+vpmultishiftqb (%rax){1to2}, %xmm17, %xmm19 {k1}
+vpmultishiftqb %xmm16, %xmm17, %xmm19 {k1}{z}
+vpmultishiftqb (%rax), %xmm17, %xmm19 {k1}{z}
+vpmultishiftqb (%rax){1to2}, %xmm17, %xmm19 {k1}{z}
+
+vpmultishiftqb %ymm16, %ymm17, %ymm19
+vpmultishiftqb (%rax), %ymm17, %ymm19
+vpmultishiftqb (%rax){1to4}, %ymm17, %ymm19
+vpmultishiftqb %ymm16, %ymm17, %ymm19 {k1}
+vpmultishiftqb (%rax), %ymm17, %ymm19 {k1}
+vpmultishiftqb (%rax){1to4}, %ymm17, %ymm19 {k1}
+vpmultishiftqb %ymm16, %ymm17, %ymm19 {k1}{z}
+vpmultishiftqb (%rax), %ymm17, %ymm19 {k1}{z}
+vpmultishiftqb (%rax){1to4}, %ymm17, %ymm19 {k1}{z}
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 2.00 vpermb %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 2.00 * vpermb (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 4 2.00 vpermb %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 11 2.00 * vpermb (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 3 2.00 vpermb %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 2.00 * vpermb (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 2.00 vpermb %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 2.00 * vpermb (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 4 2.00 vpermb %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 2.00 * vpermb (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 2.00 vpermb %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 2.00 * vpermb (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 2.00 vpermi2b %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 2.00 * vpermi2b (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 4 2.00 vpermi2b %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 11 2.00 * vpermi2b (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 3 2.00 vpermi2b %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 2.00 * vpermi2b (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 4 6 4.00 vpermi2b %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 4 13 4.00 * vpermi2b (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 4 6 4.00 vpermi2b %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 4 13 4.00 * vpermi2b (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 4 6 4.00 vpermi2b %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 4 13 4.00 * vpermi2b (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 2.00 vpermt2b %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 2.00 * vpermt2b (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 4 2.00 vpermt2b %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 11 2.00 * vpermt2b (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 3 2.00 vpermt2b %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 2.00 * vpermt2b (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 4 4 4.00 vpermt2b %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 4 11 4.00 * vpermt2b (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 4 4 4.00 vpermt2b %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 4 11 4.00 * vpermt2b (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 4 4 4.00 vpermt2b %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 4 11 4.00 * vpermt2b (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 4.00 vpmultishiftqb %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 4.00 * vpmultishiftqb (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpmultishiftqb (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: 1 4 4.00 vpmultishiftqb %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 11 4.00 * vpmultishiftqb (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpmultishiftqb (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 3 4.00 vpmultishiftqb %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 4.00 * vpmultishiftqb (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpmultishiftqb (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 4.00 vpmultishiftqb %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 4.00 * vpmultishiftqb (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpmultishiftqb (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 1 4 4.00 vpmultishiftqb %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 4.00 * vpmultishiftqb (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpmultishiftqb (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 4.00 vpmultishiftqb %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 4.00 * vpmultishiftqb (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpmultishiftqb (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 10.00 10.00 10.00 - - - - - 145.50 49.50 145.50 49.50 7.50 7.50 7.50 7.50 10.00 10.00 10.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermb %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermb (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermb %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermb (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermb %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermb (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermb %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermb (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermb %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermb (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermb %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermb (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermi2b %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermi2b (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermi2b %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermi2b (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermi2b %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermi2b (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 4.00 4.00 4.00 4.00 - - - - - - - - - - - vpermi2b %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 4.00 4.00 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermi2b (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 4.00 4.00 4.00 4.00 - - - - - - - - - - - vpermi2b %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 4.00 4.00 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermi2b (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 4.00 4.00 4.00 4.00 - - - - - - - - - - - vpermi2b %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 4.00 4.00 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermi2b (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermt2b %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermt2b (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermt2b %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermt2b (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermt2b %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermt2b (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 4.00 4.00 4.00 4.00 - - - - - - - - - - - vpermt2b %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 4.00 4.00 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermt2b (%rax), %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 4.00 4.00 4.00 4.00 - - - - - - - - - - - vpermt2b %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 4.00 4.00 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermt2b (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 4.00 4.00 4.00 4.00 - - - - - - - - - - - vpermt2b %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 4.00 4.00 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermt2b (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpmultishiftqb %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmultishiftqb (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmultishiftqb (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpmultishiftqb %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmultishiftqb (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmultishiftqb (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpmultishiftqb %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmultishiftqb (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmultishiftqb (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpmultishiftqb %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmultishiftqb (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmultishiftqb (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpmultishiftqb %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmultishiftqb (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmultishiftqb (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - vpmultishiftqb %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmultishiftqb (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmultishiftqb (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vl.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vl.s
new file mode 100644
index 0000000000000..719c45f7ebf89
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vl.s
@@ -0,0 +1,5294 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+vaddpd %xmm16, %xmm17, %xmm19
+vaddpd (%rax), %xmm17, %xmm19
+vaddpd (%rax){1to2}, %xmm17, %xmm19
+vaddpd %xmm16, %xmm17, %xmm19 {k1}
+vaddpd (%rax), %xmm17, %xmm19 {k1}
+vaddpd (%rax){1to2}, %xmm17, %xmm19 {k1}
+vaddpd %xmm16, %xmm17, %xmm19 {z}{k1}
+vaddpd (%rax), %xmm17, %xmm19 {z}{k1}
+vaddpd (%rax){1to2}, %xmm17, %xmm19 {z}{k1}
+
+vaddpd %ymm16, %ymm17, %ymm19
+vaddpd (%rax), %ymm17, %ymm19
+vaddpd (%rax){1to4}, %ymm17, %ymm19
+vaddpd %ymm16, %ymm17, %ymm19 {k1}
+vaddpd (%rax), %ymm17, %ymm19 {k1}
+vaddpd (%rax){1to4}, %ymm17, %ymm19 {k1}
+vaddpd %ymm16, %ymm17, %ymm19 {z}{k1}
+vaddpd (%rax), %ymm17, %ymm19 {z}{k1}
+vaddpd (%rax){1to4}, %ymm17, %ymm19 {z}{k1}
+
+vaddps %xmm16, %xmm17, %xmm19
+vaddps (%rax), %xmm17, %xmm19
+vaddps (%rax){1to4}, %xmm17, %xmm19
+vaddps %xmm16, %xmm17, %xmm19 {k1}
+vaddps (%rax), %xmm17, %xmm19 {k1}
+vaddps (%rax){1to4}, %xmm17, %xmm19 {k1}
+vaddps %xmm16, %xmm17, %xmm19 {z}{k1}
+vaddps (%rax), %xmm17, %xmm19 {z}{k1}
+vaddps (%rax){1to4}, %xmm17, %xmm19 {z}{k1}
+
+vaddps %ymm16, %ymm17, %ymm19
+vaddps (%rax), %ymm17, %ymm19
+vaddps (%rax){1to8}, %ymm17, %ymm19
+vaddps %ymm16, %ymm17, %ymm19 {k1}
+vaddps (%rax), %ymm17, %ymm19 {k1}
+vaddps (%rax){1to8}, %ymm17, %ymm19 {k1}
+vaddps %ymm16, %ymm17, %ymm19 {z}{k1}
+vaddps (%rax), %ymm17, %ymm19 {z}{k1}
+vaddps (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
+
+valignd $1, %xmm16, %xmm17, %xmm19
+valignd $1, (%rax), %xmm17, %xmm19
+valignd $1, (%rax){1to4}, %xmm17, %xmm19
+valignd $1, %xmm16, %xmm17, %xmm19 {k1}
+valignd $1, (%rax), %xmm17, %xmm19 {k1}
+valignd $1, (%rax){1to4}, %xmm17, %xmm19 {k1}
+valignd $1, %xmm16, %xmm17, %xmm19 {z}{k1}
+valignd $1, (%rax), %xmm17, %xmm19 {z}{k1}
+valignd $1, (%rax){1to4}, %xmm17, %xmm19 {z}{k1}
+
+valignd $1, %ymm16, %ymm17, %ymm19
+valignd $1, (%rax), %ymm17, %ymm19
+valignd $1, (%rax){1to8}, %ymm17, %ymm19
+valignd $1, %ymm16, %ymm17, %ymm19 {k1}
+valignd $1, (%rax), %ymm17, %ymm19 {k1}
+valignd $1, (%rax){1to8}, %ymm17, %ymm19 {k1}
+valignd $1, %ymm16, %ymm17, %ymm19 {z}{k1}
+valignd $1, (%rax), %ymm17, %ymm19 {z}{k1}
+valignd $1, (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
+
+valignq $1, %xmm16, %xmm17, %xmm19
+valignq $1, (%rax), %xmm17, %xmm19
+valignq $1, (%rax){1to2}, %xmm17, %xmm19
+valignq $1, %xmm16, %xmm17, %xmm19 {k1}
+valignq $1, (%rax), %xmm17, %xmm19 {k1}
+valignq $1, (%rax){1to2}, %xmm17, %xmm19 {k1}
+valignq $1, %xmm16, %xmm17, %xmm19 {z}{k1}
+valignq $1, (%rax), %xmm17, %xmm19 {z}{k1}
+valignq $1, (%rax){1to2}, %xmm17, %xmm19 {z}{k1}
+
+valignq $1, %ymm16, %ymm17, %ymm19
+valignq $1, (%rax), %ymm17, %ymm19
+valignq $1, (%rax){1to4}, %ymm17, %ymm19
+valignq $1, %ymm16, %ymm17, %ymm19 {k1}
+valignq $1, (%rax), %ymm17, %ymm19 {k1}
+valignq $1, (%rax){1to4}, %ymm17, %ymm19 {k1}
+valignq $1, %ymm16, %ymm17, %ymm19 {z}{k1}
+valignq $1, (%rax), %ymm17, %ymm19 {z}{k1}
+valignq $1, (%rax){1to4}, %ymm17, %ymm19 {z}{k1}
+
+vbroadcastf32x4 (%rax), %ymm19
+vbroadcastf32x4 (%rax), %ymm19 {k1}
+vbroadcastf32x4 (%rax), %ymm19 {z}{k1}
+
+vbroadcasti32x4 (%rax), %ymm19
+vbroadcasti32x4 (%rax), %ymm19 {k1}
+vbroadcasti32x4 (%rax), %ymm19 {z}{k1}
+
+vbroadcastsd %xmm16, %ymm19
+vbroadcastsd (%rax), %ymm19
+vbroadcastsd %xmm16, %ymm19 {k1}
+vbroadcastsd (%rax), %ymm19 {k1}
+vbroadcastsd %xmm16, %ymm19 {z}{k1}
+vbroadcastsd (%rax), %ymm19 {z}{k1}
+
+vbroadcastss %xmm16, %xmm19
+vbroadcastss (%rax), %xmm19
+vbroadcastss %xmm16, %xmm19 {k1}
+vbroadcastss (%rax), %xmm19 {k1}
+vbroadcastss %xmm16, %xmm19 {z}{k1}
+vbroadcastss (%rax), %xmm19 {z}{k1}
+
+vbroadcastss %xmm16, %ymm19
+vbroadcastss (%rax), %ymm19
+vbroadcastss %xmm16, %ymm19 {k1}
+vbroadcastss (%rax), %ymm19 {k1}
+vbroadcastss %xmm16, %ymm19 {z}{k1}
+vbroadcastss (%rax), %ymm19 {z}{k1}
+
+vcmppd $0, %xmm0, %xmm1, %k2
+vcmppd $0, (%rax), %xmm1, %k2
+vcmppd $0, (%rax){1to2}, %xmm1, %k2
+vcmppd $0, %xmm0, %xmm1, %k2 {k3}
+vcmppd $0, (%rax), %xmm1, %k2 {k3}
+vcmppd $0, (%rax){1to2}, %xmm1, %k2 {k3}
+
+vcmppd $0, %ymm0, %ymm1, %k2
+vcmppd $0, (%rax), %ymm1, %k2
+vcmppd $0, (%rax){1to4}, %ymm1, %k2
+vcmppd $0, %ymm0, %ymm1, %k2 {k3}
+vcmppd $0, (%rax), %ymm1, %k2 {k3}
+vcmppd $0, (%rax){1to4}, %ymm1, %k2 {k3}
+
+vcmpps $0, %xmm0, %xmm1, %k2
+vcmpps $0, (%rax), %xmm1, %k2
+vcmpps $0, (%rax){1to4}, %xmm1, %k2
+vcmpps $0, %xmm0, %xmm1, %k2 {k3}
+vcmpps $0, (%rax), %xmm1, %k2 {k3}
+vcmpps $0, (%rax){1to4}, %xmm1, %k2 {k3}
+
+vcmpps $0, %ymm0, %ymm1, %k2
+vcmpps $0, (%rax), %ymm1, %k2
+vcmpps $0, (%rax){1to8}, %ymm1, %k2
+vcmpps $0, %ymm0, %ymm1, %k2 {k3}
+vcmpps $0, (%rax), %ymm1, %k2 {k3}
+vcmpps $0, (%rax){1to8}, %ymm1, %k2 {k3}
+
+vcvtdq2pd %xmm16, %xmm19
+vcvtdq2pd (%rax), %xmm19
+vcvtdq2pd (%rax){1to2}, %xmm19
+vcvtdq2pd %xmm16, %xmm19 {k1}
+vcvtdq2pd (%rax), %xmm19 {k1}
+vcvtdq2pd (%rax){1to2}, %xmm19 {k1}
+vcvtdq2pd %xmm16, %xmm19 {z}{k1}
+vcvtdq2pd (%rax), %xmm19 {z}{k1}
+vcvtdq2pd (%rax){1to2}, %xmm19 {z}{k1}
+
+vcvtdq2pd %xmm16, %ymm19
+vcvtdq2pd (%rax), %ymm19
+vcvtdq2pd (%rax){1to4}, %ymm19
+vcvtdq2pd %xmm16, %ymm19 {k1}
+vcvtdq2pd (%rax), %ymm19 {k1}
+vcvtdq2pd (%rax){1to4}, %ymm19 {k1}
+vcvtdq2pd %xmm16, %ymm19 {z}{k1}
+vcvtdq2pd (%rax), %ymm19 {z}{k1}
+vcvtdq2pd (%rax){1to4}, %ymm19 {z}{k1}
+
+vcvtdq2ps %xmm16, %xmm19
+vcvtdq2ps (%rax), %xmm19
+vcvtdq2ps (%rax){1to4}, %xmm19
+vcvtdq2ps %xmm16, %xmm19 {k1}
+vcvtdq2ps (%rax), %xmm19 {k1}
+vcvtdq2ps (%rax){1to4},%xmm19 {k1}
+vcvtdq2ps %xmm16, %xmm19 {z}{k1}
+vcvtdq2ps (%rax), %xmm19 {z}{k1}
+vcvtdq2ps (%rax){1to4}, %xmm19 {z}{k1}
+
+vcvtdq2ps %ymm16, %ymm19
+vcvtdq2ps (%rax), %ymm19
+vcvtdq2ps (%rax){1to8}, %ymm19
+vcvtdq2ps %ymm16,%ymm19 {k1}
+vcvtdq2ps (%rax),%ymm19 {k1}
+vcvtdq2ps (%rax){1to8}, %ymm19 {k1}
+vcvtdq2ps %ymm16, %ymm19 {z}{k1}
+vcvtdq2ps (%rax), %ymm19 {z}{k1}
+vcvtdq2ps (%rax){1to8}, %ymm19 {z}{k1}
+
+vcvtpd2dqy %ymm16, %xmm19
+vcvtpd2dqy (%rax), %xmm19
+vcvtpd2dqy (%rax){1to4}, %xmm19
+vcvtpd2dqy %ymm16, %xmm19 {k1}
+vcvtpd2dqy (%rax), %xmm19 {k1}
+vcvtpd2dqy (%rax){1to4}, %xmm19 {k1}
+vcvtpd2dqy %ymm16, %xmm19 {z}{k1}
+vcvtpd2dqy (%rax), %xmm19 {z}{k1}
+vcvtpd2dqy (%rax){1to4}, %xmm19 {z}{k1}
+
+vcvtpd2dqx %xmm16, %xmm19
+vcvtpd2dqx (%rax), %xmm19
+vcvtpd2dqx (%rax){1to2}, %xmm19
+vcvtpd2dqx %xmm16, %xmm19 {k1}
+vcvtpd2dqx (%rax), %xmm19 {k1}
+vcvtpd2dqx (%rax){1to2},%xmm19 {k1}
+vcvtpd2dqx %xmm16, %xmm19 {z}{k1}
+vcvtpd2dqx (%rax), %xmm19 {z}{k1}
+vcvtpd2dqx (%rax){1to2}, %xmm19 {z}{k1}
+
+vcvtpd2psy %ymm16, %xmm19
+vcvtpd2psy (%rax), %xmm19
+vcvtpd2psy (%rax){1to4}, %xmm19
+vcvtpd2psy %ymm16, %xmm19 {k1}
+vcvtpd2psy (%rax), %xmm19 {k1}
+vcvtpd2psy (%rax){1to4}, %xmm19 {k1}
+vcvtpd2psy %ymm16, %xmm19 {z}{k1}
+vcvtpd2psy (%rax), %xmm19 {z}{k1}
+vcvtpd2psy (%rax){1to4}, %xmm19 {z}{k1}
+
+vcvtpd2psx %xmm16, %xmm19
+vcvtpd2psx (%rax), %xmm19
+vcvtpd2psx (%rax){1to2}, %xmm19
+vcvtpd2psx %xmm16, %xmm19 {k1}
+vcvtpd2psx (%rax), %xmm19 {k1}
+vcvtpd2psx (%rax){1to2},%xmm19 {k1}
+vcvtpd2psx %xmm16, %xmm19 {z}{k1}
+vcvtpd2psx (%rax), %xmm19 {z}{k1}
+vcvtpd2psx (%rax){1to2}, %xmm19 {z}{k1}
+
+vcvtpd2udqy %ymm16, %xmm19
+vcvtpd2udqy (%rax), %xmm19
+vcvtpd2udqy (%rax){1to4}, %xmm19
+vcvtpd2udqy %ymm16, %xmm19 {k1}
+vcvtpd2udqy (%rax), %xmm19 {k1}
+vcvtpd2udqy (%rax){1to4}, %xmm19 {k1}
+vcvtpd2udqy %ymm16, %xmm19 {z}{k1}
+vcvtpd2udqy (%rax), %xmm19 {z}{k1}
+vcvtpd2udqy (%rax){1to4}, %xmm19 {z}{k1}
+
+vcvtpd2udqx %xmm16, %xmm19
+vcvtpd2udqx (%rax), %xmm19
+vcvtpd2udqx (%rax){1to2}, %xmm19
+vcvtpd2udqx %xmm16, %xmm19 {k1}
+vcvtpd2udqx (%rax), %xmm19 {k1}
+vcvtpd2udqx (%rax){1to2},%xmm19 {k1}
+vcvtpd2udqx %xmm16, %xmm19 {z}{k1}
+vcvtpd2udqx (%rax), %xmm19 {z}{k1}
+vcvtpd2udqx (%rax){1to2}, %xmm19 {z}{k1}
+
+vcvtps2dq %xmm16, %xmm19
+vcvtps2dq (%rax), %xmm19
+vcvtps2dq (%rax){1to4}, %xmm19
+vcvtps2dq %xmm16, %xmm19 {k1}
+vcvtps2dq (%rax), %xmm19 {k1}
+vcvtps2dq (%rax){1to4},%xmm19 {k1}
+vcvtps2dq %xmm16, %xmm19 {z}{k1}
+vcvtps2dq (%rax), %xmm19 {z}{k1}
+vcvtps2dq (%rax){1to4}, %xmm19 {z}{k1}
+
+vcvtps2dq %ymm16, %ymm19
+vcvtps2dq (%rax), %ymm19
+vcvtps2dq (%rax){1to8}, %ymm19
+vcvtps2dq %ymm16,%ymm19 {k1}
+vcvtps2dq (%rax),%ymm19 {k1}
+vcvtps2dq (%rax){1to8}, %ymm19 {k1}
+vcvtps2dq %ymm16, %ymm19 {z}{k1}
+vcvtps2dq (%rax), %ymm19 {z}{k1}
+vcvtps2dq (%rax){1to8}, %ymm19 {z}{k1}
+
+vcvtps2pd %xmm16, %xmm19
+vcvtps2pd (%rax), %xmm19
+vcvtps2pd (%rax){1to2}, %xmm19
+vcvtps2pd %xmm16, %xmm19 {k1}
+vcvtps2pd (%rax), %xmm19 {k1}
+vcvtps2pd (%rax){1to2},%xmm19 {k1}
+vcvtps2pd %xmm16, %xmm19 {z}{k1}
+vcvtps2pd (%rax), %xmm19 {z}{k1}
+vcvtps2pd (%rax){1to2}, %xmm19 {z}{k1}
+
+vcvtps2pd %xmm16, %ymm19
+vcvtps2pd (%rax), %ymm19
+vcvtps2pd (%rax){1to4}, %ymm19
+vcvtps2pd %xmm16,%ymm19 {k1}
+vcvtps2pd (%rax),%ymm19 {k1}
+vcvtps2pd (%rax){1to4}, %ymm19 {k1}
+vcvtps2pd %xmm16, %ymm19 {z}{k1}
+vcvtps2pd (%rax), %ymm19 {z}{k1}
+vcvtps2pd (%rax){1to4}, %ymm19 {z}{k1}
+
+vcvtps2udq %xmm16, %xmm19
+vcvtps2udq (%rax), %xmm19
+vcvtps2udq (%rax){1to4}, %xmm19
+vcvtps2udq %xmm16, %xmm19 {k1}
+vcvtps2udq (%rax), %xmm19 {k1}
+vcvtps2udq (%rax){1to4},%xmm19 {k1}
+vcvtps2udq %xmm16, %xmm19 {z}{k1}
+vcvtps2udq (%rax), %xmm19 {z}{k1}
+vcvtps2udq (%rax){1to4}, %xmm19 {z}{k1}
+
+vcvtps2udq %ymm16, %ymm19
+vcvtps2udq (%rax), %ymm19
+vcvtps2udq (%rax){1to8}, %ymm19
+vcvtps2udq %ymm16,%ymm19 {k1}
+vcvtps2udq (%rax),%ymm19 {k1}
+vcvtps2udq (%rax){1to8}, %ymm19 {k1}
+vcvtps2udq %ymm16, %ymm19 {z}{k1}
+vcvtps2udq (%rax), %ymm19 {z}{k1}
+vcvtps2udq (%rax){1to8}, %ymm19 {z}{k1}
+
+vcvttpd2dqy %ymm16, %xmm19
+vcvttpd2dqy (%rax), %xmm19
+vcvttpd2dqy (%rax){1to4}, %xmm19
+vcvttpd2dqy %ymm16, %xmm19 {k1}
+vcvttpd2dqy (%rax), %xmm19 {k1}
+vcvttpd2dqy (%rax){1to4}, %xmm19 {k1}
+vcvttpd2dqy %ymm16, %xmm19 {z}{k1}
+vcvttpd2dqy (%rax), %xmm19 {z}{k1}
+vcvttpd2dqy (%rax){1to4}, %xmm19 {z}{k1}
+
+vcvttpd2dqx %xmm16, %xmm19
+vcvttpd2dqx (%rax), %xmm19
+vcvttpd2dqx (%rax){1to2}, %xmm19
+vcvttpd2dqx %xmm16, %xmm19 {k1}
+vcvttpd2dqx (%rax), %xmm19 {k1}
+vcvttpd2dqx (%rax){1to2},%xmm19 {k1}
+vcvttpd2dqx %xmm16, %xmm19 {z}{k1}
+vcvttpd2dqx (%rax), %xmm19 {z}{k1}
+vcvttpd2dqx (%rax){1to2}, %xmm19 {z}{k1}
+
+vcvttps2dq %xmm16, %xmm19
+vcvttps2dq (%rax), %xmm19
+vcvttps2dq (%rax){1to4}, %xmm19
+vcvttps2dq %xmm16, %xmm19 {k1}
+vcvttps2dq (%rax), %xmm19 {k1}
+vcvttps2dq (%rax){1to4},%xmm19 {k1}
+vcvttps2dq %xmm16, %xmm19 {z}{k1}
+vcvttps2dq (%rax), %xmm19 {z}{k1}
+vcvttps2dq (%rax){1to4}, %xmm19 {z}{k1}
+
+vcvttps2dq %ymm16, %ymm19
+vcvttps2dq (%rax), %ymm19
+vcvttps2dq (%rax){1to8}, %ymm19
+vcvttps2dq %ymm16,%ymm19 {k1}
+vcvttps2dq (%rax),%ymm19 {k1}
+vcvttps2dq (%rax){1to8}, %ymm19 {k1}
+vcvttps2dq %ymm16, %ymm19 {z}{k1}
+vcvttps2dq (%rax), %ymm19 {z}{k1}
+vcvttps2dq (%rax){1to8}, %ymm19 {z}{k1}
+
+vcvttpd2udqy %ymm16, %xmm19
+vcvttpd2udqy (%rax), %xmm19
+vcvttpd2udqy (%rax){1to4}, %xmm19
+vcvttpd2udqy %ymm16, %xmm19 {k1}
+vcvttpd2udqy (%rax), %xmm19 {k1}
+vcvttpd2udqy (%rax){1to4}, %xmm19 {k1}
+vcvttpd2udqy %ymm16, %xmm19 {z}{k1}
+vcvttpd2udqy (%rax), %xmm19 {z}{k1}
+vcvttpd2udqy (%rax){1to4}, %xmm19 {z}{k1}
+
+vcvttpd2udqx %xmm16, %xmm19
+vcvttpd2udqx (%rax), %xmm19
+vcvttpd2udqx (%rax){1to2}, %xmm19
+vcvttpd2udqx %xmm16, %xmm19 {k1}
+vcvttpd2udqx (%rax), %xmm19 {k1}
+vcvttpd2udqx (%rax){1to2},%xmm19 {k1}
+vcvttpd2udqx %xmm16, %xmm19 {z}{k1}
+vcvttpd2udqx (%rax), %xmm19 {z}{k1}
+vcvttpd2udqx (%rax){1to2}, %xmm19 {z}{k1}
+
+vcvttps2udq %xmm16, %xmm19
+vcvttps2udq (%rax), %xmm19
+vcvttps2udq (%rax){1to4}, %xmm19
+vcvttps2udq %xmm16, %xmm19 {k1}
+vcvttps2udq (%rax), %xmm19 {k1}
+vcvttps2udq (%rax){1to4},%xmm19 {k1}
+vcvttps2udq %xmm16, %xmm19 {z}{k1}
+vcvttps2udq (%rax), %xmm19 {z}{k1}
+vcvttps2udq (%rax){1to4}, %xmm19 {z}{k1}
+
+vcvttps2udq %ymm16, %ymm19
+vcvttps2udq (%rax), %ymm19
+vcvttps2udq (%rax){1to8}, %ymm19
+vcvttps2udq %ymm16,%ymm19 {k1}
+vcvttps2udq (%rax),%ymm19 {k1}
+vcvttps2udq (%rax){1to8}, %ymm19 {k1}
+vcvttps2udq %ymm16, %ymm19 {z}{k1}
+vcvttps2udq (%rax), %ymm19 {z}{k1}
+vcvttps2udq (%rax){1to8}, %ymm19 {z}{k1}
+
+vdivpd %xmm16, %xmm17, %xmm19
+vdivpd (%rax), %xmm17, %xmm19
+vdivpd (%rax){1to2}, %xmm17, %xmm19
+vdivpd %xmm16, %xmm17, %xmm19 {k1}
+vdivpd (%rax), %xmm17, %xmm19 {k1}
+vdivpd (%rax){1to2}, %xmm17, %xmm19 {k1}
+vdivpd %xmm16, %xmm17, %xmm19 {z}{k1}
+vdivpd (%rax), %xmm17, %xmm19 {z}{k1}
+vdivpd (%rax){1to2}, %xmm17, %xmm19 {z}{k1}
+
+vdivpd %ymm16, %ymm17, %ymm19
+vdivpd (%rax), %ymm17, %ymm19
+vdivpd (%rax){1to4}, %ymm17, %ymm19
+vdivpd %ymm16, %ymm17, %ymm19 {k1}
+vdivpd (%rax), %ymm17, %ymm19 {k1}
+vdivpd (%rax){1to4}, %ymm17, %ymm19 {k1}
+vdivpd %ymm16, %ymm17, %ymm19 {z}{k1}
+vdivpd (%rax), %ymm17, %ymm19 {z}{k1}
+vdivpd (%rax){1to4}, %ymm17, %ymm19 {z}{k1}
+
+vdivps %xmm16, %xmm17, %xmm19
+vdivps (%rax), %xmm17, %xmm19
+vdivps (%rax){1to4}, %xmm17, %xmm19
+vdivps %xmm16, %xmm17, %xmm19 {k1}
+vdivps (%rax), %xmm17, %xmm19 {k1}
+vdivps (%rax){1to4}, %xmm17, %xmm19 {k1}
+vdivps %xmm16, %xmm17, %xmm19 {z}{k1}
+vdivps (%rax), %xmm17, %xmm19 {z}{k1}
+vdivps (%rax){1to4}, %xmm17, %xmm19 {z}{k1}
+
+vdivps %ymm16, %ymm17, %ymm19
+vdivps (%rax), %ymm17, %ymm19
+vdivps (%rax){1to8}, %ymm17, %ymm19
+vdivps %ymm16, %ymm17, %ymm19 {k1}
+vdivps (%rax), %ymm17, %ymm19 {k1}
+vdivps (%rax){1to8}, %ymm17, %ymm19 {k1}
+vdivps %ymm16, %ymm17, %ymm19 {z}{k1}
+vdivps (%rax), %ymm17, %ymm19 {z}{k1}
+vdivps (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
+
+vfmadd132pd %xmm16, %xmm17, %xmm19
+vfmadd132pd (%rax), %xmm17, %xmm19
+vfmadd132pd (%rax){1to2}, %xmm17, %xmm19
+vfmadd132pd %xmm16, %xmm17, %xmm19 {k1}
+vfmadd132pd (%rax), %xmm17, %xmm19 {k1}
+vfmadd132pd (%rax){1to2}, %xmm17, %xmm19 {k1}
+vfmadd132pd %xmm16, %xmm17, %xmm19 {z}{k1}
+vfmadd132pd (%rax), %xmm17, %xmm19 {z}{k1}
+vfmadd132pd (%rax){1to2}, %xmm17, %xmm19 {z}{k1}
+
+vfmadd132pd %ymm16, %ymm17, %ymm19
+vfmadd132pd (%rax), %ymm17, %ymm19
+vfmadd132pd (%rax){1to4}, %ymm17, %ymm19
+vfmadd132pd %ymm16, %ymm17, %ymm19 {k1}
+vfmadd132pd (%rax), %ymm17, %ymm19 {k1}
+vfmadd132pd (%rax){1to4}, %ymm17, %ymm19 {k1}
+vfmadd132pd %ymm16, %ymm17, %ymm19 {z}{k1}
+vfmadd132pd (%rax), %ymm17, %ymm19 {z}{k1}
+vfmadd132pd (%rax){1to4}, %ymm17, %ymm19 {z}{k1}
+
+vfmadd213pd %xmm16, %xmm17, %xmm19
+vfmadd213pd (%rax), %xmm17, %xmm19
+vfmadd213pd (%rax){1to2}, %xmm17, %xmm19
+vfmadd213pd %xmm16, %xmm17, %xmm19 {k1}
+vfmadd213pd (%rax), %xmm17, %xmm19 {k1}
+vfmadd213pd (%rax){1to2}, %xmm17, %xmm19 {k1}
+vfmadd213pd %xmm16, %xmm17, %xmm19 {z}{k1}
+vfmadd213pd (%rax), %xmm17, %xmm19 {z}{k1}
+vfmadd213pd (%rax){1to2}, %xmm17, %xmm19 {z}{k1}
+
+vfmadd213pd %ymm16, %ymm17, %ymm19
+vfmadd213pd (%rax), %ymm17, %ymm19
+vfmadd213pd (%rax){1to4}, %ymm17, %ymm19
+vfmadd213pd %ymm16, %ymm17, %ymm19 {k1}
+vfmadd213pd (%rax), %ymm17, %ymm19 {k1}
+vfmadd213pd (%rax){1to4}, %ymm17, %ymm19 {k1}
+vfmadd213pd %ymm16, %ymm17, %ymm19 {z}{k1}
+vfmadd213pd (%rax), %ymm17, %ymm19 {z}{k1}
+vfmadd213pd (%rax){1to4}, %ymm17, %ymm19 {z}{k1}
+
+vfmadd231pd %xmm16, %xmm17, %xmm19
+vfmadd231pd (%rax), %xmm17, %xmm19
+vfmadd231pd (%rax){1to2}, %xmm17, %xmm19
+vfmadd231pd %xmm16, %xmm17, %xmm19 {k1}
+vfmadd231pd (%rax), %xmm17, %xmm19 {k1}
+vfmadd231pd (%rax){1to2}, %xmm17, %xmm19 {k1}
+vfmadd231pd %xmm16, %xmm17, %xmm19 {z}{k1}
+vfmadd231pd (%rax), %xmm17, %xmm19 {z}{k1}
+vfmadd231pd (%rax){1to2}, %xmm17, %xmm19 {z}{k1}
+
+vfmadd231pd %ymm16, %ymm17, %ymm19
+vfmadd231pd (%rax), %ymm17, %ymm19
+vfmadd231pd (%rax){1to4}, %ymm17, %ymm19
+vfmadd231pd %ymm16, %ymm17, %ymm19 {k1}
+vfmadd231pd (%rax), %ymm17, %ymm19 {k1}
+vfmadd231pd (%rax){1to4}, %ymm17, %ymm19 {k1}
+vfmadd231pd %ymm16, %ymm17, %ymm19 {z}{k1}
+vfmadd231pd (%rax), %ymm17, %ymm19 {z}{k1}
+vfmadd231pd (%rax){1to4}, %ymm17, %ymm19 {z}{k1}
+
+vfmadd132ps %xmm16, %xmm17, %xmm19
+vfmadd132ps (%rax), %xmm17, %xmm19
+vfmadd132ps (%rax){1to4}, %xmm17, %xmm19
+vfmadd132ps %xmm16, %xmm17, %xmm19 {k1}
+vfmadd132ps (%rax), %xmm17, %xmm19 {k1}
+vfmadd132ps (%rax){1to4}, %xmm17, %xmm19 {k1}
+vfmadd132ps %xmm16, %xmm17, %xmm19 {z}{k1}
+vfmadd132ps (%rax), %xmm17, %xmm19 {z}{k1}
+vfmadd132ps (%rax){1to4}, %xmm17, %xmm19 {z}{k1}
+
+vfmadd132ps %ymm16, %ymm17, %ymm19
+vfmadd132ps (%rax), %ymm17, %ymm19
+vfmadd132ps (%rax){1to8}, %ymm17, %ymm19
+vfmadd132ps %ymm16, %ymm17, %ymm19 {k1}
+vfmadd132ps (%rax), %ymm17, %ymm19 {k1}
+vfmadd132ps (%rax){1to8}, %ymm17, %ymm19 {k1}
+vfmadd132ps %ymm16, %ymm17, %ymm19 {z}{k1}
+vfmadd132ps (%rax), %ymm17, %ymm19 {z}{k1}
+vfmadd132ps (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
+
+vfmadd213ps %xmm16, %xmm17, %xmm19
+vfmadd213ps (%rax), %xmm17, %xmm19
+vfmadd213ps (%rax){1to4}, %xmm17, %xmm19
+vfmadd213ps %xmm16, %xmm17, %xmm19 {k1}
+vfmadd213ps (%rax), %xmm17, %xmm19 {k1}
+vfmadd213ps (%rax){1to4}, %xmm17, %xmm19 {k1}
+vfmadd213ps %xmm16, %xmm17, %xmm19 {z}{k1}
+vfmadd213ps (%rax), %xmm17, %xmm19 {z}{k1}
+vfmadd213ps (%rax){1to4}, %xmm17, %xmm19 {z}{k1}
+
+vfmadd213ps %ymm16, %ymm17, %ymm19
+vfmadd213ps (%rax), %ymm17, %ymm19
+vfmadd213ps (%rax){1to8}, %ymm17, %ymm19
+vfmadd213ps %ymm16, %ymm17, %ymm19 {k1}
+vfmadd213ps (%rax), %ymm17, %ymm19 {k1}
+vfmadd213ps (%rax){1to8}, %ymm17, %ymm19 {k1}
+vfmadd213ps %ymm16, %ymm17, %ymm19 {z}{k1}
+vfmadd213ps (%rax), %ymm17, %ymm19 {z}{k1}
+vfmadd213ps (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
+
+vfmadd231ps %xmm16, %xmm17, %xmm19
+vfmadd231ps (%rax), %xmm17, %xmm19
+vfmadd231ps (%rax){1to4}, %xmm17, %xmm19
+vfmadd231ps %xmm16, %xmm17, %xmm19 {k1}
+vfmadd231ps (%rax), %xmm17, %xmm19 {k1}
+vfmadd231ps (%rax){1to4}, %xmm17, %xmm19 {k1}
+vfmadd231ps %xmm16, %xmm17, %xmm19 {z}{k1}
+vfmadd231ps (%rax), %xmm17, %xmm19 {z}{k1}
+vfmadd231ps (%rax){1to4}, %xmm17, %xmm19 {z}{k1}
+
+vfmadd231ps %ymm16, %ymm17, %ymm19
+vfmadd231ps (%rax), %ymm17, %ymm19
+vfmadd231ps (%rax){1to8}, %ymm17, %ymm19
+vfmadd231ps %ymm16, %ymm17, %ymm19 {k1}
+vfmadd231ps (%rax), %ymm17, %ymm19 {k1}
+vfmadd231ps (%rax){1to8}, %ymm17, %ymm19 {k1}
+vfmadd231ps %ymm16, %ymm17, %ymm19 {z}{k1}
+vfmadd231ps (%rax), %ymm17, %ymm19 {z}{k1}
+vfmadd231ps (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
+
+vgatherdpd (%rax,%xmm1,2), %ymm2 {k1}
+vgatherdps (%rax,%ymm1,2), %ymm2 {k1}
+vgatherqpd (%rax,%ymm1,2), %ymm2 {k1}
+vgatherqps (%rax,%ymm1,2), %xmm2 {k1}
+
+vgatherdpd (%rax,%xmm1,2), %xmm2 {k1}
+vgatherdps (%rax,%xmm1,2), %xmm2 {k1}
+vgatherqpd (%rax,%xmm1,2), %xmm2 {k1}
+vgatherqps (%rax,%xmm1,2), %xmm2 {k1}
+
+vmaxpd %xmm16, %xmm17, %xmm19
+vmaxpd (%rax), %xmm17, %xmm19
+vmaxpd (%rax){1to2}, %xmm17, %xmm19
+vmaxpd %xmm16, %xmm17, %xmm19 {k1}
+vmaxpd (%rax), %xmm17, %xmm19 {k1}
+vmaxpd (%rax){1to2}, %xmm17, %xmm19 {k1}
+vmaxpd %xmm16, %xmm17, %xmm19 {z}{k1}
+vmaxpd (%rax), %xmm17, %xmm19 {z}{k1}
+vmaxpd (%rax){1to2}, %xmm17, %xmm19 {z}{k1}
+
+vmaxpd %ymm16, %ymm17, %ymm19
+vmaxpd (%rax), %ymm17, %ymm19
+vmaxpd (%rax){1to4}, %ymm17, %ymm19
+vmaxpd %ymm16, %ymm17, %ymm19 {k1}
+vmaxpd (%rax), %ymm17, %ymm19 {k1}
+vmaxpd (%rax){1to4}, %ymm17, %ymm19 {k1}
+vmaxpd %ymm16, %ymm17, %ymm19 {z}{k1}
+vmaxpd (%rax), %ymm17, %ymm19 {z}{k1}
+vmaxpd (%rax){1to4}, %ymm17, %ymm19 {z}{k1}
+
+vmaxps %xmm16, %xmm17, %xmm19
+vmaxps (%rax), %xmm17, %xmm19
+vmaxps (%rax){1to4}, %xmm17, %xmm19
+vmaxps %xmm16, %xmm17, %xmm19 {k1}
+vmaxps (%rax), %xmm17, %xmm19 {k1}
+vmaxps (%rax){1to4}, %xmm17, %xmm19 {k1}
+vmaxps %xmm16, %xmm17, %xmm19 {z}{k1}
+vmaxps (%rax), %xmm17, %xmm19 {z}{k1}
+vmaxps (%rax){1to4}, %xmm17, %xmm19 {z}{k1}
+
+vmaxps %ymm16, %ymm17, %ymm19
+vmaxps (%rax), %ymm17, %ymm19
+vmaxps (%rax){1to8}, %ymm17, %ymm19
+vmaxps %ymm16, %ymm17, %ymm19 {k1}
+vmaxps (%rax), %ymm17, %ymm19 {k1}
+vmaxps (%rax){1to8}, %ymm17, %ymm19 {k1}
+vmaxps %ymm16, %ymm17, %ymm19 {z}{k1}
+vmaxps (%rax), %ymm17, %ymm19 {z}{k1}
+vmaxps (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
+
+vminpd %xmm16, %xmm17, %xmm19
+vminpd (%rax), %xmm17, %xmm19
+vminpd (%rax){1to2}, %xmm17, %xmm19
+vminpd %xmm16, %xmm17, %xmm19 {k1}
+vminpd (%rax), %xmm17, %xmm19 {k1}
+vminpd (%rax){1to2}, %xmm17, %xmm19 {k1}
+vminpd %xmm16, %xmm17, %xmm19 {z}{k1}
+vminpd (%rax), %xmm17, %xmm19 {z}{k1}
+vminpd (%rax){1to2}, %xmm17, %xmm19 {z}{k1}
+
+vminpd %ymm16, %ymm17, %ymm19
+vminpd (%rax), %ymm17, %ymm19
+vminpd (%rax){1to4}, %ymm17, %ymm19
+vminpd %ymm16, %ymm17, %ymm19 {k1}
+vminpd (%rax), %ymm17, %ymm19 {k1}
+vminpd (%rax){1to4}, %ymm17, %ymm19 {k1}
+vminpd %ymm16, %ymm17, %ymm19 {z}{k1}
+vminpd (%rax), %ymm17, %ymm19 {z}{k1}
+vminpd (%rax){1to4}, %ymm17, %ymm19 {z}{k1}
+
+vminps %xmm16, %xmm17, %xmm19
+vminps (%rax), %xmm17, %xmm19
+vminps (%rax){1to4}, %xmm17, %xmm19
+vminps %xmm16, %xmm17, %xmm19 {k1}
+vminps (%rax), %xmm17, %xmm19 {k1}
+vminps (%rax){1to4}, %xmm17, %xmm19 {k1}
+vminps %xmm16, %xmm17, %xmm19 {z}{k1}
+vminps (%rax), %xmm17, %xmm19 {z}{k1}
+vminps (%rax){1to4}, %xmm17, %xmm19 {z}{k1}
+
+vminps %ymm16, %ymm17, %ymm19
+vminps (%rax), %ymm17, %ymm19
+vminps (%rax){1to8}, %ymm17, %ymm19
+vminps %ymm16, %ymm17, %ymm19 {k1}
+vminps (%rax), %ymm17, %ymm19 {k1}
+vminps (%rax){1to8}, %ymm17, %ymm19 {k1}
+vminps %ymm16, %ymm17, %ymm19 {z}{k1}
+vminps (%rax), %ymm17, %ymm19 {z}{k1}
+vminps (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
+
+vmovapd %xmm16, %xmm19
+vmovapd (%rax), %xmm19
+vmovapd %xmm16, (%rax)
+vmovapd %xmm16, %xmm19 {k1}
+vmovapd (%rax), %xmm19 {k1}
+vmovapd %xmm16, (%rax) {k1}
+vmovapd %xmm16, %xmm19 {z}{k1}
+vmovapd (%rax), %xmm19 {z}{k1}
+
+vmovapd %ymm16, %ymm19
+vmovapd (%rax), %ymm19
+vmovapd %ymm16, (%rax)
+vmovapd %ymm16, %ymm19 {k1}
+vmovapd (%rax), %ymm19 {k1}
+vmovapd %ymm16, (%rax) {k1}
+vmovapd %ymm16, %ymm19 {z}{k1}
+vmovapd (%rax), %ymm19 {z}{k1}
+
+vmovaps %xmm16, %xmm19
+vmovaps (%rax), %xmm19
+vmovaps %xmm16, (%rax)
+vmovaps %xmm16, %xmm19 {k1}
+vmovaps (%rax), %xmm19 {k1}
+vmovaps %xmm16, (%rax) {k1}
+vmovaps %xmm16, %xmm19 {z}{k1}
+vmovaps (%rax), %xmm19 {z}{k1}
+
+vmovaps %ymm16, %ymm19
+vmovaps (%rax), %ymm19
+vmovaps %ymm16, (%rax)
+vmovaps %ymm16, %ymm19 {k1}
+vmovaps (%rax), %ymm19 {k1}
+vmovaps %ymm16, (%rax) {k1}
+vmovaps %ymm16, %ymm19 {z}{k1}
+vmovaps (%rax), %ymm19 {z}{k1}
+
+vmovddup %xmm16, %xmm19
+vmovddup (%rax), %xmm19
+vmovddup %xmm16, %xmm19 {k1}
+vmovddup (%rax), %xmm19 {k1}
+vmovddup %xmm16, %xmm19 {z}{k1}
+vmovddup (%rax), %xmm19 {z}{k1}
+
+vmovdqa32 %xmm16, %xmm19
+vmovdqa32 (%rax), %xmm19
+vmovdqa32 %xmm16, (%rax)
+vmovdqa32 %xmm16, %xmm19 {k1}
+vmovdqa32 (%rax), %xmm19 {k1}
+vmovdqa32 %xmm16, (%rax) {k1}
+vmovdqa32 %xmm16, %xmm19 {z}{k1}
+vmovdqa32 (%rax), %xmm19 {z}{k1}
+
+vmovdqa32 %ymm16, %ymm19
+vmovdqa32 (%rax), %ymm19
+vmovdqa32 %ymm16, (%rax)
+vmovdqa32 %ymm16, %ymm19 {k1}
+vmovdqa32 (%rax), %ymm19 {k1}
+vmovdqa32 %ymm16, (%rax) {k1}
+vmovdqa32 %ymm16, %ymm19 {z}{k1}
+vmovdqa32 (%rax), %ymm19 {z}{k1}
+
+vmovdqa64 %xmm16, %xmm19
+vmovdqa64 (%rax), %xmm19
+vmovdqa64 %xmm16, (%rax)
+vmovdqa64 %xmm16, %xmm19 {k1}
+vmovdqa64 (%rax), %xmm19 {k1}
+vmovdqa64 %xmm16, (%rax) {k1}
+vmovdqa64 %xmm16, %xmm19 {z}{k1}
+vmovdqa64 (%rax), %xmm19 {z}{k1}
+
+vmovdqa64 %ymm16, %ymm19
+vmovdqa64 (%rax), %ymm19
+vmovdqa64 %ymm16, (%rax)
+vmovdqa64 %ymm16, %ymm19 {k1}
+vmovdqa64 (%rax), %ymm19 {k1}
+vmovdqa64 %ymm16, (%rax) {k1}
+vmovdqa64 %ymm16, %ymm19 {z}{k1}
+vmovdqa64 (%rax), %ymm19 {z}{k1}
+
+vmovdqu32 %xmm16, %xmm19
+vmovdqu32 (%rax), %xmm19
+vmovdqu32 %xmm16, (%rax)
+vmovdqu32 %xmm16, %xmm19 {k1}
+vmovdqu32 (%rax), %xmm19 {k1}
+vmovdqu32 %xmm16, (%rax) {k1}
+vmovdqu32 %xmm16, %xmm19 {z}{k1}
+vmovdqu32 (%rax), %xmm19 {z}{k1}
+
+vmovdqu32 %ymm16, %ymm19
+vmovdqu32 (%rax), %ymm19
+vmovdqu32 %ymm16, (%rax)
+vmovdqu32 %ymm16, %ymm19 {k1}
+vmovdqu32 (%rax), %ymm19 {k1}
+vmovdqu32 %ymm16, (%rax) {k1}
+vmovdqu32 %ymm16, %ymm19 {z}{k1}
+vmovdqu32 (%rax), %ymm19 {z}{k1}
+
+vmovdqu64 %xmm16, %xmm19
+vmovdqu64 (%rax), %xmm19
+vmovdqu64 %xmm16, (%rax)
+vmovdqu64 %xmm16, %xmm19 {k1}
+vmovdqu64 (%rax), %xmm19 {k1}
+vmovdqu64 %xmm16, (%rax) {k1}
+vmovdqu64 %xmm16, %xmm19 {z}{k1}
+vmovdqu64 (%rax), %xmm19 {z}{k1}
+
+vmovdqu64 %ymm16, %ymm19
+vmovdqu64 (%rax), %ymm19
+vmovdqu64 %ymm16, (%rax)
+vmovdqu64 %ymm16, %ymm19 {k1}
+vmovdqu64 (%rax), %ymm19 {k1}
+vmovdqu64 %ymm16, (%rax) {k1}
+vmovdqu64 %ymm16, %ymm19 {z}{k1}
+vmovdqu64 (%rax), %ymm19 {z}{k1}
+
+vmovddup %ymm16, %ymm19
+vmovddup (%rax), %ymm19
+vmovddup %ymm16, %ymm19 {k1}
+vmovddup (%rax), %ymm19 {k1}
+vmovddup %ymm16, %ymm19 {z}{k1}
+vmovddup (%rax), %ymm19 {z}{k1}
+
+{evex} vmovntdqa (%rax), %xmm0
+{evex} vmovntdqa (%rax), %ymm0
+
+vmovshdup %xmm16, %xmm19
+vmovshdup (%rax), %xmm19
+vmovshdup %xmm16, %xmm19 {k1}
+vmovshdup (%rax), %xmm19 {k1}
+vmovshdup %xmm16, %xmm19 {z}{k1}
+vmovshdup (%rax), %xmm19 {z}{k1}
+
+vmovshdup %ymm16, %ymm19
+vmovshdup (%rax), %ymm19
+vmovshdup %ymm16, %ymm19 {k1}
+vmovshdup (%rax), %ymm19 {k1}
+vmovshdup %ymm16, %ymm19 {z}{k1}
+vmovshdup (%rax), %ymm19 {z}{k1}
+
+vmovsldup %xmm16, %xmm19
+vmovsldup (%rax), %xmm19
+vmovsldup %xmm16, %xmm19 {k1}
+vmovsldup (%rax), %xmm19 {k1}
+vmovsldup %xmm16, %xmm19 {z}{k1}
+vmovsldup (%rax), %xmm19 {z}{k1}
+
+vmovsldup %ymm16, %ymm19
+vmovsldup (%rax), %ymm19
+vmovsldup %ymm16, %ymm19 {k1}
+vmovsldup (%rax), %ymm19 {k1}
+vmovsldup %ymm16, %ymm19 {z}{k1}
+vmovsldup (%rax), %ymm19 {z}{k1}
+
+vmovupd %xmm16, %xmm19
+vmovupd (%rax), %xmm19
+vmovupd %xmm16, (%rax)
+vmovupd %xmm16, %xmm19 {k1}
+vmovupd (%rax), %xmm19 {k1}
+vmovupd %xmm16, (%rax) {k1}
+vmovupd %xmm16, %xmm19 {z}{k1}
+vmovupd (%rax), %xmm19 {z}{k1}
+
+vmovupd %ymm16, %ymm19
+vmovupd (%rax), %ymm19
+vmovupd %ymm16, (%rax)
+vmovupd %ymm16, %ymm19 {k1}
+vmovupd (%rax), %ymm19 {k1}
+vmovupd %ymm16, (%rax) {k1}
+vmovupd %ymm16, %ymm19 {z}{k1}
+vmovupd (%rax), %ymm19 {z}{k1}
+
+vmovups %xmm16, %xmm19
+vmovups (%rax), %xmm19
+vmovups %xmm16, (%rax)
+vmovups %xmm16, %xmm19 {k1}
+vmovups (%rax), %xmm19 {k1}
+vmovups %xmm16, (%rax) {k1}
+vmovups %xmm16, %xmm19 {z}{k1}
+vmovups (%rax), %xmm19 {z}{k1}
+
+vmovups %ymm16, %ymm19
+vmovups (%rax), %ymm19
+vmovups %ymm16, (%rax)
+vmovups %ymm16, %ymm19 {k1}
+vmovups (%rax), %ymm19 {k1}
+vmovups %ymm16, (%rax) {k1}
+vmovups %ymm16, %ymm19 {z}{k1}
+vmovups (%rax), %ymm19 {z}{k1}
+
+vmulpd %xmm16, %xmm17, %xmm19
+vmulpd (%rax), %xmm17, %xmm19
+vmulpd (%rax){1to2}, %xmm17, %xmm19
+vmulpd %xmm16, %xmm17, %xmm19 {k1}
+vmulpd (%rax), %xmm17, %xmm19 {k1}
+vmulpd (%rax){1to2}, %xmm17, %xmm19 {k1}
+vmulpd %xmm16, %xmm17, %xmm19 {z}{k1}
+vmulpd (%rax), %xmm17, %xmm19 {z}{k1}
+vmulpd (%rax){1to2}, %xmm17, %xmm19 {z}{k1}
+
+vmulpd %ymm16, %ymm17, %ymm19
+vmulpd (%rax), %ymm17, %ymm19
+vmulpd (%rax){1to4}, %ymm17, %ymm19
+vmulpd %ymm16, %ymm17, %ymm19 {k1}
+vmulpd (%rax), %ymm17, %ymm19 {k1}
+vmulpd (%rax){1to4}, %ymm17, %ymm19 {k1}
+vmulpd %ymm16, %ymm17, %ymm19 {z}{k1}
+vmulpd (%rax), %ymm17, %ymm19 {z}{k1}
+vmulpd (%rax){1to4}, %ymm17, %ymm19 {z}{k1}
+
+vmulps %xmm16, %xmm17, %xmm19
+vmulps (%rax), %xmm17, %xmm19
+vmulps (%rax){1to4}, %xmm17, %xmm19
+vmulps %xmm16, %xmm17, %xmm19 {k1}
+vmulps (%rax), %xmm17, %xmm19 {k1}
+vmulps (%rax){1to4}, %xmm17, %xmm19 {k1}
+vmulps %xmm16, %xmm17, %xmm19 {z}{k1}
+vmulps (%rax), %xmm17, %xmm19 {z}{k1}
+vmulps (%rax){1to4}, %xmm17, %xmm19 {z}{k1}
+
+vmulps %ymm16, %ymm17, %ymm19
+vmulps (%rax), %ymm17, %ymm19
+vmulps (%rax){1to8}, %ymm17, %ymm19
+vmulps %ymm16, %ymm17, %ymm19 {k1}
+vmulps (%rax), %ymm17, %ymm19 {k1}
+vmulps (%rax){1to8}, %ymm17, %ymm19 {k1}
+vmulps %ymm16, %ymm17, %ymm19 {z}{k1}
+vmulps (%rax), %ymm17, %ymm19 {z}{k1}
+vmulps (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
+
+vpaddd %xmm16, %xmm17, %xmm19
+vpaddd (%rax), %xmm17, %xmm19
+vpaddd (%rax){1to4}, %xmm17, %xmm19
+vpaddd %xmm16, %xmm17, %xmm19 {k1}
+vpaddd (%rax), %xmm17, %xmm19 {k1}
+vpaddd (%rax){1to4}, %xmm17, %xmm19 {k1}
+vpaddd %xmm16, %xmm17, %xmm19 {z}{k1}
+vpaddd (%rax), %xmm17, %xmm19 {z}{k1}
+vpaddd (%rax){1to4}, %xmm17, %xmm19 {z}{k1}
+
+vpaddd %ymm16, %ymm17, %ymm19
+vpaddd (%rax), %ymm17, %ymm19
+vpaddd (%rax){1to8}, %ymm17, %ymm19
+vpaddd %ymm16, %ymm17, %ymm19 {k1}
+vpaddd (%rax), %ymm17, %ymm19 {k1}
+vpaddd (%rax){1to8}, %ymm17, %ymm19 {k1}
+vpaddd %ymm16, %ymm17, %ymm19 {z}{k1}
+vpaddd (%rax), %ymm17, %ymm19 {z}{k1}
+vpaddd (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
+
+vpaddq %xmm16, %xmm17, %xmm19
+vpaddq (%rax), %xmm17, %xmm19
+vpaddq (%rax){1to2}, %xmm17, %xmm19
+vpaddq %xmm16, %xmm17, %xmm19 {k1}
+vpaddq (%rax), %xmm17, %xmm19 {k1}
+vpaddq (%rax){1to2}, %xmm17, %xmm19 {k1}
+vpaddq %xmm16, %xmm17, %xmm19 {z}{k1}
+vpaddq (%rax), %xmm17, %xmm19 {z}{k1}
+vpaddq (%rax){1to2}, %xmm17, %xmm19 {z}{k1}
+
+vpaddq %ymm16, %ymm17, %ymm19
+vpaddq (%rax), %ymm17, %ymm19
+vpaddq (%rax){1to4}, %ymm17, %ymm19
+vpaddq %ymm16, %ymm17, %ymm19 {k1}
+vpaddq (%rax), %ymm17, %ymm19 {k1}
+vpaddq (%rax){1to4}, %ymm17, %ymm19 {k1}
+vpaddq %ymm16, %ymm17, %ymm19 {z}{k1}
+vpaddq (%rax), %ymm17, %ymm19 {z}{k1}
+vpaddq (%rax){1to4}, %ymm17, %ymm19 {z}{k1}
+
+vpbroadcastd %xmm16, %xmm19
+vpbroadcastd (%rax), %xmm19
+vpbroadcastd %xmm16, %xmm19 {k1}
+vpbroadcastd (%rax), %xmm19 {k1}
+vpbroadcastd %xmm16, %xmm19 {z}{k1}
+vpbroadcastd (%rax), %xmm19 {z}{k1}
+
+vpbroadcastd %xmm16, %ymm19
+vpbroadcastd (%rax), %ymm19
+vpbroadcastd %xmm16, %ymm19 {k1}
+vpbroadcastd (%rax), %ymm19 {k1}
+vpbroadcastd %xmm16, %ymm19 {z}{k1}
+vpbroadcastd (%rax), %ymm19 {z}{k1}
+
+vpbroadcastq %xmm16, %xmm19
+vpbroadcastq (%rax), %xmm19
+vpbroadcastq %xmm16, %xmm19 {k1}
+vpbroadcastq (%rax), %xmm19 {k1}
+vpbroadcastq %xmm16, %xmm19 {z}{k1}
+vpbroadcastq (%rax), %xmm19 {z}{k1}
+
+vpbroadcastq %xmm16, %ymm19
+vpbroadcastq (%rax), %ymm19
+vpbroadcastq %xmm16, %ymm19 {k1}
+vpbroadcastq (%rax), %ymm19 {k1}
+vpbroadcastq %xmm16, %ymm19 {z}{k1}
+vpbroadcastq (%rax), %ymm19 {z}{k1}
+
+vpcmpd $0, %xmm0, %xmm1, %k2
+vpcmpd $0, (%rax), %xmm1, %k2
+vpcmpd $0, (%rax){1to4}, %xmm1, %k2
+vpcmpd $0, %xmm0, %xmm1, %k2 {k3}
+vpcmpd $0, (%rax), %xmm1, %k2 {k3}
+vpcmpd $0, (%rax){1to4}, %xmm1, %k2 {k3}
+
+vpcmpd $0, %ymm0, %ymm1, %k2
+vpcmpd $0, (%rax), %ymm1, %k2
+vpcmpd $0, (%rax){1to8}, %ymm1, %k2
+vpcmpd $0, %ymm0, %ymm1, %k2 {k3}
+vpcmpd $0, (%rax), %ymm1, %k2 {k3}
+vpcmpd $0, (%rax){1to8}, %ymm1, %k2 {k3}
+
+vpcmpeqd %xmm0, %xmm1, %k2
+vpcmpeqd (%rax), %xmm1, %k2
+vpcmpeqd (%rax){1to4}, %xmm1, %k2
+vpcmpeqd %xmm0, %xmm1, %k2 {k3}
+vpcmpeqd (%rax), %xmm1, %k2 {k3}
+vpcmpeqd (%rax){1to4}, %xmm1, %k2 {k3}
+
+vpcmpeqd %ymm0, %ymm1, %k2
+vpcmpeqd (%rax), %ymm1, %k2
+vpcmpeqd (%rax){1to8}, %ymm1, %k2
+vpcmpeqd %ymm0, %ymm1, %k2 {k3}
+vpcmpeqd (%rax), %ymm1, %k2 {k3}
+vpcmpeqd (%rax){1to8}, %ymm1, %k2 {k3}
+
+vpcmpeqq %xmm0, %xmm1, %k2
+vpcmpeqq (%rax), %xmm1, %k2
+vpcmpeqq (%rax){1to2}, %xmm1, %k2
+vpcmpeqq %xmm0, %xmm1, %k2 {k3}
+vpcmpeqq (%rax), %xmm1, %k2 {k3}
+vpcmpeqq (%rax){1to2}, %xmm1, %k2 {k3}
+
+vpcmpeqq %ymm0, %ymm1, %k2
+vpcmpeqq (%rax), %ymm1, %k2
+vpcmpeqq (%rax){1to4}, %ymm1, %k2
+vpcmpeqq %ymm0, %ymm1, %k2 {k3}
+vpcmpeqq (%rax), %ymm1, %k2 {k3}
+vpcmpeqq (%rax){1to4}, %ymm1, %k2 {k3}
+
+vpcmpgtd %xmm0, %xmm1, %k2
+vpcmpgtd (%rax), %xmm1, %k2
+vpcmpgtd (%rax){1to4}, %xmm1, %k2
+vpcmpgtd %xmm0, %xmm1, %k2 {k3}
+vpcmpgtd (%rax), %xmm1, %k2 {k3}
+vpcmpgtd (%rax){1to4}, %xmm1, %k2 {k3}
+
+vpcmpgtd %ymm0, %ymm1, %k2
+vpcmpgtd (%rax), %ymm1, %k2
+vpcmpgtd (%rax){1to8}, %ymm1, %k2
+vpcmpgtd %ymm0, %ymm1, %k2 {k3}
+vpcmpgtd (%rax), %ymm1, %k2 {k3}
+vpcmpgtd (%rax){1to8}, %ymm1, %k2 {k3}
+
+vpcmpgtq %xmm0, %xmm1, %k2
+vpcmpgtq (%rax), %xmm1, %k2
+vpcmpgtq (%rax){1to2}, %xmm1, %k2
+vpcmpgtq %xmm0, %xmm1, %k2 {k3}
+vpcmpgtq (%rax), %xmm1, %k2 {k3}
+vpcmpgtq (%rax){1to2}, %xmm1, %k2 {k3}
+
+vpcmpgtq %ymm0, %ymm1, %k2
+vpcmpgtq (%rax), %ymm1, %k2
+vpcmpgtq (%rax){1to4}, %ymm1, %k2
+vpcmpgtq %ymm0, %ymm1, %k2 {k3}
+vpcmpgtq (%rax), %ymm1, %k2 {k3}
+vpcmpgtq (%rax){1to4}, %ymm1, %k2 {k3}
+
+vpcmpq $0, %xmm0, %xmm1, %k2
+vpcmpq $0, (%rax), %xmm1, %k2
+vpcmpq $0, (%rax){1to2}, %xmm1, %k2
+vpcmpq $0, %xmm0, %xmm1, %k2 {k3}
+vpcmpq $0, (%rax), %xmm1, %k2 {k3}
+vpcmpq $0, (%rax){1to2}, %xmm1, %k2 {k3}
+
+vpcmpq $0, %ymm0, %ymm1, %k2
+vpcmpq $0, (%rax), %ymm1, %k2
+vpcmpq $0, (%rax){1to4}, %ymm1, %k2
+vpcmpq $0, %ymm0, %ymm1, %k2 {k3}
+vpcmpq $0, (%rax), %ymm1, %k2 {k3}
+vpcmpq $0, (%rax){1to4}, %ymm1, %k2 {k3}
+
+vpcmpud $0, %xmm0, %xmm1, %k2
+vpcmpud $0, (%rax), %xmm1, %k2
+vpcmpud $0, (%rax){1to4}, %xmm1, %k2
+vpcmpud $0, %xmm0, %xmm1, %k2 {k3}
+vpcmpud $0, (%rax), %xmm1, %k2 {k3}
+vpcmpud $0, (%rax){1to4}, %xmm1, %k2 {k3}
+
+vpcmpud $0, %ymm0, %ymm1, %k2
+vpcmpud $0, (%rax), %ymm1, %k2
+vpcmpud $0, (%rax){1to8}, %ymm1, %k2
+vpcmpud $0, %ymm0, %ymm1, %k2 {k3}
+vpcmpud $0, (%rax), %ymm1, %k2 {k3}
+vpcmpud $0, (%rax){1to8}, %ymm1, %k2 {k3}
+
+vpcmpuq $0, %xmm0, %xmm1, %k2
+vpcmpuq $0, (%rax), %xmm1, %k2
+vpcmpuq $0, (%rax){1to2}, %xmm1, %k2
+vpcmpuq $0, %xmm0, %xmm1, %k2 {k3}
+vpcmpuq $0, (%rax), %xmm1, %k2 {k3}
+vpcmpuq $0, (%rax){1to2}, %xmm1, %k2 {k3}
+
+vpcmpuq $0, %ymm0, %ymm1, %k2
+vpcmpuq $0, (%rax), %ymm1, %k2
+vpcmpuq $0, (%rax){1to4}, %ymm1, %k2
+vpcmpuq $0, %ymm0, %ymm1, %k2 {k3}
+vpcmpuq $0, (%rax), %ymm1, %k2 {k3}
+vpcmpuq $0, (%rax){1to4}, %ymm1, %k2 {k3}
+
+vpermd %ymm16, %ymm17, %ymm19
+vpermd (%rax), %ymm17, %ymm19
+vpermd (%rax){1to8}, %ymm17, %ymm19
+vpermd %ymm16, %ymm17, %ymm19 {k1}
+vpermd (%rax), %ymm17, %ymm19 {k1}
+vpermd (%rax){1to8}, %ymm17, %ymm19 {k1}
+vpermd %ymm16, %ymm17, %ymm19 {z}{k1}
+vpermd (%rax), %ymm17, %ymm19 {z}{k1}
+vpermd (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
+
+vpermilpd $0, %xmm16, %xmm19
+vpermilpd $0, (%rax), %xmm19
+vpermilpd $0, (%rax){1to2}, %xmm19
+vpermilpd $0, %xmm16, %xmm19 {k1}
+vpermilpd $0, (%rax), %xmm19 {k1}
+vpermilpd $0, (%rax){1to2}, %xmm19 {k1}
+vpermilpd $0, %xmm16, %xmm19 {z}{k1}
+vpermilpd $0, (%rax), %xmm19 {z}{k1}
+vpermilpd $0, (%rax){1to2}, %xmm19 {z}{k1}
+
+vpermilpd $0, %ymm16, %ymm19
+vpermilpd $0, (%rax), %ymm19
+vpermilpd $0, (%rax){1to4}, %ymm19
+vpermilpd $0, %ymm16, %ymm19 {k1}
+vpermilpd $0, (%rax), %ymm19 {k1}
+vpermilpd $0, (%rax){1to4}, %ymm19 {k1}
+vpermilpd $0, %ymm16, %ymm19 {z}{k1}
+vpermilpd $0, (%rax), %ymm19 {z}{k1}
+vpermilpd $0, (%rax){1to4}, %ymm19 {z}{k1}
+
+vpermilpd %xmm16, %xmm17, %xmm19
+vpermilpd (%rax), %xmm17, %xmm19
+vpermilpd (%rax){1to2}, %xmm17, %xmm19
+vpermilpd %xmm16, %xmm17, %xmm19 {k1}
+vpermilpd (%rax), %xmm17, %xmm19 {k1}
+vpermilpd (%rax){1to2}, %xmm17, %xmm19 {k1}
+vpermilpd %xmm16, %xmm17, %xmm19 {z}{k1}
+vpermilpd (%rax), %xmm17, %xmm19 {z}{k1}
+vpermilpd (%rax){1to2}, %xmm17, %xmm19 {z}{k1}
+
+vpermilpd %ymm16, %ymm17, %ymm19
+vpermilpd (%rax), %ymm17, %ymm19
+vpermilpd (%rax){1to4}, %ymm17, %ymm19
+vpermilpd %ymm16, %ymm17, %ymm19 {k1}
+vpermilpd (%rax), %ymm17, %ymm19 {k1}
+vpermilpd (%rax){1to4}, %ymm17, %ymm19 {k1}
+vpermilpd %ymm16, %ymm17, %ymm19 {z}{k1}
+vpermilpd (%rax), %ymm17, %ymm19 {z}{k1}
+vpermilpd (%rax){1to4}, %ymm17, %ymm19 {z}{k1}
+
+vpermilps $0, %xmm16, %xmm19
+vpermilps $0, (%rax), %xmm19
+vpermilps $0, (%rax){1to4}, %xmm19
+vpermilps $0, %xmm16, %xmm19 {k1}
+vpermilps $0, (%rax), %xmm19 {k1}
+vpermilps $0, (%rax){1to4}, %xmm19 {k1}
+vpermilps $0, %xmm16, %xmm19 {z}{k1}
+vpermilps $0, (%rax), %xmm19 {z}{k1}
+vpermilps $0, (%rax){1to4}, %xmm19 {z}{k1}
+
+vpermilps $0, %ymm16, %ymm19
+vpermilps $0, (%rax), %ymm19
+vpermilps $0, (%rax){1to8}, %ymm19
+vpermilps $0, %ymm16, %ymm19 {k1}
+vpermilps $0, (%rax), %ymm19 {k1}
+vpermilps $0, (%rax){1to8}, %ymm19 {k1}
+vpermilps $0, %ymm16, %ymm19 {z}{k1}
+vpermilps $0, (%rax), %ymm19 {z}{k1}
+vpermilps $0, (%rax){1to8}, %ymm19 {z}{k1}
+
+vpermilps %xmm16, %xmm17, %xmm19
+vpermilps (%rax), %xmm17, %xmm19
+vpermilps (%rax){1to4}, %xmm17, %xmm19
+vpermilps %xmm16, %xmm17, %xmm19 {k1}
+vpermilps (%rax), %xmm17, %xmm19 {k1}
+vpermilps (%rax){1to4}, %xmm17, %xmm19 {k1}
+vpermilps %xmm16, %xmm17, %xmm19 {z}{k1}
+vpermilps (%rax), %xmm17, %xmm19 {z}{k1}
+vpermilps (%rax){1to4}, %xmm17, %xmm19 {z}{k1}
+
+vpermilps %ymm16, %ymm17, %ymm19
+vpermilps (%rax), %ymm17, %ymm19
+vpermilps (%rax){1to8}, %ymm17, %ymm19
+vpermilps %ymm16, %ymm17, %ymm19 {k1}
+vpermilps (%rax), %ymm17, %ymm19 {k1}
+vpermilps (%rax){1to8}, %ymm17, %ymm19 {k1}
+vpermilps %ymm16, %ymm17, %ymm19 {z}{k1}
+vpermilps (%rax), %ymm17, %ymm19 {z}{k1}
+vpermilps (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
+
+vpermpd $0, %ymm16, %ymm19
+vpermpd $0, (%rax), %ymm19
+vpermpd $0, (%rax){1to4}, %ymm19
+vpermpd $0, %ymm16, %ymm19 {k1}
+vpermpd $0, (%rax), %ymm19 {k1}
+vpermpd $0, (%rax){1to4}, %ymm19 {k1}
+vpermpd $0, %ymm16, %ymm19 {z}{k1}
+vpermpd $0, (%rax), %ymm19 {z}{k1}
+vpermpd $0, (%rax){1to4}, %ymm19 {z}{k1}
+
+vpermpd %ymm16, %ymm17, %ymm19
+vpermpd (%rax), %ymm17, %ymm19
+vpermpd (%rax){1to4}, %ymm17, %ymm19
+vpermpd %ymm16, %ymm17, %ymm19 {k1}
+vpermpd (%rax), %ymm17, %ymm19 {k1}
+vpermpd (%rax){1to4}, %ymm17, %ymm19 {k1}
+vpermpd %ymm16, %ymm17, %ymm19 {z}{k1}
+vpermpd (%rax), %ymm17, %ymm19 {z}{k1}
+vpermpd (%rax){1to4}, %ymm17, %ymm19 {z}{k1}
+
+vpermps %ymm16, %ymm17, %ymm19
+vpermps (%rax), %ymm17, %ymm19
+vpermps (%rax){1to8}, %ymm17, %ymm19
+vpermps %ymm16, %ymm17, %ymm19 {k1}
+vpermps (%rax), %ymm17, %ymm19 {k1}
+vpermps (%rax){1to8}, %ymm17, %ymm19 {k1}
+vpermps %ymm16, %ymm17, %ymm19 {z}{k1}
+vpermps (%rax), %ymm17, %ymm19 {z}{k1}
+vpermps (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
+
+vpermq $0, %ymm16, %ymm19
+vpermq $0, (%rax), %ymm19
+vpermq $0, (%rax){1to4}, %ymm19
+vpermq $0, %ymm16, %ymm19 {k1}
+vpermq $0, (%rax), %ymm19 {k1}
+vpermq $0, (%rax){1to4}, %ymm19 {k1}
+vpermq $0, %ymm16, %ymm19 {z}{k1}
+vpermq $0, (%rax), %ymm19 {z}{k1}
+vpermq $0, (%rax){1to4}, %ymm19 {z}{k1}
+
+vpermq %ymm16, %ymm17, %ymm19
+vpermq (%rax), %ymm17, %ymm19
+vpermq (%rax){1to4}, %ymm17, %ymm19
+vpermq %ymm16, %ymm17, %ymm19 {k1}
+vpermq (%rax), %ymm17, %ymm19 {k1}
+vpermq (%rax){1to4}, %ymm17, %ymm19 {k1}
+vpermq %ymm16, %ymm17, %ymm19 {z}{k1}
+vpermq (%rax), %ymm17, %ymm19 {z}{k1}
+vpermq (%rax){1to4}, %ymm17, %ymm19 {z}{k1}
+
+vpgatherdq (%rax,%xmm1,2), %ymm2 {k1}
+vpgatherdd (%rax,%ymm1,2), %ymm2 {k1}
+vpgatherqq (%rax,%ymm1,2), %ymm2 {k1}
+vpgatherqd (%rax,%ymm1,2), %xmm2 {k1}
+
+vpgatherdq (%rax,%xmm1,2), %xmm2 {k1}
+vpgatherdd (%rax,%xmm1,2), %xmm2 {k1}
+vpgatherqq (%rax,%xmm1,2), %xmm2 {k1}
+vpgatherqd (%rax,%xmm1,2), %xmm2 {k1}
+
+vpmovdb %xmm19, %xmm16
+vpmovdb %xmm19, (%rax)
+vpmovdb %xmm19, %xmm16 {k1}
+vpmovdb %xmm19, (%rax) {k1}
+vpmovdb %xmm19, %xmm16 {k1}{z}
+
+vpmovdb %ymm19, %xmm16
+vpmovdb %ymm19, (%rax)
+vpmovdb %ymm19, %xmm16 {k1}
+vpmovdb %ymm19, (%rax) {k1}
+vpmovdb %ymm19, %xmm16 {k1}{z}
+
+vpmovdw %xmm19, %xmm16
+vpmovdw %xmm19, (%rax)
+vpmovdw %xmm19, %xmm16 {k1}
+vpmovdw %xmm19, (%rax) {k1}
+vpmovdw %xmm19, %xmm16 {k1}{z}
+
+vpmovdw %ymm19, %xmm16
+vpmovdw %ymm19, (%rax)
+vpmovdw %ymm19, %xmm16 {k1}
+vpmovdw %ymm19, (%rax) {k1}
+vpmovdw %ymm19, %xmm16 {k1}{z}
+
+vpmovqb %xmm19, %xmm16
+vpmovqb %xmm19, (%rax)
+vpmovqb %xmm19, %xmm16 {k1}
+vpmovqb %xmm19, (%rax) {k1}
+vpmovqb %xmm19, %xmm16 {k1}{z}
+
+vpmovqb %ymm19, %xmm16
+vpmovqb %ymm19, (%rax)
+vpmovqb %ymm19, %xmm16 {k1}
+vpmovqb %ymm19, (%rax) {k1}
+vpmovqb %ymm19, %xmm16 {k1}{z}
+
+vpmovqd %xmm19, %xmm16
+vpmovqd %xmm19, (%rax)
+vpmovqd %xmm19, %xmm16 {k1}
+vpmovqd %xmm19, (%rax) {k1}
+vpmovqd %xmm19, %xmm16 {k1}{z}
+
+vpmovqd %ymm19, %xmm16
+vpmovqd %ymm19, (%rax)
+vpmovqd %ymm19, %xmm16 {k1}
+vpmovqd %ymm19, (%rax) {k1}
+vpmovqd %ymm19, %xmm16 {k1}{z}
+
+vpmovqw %xmm19, %xmm16
+vpmovqw %xmm19, (%rax)
+vpmovqw %xmm19, %xmm16 {k1}
+vpmovqw %xmm19, (%rax) {k1}
+vpmovqw %xmm19, %xmm16 {k1}{z}
+
+vpmovqw %ymm19, %xmm16
+vpmovqw %ymm19, (%rax)
+vpmovqw %ymm19, %xmm16 {k1}
+vpmovqw %ymm19, (%rax) {k1}
+vpmovqw %ymm19, %xmm16 {k1}{z}
+
+vpmovsdb %xmm19, %xmm16
+vpmovsdb %xmm19, (%rax)
+vpmovsdb %xmm19, %xmm16 {k1}
+vpmovsdb %xmm19, (%rax) {k1}
+vpmovsdb %xmm19, %xmm16 {k1}{z}
+
+vpmovsdb %ymm19, %xmm16
+vpmovsdb %ymm19, (%rax)
+vpmovsdb %ymm19, %xmm16 {k1}
+vpmovsdb %ymm19, (%rax) {k1}
+vpmovsdb %ymm19, %xmm16 {k1}{z}
+
+vpmovsdw %xmm19, %xmm16
+vpmovsdw %xmm19, (%rax)
+vpmovsdw %xmm19, %xmm16 {k1}
+vpmovsdw %xmm19, (%rax) {k1}
+vpmovsdw %xmm19, %xmm16 {k1}{z}
+
+vpmovsdw %ymm19, %xmm16
+vpmovsdw %ymm19, (%rax)
+vpmovsdw %ymm19, %xmm16 {k1}
+vpmovsdw %ymm19, (%rax) {k1}
+vpmovsdw %ymm19, %xmm16 {k1}{z}
+
+vpmovsqb %xmm19, %xmm16
+vpmovsqb %xmm19, (%rax)
+vpmovsqb %xmm19, %xmm16 {k1}
+vpmovsqb %xmm19, (%rax) {k1}
+vpmovsqb %xmm19, %xmm16 {k1}{z}
+
+vpmovsqb %ymm19, %xmm16
+vpmovsqb %ymm19, (%rax)
+vpmovsqb %ymm19, %xmm16 {k1}
+vpmovsqb %ymm19, (%rax) {k1}
+vpmovsqb %ymm19, %xmm16 {k1}{z}
+
+vpmovsqd %xmm19, %xmm16
+vpmovsqd %xmm19, (%rax)
+vpmovsqd %xmm19, %xmm16 {k1}
+vpmovsqd %xmm19, (%rax) {k1}
+vpmovsqd %xmm19, %xmm16 {k1}{z}
+
+vpmovsqd %ymm19, %xmm16
+vpmovsqd %ymm19, (%rax)
+vpmovsqd %ymm19, %xmm16 {k1}
+vpmovsqd %ymm19, (%rax) {k1}
+vpmovsqd %ymm19, %xmm16 {k1}{z}
+
+vpmovsqw %xmm19, %xmm16
+vpmovsqw %xmm19, (%rax)
+vpmovsqw %xmm19, %xmm16 {k1}
+vpmovsqw %xmm19, (%rax) {k1}
+vpmovsqw %xmm19, %xmm16 {k1}{z}
+
+vpmovsqw %ymm19, %xmm16
+vpmovsqw %ymm19, (%rax)
+vpmovsqw %ymm19, %xmm16 {k1}
+vpmovsqw %ymm19, (%rax) {k1}
+vpmovsqw %ymm19, %xmm16 {k1}{z}
+
+vpmovsxbd %xmm16, %xmm19
+vpmovsxbd (%rax), %xmm19
+vpmovsxbd %xmm16, %xmm19 {k1}
+vpmovsxbd (%rax), %xmm19 {k1}
+vpmovsxbd %xmm16, %xmm19 {z}{k1}
+vpmovsxbd (%rax), %xmm19 {z}{k1}
+
+vpmovsxbd %xmm16, %ymm19
+vpmovsxbd (%rax), %ymm19
+vpmovsxbd %xmm16, %ymm19 {k1}
+vpmovsxbd (%rax), %ymm19 {k1}
+vpmovsxbd %xmm16, %ymm19 {z}{k1}
+vpmovsxbd (%rax), %ymm19 {z}{k1}
+
+vpmovsxbq %xmm16, %xmm19
+vpmovsxbq (%rax), %xmm19
+vpmovsxbq %xmm16, %xmm19 {k1}
+vpmovsxbq (%rax), %xmm19 {k1}
+vpmovsxbq %xmm16, %xmm19 {z}{k1}
+vpmovsxbq (%rax), %xmm19 {z}{k1}
+
+vpmovsxbq %xmm16, %ymm19
+vpmovsxbq (%rax), %ymm19
+vpmovsxbq %xmm16, %ymm19 {k1}
+vpmovsxbq (%rax), %ymm19 {k1}
+vpmovsxbq %xmm16, %ymm19 {z}{k1}
+vpmovsxbq (%rax), %ymm19 {z}{k1}
+
+vpmovsxdq %xmm16, %xmm19
+vpmovsxdq (%rax), %xmm19
+vpmovsxdq %xmm16, %xmm19 {k1}
+vpmovsxdq (%rax), %xmm19 {k1}
+vpmovsxdq %xmm16, %xmm19 {z}{k1}
+vpmovsxdq (%rax), %xmm19 {z}{k1}
+
+vpmovsxdq %xmm16, %ymm19
+vpmovsxdq (%rax), %ymm19
+vpmovsxdq %xmm16, %ymm19 {k1}
+vpmovsxdq (%rax), %ymm19 {k1}
+vpmovsxdq %xmm16, %ymm19 {z}{k1}
+vpmovsxdq (%rax), %ymm19 {z}{k1}
+
+vpmovsxwd %xmm16, %xmm19
+vpmovsxwd (%rax), %xmm19
+vpmovsxwd %xmm16, %xmm19 {k1}
+vpmovsxwd (%rax), %xmm19 {k1}
+vpmovsxwd %xmm16, %xmm19 {z}{k1}
+vpmovsxwd (%rax), %xmm19 {z}{k1}
+
+vpmovsxwd %xmm16, %ymm19
+vpmovsxwd (%rax), %ymm19
+vpmovsxwd %xmm16, %ymm19 {k1}
+vpmovsxwd (%rax), %ymm19 {k1}
+vpmovsxwd %xmm16, %ymm19 {z}{k1}
+vpmovsxwd (%rax), %ymm19 {z}{k1}
+
+vpmovsxwq %xmm16, %xmm19
+vpmovsxwq (%rax), %xmm19
+vpmovsxwq %xmm16, %xmm19 {k1}
+vpmovsxwq (%rax), %xmm19 {k1}
+vpmovsxwq %xmm16, %xmm19 {z}{k1}
+vpmovsxwq (%rax), %xmm19 {z}{k1}
+
+vpmovsxwq %xmm16, %ymm19
+vpmovsxwq (%rax), %ymm19
+vpmovsxwq %xmm16, %ymm19 {k1}
+vpmovsxwq (%rax), %ymm19 {k1}
+vpmovsxwq %xmm16, %ymm19 {z}{k1}
+vpmovsxwq (%rax), %ymm19 {z}{k1}
+
+vpmovusdb %xmm19, %xmm16
+vpmovusdb %xmm19, (%rax)
+vpmovusdb %xmm19, %xmm16 {k1}
+vpmovusdb %xmm19, (%rax) {k1}
+vpmovusdb %xmm19, %xmm16 {k1}{z}
+
+vpmovusdb %ymm19, %xmm16
+vpmovusdb %ymm19, (%rax)
+vpmovusdb %ymm19, %xmm16 {k1}
+vpmovusdb %ymm19, (%rax) {k1}
+vpmovusdb %ymm19, %xmm16 {k1}{z}
+
+vpmovusdw %xmm19, %xmm16
+vpmovusdw %xmm19, (%rax)
+vpmovusdw %xmm19, %xmm16 {k1}
+vpmovusdw %xmm19, (%rax) {k1}
+vpmovusdw %xmm19, %xmm16 {k1}{z}
+
+vpmovusdw %ymm19, %xmm16
+vpmovusdw %ymm19, (%rax)
+vpmovusdw %ymm19, %xmm16 {k1}
+vpmovusdw %ymm19, (%rax) {k1}
+vpmovusdw %ymm19, %xmm16 {k1}{z}
+
+vpmovusqb %xmm19, %xmm16
+vpmovusqb %xmm19, (%rax)
+vpmovusqb %xmm19, %xmm16 {k1}
+vpmovusqb %xmm19, (%rax) {k1}
+vpmovusqb %xmm19, %xmm16 {k1}{z}
+
+vpmovusqb %ymm19, %xmm16
+vpmovusqb %ymm19, (%rax)
+vpmovusqb %ymm19, %xmm16 {k1}
+vpmovusqb %ymm19, (%rax) {k1}
+vpmovusqb %ymm19, %xmm16 {k1}{z}
+
+vpmovusqd %xmm19, %xmm16
+vpmovusqd %xmm19, (%rax)
+vpmovusqd %xmm19, %xmm16 {k1}
+vpmovusqd %xmm19, (%rax) {k1}
+vpmovusqd %xmm19, %xmm16 {k1}{z}
+
+vpmovusqd %ymm19, %xmm16
+vpmovusqd %ymm19, (%rax)
+vpmovusqd %ymm19, %xmm16 {k1}
+vpmovusqd %ymm19, (%rax) {k1}
+vpmovusqd %ymm19, %xmm16 {k1}{z}
+
+vpmovusqw %xmm19, %xmm16
+vpmovusqw %xmm19, (%rax)
+vpmovusqw %xmm19, %xmm16 {k1}
+vpmovusqw %xmm19, (%rax) {k1}
+vpmovusqw %xmm19, %xmm16 {k1}{z}
+
+vpmovusqw %ymm19, %xmm16
+vpmovusqw %ymm19, (%rax)
+vpmovusqw %ymm19, %xmm16 {k1}
+vpmovusqw %ymm19, (%rax) {k1}
+vpmovusqw %ymm19, %xmm16 {k1}{z}
+
+vpmovzxbd %xmm16, %xmm19
+vpmovzxbd (%rax), %xmm19
+vpmovzxbd %xmm16, %xmm19 {k1}
+vpmovzxbd (%rax), %xmm19 {k1}
+vpmovzxbd %xmm16, %xmm19 {z}{k1}
+vpmovzxbd (%rax), %xmm19 {z}{k1}
+
+vpmovzxbd %xmm16, %ymm19
+vpmovzxbd (%rax), %ymm19
+vpmovzxbd %xmm16, %ymm19 {k1}
+vpmovzxbd (%rax), %ymm19 {k1}
+vpmovzxbd %xmm16, %ymm19 {z}{k1}
+vpmovzxbd (%rax), %ymm19 {z}{k1}
+
+vpmovzxbq %xmm16, %xmm19
+vpmovzxbq (%rax), %xmm19
+vpmovzxbq %xmm16, %xmm19 {k1}
+vpmovzxbq (%rax), %xmm19 {k1}
+vpmovzxbq %xmm16, %xmm19 {z}{k1}
+vpmovzxbq (%rax), %xmm19 {z}{k1}
+
+vpmovzxbq %xmm16, %ymm19
+vpmovzxbq (%rax), %ymm19
+vpmovzxbq %xmm16, %ymm19 {k1}
+vpmovzxbq (%rax), %ymm19 {k1}
+vpmovzxbq %xmm16, %ymm19 {z}{k1}
+vpmovzxbq (%rax), %ymm19 {z}{k1}
+
+vpmovzxdq %xmm16, %xmm19
+vpmovzxdq (%rax), %xmm19
+vpmovzxdq %xmm16, %xmm19 {k1}
+vpmovzxdq (%rax), %xmm19 {k1}
+vpmovzxdq %xmm16, %xmm19 {z}{k1}
+vpmovzxdq (%rax), %xmm19 {z}{k1}
+
+vpmovzxdq %xmm16, %ymm19
+vpmovzxdq (%rax), %ymm19
+vpmovzxdq %xmm16, %ymm19 {k1}
+vpmovzxdq (%rax), %ymm19 {k1}
+vpmovzxdq %xmm16, %ymm19 {z}{k1}
+vpmovzxdq (%rax), %ymm19 {z}{k1}
+
+vpmovzxwd %xmm16, %xmm19
+vpmovzxwd (%rax), %xmm19
+vpmovzxwd %xmm16, %xmm19 {k1}
+vpmovzxwd (%rax), %xmm19 {k1}
+vpmovzxwd %xmm16, %xmm19 {z}{k1}
+vpmovzxwd (%rax), %xmm19 {z}{k1}
+
+vpmovzxwd %xmm16, %ymm19
+vpmovzxwd (%rax), %ymm19
+vpmovzxwd %xmm16, %ymm19 {k1}
+vpmovzxwd (%rax), %ymm19 {k1}
+vpmovzxwd %xmm16, %ymm19 {z}{k1}
+vpmovzxwd (%rax), %ymm19 {z}{k1}
+
+vpmovzxwq %xmm16, %xmm19
+vpmovzxwq (%rax), %xmm19
+vpmovzxwq %xmm16, %xmm19 {k1}
+vpmovzxwq (%rax), %xmm19 {k1}
+vpmovzxwq %xmm16, %xmm19 {z}{k1}
+vpmovzxwq (%rax), %xmm19 {z}{k1}
+
+vpmovzxwq %xmm16, %ymm19
+vpmovzxwq (%rax), %ymm19
+vpmovzxwq %xmm16, %ymm19 {k1}
+vpmovzxwq (%rax), %ymm19 {k1}
+vpmovzxwq %xmm16, %ymm19 {z}{k1}
+vpmovzxwq (%rax), %ymm19 {z}{k1}
+
+vpmulld %xmm16, %xmm17, %xmm19
+vpmulld (%rax), %xmm17, %xmm19
+vpmulld (%rax){1to4}, %xmm17, %xmm19
+vpmulld %xmm16, %xmm17, %xmm19 {k1}
+vpmulld (%rax), %xmm17, %xmm19 {k1}
+vpmulld (%rax){1to4}, %xmm17, %xmm19 {k1}
+vpmulld %xmm16, %xmm17, %xmm19 {z}{k1}
+vpmulld (%rax), %xmm17, %xmm19 {z}{k1}
+vpmulld (%rax){1to4}, %xmm17, %xmm19 {z}{k1}
+
+vpmulld %ymm16, %ymm17, %ymm19
+vpmulld (%rax), %ymm17, %ymm19
+vpmulld (%rax){1to8}, %ymm17, %ymm19
+vpmulld %ymm16, %ymm17, %ymm19 {k1}
+vpmulld (%rax), %ymm17, %ymm19 {k1}
+vpmulld (%rax){1to8}, %ymm17, %ymm19 {k1}
+vpmulld %ymm16, %ymm17, %ymm19 {z}{k1}
+vpmulld (%rax), %ymm17, %ymm19 {z}{k1}
+vpmulld (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
+
+vpscatterdd %xmm1, (%rdx,%xmm0,4) {%k1}
+vpscatterdq %xmm1, (%rdx,%xmm0,4) {%k1}
+vpscatterqd %xmm1, (%rdx,%xmm0,4) {%k1}
+vpscatterqq %xmm1, (%rdx,%xmm0,4) {%k1}
+
+vpscatterdd %ymm1, (%rdx,%ymm0,4) {%k1}
+vpscatterdq %ymm1, (%rdx,%xmm0,4) {%k1}
+vpscatterqd %xmm1, (%rdx,%ymm0,4) {%k1}
+vpscatterqq %ymm1, (%rdx,%ymm0,4) {%k1}
+
+vpshufd $0, %xmm16, %xmm19
+vpshufd $0, (%rax), %xmm19
+vpshufd $0, (%rax){1to4}, %xmm19
+vpshufd $0, %xmm16, %xmm19 {k1}
+vpshufd $0, (%rax), %xmm19 {k1}
+vpshufd $0, (%rax){1to4}, %xmm19 {k1}
+vpshufd $0, %xmm16, %xmm19 {z}{k1}
+vpshufd $0, (%rax), %xmm19 {z}{k1}
+vpshufd $0, (%rax){1to4}, %xmm19 {z}{k1}
+
+vpshufd $0, %ymm16, %ymm19
+vpshufd $0, (%rax), %ymm19
+vpshufd $0, (%rax){1to8}, %ymm19
+vpshufd $0, %ymm16, %ymm19 {k1}
+vpshufd $0, (%rax), %ymm19 {k1}
+vpshufd $0, (%rax){1to8}, %ymm19 {k1}
+vpshufd $0, %ymm16, %ymm19 {z}{k1}
+vpshufd $0, (%rax), %ymm19 {z}{k1}
+vpshufd $0, (%rax){1to8}, %ymm19 {z}{k1}
+
+vpsubd %xmm16, %xmm17, %xmm19
+vpsubd (%rax), %xmm17, %xmm19
+vpsubd (%rax){1to4}, %xmm17, %xmm19
+vpsubd %xmm16, %xmm17, %xmm19 {k1}
+vpsubd (%rax), %xmm17, %xmm19 {k1}
+vpsubd (%rax){1to4}, %xmm17, %xmm19 {k1}
+vpsubd %xmm16, %xmm17, %xmm19 {z}{k1}
+vpsubd (%rax), %xmm17, %xmm19 {z}{k1}
+vpsubd (%rax){1to4}, %xmm17, %xmm19 {z}{k1}
+
+vpsubd %ymm16, %ymm17, %ymm19
+vpsubd (%rax), %ymm17, %ymm19
+vpsubd (%rax){1to8}, %ymm17, %ymm19
+vpsubd %ymm16, %ymm17, %ymm19 {k1}
+vpsubd (%rax), %ymm17, %ymm19 {k1}
+vpsubd (%rax){1to8}, %ymm17, %ymm19 {k1}
+vpsubd %ymm16, %ymm17, %ymm19 {z}{k1}
+vpsubd (%rax), %ymm17, %ymm19 {z}{k1}
+vpsubd (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
+
+vpsubq %xmm16, %xmm17, %xmm19
+vpsubq (%rax), %xmm17, %xmm19
+vpsubq (%rax){1to2}, %xmm17, %xmm19
+vpsubq %xmm16, %xmm17, %xmm19 {k1}
+vpsubq (%rax), %xmm17, %xmm19 {k1}
+vpsubq (%rax){1to2}, %xmm17, %xmm19 {k1}
+vpsubq %xmm16, %xmm17, %xmm19 {z}{k1}
+vpsubq (%rax), %xmm17, %xmm19 {z}{k1}
+vpsubq (%rax){1to2}, %xmm17, %xmm19 {z}{k1}
+
+vpsubq %ymm16, %ymm17, %ymm19
+vpsubq (%rax), %ymm17, %ymm19
+vpsubq (%rax){1to4}, %ymm17, %ymm19
+vpsubq %ymm16, %ymm17, %ymm19 {k1}
+vpsubq (%rax), %ymm17, %ymm19 {k1}
+vpsubq (%rax){1to4}, %ymm17, %ymm19 {k1}
+vpsubq %ymm16, %ymm17, %ymm19 {z}{k1}
+vpsubq (%rax), %ymm17, %ymm19 {z}{k1}
+vpsubq (%rax){1to4}, %ymm17, %ymm19 {z}{k1}
+
+vptestmd %xmm0, %xmm1, %k2
+vptestmd (%rax), %xmm1, %k2
+vptestmd (%rax){1to4}, %xmm1, %k2
+vptestmd %xmm0, %xmm1, %k2 {k3}
+vptestmd (%rax), %xmm1, %k2 {k3}
+vptestmd (%rax){1to4}, %xmm1, %k2 {k3}
+
+vptestmd %ymm0, %ymm1, %k2
+vptestmd (%rax), %ymm1, %k2
+vptestmd (%rax){1to8}, %ymm1, %k2
+vptestmd %ymm0, %ymm1, %k2 {k3}
+vptestmd (%rax), %ymm1, %k2 {k3}
+vptestmd (%rax){1to8}, %ymm1, %k2 {k3}
+
+vptestmq %xmm0, %xmm1, %k2
+vptestmq (%rax), %xmm1, %k2
+vptestmq (%rax){1to2}, %xmm1, %k2
+vptestmq %xmm0, %xmm1, %k2 {k3}
+vptestmq (%rax), %xmm1, %k2 {k3}
+vptestmq (%rax){1to2}, %xmm1, %k2 {k3}
+
+vptestmq %ymm0, %ymm1, %k2
+vptestmq (%rax), %ymm1, %k2
+vptestmq (%rax){1to4}, %ymm1, %k2
+vptestmq %ymm0, %ymm1, %k2 {k3}
+vptestmq (%rax), %ymm1, %k2 {k3}
+vptestmq (%rax){1to4}, %ymm1, %k2 {k3}
+
+vptestnmd %xmm0, %xmm1, %k2
+vptestnmd (%rax), %xmm1, %k2
+vptestnmd (%rax){1to4}, %xmm1, %k2
+vptestnmd %xmm0, %xmm1, %k2 {k3}
+vptestnmd (%rax), %xmm1, %k2 {k3}
+vptestnmd (%rax){1to4}, %xmm1, %k2 {k3}
+
+vptestnmd %ymm0, %ymm1, %k2
+vptestnmd (%rax), %ymm1, %k2
+vptestnmd (%rax){1to8}, %ymm1, %k2
+vptestnmd %ymm0, %ymm1, %k2 {k3}
+vptestnmd (%rax), %ymm1, %k2 {k3}
+vptestnmd (%rax){1to8}, %ymm1, %k2 {k3}
+
+vptestnmq %xmm0, %xmm1, %k2
+vptestnmq (%rax), %xmm1, %k2
+vptestnmq (%rax){1to2}, %xmm1, %k2
+vptestnmq %xmm0, %xmm1, %k2 {k3}
+vptestnmq (%rax), %xmm1, %k2 {k3}
+vptestnmq (%rax){1to2}, %xmm1, %k2 {k3}
+
+vptestnmq %ymm0, %ymm1, %k2
+vptestnmq (%rax), %ymm1, %k2
+vptestnmq (%rax){1to4}, %ymm1, %k2
+vptestnmq %ymm0, %ymm1, %k2 {k3}
+vptestnmq (%rax), %ymm1, %k2 {k3}
+vptestnmq (%rax){1to4}, %ymm1, %k2 {k3}
+
+vpunpckhdq %xmm16, %xmm17, %xmm19
+vpunpckhdq (%rax), %xmm17, %xmm19
+vpunpckhdq (%rax){1to4}, %xmm17, %xmm19
+vpunpckhdq %xmm16, %xmm17, %xmm19 {k1}
+vpunpckhdq (%rax), %xmm17, %xmm19 {k1}
+vpunpckhdq (%rax){1to4}, %xmm17, %xmm19 {k1}
+vpunpckhdq %xmm16, %xmm17, %xmm19 {z}{k1}
+vpunpckhdq (%rax), %xmm17, %xmm19 {z}{k1}
+vpunpckhdq (%rax){1to4}, %xmm17, %xmm19 {z}{k1}
+
+vpunpckhdq %ymm16, %ymm17, %ymm19
+vpunpckhdq (%rax), %ymm17, %ymm19
+vpunpckhdq (%rax){1to8}, %ymm17, %ymm19
+vpunpckhdq %ymm16, %ymm17, %ymm19 {k1}
+vpunpckhdq (%rax), %ymm17, %ymm19 {k1}
+vpunpckhdq (%rax){1to8}, %ymm17, %ymm19 {k1}
+vpunpckhdq %ymm16, %ymm17, %ymm19 {z}{k1}
+vpunpckhdq (%rax), %ymm17, %ymm19 {z}{k1}
+vpunpckhdq (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
+
+vpunpckldq %xmm16, %xmm17, %xmm19
+vpunpckldq (%rax), %xmm17, %xmm19
+vpunpckldq (%rax){1to4}, %xmm17, %xmm19
+vpunpckldq %xmm16, %xmm17, %xmm19 {k1}
+vpunpckldq (%rax), %xmm17, %xmm19 {k1}
+vpunpckldq (%rax){1to4}, %xmm17, %xmm19 {k1}
+vpunpckldq %xmm16, %xmm17, %xmm19 {z}{k1}
+vpunpckldq (%rax), %xmm17, %xmm19 {z}{k1}
+vpunpckldq (%rax){1to4}, %xmm17, %xmm19 {z}{k1}
+
+vpunpckldq %ymm16, %ymm17, %ymm19
+vpunpckldq (%rax), %ymm17, %ymm19
+vpunpckldq (%rax){1to8}, %ymm17, %ymm19
+vpunpckldq %ymm16, %ymm17, %ymm19 {k1}
+vpunpckldq (%rax), %ymm17, %ymm19 {k1}
+vpunpckldq (%rax){1to8}, %ymm17, %ymm19 {k1}
+vpunpckldq %ymm16, %ymm17, %ymm19 {z}{k1}
+vpunpckldq (%rax), %ymm17, %ymm19 {z}{k1}
+vpunpckldq (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
+
+vscatterdps %xmm1, (%rdx,%xmm0,4) {%k1}
+vscatterdpd %xmm1, (%rdx,%xmm0,4) {%k1}
+vscatterqps %xmm1, (%rdx,%xmm0,4) {%k1}
+vscatterqpd %xmm1, (%rdx,%xmm0,4) {%k1}
+
+vscatterdps %ymm1, (%rdx,%ymm0,4) {%k1}
+vscatterdpd %ymm1, (%rdx,%xmm0,4) {%k1}
+vscatterqps %xmm1, (%rdx,%ymm0,4) {%k1}
+vscatterqpd %ymm1, (%rdx,%ymm0,4) {%k1}
+
+vshuff32x4 $0, %ymm16, %ymm17, %ymm19
+vshuff32x4 $0, (%rax), %ymm17, %ymm19
+vshuff32x4 $0, (%rax){1to8}, %ymm17, %ymm19
+vshuff32x4 $0, %ymm16, %ymm17, %ymm19 {k1}
+vshuff32x4 $0, (%rax), %ymm17, %ymm19 {k1}
+vshuff32x4 $0, (%rax){1to8}, %ymm17, %ymm19 {k1}
+vshuff32x4 $0, %ymm16, %ymm17, %ymm19 {z}{k1}
+vshuff32x4 $0, (%rax), %ymm17, %ymm19 {z}{k1}
+vshuff32x4 $0, (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
+
+vshuff64x2 $0, %ymm16, %ymm17, %ymm19
+vshuff64x2 $0, (%rax), %ymm17, %ymm19
+vshuff64x2 $0, (%rax){1to4}, %ymm17, %ymm19
+vshuff64x2 $0, %ymm16, %ymm17, %ymm19 {k1}
+vshuff64x2 $0, (%rax), %ymm17, %ymm19 {k1}
+vshuff64x2 $0, (%rax){1to4}, %ymm17, %ymm19 {k1}
+vshuff64x2 $0, %ymm16, %ymm17, %ymm19 {z}{k1}
+vshuff64x2 $0, (%rax), %ymm17, %ymm19 {z}{k1}
+vshuff64x2 $0, (%rax){1to4}, %ymm17, %ymm19 {z}{k1}
+
+vshufi32x4 $0, %ymm16, %ymm17, %ymm19
+vshufi32x4 $0, (%rax), %ymm17, %ymm19
+vshufi32x4 $0, (%rax){1to8}, %ymm17, %ymm19
+vshufi32x4 $0, %ymm16, %ymm17, %ymm19 {k1}
+vshufi32x4 $0, (%rax), %ymm17, %ymm19 {k1}
+vshufi32x4 $0, (%rax){1to8}, %ymm17, %ymm19 {k1}
+vshufi32x4 $0, %ymm16, %ymm17, %ymm19 {z}{k1}
+vshufi32x4 $0, (%rax), %ymm17, %ymm19 {z}{k1}
+vshufi32x4 $0, (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
+
+vshufi64x2 $0, %ymm16, %ymm17, %ymm19
+vshufi64x2 $0, (%rax), %ymm17, %ymm19
+vshufi64x2 $0, (%rax){1to4}, %ymm17, %ymm19
+vshufi64x2 $0, %ymm16, %ymm17, %ymm19 {k1}
+vshufi64x2 $0, (%rax), %ymm17, %ymm19 {k1}
+vshufi64x2 $0, (%rax){1to4}, %ymm17, %ymm19 {k1}
+vshufi64x2 $0, %ymm16, %ymm17, %ymm19 {z}{k1}
+vshufi64x2 $0, (%rax), %ymm17, %ymm19 {z}{k1}
+vshufi64x2 $0, (%rax){1to4}, %ymm17, %ymm19 {z}{k1}
+
+vsqrtpd %xmm16, %xmm19
+vsqrtpd (%rax), %xmm19
+vsqrtpd (%rax){1to2}, %xmm19
+vsqrtpd %xmm16, %xmm19 {k1}
+vsqrtpd (%rax), %xmm19 {k1}
+vsqrtpd (%rax){1to2}, %xmm19 {k1}
+vsqrtpd %xmm16, %xmm19 {z}{k1}
+vsqrtpd (%rax), %xmm19 {z}{k1}
+vsqrtpd (%rax){1to2}, %xmm19 {z}{k1}
+
+vsqrtpd %ymm16, %ymm19
+vsqrtpd (%rax), %ymm19
+vsqrtpd (%rax){1to4}, %ymm19
+vsqrtpd %ymm16, %ymm19 {k1}
+vsqrtpd (%rax), %ymm19 {k1}
+vsqrtpd (%rax){1to4}, %ymm19 {k1}
+vsqrtpd %ymm16, %ymm19 {z}{k1}
+vsqrtpd (%rax), %ymm19 {z}{k1}
+vsqrtpd (%rax){1to4}, %ymm19 {z}{k1}
+
+vsqrtps %xmm16, %xmm19
+vsqrtps (%rax), %xmm19
+vsqrtps (%rax){1to4}, %xmm19
+vsqrtps %xmm16, %xmm19 {k1}
+vsqrtps (%rax), %xmm19 {k1}
+vsqrtps (%rax){1to4}, %xmm19 {k1}
+vsqrtps %xmm16, %xmm19 {z}{k1}
+vsqrtps (%rax), %xmm19 {z}{k1}
+vsqrtps (%rax){1to4}, %xmm19 {z}{k1}
+
+vsqrtps %ymm16, %ymm19
+vsqrtps (%rax), %ymm19
+vsqrtps (%rax){1to8}, %ymm19
+vsqrtps %ymm16, %ymm19 {k1}
+vsqrtps (%rax), %ymm19 {k1}
+vsqrtps (%rax){1to8}, %ymm19 {k1}
+vsqrtps %ymm16, %ymm19 {z}{k1}
+vsqrtps (%rax), %ymm19 {z}{k1}
+vsqrtps (%rax){1to8}, %ymm19 {z}{k1}
+
+vsubpd %xmm16, %xmm17, %xmm19
+vsubpd (%rax), %xmm17, %xmm19
+vsubpd (%rax){1to2}, %xmm17, %xmm19
+vsubpd %xmm16, %xmm17, %xmm19 {k1}
+vsubpd (%rax), %xmm17, %xmm19 {k1}
+vsubpd (%rax){1to2}, %xmm17, %xmm19 {k1}
+vsubpd %xmm16, %xmm17, %xmm19 {z}{k1}
+vsubpd (%rax), %xmm17, %xmm19 {z}{k1}
+vsubpd (%rax){1to2}, %xmm17, %xmm19 {z}{k1}
+
+vsubpd %ymm16, %ymm17, %ymm19
+vsubpd (%rax), %ymm17, %ymm19
+vsubpd (%rax){1to4}, %ymm17, %ymm19
+vsubpd %ymm16, %ymm17, %ymm19 {k1}
+vsubpd (%rax), %ymm17, %ymm19 {k1}
+vsubpd (%rax){1to4}, %ymm17, %ymm19 {k1}
+vsubpd %ymm16, %ymm17, %ymm19 {z}{k1}
+vsubpd (%rax), %ymm17, %ymm19 {z}{k1}
+vsubpd (%rax){1to4}, %ymm17, %ymm19 {z}{k1}
+
+vsubps %xmm16, %xmm17, %xmm19
+vsubps (%rax), %xmm17, %xmm19
+vsubps (%rax){1to4}, %xmm17, %xmm19
+vsubps %xmm16, %xmm17, %xmm19 {k1}
+vsubps (%rax), %xmm17, %xmm19 {k1}
+vsubps (%rax){1to4}, %xmm17, %xmm19 {k1}
+vsubps %xmm16, %xmm17, %xmm19 {z}{k1}
+vsubps (%rax), %xmm17, %xmm19 {z}{k1}
+vsubps (%rax){1to4}, %xmm17, %xmm19 {z}{k1}
+
+vsubps %ymm16, %ymm17, %ymm19
+vsubps (%rax), %ymm17, %ymm19
+vsubps (%rax){1to8}, %ymm17, %ymm19
+vsubps %ymm16, %ymm17, %ymm19 {k1}
+vsubps (%rax), %ymm17, %ymm19 {k1}
+vsubps (%rax){1to8}, %ymm17, %ymm19 {k1}
+vsubps %ymm16, %ymm17, %ymm19 {z}{k1}
+vsubps (%rax), %ymm17, %ymm19 {z}{k1}
+vsubps (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
+
+vunpckhpd %xmm16, %xmm17, %xmm19
+vunpckhpd (%rax), %xmm17, %xmm19
+vunpckhpd (%rax){1to2}, %xmm17, %xmm19
+vunpckhpd %xmm16, %xmm17, %xmm19 {k1}
+vunpckhpd (%rax), %xmm17, %xmm19 {k1}
+vunpckhpd (%rax){1to2}, %xmm17, %xmm19 {k1}
+vunpckhpd %xmm16, %xmm17, %xmm19 {z}{k1}
+vunpckhpd (%rax), %xmm17, %xmm19 {z}{k1}
+vunpckhpd (%rax){1to2}, %xmm17, %xmm19 {z}{k1}
+
+vunpckhpd %ymm16, %ymm17, %ymm19
+vunpckhpd (%rax), %ymm17, %ymm19
+vunpckhpd (%rax){1to4}, %ymm17, %ymm19
+vunpckhpd %ymm16, %ymm17, %ymm19 {k1}
+vunpckhpd (%rax), %ymm17, %ymm19 {k1}
+vunpckhpd (%rax){1to4}, %ymm17, %ymm19 {k1}
+vunpckhpd %ymm16, %ymm17, %ymm19 {z}{k1}
+vunpckhpd (%rax), %ymm17, %ymm19 {z}{k1}
+vunpckhpd (%rax){1to4}, %ymm17, %ymm19 {z}{k1}
+
+vunpckhps %xmm16, %xmm17, %xmm19
+vunpckhps (%rax), %xmm17, %xmm19
+vunpckhps (%rax){1to4}, %xmm17, %xmm19
+vunpckhps %xmm16, %xmm17, %xmm19 {k1}
+vunpckhps (%rax), %xmm17, %xmm19 {k1}
+vunpckhps (%rax){1to4}, %xmm17, %xmm19 {k1}
+vunpckhps %xmm16, %xmm17, %xmm19 {z}{k1}
+vunpckhps (%rax), %xmm17, %xmm19 {z}{k1}
+vunpckhps (%rax){1to4}, %xmm17, %xmm19 {z}{k1}
+
+vunpckhps %ymm16, %ymm17, %ymm19
+vunpckhps (%rax), %ymm17, %ymm19
+vunpckhps (%rax){1to8}, %ymm17, %ymm19
+vunpckhps %ymm16, %ymm17, %ymm19 {k1}
+vunpckhps (%rax), %ymm17, %ymm19 {k1}
+vunpckhps (%rax){1to8}, %ymm17, %ymm19 {k1}
+vunpckhps %ymm16, %ymm17, %ymm19 {z}{k1}
+vunpckhps (%rax), %ymm17, %ymm19 {z}{k1}
+vunpckhps (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
+
+vunpcklpd %xmm16, %xmm17, %xmm19
+vunpcklpd (%rax), %xmm17, %xmm19
+vunpcklpd (%rax){1to2}, %xmm17, %xmm19
+vunpcklpd %xmm16, %xmm17, %xmm19 {k1}
+vunpcklpd (%rax), %xmm17, %xmm19 {k1}
+vunpcklpd (%rax){1to2}, %xmm17, %xmm19 {k1}
+vunpcklpd %xmm16, %xmm17, %xmm19 {z}{k1}
+vunpcklpd (%rax), %xmm17, %xmm19 {z}{k1}
+vunpcklpd (%rax){1to2}, %xmm17, %xmm19 {z}{k1}
+
+vunpcklpd %ymm16, %ymm17, %ymm19
+vunpcklpd (%rax), %ymm17, %ymm19
+vunpcklpd (%rax){1to4}, %ymm17, %ymm19
+vunpcklpd %ymm16, %ymm17, %ymm19 {k1}
+vunpcklpd (%rax), %ymm17, %ymm19 {k1}
+vunpcklpd (%rax){1to4}, %ymm17, %ymm19 {k1}
+vunpcklpd %ymm16, %ymm17, %ymm19 {z}{k1}
+vunpcklpd (%rax), %ymm17, %ymm19 {z}{k1}
+vunpcklpd (%rax){1to4}, %ymm17, %ymm19 {z}{k1}
+
+vunpcklps %xmm16, %xmm17, %xmm19
+vunpcklps (%rax), %xmm17, %xmm19
+vunpcklps (%rax){1to4}, %xmm17, %xmm19
+vunpcklps %xmm16, %xmm17, %xmm19 {k1}
+vunpcklps (%rax), %xmm17, %xmm19 {k1}
+vunpcklps (%rax){1to4}, %xmm17, %xmm19 {k1}
+vunpcklps %xmm16, %xmm17, %xmm19 {z}{k1}
+vunpcklps (%rax), %xmm17, %xmm19 {z}{k1}
+vunpcklps (%rax){1to4}, %xmm17, %xmm19 {z}{k1}
+
+vunpcklps %ymm16, %ymm17, %ymm19
+vunpcklps (%rax), %ymm17, %ymm19
+vunpcklps (%rax){1to8}, %ymm17, %ymm19
+vunpcklps %ymm16, %ymm17, %ymm19 {k1}
+vunpcklps (%rax), %ymm17, %ymm19 {k1}
+vunpcklps (%rax){1to8}, %ymm17, %ymm19 {k1}
+vunpcklps %ymm16, %ymm17, %ymm19 {z}{k1}
+vunpcklps (%rax), %ymm17, %ymm19 {z}{k1}
+vunpcklps (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 vaddpd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vaddpd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vaddpd (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: 1 4 0.50 vaddpd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vaddpd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vaddpd (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vaddpd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vaddpd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vaddpd (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vaddpd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vaddpd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vaddpd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 1 4 0.50 vaddpd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vaddpd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vaddpd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vaddpd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vaddpd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vaddpd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vaddps %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vaddps (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vaddps (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: 1 4 0.50 vaddps %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vaddps (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vaddps (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vaddps %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vaddps (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vaddps (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vaddps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vaddps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vaddps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 1 4 0.50 vaddps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vaddps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vaddps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vaddps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vaddps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vaddps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 valignd $1, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * valignd $1, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * valignd $1, (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 valignd $1, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * valignd $1, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * valignd $1, (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 2 0.50 valignd $1, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 0.50 * valignd $1, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * valignd $1, (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 2.00 valignd $1, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 2.00 * valignd $1, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * valignd $1, (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 1 4 2.00 valignd $1, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 2.00 * valignd $1, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * valignd $1, (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 2.00 valignd $1, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 2.00 * valignd $1, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * valignd $1, (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 valignq $1, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * valignq $1, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * valignq $1, (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 valignq $1, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * valignq $1, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * valignq $1, (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 2 0.50 valignq $1, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 9 0.50 * valignq $1, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * valignq $1, (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 2.00 valignq $1, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 2.00 * valignq $1, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * valignq $1, (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 1 4 2.00 valignq $1, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 2.00 * valignq $1, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * valignq $1, (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 2.00 valignq $1, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 2.00 * valignq $1, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * valignq $1, (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vbroadcastf32x4 (%rax), %ymm19
+# CHECK-NEXT: 1 8 0.50 * vbroadcastf32x4 (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vbroadcastf32x4 (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vbroadcasti32x4 (%rax), %ymm19
+# CHECK-NEXT: 1 8 0.50 * vbroadcasti32x4 (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vbroadcasti32x4 (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vbroadcastsd %xmm16, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vbroadcastsd (%rax), %ymm19
+# CHECK-NEXT: 1 4 2.00 vbroadcastsd %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 2.00 * vbroadcastsd (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vbroadcastsd %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vbroadcastsd (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vbroadcastss %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vbroadcastss (%rax), %xmm19
+# CHECK-NEXT: 1 2 0.50 vbroadcastss %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vbroadcastss (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vbroadcastss %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vbroadcastss (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vbroadcastss %xmm16, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vbroadcastss (%rax), %ymm19
+# CHECK-NEXT: 1 4 2.00 vbroadcastss %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 2.00 * vbroadcastss (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vbroadcastss %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vbroadcastss (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vcmpeqpd %xmm0, %xmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vcmpeqpd (%rax), %xmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vcmpeqpd (%rax){1to2}, %xmm1, %k2
+# CHECK-NEXT: 2 5 0.50 vcmpeqpd %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 2 12 0.50 * vcmpeqpd (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.50 * vcmpeqpd (%rax){1to2}, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.50 vcmpeqpd %ymm0, %ymm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vcmpeqpd (%rax), %ymm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vcmpeqpd (%rax){1to4}, %ymm1, %k2
+# CHECK-NEXT: 2 5 0.50 vcmpeqpd %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 2 12 0.50 * vcmpeqpd (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.50 * vcmpeqpd (%rax){1to4}, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.50 vcmpeqps %xmm0, %xmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vcmpeqps (%rax), %xmm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vcmpeqps (%rax){1to4}, %xmm1, %k2
+# CHECK-NEXT: 2 5 0.50 vcmpeqps %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 2 12 0.50 * vcmpeqps (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.50 * vcmpeqps (%rax){1to4}, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.50 vcmpeqps %ymm0, %ymm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vcmpeqps (%rax), %ymm1, %k2
+# CHECK-NEXT: 1 8 0.50 * vcmpeqps (%rax){1to8}, %ymm1, %k2
+# CHECK-NEXT: 2 5 0.50 vcmpeqps %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 2 12 0.50 * vcmpeqps (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.50 * vcmpeqps (%rax){1to8}, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 4 0.50 vcvtdq2pd %xmm16, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtdq2pd (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtdq2pd (%rax){1to2}, %xmm19
+# CHECK-NEXT: 2 5 1.00 vcvtdq2pd %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtdq2pd (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvtdq2pd (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvtdq2pd %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtdq2pd (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtdq2pd (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvtdq2pd %xmm16, %ymm19
+# CHECK-NEXT: 1 11 0.50 * vcvtdq2pd (%rax), %ymm19
+# CHECK-NEXT: 1 11 0.50 * vcvtdq2pd (%rax){1to4}, %ymm19
+# CHECK-NEXT: 2 5 1.00 vcvtdq2pd %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtdq2pd (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvtdq2pd (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvtdq2pd %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtdq2pd (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtdq2pd (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvtdq2ps %xmm16, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtdq2ps (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtdq2ps (%rax){1to4}, %xmm19
+# CHECK-NEXT: 2 5 1.00 vcvtdq2ps %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtdq2ps (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvtdq2ps (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvtdq2ps %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtdq2ps (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtdq2ps (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvtdq2ps %ymm16, %ymm19
+# CHECK-NEXT: 1 11 0.50 * vcvtdq2ps (%rax), %ymm19
+# CHECK-NEXT: 1 11 0.50 * vcvtdq2ps (%rax){1to8}, %ymm19
+# CHECK-NEXT: 2 5 1.00 vcvtdq2ps %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtdq2ps (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvtdq2ps (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvtdq2ps %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtdq2ps (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtdq2ps (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvtpd2dq %ymm16, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2dqy (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2dq (%rax){1to4}, %xmm19
+# CHECK-NEXT: 2 5 1.00 vcvtpd2dq %ymm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtpd2dqy (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2dq (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvtpd2dq %ymm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2dqy (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2dq (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvtpd2dq %xmm16, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2dqx (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2dq (%rax){1to2}, %xmm19
+# CHECK-NEXT: 2 5 1.00 vcvtpd2dq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtpd2dqx (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2dq (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvtpd2dq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2dqx (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2dq (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvtpd2ps %ymm16, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2psy (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2ps (%rax){1to4}, %xmm19
+# CHECK-NEXT: 2 5 1.00 vcvtpd2ps %ymm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtpd2psy (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2ps (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvtpd2ps %ymm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2psy (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2ps (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvtpd2ps %xmm16, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2psx (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2ps (%rax){1to2}, %xmm19
+# CHECK-NEXT: 2 5 1.00 vcvtpd2ps %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtpd2psx (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2ps (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvtpd2ps %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2psx (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2ps (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvtpd2udq %ymm16, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2udqy (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2udq (%rax){1to4}, %xmm19
+# CHECK-NEXT: 2 5 1.00 vcvtpd2udq %ymm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtpd2udqy (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2udq (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvtpd2udq %ymm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2udqy (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2udq (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvtpd2udq %xmm16, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2udqx (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2udq (%rax){1to2}, %xmm19
+# CHECK-NEXT: 2 5 1.00 vcvtpd2udq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtpd2udqx (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2udq (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvtpd2udq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2udqx (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtpd2udq (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvtps2dq %xmm16, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtps2dq (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtps2dq (%rax){1to4}, %xmm19
+# CHECK-NEXT: 2 5 1.00 vcvtps2dq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtps2dq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvtps2dq (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvtps2dq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtps2dq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtps2dq (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvtps2dq %ymm16, %ymm19
+# CHECK-NEXT: 1 11 0.50 * vcvtps2dq (%rax), %ymm19
+# CHECK-NEXT: 1 11 0.50 * vcvtps2dq (%rax){1to8}, %ymm19
+# CHECK-NEXT: 2 5 1.00 vcvtps2dq %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtps2dq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvtps2dq (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvtps2dq %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtps2dq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtps2dq (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvtps2pd %xmm16, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtps2pd (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtps2pd (%rax){1to2}, %xmm19
+# CHECK-NEXT: 2 5 1.00 vcvtps2pd %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtps2pd (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvtps2pd (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvtps2pd %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtps2pd (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtps2pd (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvtps2pd %xmm16, %ymm19
+# CHECK-NEXT: 1 11 0.50 * vcvtps2pd (%rax), %ymm19
+# CHECK-NEXT: 1 11 0.50 * vcvtps2pd (%rax){1to4}, %ymm19
+# CHECK-NEXT: 2 5 1.00 vcvtps2pd %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtps2pd (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvtps2pd (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvtps2pd %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtps2pd (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtps2pd (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvtps2udq %xmm16, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtps2udq (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvtps2udq (%rax){1to4}, %xmm19
+# CHECK-NEXT: 2 5 1.00 vcvtps2udq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtps2udq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvtps2udq (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvtps2udq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtps2udq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtps2udq (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvtps2udq %ymm16, %ymm19
+# CHECK-NEXT: 1 11 0.50 * vcvtps2udq (%rax), %ymm19
+# CHECK-NEXT: 1 11 0.50 * vcvtps2udq (%rax){1to8}, %ymm19
+# CHECK-NEXT: 2 5 1.00 vcvtps2udq %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvtps2udq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvtps2udq (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvtps2udq %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtps2udq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvtps2udq (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvttpd2dq %ymm16, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2dqy (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2dq (%rax){1to4}, %xmm19
+# CHECK-NEXT: 2 5 1.00 vcvttpd2dq %ymm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvttpd2dqy (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2dq (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvttpd2dq %ymm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2dqy (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2dq (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvttpd2dq %xmm16, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2dqx (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2dq (%rax){1to2}, %xmm19
+# CHECK-NEXT: 2 5 1.00 vcvttpd2dq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvttpd2dqx (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2dq (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvttpd2dq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2dqx (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2dq (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvttps2dq %xmm16, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvttps2dq (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvttps2dq (%rax){1to4}, %xmm19
+# CHECK-NEXT: 2 5 1.00 vcvttps2dq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvttps2dq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvttps2dq (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvttps2dq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvttps2dq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvttps2dq (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvttps2dq %ymm16, %ymm19
+# CHECK-NEXT: 1 11 0.50 * vcvttps2dq (%rax), %ymm19
+# CHECK-NEXT: 1 11 0.50 * vcvttps2dq (%rax){1to8}, %ymm19
+# CHECK-NEXT: 2 5 1.00 vcvttps2dq %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvttps2dq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvttps2dq (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvttps2dq %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvttps2dq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvttps2dq (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvttpd2udq %ymm16, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2udqy (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2udq (%rax){1to4}, %xmm19
+# CHECK-NEXT: 2 5 1.00 vcvttpd2udq %ymm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvttpd2udqy (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2udq (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvttpd2udq %ymm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2udqy (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2udq (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvttpd2udq %xmm16, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2udqx (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2udq (%rax){1to2}, %xmm19
+# CHECK-NEXT: 2 5 1.00 vcvttpd2udq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvttpd2udqx (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2udq (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvttpd2udq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2udqx (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvttpd2udq (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvttps2udq %xmm16, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvttps2udq (%rax), %xmm19
+# CHECK-NEXT: 1 11 0.50 * vcvttps2udq (%rax){1to4}, %xmm19
+# CHECK-NEXT: 2 5 1.00 vcvttps2udq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvttps2udq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvttps2udq (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvttps2udq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvttps2udq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvttps2udq (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vcvttps2udq %ymm16, %ymm19
+# CHECK-NEXT: 1 11 0.50 * vcvttps2udq (%rax), %ymm19
+# CHECK-NEXT: 1 11 0.50 * vcvttps2udq (%rax){1to8}, %ymm19
+# CHECK-NEXT: 2 5 1.00 vcvttps2udq %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 2 12 1.00 * vcvttps2udq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vcvttps2udq (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vcvttps2udq %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvttps2udq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vcvttps2udq (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 6.00 vdivpd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 15 6.00 * vdivpd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 15 6.00 * vdivpd (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 6.00 vdivpd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 15 6.00 * vdivpd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 15 6.00 * vdivpd (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 6.00 vdivpd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 15 6.00 * vdivpd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 15 6.00 * vdivpd (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 6.00 vdivpd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 15 6.00 * vdivpd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 15 6.00 * vdivpd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 6.00 vdivpd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 15 6.00 * vdivpd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 15 6.00 * vdivpd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 6.00 vdivpd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 15 6.00 * vdivpd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 15 6.00 * vdivpd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 4.50 vdivps %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 17 4.50 * vdivps (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 17 4.50 * vdivps (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 4.50 vdivps %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 17 4.50 * vdivps (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 17 4.50 * vdivps (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 10 4.50 vdivps %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 17 4.50 * vdivps (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 17 4.50 * vdivps (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 4.50 vdivps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 17 4.50 * vdivps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 17 4.50 * vdivps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 4.50 vdivps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 17 4.50 * vdivps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 17 4.50 * vdivps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 4.50 vdivps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 17 4.50 * vdivps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 17 4.50 * vdivps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vfmadd132pd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vfmadd132pd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vfmadd132pd (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: 1 5 0.50 vfmadd132pd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 12 0.50 * vfmadd132pd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 12 0.50 * vfmadd132pd (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vfmadd132pd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vfmadd132pd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vfmadd132pd (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vfmadd132pd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 11 0.50 * vfmadd132pd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 11 0.50 * vfmadd132pd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 1 5 0.50 vfmadd132pd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 12 0.50 * vfmadd132pd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 12 0.50 * vfmadd132pd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vfmadd132pd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vfmadd132pd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vfmadd132pd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vfmadd213pd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vfmadd213pd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vfmadd213pd (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: 1 5 0.50 vfmadd213pd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 12 0.50 * vfmadd213pd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 12 0.50 * vfmadd213pd (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vfmadd213pd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vfmadd213pd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vfmadd213pd (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vfmadd213pd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 11 0.50 * vfmadd213pd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 11 0.50 * vfmadd213pd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 1 5 0.50 vfmadd213pd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 12 0.50 * vfmadd213pd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 12 0.50 * vfmadd213pd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vfmadd213pd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vfmadd213pd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vfmadd213pd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vfmadd231pd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vfmadd231pd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vfmadd231pd (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: 1 5 0.50 vfmadd231pd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 12 0.50 * vfmadd231pd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 12 0.50 * vfmadd231pd (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vfmadd231pd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vfmadd231pd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vfmadd231pd (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vfmadd231pd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 11 0.50 * vfmadd231pd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 11 0.50 * vfmadd231pd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 1 5 0.50 vfmadd231pd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 12 0.50 * vfmadd231pd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 12 0.50 * vfmadd231pd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vfmadd231pd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vfmadd231pd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vfmadd231pd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vfmadd132ps %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vfmadd132ps (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vfmadd132ps (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: 1 5 0.50 vfmadd132ps %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 12 0.50 * vfmadd132ps (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 12 0.50 * vfmadd132ps (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vfmadd132ps %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vfmadd132ps (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vfmadd132ps (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vfmadd132ps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 11 0.50 * vfmadd132ps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 11 0.50 * vfmadd132ps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 1 5 0.50 vfmadd132ps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 12 0.50 * vfmadd132ps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 12 0.50 * vfmadd132ps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vfmadd132ps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vfmadd132ps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vfmadd132ps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vfmadd213ps %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vfmadd213ps (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vfmadd213ps (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: 1 5 0.50 vfmadd213ps %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 12 0.50 * vfmadd213ps (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 12 0.50 * vfmadd213ps (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vfmadd213ps %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vfmadd213ps (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vfmadd213ps (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vfmadd213ps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 11 0.50 * vfmadd213ps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 11 0.50 * vfmadd213ps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 1 5 0.50 vfmadd213ps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 12 0.50 * vfmadd213ps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 12 0.50 * vfmadd213ps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vfmadd213ps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vfmadd213ps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vfmadd213ps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vfmadd231ps %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vfmadd231ps (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 11 0.50 * vfmadd231ps (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: 1 5 0.50 vfmadd231ps %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 12 0.50 * vfmadd231ps (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 12 0.50 * vfmadd231ps (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vfmadd231ps %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vfmadd231ps (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vfmadd231ps (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 4 0.50 vfmadd231ps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 11 0.50 * vfmadd231ps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 11 0.50 * vfmadd231ps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 1 5 0.50 vfmadd231ps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 12 0.50 * vfmadd231ps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 12 0.50 * vfmadd231ps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 4 0.50 vfmadd231ps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vfmadd231ps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 11 0.50 * vfmadd231ps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 8 0.33 * vgatherdpd (%rax,%xmm1,2), %ymm2 {%k1}
+# CHECK-NEXT: 2 8 0.33 * vgatherdps (%rax,%ymm1,2), %ymm2 {%k1}
+# CHECK-NEXT: 2 8 0.33 * vgatherqpd (%rax,%ymm1,2), %ymm2 {%k1}
+# CHECK-NEXT: 2 8 0.33 * vgatherqps (%rax,%ymm1,2), %xmm2 {%k1}
+# CHECK-NEXT: 2 8 0.33 * vgatherdpd (%rax,%xmm1,2), %xmm2 {%k1}
+# CHECK-NEXT: 2 8 0.33 * vgatherdps (%rax,%xmm1,2), %xmm2 {%k1}
+# CHECK-NEXT: 2 8 0.33 * vgatherqpd (%rax,%xmm1,2), %xmm2 {%k1}
+# CHECK-NEXT: 2 8 0.33 * vgatherqps (%rax,%xmm1,2), %xmm2 {%k1}
+# CHECK-NEXT: 1 1 0.50 vmaxpd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vmaxpd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vmaxpd (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vmaxpd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vmaxpd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vmaxpd (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vmaxpd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vmaxpd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vmaxpd (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vmaxpd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vmaxpd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vmaxpd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vmaxpd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vmaxpd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vmaxpd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vmaxpd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vmaxpd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vmaxpd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vmaxps %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vmaxps (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vmaxps (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vmaxps %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vmaxps (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vmaxps (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vmaxps %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vmaxps (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vmaxps (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vmaxps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vmaxps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vmaxps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vmaxps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vmaxps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vmaxps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vmaxps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vmaxps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vmaxps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vminpd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vminpd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vminpd (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vminpd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vminpd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vminpd (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vminpd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vminpd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vminpd (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vminpd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vminpd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vminpd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vminpd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vminpd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vminpd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vminpd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vminpd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vminpd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vminps %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vminps (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vminps (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vminps %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vminps (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vminps (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vminps %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vminps (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vminps (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vminps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vminps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vminps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vminps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vminps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vminps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vminps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vminps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vminps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 0 0.25 vmovapd %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vmovapd (%rax), %xmm19
+# CHECK-NEXT: 1 1 0.33 * vmovapd %xmm16, (%rax)
+# CHECK-NEXT: 1 0 0.25 vmovapd %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vmovapd (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.33 * vmovapd %xmm16, (%rax) {%k1}
+# CHECK-NEXT: 1 0 0.25 vmovapd %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vmovapd (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 0 0.25 vmovapd %ymm16, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vmovapd (%rax), %ymm19
+# CHECK-NEXT: 1 1 0.33 * vmovapd %ymm16, (%rax)
+# CHECK-NEXT: 1 0 0.25 vmovapd %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vmovapd (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.33 * vmovapd %ymm16, (%rax) {%k1}
+# CHECK-NEXT: 1 0 0.25 vmovapd %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vmovapd (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 0 0.25 vmovaps %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vmovaps (%rax), %xmm19
+# CHECK-NEXT: 1 1 0.33 * vmovaps %xmm16, (%rax)
+# CHECK-NEXT: 1 0 0.25 vmovaps %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vmovaps (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.33 * vmovaps %xmm16, (%rax) {%k1}
+# CHECK-NEXT: 1 0 0.25 vmovaps %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vmovaps (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 0 0.25 vmovaps %ymm16, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vmovaps (%rax), %ymm19
+# CHECK-NEXT: 1 1 0.33 * vmovaps %ymm16, (%rax)
+# CHECK-NEXT: 1 0 0.25 vmovaps %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vmovaps (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.33 * vmovaps %ymm16, (%rax) {%k1}
+# CHECK-NEXT: 1 0 0.25 vmovaps %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vmovaps (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vmovddup %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vmovddup (%rax), %xmm19
+# CHECK-NEXT: 1 1 0.50 vmovddup %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vmovddup (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vmovddup %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vmovddup (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 0 0.25 vmovdqa32 %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vmovdqa32 (%rax), %xmm19
+# CHECK-NEXT: 1 1 0.33 * vmovdqa32 %xmm16, (%rax)
+# CHECK-NEXT: 1 0 0.25 vmovdqa32 %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vmovdqa32 (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.33 * vmovdqa32 %xmm16, (%rax) {%k1}
+# CHECK-NEXT: 1 0 0.25 vmovdqa32 %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vmovdqa32 (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 0 0.25 vmovdqa32 %ymm16, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vmovdqa32 (%rax), %ymm19
+# CHECK-NEXT: 1 1 0.33 * vmovdqa32 %ymm16, (%rax)
+# CHECK-NEXT: 1 0 0.25 vmovdqa32 %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vmovdqa32 (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.33 * vmovdqa32 %ymm16, (%rax) {%k1}
+# CHECK-NEXT: 1 0 0.25 vmovdqa32 %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vmovdqa32 (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 0 0.25 vmovdqa64 %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vmovdqa64 (%rax), %xmm19
+# CHECK-NEXT: 1 1 0.33 * vmovdqa64 %xmm16, (%rax)
+# CHECK-NEXT: 1 0 0.25 vmovdqa64 %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vmovdqa64 (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.33 * vmovdqa64 %xmm16, (%rax) {%k1}
+# CHECK-NEXT: 1 0 0.25 vmovdqa64 %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vmovdqa64 (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 0 0.25 vmovdqa64 %ymm16, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vmovdqa64 (%rax), %ymm19
+# CHECK-NEXT: 1 1 0.33 * vmovdqa64 %ymm16, (%rax)
+# CHECK-NEXT: 1 0 0.25 vmovdqa64 %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vmovdqa64 (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.33 * vmovdqa64 %ymm16, (%rax) {%k1}
+# CHECK-NEXT: 1 0 0.25 vmovdqa64 %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vmovdqa64 (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 0 0.25 vmovdqu32 %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vmovdqu32 (%rax), %xmm19
+# CHECK-NEXT: 1 1 0.33 * vmovdqu32 %xmm16, (%rax)
+# CHECK-NEXT: 1 0 0.25 vmovdqu32 %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vmovdqu32 (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.33 * vmovdqu32 %xmm16, (%rax) {%k1}
+# CHECK-NEXT: 1 0 0.25 vmovdqu32 %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vmovdqu32 (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 0 0.25 vmovdqu32 %ymm16, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vmovdqu32 (%rax), %ymm19
+# CHECK-NEXT: 1 1 0.33 * vmovdqu32 %ymm16, (%rax)
+# CHECK-NEXT: 1 0 0.25 vmovdqu32 %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vmovdqu32 (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.33 * vmovdqu32 %ymm16, (%rax) {%k1}
+# CHECK-NEXT: 1 0 0.25 vmovdqu32 %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vmovdqu32 (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 0 0.25 vmovdqu64 %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vmovdqu64 (%rax), %xmm19
+# CHECK-NEXT: 1 1 0.33 * vmovdqu64 %xmm16, (%rax)
+# CHECK-NEXT: 1 0 0.25 vmovdqu64 %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vmovdqu64 (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.33 * vmovdqu64 %xmm16, (%rax) {%k1}
+# CHECK-NEXT: 1 0 0.25 vmovdqu64 %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vmovdqu64 (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 0 0.25 vmovdqu64 %ymm16, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vmovdqu64 (%rax), %ymm19
+# CHECK-NEXT: 1 1 0.33 * vmovdqu64 %ymm16, (%rax)
+# CHECK-NEXT: 1 0 0.25 vmovdqu64 %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vmovdqu64 (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.33 * vmovdqu64 %ymm16, (%rax) {%k1}
+# CHECK-NEXT: 1 0 0.25 vmovdqu64 %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vmovdqu64 (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vmovddup %ymm16, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vmovddup (%rax), %ymm19
+# CHECK-NEXT: 1 1 0.50 vmovddup %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vmovddup (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vmovddup %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vmovddup (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * {evex} vmovntdqa (%rax), %xmm0
+# CHECK-NEXT: 1 8 0.33 * {evex} vmovntdqa (%rax), %ymm0
+# CHECK-NEXT: 1 1 0.50 vmovshdup %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vmovshdup (%rax), %xmm19
+# CHECK-NEXT: 1 1 0.50 vmovshdup %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vmovshdup (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vmovshdup %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vmovshdup (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vmovshdup %ymm16, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vmovshdup (%rax), %ymm19
+# CHECK-NEXT: 1 1 0.50 vmovshdup %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vmovshdup (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vmovshdup %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vmovshdup (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vmovsldup %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vmovsldup (%rax), %xmm19
+# CHECK-NEXT: 1 1 0.50 vmovsldup %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vmovsldup (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vmovsldup %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vmovsldup (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vmovsldup %ymm16, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vmovsldup (%rax), %ymm19
+# CHECK-NEXT: 1 1 0.50 vmovsldup %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vmovsldup (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vmovsldup %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vmovsldup (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 0 0.25 vmovupd %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vmovupd (%rax), %xmm19
+# CHECK-NEXT: 1 1 0.33 * vmovupd %xmm16, (%rax)
+# CHECK-NEXT: 1 0 0.25 vmovupd %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vmovupd (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.33 * vmovupd %xmm16, (%rax) {%k1}
+# CHECK-NEXT: 1 0 0.25 vmovupd %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vmovupd (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 0 0.25 vmovupd %ymm16, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vmovupd (%rax), %ymm19
+# CHECK-NEXT: 1 1 0.33 * vmovupd %ymm16, (%rax)
+# CHECK-NEXT: 1 0 0.25 vmovupd %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vmovupd (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.33 * vmovupd %ymm16, (%rax) {%k1}
+# CHECK-NEXT: 1 0 0.25 vmovupd %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vmovupd (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 0 0.25 vmovups %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vmovups (%rax), %xmm19
+# CHECK-NEXT: 1 1 0.33 * vmovups %xmm16, (%rax)
+# CHECK-NEXT: 1 0 0.25 vmovups %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vmovups (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.33 * vmovups %xmm16, (%rax) {%k1}
+# CHECK-NEXT: 1 0 0.25 vmovups %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vmovups (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 0 0.25 vmovups %ymm16, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vmovups (%rax), %ymm19
+# CHECK-NEXT: 1 1 0.33 * vmovups %ymm16, (%rax)
+# CHECK-NEXT: 1 0 0.25 vmovups %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vmovups (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.33 * vmovups %ymm16, (%rax) {%k1}
+# CHECK-NEXT: 1 0 0.25 vmovups %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vmovups (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vmulpd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vmulpd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vmulpd (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: 1 4 1.00 vmulpd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vmulpd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vmulpd (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vmulpd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vmulpd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vmulpd (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vmulpd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vmulpd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vmulpd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 1 4 1.00 vmulpd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vmulpd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vmulpd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vmulpd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vmulpd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vmulpd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vmulps %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vmulps (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vmulps (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: 1 4 1.00 vmulps %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vmulps (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vmulps (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vmulps %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vmulps (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vmulps (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vmulps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vmulps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vmulps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 1 4 1.00 vmulps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vmulps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vmulps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vmulps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vmulps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vmulps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpaddd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpaddd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpaddd (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: 1 1 0.25 vpaddd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpaddd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpaddd (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpaddd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpaddd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpaddd (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpaddd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpaddd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpaddd (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 1 1 0.25 vpaddd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpaddd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpaddd (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpaddd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpaddd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpaddd (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpaddq %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpaddq (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpaddq (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: 1 1 0.25 vpaddq %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpaddq (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpaddq (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpaddq %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpaddq (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpaddq (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpaddq %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpaddq (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpaddq (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 1 1 0.25 vpaddq %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpaddq (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpaddq (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpaddq %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpaddq (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpaddq (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpbroadcastd %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpbroadcastd (%rax), %xmm19
+# CHECK-NEXT: 1 2 0.50 vpbroadcastd %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpbroadcastd (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpbroadcastd %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpbroadcastd (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpbroadcastd %xmm16, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpbroadcastd (%rax), %ymm19
+# CHECK-NEXT: 1 4 2.00 vpbroadcastd %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 2.00 * vpbroadcastd (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpbroadcastd %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpbroadcastd (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpbroadcastq %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpbroadcastq (%rax), %xmm19
+# CHECK-NEXT: 1 2 0.50 vpbroadcastq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vpbroadcastq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpbroadcastq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpbroadcastq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpbroadcastq %xmm16, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpbroadcastq (%rax), %ymm19
+# CHECK-NEXT: 1 4 2.00 vpbroadcastq %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 2.00 * vpbroadcastq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpbroadcastq %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpbroadcastq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpcmpeqd %xmm0, %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqd (%rax), %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqd (%rax){1to4}, %xmm1, %k2
+# CHECK-NEXT: 2 6 0.75 vpcmpeqd %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 0.75 * vpcmpeqd (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqd (%rax){1to4}, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpeqd %ymm0, %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqd (%rax), %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqd (%rax){1to8}, %ymm1, %k2
+# CHECK-NEXT: 2 6 0.75 vpcmpeqd %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 0.75 * vpcmpeqd (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqd (%rax){1to8}, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpeqd %xmm0, %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqd (%rax), %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqd (%rax){1to4}, %xmm1, %k2
+# CHECK-NEXT: 2 6 0.75 vpcmpeqd %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 0.75 * vpcmpeqd (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqd (%rax){1to4}, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpeqd %ymm0, %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqd (%rax), %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqd (%rax){1to8}, %ymm1, %k2
+# CHECK-NEXT: 2 6 0.75 vpcmpeqd %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 0.75 * vpcmpeqd (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqd (%rax){1to8}, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpeqq %xmm0, %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqq (%rax), %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqq (%rax){1to2}, %xmm1, %k2
+# CHECK-NEXT: 2 6 0.75 vpcmpeqq %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 0.75 * vpcmpeqq (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqq (%rax){1to2}, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpeqq %ymm0, %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqq (%rax), %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqq (%rax){1to4}, %ymm1, %k2
+# CHECK-NEXT: 2 6 0.75 vpcmpeqq %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 0.75 * vpcmpeqq (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqq (%rax){1to4}, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpgtd %xmm0, %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpgtd (%rax), %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpgtd (%rax){1to4}, %xmm1, %k2
+# CHECK-NEXT: 2 6 0.75 vpcmpgtd %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 0.75 * vpcmpgtd (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.33 * vpcmpgtd (%rax){1to4}, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpgtd %ymm0, %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpgtd (%rax), %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpgtd (%rax){1to8}, %ymm1, %k2
+# CHECK-NEXT: 2 6 0.75 vpcmpgtd %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 0.75 * vpcmpgtd (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.33 * vpcmpgtd (%rax){1to8}, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpgtq %xmm0, %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpgtq (%rax), %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpgtq (%rax){1to2}, %xmm1, %k2
+# CHECK-NEXT: 2 6 0.75 vpcmpgtq %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 0.75 * vpcmpgtq (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.33 * vpcmpgtq (%rax){1to2}, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpgtq %ymm0, %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpgtq (%rax), %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpgtq (%rax){1to4}, %ymm1, %k2
+# CHECK-NEXT: 2 6 0.75 vpcmpgtq %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 0.75 * vpcmpgtq (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.33 * vpcmpgtq (%rax){1to4}, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpeqq %xmm0, %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqq (%rax), %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqq (%rax){1to2}, %xmm1, %k2
+# CHECK-NEXT: 2 6 0.75 vpcmpeqq %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 0.75 * vpcmpeqq (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqq (%rax){1to2}, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpeqq %ymm0, %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqq (%rax), %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqq (%rax){1to4}, %ymm1, %k2
+# CHECK-NEXT: 2 6 0.75 vpcmpeqq %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 0.75 * vpcmpeqq (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.33 * vpcmpeqq (%rax){1to4}, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpequd %xmm0, %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpequd (%rax), %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpequd (%rax){1to4}, %xmm1, %k2
+# CHECK-NEXT: 2 6 0.75 vpcmpequd %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 0.75 * vpcmpequd (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.33 * vpcmpequd (%rax){1to4}, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpequd %ymm0, %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpequd (%rax), %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpequd (%rax){1to8}, %ymm1, %k2
+# CHECK-NEXT: 2 6 0.75 vpcmpequd %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 0.75 * vpcmpequd (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.33 * vpcmpequd (%rax){1to8}, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpequq %xmm0, %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpequq (%rax), %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpequq (%rax){1to2}, %xmm1, %k2
+# CHECK-NEXT: 2 6 0.75 vpcmpequq %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 0.75 * vpcmpequq (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.33 * vpcmpequq (%rax){1to2}, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vpcmpequq %ymm0, %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpequq (%rax), %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vpcmpequq (%rax){1to4}, %ymm1, %k2
+# CHECK-NEXT: 2 6 0.75 vpcmpequq %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 0.75 * vpcmpequq (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.33 * vpcmpequq (%rax){1to4}, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 3 2.00 vpermd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 2.00 * vpermd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 2 9 2.00 * vpermd (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 1 4 2.00 vpermd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 2.00 * vpermd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 2 9 2.00 * vpermd (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 2.00 vpermd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 2.00 * vpermd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 9 2.00 * vpermd (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpermilpd $0, %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpermilpd $0, (%rax), %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpermilpd $0, (%rax){1to2}, %xmm19
+# CHECK-NEXT: 1 1 0.50 vpermilpd $0, %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpermilpd $0, (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpermilpd $0, (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpermilpd $0, %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpermilpd $0, (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpermilpd $0, (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpermilpd $0, %ymm16, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpermilpd $0, (%rax), %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpermilpd $0, (%rax){1to4}, %ymm19
+# CHECK-NEXT: 1 1 0.50 vpermilpd $0, %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpermilpd $0, (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpermilpd $0, (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpermilpd $0, %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpermilpd $0, (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpermilpd $0, (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 2.00 vpermilpd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 2.00 * vpermilpd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 10 2.00 * vpermilpd (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: 1 4 2.00 vpermilpd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 11 2.00 * vpermilpd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 10 2.00 * vpermilpd (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 3 2.00 vpermilpd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 2.00 * vpermilpd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 2.00 * vpermilpd (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 2.00 vpermilpd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 2.00 * vpermilpd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 2.00 * vpermilpd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 1 4 2.00 vpermilpd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 2.00 * vpermilpd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 2.00 * vpermilpd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 2.00 vpermilpd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 2.00 * vpermilpd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 2.00 * vpermilpd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpermilps $0, %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpermilps $0, (%rax), %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpermilps $0, (%rax){1to4}, %xmm19
+# CHECK-NEXT: 1 1 0.50 vpermilps $0, %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpermilps $0, (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpermilps $0, (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpermilps $0, %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpermilps $0, (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpermilps $0, (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpermilps $0, %ymm16, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpermilps $0, (%rax), %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpermilps $0, (%rax){1to8}, %ymm19
+# CHECK-NEXT: 1 1 0.50 vpermilps $0, %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpermilps $0, (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpermilps $0, (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpermilps $0, %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpermilps $0, (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpermilps $0, (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 2.00 vpermilps %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 2.00 * vpermilps (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 10 2.00 * vpermilps (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: 1 4 2.00 vpermilps %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 11 2.00 * vpermilps (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 10 2.00 * vpermilps (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 3 2.00 vpermilps %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 2.00 * vpermilps (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 2.00 * vpermilps (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 2.00 vpermilps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 2.00 * vpermilps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 2.00 * vpermilps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 1 4 2.00 vpermilps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 2.00 * vpermilps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 2.00 * vpermilps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 2.00 vpermilps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 2.00 * vpermilps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 2.00 * vpermilps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 2.00 vpermpd $0, %ymm16, %ymm19
+# CHECK-NEXT: 1 10 2.00 * vpermpd $0, (%rax), %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpermpd $0, (%rax){1to4}, %ymm19
+# CHECK-NEXT: 1 4 2.00 vpermpd $0, %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 2.00 * vpermpd $0, (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpermpd $0, (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 2.00 vpermpd $0, %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 2.00 * vpermpd $0, (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpermpd $0, (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 2.00 vpermpd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 2.00 * vpermpd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpermpd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 1 4 2.00 vpermpd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 2.00 * vpermpd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpermpd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 2.00 vpermpd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 2.00 * vpermpd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpermpd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 2.00 vpermps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 2.00 * vpermps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpermps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 1 4 2.00 vpermps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 2.00 * vpermps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpermps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 2.00 vpermps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 2.00 * vpermps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpermps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 2.00 vpermq $0, %ymm16, %ymm19
+# CHECK-NEXT: 1 10 2.00 * vpermq $0, (%rax), %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpermq $0, (%rax){1to4}, %ymm19
+# CHECK-NEXT: 1 4 2.00 vpermq $0, %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 2.00 * vpermq $0, (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpermq $0, (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 2.00 vpermq $0, %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 2.00 * vpermq $0, (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpermq $0, (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 2.00 vpermq %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 2.00 * vpermq (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 2 9 2.00 * vpermq (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 1 4 2.00 vpermq %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 2.00 * vpermq (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 2 9 2.00 * vpermq (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 2.00 vpermq %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 2.00 * vpermq (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 9 2.00 * vpermq (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 2 8 0.33 * vpgatherdq (%rax,%xmm1,2), %ymm2 {%k1}
+# CHECK-NEXT: 2 8 0.33 * vpgatherdd (%rax,%ymm1,2), %ymm2 {%k1}
+# CHECK-NEXT: 2 8 0.33 * vpgatherqq (%rax,%ymm1,2), %ymm2 {%k1}
+# CHECK-NEXT: 2 8 0.33 * vpgatherqd (%rax,%ymm1,2), %xmm2 {%k1}
+# CHECK-NEXT: 2 8 0.33 * vpgatherdq (%rax,%xmm1,2), %xmm2 {%k1}
+# CHECK-NEXT: 2 8 0.33 * vpgatherdd (%rax,%xmm1,2), %xmm2 {%k1}
+# CHECK-NEXT: 2 8 0.33 * vpgatherqq (%rax,%xmm1,2), %xmm2 {%k1}
+# CHECK-NEXT: 2 8 0.33 * vpgatherqd (%rax,%xmm1,2), %xmm2 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovdb %xmm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovdb %xmm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovdb %xmm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovdb %xmm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovdb %xmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovdb %ymm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovdb %ymm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovdb %ymm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovdb %ymm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovdb %ymm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovdw %xmm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovdw %xmm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovdw %xmm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovdw %xmm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovdw %xmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovdw %ymm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovdw %ymm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovdw %ymm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovdw %ymm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovdw %ymm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovqb %xmm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovqb %xmm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovqb %xmm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovqb %xmm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovqb %xmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovqb %ymm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovqb %ymm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovqb %ymm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovqb %ymm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovqb %ymm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovqd %xmm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovqd %xmm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovqd %xmm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovqd %xmm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovqd %xmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovqd %ymm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovqd %ymm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovqd %ymm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovqd %ymm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovqd %ymm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovqw %xmm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovqw %xmm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovqw %xmm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovqw %xmm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovqw %xmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovqw %ymm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovqw %ymm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovqw %ymm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovqw %ymm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovqw %ymm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovsdb %xmm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovsdb %xmm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovsdb %xmm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovsdb %xmm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovsdb %xmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovsdb %ymm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovsdb %ymm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovsdb %ymm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovsdb %ymm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovsdb %ymm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovsdw %xmm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovsdw %xmm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovsdw %xmm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovsdw %xmm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovsdw %xmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovsdw %ymm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovsdw %ymm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovsdw %ymm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovsdw %ymm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovsdw %ymm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovsqb %xmm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovsqb %xmm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovsqb %xmm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovsqb %xmm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovsqb %xmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovsqb %ymm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovsqb %ymm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovsqb %ymm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovsqb %ymm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovsqb %ymm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovsqd %xmm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovsqd %xmm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovsqd %xmm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovsqd %xmm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovsqd %xmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovsqd %ymm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovsqd %ymm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovsqd %ymm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovsqd %ymm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovsqd %ymm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovsqw %xmm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovsqw %xmm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovsqw %xmm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovsqw %xmm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovsqw %xmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovsqw %ymm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovsqw %ymm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovsqw %ymm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovsqw %ymm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovsqw %ymm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpmovsxbd %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpmovsxbd (%rax), %xmm19
+# CHECK-NEXT: 1 1 0.50 vpmovsxbd %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpmovsxbd (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpmovsxbd %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpmovsxbd (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovsxbd %xmm16, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpmovsxbd (%rax), %ymm19
+# CHECK-NEXT: 1 3 0.50 vpmovsxbd %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovsxbd (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovsxbd %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmovsxbd (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpmovsxbq %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpmovsxbq (%rax), %xmm19
+# CHECK-NEXT: 1 1 0.50 vpmovsxbq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpmovsxbq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpmovsxbq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpmovsxbq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovsxbq %xmm16, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpmovsxbq (%rax), %ymm19
+# CHECK-NEXT: 1 3 0.50 vpmovsxbq %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovsxbq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovsxbq %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmovsxbq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpmovsxdq %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpmovsxdq (%rax), %xmm19
+# CHECK-NEXT: 1 1 0.50 vpmovsxdq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpmovsxdq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpmovsxdq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpmovsxdq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovsxdq %xmm16, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpmovsxdq (%rax), %ymm19
+# CHECK-NEXT: 1 3 0.50 vpmovsxdq %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovsxdq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovsxdq %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmovsxdq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpmovsxwd %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpmovsxwd (%rax), %xmm19
+# CHECK-NEXT: 1 1 0.50 vpmovsxwd %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpmovsxwd (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpmovsxwd %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpmovsxwd (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovsxwd %xmm16, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpmovsxwd (%rax), %ymm19
+# CHECK-NEXT: 1 3 0.50 vpmovsxwd %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovsxwd (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovsxwd %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmovsxwd (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpmovsxwq %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpmovsxwq (%rax), %xmm19
+# CHECK-NEXT: 1 1 0.50 vpmovsxwq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpmovsxwq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpmovsxwq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpmovsxwq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovsxwq %xmm16, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpmovsxwq (%rax), %ymm19
+# CHECK-NEXT: 1 3 0.50 vpmovsxwq %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovsxwq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovsxwq %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmovsxwq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovusdb %xmm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovusdb %xmm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovusdb %xmm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovusdb %xmm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovusdb %xmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovusdb %ymm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovusdb %ymm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovusdb %ymm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovusdb %ymm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovusdb %ymm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovusdw %xmm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovusdw %xmm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovusdw %xmm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovusdw %xmm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovusdw %xmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovusdw %ymm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovusdw %ymm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovusdw %ymm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovusdw %ymm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovusdw %ymm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovusqb %xmm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovusqb %xmm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovusqb %xmm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovusqb %xmm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovusqb %xmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovusqb %ymm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovusqb %ymm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovusqb %ymm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovusqb %ymm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovusqb %ymm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovusqd %xmm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovusqd %xmm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovusqd %xmm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovusqd %xmm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovusqd %xmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovusqd %ymm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovusqd %ymm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovusqd %ymm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovusqd %ymm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovusqd %ymm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovusqw %xmm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovusqw %xmm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovusqw %xmm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovusqw %xmm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovusqw %xmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovusqw %ymm19, %xmm16
+# CHECK-NEXT: 1 10 0.50 * vpmovusqw %ymm19, (%rax)
+# CHECK-NEXT: 1 3 0.50 vpmovusqw %ymm19, %xmm16 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovusqw %ymm19, (%rax) {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovusqw %ymm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpmovzxbd %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpmovzxbd (%rax), %xmm19
+# CHECK-NEXT: 1 1 0.50 vpmovzxbd %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpmovzxbd (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpmovzxbd %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpmovzxbd (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovzxbd %xmm16, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpmovzxbd (%rax), %ymm19
+# CHECK-NEXT: 1 3 0.50 vpmovzxbd %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovzxbd (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovzxbd %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmovzxbd (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpmovzxbq %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpmovzxbq (%rax), %xmm19
+# CHECK-NEXT: 1 1 0.50 vpmovzxbq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpmovzxbq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpmovzxbq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpmovzxbq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovzxbq %xmm16, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpmovzxbq (%rax), %ymm19
+# CHECK-NEXT: 1 3 0.50 vpmovzxbq %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovzxbq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovzxbq %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmovzxbq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpmovzxdq %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpmovzxdq (%rax), %xmm19
+# CHECK-NEXT: 1 1 0.50 vpmovzxdq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpmovzxdq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpmovzxdq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpmovzxdq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovzxdq %xmm16, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpmovzxdq (%rax), %ymm19
+# CHECK-NEXT: 1 3 0.50 vpmovzxdq %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovzxdq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovzxdq %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmovzxdq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpmovzxwd %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpmovzxwd (%rax), %xmm19
+# CHECK-NEXT: 1 1 0.50 vpmovzxwd %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpmovzxwd (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpmovzxwd %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpmovzxwd (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovzxwd %xmm16, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpmovzxwd (%rax), %ymm19
+# CHECK-NEXT: 1 3 0.50 vpmovzxwd %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovzxwd (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovzxwd %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmovzxwd (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpmovzxwq %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpmovzxwq (%rax), %xmm19
+# CHECK-NEXT: 1 1 0.50 vpmovzxwq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpmovzxwq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpmovzxwq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpmovzxwq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmovzxwq %xmm16, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpmovzxwq (%rax), %ymm19
+# CHECK-NEXT: 1 3 0.50 vpmovzxwq %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmovzxwq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmovzxwq %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmovzxwq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmulld %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpmulld (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpmulld (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: 1 4 1.00 vpmulld %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vpmulld (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmulld (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmulld %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmulld (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmulld (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpmulld %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpmulld (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpmulld (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 1 4 1.00 vpmulld %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vpmulld (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpmulld (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpmulld %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmulld (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpmulld (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 * vpscatterdd %xmm1, (%rdx,%xmm0,4) {%k1}
+# CHECK-NEXT: 1 1 0.50 * vpscatterdq %xmm1, (%rdx,%xmm0,4) {%k1}
+# CHECK-NEXT: 1 1 0.50 * vpscatterqd %xmm1, (%rdx,%xmm0,4) {%k1}
+# CHECK-NEXT: 1 1 0.50 * vpscatterqq %xmm1, (%rdx,%xmm0,4) {%k1}
+# CHECK-NEXT: 1 1 0.50 * vpscatterdd %ymm1, (%rdx,%ymm0,4) {%k1}
+# CHECK-NEXT: 1 1 0.50 * vpscatterdq %ymm1, (%rdx,%xmm0,4) {%k1}
+# CHECK-NEXT: 1 1 0.50 * vpscatterqd %xmm1, (%rdx,%ymm0,4) {%k1}
+# CHECK-NEXT: 1 1 0.50 * vpscatterqq %ymm1, (%rdx,%ymm0,4) {%k1}
+# CHECK-NEXT: 1 1 0.50 vpshufd $0, %xmm16, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpshufd $0, (%rax), %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpshufd $0, (%rax){1to4}, %xmm19
+# CHECK-NEXT: 1 1 0.50 vpshufd $0, %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpshufd $0, (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpshufd $0, (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpshufd $0, %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpshufd $0, (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpshufd $0, (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpshufd $0, %ymm16, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpshufd $0, (%rax), %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpshufd $0, (%rax){1to8}, %ymm19
+# CHECK-NEXT: 1 1 0.50 vpshufd $0, %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpshufd $0, (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpshufd $0, (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpshufd $0, %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpshufd $0, (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpshufd $0, (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpsubd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpsubd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpsubd (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: 1 1 0.25 vpsubd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpsubd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpsubd (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpsubd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpsubd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpsubd (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpsubd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpsubd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpsubd (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 1 1 0.25 vpsubd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpsubd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpsubd (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpsubd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpsubd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpsubd (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpsubq %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpsubq (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.33 * vpsubq (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: 1 1 0.25 vpsubq %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpsubq (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpsubq (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpsubq %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpsubq (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpsubq (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpsubq %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpsubq (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.33 * vpsubq (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 1 1 0.25 vpsubq %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpsubq (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpsubq (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpsubq %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpsubq (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpsubq (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vptestmd %xmm0, %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestmd (%rax), %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestmd (%rax){1to4}, %xmm1, %k2
+# CHECK-NEXT: 2 6 1.00 vptestmd %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 1.00 * vptestmd (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.33 * vptestmd (%rax){1to4}, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vptestmd %ymm0, %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestmd (%rax), %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestmd (%rax){1to8}, %ymm1, %k2
+# CHECK-NEXT: 2 6 1.00 vptestmd %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 1.00 * vptestmd (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.33 * vptestmd (%rax){1to8}, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vptestmq %xmm0, %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestmq (%rax), %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestmq (%rax){1to2}, %xmm1, %k2
+# CHECK-NEXT: 2 6 1.00 vptestmq %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 1.00 * vptestmq (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.33 * vptestmq (%rax){1to2}, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vptestmq %ymm0, %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestmq (%rax), %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestmq (%rax){1to4}, %ymm1, %k2
+# CHECK-NEXT: 2 6 1.00 vptestmq %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 1.00 * vptestmq (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.33 * vptestmq (%rax){1to4}, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vptestnmd %xmm0, %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestnmd (%rax), %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestnmd (%rax){1to4}, %xmm1, %k2
+# CHECK-NEXT: 2 6 1.00 vptestnmd %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 1.00 * vptestnmd (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.33 * vptestnmd (%rax){1to4}, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vptestnmd %ymm0, %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestnmd (%rax), %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestnmd (%rax){1to8}, %ymm1, %k2
+# CHECK-NEXT: 2 6 1.00 vptestnmd %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 1.00 * vptestnmd (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.33 * vptestnmd (%rax){1to8}, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vptestnmq %xmm0, %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestnmq (%rax), %xmm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestnmq (%rax){1to2}, %xmm1, %k2
+# CHECK-NEXT: 2 6 1.00 vptestnmq %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 1.00 * vptestnmq (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.33 * vptestnmq (%rax){1to2}, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.25 vptestnmq %ymm0, %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestnmq (%rax), %ymm1, %k2
+# CHECK-NEXT: 1 8 0.33 * vptestnmq (%rax){1to4}, %ymm1, %k2
+# CHECK-NEXT: 2 6 1.00 vptestnmq %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 2 13 1.00 * vptestnmq (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 8 0.33 * vptestnmq (%rax){1to4}, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 1 1 0.50 vpunpckhdq %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpunpckhdq (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpunpckhdq (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: 1 1 0.50 vpunpckhdq %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpunpckhdq (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpunpckhdq (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpunpckhdq %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpunpckhdq (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpunpckhdq (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpunpckhdq %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpunpckhdq (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpunpckhdq (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 1 1 0.50 vpunpckhdq %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpunpckhdq (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpunpckhdq (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpunpckhdq %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpunpckhdq (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpunpckhdq (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpunpckldq %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpunpckldq (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vpunpckldq (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: 1 1 0.50 vpunpckldq %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpunpckldq (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpunpckldq (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpunpckldq %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpunpckldq (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpunpckldq (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpunpckldq %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpunpckldq (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vpunpckldq (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 1 1 0.50 vpunpckldq %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpunpckldq (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpunpckldq (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpunpckldq %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpunpckldq (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpunpckldq (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 * vscatterdps %xmm1, (%rdx,%xmm0,4) {%k1}
+# CHECK-NEXT: 1 1 0.50 * vscatterdpd %xmm1, (%rdx,%xmm0,4) {%k1}
+# CHECK-NEXT: 1 1 0.50 * vscatterqps %xmm1, (%rdx,%xmm0,4) {%k1}
+# CHECK-NEXT: 1 1 0.50 * vscatterqpd %xmm1, (%rdx,%xmm0,4) {%k1}
+# CHECK-NEXT: 1 1 0.50 * vscatterdps %ymm1, (%rdx,%ymm0,4) {%k1}
+# CHECK-NEXT: 1 1 0.50 * vscatterdpd %ymm1, (%rdx,%xmm0,4) {%k1}
+# CHECK-NEXT: 1 1 0.50 * vscatterqps %xmm1, (%rdx,%ymm0,4) {%k1}
+# CHECK-NEXT: 1 1 0.50 * vscatterqpd %ymm1, (%rdx,%ymm0,4) {%k1}
+# CHECK-NEXT: 1 3 0.50 vshuff32x4 $0, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vshuff32x4 $0, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vshuff32x4 $0, (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 1 3 2.00 vshuff32x4 $0, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 2.00 * vshuff32x4 $0, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vshuff32x4 $0, (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vshuff32x4 $0, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vshuff32x4 $0, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vshuff32x4 $0, (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vshuff64x2 $0, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vshuff64x2 $0, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vshuff64x2 $0, (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 1 3 2.00 vshuff64x2 $0, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 2.00 * vshuff64x2 $0, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vshuff64x2 $0, (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vshuff64x2 $0, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vshuff64x2 $0, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vshuff64x2 $0, (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vshufi32x4 $0, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vshufi32x4 $0, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vshufi32x4 $0, (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 1 3 2.00 vshufi32x4 $0, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 2.00 * vshufi32x4 $0, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vshufi32x4 $0, (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vshufi32x4 $0, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vshufi32x4 $0, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vshufi32x4 $0, (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vshufi64x2 $0, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vshufi64x2 $0, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vshufi64x2 $0, (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 1 3 2.00 vshufi64x2 $0, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 2.00 * vshufi64x2 $0, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vshufi64x2 $0, (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vshufi64x2 $0, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vshufi64x2 $0, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vshufi64x2 $0, (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 9.50 vsqrtpd %xmm16, %xmm19
+# CHECK-NEXT: 1 15 9.50 * vsqrtpd (%rax), %xmm19
+# CHECK-NEXT: 1 15 9.50 * vsqrtpd (%rax){1to2}, %xmm19
+# CHECK-NEXT: 1 8 9.50 vsqrtpd %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 15 9.50 * vsqrtpd (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 15 9.50 * vsqrtpd (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 9.50 vsqrtpd %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 15 9.50 * vsqrtpd (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 15 9.50 * vsqrtpd (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 9.50 vsqrtpd %ymm16, %ymm19
+# CHECK-NEXT: 1 15 9.50 * vsqrtpd (%rax), %ymm19
+# CHECK-NEXT: 1 15 9.50 * vsqrtpd (%rax){1to4}, %ymm19
+# CHECK-NEXT: 1 8 9.50 vsqrtpd %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 15 9.50 * vsqrtpd (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 15 9.50 * vsqrtpd (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 9.50 vsqrtpd %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 15 9.50 * vsqrtpd (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 15 9.50 * vsqrtpd (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 6.50 vsqrtps %xmm16, %xmm19
+# CHECK-NEXT: 1 15 6.50 * vsqrtps (%rax), %xmm19
+# CHECK-NEXT: 1 15 6.50 * vsqrtps (%rax){1to4}, %xmm19
+# CHECK-NEXT: 1 8 6.50 vsqrtps %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 1 15 6.50 * vsqrtps (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 1 15 6.50 * vsqrtps (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 6.50 vsqrtps %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 15 6.50 * vsqrtps (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 15 6.50 * vsqrtps (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 6.50 vsqrtps %ymm16, %ymm19
+# CHECK-NEXT: 1 15 6.50 * vsqrtps (%rax), %ymm19
+# CHECK-NEXT: 1 15 6.50 * vsqrtps (%rax){1to8}, %ymm19
+# CHECK-NEXT: 1 8 6.50 vsqrtps %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 1 15 6.50 * vsqrtps (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 1 15 6.50 * vsqrtps (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 6.50 vsqrtps %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 15 6.50 * vsqrtps (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 15 6.50 * vsqrtps (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vsubpd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vsubpd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vsubpd (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: 1 4 0.50 vsubpd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vsubpd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vsubpd (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vsubpd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vsubpd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vsubpd (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vsubpd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vsubpd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vsubpd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 1 4 0.50 vsubpd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vsubpd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vsubpd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vsubpd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vsubpd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vsubpd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vsubps %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vsubps (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vsubps (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: 1 4 0.50 vsubps %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vsubps (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vsubps (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vsubps %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vsubps (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vsubps (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vsubps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vsubps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vsubps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 1 4 0.50 vsubps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vsubps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vsubps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vsubps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vsubps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vsubps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vunpckhpd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vunpckhpd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vunpckhpd (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vunpckhpd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vunpckhpd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vunpckhpd (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vunpckhpd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vunpckhpd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vunpckhpd (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vunpckhpd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vunpckhpd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vunpckhpd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vunpckhpd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vunpckhpd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vunpckhpd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vunpckhpd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vunpckhpd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vunpckhpd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vunpckhps %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vunpckhps (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vunpckhps (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vunpckhps %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vunpckhps (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vunpckhps (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vunpckhps %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vunpckhps (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vunpckhps (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vunpckhps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vunpckhps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vunpckhps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vunpckhps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vunpckhps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vunpckhps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vunpckhps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vunpckhps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vunpckhps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vunpcklpd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vunpcklpd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vunpcklpd (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vunpcklpd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vunpcklpd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vunpcklpd (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vunpcklpd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vunpcklpd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vunpcklpd (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vunpcklpd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vunpcklpd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vunpcklpd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vunpcklpd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vunpcklpd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vunpcklpd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vunpcklpd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vunpcklpd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vunpcklpd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vunpcklps %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vunpcklps (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 8 0.50 * vunpcklps (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: 1 2 0.50 vunpcklps %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vunpcklps (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vunpcklps (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vunpcklps %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vunpcklps (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vunpcklps (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vunpcklps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vunpcklps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 8 0.50 * vunpcklps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 1 2 0.50 vunpcklps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 9 0.50 * vunpcklps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vunpcklps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 1 0.50 vunpcklps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vunpcklps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vunpcklps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 350.33 350.33 350.33 - - - - - 556.00 889.50 550.50 896.00 266.75 266.75 266.75 266.75 334.33 334.33 334.33 16.00 16.00 16.00 16.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaddpd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddpd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddpd (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vaddpd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddpd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddpd (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaddpd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddpd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddpd (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaddpd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddpd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddpd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vaddpd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddpd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddpd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaddpd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddpd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddpd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaddps %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddps (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddps (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vaddps %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddps (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddps (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaddps %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddps (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddps (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaddps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vaddps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaddps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaddps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - valignd $1, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignd $1, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignd $1, (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - valignd $1, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignd $1, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignd $1, (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - valignd $1, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignd $1, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignd $1, (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - valignd $1, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignd $1, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignd $1, (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - valignd $1, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignd $1, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignd $1, (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - valignd $1, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignd $1, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignd $1, (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - valignq $1, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignq $1, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignq $1, (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - valignq $1, %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignq $1, (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignq $1, (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - valignq $1, %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignq $1, (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignq $1, (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - valignq $1, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignq $1, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignq $1, (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - valignq $1, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignq $1, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignq $1, (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - valignq $1, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignq $1, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - valignq $1, (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastf32x4 (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastf32x4 (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastf32x4 (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcasti32x4 (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcasti32x4 (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcasti32x4 (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vbroadcastsd %xmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastsd (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vbroadcastsd %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastsd (%rax), %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vbroadcastsd %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastsd (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vbroadcastss %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastss (%rax), %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vbroadcastss %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastss (%rax), %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vbroadcastss %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastss (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vbroadcastss %xmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastss (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vbroadcastss %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastss (%rax), %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vbroadcastss %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vbroadcastss (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vcmpeqpd %xmm0, %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqpd (%rax), %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqpd (%rax){1to2}, %xmm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vcmpeqpd %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqpd (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqpd (%rax){1to2}, %xmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vcmpeqpd %ymm0, %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqpd (%rax), %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqpd (%rax){1to4}, %ymm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vcmpeqpd %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqpd (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqpd (%rax){1to4}, %ymm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vcmpeqps %xmm0, %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqps (%rax), %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqps (%rax){1to4}, %xmm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vcmpeqps %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqps (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqps (%rax){1to4}, %xmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vcmpeqps %ymm0, %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqps (%rax), %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqps (%rax){1to8}, %ymm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vcmpeqps %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqps (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcmpeqps (%rax){1to8}, %ymm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtdq2pd %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2pd (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2pd (%rax){1to2}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtdq2pd %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2pd (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2pd (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtdq2pd %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2pd (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2pd (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtdq2pd %xmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2pd (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2pd (%rax){1to4}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtdq2pd %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2pd (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2pd (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtdq2pd %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2pd (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2pd (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtdq2ps %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2ps (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2ps (%rax){1to4}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtdq2ps %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2ps (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2ps (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtdq2ps %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2ps (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2ps (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtdq2ps %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2ps (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2ps (%rax){1to8}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtdq2ps %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2ps (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2ps (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtdq2ps %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2ps (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtdq2ps (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtpd2dq %ymm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2dqy (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2dq (%rax){1to4}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2dq %ymm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2dqy (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2dq (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtpd2dq %ymm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2dqy (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2dq (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtpd2dq %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2dqx (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2dq (%rax){1to2}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2dq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2dqx (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2dq (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtpd2dq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2dqx (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2dq (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtpd2ps %ymm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2psy (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2ps (%rax){1to4}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2ps %ymm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2psy (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2ps (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtpd2ps %ymm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2psy (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2ps (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtpd2ps %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2psx (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2ps (%rax){1to2}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2ps %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2psx (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2ps (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtpd2ps %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2psx (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2ps (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtpd2udq %ymm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2udqy (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2udq (%rax){1to4}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2udq %ymm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2udqy (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2udq (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtpd2udq %ymm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2udqy (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2udq (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtpd2udq %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2udqx (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2udq (%rax){1to2}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtpd2udq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2udqx (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2udq (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtpd2udq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2udqx (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtpd2udq (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtps2dq %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2dq (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2dq (%rax){1to4}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtps2dq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2dq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2dq (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtps2dq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2dq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2dq (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtps2dq %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2dq (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2dq (%rax){1to8}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtps2dq %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2dq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2dq (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtps2dq %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2dq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2dq (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtps2pd %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2pd (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2pd (%rax){1to2}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtps2pd %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2pd (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2pd (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtps2pd %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2pd (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2pd (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtps2pd %xmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2pd (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2pd (%rax){1to4}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtps2pd %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2pd (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2pd (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtps2pd %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2pd (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2pd (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtps2udq %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2udq (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2udq (%rax){1to4}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtps2udq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2udq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2udq (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtps2udq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2udq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2udq (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtps2udq %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2udq (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2udq (%rax){1to8}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvtps2udq %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2udq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2udq (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtps2udq %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2udq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtps2udq (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvttpd2dq %ymm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2dqy (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2dq (%rax){1to4}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttpd2dq %ymm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2dqy (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2dq (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvttpd2dq %ymm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2dqy (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2dq (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvttpd2dq %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2dqx (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2dq (%rax){1to2}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttpd2dq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2dqx (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2dq (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvttpd2dq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2dqx (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2dq (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvttps2dq %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2dq (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2dq (%rax){1to4}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttps2dq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2dq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2dq (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvttps2dq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2dq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2dq (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvttps2dq %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2dq (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2dq (%rax){1to8}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttps2dq %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2dq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2dq (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvttps2dq %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2dq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2dq (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvttpd2udq %ymm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2udqy (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2udq (%rax){1to4}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttpd2udq %ymm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2udqy (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2udq (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvttpd2udq %ymm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2udqy (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2udq (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvttpd2udq %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2udqx (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2udq (%rax){1to2}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttpd2udq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2udqx (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2udq (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvttpd2udq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2udqx (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttpd2udq (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvttps2udq %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2udq (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2udq (%rax){1to4}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttps2udq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2udq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2udq (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvttps2udq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2udq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2udq (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvttps2udq %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2udq (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2udq (%rax){1to8}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - vcvttps2udq %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2udq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2udq (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvttps2udq %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2udq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvttps2udq (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 6.00 - 6.00 - - - - - - - - - - - vdivpd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.00 - 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivpd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.00 - 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivpd (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - - 6.00 - 6.00 - - - - - - - - - - - vdivpd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.00 - 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivpd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.00 - 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivpd (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 6.00 - 6.00 - - - - - - - - - - - vdivpd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.00 - 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivpd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.00 - 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivpd (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 6.00 - 6.00 - - - - - - - - - - - vdivpd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.00 - 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivpd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.00 - 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivpd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - - 6.00 - 6.00 - - - - - - - - - - - vdivpd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.00 - 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivpd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.00 - 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivpd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 6.00 - 6.00 - - - - - - - - - - - vdivpd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.00 - 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivpd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.00 - 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivpd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 4.50 - 4.50 - - - - - - - - - - - vdivps %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.50 - 4.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivps (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.50 - 4.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivps (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - - 4.50 - 4.50 - - - - - - - - - - - vdivps %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.50 - 4.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivps (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.50 - 4.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivps (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 4.50 - 4.50 - - - - - - - - - - - vdivps %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.50 - 4.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivps (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.50 - 4.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivps (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 4.50 - 4.50 - - - - - - - - - - - vdivps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.50 - 4.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.50 - 4.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - - 4.50 - 4.50 - - - - - - - - - - - vdivps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.50 - 4.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.50 - 4.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 4.50 - 4.50 - - - - - - - - - - - vdivps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.50 - 4.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.50 - 4.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vdivps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd132pd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132pd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132pd (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd132pd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132pd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132pd (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd132pd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132pd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132pd (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd132pd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132pd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132pd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd132pd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132pd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132pd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd132pd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132pd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132pd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd213pd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213pd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213pd (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd213pd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213pd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213pd (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd213pd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213pd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213pd (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd213pd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213pd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213pd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd213pd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213pd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213pd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd213pd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213pd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213pd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd231pd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231pd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231pd (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd231pd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231pd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231pd (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd231pd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231pd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231pd (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd231pd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231pd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231pd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd231pd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231pd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231pd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd231pd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231pd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231pd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd132ps %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132ps (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132ps (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd132ps %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132ps (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132ps (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd132ps %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132ps (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132ps (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd132ps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132ps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132ps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd132ps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132ps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132ps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd132ps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132ps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132ps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd213ps %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213ps (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213ps (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd213ps %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213ps (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213ps (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd213ps %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213ps (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213ps (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd213ps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213ps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213ps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd213ps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213ps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213ps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd213ps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213ps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213ps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd231ps %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231ps (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231ps (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd231ps %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231ps (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231ps (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd231ps %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231ps (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231ps (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd231ps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231ps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231ps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd231ps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231ps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231ps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd231ps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231ps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231ps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgatherdpd (%rax,%xmm1,2), %ymm2 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgatherdps (%rax,%ymm1,2), %ymm2 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgatherqpd (%rax,%ymm1,2), %ymm2 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgatherqps (%rax,%ymm1,2), %xmm2 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgatherdpd (%rax,%xmm1,2), %xmm2 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgatherdps (%rax,%xmm1,2), %xmm2 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgatherqpd (%rax,%xmm1,2), %xmm2 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgatherqps (%rax,%xmm1,2), %xmm2 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmaxpd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxpd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxpd (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmaxpd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxpd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxpd (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmaxpd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxpd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxpd (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmaxpd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxpd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxpd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmaxpd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxpd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxpd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmaxpd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxpd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxpd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmaxps %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxps (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxps (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmaxps %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxps (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxps (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmaxps %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxps (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxps (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmaxps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmaxps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmaxps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmaxps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vminpd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminpd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminpd (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vminpd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminpd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminpd (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vminpd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminpd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminpd (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vminpd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminpd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminpd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vminpd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminpd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminpd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vminpd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminpd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminpd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vminps %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminps (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminps (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vminps %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminps (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminps (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vminps %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminps (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminps (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vminps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vminps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vminps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vminps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovapd %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovapd (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovapd %xmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovapd %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovapd (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovapd %xmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovapd %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovapd (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovapd %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovapd (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovapd %ymm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovapd %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovapd (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovapd %ymm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovapd %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovapd (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovaps %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovaps (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovaps %xmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovaps %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovaps (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovaps %xmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovaps %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovaps (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovaps %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovaps (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovaps %ymm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovaps %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovaps (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovaps %ymm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovaps %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovaps (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vmovddup %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovddup (%rax), %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vmovddup %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovddup (%rax), %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vmovddup %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovddup (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqa32 %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqa32 (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqa32 %xmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqa32 %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqa32 (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqa32 %xmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqa32 %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqa32 (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqa32 %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqa32 (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqa32 %ymm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqa32 %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqa32 (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqa32 %ymm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqa32 %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqa32 (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqa64 %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqa64 (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqa64 %xmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqa64 %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqa64 (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqa64 %xmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqa64 %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqa64 (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqa64 %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqa64 (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqa64 %ymm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqa64 %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqa64 (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqa64 %ymm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqa64 %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqa64 (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu32 %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu32 (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqu32 %xmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu32 %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu32 (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqu32 %xmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu32 %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu32 (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu32 %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu32 (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqu32 %ymm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu32 %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu32 (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqu32 %ymm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu32 %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu32 (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu64 %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu64 (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqu64 %xmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu64 %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu64 (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqu64 %xmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu64 %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu64 (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu64 %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu64 (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqu64 %ymm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu64 %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu64 (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovdqu64 %ymm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovdqu64 %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovdqu64 (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vmovddup %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovddup (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vmovddup %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovddup (%rax), %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vmovddup %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovddup (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - {evex} vmovntdqa (%rax), %xmm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - {evex} vmovntdqa (%rax), %ymm0
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vmovshdup %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovshdup (%rax), %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vmovshdup %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovshdup (%rax), %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vmovshdup %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovshdup (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vmovshdup %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovshdup (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vmovshdup %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovshdup (%rax), %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vmovshdup %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovshdup (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vmovsldup %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovsldup (%rax), %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vmovsldup %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovsldup (%rax), %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vmovsldup %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovsldup (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vmovsldup %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovsldup (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vmovsldup %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovsldup (%rax), %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vmovsldup %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovsldup (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovupd %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovupd (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovupd %xmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovupd %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovupd (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovupd %xmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovupd %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovupd (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovupd %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovupd (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovupd %ymm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovupd %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovupd (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovupd %ymm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovupd %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovupd (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovups %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovups (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovups %xmm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovups %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovups (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovups %xmm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovups %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovups (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovups %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovups (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovups %ymm16, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovups %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovups (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vmovups %ymm16, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vmovups %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmovups (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmulpd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulpd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulpd (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vmulpd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulpd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulpd (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmulpd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulpd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulpd (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmulpd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulpd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulpd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vmulpd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulpd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulpd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmulpd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulpd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulpd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmulps %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulps (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulps (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vmulps %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulps (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulps (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmulps %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulps (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulps (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmulps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vmulps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vmulps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vmulps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddd (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddd (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddd (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddd (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddd (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddd (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddq %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddq (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddq (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddq %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddq (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddq (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddq %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddq (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddq (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddq %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddq (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddq (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddq %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddq (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddq (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpaddq %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddq (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpaddq (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpbroadcastd %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastd (%rax), %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpbroadcastd %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastd (%rax), %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpbroadcastd %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastd (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpbroadcastd %xmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastd (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpbroadcastd %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastd (%rax), %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpbroadcastd %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastd (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpbroadcastq %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastq (%rax), %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpbroadcastq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpbroadcastq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpbroadcastq %xmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastq (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpbroadcastq %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - - - - - - vpbroadcastq %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpbroadcastq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpeqd %xmm0, %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqd (%rax), %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqd (%rax){1to4}, %xmm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 1.00 0.50 1.00 - - - - - - - - - - - vpcmpeqd %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 1.00 0.50 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqd (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqd (%rax){1to4}, %xmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpeqd %ymm0, %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqd (%rax), %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqd (%rax){1to8}, %ymm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 1.00 0.50 1.00 - - - - - - - - - - - vpcmpeqd %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 1.00 0.50 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqd (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqd (%rax){1to8}, %ymm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpeqd %xmm0, %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqd (%rax), %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqd (%rax){1to4}, %xmm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 1.00 0.50 1.00 - - - - - - - - - - - vpcmpeqd %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 1.00 0.50 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqd (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqd (%rax){1to4}, %xmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpeqd %ymm0, %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqd (%rax), %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqd (%rax){1to8}, %ymm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 1.00 0.50 1.00 - - - - - - - - - - - vpcmpeqd %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 1.00 0.50 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqd (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqd (%rax){1to8}, %ymm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpeqq %xmm0, %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqq (%rax), %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqq (%rax){1to2}, %xmm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 1.00 0.50 1.00 - - - - - - - - - - - vpcmpeqq %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 1.00 0.50 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqq (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqq (%rax){1to2}, %xmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpeqq %ymm0, %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqq (%rax), %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqq (%rax){1to4}, %ymm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 1.00 0.50 1.00 - - - - - - - - - - - vpcmpeqq %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 1.00 0.50 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqq (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqq (%rax){1to4}, %ymm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpgtd %xmm0, %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtd (%rax), %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtd (%rax){1to4}, %xmm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 1.00 0.50 1.00 - - - - - - - - - - - vpcmpgtd %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 1.00 0.50 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtd (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtd (%rax){1to4}, %xmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpgtd %ymm0, %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtd (%rax), %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtd (%rax){1to8}, %ymm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 1.00 0.50 1.00 - - - - - - - - - - - vpcmpgtd %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 1.00 0.50 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtd (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtd (%rax){1to8}, %ymm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpgtq %xmm0, %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtq (%rax), %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtq (%rax){1to2}, %xmm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 1.00 0.50 1.00 - - - - - - - - - - - vpcmpgtq %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 1.00 0.50 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtq (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtq (%rax){1to2}, %xmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpgtq %ymm0, %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtq (%rax), %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtq (%rax){1to4}, %ymm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 1.00 0.50 1.00 - - - - - - - - - - - vpcmpgtq %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 1.00 0.50 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtq (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpgtq (%rax){1to4}, %ymm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpeqq %xmm0, %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqq (%rax), %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqq (%rax){1to2}, %xmm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 1.00 0.50 1.00 - - - - - - - - - - - vpcmpeqq %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 1.00 0.50 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqq (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqq (%rax){1to2}, %xmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpeqq %ymm0, %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqq (%rax), %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqq (%rax){1to4}, %ymm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 1.00 0.50 1.00 - - - - - - - - - - - vpcmpeqq %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 1.00 0.50 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqq (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpeqq (%rax){1to4}, %ymm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpequd %xmm0, %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequd (%rax), %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequd (%rax){1to4}, %xmm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 1.00 0.50 1.00 - - - - - - - - - - - vpcmpequd %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 1.00 0.50 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequd (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequd (%rax){1to4}, %xmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpequd %ymm0, %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequd (%rax), %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequd (%rax){1to8}, %ymm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 1.00 0.50 1.00 - - - - - - - - - - - vpcmpequd %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 1.00 0.50 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequd (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequd (%rax){1to8}, %ymm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpequq %xmm0, %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequq (%rax), %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequq (%rax){1to2}, %xmm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 1.00 0.50 1.00 - - - - - - - - - - - vpcmpequq %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 1.00 0.50 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequq (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequq (%rax){1to2}, %xmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpcmpequq %ymm0, %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequq (%rax), %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequq (%rax){1to4}, %ymm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.50 1.00 0.50 1.00 - - - - - - - - - - - vpcmpequq %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 1.00 0.50 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequq (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpcmpequq (%rax){1to4}, %ymm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermd (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermd (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermd (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpermilpd $0, %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd $0, (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd $0, (%rax){1to2}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpermilpd $0, %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd $0, (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd $0, (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpermilpd $0, %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd $0, (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd $0, (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpermilpd $0, %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd $0, (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd $0, (%rax){1to4}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpermilpd $0, %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd $0, (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd $0, (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpermilpd $0, %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd $0, (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd $0, (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermilpd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermilpd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermilpd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermilpd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermilpd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermilpd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilpd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpermilps $0, %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps $0, (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps $0, (%rax){1to4}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpermilps $0, %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps $0, (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps $0, (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpermilps $0, %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps $0, (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps $0, (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpermilps $0, %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps $0, (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps $0, (%rax){1to8}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpermilps $0, %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps $0, (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps $0, (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpermilps $0, %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps $0, (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps $0, (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermilps %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermilps %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermilps %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermilps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermilps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermilps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermilps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermpd $0, %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermpd $0, (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermpd $0, (%rax){1to4}, %ymm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermpd $0, %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermpd $0, (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermpd $0, (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermpd $0, %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermpd $0, (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermpd $0, (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermpd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermpd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermpd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermpd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermpd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermpd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermpd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermpd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermpd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermq $0, %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermq $0, (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermq $0, (%rax){1to4}, %ymm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermq $0, %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermq $0, (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermq $0, (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermq $0, %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermq $0, (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermq $0, (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermq %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermq (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermq (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermq %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermq (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermq (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vpermq %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermq (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpermq (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpgatherdq (%rax,%xmm1,2), %ymm2 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpgatherdd (%rax,%ymm1,2), %ymm2 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpgatherqq (%rax,%ymm1,2), %ymm2 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpgatherqd (%rax,%ymm1,2), %xmm2 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpgatherdq (%rax,%xmm1,2), %xmm2 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpgatherdd (%rax,%xmm1,2), %xmm2 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpgatherqq (%rax,%xmm1,2), %xmm2 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpgatherqd (%rax,%xmm1,2), %xmm2 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovdb %xmm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovdb %xmm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovdb %xmm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovdb %xmm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovdb %xmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovdb %ymm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovdb %ymm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovdb %ymm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovdb %ymm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovdb %ymm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovdw %xmm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovdw %xmm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovdw %xmm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovdw %xmm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovdw %xmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovdw %ymm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovdw %ymm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovdw %ymm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovdw %ymm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovdw %ymm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovqb %xmm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovqb %xmm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovqb %xmm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovqb %xmm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovqb %xmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovqb %ymm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovqb %ymm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovqb %ymm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovqb %ymm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovqb %ymm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovqd %xmm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovqd %xmm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovqd %xmm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovqd %xmm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovqd %xmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovqd %ymm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovqd %ymm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovqd %ymm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovqd %ymm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovqd %ymm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovqw %xmm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovqw %xmm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovqw %xmm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovqw %xmm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovqw %xmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovqw %ymm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovqw %ymm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovqw %ymm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovqw %ymm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovqw %ymm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsdb %xmm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsdb %xmm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsdb %xmm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsdb %xmm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsdb %xmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsdb %ymm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsdb %ymm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsdb %ymm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsdb %ymm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsdb %ymm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsdw %xmm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsdw %xmm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsdw %xmm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsdw %xmm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsdw %xmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsdw %ymm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsdw %ymm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsdw %ymm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsdw %ymm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsdw %ymm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsqb %xmm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsqb %xmm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsqb %xmm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsqb %xmm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsqb %xmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsqb %ymm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsqb %ymm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsqb %ymm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsqb %ymm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsqb %ymm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsqd %xmm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsqd %xmm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsqd %xmm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsqd %xmm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsqd %xmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsqd %ymm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsqd %ymm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsqd %ymm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsqd %ymm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsqd %ymm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsqw %xmm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsqw %xmm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsqw %xmm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsqw %xmm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsqw %xmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsqw %ymm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsqw %ymm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsqw %ymm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsqw %ymm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsqw %ymm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovsxbd %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbd (%rax), %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovsxbd %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbd (%rax), %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovsxbd %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbd (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxbd %xmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbd (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxbd %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbd (%rax), %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxbd %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbd (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovsxbq %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbq (%rax), %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovsxbq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovsxbq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxbq %xmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbq (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxbq %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxbq %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxbq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovsxdq %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxdq (%rax), %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovsxdq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxdq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovsxdq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxdq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxdq %xmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxdq (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxdq %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxdq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxdq %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxdq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovsxwd %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxwd (%rax), %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovsxwd %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxwd (%rax), %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovsxwd %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxwd (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxwd %xmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxwd (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxwd %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxwd (%rax), %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxwd %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxwd (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovsxwq %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxwq (%rax), %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovsxwq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxwq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovsxwq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxwq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxwq %xmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxwq (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxwq %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxwq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovsxwq %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovsxwq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusdb %xmm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovusdb %xmm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusdb %xmm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovusdb %xmm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusdb %xmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusdb %ymm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovusdb %ymm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusdb %ymm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovusdb %ymm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusdb %ymm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusdw %xmm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovusdw %xmm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusdw %xmm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovusdw %xmm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusdw %xmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusdw %ymm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovusdw %ymm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusdw %ymm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovusdw %ymm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusdw %ymm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusqb %xmm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovusqb %xmm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusqb %xmm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovusqb %xmm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusqb %xmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusqb %ymm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovusqb %ymm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusqb %ymm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovusqb %ymm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusqb %ymm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusqd %xmm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovusqd %xmm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusqd %xmm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovusqd %xmm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusqd %xmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusqd %ymm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovusqd %ymm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusqd %ymm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovusqd %ymm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusqd %ymm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusqw %xmm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovusqw %xmm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusqw %xmm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovusqw %xmm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusqw %xmm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusqw %ymm19, %xmm16
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovusqw %ymm19, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusqw %ymm19, %xmm16 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovusqw %ymm19, (%rax) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovusqw %ymm19, %xmm16 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovzxbd %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbd (%rax), %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovzxbd %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbd (%rax), %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovzxbd %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbd (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxbd %xmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbd (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxbd %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbd (%rax), %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxbd %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbd (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovzxbq %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbq (%rax), %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovzxbq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovzxbq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxbq %xmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbq (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxbq %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxbq %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxbq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovzxdq %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxdq (%rax), %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovzxdq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxdq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovzxdq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxdq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxdq %xmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxdq (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxdq %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxdq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxdq %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxdq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovzxwd %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxwd (%rax), %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovzxwd %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxwd (%rax), %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovzxwd %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxwd (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxwd %xmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxwd (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxwd %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxwd (%rax), %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxwd %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxwd (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovzxwq %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxwq (%rax), %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovzxwq %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxwq (%rax), %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpmovzxwq %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxwq (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxwq %xmm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxwq (%rax), %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxwq %xmm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxwq (%rax), %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmovzxwq %xmm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmovzxwq (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmulld %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulld (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulld (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmulld %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulld (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulld (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmulld %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulld (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulld (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmulld %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulld (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulld (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpmulld %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulld (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulld (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpmulld %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulld (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpmulld (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 vpscatterdd %xmm1, (%rdx,%xmm0,4) {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 vpscatterdq %xmm1, (%rdx,%xmm0,4) {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 vpscatterqd %xmm1, (%rdx,%xmm0,4) {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 vpscatterqq %xmm1, (%rdx,%xmm0,4) {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 vpscatterdd %ymm1, (%rdx,%ymm0,4) {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 vpscatterdq %ymm1, (%rdx,%xmm0,4) {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 vpscatterqd %xmm1, (%rdx,%ymm0,4) {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 vpscatterqq %ymm1, (%rdx,%ymm0,4) {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpshufd $0, %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufd $0, (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufd $0, (%rax){1to4}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpshufd $0, %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufd $0, (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufd $0, (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpshufd $0, %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufd $0, (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufd $0, (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpshufd $0, %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufd $0, (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufd $0, (%rax){1to8}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpshufd $0, %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufd $0, (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufd $0, (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpshufd $0, %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufd $0, (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpshufd $0, (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubd (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubd (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubd (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubd (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubd (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubd (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubq %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubq (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubq (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubq %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubq (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubq (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubq %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubq (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubq (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubq %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubq (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubq (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubq %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubq (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubq (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpsubq %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubq (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpsubq (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vptestmd %xmm0, %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmd (%rax), %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmd (%rax){1to4}, %xmm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.75 1.25 0.75 1.25 - - - - - - - - - - - vptestmd %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.75 1.25 0.75 1.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmd (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmd (%rax){1to4}, %xmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vptestmd %ymm0, %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmd (%rax), %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmd (%rax){1to8}, %ymm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.75 1.25 0.75 1.25 - - - - - - - - - - - vptestmd %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.75 1.25 0.75 1.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmd (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmd (%rax){1to8}, %ymm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vptestmq %xmm0, %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmq (%rax), %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmq (%rax){1to2}, %xmm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.75 1.25 0.75 1.25 - - - - - - - - - - - vptestmq %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.75 1.25 0.75 1.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmq (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmq (%rax){1to2}, %xmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vptestmq %ymm0, %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmq (%rax), %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmq (%rax){1to4}, %ymm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.75 1.25 0.75 1.25 - - - - - - - - - - - vptestmq %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.75 1.25 0.75 1.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmq (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestmq (%rax){1to4}, %ymm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vptestnmd %xmm0, %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmd (%rax), %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmd (%rax){1to4}, %xmm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.75 1.25 0.75 1.25 - - - - - - - - - - - vptestnmd %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.75 1.25 0.75 1.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmd (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmd (%rax){1to4}, %xmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vptestnmd %ymm0, %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmd (%rax), %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmd (%rax){1to8}, %ymm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.75 1.25 0.75 1.25 - - - - - - - - - - - vptestnmd %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.75 1.25 0.75 1.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmd (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmd (%rax){1to8}, %ymm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vptestnmq %xmm0, %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmq (%rax), %xmm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmq (%rax){1to2}, %xmm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.75 1.25 0.75 1.25 - - - - - - - - - - - vptestnmq %xmm0, %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.75 1.25 0.75 1.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmq (%rax), %xmm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmq (%rax){1to2}, %xmm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vptestnmq %ymm0, %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmq (%rax), %ymm1, %k2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmq (%rax){1to4}, %ymm1, %k2
+# CHECK-NEXT: - - - - - - - - 0.75 1.25 0.75 1.25 - - - - - - - - - - - vptestnmq %ymm0, %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.75 1.25 0.75 1.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmq (%rax), %ymm1, %k2 {%k3}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vptestnmq (%rax){1to4}, %ymm1, %k2 {%k3}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckhdq %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhdq (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhdq (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckhdq %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhdq (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhdq (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckhdq %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhdq (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhdq (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckhdq %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhdq (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhdq (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckhdq %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhdq (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhdq (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckhdq %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhdq (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckhdq (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckldq %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckldq (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckldq (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckldq %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckldq (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckldq (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckldq %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckldq (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckldq (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckldq %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckldq (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckldq (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckldq %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckldq (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckldq (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vpunpckldq %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckldq (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpunpckldq (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 vscatterdps %xmm1, (%rdx,%xmm0,4) {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 vscatterdpd %xmm1, (%rdx,%xmm0,4) {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 vscatterqps %xmm1, (%rdx,%xmm0,4) {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 vscatterqpd %xmm1, (%rdx,%xmm0,4) {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 vscatterdps %ymm1, (%rdx,%ymm0,4) {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 vscatterdpd %ymm1, (%rdx,%xmm0,4) {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 vscatterqps %xmm1, (%rdx,%ymm0,4) {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 vscatterqpd %ymm1, (%rdx,%ymm0,4) {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vshuff32x4 $0, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshuff32x4 $0, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshuff32x4 $0, (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vshuff32x4 $0, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshuff32x4 $0, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshuff32x4 $0, (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vshuff32x4 $0, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshuff32x4 $0, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshuff32x4 $0, (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vshuff64x2 $0, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshuff64x2 $0, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshuff64x2 $0, (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vshuff64x2 $0, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshuff64x2 $0, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshuff64x2 $0, (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vshuff64x2 $0, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshuff64x2 $0, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshuff64x2 $0, (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vshufi32x4 $0, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshufi32x4 $0, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshufi32x4 $0, (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vshufi32x4 $0, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshufi32x4 $0, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshufi32x4 $0, (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vshufi32x4 $0, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshufi32x4 $0, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshufi32x4 $0, (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vshufi64x2 $0, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshufi64x2 $0, (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshufi64x2 $0, (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - vshufi64x2 $0, %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshufi64x2 $0, (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshufi64x2 $0, (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vshufi64x2 $0, %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshufi64x2 $0, (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vshufi64x2 $0, (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 9.50 - 9.50 - - - - - - - - - - - vsqrtpd %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 9.50 - 9.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtpd (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 9.50 - 9.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtpd (%rax){1to2}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 9.50 - 9.50 - - - - - - - - - - - vsqrtpd %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 9.50 - 9.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtpd (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 9.50 - 9.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtpd (%rax){1to2}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 9.50 - 9.50 - - - - - - - - - - - vsqrtpd %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 9.50 - 9.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtpd (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 9.50 - 9.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtpd (%rax){1to2}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 9.50 - 9.50 - - - - - - - - - - - vsqrtpd %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 9.50 - 9.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtpd (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 9.50 - 9.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtpd (%rax){1to4}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 9.50 - 9.50 - - - - - - - - - - - vsqrtpd %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 9.50 - 9.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtpd (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 9.50 - 9.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtpd (%rax){1to4}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 9.50 - 9.50 - - - - - - - - - - - vsqrtpd %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 9.50 - 9.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtpd (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 9.50 - 9.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtpd (%rax){1to4}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 6.50 - 6.50 - - - - - - - - - - - vsqrtps %xmm16, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.50 - 6.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtps (%rax), %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.50 - 6.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtps (%rax){1to4}, %xmm19
+# CHECK-NEXT: - - - - - - - - - 6.50 - 6.50 - - - - - - - - - - - vsqrtps %xmm16, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.50 - 6.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtps (%rax), %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.50 - 6.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtps (%rax){1to4}, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 6.50 - 6.50 - - - - - - - - - - - vsqrtps %xmm16, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.50 - 6.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtps (%rax), %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.50 - 6.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtps (%rax){1to4}, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 6.50 - 6.50 - - - - - - - - - - - vsqrtps %ymm16, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.50 - 6.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtps (%rax), %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.50 - 6.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtps (%rax){1to8}, %ymm19
+# CHECK-NEXT: - - - - - - - - - 6.50 - 6.50 - - - - - - - - - - - vsqrtps %ymm16, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.50 - 6.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtps (%rax), %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.50 - 6.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtps (%rax){1to8}, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 6.50 - 6.50 - - - - - - - - - - - vsqrtps %ymm16, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.50 - 6.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtps (%rax), %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.50 - 6.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsqrtps (%rax){1to8}, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vsubpd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubpd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubpd (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vsubpd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubpd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubpd (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vsubpd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubpd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubpd (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vsubpd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubpd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubpd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vsubpd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubpd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubpd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vsubpd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubpd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubpd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vsubps %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubps (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubps (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vsubps %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubps (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubps (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vsubps %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubps (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubps (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vsubps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vsubps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vsubps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vsubps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vunpckhpd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhpd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhpd (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vunpckhpd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhpd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhpd (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vunpckhpd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhpd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhpd (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vunpckhpd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhpd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhpd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vunpckhpd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhpd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhpd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vunpckhpd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhpd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhpd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vunpckhps %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhps (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhps (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vunpckhps %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhps (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhps (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vunpckhps %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhps (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhps (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vunpckhps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vunpckhps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vunpckhps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpckhps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vunpcklpd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklpd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklpd (%rax){1to2}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vunpcklpd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklpd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklpd (%rax){1to2}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vunpcklpd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklpd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklpd (%rax){1to2}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vunpcklpd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklpd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklpd (%rax){1to4}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vunpcklpd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklpd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklpd (%rax){1to4}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vunpcklpd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklpd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklpd (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vunpcklps %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklps (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklps (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vunpcklps %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklps (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklps (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vunpcklps %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklps (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklps (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vunpcklps %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklps (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklps (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vunpcklps %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklps (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklps (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vunpcklps %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklps (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vunpcklps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vnni.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vnni.s
new file mode 100644
index 0000000000000..8ec67dfe701f0
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vnni.s
@@ -0,0 +1,156 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+vpdpbusd %zmm16, %zmm17, %zmm19
+vpdpbusd (%rax), %zmm17, %zmm19
+vpdpbusd (%rax){1to16}, %zmm17, %zmm19
+vpdpbusd %zmm16, %zmm17, %zmm19 {k1}
+vpdpbusd (%rax), %zmm17, %zmm19 {k1}
+vpdpbusd (%rax){1to16}, %zmm17, %zmm19 {k1}
+vpdpbusd %zmm16, %zmm17, %zmm19 {z}{k1}
+vpdpbusd (%rax), %zmm17, %zmm19 {z}{k1}
+vpdpbusd (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
+
+vpdpbusds %zmm16, %zmm17, %zmm19
+vpdpbusds (%rax), %zmm17, %zmm19
+vpdpbusds (%rax){1to16}, %zmm17, %zmm19
+vpdpbusds %zmm16, %zmm17, %zmm19 {k1}
+vpdpbusds (%rax), %zmm17, %zmm19 {k1}
+vpdpbusds (%rax){1to16}, %zmm17, %zmm19 {k1}
+vpdpbusds %zmm16, %zmm17, %zmm19 {z}{k1}
+vpdpbusds (%rax), %zmm17, %zmm19 {z}{k1}
+vpdpbusds (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
+
+vpdpwssd %zmm16, %zmm17, %zmm19
+vpdpwssd (%rax), %zmm17, %zmm19
+vpdpwssd (%rax){1to16}, %zmm17, %zmm19
+vpdpwssd %zmm16, %zmm17, %zmm19 {k1}
+vpdpwssd (%rax), %zmm17, %zmm19 {k1}
+vpdpwssd (%rax){1to16}, %zmm17, %zmm19 {k1}
+vpdpwssd %zmm16, %zmm17, %zmm19 {z}{k1}
+vpdpwssd (%rax), %zmm17, %zmm19 {z}{k1}
+vpdpwssd (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
+
+vpdpwssds %zmm16, %zmm17, %zmm19
+vpdpwssds (%rax), %zmm17, %zmm19
+vpdpwssds (%rax){1to16}, %zmm17, %zmm19
+vpdpwssds %zmm16, %zmm17, %zmm19 {k1}
+vpdpwssds (%rax), %zmm17, %zmm19 {k1}
+vpdpwssds (%rax){1to16}, %zmm17, %zmm19 {k1}
+vpdpwssds %zmm16, %zmm17, %zmm19 {z}{k1}
+vpdpwssds (%rax), %zmm17, %zmm19 {z}{k1}
+vpdpwssds (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 1.00 vpdpbusd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vpdpbusd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vpdpbusd (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 1 4 1.00 vpdpbusd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vpdpbusd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 1.00 * vpdpbusd (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 3 1.00 vpdpbusd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vpdpbusd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vpdpbusd (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 1.00 vpdpbusds %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vpdpbusds (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vpdpbusds (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 1 4 1.00 vpdpbusds %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vpdpbusds (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 1.00 * vpdpbusds (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 3 1.00 vpdpbusds %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vpdpbusds (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vpdpbusds (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 1.00 vpdpwssd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vpdpwssd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vpdpwssd (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 1 4 1.00 vpdpwssd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vpdpwssd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 1.00 * vpdpwssd (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 3 1.00 vpdpwssd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vpdpwssd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vpdpwssd (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 1.00 vpdpwssds %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vpdpwssds (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 1 10 1.00 * vpdpwssds (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: 1 4 1.00 vpdpwssds %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 11 1.00 * vpdpwssds (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 10 1.00 * vpdpwssds (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 1 3 1.00 vpdpwssds %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vpdpwssds (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 1.00 * vpdpwssds (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 8.00 8.00 8.00 - - - - - 36.00 - 36.00 - 6.00 6.00 6.00 6.00 8.00 8.00 8.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpdpbusd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusd (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpdpbusd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusd (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpdpbusd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusd (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpdpbusds %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusds (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusds (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpdpbusds %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusds (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusds (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpdpbusds %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusds (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusds (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpdpwssd %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssd (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssd (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpdpwssd %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssd (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssd (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpdpwssd %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssd (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssd (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpdpwssds %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssds (%rax), %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssds (%rax){1to16}, %zmm17, %zmm19
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpdpwssds %zmm16, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssds (%rax), %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssds (%rax){1to16}, %zmm17, %zmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - vpdpwssds %zmm16, %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssds (%rax), %zmm17, %zmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssds (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vnnivl.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vnnivl.s
new file mode 100644
index 0000000000000..13a71f6b4bbdf
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vnnivl.s
@@ -0,0 +1,268 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+vpdpbusd %xmm16, %xmm17, %xmm19
+vpdpbusd (%rax), %xmm17, %xmm19
+vpdpbusd (%rax){1to4}, %xmm17, %xmm19
+vpdpbusd %xmm16, %xmm17, %xmm19 {k1}
+vpdpbusd (%rax), %xmm17, %xmm19 {k1}
+vpdpbusd (%rax){1to4}, %xmm17, %xmm19 {k1}
+vpdpbusd %xmm16, %xmm17, %xmm19 {z}{k1}
+vpdpbusd (%rax), %xmm17, %xmm19 {z}{k1}
+vpdpbusd (%rax){1to4}, %xmm17, %xmm19 {z}{k1}
+
+vpdpbusd %ymm16, %ymm17, %ymm19
+vpdpbusd (%rax), %ymm17, %ymm19
+vpdpbusd (%rax){1to8}, %ymm17, %ymm19
+vpdpbusd %ymm16, %ymm17, %ymm19 {k1}
+vpdpbusd (%rax), %ymm17, %ymm19 {k1}
+vpdpbusd (%rax){1to8}, %ymm17, %ymm19 {k1}
+vpdpbusd %ymm16, %ymm17, %ymm19 {z}{k1}
+vpdpbusd (%rax), %ymm17, %ymm19 {z}{k1}
+vpdpbusd (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
+
+vpdpbusds %xmm16, %xmm17, %xmm19
+vpdpbusds (%rax), %xmm17, %xmm19
+vpdpbusds (%rax){1to4}, %xmm17, %xmm19
+vpdpbusds %xmm16, %xmm17, %xmm19 {k1}
+vpdpbusds (%rax), %xmm17, %xmm19 {k1}
+vpdpbusds (%rax){1to4}, %xmm17, %xmm19 {k1}
+vpdpbusds %xmm16, %xmm17, %xmm19 {z}{k1}
+vpdpbusds (%rax), %xmm17, %xmm19 {z}{k1}
+vpdpbusds (%rax){1to4}, %xmm17, %xmm19 {z}{k1}
+
+vpdpbusds %ymm16, %ymm17, %ymm19
+vpdpbusds (%rax), %ymm17, %ymm19
+vpdpbusds (%rax){1to8}, %ymm17, %ymm19
+vpdpbusds %ymm16, %ymm17, %ymm19 {k1}
+vpdpbusds (%rax), %ymm17, %ymm19 {k1}
+vpdpbusds (%rax){1to8}, %ymm17, %ymm19 {k1}
+vpdpbusds %ymm16, %ymm17, %ymm19 {z}{k1}
+vpdpbusds (%rax), %ymm17, %ymm19 {z}{k1}
+vpdpbusds (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
+
+vpdpwssd %xmm16, %xmm17, %xmm19
+vpdpwssd (%rax), %xmm17, %xmm19
+vpdpwssd (%rax){1to4}, %xmm17, %xmm19
+vpdpwssd %xmm16, %xmm17, %xmm19 {k1}
+vpdpwssd (%rax), %xmm17, %xmm19 {k1}
+vpdpwssd (%rax){1to4}, %xmm17, %xmm19 {k1}
+vpdpwssd %xmm16, %xmm17, %xmm19 {z}{k1}
+vpdpwssd (%rax), %xmm17, %xmm19 {z}{k1}
+vpdpwssd (%rax){1to4}, %xmm17, %xmm19 {z}{k1}
+
+vpdpwssd %ymm16, %ymm17, %ymm19
+vpdpwssd (%rax), %ymm17, %ymm19
+vpdpwssd (%rax){1to8}, %ymm17, %ymm19
+vpdpwssd %ymm16, %ymm17, %ymm19 {k1}
+vpdpwssd (%rax), %ymm17, %ymm19 {k1}
+vpdpwssd (%rax){1to8}, %ymm17, %ymm19 {k1}
+vpdpwssd %ymm16, %ymm17, %ymm19 {z}{k1}
+vpdpwssd (%rax), %ymm17, %ymm19 {z}{k1}
+vpdpwssd (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
+
+vpdpwssds %xmm16, %xmm17, %xmm19
+vpdpwssds (%rax), %xmm17, %xmm19
+vpdpwssds (%rax){1to4}, %xmm17, %xmm19
+vpdpwssds %xmm16, %xmm17, %xmm19 {k1}
+vpdpwssds (%rax), %xmm17, %xmm19 {k1}
+vpdpwssds (%rax){1to4}, %xmm17, %xmm19 {k1}
+vpdpwssds %xmm16, %xmm17, %xmm19 {z}{k1}
+vpdpwssds (%rax), %xmm17, %xmm19 {z}{k1}
+vpdpwssds (%rax){1to4}, %xmm17, %xmm19 {z}{k1}
+
+vpdpwssds %ymm16, %ymm17, %ymm19
+vpdpwssds (%rax), %ymm17, %ymm19
+vpdpwssds (%rax){1to8}, %ymm17, %ymm19
+vpdpwssds %ymm16, %ymm17, %ymm19 {k1}
+vpdpwssds (%rax), %ymm17, %ymm19 {k1}
+vpdpwssds (%rax){1to8}, %ymm17, %ymm19 {k1}
+vpdpwssds %ymm16, %ymm17, %ymm19 {z}{k1}
+vpdpwssds (%rax), %ymm17, %ymm19 {z}{k1}
+vpdpwssds (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 vpdpbusd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpdpbusd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpdpbusd (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: 1 4 0.50 vpdpbusd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vpdpbusd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpdpbusd (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpdpbusd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpdpbusd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpdpbusd (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpdpbusd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpdpbusd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpdpbusd (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 1 4 0.50 vpdpbusd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vpdpbusd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpdpbusd (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpdpbusd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpdpbusd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpdpbusd (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpdpbusds %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpdpbusds (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpdpbusds (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: 1 4 0.50 vpdpbusds %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vpdpbusds (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpdpbusds (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpdpbusds %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpdpbusds (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpdpbusds (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpdpbusds %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpdpbusds (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpdpbusds (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 1 4 0.50 vpdpbusds %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vpdpbusds (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpdpbusds (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpdpbusds %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpdpbusds (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpdpbusds (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpdpwssd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpdpwssd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpdpwssd (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: 1 4 0.50 vpdpwssd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vpdpwssd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpdpwssd (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpdpwssd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpdpwssd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpdpwssd (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpdpwssd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpdpwssd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpdpwssd (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 1 4 0.50 vpdpwssd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vpdpwssd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpdpwssd (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpdpwssd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpdpwssd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpdpwssd (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpdpwssds %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpdpwssds (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpdpwssds (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: 1 4 0.50 vpdpwssds %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vpdpwssds (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpdpwssds (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpdpwssds %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpdpwssds (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpdpwssds (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 1 3 0.50 vpdpwssds %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpdpwssds (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpdpwssds (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: 1 4 0.50 vpdpwssds %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 11 0.50 * vpdpwssds (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 10 0.50 * vpdpwssds (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 1 3 0.50 vpdpwssds %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpdpwssds (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 1 10 0.50 * vpdpwssds (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 16.00 16.00 16.00 - - - - - 36.00 - 36.00 - 12.00 12.00 12.00 12.00 16.00 16.00 16.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpdpbusd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusd (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpdpbusd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusd (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpdpbusd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusd (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpdpbusd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusd (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpdpbusd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusd (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpdpbusd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusd (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpdpbusds %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusds (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusds (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpdpbusds %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusds (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusds (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpdpbusds %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusds (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusds (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpdpbusds %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusds (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusds (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpdpbusds %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusds (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusds (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpdpbusds %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusds (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpbusds (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpdpwssd %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssd (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssd (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpdpwssd %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssd (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssd (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpdpwssd %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssd (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssd (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpdpwssd %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssd (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssd (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpdpwssd %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssd (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssd (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpdpwssd %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssd (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssd (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpdpwssds %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssds (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssds (%rax){1to4}, %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpdpwssds %xmm16, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssds (%rax), %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssds (%rax){1to4}, %xmm17, %xmm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpdpwssds %xmm16, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssds (%rax), %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssds (%rax){1to4}, %xmm17, %xmm19 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpdpwssds %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssds (%rax), %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssds (%rax){1to8}, %ymm17, %ymm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpdpwssds %ymm16, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssds (%rax), %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssds (%rax){1to8}, %ymm17, %ymm19 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpdpwssds %ymm16, %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssds (%rax), %ymm17, %ymm19 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpdpwssds (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vp2intersect.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vp2intersect.s
new file mode 100644
index 0000000000000..3230ae9d473c5
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vp2intersect.s
@@ -0,0 +1,53 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=tigerlake -instruction-tables < %s | FileCheck %s
+
+vp2intersectd %zmm16, %zmm19, %k0
+vp2intersectd (%rax), %zmm19, %k0
+vp2intersectd (%rax){1to16}, %zmm19, %k0
+
+vp2intersectq %zmm16, %zmm19, %k0
+vp2intersectq (%rax), %zmm19, %k0
+vp2intersectq (%rax){1to8}, %zmm19, %k0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 vp2intersectd %zmm16, %zmm19, %k0
+# CHECK-NEXT: 2 8 1.00 * vp2intersectd (%rax), %zmm19, %k0
+# CHECK-NEXT: 2 8 1.00 * vp2intersectd (%rax){1to16}, %zmm19, %k0
+# CHECK-NEXT: 1 1 1.00 vp2intersectq %zmm16, %zmm19, %k0
+# CHECK-NEXT: 2 8 1.00 * vp2intersectq (%rax), %zmm19, %k0
+# CHECK-NEXT: 2 8 1.00 * vp2intersectq (%rax){1to8}, %zmm19, %k0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ICXDivider
+# CHECK-NEXT: [1] - ICXFPDivider
+# CHECK-NEXT: [2] - ICXPort0
+# CHECK-NEXT: [3] - ICXPort1
+# CHECK-NEXT: [4] - ICXPort2
+# CHECK-NEXT: [5] - ICXPort3
+# CHECK-NEXT: [6] - ICXPort4
+# CHECK-NEXT: [7] - ICXPort5
+# CHECK-NEXT: [8] - ICXPort6
+# CHECK-NEXT: [9] - ICXPort7
+# CHECK-NEXT: [10] - ICXPort8
+# CHECK-NEXT: [11] - ICXPort9
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
+# CHECK-NEXT: - - 6.00 - 2.00 2.00 - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - - - - - vp2intersectd %zmm16, %zmm19, %k0
+# CHECK-NEXT: - - 1.00 - 0.50 0.50 - - - - - - vp2intersectd (%rax), %zmm19, %k0
+# CHECK-NEXT: - - 1.00 - 0.50 0.50 - - - - - - vp2intersectd (%rax){1to16}, %zmm19, %k0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - vp2intersectq %zmm16, %zmm19, %k0
+# CHECK-NEXT: - - 1.00 - 0.50 0.50 - - - - - - vp2intersectq (%rax), %zmm19, %k0
+# CHECK-NEXT: - - 1.00 - 0.50 0.50 - - - - - - vp2intersectq (%rax){1to8}, %zmm19, %k0
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vp2intersectvl.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vp2intersectvl.s
new file mode 100644
index 0000000000000..b7e81f560fb8a
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vp2intersectvl.s
@@ -0,0 +1,73 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=tigerlake -instruction-tables < %s | FileCheck %s
+
+vp2intersectd %xmm16, %xmm19, %k0
+vp2intersectd (%rax), %xmm19, %k0
+vp2intersectd (%rax){1to4}, %xmm19, %k0
+
+vp2intersectd %ymm16, %ymm19, %k0
+vp2intersectd (%rax), %ymm19, %k0
+vp2intersectd (%rax){1to8}, %ymm19, %k0
+
+vp2intersectq %xmm16, %xmm19, %k0
+vp2intersectq (%rax), %xmm19, %k0
+vp2intersectq (%rax){1to2}, %xmm19, %k0
+
+vp2intersectq %ymm16, %ymm19, %k0
+vp2intersectq (%rax), %ymm19, %k0
+vp2intersectq (%rax){1to4}, %ymm19, %k0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.50 vp2intersectd %xmm16, %xmm19, %k0
+# CHECK-NEXT: 2 7 0.50 * vp2intersectd (%rax), %xmm19, %k0
+# CHECK-NEXT: 2 7 0.50 * vp2intersectd (%rax){1to4}, %xmm19, %k0
+# CHECK-NEXT: 1 1 0.50 vp2intersectd %ymm16, %ymm19, %k0
+# CHECK-NEXT: 2 8 0.50 * vp2intersectd (%rax), %ymm19, %k0
+# CHECK-NEXT: 2 8 0.50 * vp2intersectd (%rax){1to8}, %ymm19, %k0
+# CHECK-NEXT: 1 1 0.50 vp2intersectq %xmm16, %xmm19, %k0
+# CHECK-NEXT: 2 7 0.50 * vp2intersectq (%rax), %xmm19, %k0
+# CHECK-NEXT: 2 7 0.50 * vp2intersectq (%rax){1to2}, %xmm19, %k0
+# CHECK-NEXT: 1 1 0.50 vp2intersectq %ymm16, %ymm19, %k0
+# CHECK-NEXT: 2 8 0.50 * vp2intersectq (%rax), %ymm19, %k0
+# CHECK-NEXT: 2 8 0.50 * vp2intersectq (%rax){1to4}, %ymm19, %k0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ICXDivider
+# CHECK-NEXT: [1] - ICXFPDivider
+# CHECK-NEXT: [2] - ICXPort0
+# CHECK-NEXT: [3] - ICXPort1
+# CHECK-NEXT: [4] - ICXPort2
+# CHECK-NEXT: [5] - ICXPort3
+# CHECK-NEXT: [6] - ICXPort4
+# CHECK-NEXT: [7] - ICXPort5
+# CHECK-NEXT: [8] - ICXPort6
+# CHECK-NEXT: [9] - ICXPort7
+# CHECK-NEXT: [10] - ICXPort8
+# CHECK-NEXT: [11] - ICXPort9
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
+# CHECK-NEXT: - - 6.00 6.00 4.00 4.00 - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] Instructions:
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - vp2intersectd %xmm16, %xmm19, %k0
+# CHECK-NEXT: - - 0.50 0.50 0.50 0.50 - - - - - - vp2intersectd (%rax), %xmm19, %k0
+# CHECK-NEXT: - - 0.50 0.50 0.50 0.50 - - - - - - vp2intersectd (%rax){1to4}, %xmm19, %k0
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - vp2intersectd %ymm16, %ymm19, %k0
+# CHECK-NEXT: - - 0.50 0.50 0.50 0.50 - - - - - - vp2intersectd (%rax), %ymm19, %k0
+# CHECK-NEXT: - - 0.50 0.50 0.50 0.50 - - - - - - vp2intersectd (%rax){1to8}, %ymm19, %k0
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - vp2intersectq %xmm16, %xmm19, %k0
+# CHECK-NEXT: - - 0.50 0.50 0.50 0.50 - - - - - - vp2intersectq (%rax), %xmm19, %k0
+# CHECK-NEXT: - - 0.50 0.50 0.50 0.50 - - - - - - vp2intersectq (%rax){1to2}, %xmm19, %k0
+# CHECK-NEXT: - - 0.50 0.50 - - - - - - - - vp2intersectq %ymm16, %ymm19, %k0
+# CHECK-NEXT: - - 0.50 0.50 0.50 0.50 - - - - - - vp2intersectq (%rax), %ymm19, %k0
+# CHECK-NEXT: - - 0.50 0.50 0.50 0.50 - - - - - - vp2intersectq (%rax){1to4}, %ymm19, %k0
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpclmulqdq.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpclmulqdq.s
new file mode 100644
index 0000000000000..df38ed8ed9033
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpclmulqdq.s
@@ -0,0 +1,51 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+vpclmulqdq $11, %zmm16, %zmm17, %zmm19
+vpclmulqdq $11, (%rax), %zmm17, %zmm19
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 vpclmulqdq $11, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 1 10 0.50 * vpclmulqdq $11, (%rax), %zmm17, %zmm19
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpclmulqdq $11, %zmm16, %zmm17, %zmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpclmulqdq $11, (%rax), %zmm17, %zmm19
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpclmulqdqvl.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpclmulqdqvl.s
new file mode 100644
index 0000000000000..469ef374dd14d
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpclmulqdqvl.s
@@ -0,0 +1,58 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+vpclmulqdq $11, %xmm16, %xmm17, %xmm19
+vpclmulqdq $11, (%rax), %xmm17, %xmm19
+
+vpclmulqdq $11, %ymm16, %ymm17, %ymm19
+vpclmulqdq $11, (%rax), %ymm17, %ymm19
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 vpclmulqdq $11, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 1 10 0.50 * vpclmulqdq $11, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: 1 3 0.50 vpclmulqdq $11, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 1 10 0.50 * vpclmulqdq $11, (%rax), %ymm17, %ymm19
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 0.67 0.67 0.67 - - - - - 2.00 - 2.00 - 0.50 0.50 0.50 0.50 0.67 0.67 0.67 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpclmulqdq $11, %xmm16, %xmm17, %xmm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpclmulqdq $11, (%rax), %xmm17, %xmm19
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpclmulqdq $11, %ymm16, %ymm17, %ymm19
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpclmulqdq $11, (%rax), %ymm17, %ymm19
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpopcntdq.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpopcntdq.s
new file mode 100644
index 0000000000000..7900e3d4af92e
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpopcntdq.s
@@ -0,0 +1,104 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+vpopcntd %zmm1, %zmm0
+vpopcntd (%rdi), %zmm0
+vpopcntd (%rdi){1to16}, %zmm0
+
+vpopcntd %zmm1, %zmm0 {%k1}
+vpopcntd (%rdi), %zmm0 {%k1}
+vpopcntd (%rdi){1to16}, %zmm0 {%k1}
+
+vpopcntd %zmm1, %zmm0 {%k1} {z}
+vpopcntd (%rdi), %zmm0 {%k1} {z}
+vpopcntd (%rdi){1to16}, %zmm0 {%k1} {z}
+
+vpopcntq %zmm1, %zmm0
+vpopcntq (%rdi), %zmm0
+vpopcntq (%rdi){1to8}, %zmm0
+
+vpopcntq %zmm1, %zmm0 {%k1}
+vpopcntq (%rdi), %zmm0 {%k1}
+vpopcntq (%rdi){1to8}, %zmm0 {%k1}
+
+vpopcntq %zmm1, %zmm0 {%k1} {z}
+vpopcntq (%rdi), %zmm0 {%k1} {z}
+vpopcntq (%rdi){1to8}, %zmm0 {%k1} {z}
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.50 vpopcntd %zmm1, %zmm0
+# CHECK-NEXT: 1 8 0.50 * vpopcntd (%rdi), %zmm0
+# CHECK-NEXT: 1 8 0.50 * vpopcntd (%rdi){1to16}, %zmm0
+# CHECK-NEXT: 1 1 0.50 vpopcntd %zmm1, %zmm0 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpopcntd (%rdi), %zmm0 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpopcntd (%rdi){1to16}, %zmm0 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpopcntd %zmm1, %zmm0 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpopcntd (%rdi), %zmm0 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpopcntd (%rdi){1to16}, %zmm0 {%k1} {z}
+# CHECK-NEXT: 1 1 0.50 vpopcntq %zmm1, %zmm0
+# CHECK-NEXT: 1 8 0.50 * vpopcntq (%rdi), %zmm0
+# CHECK-NEXT: 1 8 0.50 * vpopcntq (%rdi){1to8}, %zmm0
+# CHECK-NEXT: 1 1 0.50 vpopcntq %zmm1, %zmm0 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpopcntq (%rdi), %zmm0 {%k1}
+# CHECK-NEXT: 1 8 0.50 * vpopcntq (%rdi){1to8}, %zmm0 {%k1}
+# CHECK-NEXT: 1 1 0.50 vpopcntq %zmm1, %zmm0 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpopcntq (%rdi), %zmm0 {%k1} {z}
+# CHECK-NEXT: 1 8 0.50 * vpopcntq (%rdi){1to8}, %zmm0 {%k1} {z}
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 4.00 4.00 4.00 - - - - - 9.00 9.00 9.00 9.00 3.00 3.00 3.00 3.00 4.00 4.00 4.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpopcntd %zmm1, %zmm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntd (%rdi), %zmm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntd (%rdi){1to16}, %zmm0
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpopcntd %zmm1, %zmm0 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntd (%rdi), %zmm0 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntd (%rdi){1to16}, %zmm0 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpopcntd %zmm1, %zmm0 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntd (%rdi), %zmm0 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntd (%rdi){1to16}, %zmm0 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpopcntq %zmm1, %zmm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntq (%rdi), %zmm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntq (%rdi){1to8}, %zmm0
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpopcntq %zmm1, %zmm0 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntq (%rdi), %zmm0 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntq (%rdi){1to8}, %zmm0 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - vpopcntq %zmm1, %zmm0 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntq (%rdi), %zmm0 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntq (%rdi){1to8}, %zmm0 {%k1} {z}
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpopcntdqvl.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpopcntdqvl.s
new file mode 100644
index 0000000000000..aaa146ea5d952
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpopcntdqvl.s
@@ -0,0 +1,164 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+vpopcntd %xmm1, %xmm0
+vpopcntd (%rdi), %xmm0
+vpopcntd (%rdi){1to4}, %xmm0
+
+vpopcntd %xmm1, %xmm0 {%k1}
+vpopcntd (%rdi), %xmm0 {%k1}
+vpopcntd (%rdi){1to4}, %xmm0 {%k1}
+
+vpopcntd %xmm1, %xmm0 {%k1} {z}
+vpopcntd (%rdi), %xmm0 {%k1} {z}
+vpopcntd (%rdi){1to4}, %xmm0 {%k1} {z}
+
+vpopcntd %ymm1, %ymm0
+vpopcntd (%rdi), %ymm0
+vpopcntd (%rdi){1to8}, %ymm0
+
+vpopcntd %ymm1, %ymm0 {%k1}
+vpopcntd (%rdi), %ymm0 {%k1}
+vpopcntd (%rdi){1to8}, %ymm0 {%k1}
+
+vpopcntd %ymm1, %ymm0 {%k1} {z}
+vpopcntd (%rdi), %ymm0 {%k1} {z}
+vpopcntd (%rdi){1to8}, %ymm0 {%k1} {z}
+
+vpopcntq %xmm1, %xmm0
+vpopcntq (%rdi), %xmm0
+vpopcntq (%rdi){1to2}, %xmm0
+
+vpopcntq %xmm1, %xmm0 {%k1}
+vpopcntq (%rdi), %xmm0 {%k1}
+vpopcntq (%rdi){1to2}, %xmm0 {%k1}
+
+vpopcntq %xmm1, %xmm0 {%k1} {z}
+vpopcntq (%rdi), %xmm0 {%k1} {z}
+vpopcntq (%rdi){1to2}, %xmm0 {%k1} {z}
+
+vpopcntq %ymm1, %ymm0
+vpopcntq (%rdi), %ymm0
+vpopcntq (%rdi){1to4}, %ymm0
+
+vpopcntq %ymm1, %ymm0 {%k1}
+vpopcntq (%rdi), %ymm0 {%k1}
+vpopcntq (%rdi){1to4}, %ymm0 {%k1}
+
+vpopcntq %ymm1, %ymm0 {%k1} {z}
+vpopcntq (%rdi), %ymm0 {%k1} {z}
+vpopcntq (%rdi){1to4}, %ymm0 {%k1} {z}
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.25 vpopcntd %xmm1, %xmm0
+# CHECK-NEXT: 1 8 0.33 * vpopcntd (%rdi), %xmm0
+# CHECK-NEXT: 1 8 0.33 * vpopcntd (%rdi){1to4}, %xmm0
+# CHECK-NEXT: 1 1 0.25 vpopcntd %xmm1, %xmm0 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpopcntd (%rdi), %xmm0 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpopcntd (%rdi){1to4}, %xmm0 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpopcntd %xmm1, %xmm0 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpopcntd (%rdi), %xmm0 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpopcntd (%rdi){1to4}, %xmm0 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpopcntd %ymm1, %ymm0
+# CHECK-NEXT: 1 8 0.33 * vpopcntd (%rdi), %ymm0
+# CHECK-NEXT: 1 8 0.33 * vpopcntd (%rdi){1to8}, %ymm0
+# CHECK-NEXT: 1 1 0.25 vpopcntd %ymm1, %ymm0 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpopcntd (%rdi), %ymm0 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpopcntd (%rdi){1to8}, %ymm0 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpopcntd %ymm1, %ymm0 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpopcntd (%rdi), %ymm0 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpopcntd (%rdi){1to8}, %ymm0 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpopcntq %xmm1, %xmm0
+# CHECK-NEXT: 1 8 0.33 * vpopcntq (%rdi), %xmm0
+# CHECK-NEXT: 1 8 0.33 * vpopcntq (%rdi){1to2}, %xmm0
+# CHECK-NEXT: 1 1 0.25 vpopcntq %xmm1, %xmm0 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpopcntq (%rdi), %xmm0 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpopcntq (%rdi){1to2}, %xmm0 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpopcntq %xmm1, %xmm0 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpopcntq (%rdi), %xmm0 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpopcntq (%rdi){1to2}, %xmm0 {%k1} {z}
+# CHECK-NEXT: 1 1 0.25 vpopcntq %ymm1, %ymm0
+# CHECK-NEXT: 1 8 0.33 * vpopcntq (%rdi), %ymm0
+# CHECK-NEXT: 1 8 0.33 * vpopcntq (%rdi){1to4}, %ymm0
+# CHECK-NEXT: 1 1 0.25 vpopcntq %ymm1, %ymm0 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpopcntq (%rdi), %ymm0 {%k1}
+# CHECK-NEXT: 1 8 0.33 * vpopcntq (%rdi){1to4}, %ymm0 {%k1}
+# CHECK-NEXT: 1 1 0.25 vpopcntq %ymm1, %ymm0 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpopcntq (%rdi), %ymm0 {%k1} {z}
+# CHECK-NEXT: 1 8 0.33 * vpopcntq (%rdi){1to4}, %ymm0 {%k1} {z}
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 8.00 8.00 8.00 - - - - - 9.00 9.00 9.00 9.00 6.00 6.00 6.00 6.00 8.00 8.00 8.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpopcntd %xmm1, %xmm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntd (%rdi), %xmm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntd (%rdi){1to4}, %xmm0
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpopcntd %xmm1, %xmm0 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntd (%rdi), %xmm0 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntd (%rdi){1to4}, %xmm0 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpopcntd %xmm1, %xmm0 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntd (%rdi), %xmm0 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntd (%rdi){1to4}, %xmm0 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpopcntd %ymm1, %ymm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntd (%rdi), %ymm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntd (%rdi){1to8}, %ymm0
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpopcntd %ymm1, %ymm0 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntd (%rdi), %ymm0 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntd (%rdi){1to8}, %ymm0 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpopcntd %ymm1, %ymm0 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntd (%rdi), %ymm0 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntd (%rdi){1to8}, %ymm0 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpopcntq %xmm1, %xmm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntq (%rdi), %xmm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntq (%rdi){1to2}, %xmm0
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpopcntq %xmm1, %xmm0 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntq (%rdi), %xmm0 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntq (%rdi){1to2}, %xmm0 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpopcntq %xmm1, %xmm0 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntq (%rdi), %xmm0 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntq (%rdi){1to2}, %xmm0 {%k1} {z}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpopcntq %ymm1, %ymm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntq (%rdi), %ymm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntq (%rdi){1to4}, %ymm0
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpopcntq %ymm1, %ymm0 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntq (%rdi), %ymm0 {%k1}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntq (%rdi){1to4}, %ymm0 {%k1}
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - vpopcntq %ymm1, %ymm0 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntq (%rdi), %ymm0 {%k1} {z}
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpopcntq (%rdi){1to4}, %ymm0 {%k1} {z}
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avxgfni.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avxgfni.s
new file mode 100644
index 0000000000000..995659f21b7d8
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avxgfni.s
@@ -0,0 +1,86 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+vgf2p8affineinvqb $0, %xmm0, %xmm1, %xmm2
+vgf2p8affineinvqb $0, (%rax), %xmm1, %xmm2
+
+vgf2p8affineinvqb $0, %ymm0, %ymm1, %ymm2
+vgf2p8affineinvqb $0, (%rax), %ymm1, %ymm2
+
+vgf2p8affineqb $0, %xmm0, %xmm1, %xmm2
+vgf2p8affineqb $0, (%rax), %xmm1, %xmm2
+
+vgf2p8affineqb $0, %ymm0, %ymm1, %ymm2
+vgf2p8affineqb $0, (%rax), %ymm1, %ymm2
+
+vgf2p8mulb %xmm0, %xmm1, %xmm2
+vgf2p8mulb (%rax), %xmm1, %xmm2
+
+vgf2p8mulb %ymm0, %ymm1, %ymm2
+vgf2p8mulb (%rax), %ymm1, %ymm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 vgf2p8affineinvqb $0, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vgf2p8affineinvqb $0, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vgf2p8affineinvqb $0, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vgf2p8affineinvqb $0, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vgf2p8affineqb $0, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vgf2p8affineqb $0, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vgf2p8affineqb $0, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vgf2p8affineqb $0, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vgf2p8mulb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * vgf2p8mulb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vgf2p8mulb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * vgf2p8mulb (%rax), %ymm1, %ymm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 2.00 2.00 2.00 - - - - - 4.00 2.00 4.00 2.00 1.50 1.50 1.50 1.50 2.00 2.00 2.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vgf2p8affineinvqb $0, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineinvqb $0, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vgf2p8affineinvqb $0, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineinvqb $0, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vgf2p8affineqb $0, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineqb $0, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vgf2p8affineqb $0, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8affineqb $0, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vgf2p8mulb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8mulb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vgf2p8mulb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vgf2p8mulb (%rax), %ymm1, %ymm2
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avxvnni.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avxvnni.s
new file mode 100644
index 0000000000000..e18e84da8b886
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avxvnni.s
@@ -0,0 +1,100 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+{vex} vpdpbusd %xmm0, %xmm1, %xmm2
+{vex} vpdpbusd (%rax), %xmm1, %xmm2
+
+{vex} vpdpbusd %ymm0, %ymm1, %ymm2
+{vex} vpdpbusd (%rax), %ymm1, %ymm2
+
+{vex} vpdpbusds %xmm0, %xmm1, %xmm2
+{vex} vpdpbusds (%rax), %xmm1, %xmm2
+
+{vex} vpdpbusds %ymm0, %ymm1, %ymm2
+{vex} vpdpbusds (%rax), %ymm1, %ymm2
+
+{vex} vpdpwssd %xmm0, %xmm1, %xmm2
+{vex} vpdpwssd (%rax), %xmm1, %xmm2
+
+{vex} vpdpwssd %ymm0, %ymm1, %ymm2
+{vex} vpdpwssd (%rax), %ymm1, %ymm2
+
+{vex} vpdpwssds %xmm0, %xmm1, %xmm2
+{vex} vpdpwssds (%rax), %xmm1, %xmm2
+
+{vex} vpdpwssds %ymm0, %ymm1, %ymm2
+{vex} vpdpwssds (%rax), %ymm1, %ymm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 {vex} vpdpbusd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * {vex} vpdpbusd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 {vex} vpdpbusd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * {vex} vpdpbusd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 {vex} vpdpbusds %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * {vex} vpdpbusds (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 {vex} vpdpbusds %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * {vex} vpdpbusds (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 {vex} vpdpwssd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * {vex} vpdpwssd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 {vex} vpdpwssd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * {vex} vpdpwssd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 {vex} vpdpwssds %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 10 0.50 * {vex} vpdpwssds (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 {vex} vpdpwssds %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 10 0.50 * {vex} vpdpwssds (%rax), %ymm1, %ymm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 2.67 2.67 2.67 - - - - - 8.00 - 8.00 - 2.00 2.00 2.00 2.00 2.67 2.67 2.67 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - {vex} vpdpbusd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - {vex} vpdpbusd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - {vex} vpdpbusd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - {vex} vpdpbusd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - {vex} vpdpbusds %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - {vex} vpdpbusds (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - {vex} vpdpbusds %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - {vex} vpdpbusds (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - {vex} vpdpwssd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - {vex} vpdpwssd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - {vex} vpdpwssd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - {vex} vpdpwssd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - {vex} vpdpwssds %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - {vex} vpdpwssds (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - {vex} vpdpwssds %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - {vex} vpdpwssds (%rax), %ymm1, %ymm2
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-bmi1.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-bmi1.s
new file mode 100644
index 0000000000000..36ca3d688af2c
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-bmi1.s
@@ -0,0 +1,135 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+andn %eax, %ebx, %ecx
+andn (%rax), %ebx, %ecx
+
+andn %rax, %rbx, %rcx
+andn (%rax), %rbx, %rcx
+
+bextr %eax, %ebx, %ecx
+bextr %eax, (%rbx), %ecx
+
+bextr %rax, %rbx, %rcx
+bextr %rax, (%rbx), %rcx
+
+blsi %eax, %ecx
+blsi (%rax), %ecx
+
+blsi %rax, %rcx
+blsi (%rax), %rcx
+
+blsmsk %eax, %ecx
+blsmsk (%rax), %ecx
+
+blsmsk %rax, %rcx
+blsmsk (%rax), %rcx
+
+blsr %eax, %ecx
+blsr (%rax), %ecx
+
+blsr %rax, %rcx
+blsr (%rax), %rcx
+
+tzcnt %ax, %cx
+tzcnt (%rax), %cx
+
+tzcnt %eax, %ecx
+tzcnt (%rax), %ecx
+
+tzcnt %rax, %rcx
+tzcnt (%rax), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.25 andnl %eax, %ebx, %ecx
+# CHECK-NEXT: 1 5 0.33 * andnl (%rax), %ebx, %ecx
+# CHECK-NEXT: 1 1 0.25 andnq %rax, %rbx, %rcx
+# CHECK-NEXT: 1 5 0.33 * andnq (%rax), %rbx, %rcx
+# CHECK-NEXT: 1 1 0.25 bextrl %eax, %ebx, %ecx
+# CHECK-NEXT: 1 5 0.33 * bextrl %eax, (%rbx), %ecx
+# CHECK-NEXT: 1 1 0.25 bextrq %rax, %rbx, %rcx
+# CHECK-NEXT: 1 5 0.33 * bextrq %rax, (%rbx), %rcx
+# CHECK-NEXT: 3 2 0.50 blsil %eax, %ecx
+# CHECK-NEXT: 3 6 0.50 * blsil (%rax), %ecx
+# CHECK-NEXT: 3 2 0.50 blsiq %rax, %rcx
+# CHECK-NEXT: 3 6 0.50 * blsiq (%rax), %rcx
+# CHECK-NEXT: 3 2 0.50 blsmskl %eax, %ecx
+# CHECK-NEXT: 3 6 0.50 * blsmskl (%rax), %ecx
+# CHECK-NEXT: 3 2 0.50 blsmskq %rax, %rcx
+# CHECK-NEXT: 3 6 0.50 * blsmskq (%rax), %rcx
+# CHECK-NEXT: 3 2 0.50 blsrl %eax, %ecx
+# CHECK-NEXT: 3 6 0.50 * blsrl (%rax), %ecx
+# CHECK-NEXT: 3 2 0.50 blsrq %rax, %rcx
+# CHECK-NEXT: 3 6 0.50 * blsrq (%rax), %rcx
+# CHECK-NEXT: 2 2 0.50 tzcntw %ax, %cx
+# CHECK-NEXT: 2 6 0.50 * tzcntw (%rax), %cx
+# CHECK-NEXT: 2 2 0.50 tzcntl %eax, %ecx
+# CHECK-NEXT: 2 6 0.50 * tzcntl (%rax), %ecx
+# CHECK-NEXT: 2 2 0.50 tzcntq %rax, %rcx
+# CHECK-NEXT: 2 6 0.50 * tzcntq (%rax), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 4.33 4.33 4.33 11.00 11.00 11.00 11.00 - - - - - 3.25 3.25 3.25 3.25 4.33 4.33 4.33 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - andnl %eax, %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - andnl (%rax), %ebx, %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - andnq %rax, %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - andnq (%rax), %rbx, %rcx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - bextrl %eax, %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - bextrl %eax, (%rbx), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - bextrq %rax, %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - bextrq %rax, (%rbx), %rcx
+# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - - - blsil %eax, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - blsil (%rax), %ecx
+# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - - - blsiq %rax, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - blsiq (%rax), %rcx
+# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - - - blsmskl %eax, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - blsmskl (%rax), %ecx
+# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - - - blsmskq %rax, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - blsmskq (%rax), %rcx
+# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - - - blsrl %eax, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - blsrl (%rax), %ecx
+# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - - - blsrq %rax, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - blsrq (%rax), %rcx
+# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - - - tzcntw %ax, %cx
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - tzcntw (%rax), %cx
+# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - - - tzcntl %eax, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - tzcntl (%rax), %ecx
+# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - - - tzcntq %rax, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - tzcntq (%rax), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-bmi2.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-bmi2.s
new file mode 100644
index 0000000000000..6696c6c73fbcf
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-bmi2.s
@@ -0,0 +1,156 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+bzhi %eax, %ebx, %ecx
+bzhi %eax, (%rbx), %ecx
+
+bzhi %rax, %rbx, %rcx
+bzhi %rax, (%rbx), %rcx
+
+mulx %eax, %ebx, %ecx
+mulx (%rax), %ebx, %ecx
+
+mulx %rax, %rbx, %rcx
+mulx (%rax), %rbx, %rcx
+
+pdep %eax, %ebx, %ecx
+pdep (%rax), %ebx, %ecx
+
+pdep %rax, %rbx, %rcx
+pdep (%rax), %rbx, %rcx
+
+pext %eax, %ebx, %ecx
+pext (%rax), %ebx, %ecx
+
+pext %rax, %rbx, %rcx
+pext (%rax), %rbx, %rcx
+
+rorx $1, %eax, %ecx
+rorx $1, (%rax), %ecx
+
+rorx $1, %rax, %rcx
+rorx $1, (%rax), %rcx
+
+sarx %eax, %ebx, %ecx
+sarx %eax, (%rbx), %ecx
+
+sarx %rax, %rbx, %rcx
+sarx %rax, (%rbx), %rcx
+
+shlx %eax, %ebx, %ecx
+shlx %eax, (%rbx), %ecx
+
+shlx %rax, %rbx, %rcx
+shlx %rax, (%rbx), %rcx
+
+shrx %eax, %ebx, %ecx
+shrx %eax, (%rbx), %ecx
+
+shrx %rax, %rbx, %rcx
+shrx %rax, (%rbx), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.25 bzhil %eax, %ebx, %ecx
+# CHECK-NEXT: 1 5 0.33 * bzhil %eax, (%rbx), %ecx
+# CHECK-NEXT: 1 1 0.25 bzhiq %rax, %rbx, %rcx
+# CHECK-NEXT: 1 5 0.33 * bzhiq %rax, (%rbx), %rcx
+# CHECK-NEXT: 2 3 3.00 mulxl %eax, %ebx, %ecx
+# CHECK-NEXT: 2 7 3.00 * mulxl (%rax), %ebx, %ecx
+# CHECK-NEXT: 2 4 3.00 mulxq %rax, %rbx, %rcx
+# CHECK-NEXT: 2 8 3.00 * mulxq (%rax), %rbx, %rcx
+# CHECK-NEXT: 1 1 0.25 pdepl %eax, %ebx, %ecx
+# CHECK-NEXT: 1 5 0.33 * pdepl (%rax), %ebx, %ecx
+# CHECK-NEXT: 1 1 0.25 pdepq %rax, %rbx, %rcx
+# CHECK-NEXT: 1 5 0.33 * pdepq (%rax), %rbx, %rcx
+# CHECK-NEXT: 1 1 0.25 pextl %eax, %ebx, %ecx
+# CHECK-NEXT: 1 5 0.33 * pextl (%rax), %ebx, %ecx
+# CHECK-NEXT: 1 1 0.25 pextq %rax, %rbx, %rcx
+# CHECK-NEXT: 1 5 0.33 * pextq (%rax), %rbx, %rcx
+# CHECK-NEXT: 1 1 0.25 rorxl $1, %eax, %ecx
+# CHECK-NEXT: 1 5 0.33 * rorxl $1, (%rax), %ecx
+# CHECK-NEXT: 1 1 0.25 rorxq $1, %rax, %rcx
+# CHECK-NEXT: 1 5 0.33 * rorxq $1, (%rax), %rcx
+# CHECK-NEXT: 1 1 0.25 sarxl %eax, %ebx, %ecx
+# CHECK-NEXT: 1 5 0.33 * sarxl %eax, (%rbx), %ecx
+# CHECK-NEXT: 1 1 0.25 sarxq %rax, %rbx, %rcx
+# CHECK-NEXT: 1 5 0.33 * sarxq %rax, (%rbx), %rcx
+# CHECK-NEXT: 1 1 0.25 shlxl %eax, %ebx, %ecx
+# CHECK-NEXT: 1 5 0.33 * shlxl %eax, (%rbx), %ecx
+# CHECK-NEXT: 1 1 0.25 shlxq %rax, %rbx, %rcx
+# CHECK-NEXT: 1 5 0.33 * shlxq %rax, (%rbx), %rcx
+# CHECK-NEXT: 1 1 0.25 shrxl %eax, %ebx, %ecx
+# CHECK-NEXT: 1 5 0.33 * shrxl %eax, (%rbx), %ecx
+# CHECK-NEXT: 1 1 0.25 shrxq %rax, %rbx, %rcx
+# CHECK-NEXT: 1 5 0.33 * shrxq %rax, (%rbx), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 5.33 5.33 5.33 7.00 19.00 7.00 7.00 - - - - - 4.00 4.00 4.00 4.00 5.33 5.33 5.33 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - bzhil %eax, %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - bzhil %eax, (%rbx), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - bzhiq %rax, %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - bzhiq %rax, (%rbx), %rcx
+# CHECK-NEXT: - - - - 3.00 - - - - - - - - - - - - - - - - - - mulxl %eax, %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - 3.00 - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - mulxl (%rax), %ebx, %ecx
+# CHECK-NEXT: - - - - 3.00 - - - - - - - - - - - - - - - - - - mulxq %rax, %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - 3.00 - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - mulxq (%rax), %rbx, %rcx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - pdepl %eax, %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pdepl (%rax), %ebx, %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - pdepq %rax, %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pdepq (%rax), %rbx, %rcx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - pextl %eax, %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pextl (%rax), %ebx, %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - pextq %rax, %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pextq (%rax), %rbx, %rcx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rorxl $1, %eax, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - rorxl $1, (%rax), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rorxq $1, %rax, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - rorxq $1, (%rax), %rcx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sarxl %eax, %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - sarxl %eax, (%rbx), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sarxq %rax, %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - sarxq %rax, (%rbx), %rcx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - shlxl %eax, %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - shlxl %eax, (%rbx), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - shlxq %rax, %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - shlxq %rax, (%rbx), %rcx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - shrxl %eax, %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - shrxl %eax, (%rbx), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - shrxq %rax, %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - shrxq %rax, (%rbx), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-clflushopt.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-clflushopt.s
new file mode 100644
index 0000000000000..e76f8fee7d7f9
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-clflushopt.s
@@ -0,0 +1,48 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+clflushopt (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 5 0.33 * * U clflushopt (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - clflushopt (%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-clwb.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-clwb.s
new file mode 100644
index 0000000000000..dd065ff35f5b9
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-clwb.s
@@ -0,0 +1,48 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+clwb (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 5 0.33 * * U clwb (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - clwb (%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-cmov.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-cmov.s
new file mode 100644
index 0000000000000..37f30f3715f1f
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-cmov.s
@@ -0,0 +1,338 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+cmovow %si, %di
+cmovnow %si, %di
+cmovbw %si, %di
+cmovaew %si, %di
+cmovew %si, %di
+cmovnew %si, %di
+cmovbew %si, %di
+cmovaw %si, %di
+cmovsw %si, %di
+cmovnsw %si, %di
+cmovpw %si, %di
+cmovnpw %si, %di
+cmovlw %si, %di
+cmovgew %si, %di
+cmovlew %si, %di
+cmovgw %si, %di
+
+cmovow (%rax), %di
+cmovnow (%rax), %di
+cmovbw (%rax), %di
+cmovaew (%rax), %di
+cmovew (%rax), %di
+cmovnew (%rax), %di
+cmovbew (%rax), %di
+cmovaw (%rax), %di
+cmovsw (%rax), %di
+cmovnsw (%rax), %di
+cmovpw (%rax), %di
+cmovnpw (%rax), %di
+cmovlw (%rax), %di
+cmovgew (%rax), %di
+cmovlew (%rax), %di
+cmovgw (%rax), %di
+
+cmovol %esi, %edi
+cmovnol %esi, %edi
+cmovbl %esi, %edi
+cmovael %esi, %edi
+cmovel %esi, %edi
+cmovnel %esi, %edi
+cmovbel %esi, %edi
+cmoval %esi, %edi
+cmovsl %esi, %edi
+cmovnsl %esi, %edi
+cmovpl %esi, %edi
+cmovnpl %esi, %edi
+cmovll %esi, %edi
+cmovgel %esi, %edi
+cmovlel %esi, %edi
+cmovgl %esi, %edi
+
+cmovol (%rax), %edi
+cmovnol (%rax), %edi
+cmovbl (%rax), %edi
+cmovael (%rax), %edi
+cmovel (%rax), %edi
+cmovnel (%rax), %edi
+cmovbel (%rax), %edi
+cmoval (%rax), %edi
+cmovsl (%rax), %edi
+cmovnsl (%rax), %edi
+cmovpl (%rax), %edi
+cmovnpl (%rax), %edi
+cmovll (%rax), %edi
+cmovgel (%rax), %edi
+cmovlel (%rax), %edi
+cmovgl (%rax), %edi
+
+cmovoq %rsi, %rdi
+cmovnoq %rsi, %rdi
+cmovbq %rsi, %rdi
+cmovaeq %rsi, %rdi
+cmoveq %rsi, %rdi
+cmovneq %rsi, %rdi
+cmovbeq %rsi, %rdi
+cmovaq %rsi, %rdi
+cmovsq %rsi, %rdi
+cmovnsq %rsi, %rdi
+cmovpq %rsi, %rdi
+cmovnpq %rsi, %rdi
+cmovlq %rsi, %rdi
+cmovgeq %rsi, %rdi
+cmovleq %rsi, %rdi
+cmovgq %rsi, %rdi
+
+cmovoq (%rax), %rdi
+cmovnoq (%rax), %rdi
+cmovbq (%rax), %rdi
+cmovaeq (%rax), %rdi
+cmoveq (%rax), %rdi
+cmovneq (%rax), %rdi
+cmovbeq (%rax), %rdi
+cmovaq (%rax), %rdi
+cmovsq (%rax), %rdi
+cmovnsq (%rax), %rdi
+cmovpq (%rax), %rdi
+cmovnpq (%rax), %rdi
+cmovlq (%rax), %rdi
+cmovgeq (%rax), %rdi
+cmovleq (%rax), %rdi
+cmovgq (%rax), %rdi
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.25 cmovow %si, %di
+# CHECK-NEXT: 1 1 0.25 cmovnow %si, %di
+# CHECK-NEXT: 1 1 0.25 cmovbw %si, %di
+# CHECK-NEXT: 1 1 0.25 cmovaew %si, %di
+# CHECK-NEXT: 1 1 0.25 cmovew %si, %di
+# CHECK-NEXT: 1 1 0.25 cmovnew %si, %di
+# CHECK-NEXT: 1 1 0.25 cmovbew %si, %di
+# CHECK-NEXT: 1 1 0.25 cmovaw %si, %di
+# CHECK-NEXT: 1 1 0.25 cmovsw %si, %di
+# CHECK-NEXT: 1 1 0.25 cmovnsw %si, %di
+# CHECK-NEXT: 1 1 0.25 cmovpw %si, %di
+# CHECK-NEXT: 1 1 0.25 cmovnpw %si, %di
+# CHECK-NEXT: 1 1 0.25 cmovlw %si, %di
+# CHECK-NEXT: 1 1 0.25 cmovgew %si, %di
+# CHECK-NEXT: 1 1 0.25 cmovlew %si, %di
+# CHECK-NEXT: 1 1 0.25 cmovgw %si, %di
+# CHECK-NEXT: 1 5 0.33 * cmovow (%rax), %di
+# CHECK-NEXT: 1 5 0.33 * cmovnow (%rax), %di
+# CHECK-NEXT: 1 5 0.33 * cmovbw (%rax), %di
+# CHECK-NEXT: 1 5 0.33 * cmovaew (%rax), %di
+# CHECK-NEXT: 1 5 0.33 * cmovew (%rax), %di
+# CHECK-NEXT: 1 5 0.33 * cmovnew (%rax), %di
+# CHECK-NEXT: 1 5 0.33 * cmovbew (%rax), %di
+# CHECK-NEXT: 1 5 0.33 * cmovaw (%rax), %di
+# CHECK-NEXT: 1 5 0.33 * cmovsw (%rax), %di
+# CHECK-NEXT: 1 5 0.33 * cmovnsw (%rax), %di
+# CHECK-NEXT: 1 5 0.33 * cmovpw (%rax), %di
+# CHECK-NEXT: 1 5 0.33 * cmovnpw (%rax), %di
+# CHECK-NEXT: 1 5 0.33 * cmovlw (%rax), %di
+# CHECK-NEXT: 1 5 0.33 * cmovgew (%rax), %di
+# CHECK-NEXT: 1 5 0.33 * cmovlew (%rax), %di
+# CHECK-NEXT: 1 5 0.33 * cmovgw (%rax), %di
+# CHECK-NEXT: 1 1 0.25 cmovol %esi, %edi
+# CHECK-NEXT: 1 1 0.25 cmovnol %esi, %edi
+# CHECK-NEXT: 1 1 0.25 cmovbl %esi, %edi
+# CHECK-NEXT: 1 1 0.25 cmovael %esi, %edi
+# CHECK-NEXT: 1 1 0.25 cmovel %esi, %edi
+# CHECK-NEXT: 1 1 0.25 cmovnel %esi, %edi
+# CHECK-NEXT: 1 1 0.25 cmovbel %esi, %edi
+# CHECK-NEXT: 1 1 0.25 cmoval %esi, %edi
+# CHECK-NEXT: 1 1 0.25 cmovsl %esi, %edi
+# CHECK-NEXT: 1 1 0.25 cmovnsl %esi, %edi
+# CHECK-NEXT: 1 1 0.25 cmovpl %esi, %edi
+# CHECK-NEXT: 1 1 0.25 cmovnpl %esi, %edi
+# CHECK-NEXT: 1 1 0.25 cmovll %esi, %edi
+# CHECK-NEXT: 1 1 0.25 cmovgel %esi, %edi
+# CHECK-NEXT: 1 1 0.25 cmovlel %esi, %edi
+# CHECK-NEXT: 1 1 0.25 cmovgl %esi, %edi
+# CHECK-NEXT: 1 5 0.33 * cmovol (%rax), %edi
+# CHECK-NEXT: 1 5 0.33 * cmovnol (%rax), %edi
+# CHECK-NEXT: 1 5 0.33 * cmovbl (%rax), %edi
+# CHECK-NEXT: 1 5 0.33 * cmovael (%rax), %edi
+# CHECK-NEXT: 1 5 0.33 * cmovel (%rax), %edi
+# CHECK-NEXT: 1 5 0.33 * cmovnel (%rax), %edi
+# CHECK-NEXT: 1 5 0.33 * cmovbel (%rax), %edi
+# CHECK-NEXT: 1 5 0.33 * cmoval (%rax), %edi
+# CHECK-NEXT: 1 5 0.33 * cmovsl (%rax), %edi
+# CHECK-NEXT: 1 5 0.33 * cmovnsl (%rax), %edi
+# CHECK-NEXT: 1 5 0.33 * cmovpl (%rax), %edi
+# CHECK-NEXT: 1 5 0.33 * cmovnpl (%rax), %edi
+# CHECK-NEXT: 1 5 0.33 * cmovll (%rax), %edi
+# CHECK-NEXT: 1 5 0.33 * cmovgel (%rax), %edi
+# CHECK-NEXT: 1 5 0.33 * cmovlel (%rax), %edi
+# CHECK-NEXT: 1 5 0.33 * cmovgl (%rax), %edi
+# CHECK-NEXT: 1 1 0.25 cmovoq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.25 cmovnoq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.25 cmovbq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.25 cmovaeq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.25 cmoveq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.25 cmovneq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.25 cmovbeq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.25 cmovaq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.25 cmovsq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.25 cmovnsq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.25 cmovpq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.25 cmovnpq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.25 cmovlq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.25 cmovgeq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.25 cmovleq %rsi, %rdi
+# CHECK-NEXT: 1 1 0.25 cmovgq %rsi, %rdi
+# CHECK-NEXT: 1 5 0.33 * cmovoq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.33 * cmovnoq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.33 * cmovbq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.33 * cmovaeq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.33 * cmoveq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.33 * cmovneq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.33 * cmovbeq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.33 * cmovaq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.33 * cmovsq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.33 * cmovnsq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.33 * cmovpq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.33 * cmovnpq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.33 * cmovlq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.33 * cmovgeq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.33 * cmovleq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.33 * cmovgq (%rax), %rdi
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 16.00 16.00 16.00 24.00 24.00 24.00 24.00 - - - - - 12.00 12.00 12.00 12.00 16.00 16.00 16.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovow %si, %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovnow %si, %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovbw %si, %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovaew %si, %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovew %si, %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovnew %si, %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovbew %si, %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovaw %si, %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovsw %si, %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovnsw %si, %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovpw %si, %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovnpw %si, %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovlw %si, %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovgew %si, %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovlew %si, %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovgw %si, %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovow (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovnow (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovbw (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovaew (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovew (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovnew (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovbew (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovaw (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovsw (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovnsw (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovpw (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovnpw (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovlw (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovgew (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovlew (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovgw (%rax), %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovol %esi, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovnol %esi, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovbl %esi, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovael %esi, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovel %esi, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovnel %esi, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovbel %esi, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmoval %esi, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovsl %esi, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovnsl %esi, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovpl %esi, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovnpl %esi, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovll %esi, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovgel %esi, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovlel %esi, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovgl %esi, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovol (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovnol (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovbl (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovael (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovel (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovnel (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovbel (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmoval (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovsl (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovnsl (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovpl (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovnpl (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovll (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovgel (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovlel (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovgl (%rax), %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovoq %rsi, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovnoq %rsi, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovbq %rsi, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovaeq %rsi, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmoveq %rsi, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovneq %rsi, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovbeq %rsi, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovaq %rsi, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovsq %rsi, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovnsq %rsi, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovpq %rsi, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovnpq %rsi, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovlq %rsi, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovgeq %rsi, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovleq %rsi, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmovgq %rsi, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovoq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovnoq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovbq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovaeq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmoveq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovneq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovbeq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovaq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovsq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovnsq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovpq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovnpq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovlq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovgeq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovleq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmovgq (%rax), %rdi
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-cmpxchg.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-cmpxchg.s
new file mode 100644
index 0000000000000..d45d287c0c702
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-cmpxchg.s
@@ -0,0 +1,57 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+cmpxchg8b (%rax)
+cmpxchg16b (%rax)
+lock cmpxchg8b (%rax)
+lock cmpxchg16b (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 6 3 3.00 * * cmpxchg8b (%rax)
+# CHECK-NEXT: 6 3 3.00 * * cmpxchg16b (%rax)
+# CHECK-NEXT: 6 3 3.00 * * lock cmpxchg8b (%rax)
+# CHECK-NEXT: 6 3 3.00 * * lock cmpxchg16b (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: - - - 12.00 12.00 12.00 12.00 - - - - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - - - - - - cmpxchg8b (%rax)
+# CHECK-NEXT: - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - - - - - - cmpxchg16b (%rax)
+# CHECK-NEXT: - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - - - - - - lock cmpxchg8b (%rax)
+# CHECK-NEXT: - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - - - - - - lock cmpxchg16b (%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-f16c.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-f16c.s
new file mode 100644
index 0000000000000..b7b2d4aaa8403
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-f16c.s
@@ -0,0 +1,72 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+vcvtph2ps %xmm0, %xmm2
+vcvtph2ps (%rax), %xmm2
+
+vcvtph2ps %xmm0, %ymm2
+vcvtph2ps (%rax), %ymm2
+
+vcvtps2ph $0, %xmm0, %xmm2
+vcvtps2ph $0, %xmm0, (%rax)
+
+vcvtps2ph $0, %ymm0, %xmm2
+vcvtps2ph $0, %ymm0, (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 4 0.50 vcvtph2ps %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vcvtph2ps (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 vcvtph2ps %xmm0, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vcvtph2ps (%rax), %ymm2
+# CHECK-NEXT: 1 4 0.50 vcvtps2ph $0, %xmm0, %xmm2
+# CHECK-NEXT: 2 5 0.50 * vcvtps2ph $0, %xmm0, (%rax)
+# CHECK-NEXT: 1 4 0.50 vcvtps2ph $0, %ymm0, %xmm2
+# CHECK-NEXT: 2 5 0.50 * vcvtps2ph $0, %ymm0, (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 1.33 1.33 1.33 - - - - - - 4.00 - 4.00 1.00 1.00 1.00 1.00 0.67 0.67 0.67 0.50 0.50 0.50 0.50
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtph2ps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtph2ps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtph2ps %xmm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vcvtph2ps (%rax), %ymm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtps2ph $0, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vcvtps2ph $0, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vcvtps2ph $0, %ymm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 vcvtps2ph $0, %ymm0, (%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-fma.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-fma.s
new file mode 100644
index 0000000000000..eee4d6c7eb177
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-fma.s
@@ -0,0 +1,716 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+vfmadd132pd %xmm0, %xmm1, %xmm2
+vfmadd132pd (%rax), %xmm1, %xmm2
+
+vfmadd132pd %ymm0, %ymm1, %ymm2
+vfmadd132pd (%rax), %ymm1, %ymm2
+
+vfmadd213pd %xmm0, %xmm1, %xmm2
+vfmadd213pd (%rax), %xmm1, %xmm2
+
+vfmadd213pd %ymm0, %ymm1, %ymm2
+vfmadd213pd (%rax), %ymm1, %ymm2
+
+vfmadd231pd %xmm0, %xmm1, %xmm2
+vfmadd231pd (%rax), %xmm1, %xmm2
+
+vfmadd231pd %ymm0, %ymm1, %ymm2
+vfmadd231pd (%rax), %ymm1, %ymm2
+
+vfmadd132ps %xmm0, %xmm1, %xmm2
+vfmadd132ps (%rax), %xmm1, %xmm2
+
+vfmadd132ps %ymm0, %ymm1, %ymm2
+vfmadd132ps (%rax), %ymm1, %ymm2
+
+vfmadd213ps %xmm0, %xmm1, %xmm2
+vfmadd213ps (%rax), %xmm1, %xmm2
+
+vfmadd213ps %ymm0, %ymm1, %ymm2
+vfmadd213ps (%rax), %ymm1, %ymm2
+
+vfmadd231ps %xmm0, %xmm1, %xmm2
+vfmadd231ps (%rax), %xmm1, %xmm2
+
+vfmadd231ps %ymm0, %ymm1, %ymm2
+vfmadd231ps (%rax), %ymm1, %ymm2
+
+vfmadd132sd %xmm0, %xmm1, %xmm2
+vfmadd132sd (%rax), %xmm1, %xmm2
+
+vfmadd213sd %xmm0, %xmm1, %xmm2
+vfmadd213sd (%rax), %xmm1, %xmm2
+
+vfmadd231sd %xmm0, %xmm1, %xmm2
+vfmadd231sd (%rax), %xmm1, %xmm2
+
+vfmadd132ss %xmm0, %xmm1, %xmm2
+vfmadd132ss (%rax), %xmm1, %xmm2
+
+vfmadd213ss %xmm0, %xmm1, %xmm2
+vfmadd213ss (%rax), %xmm1, %xmm2
+
+vfmadd231ss %xmm0, %xmm1, %xmm2
+vfmadd231ss (%rax), %xmm1, %xmm2
+
+vfmaddsub132pd %xmm0, %xmm1, %xmm2
+vfmaddsub132pd (%rax), %xmm1, %xmm2
+
+vfmaddsub132pd %ymm0, %ymm1, %ymm2
+vfmaddsub132pd (%rax), %ymm1, %ymm2
+
+vfmaddsub213pd %xmm0, %xmm1, %xmm2
+vfmaddsub213pd (%rax), %xmm1, %xmm2
+
+vfmaddsub213pd %ymm0, %ymm1, %ymm2
+vfmaddsub213pd (%rax), %ymm1, %ymm2
+
+vfmaddsub231pd %xmm0, %xmm1, %xmm2
+vfmaddsub231pd (%rax), %xmm1, %xmm2
+
+vfmaddsub231pd %ymm0, %ymm1, %ymm2
+vfmaddsub231pd (%rax), %ymm1, %ymm2
+
+vfmaddsub132ps %xmm0, %xmm1, %xmm2
+vfmaddsub132ps (%rax), %xmm1, %xmm2
+
+vfmaddsub132ps %ymm0, %ymm1, %ymm2
+vfmaddsub132ps (%rax), %ymm1, %ymm2
+
+vfmaddsub213ps %xmm0, %xmm1, %xmm2
+vfmaddsub213ps (%rax), %xmm1, %xmm2
+
+vfmaddsub213ps %ymm0, %ymm1, %ymm2
+vfmaddsub213ps (%rax), %ymm1, %ymm2
+
+vfmaddsub231ps %xmm0, %xmm1, %xmm2
+vfmaddsub231ps (%rax), %xmm1, %xmm2
+
+vfmaddsub231ps %ymm0, %ymm1, %ymm2
+vfmaddsub231ps (%rax), %ymm1, %ymm2
+
+vfmsub132pd %xmm0, %xmm1, %xmm2
+vfmsub132pd (%rax), %xmm1, %xmm2
+
+vfmsub132pd %ymm0, %ymm1, %ymm2
+vfmsub132pd (%rax), %ymm1, %ymm2
+
+vfmsub213pd %xmm0, %xmm1, %xmm2
+vfmsub213pd (%rax), %xmm1, %xmm2
+
+vfmsub213pd %ymm0, %ymm1, %ymm2
+vfmsub213pd (%rax), %ymm1, %ymm2
+
+vfmsub231pd %xmm0, %xmm1, %xmm2
+vfmsub231pd (%rax), %xmm1, %xmm2
+
+vfmsub231pd %ymm0, %ymm1, %ymm2
+vfmsub231pd (%rax), %ymm1, %ymm2
+
+vfmsub132ps %xmm0, %xmm1, %xmm2
+vfmsub132ps (%rax), %xmm1, %xmm2
+
+vfmsub132ps %ymm0, %ymm1, %ymm2
+vfmsub132ps (%rax), %ymm1, %ymm2
+
+vfmsub213ps %xmm0, %xmm1, %xmm2
+vfmsub213ps (%rax), %xmm1, %xmm2
+
+vfmsub213ps %ymm0, %ymm1, %ymm2
+vfmsub213ps (%rax), %ymm1, %ymm2
+
+vfmsub231ps %xmm0, %xmm1, %xmm2
+vfmsub231ps (%rax), %xmm1, %xmm2
+
+vfmsub231ps %ymm0, %ymm1, %ymm2
+vfmsub231ps (%rax), %ymm1, %ymm2
+
+vfmsub132sd %xmm0, %xmm1, %xmm2
+vfmsub132sd (%rax), %xmm1, %xmm2
+
+vfmsub213sd %xmm0, %xmm1, %xmm2
+vfmsub213sd (%rax), %xmm1, %xmm2
+
+vfmsub231sd %xmm0, %xmm1, %xmm2
+vfmsub231sd (%rax), %xmm1, %xmm2
+
+vfmsub132ss %xmm0, %xmm1, %xmm2
+vfmsub132ss (%rax), %xmm1, %xmm2
+
+vfmsub213ss %xmm0, %xmm1, %xmm2
+vfmsub213ss (%rax), %xmm1, %xmm2
+
+vfmsub231ss %xmm0, %xmm1, %xmm2
+vfmsub231ss (%rax), %xmm1, %xmm2
+
+vfmsubadd132pd %xmm0, %xmm1, %xmm2
+vfmsubadd132pd (%rax), %xmm1, %xmm2
+
+vfmsubadd132pd %ymm0, %ymm1, %ymm2
+vfmsubadd132pd (%rax), %ymm1, %ymm2
+
+vfmsubadd213pd %xmm0, %xmm1, %xmm2
+vfmsubadd213pd (%rax), %xmm1, %xmm2
+
+vfmsubadd213pd %ymm0, %ymm1, %ymm2
+vfmsubadd213pd (%rax), %ymm1, %ymm2
+
+vfmsubadd231pd %xmm0, %xmm1, %xmm2
+vfmsubadd231pd (%rax), %xmm1, %xmm2
+
+vfmsubadd231pd %ymm0, %ymm1, %ymm2
+vfmsubadd231pd (%rax), %ymm1, %ymm2
+
+vfmsubadd132ps %xmm0, %xmm1, %xmm2
+vfmsubadd132ps (%rax), %xmm1, %xmm2
+
+vfmsubadd132ps %ymm0, %ymm1, %ymm2
+vfmsubadd132ps (%rax), %ymm1, %ymm2
+
+vfmsubadd213ps %xmm0, %xmm1, %xmm2
+vfmsubadd213ps (%rax), %xmm1, %xmm2
+
+vfmsubadd213ps %ymm0, %ymm1, %ymm2
+vfmsubadd213ps (%rax), %ymm1, %ymm2
+
+vfmsubadd231ps %xmm0, %xmm1, %xmm2
+vfmsubadd231ps (%rax), %xmm1, %xmm2
+
+vfmsubadd231ps %ymm0, %ymm1, %ymm2
+vfmsubadd231ps (%rax), %ymm1, %ymm2
+
+vfnmadd132pd %xmm0, %xmm1, %xmm2
+vfnmadd132pd (%rax), %xmm1, %xmm2
+
+vfnmadd132pd %ymm0, %ymm1, %ymm2
+vfnmadd132pd (%rax), %ymm1, %ymm2
+
+vfnmadd213pd %xmm0, %xmm1, %xmm2
+vfnmadd213pd (%rax), %xmm1, %xmm2
+
+vfnmadd213pd %ymm0, %ymm1, %ymm2
+vfnmadd213pd (%rax), %ymm1, %ymm2
+
+vfnmadd231pd %xmm0, %xmm1, %xmm2
+vfnmadd231pd (%rax), %xmm1, %xmm2
+
+vfnmadd231pd %ymm0, %ymm1, %ymm2
+vfnmadd231pd (%rax), %ymm1, %ymm2
+
+vfnmadd132ps %xmm0, %xmm1, %xmm2
+vfnmadd132ps (%rax), %xmm1, %xmm2
+
+vfnmadd132ps %ymm0, %ymm1, %ymm2
+vfnmadd132ps (%rax), %ymm1, %ymm2
+
+vfnmadd213ps %xmm0, %xmm1, %xmm2
+vfnmadd213ps (%rax), %xmm1, %xmm2
+
+vfnmadd213ps %ymm0, %ymm1, %ymm2
+vfnmadd213ps (%rax), %ymm1, %ymm2
+
+vfnmadd231ps %xmm0, %xmm1, %xmm2
+vfnmadd231ps (%rax), %xmm1, %xmm2
+
+vfnmadd231ps %ymm0, %ymm1, %ymm2
+vfnmadd231ps (%rax), %ymm1, %ymm2
+
+vfnmadd132sd %xmm0, %xmm1, %xmm2
+vfnmadd132sd (%rax), %xmm1, %xmm2
+
+vfnmadd213sd %xmm0, %xmm1, %xmm2
+vfnmadd213sd (%rax), %xmm1, %xmm2
+
+vfnmadd231sd %xmm0, %xmm1, %xmm2
+vfnmadd231sd (%rax), %xmm1, %xmm2
+
+vfnmadd132ss %xmm0, %xmm1, %xmm2
+vfnmadd132ss (%rax), %xmm1, %xmm2
+
+vfnmadd213ss %xmm0, %xmm1, %xmm2
+vfnmadd213ss (%rax), %xmm1, %xmm2
+
+vfnmadd231ss %xmm0, %xmm1, %xmm2
+vfnmadd231ss (%rax), %xmm1, %xmm2
+
+vfnmsub132pd %xmm0, %xmm1, %xmm2
+vfnmsub132pd (%rax), %xmm1, %xmm2
+
+vfnmsub132pd %ymm0, %ymm1, %ymm2
+vfnmsub132pd (%rax), %ymm1, %ymm2
+
+vfnmsub213pd %xmm0, %xmm1, %xmm2
+vfnmsub213pd (%rax), %xmm1, %xmm2
+
+vfnmsub213pd %ymm0, %ymm1, %ymm2
+vfnmsub213pd (%rax), %ymm1, %ymm2
+
+vfnmsub231pd %xmm0, %xmm1, %xmm2
+vfnmsub231pd (%rax), %xmm1, %xmm2
+
+vfnmsub231pd %ymm0, %ymm1, %ymm2
+vfnmsub231pd (%rax), %ymm1, %ymm2
+
+vfnmsub132ps %xmm0, %xmm1, %xmm2
+vfnmsub132ps (%rax), %xmm1, %xmm2
+
+vfnmsub132ps %ymm0, %ymm1, %ymm2
+vfnmsub132ps (%rax), %ymm1, %ymm2
+
+vfnmsub213ps %xmm0, %xmm1, %xmm2
+vfnmsub213ps (%rax), %xmm1, %xmm2
+
+vfnmsub213ps %ymm0, %ymm1, %ymm2
+vfnmsub213ps (%rax), %ymm1, %ymm2
+
+vfnmsub231ps %xmm0, %xmm1, %xmm2
+vfnmsub231ps (%rax), %xmm1, %xmm2
+
+vfnmsub231ps %ymm0, %ymm1, %ymm2
+vfnmsub231ps (%rax), %ymm1, %ymm2
+
+vfnmsub132sd %xmm0, %xmm1, %xmm2
+vfnmsub132sd (%rax), %xmm1, %xmm2
+
+vfnmsub213sd %xmm0, %xmm1, %xmm2
+vfnmsub213sd (%rax), %xmm1, %xmm2
+
+vfnmsub231sd %xmm0, %xmm1, %xmm2
+vfnmsub231sd (%rax), %xmm1, %xmm2
+
+vfnmsub132ss %xmm0, %xmm1, %xmm2
+vfnmsub132ss (%rax), %xmm1, %xmm2
+
+vfnmsub213ss %xmm0, %xmm1, %xmm2
+vfnmsub213ss (%rax), %xmm1, %xmm2
+
+vfnmsub231ss %xmm0, %xmm1, %xmm2
+vfnmsub231ss (%rax), %xmm1, %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 4 0.50 vfmadd132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmadd132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfmadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmadd213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmadd213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfmadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmadd231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmadd231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfmadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmadd132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmadd132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfmadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmadd213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmadd213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfmadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmadd231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmadd231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfmadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmadd132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmadd132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmadd213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmadd213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmadd231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmadd231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmadd132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmadd132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmadd213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmadd213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmadd231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmadd231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmaddsub132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmaddsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmaddsub132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfmaddsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmaddsub213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmaddsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmaddsub213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfmaddsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmaddsub231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmaddsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmaddsub231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfmaddsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmaddsub132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmaddsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmaddsub132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfmaddsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmaddsub213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmaddsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmaddsub213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfmaddsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmaddsub231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmaddsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmaddsub231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfmaddsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmsub132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsub132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfmsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmsub213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsub213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfmsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmsub231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsub231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfmsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmsub132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsub132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfmsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmsub213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsub213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfmsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmsub231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsub231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfmsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmsub132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmsub132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsub213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmsub213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsub231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmsub231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsub132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmsub132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsub213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmsub213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsub231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmsub231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsubadd132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmsubadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsubadd132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfmsubadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmsubadd213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmsubadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsubadd213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfmsubadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmsubadd231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmsubadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsubadd231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfmsubadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmsubadd132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmsubadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsubadd132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfmsubadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmsubadd213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmsubadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsubadd213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfmsubadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfmsubadd231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfmsubadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfmsubadd231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfmsubadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfnmadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfnmadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfnmadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfnmadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfnmadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfnmadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfnmadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfnmadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfnmadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfnmadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfnmadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfnmadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfnmadd132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfnmadd213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfnmadd231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfnmadd132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfnmadd213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmadd231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfnmadd231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfnmsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfnmsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfnmsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfnmsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfnmsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfnmsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfnmsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfnmsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfnmsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfnmsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfnmsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 1 11 0.50 * vfnmsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfnmsub132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfnmsub213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfnmsub231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfnmsub132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfnmsub213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 4 0.50 vfnmsub231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1 11 0.50 * vfnmsub231ss (%rax), %xmm1, %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 32.00 32.00 32.00 - - - - - 96.00 - 96.00 - 24.00 24.00 24.00 24.00 32.00 32.00 32.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmadd231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmadd231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmaddsub132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmaddsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmaddsub132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmaddsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmaddsub213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmaddsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmaddsub213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmaddsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmaddsub231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmaddsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmaddsub231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmaddsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmaddsub132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmaddsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmaddsub132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmaddsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmaddsub213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmaddsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmaddsub213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmaddsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmaddsub231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmaddsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmaddsub231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmaddsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmsub132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmsub132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmsub213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmsub213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmsub231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmsub231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmsub132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmsub132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmsub213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmsub213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmsub231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmsub231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmsub132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmsub132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmsub213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmsub213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmsub231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmsub231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmsub132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmsub132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmsub213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmsub213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmsub231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmsub231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmsubadd132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmsubadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmsubadd132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmsubadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmsubadd213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmsubadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmsubadd213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmsubadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmsubadd231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmsubadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmsubadd231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmsubadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmsubadd132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmsubadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmsubadd132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmsubadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmsubadd213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmsubadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmsubadd213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmsubadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmsubadd231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmsubadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfmsubadd231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfmsubadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmadd132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmadd132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmadd213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmadd213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmadd231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmadd231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmadd132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmadd132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmadd213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmadd213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmadd231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmadd231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmadd132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmadd132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmadd213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmadd213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmadd231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmadd231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmadd132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmadd132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmadd213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmadd213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmadd231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmadd231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmsub132pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmsub132pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmsub213pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmsub213pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmsub231pd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmsub231pd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmsub132ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmsub132ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmsub213ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmsub213ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmsub231ps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmsub231ps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmsub132sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmsub132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmsub213sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmsub213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmsub231sd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmsub231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmsub132ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmsub132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmsub213ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmsub213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vfnmsub231ss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vfnmsub231ss (%rax), %xmm1, %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-fsgsbase.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-fsgsbase.s
new file mode 100644
index 0000000000000..e711c8ce42597
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-fsgsbase.s
@@ -0,0 +1,72 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+rdfsbase %eax
+rdfsbase %rax
+
+rdgsbase %eax
+rdgsbase %rax
+
+wrfsbase %edi
+wrfsbase %rdi
+
+wrgsbase %edi
+wrgsbase %rdi
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 100 0.25 * * U rdfsbasel %eax
+# CHECK-NEXT: 1 100 0.25 * * U rdfsbaseq %rax
+# CHECK-NEXT: 1 100 0.25 * * U rdgsbasel %eax
+# CHECK-NEXT: 1 100 0.25 * * U rdgsbaseq %rax
+# CHECK-NEXT: 1 100 0.25 * * U wrfsbasel %edi
+# CHECK-NEXT: 1 100 0.25 * * U wrfsbaseq %rdi
+# CHECK-NEXT: 1 100 0.25 * * U wrgsbasel %edi
+# CHECK-NEXT: 1 100 0.25 * * U wrgsbaseq %rdi
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - rdfsbasel %eax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - rdfsbaseq %rax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - rdgsbasel %eax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - rdgsbaseq %rax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - wrfsbasel %edi
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - wrfsbaseq %rdi
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - wrgsbasel %edi
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - wrgsbaseq %rdi
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-gfni.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-gfni.s
new file mode 100644
index 0000000000000..bff9238601630
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-gfni.s
@@ -0,0 +1,65 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+gf2p8affineinvqb $0, %xmm0, %xmm1
+gf2p8affineinvqb $0, (%rax), %xmm1
+
+gf2p8affineqb $0, %xmm0, %xmm1
+gf2p8affineqb $0, (%rax), %xmm1
+
+gf2p8mulb %xmm0, %xmm1
+gf2p8mulb (%rax), %xmm1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 gf2p8affineinvqb $0, %xmm0, %xmm1
+# CHECK-NEXT: 1 10 0.50 * gf2p8affineinvqb $0, (%rax), %xmm1
+# CHECK-NEXT: 1 3 0.50 gf2p8affineqb $0, %xmm0, %xmm1
+# CHECK-NEXT: 1 10 0.50 * gf2p8affineqb $0, (%rax), %xmm1
+# CHECK-NEXT: 1 3 0.50 gf2p8mulb %xmm0, %xmm1
+# CHECK-NEXT: 1 10 0.50 * gf2p8mulb (%rax), %xmm1
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 1.00 1.00 1.00 - - - - - 2.00 1.00 2.00 1.00 0.75 0.75 0.75 0.75 1.00 1.00 1.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - gf2p8affineinvqb $0, %xmm0, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - gf2p8affineinvqb $0, (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - gf2p8affineqb $0, %xmm0, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - gf2p8affineqb $0, (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - gf2p8mulb %xmm0, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - gf2p8mulb (%rax), %xmm1
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-lea.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-lea.s
new file mode 100644
index 0000000000000..d996afee688c2
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-lea.s
@@ -0,0 +1,452 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+lea 0(), %cx
+lea 0(), %ecx
+lea 0(), %rcx
+lea (%eax), %cx
+lea (%eax), %ecx
+lea (%eax), %rcx
+lea (%rax), %cx
+lea (%rax), %ecx
+lea (%rax), %rcx
+lea (, %ebx), %cx
+lea (, %ebx), %ecx
+lea (, %ebx), %rcx
+lea (, %rbx), %cx
+lea (, %rbx), %ecx
+lea (, %rbx), %rcx
+lea (, %ebx, 1), %cx
+lea (, %ebx, 1), %ecx
+lea (, %ebx, 1), %rcx
+lea (, %rbx, 1), %cx
+lea (, %rbx, 1), %ecx
+lea (, %rbx, 1), %rcx
+lea (, %ebx, 2), %cx
+lea (, %ebx, 2), %ecx
+lea (, %ebx, 2), %rcx
+lea (, %rbx, 2), %cx
+lea (, %rbx, 2), %ecx
+lea (, %rbx, 2), %rcx
+lea (%eax, %ebx), %cx
+lea (%eax, %ebx), %ecx
+lea (%eax, %ebx), %rcx
+lea (%rax, %rbx), %cx
+lea (%rax, %rbx), %ecx
+lea (%rax, %rbx), %rcx
+lea (%eax, %ebx, 1), %cx
+lea (%eax, %ebx, 1), %ecx
+lea (%eax, %ebx, 1), %rcx
+lea (%rax, %rbx, 1), %cx
+lea (%rax, %rbx, 1), %ecx
+lea (%rax, %rbx, 1), %rcx
+lea (%eax, %ebx, 2), %cx
+lea (%eax, %ebx, 2), %ecx
+lea (%eax, %ebx, 2), %rcx
+lea (%rax, %rbx, 2), %cx
+lea (%rax, %rbx, 2), %ecx
+lea (%rax, %rbx, 2), %rcx
+
+lea -16(), %cx
+lea -16(), %ecx
+lea -16(), %rcx
+lea -16(%eax), %cx
+lea -16(%eax), %ecx
+lea -16(%eax), %rcx
+lea -16(%rax), %cx
+lea -16(%rax), %ecx
+lea -16(%rax), %rcx
+lea -16(, %ebx), %cx
+lea -16(, %ebx), %ecx
+lea -16(, %ebx), %rcx
+lea -16(, %rbx), %cx
+lea -16(, %rbx), %ecx
+lea -16(, %rbx), %rcx
+lea -16(, %ebx, 1), %cx
+lea -16(, %ebx, 1), %ecx
+lea -16(, %ebx, 1), %rcx
+lea -16(, %rbx, 1), %cx
+lea -16(, %rbx, 1), %ecx
+lea -16(, %rbx, 1), %rcx
+lea -16(, %ebx, 2), %cx
+lea -16(, %ebx, 2), %ecx
+lea -16(, %ebx, 2), %rcx
+lea -16(, %rbx, 2), %cx
+lea -16(, %rbx, 2), %ecx
+lea -16(, %rbx, 2), %rcx
+lea -16(%eax, %ebx), %cx
+lea -16(%eax, %ebx), %ecx
+lea -16(%eax, %ebx), %rcx
+lea -16(%rax, %rbx), %cx
+lea -16(%rax, %rbx), %ecx
+lea -16(%rax, %rbx), %rcx
+lea -16(%eax, %ebx, 1), %cx
+lea -16(%eax, %ebx, 1), %ecx
+lea -16(%eax, %ebx, 1), %rcx
+lea -16(%rax, %rbx, 1), %cx
+lea -16(%rax, %rbx, 1), %ecx
+lea -16(%rax, %rbx, 1), %rcx
+lea -16(%eax, %ebx, 2), %cx
+lea -16(%eax, %ebx, 2), %ecx
+lea -16(%eax, %ebx, 2), %rcx
+lea -16(%rax, %rbx, 2), %cx
+lea -16(%rax, %rbx, 2), %ecx
+lea -16(%rax, %rbx, 2), %rcx
+
+lea 1024(), %cx
+lea 1024(), %ecx
+lea 1024(), %rcx
+lea 1024(%eax), %cx
+lea 1024(%eax), %ecx
+lea 1024(%eax), %rcx
+lea 1024(%rax), %cx
+lea 1024(%rax), %ecx
+lea 1024(%rax), %rcx
+lea 1024(, %ebx), %cx
+lea 1024(, %ebx), %ecx
+lea 1024(, %ebx), %rcx
+lea 1024(, %rbx), %cx
+lea 1024(, %rbx), %ecx
+lea 1024(, %rbx), %rcx
+lea 1024(, %ebx, 1), %cx
+lea 1024(, %ebx, 1), %ecx
+lea 1024(, %ebx, 1), %rcx
+lea 1024(, %rbx, 1), %cx
+lea 1024(, %rbx, 1), %ecx
+lea 1024(, %rbx, 1), %rcx
+lea 1024(, %ebx, 2), %cx
+lea 1024(, %ebx, 2), %ecx
+lea 1024(, %ebx, 2), %rcx
+lea 1024(, %rbx, 2), %cx
+lea 1024(, %rbx, 2), %ecx
+lea 1024(, %rbx, 2), %rcx
+lea 1024(%eax, %ebx), %cx
+lea 1024(%eax, %ebx), %ecx
+lea 1024(%eax, %ebx), %rcx
+lea 1024(%rax, %rbx), %cx
+lea 1024(%rax, %rbx), %ecx
+lea 1024(%rax, %rbx), %rcx
+lea 1024(%eax, %ebx, 1), %cx
+lea 1024(%eax, %ebx, 1), %ecx
+lea 1024(%eax, %ebx, 1), %rcx
+lea 1024(%rax, %rbx, 1), %cx
+lea 1024(%rax, %rbx, 1), %ecx
+lea 1024(%rax, %rbx, 1), %rcx
+lea 1024(%eax, %ebx, 2), %cx
+lea 1024(%eax, %ebx, 2), %ecx
+lea 1024(%eax, %ebx, 2), %rcx
+lea 1024(%rax, %rbx, 2), %cx
+lea 1024(%rax, %rbx, 2), %ecx
+lea 1024(%rax, %rbx, 2), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.33 leaw 0, %cx
+# CHECK-NEXT: 1 1 0.33 leal 0, %ecx
+# CHECK-NEXT: 1 1 0.33 leaq 0, %rcx
+# CHECK-NEXT: 1 1 0.33 leaw (%eax), %cx
+# CHECK-NEXT: 1 1 0.33 leal (%eax), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq (%eax), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw (%rax), %cx
+# CHECK-NEXT: 1 1 0.33 leal (%rax), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq (%rax), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw (,%ebx), %cx
+# CHECK-NEXT: 1 1 0.33 leal (,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq (,%ebx), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw (,%rbx), %cx
+# CHECK-NEXT: 1 1 0.33 leal (,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq (,%rbx), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw (,%ebx), %cx
+# CHECK-NEXT: 1 1 0.33 leal (,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq (,%ebx), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw (,%rbx), %cx
+# CHECK-NEXT: 1 1 0.33 leal (,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq (,%rbx), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw (,%ebx,2), %cx
+# CHECK-NEXT: 2 2 0.25 leal (,%ebx,2), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq (,%ebx,2), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw (,%rbx,2), %cx
+# CHECK-NEXT: 2 2 0.25 leal (,%rbx,2), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq (,%rbx,2), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw (%eax,%ebx), %cx
+# CHECK-NEXT: 1 1 0.33 leal (%eax,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq (%eax,%ebx), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw (%rax,%rbx), %cx
+# CHECK-NEXT: 1 1 0.33 leal (%rax,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq (%rax,%rbx), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw (%eax,%ebx), %cx
+# CHECK-NEXT: 1 1 0.33 leal (%eax,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq (%eax,%ebx), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw (%rax,%rbx), %cx
+# CHECK-NEXT: 1 1 0.33 leal (%rax,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq (%rax,%rbx), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw (%eax,%ebx,2), %cx
+# CHECK-NEXT: 2 2 0.25 leal (%eax,%ebx,2), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq (%eax,%ebx,2), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw (%rax,%rbx,2), %cx
+# CHECK-NEXT: 2 2 0.25 leal (%rax,%rbx,2), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq (%rax,%rbx,2), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw -16, %cx
+# CHECK-NEXT: 1 1 0.33 leal -16, %ecx
+# CHECK-NEXT: 1 1 0.33 leaq -16, %rcx
+# CHECK-NEXT: 1 1 0.33 leaw -16(%eax), %cx
+# CHECK-NEXT: 1 1 0.33 leal -16(%eax), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq -16(%eax), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw -16(%rax), %cx
+# CHECK-NEXT: 1 1 0.33 leal -16(%rax), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq -16(%rax), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw -16(,%ebx), %cx
+# CHECK-NEXT: 1 1 0.33 leal -16(,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq -16(,%ebx), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw -16(,%rbx), %cx
+# CHECK-NEXT: 1 1 0.33 leal -16(,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq -16(,%rbx), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw -16(,%ebx), %cx
+# CHECK-NEXT: 1 1 0.33 leal -16(,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq -16(,%ebx), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw -16(,%rbx), %cx
+# CHECK-NEXT: 1 1 0.33 leal -16(,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq -16(,%rbx), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw -16(,%ebx,2), %cx
+# CHECK-NEXT: 2 2 0.25 leal -16(,%ebx,2), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq -16(,%ebx,2), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw -16(,%rbx,2), %cx
+# CHECK-NEXT: 2 2 0.25 leal -16(,%rbx,2), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq -16(,%rbx,2), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw -16(%eax,%ebx), %cx
+# CHECK-NEXT: 2 2 0.25 leal -16(%eax,%ebx), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq -16(%eax,%ebx), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw -16(%rax,%rbx), %cx
+# CHECK-NEXT: 2 2 0.25 leal -16(%rax,%rbx), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq -16(%rax,%rbx), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw -16(%eax,%ebx), %cx
+# CHECK-NEXT: 2 2 0.25 leal -16(%eax,%ebx), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq -16(%eax,%ebx), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw -16(%rax,%rbx), %cx
+# CHECK-NEXT: 2 2 0.25 leal -16(%rax,%rbx), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq -16(%rax,%rbx), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw -16(%eax,%ebx,2), %cx
+# CHECK-NEXT: 2 2 0.25 leal -16(%eax,%ebx,2), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq -16(%eax,%ebx,2), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw -16(%rax,%rbx,2), %cx
+# CHECK-NEXT: 2 2 0.25 leal -16(%rax,%rbx,2), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq -16(%rax,%rbx,2), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw 1024, %cx
+# CHECK-NEXT: 1 1 0.33 leal 1024, %ecx
+# CHECK-NEXT: 1 1 0.33 leaq 1024, %rcx
+# CHECK-NEXT: 1 1 0.33 leaw 1024(%eax), %cx
+# CHECK-NEXT: 1 1 0.33 leal 1024(%eax), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq 1024(%eax), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw 1024(%rax), %cx
+# CHECK-NEXT: 1 1 0.33 leal 1024(%rax), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq 1024(%rax), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw 1024(,%ebx), %cx
+# CHECK-NEXT: 1 1 0.33 leal 1024(,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq 1024(,%ebx), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw 1024(,%rbx), %cx
+# CHECK-NEXT: 1 1 0.33 leal 1024(,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq 1024(,%rbx), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw 1024(,%ebx), %cx
+# CHECK-NEXT: 1 1 0.33 leal 1024(,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq 1024(,%ebx), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw 1024(,%rbx), %cx
+# CHECK-NEXT: 1 1 0.33 leal 1024(,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.33 leaq 1024(,%rbx), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw 1024(,%ebx,2), %cx
+# CHECK-NEXT: 2 2 0.25 leal 1024(,%ebx,2), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq 1024(,%ebx,2), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw 1024(,%rbx,2), %cx
+# CHECK-NEXT: 2 2 0.25 leal 1024(,%rbx,2), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq 1024(,%rbx,2), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw 1024(%eax,%ebx), %cx
+# CHECK-NEXT: 2 2 0.25 leal 1024(%eax,%ebx), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq 1024(%eax,%ebx), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw 1024(%rax,%rbx), %cx
+# CHECK-NEXT: 2 2 0.25 leal 1024(%rax,%rbx), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq 1024(%rax,%rbx), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw 1024(%eax,%ebx), %cx
+# CHECK-NEXT: 2 2 0.25 leal 1024(%eax,%ebx), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq 1024(%eax,%ebx), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw 1024(%rax,%rbx), %cx
+# CHECK-NEXT: 2 2 0.25 leal 1024(%rax,%rbx), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq 1024(%rax,%rbx), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw 1024(%eax,%ebx,2), %cx
+# CHECK-NEXT: 2 2 0.25 leal 1024(%eax,%ebx,2), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq 1024(%eax,%ebx,2), %rcx
+# CHECK-NEXT: 1 1 0.33 leaw 1024(%rax,%rbx,2), %cx
+# CHECK-NEXT: 2 2 0.25 leal 1024(%rax,%rbx,2), %ecx
+# CHECK-NEXT: 2 2 0.25 leaq 1024(%rax,%rbx,2), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 31.67 31.67 31.67 10.00 10.00 10.00 10.00 - - - - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw 0, %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal 0, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq 0, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw (%eax), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal (%eax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq (%eax), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw (%rax), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal (%rax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq (%rax), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw (,%ebx), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal (,%ebx), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq (,%ebx), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw (,%rbx), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal (,%rbx), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq (,%rbx), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw (,%ebx), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal (,%ebx), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq (,%ebx), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw (,%rbx), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal (,%rbx), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq (,%rbx), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw (,%ebx,2), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal (,%ebx,2), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq (,%ebx,2), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw (,%rbx,2), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal (,%rbx,2), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq (,%rbx,2), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw (%eax,%ebx), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal (%eax,%ebx), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq (%eax,%ebx), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw (%rax,%rbx), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal (%rax,%rbx), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq (%rax,%rbx), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw (%eax,%ebx), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal (%eax,%ebx), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq (%eax,%ebx), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw (%rax,%rbx), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal (%rax,%rbx), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq (%rax,%rbx), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw (%eax,%ebx,2), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal (%eax,%ebx,2), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq (%eax,%ebx,2), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw (%rax,%rbx,2), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal (%rax,%rbx,2), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq (%rax,%rbx,2), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw -16, %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal -16, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq -16, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw -16(%eax), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal -16(%eax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq -16(%eax), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw -16(%rax), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal -16(%rax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq -16(%rax), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw -16(,%ebx), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal -16(,%ebx), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq -16(,%ebx), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw -16(,%rbx), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal -16(,%rbx), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq -16(,%rbx), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw -16(,%ebx), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal -16(,%ebx), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq -16(,%ebx), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw -16(,%rbx), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal -16(,%rbx), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq -16(,%rbx), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw -16(,%ebx,2), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal -16(,%ebx,2), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq -16(,%ebx,2), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw -16(,%rbx,2), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal -16(,%rbx,2), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq -16(,%rbx,2), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw -16(%eax,%ebx), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal -16(%eax,%ebx), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq -16(%eax,%ebx), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw -16(%rax,%rbx), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal -16(%rax,%rbx), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq -16(%rax,%rbx), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw -16(%eax,%ebx), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal -16(%eax,%ebx), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq -16(%eax,%ebx), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw -16(%rax,%rbx), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal -16(%rax,%rbx), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq -16(%rax,%rbx), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw -16(%eax,%ebx,2), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal -16(%eax,%ebx,2), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq -16(%eax,%ebx,2), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw -16(%rax,%rbx,2), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal -16(%rax,%rbx,2), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq -16(%rax,%rbx,2), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw 1024, %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal 1024, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq 1024, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw 1024(%eax), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal 1024(%eax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq 1024(%eax), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw 1024(%rax), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal 1024(%rax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq 1024(%rax), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw 1024(,%ebx), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal 1024(,%ebx), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq 1024(,%ebx), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw 1024(,%rbx), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal 1024(,%rbx), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq 1024(,%rbx), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw 1024(,%ebx), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal 1024(,%ebx), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq 1024(,%ebx), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw 1024(,%rbx), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leal 1024(,%rbx), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaq 1024(,%rbx), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw 1024(,%ebx,2), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal 1024(,%ebx,2), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq 1024(,%ebx,2), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw 1024(,%rbx,2), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal 1024(,%rbx,2), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq 1024(,%rbx,2), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw 1024(%eax,%ebx), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal 1024(%eax,%ebx), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq 1024(%eax,%ebx), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw 1024(%rax,%rbx), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal 1024(%rax,%rbx), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq 1024(%rax,%rbx), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw 1024(%eax,%ebx), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal 1024(%eax,%ebx), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq 1024(%eax,%ebx), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw 1024(%rax,%rbx), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal 1024(%rax,%rbx), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq 1024(%rax,%rbx), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw 1024(%eax,%ebx,2), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal 1024(%eax,%ebx,2), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq 1024(%eax,%ebx,2), %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - leaw 1024(%rax,%rbx,2), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leal 1024(%rax,%rbx,2), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leaq 1024(%rax,%rbx,2), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-lzcnt.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-lzcnt.s
new file mode 100644
index 0000000000000..acc58ea3c4a1e
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-lzcnt.s
@@ -0,0 +1,65 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+lzcntw %cx, %cx
+lzcntw (%rax), %cx
+
+lzcntl %eax, %ecx
+lzcntl (%rax), %ecx
+
+lzcntq %rax, %rcx
+lzcntq (%rax), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.25 lzcntw %cx, %cx
+# CHECK-NEXT: 1 5 0.33 * lzcntw (%rax), %cx
+# CHECK-NEXT: 1 1 0.25 lzcntl %eax, %ecx
+# CHECK-NEXT: 1 5 0.33 * lzcntl (%rax), %ecx
+# CHECK-NEXT: 1 1 0.25 lzcntq %rax, %rcx
+# CHECK-NEXT: 1 5 0.33 * lzcntq (%rax), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 1.00 1.00 1.00 1.50 1.50 1.50 1.50 - - - - - 0.75 0.75 0.75 0.75 1.00 1.00 1.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - lzcntw %cx, %cx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - lzcntw (%rax), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - lzcntl %eax, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - lzcntl (%rax), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - lzcntq %rax, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - lzcntq (%rax), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-mmx.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-mmx.s
new file mode 100644
index 0000000000000..e1e38b868bdf3
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-mmx.s
@@ -0,0 +1,408 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+emms
+
+movd %eax, %mm2
+movd (%rax), %mm2
+
+movd %mm0, %ecx
+movd %mm0, (%rax)
+
+movq %rax, %mm2
+movq (%rax), %mm2
+
+movq %mm0, %rcx
+movq %mm0, (%rax)
+
+packsswb %mm0, %mm2
+packsswb (%rax), %mm2
+
+packssdw %mm0, %mm2
+packssdw (%rax), %mm2
+
+packuswb %mm0, %mm2
+packuswb (%rax), %mm2
+
+paddb %mm0, %mm2
+paddb (%rax), %mm2
+
+paddd %mm0, %mm2
+paddd (%rax), %mm2
+
+paddsb %mm0, %mm2
+paddsb (%rax), %mm2
+
+paddsw %mm0, %mm2
+paddsw (%rax), %mm2
+
+paddusb %mm0, %mm2
+paddusb (%rax), %mm2
+
+paddusw %mm0, %mm2
+paddusw (%rax), %mm2
+
+paddw %mm0, %mm2
+paddw (%rax), %mm2
+
+pand %mm0, %mm2
+pand (%rax), %mm2
+
+pandn %mm0, %mm2
+pandn (%rax), %mm2
+
+pcmpeqb %mm0, %mm2
+pcmpeqb (%rax), %mm2
+
+pcmpeqd %mm0, %mm2
+pcmpeqd (%rax), %mm2
+
+pcmpeqw %mm0, %mm2
+pcmpeqw (%rax), %mm2
+
+pcmpgtb %mm0, %mm2
+pcmpgtb (%rax), %mm2
+
+pcmpgtd %mm0, %mm2
+pcmpgtd (%rax), %mm2
+
+pcmpgtw %mm0, %mm2
+pcmpgtw (%rax), %mm2
+
+pmaddwd %mm0, %mm2
+pmaddwd (%rax), %mm2
+
+pmulhw %mm0, %mm2
+pmulhw (%rax), %mm2
+
+pmullw %mm0, %mm2
+pmullw (%rax), %mm2
+
+por %mm0, %mm2
+por (%rax), %mm2
+
+pslld $1, %mm2
+pslld %mm0, %mm2
+pslld (%rax), %mm2
+
+psllq $1, %mm2
+psllq %mm0, %mm2
+psllq (%rax), %mm2
+
+psllw $1, %mm2
+psllw %mm0, %mm2
+psllw (%rax), %mm2
+
+psrad $1, %mm2
+psrad %mm0, %mm2
+psrad (%rax), %mm2
+
+psraw $1, %mm2
+psraw %mm0, %mm2
+psraw (%rax), %mm2
+
+psrld $1, %mm2
+psrld %mm0, %mm2
+psrld (%rax), %mm2
+
+psrlq $1, %mm2
+psrlq %mm0, %mm2
+psrlq (%rax), %mm2
+
+psrlw $1, %mm2
+psrlw %mm0, %mm2
+psrlw (%rax), %mm2
+
+psubb %mm0, %mm2
+psubb (%rax), %mm2
+
+psubd %mm0, %mm2
+psubd (%rax), %mm2
+
+psubsb %mm0, %mm2
+psubsb (%rax), %mm2
+
+psubsw %mm0, %mm2
+psubsw (%rax), %mm2
+
+psubusb %mm0, %mm2
+psubusb (%rax), %mm2
+
+psubusw %mm0, %mm2
+psubusw (%rax), %mm2
+
+psubw %mm0, %mm2
+psubw (%rax), %mm2
+
+punpckhbw %mm0, %mm2
+punpckhbw (%rax), %mm2
+
+punpckhdq %mm0, %mm2
+punpckhdq (%rax), %mm2
+
+punpckhwd %mm0, %mm2
+punpckhwd (%rax), %mm2
+
+punpcklbw %mm0, %mm2
+punpcklbw (%rax), %mm2
+
+punpckldq %mm0, %mm2
+punpckldq (%rax), %mm2
+
+punpcklwd %mm0, %mm2
+punpcklwd (%rax), %mm2
+
+pxor %mm0, %mm2
+pxor (%rax), %mm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 0 0.25 * * U emms
+# CHECK-NEXT: 2 1 1.00 movd %eax, %mm2
+# CHECK-NEXT: 1 8 0.33 * movd (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 movd %mm0, %ecx
+# CHECK-NEXT: 1 1 0.33 * U movd %mm0, (%rax)
+# CHECK-NEXT: 2 1 1.00 movq %rax, %mm2
+# CHECK-NEXT: 1 8 0.33 * movq (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 movq %mm0, %rcx
+# CHECK-NEXT: 1 1 0.33 * movq %mm0, (%rax)
+# CHECK-NEXT: 1 1 0.50 packsswb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * packsswb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 packssdw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * packssdw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 packuswb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * packuswb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 paddb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * paddb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 paddd %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * paddd (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 paddsb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * paddsb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 paddsw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * paddsw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 paddusb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * paddusb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 paddusw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * paddusw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 paddw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * paddw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pand %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * pand (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pandn %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * pandn (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pcmpeqb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * pcmpeqb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pcmpeqd %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * pcmpeqd (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pcmpeqw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * pcmpeqw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * pcmpgtb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtd %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * pcmpgtd (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * pcmpgtw (%rax), %mm2
+# CHECK-NEXT: 1 3 0.50 pmaddwd %mm0, %mm2
+# CHECK-NEXT: 1 10 0.50 * pmaddwd (%rax), %mm2
+# CHECK-NEXT: 1 3 0.50 pmulhw %mm0, %mm2
+# CHECK-NEXT: 1 10 0.50 * pmulhw (%rax), %mm2
+# CHECK-NEXT: 1 3 0.50 pmullw %mm0, %mm2
+# CHECK-NEXT: 1 10 0.50 * pmullw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 por %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * por (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 pslld $1, %mm2
+# CHECK-NEXT: 1 1 0.50 pslld %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pslld (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psllq $1, %mm2
+# CHECK-NEXT: 1 1 0.50 psllq %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psllq (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psllw $1, %mm2
+# CHECK-NEXT: 1 1 0.50 psllw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psllw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psrad $1, %mm2
+# CHECK-NEXT: 1 1 0.50 psrad %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psrad (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psraw $1, %mm2
+# CHECK-NEXT: 1 1 0.50 psraw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psraw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psrld $1, %mm2
+# CHECK-NEXT: 1 1 0.50 psrld %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psrld (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psrlq $1, %mm2
+# CHECK-NEXT: 1 1 0.50 psrlq %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psrlq (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 psrlw $1, %mm2
+# CHECK-NEXT: 1 1 0.50 psrlw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * psrlw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 psubb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * psubb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 psubd %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * psubd (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 psubsb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * psubsb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 psubsw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * psubsw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 psubusb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * psubusb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 psubusw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * psubusw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 psubw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * psubw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 punpckhbw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * punpckhbw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 punpckhdq %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * punpckhdq (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 punpckhwd %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * punpckhwd (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 punpcklbw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * punpcklbw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 punpckldq %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * punpckldq (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 punpcklwd %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * punpcklwd (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pxor %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * pxor (%rax), %mm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 16.00 16.00 16.00 - - - - - 29.00 25.00 29.00 25.00 12.00 12.00 12.00 12.00 15.33 15.33 15.33 0.50 0.50 0.50 0.50
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - emms
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - movd %eax, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - movd %mm0, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 movd %mm0, (%rax)
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - movq %rax, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movq (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - movq %mm0, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 movq %mm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - packsswb %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - packsswb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - packssdw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - packssdw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - packuswb %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - packuswb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - paddb %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - paddb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - paddd %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - paddd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - paddsb %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - paddsb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - paddsw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - paddsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - paddusb %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - paddusb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - paddusw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - paddusw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - paddw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - paddw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pand %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pand (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pandn %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pandn (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pcmpeqb %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pcmpeqb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pcmpeqd %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pcmpeqd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pcmpeqw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pcmpeqw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pcmpgtb %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pcmpgtb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pcmpgtd %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pcmpgtd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pcmpgtw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pcmpgtw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - pmaddwd %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmaddwd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - pmulhw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmulhw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - pmullw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmullw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - por %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - por (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - pslld $1, %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - pslld %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pslld (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - psllq $1, %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - psllq %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psllq (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - psllw $1, %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - psllw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psllw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - psrad $1, %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - psrad %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psrad (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - psraw $1, %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - psraw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psraw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - psrld $1, %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - psrld %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psrld (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - psrlq $1, %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - psrlq %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psrlq (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - psrlw $1, %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - psrlw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psrlw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - psubb %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psubb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - psubd %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psubd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - psubsb %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psubsb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - psubsw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psubsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - psubusb %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psubusb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - psubusw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psubusw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - psubw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psubw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - punpckhbw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - punpckhbw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - punpckhdq %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - punpckhdq (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - punpckhwd %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - punpckhwd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - punpcklbw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - punpcklbw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - punpckldq %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - punpckldq (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - punpcklwd %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - punpcklwd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pxor %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pxor (%rax), %mm2
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-movbe.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-movbe.s
new file mode 100644
index 0000000000000..e3ef3769b68e6
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-movbe.s
@@ -0,0 +1,65 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+movbe %cx, (%rax)
+movbe (%rax), %cx
+
+movbe %ecx, (%rax)
+movbe (%rax), %ecx
+
+movbe %rcx, (%rax)
+movbe (%rax), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.50 * movbew %cx, (%rax)
+# CHECK-NEXT: 1 5 0.33 * movbew (%rax), %cx
+# CHECK-NEXT: 1 1 0.50 * movbel %ecx, (%rax)
+# CHECK-NEXT: 1 5 0.33 * movbel (%rax), %ecx
+# CHECK-NEXT: 1 1 0.50 * movbeq %rcx, (%rax)
+# CHECK-NEXT: 1 5 0.33 * movbeq (%rax), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 2.00 2.00 2.00 0.75 0.75 0.75 0.75 - - - - - 2.25 2.25 2.25 2.25 1.00 1.00 1.00 1.50 1.50 1.50 1.50
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 movbew %cx, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movbew (%rax), %cx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 movbel %ecx, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movbel (%rax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 movbeq %rcx, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movbeq (%rax), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-mwaitx.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-mwaitx.s
new file mode 100644
index 0000000000000..0e0588cbe9df7
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-mwaitx.s
@@ -0,0 +1,51 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+monitorx
+mwaitx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 100 0.25 U monitorx
+# CHECK-NEXT: 1 100 0.25 U mwaitx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - monitorx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - mwaitx
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-pclmul.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-pclmul.s
new file mode 100644
index 0000000000000..821e9e29a2747
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-pclmul.s
@@ -0,0 +1,51 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+pclmulqdq $11, %xmm0, %xmm2
+pclmulqdq $11, (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 pclmulqdq $11, %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * pclmulqdq $11, (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - pclmulqdq $11, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pclmulqdq $11, (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-popcnt.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-popcnt.s
new file mode 100644
index 0000000000000..ef88fc50deb8a
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-popcnt.s
@@ -0,0 +1,65 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+popcntw %cx, %cx
+popcntw (%rax), %cx
+
+popcntl %eax, %ecx
+popcntl (%rax), %ecx
+
+popcntq %rax, %rcx
+popcntq (%rax), %rcx
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.25 popcntw %cx, %cx
+# CHECK-NEXT: 1 5 0.33 * popcntw (%rax), %cx
+# CHECK-NEXT: 1 1 0.25 popcntl %eax, %ecx
+# CHECK-NEXT: 1 5 0.33 * popcntl (%rax), %ecx
+# CHECK-NEXT: 1 1 0.25 popcntq %rax, %rcx
+# CHECK-NEXT: 1 5 0.33 * popcntq (%rax), %rcx
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 1.00 1.00 1.00 1.50 1.50 1.50 1.50 - - - - - 0.75 0.75 0.75 0.75 1.00 1.00 1.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - popcntw %cx, %cx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - popcntw (%rax), %cx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - popcntl %eax, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - popcntl (%rax), %ecx
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - popcntq %rax, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - popcntq (%rax), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-prefetchw.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-prefetchw.s
new file mode 100644
index 0000000000000..73f7f7c96ebb8
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-prefetchw.s
@@ -0,0 +1,51 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+prefetch (%rax)
+prefetchw (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 5 0.33 * * prefetch (%rax)
+# CHECK-NEXT: 1 5 0.33 * * prefetchw (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 0.67 0.67 0.67 - - - - - - - - - 0.50 0.50 0.50 0.50 0.67 0.67 0.67 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - prefetch (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - prefetchw (%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-rdrand.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-rdrand.s
new file mode 100644
index 0000000000000..e11150c4d504e
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-rdrand.s
@@ -0,0 +1,54 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+rdrand %ax
+rdrand %eax
+rdrand %rax
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 100 0.25 U rdrandw %ax
+# CHECK-NEXT: 1 100 0.25 U rdrandl %eax
+# CHECK-NEXT: 1 100 0.25 U rdrandq %rax
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - rdrandw %ax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - rdrandl %eax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - rdrandq %rax
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-rdseed.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-rdseed.s
new file mode 100644
index 0000000000000..ca5bdfd7ac250
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-rdseed.s
@@ -0,0 +1,54 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+rdseed %ax
+rdseed %eax
+rdseed %rax
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 100 0.25 U rdseedw %ax
+# CHECK-NEXT: 1 100 0.25 U rdseedl %eax
+# CHECK-NEXT: 1 100 0.25 U rdseedq %rax
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - rdseedw %ax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - rdseedl %eax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - rdseedq %rax
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-sha.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-sha.s
new file mode 100644
index 0000000000000..f23598bf6fe0a
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-sha.s
@@ -0,0 +1,93 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+sha1msg1 %xmm0, %xmm2
+sha1msg1 (%rax), %xmm2
+
+sha1msg2 %xmm0, %xmm2
+sha1msg2 (%rax), %xmm2
+
+sha1nexte %xmm0, %xmm2
+sha1nexte (%rax), %xmm2
+
+sha1rnds4 $3, %xmm0, %xmm2
+sha1rnds4 $3, (%rax), %xmm2
+
+sha256msg1 %xmm0, %xmm2
+sha256msg1 (%rax), %xmm2
+
+sha256msg2 %xmm0, %xmm2
+sha256msg2 (%rax), %xmm2
+
+sha256rnds2 %xmm0, %xmm2
+sha256rnds2 (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.50 sha1msg1 %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * sha1msg1 (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 sha1msg2 %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * sha1msg2 (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 sha1nexte %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * sha1nexte (%rax), %xmm2
+# CHECK-NEXT: 1 5 4.00 sha1rnds4 $3, %xmm0, %xmm2
+# CHECK-NEXT: 1 12 4.00 * sha1rnds4 $3, (%rax), %xmm2
+# CHECK-NEXT: 2 2 0.50 sha256msg1 %xmm0, %xmm2
+# CHECK-NEXT: 2 9 0.50 * sha256msg1 (%rax), %xmm2
+# CHECK-NEXT: 1 4 2.00 sha256msg2 %xmm0, %xmm2
+# CHECK-NEXT: 1 11 2.00 * sha256msg2 (%rax), %xmm2
+# CHECK-NEXT: 1 4 2.00 sha256rnds2 %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: 1 11 2.00 * sha256rnds2 %xmm0, (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 2.33 2.33 2.33 - - - - - 20.00 1.00 20.00 1.00 1.75 1.75 1.75 1.75 2.33 2.33 2.33 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - sha1msg1 %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - sha1msg1 (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - sha1msg2 %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - sha1msg2 (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - sha1nexte %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - sha1nexte (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - - sha1rnds4 $3, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 4.00 - 4.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - sha1rnds4 $3, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - sha256msg1 %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - sha256msg1 (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - sha256msg2 %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - sha256msg2 (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - sha256rnds2 %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - sha256rnds2 %xmm0, (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse1.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse1.s
new file mode 100644
index 0000000000000..e0fc977b27aa9
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse1.s
@@ -0,0 +1,476 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+addps %xmm0, %xmm2
+addps (%rax), %xmm2
+
+addss %xmm0, %xmm2
+addss (%rax), %xmm2
+
+andnps %xmm0, %xmm2
+andnps (%rax), %xmm2
+
+andps %xmm0, %xmm2
+andps (%rax), %xmm2
+
+cmpps $0, %xmm0, %xmm2
+cmpps $0, (%rax), %xmm2
+
+cmpss $0, %xmm0, %xmm2
+cmpss $0, (%rax), %xmm2
+
+comiss %xmm0, %xmm1
+comiss (%rax), %xmm1
+
+cvtpi2ps %mm0, %xmm2
+cvtpi2ps (%rax), %xmm2
+
+cvtps2pi %xmm0, %mm2
+cvtps2pi (%rax), %mm2
+
+cvtsi2ss %ecx, %xmm2
+cvtsi2ss %rcx, %xmm2
+cvtsi2ssl (%rax), %xmm2
+cvtsi2ssq (%rax), %xmm2
+
+cvtss2si %xmm0, %ecx
+cvtss2si %xmm0, %rcx
+cvtss2si (%rax), %ecx
+cvtss2si (%rax), %rcx
+
+cvttps2pi %xmm0, %mm2
+cvttps2pi (%rax), %mm2
+
+cvttss2si %xmm0, %ecx
+cvttss2si %xmm0, %rcx
+cvttss2si (%rax), %ecx
+cvttss2si (%rax), %rcx
+
+divps %xmm0, %xmm2
+divps (%rax), %xmm2
+
+divss %xmm0, %xmm2
+divss (%rax), %xmm2
+
+ldmxcsr (%rax)
+
+maskmovq %mm0, %mm1
+
+maxps %xmm0, %xmm2
+maxps (%rax), %xmm2
+
+maxss %xmm0, %xmm2
+maxss (%rax), %xmm2
+
+minps %xmm0, %xmm2
+minps (%rax), %xmm2
+
+minss %xmm0, %xmm2
+minss (%rax), %xmm2
+
+movaps %xmm0, %xmm2
+movaps %xmm0, (%rax)
+movaps (%rax), %xmm2
+
+movhlps %xmm0, %xmm2
+movlhps %xmm0, %xmm2
+
+movhps %xmm0, (%rax)
+movhps (%rax), %xmm2
+
+movlps %xmm0, (%rax)
+movlps (%rax), %xmm2
+
+movmskps %xmm0, %rcx
+
+movntps %xmm0, (%rax)
+movntq %mm0, (%rax)
+
+movss %xmm0, %xmm2
+movss %xmm0, (%rax)
+movss (%rax), %xmm2
+
+movups %xmm0, %xmm2
+movups %xmm0, (%rax)
+movups (%rax), %xmm2
+
+mulps %xmm0, %xmm2
+mulps (%rax), %xmm2
+
+mulss %xmm0, %xmm2
+mulss (%rax), %xmm2
+
+orps %xmm0, %xmm2
+orps (%rax), %xmm2
+
+pavgb %mm0, %mm2
+pavgb (%rax), %mm2
+
+pavgw %mm0, %mm2
+pavgw (%rax), %mm2
+
+pextrw $1, %mm0, %rcx
+
+pinsrw $1, %rax, %mm2
+pinsrw $1, (%rax), %mm2
+
+pmaxsw %mm0, %mm2
+pmaxsw (%rax), %mm2
+
+pmaxub %mm0, %mm2
+pmaxub (%rax), %mm2
+
+pminsw %mm0, %mm2
+pminsw (%rax), %mm2
+
+pminub %mm0, %mm2
+pminub (%rax), %mm2
+
+pmovmskb %mm0, %rcx
+
+pmulhuw %mm0, %mm2
+pmulhuw (%rax), %mm2
+
+prefetcht0 (%rax)
+prefetcht1 (%rax)
+prefetcht2 (%rax)
+prefetchnta (%rax)
+
+psadbw %mm0, %mm2
+psadbw (%rax), %mm2
+
+pshufw $1, %mm0, %mm2
+pshufw $1, (%rax), %mm2
+
+rcpps %xmm0, %xmm2
+rcpps (%rax), %xmm2
+
+rcpss %xmm0, %xmm2
+rcpss (%rax), %xmm2
+
+rsqrtps %xmm0, %xmm2
+rsqrtps (%rax), %xmm2
+
+rsqrtss %xmm0, %xmm2
+rsqrtss (%rax), %xmm2
+
+sfence
+
+shufps $1, %xmm0, %xmm2
+shufps $1, (%rax), %xmm2
+
+sqrtps %xmm0, %xmm2
+sqrtps (%rax), %xmm2
+
+sqrtss %xmm0, %xmm2
+sqrtss (%rax), %xmm2
+
+stmxcsr (%rax)
+
+subps %xmm0, %xmm2
+subps (%rax), %xmm2
+
+subss %xmm0, %xmm2
+subss (%rax), %xmm2
+
+ucomiss %xmm0, %xmm1
+ucomiss (%rax), %xmm1
+
+unpckhps %xmm0, %xmm2
+unpckhps (%rax), %xmm2
+
+unpcklps %xmm0, %xmm2
+unpcklps (%rax), %xmm2
+
+xorps %xmm0, %xmm2
+xorps (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 addps %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * addps (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 addss %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * addss (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 andnps %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * andnps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 andps %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * andps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 cmpeqps %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * cmpeqps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 cmpeqss %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * cmpeqss (%rax), %xmm2
+# CHECK-NEXT: 2 1 0.50 comiss %xmm0, %xmm1
+# CHECK-NEXT: 2 8 0.50 * comiss (%rax), %xmm1
+# CHECK-NEXT: 1 4 0.50 cvtpi2ps %mm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * cvtpi2ps (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 cvtps2pi %xmm0, %mm2
+# CHECK-NEXT: 1 11 0.50 * cvtps2pi (%rax), %mm2
+# CHECK-NEXT: 2 4 1.50 cvtsi2ss %ecx, %xmm2
+# CHECK-NEXT: 2 4 1.50 cvtsi2ss %rcx, %xmm2
+# CHECK-NEXT: 2 11 1.50 * cvtsi2ssl (%rax), %xmm2
+# CHECK-NEXT: 2 11 1.50 * cvtsi2ssq (%rax), %xmm2
+# CHECK-NEXT: 2 2 1.00 cvtss2si %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 cvtss2si %xmm0, %rcx
+# CHECK-NEXT: 2 9 1.00 * cvtss2si (%rax), %ecx
+# CHECK-NEXT: 2 9 1.00 * cvtss2si (%rax), %rcx
+# CHECK-NEXT: 1 4 0.50 cvttps2pi %xmm0, %mm2
+# CHECK-NEXT: 1 11 0.50 * cvttps2pi (%rax), %mm2
+# CHECK-NEXT: 2 2 1.00 cvttss2si %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 cvttss2si %xmm0, %rcx
+# CHECK-NEXT: 2 9 1.00 * cvttss2si (%rax), %ecx
+# CHECK-NEXT: 2 9 1.00 * cvttss2si (%rax), %rcx
+# CHECK-NEXT: 1 10 4.50 divps %xmm0, %xmm2
+# CHECK-NEXT: 1 17 4.50 * divps (%rax), %xmm2
+# CHECK-NEXT: 1 10 4.50 divss %xmm0, %xmm2
+# CHECK-NEXT: 1 17 4.50 * divss (%rax), %xmm2
+# CHECK-NEXT: 1 100 0.25 * * U ldmxcsr (%rax)
+# CHECK-NEXT: 1 1 0.50 * * U maskmovq %mm0, %mm1
+# CHECK-NEXT: 1 1 0.50 maxps %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * maxps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 maxss %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * maxss (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 minps %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * minps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 minss %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * minss (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 movaps %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * movaps %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.33 * movaps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 movhlps %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.50 movlhps %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * movhps %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * movhps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 * movlps %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * movlps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 movmskps %xmm0, %ecx
+# CHECK-NEXT: 1 2 1.00 * movntps %xmm0, (%rax)
+# CHECK-NEXT: 1 2 1.00 * * U movntq %mm0, (%rax)
+# CHECK-NEXT: 1 1 0.50 movss %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * movss %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.33 * movss (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 movups %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * movups %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.33 * movups (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 mulps %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * mulps (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 mulss %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * mulss (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 orps %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * orps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pavgb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * pavgb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pavgw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * pavgw (%rax), %mm2
+# CHECK-NEXT: 1 1 2.00 pextrw $1, %mm0, %ecx
+# CHECK-NEXT: 1 2 0.50 pinsrw $1, %eax, %mm2
+# CHECK-NEXT: 1 9 0.50 * pinsrw $1, (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pmaxsw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * pmaxsw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pmaxub %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * pmaxub (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pminsw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * pminsw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pminub %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * pminub (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 pmovmskb %mm0, %ecx
+# CHECK-NEXT: 1 3 0.50 pmulhuw %mm0, %mm2
+# CHECK-NEXT: 1 10 0.50 * pmulhuw (%rax), %mm2
+# CHECK-NEXT: 1 5 0.33 * * prefetcht0 (%rax)
+# CHECK-NEXT: 1 5 0.33 * * prefetcht1 (%rax)
+# CHECK-NEXT: 1 5 0.33 * * prefetcht2 (%rax)
+# CHECK-NEXT: 1 5 0.33 * * prefetchnta (%rax)
+# CHECK-NEXT: 1 3 1.00 psadbw %mm0, %mm2
+# CHECK-NEXT: 1 10 1.00 * psadbw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 pshufw $1, %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pshufw $1, (%rax), %mm2
+# CHECK-NEXT: 1 5 1.00 rcpps %xmm0, %xmm2
+# CHECK-NEXT: 1 12 1.00 * rcpps (%rax), %xmm2
+# CHECK-NEXT: 1 5 1.00 rcpss %xmm0, %xmm2
+# CHECK-NEXT: 1 12 1.00 * rcpss (%rax), %xmm2
+# CHECK-NEXT: 1 5 1.00 rsqrtps %xmm0, %xmm2
+# CHECK-NEXT: 1 12 1.00 * rsqrtps (%rax), %xmm2
+# CHECK-NEXT: 1 5 1.00 rsqrtss %xmm0, %xmm2
+# CHECK-NEXT: 1 12 1.00 * rsqrtss (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 * * U sfence
+# CHECK-NEXT: 1 1 0.50 shufps $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * shufps $1, (%rax), %xmm2
+# CHECK-NEXT: 1 8 6.50 sqrtps %xmm0, %xmm2
+# CHECK-NEXT: 1 15 6.50 * sqrtps (%rax), %xmm2
+# CHECK-NEXT: 1 8 6.50 sqrtss %xmm0, %xmm2
+# CHECK-NEXT: 1 15 6.50 * sqrtss (%rax), %xmm2
+# CHECK-NEXT: 1 100 0.25 * U stmxcsr (%rax)
+# CHECK-NEXT: 1 3 0.50 subps %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * subps (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 subss %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * subss (%rax), %xmm2
+# CHECK-NEXT: 2 1 0.50 ucomiss %xmm0, %xmm1
+# CHECK-NEXT: 2 8 0.50 * ucomiss (%rax), %xmm1
+# CHECK-NEXT: 1 1 0.50 unpckhps %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * unpckhps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 unpcklps %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * unpcklps (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 xorps %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * xorps (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 21.67 21.67 21.67 - - - - - 28.00 83.00 28.00 81.00 16.00 16.00 16.00 16.00 19.00 19.00 19.00 1.75 1.75 1.75 1.75
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - addps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - addps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - addss %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - addss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - andnps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - andnps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - andps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - andps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - cmpeqps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmpeqps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - cmpeqss %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmpeqss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - comiss %xmm0, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - comiss (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - cvtpi2ps %mm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cvtpi2ps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - cvtps2pi %xmm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cvtps2pi (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 1.50 - 1.50 - - - - - - - - - - - cvtsi2ss %ecx, %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.50 - 1.50 - - - - - - - - - - - cvtsi2ss %rcx, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.50 - 1.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cvtsi2ssl (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.50 - 1.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cvtsi2ssq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - cvtss2si %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - cvtss2si %xmm0, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cvtss2si (%rax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cvtss2si (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - cvttps2pi %xmm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cvttps2pi (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - cvttss2si %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - cvttss2si %xmm0, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cvttss2si (%rax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cvttss2si (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - - 4.50 - 4.50 - - - - - - - - - - - divps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.50 - 4.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - divps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 4.50 - 4.50 - - - - - - - - - - - divss %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.50 - 4.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - divss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - ldmxcsr (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - maskmovq %mm0, %mm1
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - maxps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - maxps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - maxss %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - maxss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - minps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - minps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - minss %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - minss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - movaps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 movaps %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movaps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - movhlps %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - movlhps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 movhps %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movhps (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 movlps %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movlps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - movmskps %xmm0, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 movntps %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 movntq %mm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - movss %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 movss %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - movups %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 movups %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movups (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - mulps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - mulps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - mulss %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - mulss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - orps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - orps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pavgb %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pavgb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pavgw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pavgw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - pextrw $1, %mm0, %ecx
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - pinsrw $1, %eax, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pinsrw $1, (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pmaxsw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmaxsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pmaxub %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmaxub (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pminsw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pminsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pminub %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pminub (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - pmovmskb %mm0, %ecx
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - pmulhuw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmulhuw (%rax), %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - prefetcht0 (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - prefetcht1 (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - prefetcht2 (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - prefetchnta (%rax)
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - psadbw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psadbw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - pshufw $1, %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pshufw $1, (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - rcpps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - rcpps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - rcpss %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - rcpss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - rsqrtps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - rsqrtps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - rsqrtss %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - rsqrtss (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - sfence
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - shufps $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - shufps $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 6.50 - 6.50 - - - - - - - - - - - sqrtps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.50 - 6.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - sqrtps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 6.50 - 6.50 - - - - - - - - - - - sqrtss %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.50 - 6.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - sqrtss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - stmxcsr (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - subps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - subps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - subss %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - subss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - ucomiss %xmm0, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - ucomiss (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - unpckhps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - unpckhps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - unpcklps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - unpcklps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - xorps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - xorps (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse2.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse2.s
new file mode 100644
index 0000000000000..63eda51da975b
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse2.s
@@ -0,0 +1,975 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+addpd %xmm0, %xmm2
+addpd (%rax), %xmm2
+
+addsd %xmm0, %xmm2
+addsd (%rax), %xmm2
+
+andnpd %xmm0, %xmm2
+andnpd (%rax), %xmm2
+
+andpd %xmm0, %xmm2
+andpd (%rax), %xmm2
+
+clflush (%rax)
+
+cmppd $0, %xmm0, %xmm2
+cmppd $0, (%rax), %xmm2
+
+cmpsd $0, %xmm0, %xmm2
+cmpsd $0, (%rax), %xmm2
+
+comisd %xmm0, %xmm1
+comisd (%rax), %xmm1
+
+cvtdq2pd %xmm0, %xmm2
+cvtdq2pd (%rax), %xmm2
+
+cvtdq2ps %xmm0, %xmm2
+cvtdq2ps (%rax), %xmm2
+
+cvtpd2dq %xmm0, %xmm2
+cvtpd2dq (%rax), %xmm2
+
+cvtpd2pi %xmm0, %mm2
+cvtpd2pi (%rax), %mm2
+
+cvtpd2ps %xmm0, %xmm2
+cvtpd2ps (%rax), %xmm2
+
+cvtpi2pd %mm0, %xmm2
+cvtpi2pd (%rax), %xmm2
+
+cvtps2dq %xmm0, %xmm2
+cvtps2dq (%rax), %xmm2
+
+cvtps2pd %xmm0, %xmm2
+cvtps2pd (%rax), %xmm2
+
+cvtsd2si %xmm0, %ecx
+cvtsd2si %xmm0, %rcx
+cvtsd2si (%rax), %ecx
+cvtsd2si (%rax), %rcx
+
+cvtsd2ss %xmm0, %xmm2
+cvtsd2ss (%rax), %xmm2
+
+cvtsi2sd %ecx, %xmm2
+cvtsi2sd %rcx, %xmm2
+cvtsi2sdl (%rax), %xmm2
+cvtsi2sdq (%rax), %xmm2
+
+cvtss2sd %xmm0, %xmm2
+cvtss2sd (%rax), %xmm2
+
+cvttpd2dq %xmm0, %xmm2
+cvttpd2dq (%rax), %xmm2
+
+cvttpd2pi %xmm0, %mm2
+cvttpd2pi (%rax), %mm2
+
+cvttps2dq %xmm0, %xmm2
+cvttps2dq (%rax), %xmm2
+
+cvttsd2si %xmm0, %ecx
+cvttsd2si %xmm0, %rcx
+cvttsd2si (%rax), %ecx
+cvttsd2si (%rax), %rcx
+
+divpd %xmm0, %xmm2
+divpd (%rax), %xmm2
+
+divsd %xmm0, %xmm2
+divsd (%rax), %xmm2
+
+lfence
+
+maskmovdqu %xmm0, %xmm1
+
+maxpd %xmm0, %xmm2
+maxpd (%rax), %xmm2
+
+maxsd %xmm0, %xmm2
+maxsd (%rax), %xmm2
+
+mfence
+
+minpd %xmm0, %xmm2
+minpd (%rax), %xmm2
+
+minsd %xmm0, %xmm2
+minsd (%rax), %xmm2
+
+movapd %xmm0, %xmm2
+movapd %xmm0, (%rax)
+movapd (%rax), %xmm2
+
+movd %eax, %xmm2
+movd (%rax), %xmm2
+
+movd %xmm0, %ecx
+movd %xmm0, (%rax)
+
+movdqa %xmm0, %xmm2
+movdqa %xmm0, (%rax)
+movdqa (%rax), %xmm2
+
+movdqu %xmm0, %xmm2
+movdqu %xmm0, (%rax)
+movdqu (%rax), %xmm2
+
+movdq2q %xmm0, %mm2
+
+movhpd %xmm0, (%rax)
+movhpd (%rax), %xmm2
+
+movlpd %xmm0, (%rax)
+movlpd (%rax), %xmm2
+
+movmskpd %xmm0, %rcx
+
+movntil %eax, (%rax)
+movntiq %rax, (%rax)
+
+movntdq %xmm0, (%rax)
+movntpd %xmm0, (%rax)
+
+movq %xmm0, %xmm2
+
+movq %rax, %xmm2
+movq (%rax), %xmm2
+
+movq %xmm0, %rcx
+movq %xmm0, (%rax)
+
+movq2dq %mm0, %xmm2
+
+movsd %xmm0, %xmm2
+movsd %xmm0, (%rax)
+movsd (%rax), %xmm2
+
+movupd %xmm0, %xmm2
+movupd %xmm0, (%rax)
+movupd (%rax), %xmm2
+
+mulpd %xmm0, %xmm2
+mulpd (%rax), %xmm2
+
+mulsd %xmm0, %xmm2
+mulsd (%rax), %xmm2
+
+orpd %xmm0, %xmm2
+orpd (%rax), %xmm2
+
+packssdw %xmm0, %xmm2
+packssdw (%rax), %xmm2
+
+packsswb %xmm0, %xmm2
+packsswb (%rax), %xmm2
+
+packuswb %xmm0, %xmm2
+packuswb (%rax), %xmm2
+
+paddb %xmm0, %xmm2
+paddb (%rax), %xmm2
+
+paddd %xmm0, %xmm2
+paddd (%rax), %xmm2
+
+paddq %mm0, %mm2
+paddq (%rax), %mm2
+
+paddq %xmm0, %xmm2
+paddq (%rax), %xmm2
+
+paddsb %xmm0, %xmm2
+paddsb (%rax), %xmm2
+
+paddsw %xmm0, %xmm2
+paddsw (%rax), %xmm2
+
+paddusb %xmm0, %xmm2
+paddusb (%rax), %xmm2
+
+paddusw %xmm0, %xmm2
+paddusw (%rax), %xmm2
+
+paddw %xmm0, %xmm2
+paddw (%rax), %xmm2
+
+pand %xmm0, %xmm2
+pand (%rax), %xmm2
+
+pandn %xmm0, %xmm2
+pandn (%rax), %xmm2
+
+pavgb %xmm0, %xmm2
+pavgb (%rax), %xmm2
+
+pavgw %xmm0, %xmm2
+pavgw (%rax), %xmm2
+
+pcmpeqb %xmm0, %xmm2
+pcmpeqb (%rax), %xmm2
+
+pcmpeqd %xmm0, %xmm2
+pcmpeqd (%rax), %xmm2
+
+pcmpeqw %xmm0, %xmm2
+pcmpeqw (%rax), %xmm2
+
+pcmpgtb %xmm0, %xmm2
+pcmpgtb (%rax), %xmm2
+
+pcmpgtd %xmm0, %xmm2
+pcmpgtd (%rax), %xmm2
+
+pcmpgtw %xmm0, %xmm2
+pcmpgtw (%rax), %xmm2
+
+pextrw $1, %xmm0, %rcx
+
+pinsrw $1, %rax, %xmm0
+pinsrw $1, (%rax), %xmm0
+
+pmaddwd %xmm0, %xmm2
+pmaddwd (%rax), %xmm2
+
+pmaxsw %xmm0, %xmm2
+pmaxsw (%rax), %xmm2
+
+pmaxub %xmm0, %xmm2
+pmaxub (%rax), %xmm2
+
+pminsw %xmm0, %xmm2
+pminsw (%rax), %xmm2
+
+pminub %xmm0, %xmm2
+pminub (%rax), %xmm2
+
+pmovmskb %xmm0, %rcx
+
+pmulhuw %xmm0, %xmm2
+pmulhuw (%rax), %xmm2
+
+pmulhw %xmm0, %xmm2
+pmulhw (%rax), %xmm2
+
+pmullw %xmm0, %xmm2
+pmullw (%rax), %xmm2
+
+pmuludq %mm0, %mm2
+pmuludq (%rax), %mm2
+
+pmuludq %xmm0, %xmm2
+pmuludq (%rax), %xmm2
+
+por %xmm0, %xmm2
+por (%rax), %xmm2
+
+psadbw %xmm0, %xmm2
+psadbw (%rax), %xmm2
+
+pshufd $1, %xmm0, %xmm2
+pshufd $1, (%rax), %xmm2
+
+pshufhw $1, %xmm0, %xmm2
+pshufhw $1, (%rax), %xmm2
+
+pshuflw $1, %xmm0, %xmm2
+pshuflw $1, (%rax), %xmm2
+
+pslld $1, %xmm2
+pslld %xmm0, %xmm2
+pslld (%rax), %xmm2
+
+pslldq $1, %xmm2
+
+psllq $1, %xmm2
+psllq %xmm0, %xmm2
+psllq (%rax), %xmm2
+
+psllw $1, %xmm2
+psllw %xmm0, %xmm2
+psllw (%rax), %xmm2
+
+psrad $1, %xmm2
+psrad %xmm0, %xmm2
+psrad (%rax), %xmm2
+
+psraw $1, %xmm2
+psraw %xmm0, %xmm2
+psraw (%rax), %xmm2
+
+psrld $1, %xmm2
+psrld %xmm0, %xmm2
+psrld (%rax), %xmm2
+
+psrldq $1, %xmm2
+
+psrlq $1, %xmm2
+psrlq %xmm0, %xmm2
+psrlq (%rax), %xmm2
+
+psrlw $1, %xmm2
+psrlw %xmm0, %xmm2
+psrlw (%rax), %xmm2
+
+psubb %xmm0, %xmm2
+psubb (%rax), %xmm2
+
+psubd %xmm0, %xmm2
+psubd (%rax), %xmm2
+
+psubq %mm0, %mm2
+psubq (%rax), %mm2
+
+psubq %xmm0, %xmm2
+psubq (%rax), %xmm2
+
+psubsb %xmm0, %xmm2
+psubsb (%rax), %xmm2
+
+psubsw %xmm0, %xmm2
+psubsw (%rax), %xmm2
+
+psubusb %xmm0, %xmm2
+psubusb (%rax), %xmm2
+
+psubusw %xmm0, %xmm2
+psubusw (%rax), %xmm2
+
+psubw %xmm0, %xmm2
+psubw (%rax), %xmm2
+
+punpckhbw %xmm0, %xmm2
+punpckhbw (%rax), %xmm2
+
+punpckhdq %xmm0, %xmm2
+punpckhdq (%rax), %xmm2
+
+punpckhqdq %xmm0, %xmm2
+punpckhqdq (%rax), %xmm2
+
+punpckhwd %xmm0, %xmm2
+punpckhwd (%rax), %xmm2
+
+punpcklbw %xmm0, %xmm2
+punpcklbw (%rax), %xmm2
+
+punpckldq %xmm0, %xmm2
+punpckldq (%rax), %xmm2
+
+punpcklqdq %xmm0, %xmm2
+punpcklqdq (%rax), %xmm2
+
+punpcklwd %xmm0, %xmm2
+punpcklwd (%rax), %xmm2
+
+pxor %xmm0, %xmm2
+pxor (%rax), %xmm2
+
+shufpd $1, %xmm0, %xmm2
+shufpd $1, (%rax), %xmm2
+
+sqrtpd %xmm0, %xmm2
+sqrtpd (%rax), %xmm2
+
+sqrtsd %xmm0, %xmm2
+sqrtsd (%rax), %xmm2
+
+subpd %xmm0, %xmm2
+subpd (%rax), %xmm2
+
+subsd %xmm0, %xmm2
+subsd (%rax), %xmm2
+
+ucomisd %xmm0, %xmm1
+ucomisd (%rax), %xmm1
+
+unpckhpd %xmm0, %xmm2
+unpckhpd (%rax), %xmm2
+
+unpcklpd %xmm0, %xmm2
+unpcklpd (%rax), %xmm2
+
+xorpd %xmm0, %xmm2
+xorpd (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 addpd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * addpd (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 addsd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * addsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 andnpd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * andnpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 andpd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * andpd (%rax), %xmm2
+# CHECK-NEXT: 1 5 0.33 * * U clflush (%rax)
+# CHECK-NEXT: 1 1 0.50 cmpeqpd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * cmpeqpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 cmpeqsd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * cmpeqsd (%rax), %xmm2
+# CHECK-NEXT: 2 1 0.50 comisd %xmm0, %xmm1
+# CHECK-NEXT: 2 8 0.50 * comisd (%rax), %xmm1
+# CHECK-NEXT: 1 4 0.50 cvtdq2pd %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * cvtdq2pd (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 cvtdq2ps %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * cvtdq2ps (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 cvtpd2dq %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * cvtpd2dq (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 cvtpd2pi %xmm0, %mm2
+# CHECK-NEXT: 1 11 0.50 * cvtpd2pi (%rax), %mm2
+# CHECK-NEXT: 1 4 0.50 cvtpd2ps %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * cvtpd2ps (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 cvtpi2pd %mm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * cvtpi2pd (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 cvtps2dq %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * cvtps2dq (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 cvtps2pd %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * cvtps2pd (%rax), %xmm2
+# CHECK-NEXT: 2 2 1.00 cvtsd2si %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 cvtsd2si %xmm0, %rcx
+# CHECK-NEXT: 2 9 1.00 * cvtsd2si (%rax), %ecx
+# CHECK-NEXT: 2 9 1.00 * cvtsd2si (%rax), %rcx
+# CHECK-NEXT: 1 4 0.50 cvtsd2ss %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * cvtsd2ss (%rax), %xmm2
+# CHECK-NEXT: 2 4 1.50 cvtsi2sd %ecx, %xmm2
+# CHECK-NEXT: 2 4 1.50 cvtsi2sd %rcx, %xmm2
+# CHECK-NEXT: 2 11 1.50 * cvtsi2sdl (%rax), %xmm2
+# CHECK-NEXT: 2 11 1.50 * cvtsi2sdq (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 cvtss2sd %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * cvtss2sd (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 cvttpd2dq %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * cvttpd2dq (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 cvttpd2pi %xmm0, %mm2
+# CHECK-NEXT: 1 11 0.50 * cvttpd2pi (%rax), %mm2
+# CHECK-NEXT: 1 4 0.50 cvttps2dq %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * cvttps2dq (%rax), %xmm2
+# CHECK-NEXT: 2 2 1.00 cvttsd2si %xmm0, %ecx
+# CHECK-NEXT: 2 2 1.00 cvttsd2si %xmm0, %rcx
+# CHECK-NEXT: 2 9 1.00 * cvttsd2si (%rax), %ecx
+# CHECK-NEXT: 2 9 1.00 * cvttsd2si (%rax), %rcx
+# CHECK-NEXT: 1 8 6.00 divpd %xmm0, %xmm2
+# CHECK-NEXT: 1 15 6.00 * divpd (%rax), %xmm2
+# CHECK-NEXT: 1 8 6.00 divsd %xmm0, %xmm2
+# CHECK-NEXT: 1 15 6.00 * divsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 * * U lfence
+# CHECK-NEXT: 1 1 0.33 * * U maskmovdqu %xmm0, %xmm1
+# CHECK-NEXT: 1 1 0.50 maxpd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * maxpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 maxsd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * maxsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 * * U mfence
+# CHECK-NEXT: 1 1 0.50 minpd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * minpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 minsd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * minsd (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 movapd %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * movapd %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.33 * movapd (%rax), %xmm2
+# CHECK-NEXT: 2 1 1.00 movd %eax, %xmm2
+# CHECK-NEXT: 1 8 0.33 * movd (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 movd %xmm0, %ecx
+# CHECK-NEXT: 1 1 0.33 * movd %xmm0, (%rax)
+# CHECK-NEXT: 1 0 0.25 movdqa %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * movdqa %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.33 * movdqa (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 movdqu %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * movdqu %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.33 * movdqu (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 movdq2q %xmm0, %mm2
+# CHECK-NEXT: 1 1 0.33 * movhpd %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * movhpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.33 * movlpd %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.50 * movlpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 movmskpd %xmm0, %ecx
+# CHECK-NEXT: 1 1 0.50 * movntil %eax, (%rax)
+# CHECK-NEXT: 1 1 0.50 * movntiq %rax, (%rax)
+# CHECK-NEXT: 1 2 1.00 * movntdq %xmm0, (%rax)
+# CHECK-NEXT: 1 2 1.00 * movntpd %xmm0, (%rax)
+# CHECK-NEXT: 1 1 0.25 movq %xmm0, %xmm2
+# CHECK-NEXT: 2 1 1.00 movq %rax, %xmm2
+# CHECK-NEXT: 1 8 0.33 * movq (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 movq %xmm0, %rcx
+# CHECK-NEXT: 1 1 0.33 * movq %xmm0, (%rax)
+# CHECK-NEXT: 1 0 0.25 movq2dq %mm0, %xmm2
+# CHECK-NEXT: 1 1 0.50 movsd %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * movsd %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.33 * movsd (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.25 movupd %xmm0, %xmm2
+# CHECK-NEXT: 1 1 0.33 * movupd %xmm0, (%rax)
+# CHECK-NEXT: 1 8 0.33 * movupd (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 mulpd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * mulpd (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 mulsd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * mulsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 orpd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * orpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 packssdw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * packssdw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 packsswb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * packsswb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 packuswb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * packuswb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 paddb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * paddb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 paddd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * paddd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 paddq %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * paddq (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 paddq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * paddq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 paddsb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * paddsb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 paddsw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * paddsw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 paddusb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * paddusb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 paddusw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * paddusw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 paddw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * paddw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pand %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * pand (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pandn %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * pandn (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pavgb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * pavgb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pavgw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * pavgw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pcmpeqb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * pcmpeqb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pcmpeqd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * pcmpeqd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pcmpeqw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * pcmpeqw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * pcmpgtb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * pcmpgtd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * pcmpgtw (%rax), %xmm2
+# CHECK-NEXT: 1 1 2.00 pextrw $1, %xmm0, %ecx
+# CHECK-NEXT: 1 2 0.50 pinsrw $1, %eax, %xmm0
+# CHECK-NEXT: 1 9 0.50 * pinsrw $1, (%rax), %xmm0
+# CHECK-NEXT: 1 3 0.50 pmaddwd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * pmaddwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pmaxsw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * pmaxsw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pmaxub %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * pmaxub (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pminsw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * pminsw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pminub %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * pminub (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovmskb %xmm0, %ecx
+# CHECK-NEXT: 1 3 0.50 pmulhuw %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * pmulhuw (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 pmulhw %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * pmulhw (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 pmullw %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * pmullw (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 pmuludq %mm0, %mm2
+# CHECK-NEXT: 1 10 0.50 * pmuludq (%rax), %mm2
+# CHECK-NEXT: 1 3 0.50 pmuludq %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * pmuludq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 por %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * por (%rax), %xmm2
+# CHECK-NEXT: 1 3 1.00 psadbw %xmm0, %xmm2
+# CHECK-NEXT: 1 10 1.00 * psadbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pshufd $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pshufd $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pshufhw $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pshufhw $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pshuflw $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pshuflw $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pslld $1, %xmm2
+# CHECK-NEXT: 1 1 0.50 pslld %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pslld (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pslldq $1, %xmm2
+# CHECK-NEXT: 1 1 0.50 psllq $1, %xmm2
+# CHECK-NEXT: 1 1 0.50 psllq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psllq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psllw $1, %xmm2
+# CHECK-NEXT: 1 1 0.50 psllw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psllw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psrad $1, %xmm2
+# CHECK-NEXT: 1 1 0.50 psrad %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psrad (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psraw $1, %xmm2
+# CHECK-NEXT: 1 1 0.50 psraw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psraw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psrld $1, %xmm2
+# CHECK-NEXT: 1 1 0.50 psrld %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psrld (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psrldq $1, %xmm2
+# CHECK-NEXT: 1 1 0.50 psrlq $1, %xmm2
+# CHECK-NEXT: 1 1 0.50 psrlq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psrlq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 psrlw $1, %xmm2
+# CHECK-NEXT: 1 1 0.50 psrlw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * psrlw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 psubb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * psubb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 psubd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * psubd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 psubq %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * psubq (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 psubq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * psubq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 psubsb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * psubsb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 psubsw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * psubsw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 psubusb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * psubusb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 psubusw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * psubusw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 psubw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * psubw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpckhbw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * punpckhbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpckhdq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * punpckhdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpckhqdq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * punpckhqdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpckhwd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * punpckhwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpcklbw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * punpcklbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpckldq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * punpckldq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpcklqdq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * punpcklqdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 punpcklwd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * punpcklwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pxor %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * pxor (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 shufpd $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * shufpd $1, (%rax), %xmm2
+# CHECK-NEXT: 1 8 9.50 sqrtpd %xmm0, %xmm2
+# CHECK-NEXT: 1 15 9.50 * sqrtpd (%rax), %xmm2
+# CHECK-NEXT: 1 8 9.50 sqrtsd %xmm0, %xmm2
+# CHECK-NEXT: 1 15 9.50 * sqrtsd (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 subpd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * subpd (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 subsd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * subsd (%rax), %xmm2
+# CHECK-NEXT: 2 1 0.50 ucomisd %xmm0, %xmm1
+# CHECK-NEXT: 2 8 0.50 * ucomisd (%rax), %xmm1
+# CHECK-NEXT: 1 1 0.50 unpckhpd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * unpckhpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 unpcklpd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * unpcklpd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 xorpd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * xorpd (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 44.67 44.67 44.67 - - - - - 53.25 141.75 53.25 139.75 33.50 33.50 33.50 33.50 39.33 39.33 39.33 4.00 4.00 4.00 4.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - addpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - addpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - addsd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - addsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - andnpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - andnpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - andpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - andpd (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - clflush (%rax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - cmpeqpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmpeqpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - cmpeqsd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmpeqsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - comisd %xmm0, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - comisd (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - cvtdq2pd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cvtdq2pd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - cvtdq2ps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cvtdq2ps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - cvtpd2dq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cvtpd2dq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - cvtpd2pi %xmm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cvtpd2pi (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - cvtpd2ps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cvtpd2ps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - cvtpi2pd %mm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cvtpi2pd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - cvtps2dq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cvtps2dq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - cvtps2pd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cvtps2pd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - cvtsd2si %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - cvtsd2si %xmm0, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cvtsd2si (%rax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cvtsd2si (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - cvtsd2ss %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cvtsd2ss (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.50 - 1.50 - - - - - - - - - - - cvtsi2sd %ecx, %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.50 - 1.50 - - - - - - - - - - - cvtsi2sd %rcx, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.50 - 1.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cvtsi2sdl (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.50 - 1.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cvtsi2sdq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - cvtss2sd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cvtss2sd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - cvttpd2dq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cvttpd2dq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - cvttpd2pi %xmm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cvttpd2pi (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - cvttps2dq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cvttps2dq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - cvttsd2si %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - cvttsd2si %xmm0, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cvttsd2si (%rax), %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - 1.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cvttsd2si (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - - 6.00 - 6.00 - - - - - - - - - - - divpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.00 - 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - divpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 6.00 - 6.00 - - - - - - - - - - - divsd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 6.00 - 6.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - divsd (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - lfence
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 maskmovdqu %xmm0, %xmm1
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - maxpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - maxpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - maxsd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - maxsd (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - - - - - - - - - - - - mfence
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - minpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - minpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - minsd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - minsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - movapd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 movapd %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movapd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - movd %eax, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - movd %xmm0, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 movd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - movdqa %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 movdqa %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movdqa (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - movdqu %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 movdqu %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movdqu (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - movdq2q %xmm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 movhpd %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movhpd (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 movlpd %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movlpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - movmskpd %xmm0, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 movntil %eax, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 movntiq %rax, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 movntdq %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 movntpd %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - movq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - movq %rax, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - movq %xmm0, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 movq %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - movq2dq %mm0, %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - movsd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 movsd %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - movupd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 movupd %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movupd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - mulpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - mulpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - mulsd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - mulsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - orpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - orpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - packssdw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - packssdw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - packsswb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - packsswb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - packuswb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - packuswb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - paddb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - paddb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - paddd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - paddd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - paddq %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - paddq (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - paddq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - paddq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - paddsb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - paddsb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - paddsw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - paddsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - paddusb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - paddusb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - paddusw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - paddusw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - paddw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - paddw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pand %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pand (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pandn %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pandn (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pavgb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pavgb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pavgw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pavgw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pcmpeqb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pcmpeqb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pcmpeqd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pcmpeqd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pcmpeqw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pcmpeqw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pcmpgtb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pcmpgtb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pcmpgtd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pcmpgtd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pcmpgtw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pcmpgtw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - pextrw $1, %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - pinsrw $1, %eax, %xmm0
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pinsrw $1, (%rax), %xmm0
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - pmaddwd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmaddwd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pmaxsw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmaxsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pmaxub %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmaxub (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pminsw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pminsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pminub %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pminub (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - pmovmskb %xmm0, %ecx
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - pmulhuw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmulhuw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - pmulhw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmulhw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - pmullw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmullw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - pmuludq %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmuludq (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - pmuludq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmuludq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - por %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - por (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - psadbw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psadbw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - pshufd $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pshufd $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - pshufhw $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pshufhw $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - pshuflw $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pshuflw $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - pslld $1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - pslld %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pslld (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - pslldq $1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - psllq $1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - psllq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psllq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - psllw $1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - psllw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psllw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - psrad $1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - psrad %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psrad (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - psraw $1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - psraw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psraw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - psrld $1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - psrld %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psrld (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - psrldq $1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - psrlq $1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - psrlq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psrlq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - psrlw $1, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - psrlw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psrlw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - psubb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psubb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - psubd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psubd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - psubq %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psubq (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - psubq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psubq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - psubsb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psubsb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - psubsw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psubsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - psubusb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psubusb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - psubusw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psubusw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - psubw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psubw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - punpckhbw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - punpckhbw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - punpckhdq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - punpckhdq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - punpckhqdq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - punpckhqdq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - punpckhwd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - punpckhwd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - punpcklbw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - punpcklbw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - punpckldq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - punpckldq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - punpcklqdq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - punpcklqdq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - punpcklwd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - punpcklwd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pxor %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pxor (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - shufpd $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - shufpd $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 9.50 - 9.50 - - - - - - - - - - - sqrtpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 9.50 - 9.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - sqrtpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 9.50 - 9.50 - - - - - - - - - - - sqrtsd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 9.50 - 9.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - sqrtsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - subpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - subpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - subsd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - subsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - ucomisd %xmm0, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 0.50 0.50 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - ucomisd (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - unpckhpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - unpckhpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - unpcklpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - unpcklpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - xorpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - xorpd (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse3.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse3.s
new file mode 100644
index 0000000000000..8b210aede2178
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse3.s
@@ -0,0 +1,119 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+addsubpd %xmm0, %xmm2
+addsubpd (%rax), %xmm2
+
+addsubps %xmm0, %xmm2
+addsubps (%rax), %xmm2
+
+haddpd %xmm0, %xmm2
+haddpd (%rax), %xmm2
+
+haddps %xmm0, %xmm2
+haddps (%rax), %xmm2
+
+hsubpd %xmm0, %xmm2
+hsubpd (%rax), %xmm2
+
+hsubps %xmm0, %xmm2
+hsubps (%rax), %xmm2
+
+lddqu (%rax), %xmm2
+
+monitor
+
+movddup %xmm0, %xmm2
+movddup (%rax), %xmm2
+
+movshdup %xmm0, %xmm2
+movshdup (%rax), %xmm2
+
+movsldup %xmm0, %xmm2
+movsldup (%rax), %xmm2
+
+mwait
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 addsubpd %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * addsubpd (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 addsubps %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * addsubps (%rax), %xmm2
+# CHECK-NEXT: 4 7 4.00 haddpd %xmm0, %xmm2
+# CHECK-NEXT: 7 14 4.00 * haddpd (%rax), %xmm2
+# CHECK-NEXT: 4 7 4.00 haddps %xmm0, %xmm2
+# CHECK-NEXT: 7 14 4.00 * haddps (%rax), %xmm2
+# CHECK-NEXT: 4 7 4.00 hsubpd %xmm0, %xmm2
+# CHECK-NEXT: 7 14 4.00 * hsubpd (%rax), %xmm2
+# CHECK-NEXT: 4 7 4.00 hsubps %xmm0, %xmm2
+# CHECK-NEXT: 7 14 4.00 * hsubps (%rax), %xmm2
+# CHECK-NEXT: 1 8 0.33 * lddqu (%rax), %xmm2
+# CHECK-NEXT: 1 100 0.25 U monitor
+# CHECK-NEXT: 1 1 0.50 movddup %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * movddup (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 movshdup %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * movshdup (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 movsldup %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * movsldup (%rax), %xmm2
+# CHECK-NEXT: 1 100 0.25 * * U mwait
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 3.33 3.33 3.33 - - - - - - 37.00 - 37.00 2.50 2.50 2.50 2.50 3.33 3.33 3.33 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - addsubpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - addsubpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - addsubps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - addsubps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - haddpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - haddpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - haddps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - haddps (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - hsubpd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - hsubpd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - hsubps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - hsubps (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - lddqu (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - monitor
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - movddup %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movddup (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - movshdup %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movshdup (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - movsldup %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movsldup (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - mwait
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse41.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse41.s
new file mode 100644
index 0000000000000..bdaf851fb47c1
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse41.s
@@ -0,0 +1,381 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+blendpd $11, %xmm0, %xmm2
+blendpd $11, (%rax), %xmm2
+
+blendps $11, %xmm0, %xmm2
+blendps $11, (%rax), %xmm2
+
+blendvpd %xmm0, %xmm2
+blendvpd (%rax), %xmm2
+
+blendvps %xmm0, %xmm2
+blendvps (%rax), %xmm2
+
+dppd $22, %xmm0, %xmm2
+dppd $22, (%rax), %xmm2
+
+dpps $22, %xmm0, %xmm2
+dpps $22, (%rax), %xmm2
+
+extractps $1, %xmm0, %rcx
+extractps $1, %xmm0, (%rax)
+
+insertps $1, %xmm0, %xmm2
+insertps $1, (%rax), %xmm2
+
+movntdqa (%rax), %xmm2
+
+mpsadbw $1, %xmm0, %xmm2
+mpsadbw $1, (%rax), %xmm2
+
+packusdw %xmm0, %xmm2
+packusdw (%rax), %xmm2
+
+pblendvb %xmm0, %xmm2
+pblendvb (%rax), %xmm2
+
+pblendw $11, %xmm0, %xmm2
+pblendw $11, (%rax), %xmm2
+
+pcmpeqq %xmm0, %xmm2
+pcmpeqq (%rax), %xmm2
+
+pextrb $1, %xmm0, %ecx
+pextrb $1, %xmm0, (%rax)
+
+pextrd $1, %xmm0, %ecx
+pextrd $1, %xmm0, (%rax)
+
+pextrq $1, %xmm0, %rcx
+pextrq $1, %xmm0, (%rax)
+
+pextrw $1, %xmm0, (%rax)
+
+phminposuw %xmm0, %xmm2
+phminposuw (%rax), %xmm2
+
+pinsrb $1, %eax, %xmm1
+pinsrb $1, (%rax), %xmm1
+
+pinsrd $1, %eax, %xmm1
+pinsrd $1, (%rax), %xmm1
+
+pinsrq $1, %rax, %xmm1
+pinsrq $1, (%rax), %xmm1
+
+pmaxsb %xmm0, %xmm2
+pmaxsb (%rax), %xmm2
+
+pmaxsd %xmm0, %xmm2
+pmaxsd (%rax), %xmm2
+
+pmaxud %xmm0, %xmm2
+pmaxud (%rax), %xmm2
+
+pmaxuw %xmm0, %xmm2
+pmaxuw (%rax), %xmm2
+
+pminsb %xmm0, %xmm2
+pminsb (%rax), %xmm2
+
+pminsd %xmm0, %xmm2
+pminsd (%rax), %xmm2
+
+pminud %xmm0, %xmm2
+pminud (%rax), %xmm2
+
+pminuw %xmm0, %xmm2
+pminuw (%rax), %xmm2
+
+pmovsxbd %xmm0, %xmm2
+pmovsxbd (%rax), %xmm2
+
+pmovsxbq %xmm0, %xmm2
+pmovsxbq (%rax), %xmm2
+
+pmovsxbw %xmm0, %xmm2
+pmovsxbw (%rax), %xmm2
+
+pmovsxdq %xmm0, %xmm2
+pmovsxdq (%rax), %xmm2
+
+pmovsxwd %xmm0, %xmm2
+pmovsxwd (%rax), %xmm2
+
+pmovsxwq %xmm0, %xmm2
+pmovsxwq (%rax), %xmm2
+
+pmovzxbd %xmm0, %xmm2
+pmovzxbd (%rax), %xmm2
+
+pmovzxbq %xmm0, %xmm2
+pmovzxbq (%rax), %xmm2
+
+pmovzxbw %xmm0, %xmm2
+pmovzxbw (%rax), %xmm2
+
+pmovzxdq %xmm0, %xmm2
+pmovzxdq (%rax), %xmm2
+
+pmovzxwd %xmm0, %xmm2
+pmovzxwd (%rax), %xmm2
+
+pmovzxwq %xmm0, %xmm2
+pmovzxwq (%rax), %xmm2
+
+pmuldq %xmm0, %xmm2
+pmuldq (%rax), %xmm2
+
+pmulld %xmm0, %xmm2
+pmulld (%rax), %xmm2
+
+ptest %xmm0, %xmm1
+ptest (%rax), %xmm1
+
+roundpd $1, %xmm0, %xmm2
+roundpd $1, (%rax), %xmm2
+
+roundps $1, %xmm0, %xmm2
+roundps $1, (%rax), %xmm2
+
+roundsd $1, %xmm0, %xmm2
+roundsd $1, (%rax), %xmm2
+
+roundss $1, %xmm0, %xmm2
+roundss $1, (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.25 blendpd $11, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * blendpd $11, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 blendps $11, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * blendps $11, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 blendvpd %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * blendvpd %xmm0, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 blendvps %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * blendvps %xmm0, (%rax), %xmm2
+# CHECK-NEXT: 4 9 4.00 dppd $22, %xmm0, %xmm2
+# CHECK-NEXT: 4 16 4.00 * dppd $22, (%rax), %xmm2
+# CHECK-NEXT: 8 14 4.00 dpps $22, %xmm0, %xmm2
+# CHECK-NEXT: 8 21 4.00 * dpps $22, (%rax), %xmm2
+# CHECK-NEXT: 1 1 2.00 extractps $1, %xmm0, %ecx
+# CHECK-NEXT: 1 3 2.00 * extractps $1, %xmm0, (%rax)
+# CHECK-NEXT: 1 1 0.50 insertps $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * insertps $1, (%rax), %xmm2
+# CHECK-NEXT: 1 8 0.33 * movntdqa (%rax), %xmm2
+# CHECK-NEXT: 1 4 2.00 mpsadbw $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 11 2.00 * mpsadbw $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 packusdw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * packusdw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pblendvb %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * pblendvb %xmm0, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pblendw $11, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * pblendw $11, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pcmpeqq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * pcmpeqq (%rax), %xmm2
+# CHECK-NEXT: 1 1 2.00 pextrb $1, %xmm0, %ecx
+# CHECK-NEXT: 1 3 2.00 * pextrb $1, %xmm0, (%rax)
+# CHECK-NEXT: 1 1 2.00 pextrd $1, %xmm0, %ecx
+# CHECK-NEXT: 1 3 2.00 * pextrd $1, %xmm0, (%rax)
+# CHECK-NEXT: 1 1 2.00 pextrq $1, %xmm0, %rcx
+# CHECK-NEXT: 1 3 2.00 * pextrq $1, %xmm0, (%rax)
+# CHECK-NEXT: 1 3 2.00 * pextrw $1, %xmm0, (%rax)
+# CHECK-NEXT: 1 3 1.00 phminposuw %xmm0, %xmm2
+# CHECK-NEXT: 1 10 1.00 * phminposuw (%rax), %xmm2
+# CHECK-NEXT: 1 2 0.50 pinsrb $1, %eax, %xmm1
+# CHECK-NEXT: 1 9 0.50 * pinsrb $1, (%rax), %xmm1
+# CHECK-NEXT: 1 2 0.50 pinsrd $1, %eax, %xmm1
+# CHECK-NEXT: 1 9 0.50 * pinsrd $1, (%rax), %xmm1
+# CHECK-NEXT: 1 2 0.50 pinsrq $1, %rax, %xmm1
+# CHECK-NEXT: 1 9 0.50 * pinsrq $1, (%rax), %xmm1
+# CHECK-NEXT: 1 1 0.25 pmaxsb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * pmaxsb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pmaxsd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * pmaxsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pmaxud %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * pmaxud (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pmaxuw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * pmaxuw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pminsb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * pminsb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pminsd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * pminsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pminud %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * pminud (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pminuw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * pminuw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovsxbd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovsxbd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovsxbq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovsxbq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovsxbw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovsxbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovsxdq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovsxdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovsxwd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovsxwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovsxwq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovsxwq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovzxbd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovzxbd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovzxbq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovzxbq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovzxbw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovzxbw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovzxdq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovzxdq (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovzxwd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovzxwd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pmovzxwq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pmovzxwq (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 pmuldq %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * pmuldq (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 pmulld %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * pmulld (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 ptest %xmm0, %xmm1
+# CHECK-NEXT: 1 8 0.50 * ptest (%rax), %xmm1
+# CHECK-NEXT: 1 4 0.50 roundpd $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * roundpd $1, (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 roundps $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * roundps $1, (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 roundsd $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * roundsd $1, (%rax), %xmm2
+# CHECK-NEXT: 1 4 0.50 roundss $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 11 0.50 * roundss $1, (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 16.33 16.33 16.33 - - - - - 33.50 49.50 33.50 49.50 12.25 12.25 12.25 12.25 14.67 14.67 14.67 1.25 1.25 1.25 1.25
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - blendpd $11, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - blendpd $11, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - blendps $11, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - blendps $11, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - blendvpd %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - blendvpd %xmm0, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - blendvps %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - blendvps %xmm0, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - dppd $22, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - dppd $22, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - dpps $22, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - dpps $22, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - extractps $1, %xmm0, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 extractps $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - insertps $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - insertps $1, (%rax), %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movntdqa (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 2.00 2.00 2.00 - - - - - - - - - - - mpsadbw $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 2.00 2.00 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - mpsadbw $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - packusdw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - packusdw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pblendvb %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pblendvb %xmm0, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pblendw $11, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pblendw $11, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pcmpeqq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pcmpeqq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - pextrb $1, %xmm0, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 pextrb $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - pextrd $1, %xmm0, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 pextrd $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - 2.00 - 2.00 - - - - - - - - - - - - pextrq $1, %xmm0, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 pextrq $1, %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 - 2.00 - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 pextrw $1, %xmm0, (%rax)
+# CHECK-NEXT: - - - - - - - - 1.00 - 1.00 - - - - - - - - - - - - phminposuw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - phminposuw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - pinsrb $1, %eax, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pinsrb $1, (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - pinsrd $1, %eax, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pinsrd $1, (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - pinsrq $1, %rax, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pinsrq $1, (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pmaxsb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmaxsb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pmaxsd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmaxsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pmaxud %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmaxud (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pmaxuw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmaxuw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pminsb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pminsb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pminsd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pminsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pminud %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pminud (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pminuw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pminuw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - pmovsxbd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmovsxbd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - pmovsxbq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmovsxbq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - pmovsxbw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmovsxbw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - pmovsxdq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmovsxdq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - pmovsxwd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmovsxwd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - pmovsxwq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmovsxwq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - pmovzxbd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmovzxbd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - pmovzxbq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmovzxbq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - pmovzxbw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmovzxbw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - pmovzxdq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmovzxdq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - pmovzxwd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmovzxwd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - pmovzxwq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmovzxwq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - pmuldq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmuldq (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - pmulld %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmulld (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - ptest %xmm0, %xmm1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - ptest (%rax), %xmm1
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - roundpd $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - roundpd $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - roundps $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - roundps $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - roundsd $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - roundsd $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - roundss $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - roundss $1, (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse42.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse42.s
new file mode 100644
index 0000000000000..5131206715004
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse42.s
@@ -0,0 +1,114 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+crc32b %al, %ecx
+crc32b (%rax), %ecx
+
+crc32l %eax, %ecx
+crc32l (%rax), %ecx
+
+crc32w %ax, %ecx
+crc32w (%rax), %ecx
+
+crc32b %al, %rcx
+crc32b (%rax), %rcx
+
+crc32q %rax, %rcx
+crc32q (%rax), %rcx
+
+pcmpestri $1, %xmm0, %xmm2
+pcmpestri $1, (%rax), %xmm2
+
+pcmpestrm $1, %xmm0, %xmm2
+pcmpestrm $1, (%rax), %xmm2
+
+pcmpistri $1, %xmm0, %xmm2
+pcmpistri $1, (%rax), %xmm2
+
+pcmpistrm $1, %xmm0, %xmm2
+pcmpistrm $1, (%rax), %xmm2
+
+pcmpgtq %xmm0, %xmm2
+pcmpgtq (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 3 3 3.00 crc32b %al, %ecx
+# CHECK-NEXT: 3 7 3.00 * crc32b (%rax), %ecx
+# CHECK-NEXT: 3 3 3.00 crc32l %eax, %ecx
+# CHECK-NEXT: 3 7 3.00 * crc32l (%rax), %ecx
+# CHECK-NEXT: 3 3 3.00 crc32w %ax, %ecx
+# CHECK-NEXT: 3 7 3.00 * crc32w (%rax), %ecx
+# CHECK-NEXT: 3 3 3.00 crc32b %al, %rcx
+# CHECK-NEXT: 3 7 3.00 * crc32b (%rax), %rcx
+# CHECK-NEXT: 3 3 3.00 crc32q %rax, %rcx
+# CHECK-NEXT: 3 7 3.00 * crc32q (%rax), %rcx
+# CHECK-NEXT: 8 8 3.25 pcmpestri $1, %xmm0, %xmm2
+# CHECK-NEXT: 8 15 3.25 * pcmpestri $1, (%rax), %xmm2
+# CHECK-NEXT: 8 7 6.25 pcmpestrm $1, %xmm0, %xmm2
+# CHECK-NEXT: 8 14 6.25 * pcmpestrm $1, (%rax), %xmm2
+# CHECK-NEXT: 2 2 2.00 pcmpistri $1, %xmm0, %xmm2
+# CHECK-NEXT: 2 9 2.00 * pcmpistri $1, (%rax), %xmm2
+# CHECK-NEXT: 3 7 6.25 pcmpistrm $1, %xmm0, %xmm2
+# CHECK-NEXT: 3 14 6.25 * pcmpistrm $1, (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtq %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * pcmpgtq (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 3.33 3.33 3.33 30.00 30.00 30.00 30.00 - 36.00 36.00 36.00 36.00 2.50 2.50 2.50 2.50 3.33 3.33 3.33 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - - - - - - crc32b %al, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 3.00 3.00 3.00 3.00 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - crc32b (%rax), %ecx
+# CHECK-NEXT: - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - - - - - - crc32l %eax, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 3.00 3.00 3.00 3.00 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - crc32l (%rax), %ecx
+# CHECK-NEXT: - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - - - - - - crc32w %ax, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 3.00 3.00 3.00 3.00 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - crc32w (%rax), %ecx
+# CHECK-NEXT: - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - - - - - - crc32b %al, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 3.00 3.00 3.00 3.00 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - crc32b (%rax), %rcx
+# CHECK-NEXT: - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - - - - - - crc32q %rax, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 3.00 3.00 3.00 3.00 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - crc32q (%rax), %rcx
+# CHECK-NEXT: - - - - - - - - 3.25 3.25 3.25 3.25 - - - - - - - - - - - pcmpestri $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 3.25 3.25 3.25 3.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pcmpestri $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 6.25 6.25 6.25 6.25 - - - - - - - - - - - pcmpestrm $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 6.25 6.25 6.25 6.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pcmpestrm $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 2.00 2.00 2.00 2.00 - - - - - - - - - - - pcmpistri $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 2.00 2.00 2.00 2.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pcmpistri $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 6.25 6.25 6.25 6.25 - - - - - - - - - - - pcmpistrm $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 6.25 6.25 6.25 6.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pcmpistrm $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pcmpgtq %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pcmpgtq (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse4a.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse4a.s
new file mode 100644
index 0000000000000..e1b6784322802
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse4a.s
@@ -0,0 +1,65 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+extrq %xmm0, %xmm2
+extrq $22, $2, %xmm2
+
+insertq %xmm0, %xmm2
+insertq $22, $22, %xmm0, %xmm2
+
+movntsd %xmm0, (%rax)
+movntss %xmm0, (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.25 extrq %xmm0, %xmm2
+# CHECK-NEXT: 1 3 0.25 extrq $22, $2, %xmm2
+# CHECK-NEXT: 1 3 0.25 insertq %xmm0, %xmm2
+# CHECK-NEXT: 1 3 0.25 insertq $22, $22, %xmm0, %xmm2
+# CHECK-NEXT: 1 2 1.00 * movntsd %xmm0, (%rax)
+# CHECK-NEXT: 1 2 1.00 * movntss %xmm0, (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 0.67 0.67 0.67 - - - - - 1.00 3.00 1.00 1.00 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - extrq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - extrq $22, $2, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - insertq %xmm0, %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - insertq $22, $22, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 movntsd %xmm0, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 movntss %xmm0, (%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-ssse3.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-ssse3.s
new file mode 100644
index 0000000000000..20f93557d8abe
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-ssse3.s
@@ -0,0 +1,268 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+pabsb %mm0, %mm2
+pabsb (%rax), %mm2
+
+pabsb %xmm0, %xmm2
+pabsb (%rax), %xmm2
+
+pabsd %mm0, %mm2
+pabsd (%rax), %mm2
+
+pabsd %xmm0, %xmm2
+pabsd (%rax), %xmm2
+
+pabsw %mm0, %mm2
+pabsw (%rax), %mm2
+
+pabsw %xmm0, %xmm2
+pabsw (%rax), %xmm2
+
+palignr $1, %mm0, %mm2
+palignr $1, (%rax), %mm2
+
+palignr $1, %xmm0, %xmm2
+palignr $1, (%rax), %xmm2
+
+phaddd %mm0, %mm2
+phaddd (%rax), %mm2
+
+phaddd %xmm0, %xmm2
+phaddd (%rax), %xmm2
+
+phaddsw %mm0, %mm2
+phaddsw (%rax), %mm2
+
+phaddsw %xmm0, %xmm2
+phaddsw (%rax), %xmm2
+
+phaddw %mm0, %mm2
+phaddw (%rax), %mm2
+
+phaddw %xmm0, %xmm2
+phaddw (%rax), %xmm2
+
+phsubd %mm0, %mm2
+phsubd (%rax), %mm2
+
+phsubd %xmm0, %xmm2
+phsubd (%rax), %xmm2
+
+phsubsw %mm0, %mm2
+phsubsw (%rax), %mm2
+
+phsubsw %xmm0, %xmm2
+phsubsw (%rax), %xmm2
+
+phsubw %mm0, %mm2
+phsubw (%rax), %mm2
+
+phsubw %xmm0, %xmm2
+phsubw (%rax), %xmm2
+
+pmaddubsw %mm0, %mm2
+pmaddubsw (%rax), %mm2
+
+pmaddubsw %xmm0, %xmm2
+pmaddubsw (%rax), %xmm2
+
+pmulhrsw %mm0, %mm2
+pmulhrsw (%rax), %mm2
+
+pmulhrsw %xmm0, %xmm2
+pmulhrsw (%rax), %xmm2
+
+pshufb %mm0, %mm2
+pshufb (%rax), %mm2
+
+pshufb %xmm0, %xmm2
+pshufb (%rax), %xmm2
+
+psignb %mm0, %mm2
+psignb (%rax), %mm2
+
+psignb %xmm0, %xmm2
+psignb (%rax), %xmm2
+
+psignd %mm0, %mm2
+psignd (%rax), %mm2
+
+psignd %xmm0, %xmm2
+psignd (%rax), %xmm2
+
+psignw %mm0, %mm2
+psignw (%rax), %mm2
+
+psignw %xmm0, %xmm2
+psignw (%rax), %xmm2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.25 pabsb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * pabsb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pabsb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * pabsb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pabsd %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * pabsd (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pabsd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * pabsd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 pabsw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * pabsw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 pabsw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * pabsw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 palignr $1, %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * palignr $1, (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 palignr $1, %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * palignr $1, (%rax), %xmm2
+# CHECK-NEXT: 4 3 4.00 phaddd %mm0, %mm2
+# CHECK-NEXT: 7 10 4.00 * phaddd (%rax), %mm2
+# CHECK-NEXT: 4 3 4.00 phaddd %xmm0, %xmm2
+# CHECK-NEXT: 7 10 4.00 * phaddd (%rax), %xmm2
+# CHECK-NEXT: 4 3 4.00 phaddsw %mm0, %mm2
+# CHECK-NEXT: 7 10 4.00 * phaddsw (%rax), %mm2
+# CHECK-NEXT: 4 3 4.00 phaddsw %xmm0, %xmm2
+# CHECK-NEXT: 7 10 4.00 * phaddsw (%rax), %xmm2
+# CHECK-NEXT: 4 3 4.00 phaddw %mm0, %mm2
+# CHECK-NEXT: 7 10 4.00 * phaddw (%rax), %mm2
+# CHECK-NEXT: 4 3 4.00 phaddw %xmm0, %xmm2
+# CHECK-NEXT: 7 10 4.00 * phaddw (%rax), %xmm2
+# CHECK-NEXT: 4 3 4.00 phsubd %mm0, %mm2
+# CHECK-NEXT: 7 10 4.00 * phsubd (%rax), %mm2
+# CHECK-NEXT: 4 3 4.00 phsubd %xmm0, %xmm2
+# CHECK-NEXT: 7 10 4.00 * phsubd (%rax), %xmm2
+# CHECK-NEXT: 4 3 4.00 phsubsw %mm0, %mm2
+# CHECK-NEXT: 7 10 4.00 * phsubsw (%rax), %mm2
+# CHECK-NEXT: 4 3 4.00 phsubsw %xmm0, %xmm2
+# CHECK-NEXT: 7 10 4.00 * phsubsw (%rax), %xmm2
+# CHECK-NEXT: 4 3 4.00 phsubw %mm0, %mm2
+# CHECK-NEXT: 7 10 4.00 * phsubw (%rax), %mm2
+# CHECK-NEXT: 4 3 4.00 phsubw %xmm0, %xmm2
+# CHECK-NEXT: 7 10 4.00 * phsubw (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 pmaddubsw %mm0, %mm2
+# CHECK-NEXT: 1 10 0.50 * pmaddubsw (%rax), %mm2
+# CHECK-NEXT: 1 3 0.50 pmaddubsw %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * pmaddubsw (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 pmulhrsw %mm0, %mm2
+# CHECK-NEXT: 1 10 0.50 * pmulhrsw (%rax), %mm2
+# CHECK-NEXT: 1 3 0.50 pmulhrsw %xmm0, %xmm2
+# CHECK-NEXT: 1 10 0.50 * pmulhrsw (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.50 pshufb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.50 * pshufb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.50 pshufb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.50 * pshufb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 psignb %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * psignb (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 psignb %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * psignb (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 psignd %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * psignd (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 psignd %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * psignd (%rax), %xmm2
+# CHECK-NEXT: 1 1 0.25 psignw %mm0, %mm2
+# CHECK-NEXT: 1 8 0.33 * psignw (%rax), %mm2
+# CHECK-NEXT: 1 1 0.25 psignw %xmm0, %xmm2
+# CHECK-NEXT: 1 8 0.33 * psignw (%rax), %xmm2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 10.67 10.67 10.67 - - - - - 10.00 106.00 10.00 106.00 8.00 8.00 8.00 8.00 10.67 10.67 10.67 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pabsb %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pabsb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pabsb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pabsb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pabsd %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pabsd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pabsd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pabsd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pabsw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pabsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - pabsw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pabsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - palignr $1, %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - palignr $1, (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - palignr $1, %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - palignr $1, (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - phaddd %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - phaddd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - phaddd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - phaddd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - phaddsw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - phaddsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - phaddsw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - phaddsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - phaddw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - phaddw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - phaddw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - phaddw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - phsubd %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - phsubd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - phsubd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - phsubd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - phsubsw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - phsubsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - phsubsw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - phsubsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - phsubw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - phsubw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 4.00 - 4.00 - - - - - - - - - - - phsubw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.00 - 4.00 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - phsubw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - pmaddubsw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmaddubsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - pmaddubsw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmaddubsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - pmulhrsw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmulhrsw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - pmulhrsw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pmulhrsw (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - pshufb %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pshufb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - pshufb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - pshufb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - psignb %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psignb (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - psignb %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psignb (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - psignd %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psignd (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - psignd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psignd (%rax), %xmm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - psignw %mm0, %mm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psignw (%rax), %mm2
+# CHECK-NEXT: - - - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - psignw %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - psignw (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-vaes.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-vaes.s
new file mode 100644
index 0000000000000..1a9d48741d04e
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-vaes.s
@@ -0,0 +1,72 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+vaesdec %ymm0, %ymm1, %ymm3
+vaesdec (%rax), %ymm1, %ymm3
+
+vaesdeclast %ymm0, %ymm1, %ymm3
+vaesdeclast (%rax), %ymm1, %ymm3
+
+vaesenc %ymm0, %ymm1, %ymm3
+vaesenc (%rax), %ymm1, %ymm3
+
+vaesenclast %ymm0, %ymm1, %ymm3
+vaesenclast (%rax), %ymm1, %ymm3
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 vaesdec %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: 1 10 0.50 * vaesdec (%rax), %ymm1, %ymm3
+# CHECK-NEXT: 1 3 0.50 vaesdeclast %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: 1 10 0.50 * vaesdeclast (%rax), %ymm1, %ymm3
+# CHECK-NEXT: 1 3 0.50 vaesenc %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: 1 10 0.50 * vaesenc (%rax), %ymm1, %ymm3
+# CHECK-NEXT: 1 3 0.50 vaesenclast %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: 1 10 0.50 * vaesenclast (%rax), %ymm1, %ymm3
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 1.33 1.33 1.33 - - - - - - 4.00 - 4.00 1.00 1.00 1.00 1.00 1.33 1.33 1.33 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaesdec %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaesdec (%rax), %ymm1, %ymm3
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaesdeclast %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaesdeclast (%rax), %ymm1, %ymm3
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaesenc %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaesenc (%rax), %ymm1, %ymm3
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - vaesenclast %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vaesenclast (%rax), %ymm1, %ymm3
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-vpclmulqdq.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-vpclmulqdq.s
new file mode 100644
index 0000000000000..577932a44ab4d
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-vpclmulqdq.s
@@ -0,0 +1,51 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+vpclmulqdq $11, %ymm0, %ymm1, %ymm3
+vpclmulqdq $11, (%rax), %ymm1, %ymm3
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 vpclmulqdq $11, %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: 1 10 0.50 * vpclmulqdq $11, (%rax), %ymm1, %ymm3
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 1.00 - 1.00 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - vpclmulqdq $11, %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - vpclmulqdq $11, (%rax), %ymm1, %ymm3
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-x86_32.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-x86_32.s
new file mode 100644
index 0000000000000..0b2f8aacd9fa5
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-x86_32.s
@@ -0,0 +1,93 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=i686-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+aaa
+
+aad
+aad $7
+
+aam
+aam $7
+
+aas
+
+bound %bx, (%eax)
+bound %ebx, (%eax)
+
+daa
+
+das
+
+into
+
+leave
+
+salc
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 100 0.25 aaa
+# CHECK-NEXT: 1 100 0.25 aad
+# CHECK-NEXT: 1 100 0.25 aad $7
+# CHECK-NEXT: 1 100 0.25 aam
+# CHECK-NEXT: 1 100 0.25 aam $7
+# CHECK-NEXT: 1 100 0.25 aas
+# CHECK-NEXT: 1 100 0.25 U bound %bx, (%eax)
+# CHECK-NEXT: 1 100 0.25 U bound %ebx, (%eax)
+# CHECK-NEXT: 1 100 0.25 daa
+# CHECK-NEXT: 1 100 0.25 das
+# CHECK-NEXT: 1 100 0.25 U into
+# CHECK-NEXT: 1 1 0.25 * leave
+# CHECK-NEXT: 1 1 0.25 U salc
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - aaa
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - aad
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - aad $7
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - aam
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - aam $7
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - aas
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - bound %bx, (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - bound %ebx, (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - daa
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - das
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - into
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leave
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - salc
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-x86_64.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-x86_64.s
new file mode 100644
index 0000000000000..c4284ca25d5a9
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-x86_64.s
@@ -0,0 +1,2894 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+adcb $0, %al
+adcb $0, %dil
+adcb $0, (%rax)
+lock adcb $0, (%rax)
+adcb $7, %al
+adcb $7, %dil
+adcb $7, (%rax)
+lock adcb $7, (%rax)
+adcb %sil, %dil
+adcb %sil, (%rax)
+lock adcb %sil, (%rax)
+adcb (%rax), %dil
+
+adcw $0, %ax
+adcw $0, %di
+adcw $0, (%rax)
+lock adcw $0, (%rax)
+adcw $511, %ax
+adcw $511, %di
+adcw $511, (%rax)
+lock adcw $511, (%rax)
+adcw $7, %di
+adcw $7, (%rax)
+lock adcw $7, (%rax)
+adcw %si, %di
+adcw %si, (%rax)
+lock adcw %si, (%rax)
+adcw (%rax), %di
+
+adcl $0, %eax
+adcl $0, %edi
+adcl $0, (%rax)
+lock adcl $0, (%rax)
+adcl $665536, %eax
+adcl $665536, %edi
+adcl $665536, (%rax)
+lock adcl $665536, (%rax)
+adcl $7, %edi
+adcl $7, (%rax)
+lock adcl $7, (%rax)
+adcl %esi, %edi
+adcl %esi, (%rax)
+lock adcl %esi, (%rax)
+adcl (%rax), %edi
+
+adcq $0, %rax
+adcq $0, %rdi
+adcq $0, (%rax)
+lock adcq $0, (%rax)
+adcq $665536, %rax
+adcq $665536, %rdi
+adcq $665536, (%rax)
+lock adcq $665536, (%rax)
+adcq $7, %rdi
+adcq $7, (%rax)
+lock adcq $7, (%rax)
+adcq %rsi, %rdi
+adcq %rsi, (%rax)
+lock adcq %rsi, (%rax)
+adcq (%rax), %rdi
+
+addb $7, %al
+addb $7, %dil
+addb $7, (%rax)
+lock addb $7, (%rax)
+addb %sil, %dil
+addb %sil, (%rax)
+lock addb %sil, (%rax)
+addb (%rax), %dil
+
+addw $511, %ax
+addw $511, %di
+addw $511, (%rax)
+lock addw $511, (%rax)
+addw $7, %di
+addw $7, (%rax)
+lock addw $7, (%rax)
+addw %si, %di
+addw %si, (%rax)
+lock addw %si, (%rax)
+addw (%rax), %di
+
+addl $665536, %eax
+addl $665536, %edi
+addl $665536, (%rax)
+lock addl $665536, (%rax)
+addl $7, %edi
+addl $7, (%rax)
+lock addl $7, (%rax)
+addl %esi, %edi
+addl %esi, (%rax)
+lock addl %esi, (%rax)
+addl (%rax), %edi
+
+addq $665536, %rax
+addq $665536, %rdi
+addq $665536, (%rax)
+lock addq $665536, (%rax)
+addq $7, %rdi
+addq $7, (%rax)
+lock addq $7, (%rax)
+addq %rsi, %rdi
+addq %rsi, (%rax)
+lock addq %rsi, (%rax)
+addq (%rax), %rdi
+
+andb $7, %al
+andb $7, %dil
+andb $7, (%rax)
+lock andb $7, (%rax)
+andb %sil, %dil
+andb %sil, (%rax)
+lock andb %sil, (%rax)
+andb (%rax), %dil
+
+andw $511, %ax
+andw $511, %di
+andw $511, (%rax)
+lock andw $511, (%rax)
+andw $7, %di
+andw $7, (%rax)
+lock andw $7, (%rax)
+andw %si, %di
+andw %si, (%rax)
+lock andw %si, (%rax)
+andw (%rax), %di
+
+andl $665536, %eax
+andl $665536, %edi
+andl $665536, (%rax)
+lock andl $665536, (%rax)
+andl $7, %edi
+andl $7, (%rax)
+lock andl $7, (%rax)
+andl %esi, %edi
+andl %esi, (%rax)
+lock andl %esi, (%rax)
+andl (%rax), %edi
+
+andq $665536, %rax
+andq $665536, %rdi
+andq $665536, (%rax)
+lock andq $665536, (%rax)
+andq $7, %rdi
+andq $7, (%rax)
+lock andq $7, (%rax)
+andq %rsi, %rdi
+andq %rsi, (%rax)
+lock andq %rsi, (%rax)
+andq (%rax), %rdi
+
+bsfw %si, %di
+bsrw %si, %di
+bsfw (%rax), %di
+bsrw (%rax), %di
+
+bsfl %esi, %edi
+bsrl %esi, %edi
+bsfl (%rax), %edi
+bsrl (%rax), %edi
+
+bsfq %rsi, %rdi
+bsrq %rsi, %rdi
+bsfq (%rax), %rdi
+bsrq (%rax), %rdi
+
+bswap %eax
+bswap %rax
+
+btw %si, %di
+btcw %si, %di
+btrw %si, %di
+btsw %si, %di
+btw %si, (%rax)
+btcw %si, (%rax)
+btrw %si, (%rax)
+btsw %si, (%rax)
+lock btcw %si, (%rax)
+lock btrw %si, (%rax)
+lock btsw %si, (%rax)
+btw $7, %di
+btcw $7, %di
+btrw $7, %di
+btsw $7, %di
+btw $7, (%rax)
+btcw $7, (%rax)
+btrw $7, (%rax)
+btsw $7, (%rax)
+lock btcw $7, (%rax)
+lock btrw $7, (%rax)
+lock btsw $7, (%rax)
+
+btl %esi, %edi
+btcl %esi, %edi
+btrl %esi, %edi
+btsl %esi, %edi
+btl %esi, (%rax)
+btcl %esi, (%rax)
+btrl %esi, (%rax)
+btsl %esi, (%rax)
+lock btcl %esi, (%rax)
+lock btrl %esi, (%rax)
+lock btsl %esi, (%rax)
+btl $7, %edi
+btcl $7, %edi
+btrl $7, %edi
+btsl $7, %edi
+btl $7, (%rax)
+btcl $7, (%rax)
+btrl $7, (%rax)
+btsl $7, (%rax)
+lock btcl $7, (%rax)
+lock btrl $7, (%rax)
+lock btsl $7, (%rax)
+
+btq %rsi, %rdi
+btcq %rsi, %rdi
+btrq %rsi, %rdi
+btsq %rsi, %rdi
+btq %rsi, (%rax)
+btcq %rsi, (%rax)
+btrq %rsi, (%rax)
+btsq %rsi, (%rax)
+lock btcq %rsi, (%rax)
+lock btrq %rsi, (%rax)
+lock btsq %rsi, (%rax)
+btq $7, %rdi
+btcq $7, %rdi
+btrq $7, %rdi
+btsq $7, %rdi
+btq $7, (%rax)
+btcq $7, (%rax)
+btrq $7, (%rax)
+btsq $7, (%rax)
+lock btcq $7, (%rax)
+lock btrq $7, (%rax)
+lock btsq $7, (%rax)
+
+cbw
+cwde
+cdqe
+cwd
+cdq
+cqo
+
+clc
+cld
+cmc
+
+cmpb $7, %al
+cmpb $7, %dil
+cmpb $7, (%rax)
+cmpb %sil, %dil
+cmpb %sil, (%rax)
+cmpb (%rax), %dil
+
+cmpw $511, %ax
+cmpw $511, %di
+cmpw $511, (%rax)
+cmpw $7, %di
+cmpw $7, (%rax)
+cmpw %si, %di
+cmpw %si, (%rax)
+cmpw (%rax), %di
+
+cmpl $665536, %eax
+cmpl $665536, %edi
+cmpl $665536, (%rax)
+cmpl $7, %edi
+cmpl $7, (%rax)
+cmpl %esi, %edi
+cmpl %esi, (%rax)
+cmpl (%rax), %edi
+
+cmpq $665536, %rax
+cmpq $665536, %rdi
+cmpq $665536, (%rax)
+cmpq $7, %rdi
+cmpq $7, (%rax)
+cmpq %rsi, %rdi
+cmpq %rsi, (%rax)
+cmpq (%rax), %rdi
+
+cmpsb
+cmpsw
+cmpsl
+cmpsq
+
+cmpxchgb %cl, %bl
+cmpxchgb %cl, (%rbx)
+lock cmpxchgb %cl, (%rbx)
+
+cmpxchgw %cx, %bx
+cmpxchgw %cx, (%rbx)
+lock cmpxchgw %cx, (%rbx)
+
+cmpxchgl %ecx, %ebx
+cmpxchgl %ecx, (%rbx)
+lock cmpxchgl %ecx, (%rbx)
+
+cmpxchgq %rcx, %rbx
+cmpxchgq %rcx, (%rbx)
+lock cmpxchgq %rcx, (%rbx)
+
+cpuid
+
+decb %dil
+decb (%rax)
+lock decb (%rax)
+decw %di
+decw (%rax)
+lock decw (%rax)
+decl %edi
+decl (%rax)
+lock decl (%rax)
+decq %rdi
+decq (%rax)
+lock decq (%rax)
+
+divb %dil
+divb (%rax)
+divw %si
+divw (%rax)
+divl %edx
+divl (%rax)
+divq %rcx
+divq (%rax)
+
+enter $7, $4095
+
+idivb %dil
+idivb (%rax)
+idivw %si
+idivw (%rax)
+idivl %edx
+idivl (%rax)
+idivq %rcx
+idivq (%rax)
+
+imulb %dil
+imulb (%rax)
+
+imulw %di
+imulw (%rax)
+imulw %si, %di
+imulw (%rax), %di
+imulw $511, %si, %di
+imulw $511, (%rax), %di
+imulw $7, %si, %di
+imulw $7, (%rax), %di
+
+imull %edi
+imull (%rax)
+imull %esi, %edi
+imull (%rax), %edi
+imull $665536, %esi, %edi
+imull $665536, (%rax), %edi
+imull $7, %esi, %edi
+imull $7, (%rax), %edi
+
+imulq %rdi
+imulq (%rax)
+imulq %rsi, %rdi
+imulq (%rax), %rdi
+imulq $665536, %rsi, %rdi
+imulq $665536, (%rax), %rdi
+imulq $7, %rsi, %rdi
+imulq $7, (%rax), %rdi
+
+inb $7, %al
+inb %dx, %al
+inw $7, %ax
+inw %dx, %ax
+inl $7, %eax
+inl %dx, %eax
+
+incb %dil
+incb (%rax)
+lock incb (%rax)
+incw %di
+incw (%rax)
+lock incw (%rax)
+incl %edi
+incl (%rax)
+lock incl (%rax)
+incq %rdi
+incq (%rax)
+lock incq (%rax)
+
+insb
+insw
+insl
+
+int $7
+
+invlpg (%rax)
+invlpga %rax, %ecx
+
+lahf
+
+leave
+
+lodsb
+lodsw
+lodsl
+lodsq
+
+loop 0
+loope 0
+loopne 0
+
+movsb
+movsw
+movsl
+movsq
+
+movsbw %al, %di
+movzbw %al, %di
+movsbw (%rax), %di
+movzbw (%rax), %di
+movsbl %al, %edi
+movzbl %al, %edi
+movsbl (%rax), %edi
+movzbl (%rax), %edi
+movsbq %al, %rdi
+movzbq %al, %rdi
+movsbq (%rax), %rdi
+movzbq (%rax), %rdi
+
+movswl %ax, %edi
+movzwl %ax, %edi
+movswl (%rax), %edi
+movzwl (%rax), %edi
+movswq %ax, %rdi
+movzwq %ax, %rdi
+movswq (%rax), %rdi
+movzwq (%rax), %rdi
+
+movslq %eax, %rdi
+movslq (%rax), %rdi
+
+mulb %dil
+mulb (%rax)
+mulw %si
+mulw (%rax)
+mull %edx
+mull (%rax)
+mulq %rcx
+mulq (%rax)
+
+negb %dil
+negb (%r8)
+lock negb (%r8)
+negw %si
+negw (%r9)
+lock negw (%r9)
+negl %edx
+negl (%rax)
+lock negl (%rax)
+negq %rcx
+negq (%r10)
+lock negq (%r10)
+
+nop
+nopw %di
+nopw (%rcx)
+nopl %esi
+nopl (%r8)
+nopq %rdx
+nopq (%r9)
+
+notb %dil
+notb (%r8)
+lock notb (%r8)
+notw %si
+notw (%r9)
+lock notw (%r9)
+notl %edx
+notl (%rax)
+lock notl (%rax)
+notq %rcx
+notq (%r10)
+lock notq (%r10)
+
+orb $7, %al
+orb $7, %dil
+orb $7, (%rax)
+lock orb $7, (%rax)
+orb %sil, %dil
+orb %sil, (%rax)
+lock orb %sil, (%rax)
+orb (%rax), %dil
+
+orw $511, %ax
+orw $511, %di
+orw $511, (%rax)
+lock orw $511, (%rax)
+orw $7, %di
+orw $7, (%rax)
+lock orw $7, (%rax)
+orw %si, %di
+orw %si, (%rax)
+lock orw %si, (%rax)
+orw (%rax), %di
+
+orl $665536, %eax
+orl $665536, %edi
+orl $665536, (%rax)
+lock orl $665536, (%rax)
+orl $7, %edi
+orl $7, (%rax)
+lock orl $7, (%rax)
+orl %esi, %edi
+orl %esi, (%rax)
+lock orl %esi, (%rax)
+orl (%rax), %edi
+
+orq $665536, %rax
+orq $665536, %rdi
+orq $665536, (%rax)
+lock orq $665536, (%rax)
+orq $7, %rdi
+orq $7, (%rax)
+lock orq $7, (%rax)
+orq %rsi, %rdi
+orq %rsi, (%rax)
+lock orq %rsi, (%rax)
+orq (%rax), %rdi
+
+outb %al, $7
+outb %al, %dx
+outw %ax, $7
+outw %ax, %dx
+outl %eax, $7
+outl %eax, %dx
+
+outsb
+outsw
+outsl
+
+pause
+
+rclb %dil
+rcrb %dil
+rclb (%rax)
+rcrb (%rax)
+rclb $7, %dil
+rcrb $7, %dil
+rclb $7, (%rax)
+rcrb $7, (%rax)
+rclb %cl, %dil
+rcrb %cl, %dil
+rclb %cl, (%rax)
+rcrb %cl, (%rax)
+
+rclw %di
+rcrw %di
+rclw (%rax)
+rcrw (%rax)
+rclw $7, %di
+rcrw $7, %di
+rclw $7, (%rax)
+rcrw $7, (%rax)
+rclw %cl, %di
+rcrw %cl, %di
+rclw %cl, (%rax)
+rcrw %cl, (%rax)
+
+rcll %edi
+rcrl %edi
+rcll (%rax)
+rcrl (%rax)
+rcll $7, %edi
+rcrl $7, %edi
+rcll $7, (%rax)
+rcrl $7, (%rax)
+rcll %cl, %edi
+rcrl %cl, %edi
+rcll %cl, (%rax)
+rcrl %cl, (%rax)
+
+rclq %rdi
+rcrq %rdi
+rclq (%rax)
+rcrq (%rax)
+rclq $7, %rdi
+rcrq $7, %rdi
+rclq $7, (%rax)
+rcrq $7, (%rax)
+rclq %cl, %rdi
+rcrq %cl, %rdi
+rclq %cl, (%rax)
+rcrq %cl, (%rax)
+
+rdmsr
+rdpmc
+rdtsc
+rdtscp
+
+rolb %dil
+rorb %dil
+rolb (%rax)
+rorb (%rax)
+rolb $7, %dil
+rorb $7, %dil
+rolb $7, (%rax)
+rorb $7, (%rax)
+rolb %cl, %dil
+rorb %cl, %dil
+rolb %cl, (%rax)
+rorb %cl, (%rax)
+
+rolw %di
+rorw %di
+rolw (%rax)
+rorw (%rax)
+rolw $7, %di
+rorw $7, %di
+rolw $7, (%rax)
+rorw $7, (%rax)
+rolw %cl, %di
+rorw %cl, %di
+rolw %cl, (%rax)
+rorw %cl, (%rax)
+
+roll %edi
+rorl %edi
+roll (%rax)
+rorl (%rax)
+roll $7, %edi
+rorl $7, %edi
+roll $7, (%rax)
+rorl $7, (%rax)
+roll %cl, %edi
+rorl %cl, %edi
+roll %cl, (%rax)
+rorl %cl, (%rax)
+
+rolq %rdi
+rorq %rdi
+rolq (%rax)
+rorq (%rax)
+rolq $7, %rdi
+rorq $7, %rdi
+rolq $7, (%rax)
+rorq $7, (%rax)
+rolq %cl, %rdi
+rorq %cl, %rdi
+rolq %cl, (%rax)
+rorq %cl, (%rax)
+
+sahf
+
+sarb %dil
+shlb %dil
+shrb %dil
+sarb (%rax)
+shlb (%rax)
+shrb (%rax)
+sarb $7, %dil
+shlb $7, %dil
+shrb $7, %dil
+sarb $7, (%rax)
+shlb $7, (%rax)
+shrb $7, (%rax)
+sarb %cl, %dil
+shlb %cl, %dil
+shrb %cl, %dil
+sarb %cl, (%rax)
+shlb %cl, (%rax)
+shrb %cl, (%rax)
+
+sarw %di
+shlw %di
+shrw %di
+sarw (%rax)
+shlw (%rax)
+shrw (%rax)
+sarw $7, %di
+shlw $7, %di
+shrw $7, %di
+sarw $7, (%rax)
+shlw $7, (%rax)
+shrw $7, (%rax)
+sarw %cl, %di
+shlw %cl, %di
+shrw %cl, %di
+sarw %cl, (%rax)
+shlw %cl, (%rax)
+shrw %cl, (%rax)
+
+sarl %edi
+shll %edi
+shrl %edi
+sarl (%rax)
+shll (%rax)
+shrl (%rax)
+sarl $7, %edi
+shll $7, %edi
+shrl $7, %edi
+sarl $7, (%rax)
+shll $7, (%rax)
+shrl $7, (%rax)
+sarl %cl, %edi
+shll %cl, %edi
+shrl %cl, %edi
+sarl %cl, (%rax)
+shll %cl, (%rax)
+shrl %cl, (%rax)
+
+sarq %rdi
+shlq %rdi
+shrq %rdi
+sarq (%rax)
+shlq (%rax)
+shrq (%rax)
+sarq $7, %rdi
+shlq $7, %rdi
+shrq $7, %rdi
+sarq $7, (%rax)
+shlq $7, (%rax)
+shrq $7, (%rax)
+sarq %cl, %rdi
+shlq %cl, %rdi
+shrq %cl, %rdi
+sarq %cl, (%rax)
+shlq %cl, (%rax)
+shrq %cl, (%rax)
+
+sbbb $0, %al
+sbbb $0, %dil
+sbbb $0, (%rax)
+lock sbbb $0, (%rax)
+sbbb $7, %al
+sbbb $7, %dil
+sbbb $7, (%rax)
+lock sbbb $7, (%rax)
+sbbb %sil, %dil
+sbbb %sil, (%rax)
+lock sbbb %sil, (%rax)
+sbbb (%rax), %dil
+
+sbbw $0, %ax
+sbbw $0, %di
+sbbw $0, (%rax)
+lock sbbw $0, (%rax)
+sbbw $511, %ax
+sbbw $511, %di
+sbbw $511, (%rax)
+lock sbbw $511, (%rax)
+sbbw $7, %di
+sbbw $7, (%rax)
+lock sbbw $7, (%rax)
+sbbw %si, %di
+sbbw %si, (%rax)
+lock sbbw %si, (%rax)
+sbbw (%rax), %di
+
+sbbl $0, %eax
+sbbl $0, %edi
+sbbl $0, (%rax)
+lock sbbl $0, (%rax)
+sbbl $665536, %eax
+sbbl $665536, %edi
+sbbl $665536, (%rax)
+lock sbbl $665536, (%rax)
+sbbl $7, %edi
+sbbl $7, (%rax)
+lock sbbl $7, (%rax)
+sbbl %esi, %edi
+sbbl %esi, (%rax)
+lock sbbl %esi, (%rax)
+sbbl (%rax), %edi
+
+sbbq $0, %rax
+sbbq $0, %rdi
+sbbq $0, (%rax)
+lock sbbq $0, (%rax)
+sbbq $665536, %rax
+sbbq $665536, %rdi
+sbbq $665536, (%rax)
+lock sbbq $665536, (%rax)
+sbbq $7, %rdi
+sbbq $7, (%rax)
+lock sbbq $7, (%rax)
+sbbq %rsi, %rdi
+sbbq %rsi, (%rax)
+lock sbbq %rsi, (%rax)
+sbbq (%rax), %rdi
+
+scasb
+scasw
+scasl
+scasq
+
+seto %al
+seto (%rax)
+setno %al
+setno (%rax)
+setb %al
+setb (%rax)
+setnb %al
+setnb (%rax)
+setz %al
+setz (%rax)
+setnz %al
+setnz (%rax)
+seta %al
+seta (%rax)
+setna %al
+setna (%rax)
+sets %al
+sets (%rax)
+setns %al
+setns (%rax)
+setp %al
+setp (%rax)
+setnp %al
+setnp (%rax)
+setl %al
+setl (%rax)
+setnl %al
+setnl (%rax)
+setg %al
+setg (%rax)
+setng %al
+setng (%rax)
+
+shldw %cl, %si, %di
+shrdw %cl, %si, %di
+shldw %cl, %si, (%rax)
+shrdw %cl, %si, (%rax)
+shldw $7, %si, %di
+shrdw $7, %si, %di
+shldw $7, %si, (%rax)
+shrdw $7, %si, (%rax)
+
+shldl %cl, %esi, %edi
+shrdl %cl, %esi, %edi
+shldl %cl, %esi, (%rax)
+shrdl %cl, %esi, (%rax)
+shldl $7, %esi, %edi
+shrdl $7, %esi, %edi
+shldl $7, %esi, (%rax)
+shrdl $7, %esi, (%rax)
+
+shldq %cl, %rsi, %rdi
+shrdq %cl, %rsi, %rdi
+shldq %cl, %rsi, (%rax)
+shrdq %cl, %rsi, (%rax)
+shldq $7, %rsi, %rdi
+shrdq $7, %rsi, %rdi
+shldq $7, %rsi, (%rax)
+shrdq $7, %rsi, (%rax)
+
+stc
+std
+
+stosb
+stosw
+stosl
+stosq
+
+subb $7, %al
+subb $7, %dil
+subb $7, (%rax)
+lock subb $7, (%rax)
+subb %sil, %dil
+subb %sil, (%rax)
+lock subb %sil, (%rax)
+subb (%rax), %dil
+
+subw $511, %ax
+subw $511, %di
+subw $511, (%rax)
+lock subw $511, (%rax)
+subw $7, %di
+subw $7, (%rax)
+lock subw $7, (%rax)
+subw %si, %di
+subw %si, (%rax)
+lock subw %si, (%rax)
+subw (%rax), %di
+
+subl $665536, %eax
+subl $665536, %edi
+subl $665536, (%rax)
+lock subl $665536, (%rax)
+subl $7, %edi
+subl $7, (%rax)
+lock subl $7, (%rax)
+subl %esi, %edi
+subl %esi, (%rax)
+lock subl %esi, (%rax)
+subl (%rax), %edi
+
+subq $665536, %rax
+subq $665536, %rdi
+subq $665536, (%rax)
+lock subq $665536, (%rax)
+subq $7, %rdi
+subq $7, (%rax)
+lock subq $7, (%rax)
+subq %rsi, %rdi
+subq %rsi, (%rax)
+lock subq %rsi, (%rax)
+subq (%rax), %rdi
+
+testb $7, %al
+testb $7, %dil
+testb $7, (%rax)
+testb %sil, %dil
+testb %sil, (%rax)
+
+testw $511, %ax
+testw $511, %di
+testw $511, (%rax)
+testw $7, %di
+testw $7, (%rax)
+testw %si, %di
+testw %si, (%rax)
+
+testl $665536, %eax
+testl $665536, %edi
+testl $665536, (%rax)
+testl $7, %edi
+testl $7, (%rax)
+testl %esi, %edi
+testl %esi, (%rax)
+
+testq $665536, %rax
+testq $665536, %rdi
+testq $665536, (%rax)
+testq $7, %rdi
+testq $7, (%rax)
+testq %rsi, %rdi
+testq %rsi, (%rax)
+
+ud2
+
+wrmsr
+
+xaddb %bl, %cl
+xaddb %bl, (%rcx)
+lock xaddb %bl, (%rcx)
+
+xaddw %bx, %cx
+xaddw %ax, (%rbx)
+lock xaddw %ax, (%rbx)
+
+xaddl %ebx, %ecx
+xaddl %eax, (%rbx)
+lock xaddl %eax, (%rbx)
+
+xaddq %rbx, %rcx
+xaddq %rax, (%rbx)
+lock xaddq %rax, (%rbx)
+
+xchgb %bl, %cl
+xchgb %bl, (%rbx)
+lock xchgb %bl, (%rbx)
+
+xchgw %ax, %bx
+xchgw %bx, %cx
+xchgw %ax, (%rbx)
+lock xchgw %ax, (%rbx)
+
+xchgl %eax, %ebx
+xchgl %ebx, %ecx
+xchgl %eax, (%rbx)
+lock xchgl %eax, (%rbx)
+
+xchgq %rax, %rbx
+xchgq %rbx, %rcx
+xchgq %rax, (%rbx)
+lock xchgq %rax, (%rbx)
+
+xlatb
+
+xorb $7, %al
+xorb $7, %dil
+xorb $7, (%rax)
+lock xorb $7, (%rax)
+xorb %sil, %dil
+xorb %sil, (%rax)
+lock xorb %sil, (%rax)
+xorb (%rax), %dil
+
+xorw $511, %ax
+xorw $511, %di
+xorw $511, (%rax)
+lock xorw $511, (%rax)
+xorw $7, %di
+xorw $7, (%rax)
+lock xorw $7, (%rax)
+xorw %si, %di
+xorw %si, (%rax)
+lock xorw %si, (%rax)
+xorw (%rax), %di
+
+xorl $665536, %eax
+xorl $665536, %edi
+xorl $665536, (%rax)
+lock xorl $665536, (%rax)
+xorl $7, %edi
+xorl $7, (%rax)
+lock xorl $7, (%rax)
+xorl %esi, %edi
+xorl %esi, (%rax)
+lock xorl %esi, (%rax)
+xorl (%rax), %edi
+
+xorq $665536, %rax
+xorq $665536, %rdi
+xorq $665536, (%rax)
+lock xorq $665536, (%rax)
+xorq $7, %rdi
+xorq $7, (%rax)
+lock xorq $7, (%rax)
+xorq %rsi, %rdi
+xorq %rsi, (%rax)
+lock xorq %rsi, (%rax)
+xorq (%rax), %rdi
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.25 adcb $0, %al
+# CHECK-NEXT: 1 1 0.25 adcb $0, %dil
+# CHECK-NEXT: 1 6 0.67 * * adcb $0, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock adcb $0, (%rax)
+# CHECK-NEXT: 1 1 0.25 adcb $7, %al
+# CHECK-NEXT: 1 1 0.25 adcb $7, %dil
+# CHECK-NEXT: 1 6 0.67 * * adcb $7, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock adcb $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 adcb %sil, %dil
+# CHECK-NEXT: 1 6 0.67 * * adcb %sil, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock adcb %sil, (%rax)
+# CHECK-NEXT: 1 5 0.33 * adcb (%rax), %dil
+# CHECK-NEXT: 1 1 0.25 adcw $0, %ax
+# CHECK-NEXT: 1 1 0.25 adcw $0, %di
+# CHECK-NEXT: 1 6 0.67 * * adcw $0, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock adcw $0, (%rax)
+# CHECK-NEXT: 1 1 0.25 adcw $511, %ax
+# CHECK-NEXT: 1 1 0.25 adcw $511, %di
+# CHECK-NEXT: 1 6 0.67 * * adcw $511, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock adcw $511, (%rax)
+# CHECK-NEXT: 1 1 0.25 adcw $7, %di
+# CHECK-NEXT: 1 6 0.67 * * adcw $7, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock adcw $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 adcw %si, %di
+# CHECK-NEXT: 1 6 0.67 * * adcw %si, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock adcw %si, (%rax)
+# CHECK-NEXT: 1 5 0.33 * adcw (%rax), %di
+# CHECK-NEXT: 1 1 0.25 adcl $0, %eax
+# CHECK-NEXT: 1 1 0.25 adcl $0, %edi
+# CHECK-NEXT: 1 6 0.67 * * adcl $0, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock adcl $0, (%rax)
+# CHECK-NEXT: 1 1 0.25 adcl $665536, %eax
+# CHECK-NEXT: 1 1 0.25 adcl $665536, %edi
+# CHECK-NEXT: 1 6 0.67 * * adcl $665536, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock adcl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.25 adcl $7, %edi
+# CHECK-NEXT: 1 6 0.67 * * adcl $7, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock adcl $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 adcl %esi, %edi
+# CHECK-NEXT: 1 6 0.67 * * adcl %esi, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock adcl %esi, (%rax)
+# CHECK-NEXT: 1 5 0.33 * adcl (%rax), %edi
+# CHECK-NEXT: 1 1 0.25 adcq $0, %rax
+# CHECK-NEXT: 1 1 0.25 adcq $0, %rdi
+# CHECK-NEXT: 1 6 0.67 * * adcq $0, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock adcq $0, (%rax)
+# CHECK-NEXT: 1 1 0.25 adcq $665536, %rax
+# CHECK-NEXT: 1 1 0.25 adcq $665536, %rdi
+# CHECK-NEXT: 1 6 0.67 * * adcq $665536, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock adcq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.25 adcq $7, %rdi
+# CHECK-NEXT: 1 6 0.67 * * adcq $7, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock adcq $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 adcq %rsi, %rdi
+# CHECK-NEXT: 1 6 0.67 * * adcq %rsi, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock adcq %rsi, (%rax)
+# CHECK-NEXT: 1 5 0.33 * adcq (%rax), %rdi
+# CHECK-NEXT: 1 1 0.25 addb $7, %al
+# CHECK-NEXT: 1 1 0.25 addb $7, %dil
+# CHECK-NEXT: 1 6 0.67 * * addb $7, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock addb $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 addb %sil, %dil
+# CHECK-NEXT: 1 6 0.67 * * addb %sil, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock addb %sil, (%rax)
+# CHECK-NEXT: 1 5 0.33 * addb (%rax), %dil
+# CHECK-NEXT: 1 1 0.25 addw $511, %ax
+# CHECK-NEXT: 1 1 0.25 addw $511, %di
+# CHECK-NEXT: 1 6 0.67 * * addw $511, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock addw $511, (%rax)
+# CHECK-NEXT: 1 1 0.25 addw $7, %di
+# CHECK-NEXT: 1 6 0.67 * * addw $7, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock addw $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 addw %si, %di
+# CHECK-NEXT: 1 6 0.67 * * addw %si, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock addw %si, (%rax)
+# CHECK-NEXT: 1 5 0.33 * addw (%rax), %di
+# CHECK-NEXT: 1 1 0.25 addl $665536, %eax
+# CHECK-NEXT: 1 1 0.25 addl $665536, %edi
+# CHECK-NEXT: 1 6 0.67 * * addl $665536, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock addl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.25 addl $7, %edi
+# CHECK-NEXT: 1 6 0.67 * * addl $7, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock addl $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 addl %esi, %edi
+# CHECK-NEXT: 1 6 0.67 * * addl %esi, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock addl %esi, (%rax)
+# CHECK-NEXT: 1 5 0.33 * addl (%rax), %edi
+# CHECK-NEXT: 1 1 0.25 addq $665536, %rax
+# CHECK-NEXT: 1 1 0.25 addq $665536, %rdi
+# CHECK-NEXT: 1 6 0.67 * * addq $665536, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock addq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.25 addq $7, %rdi
+# CHECK-NEXT: 1 6 0.67 * * addq $7, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock addq $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 addq %rsi, %rdi
+# CHECK-NEXT: 1 6 0.67 * * addq %rsi, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock addq %rsi, (%rax)
+# CHECK-NEXT: 1 5 0.33 * addq (%rax), %rdi
+# CHECK-NEXT: 1 1 0.25 andb $7, %al
+# CHECK-NEXT: 1 1 0.25 andb $7, %dil
+# CHECK-NEXT: 1 6 0.67 * * andb $7, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock andb $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 andb %sil, %dil
+# CHECK-NEXT: 1 6 0.67 * * andb %sil, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock andb %sil, (%rax)
+# CHECK-NEXT: 1 5 0.33 * andb (%rax), %dil
+# CHECK-NEXT: 1 1 0.25 andw $511, %ax
+# CHECK-NEXT: 1 1 0.25 andw $511, %di
+# CHECK-NEXT: 1 6 0.67 * * andw $511, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock andw $511, (%rax)
+# CHECK-NEXT: 1 1 0.25 andw $7, %di
+# CHECK-NEXT: 1 6 0.67 * * andw $7, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock andw $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 andw %si, %di
+# CHECK-NEXT: 1 6 0.67 * * andw %si, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock andw %si, (%rax)
+# CHECK-NEXT: 1 5 0.33 * andw (%rax), %di
+# CHECK-NEXT: 1 1 0.25 andl $665536, %eax
+# CHECK-NEXT: 1 1 0.25 andl $665536, %edi
+# CHECK-NEXT: 1 6 0.67 * * andl $665536, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock andl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.25 andl $7, %edi
+# CHECK-NEXT: 1 6 0.67 * * andl $7, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock andl $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 andl %esi, %edi
+# CHECK-NEXT: 1 6 0.67 * * andl %esi, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock andl %esi, (%rax)
+# CHECK-NEXT: 1 5 0.33 * andl (%rax), %edi
+# CHECK-NEXT: 1 1 0.25 andq $665536, %rax
+# CHECK-NEXT: 1 1 0.25 andq $665536, %rdi
+# CHECK-NEXT: 1 6 0.67 * * andq $665536, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock andq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.25 andq $7, %rdi
+# CHECK-NEXT: 1 6 0.67 * * andq $7, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock andq $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 andq %rsi, %rdi
+# CHECK-NEXT: 1 6 0.67 * * andq %rsi, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock andq %rsi, (%rax)
+# CHECK-NEXT: 1 5 0.33 * andq (%rax), %rdi
+# CHECK-NEXT: 6 3 3.00 bsfw %si, %di
+# CHECK-NEXT: 6 4 4.00 bsrw %si, %di
+# CHECK-NEXT: 4 7 3.00 * bsfw (%rax), %di
+# CHECK-NEXT: 3 8 4.00 * bsrw (%rax), %di
+# CHECK-NEXT: 6 3 3.00 bsfl %esi, %edi
+# CHECK-NEXT: 6 4 4.00 bsrl %esi, %edi
+# CHECK-NEXT: 4 7 3.00 * bsfl (%rax), %edi
+# CHECK-NEXT: 3 8 4.00 * bsrl (%rax), %edi
+# CHECK-NEXT: 6 3 3.00 bsfq %rsi, %rdi
+# CHECK-NEXT: 6 4 4.00 bsrq %rsi, %rdi
+# CHECK-NEXT: 4 7 3.00 * bsfq (%rax), %rdi
+# CHECK-NEXT: 3 8 4.00 * bsrq (%rax), %rdi
+# CHECK-NEXT: 1 1 0.25 bswapl %eax
+# CHECK-NEXT: 1 1 0.25 bswapq %rax
+# CHECK-NEXT: 1 1 0.25 btw %si, %di
+# CHECK-NEXT: 2 2 0.25 btcw %si, %di
+# CHECK-NEXT: 2 2 0.25 btrw %si, %di
+# CHECK-NEXT: 2 2 0.25 btsw %si, %di
+# CHECK-NEXT: 6 5 0.33 * btw %si, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * btcw %si, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * btrw %si, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * btsw %si, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * lock btcw %si, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * lock btrw %si, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * lock btsw %si, (%rax)
+# CHECK-NEXT: 1 1 0.25 btw $7, %di
+# CHECK-NEXT: 2 2 0.25 btcw $7, %di
+# CHECK-NEXT: 2 2 0.25 btrw $7, %di
+# CHECK-NEXT: 2 2 0.25 btsw $7, %di
+# CHECK-NEXT: 2 5 0.33 * btw $7, (%rax)
+# CHECK-NEXT: 4 7 0.67 * * btcw $7, (%rax)
+# CHECK-NEXT: 4 7 0.67 * * btrw $7, (%rax)
+# CHECK-NEXT: 4 7 0.67 * * btsw $7, (%rax)
+# CHECK-NEXT: 4 7 0.67 * * lock btcw $7, (%rax)
+# CHECK-NEXT: 4 7 0.67 * * lock btrw $7, (%rax)
+# CHECK-NEXT: 4 7 0.67 * * lock btsw $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 btl %esi, %edi
+# CHECK-NEXT: 2 2 0.25 btcl %esi, %edi
+# CHECK-NEXT: 2 2 0.25 btrl %esi, %edi
+# CHECK-NEXT: 2 2 0.25 btsl %esi, %edi
+# CHECK-NEXT: 6 5 0.33 * btl %esi, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * btcl %esi, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * btrl %esi, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * btsl %esi, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * lock btcl %esi, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * lock btrl %esi, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * lock btsl %esi, (%rax)
+# CHECK-NEXT: 1 1 0.25 btl $7, %edi
+# CHECK-NEXT: 2 2 0.25 btcl $7, %edi
+# CHECK-NEXT: 2 2 0.25 btrl $7, %edi
+# CHECK-NEXT: 2 2 0.25 btsl $7, %edi
+# CHECK-NEXT: 2 5 0.33 * btl $7, (%rax)
+# CHECK-NEXT: 4 7 0.67 * * btcl $7, (%rax)
+# CHECK-NEXT: 4 7 0.67 * * btrl $7, (%rax)
+# CHECK-NEXT: 4 7 0.67 * * btsl $7, (%rax)
+# CHECK-NEXT: 4 7 0.67 * * lock btcl $7, (%rax)
+# CHECK-NEXT: 4 7 0.67 * * lock btrl $7, (%rax)
+# CHECK-NEXT: 4 7 0.67 * * lock btsl $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 btq %rsi, %rdi
+# CHECK-NEXT: 2 2 0.25 btcq %rsi, %rdi
+# CHECK-NEXT: 2 2 0.25 btrq %rsi, %rdi
+# CHECK-NEXT: 2 2 0.25 btsq %rsi, %rdi
+# CHECK-NEXT: 6 5 0.33 * btq %rsi, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * btcq %rsi, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * btrq %rsi, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * btsq %rsi, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * lock btcq %rsi, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * lock btrq %rsi, (%rax)
+# CHECK-NEXT: 8 7 0.67 * * lock btsq %rsi, (%rax)
+# CHECK-NEXT: 1 1 0.25 btq $7, %rdi
+# CHECK-NEXT: 2 2 0.25 btcq $7, %rdi
+# CHECK-NEXT: 2 2 0.25 btrq $7, %rdi
+# CHECK-NEXT: 2 2 0.25 btsq $7, %rdi
+# CHECK-NEXT: 2 5 0.33 * btq $7, (%rax)
+# CHECK-NEXT: 4 7 0.67 * * btcq $7, (%rax)
+# CHECK-NEXT: 4 7 0.67 * * btrq $7, (%rax)
+# CHECK-NEXT: 4 7 0.67 * * btsq $7, (%rax)
+# CHECK-NEXT: 4 7 0.67 * * lock btcq $7, (%rax)
+# CHECK-NEXT: 4 7 0.67 * * lock btrq $7, (%rax)
+# CHECK-NEXT: 4 7 0.67 * * lock btsq $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 cbtw
+# CHECK-NEXT: 1 1 0.25 cwtl
+# CHECK-NEXT: 1 1 0.25 cltq
+# CHECK-NEXT: 1 1 0.25 cwtd
+# CHECK-NEXT: 1 1 0.25 cltd
+# CHECK-NEXT: 1 1 0.25 cqto
+# CHECK-NEXT: 1 1 0.25 U clc
+# CHECK-NEXT: 1 1 0.25 U cld
+# CHECK-NEXT: 1 1 0.25 U cmc
+# CHECK-NEXT: 1 1 0.25 cmpb $7, %al
+# CHECK-NEXT: 1 1 0.25 cmpb $7, %dil
+# CHECK-NEXT: 1 5 0.33 * cmpb $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 cmpb %sil, %dil
+# CHECK-NEXT: 1 5 0.33 * cmpb %sil, (%rax)
+# CHECK-NEXT: 1 5 0.33 * cmpb (%rax), %dil
+# CHECK-NEXT: 1 1 0.25 cmpw $511, %ax
+# CHECK-NEXT: 1 1 0.25 cmpw $511, %di
+# CHECK-NEXT: 1 5 0.33 * cmpw $511, (%rax)
+# CHECK-NEXT: 1 1 0.25 cmpw $7, %di
+# CHECK-NEXT: 1 5 0.33 * cmpw $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 cmpw %si, %di
+# CHECK-NEXT: 1 5 0.33 * cmpw %si, (%rax)
+# CHECK-NEXT: 1 5 0.33 * cmpw (%rax), %di
+# CHECK-NEXT: 1 1 0.25 cmpl $665536, %eax
+# CHECK-NEXT: 1 1 0.25 cmpl $665536, %edi
+# CHECK-NEXT: 1 5 0.33 * cmpl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.25 cmpl $7, %edi
+# CHECK-NEXT: 1 5 0.33 * cmpl $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 cmpl %esi, %edi
+# CHECK-NEXT: 1 5 0.33 * cmpl %esi, (%rax)
+# CHECK-NEXT: 1 5 0.33 * cmpl (%rax), %edi
+# CHECK-NEXT: 1 1 0.25 cmpq $665536, %rax
+# CHECK-NEXT: 1 1 0.25 cmpq $665536, %rdi
+# CHECK-NEXT: 1 5 0.33 * cmpq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.25 cmpq $7, %rdi
+# CHECK-NEXT: 1 5 0.33 * cmpq $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 cmpq %rsi, %rdi
+# CHECK-NEXT: 1 5 0.33 * cmpq %rsi, (%rax)
+# CHECK-NEXT: 1 5 0.33 * cmpq (%rax), %rdi
+# CHECK-NEXT: 1 100 0.25 U cmpsb %es:(%rdi), (%rsi)
+# CHECK-NEXT: 1 100 0.25 U cmpsw %es:(%rdi), (%rsi)
+# CHECK-NEXT: 1 100 0.25 U cmpsl %es:(%rdi), (%rsi)
+# CHECK-NEXT: 1 100 0.25 U cmpsq %es:(%rdi), (%rsi)
+# CHECK-NEXT: 3 3 3.00 cmpxchgb %cl, %bl
+# CHECK-NEXT: 5 4 3.00 * * cmpxchgb %cl, (%rbx)
+# CHECK-NEXT: 5 4 3.00 * * lock cmpxchgb %cl, (%rbx)
+# CHECK-NEXT: 5 3 3.00 cmpxchgw %cx, %bx
+# CHECK-NEXT: 6 3 3.00 * * cmpxchgw %cx, (%rbx)
+# CHECK-NEXT: 6 3 3.00 * * lock cmpxchgw %cx, (%rbx)
+# CHECK-NEXT: 5 3 3.00 cmpxchgl %ecx, %ebx
+# CHECK-NEXT: 6 3 3.00 * * cmpxchgl %ecx, (%rbx)
+# CHECK-NEXT: 6 3 3.00 * * lock cmpxchgl %ecx, (%rbx)
+# CHECK-NEXT: 5 3 3.00 cmpxchgq %rcx, %rbx
+# CHECK-NEXT: 6 3 3.00 * * cmpxchgq %rcx, (%rbx)
+# CHECK-NEXT: 6 3 3.00 * * lock cmpxchgq %rcx, (%rbx)
+# CHECK-NEXT: 1 100 0.25 U cpuid
+# CHECK-NEXT: 1 1 0.25 decb %dil
+# CHECK-NEXT: 1 6 0.67 * * decb (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock decb (%rax)
+# CHECK-NEXT: 1 1 0.25 decw %di
+# CHECK-NEXT: 1 6 0.67 * * decw (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock decw (%rax)
+# CHECK-NEXT: 1 1 0.25 decl %edi
+# CHECK-NEXT: 1 6 0.67 * * decl (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock decl (%rax)
+# CHECK-NEXT: 1 1 0.25 decq %rdi
+# CHECK-NEXT: 1 6 0.67 * * decq (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock decq (%rax)
+# CHECK-NEXT: 2 9 4.00 U divb %dil
+# CHECK-NEXT: 2 13 4.00 * U divb (%rax)
+# CHECK-NEXT: 2 10 4.00 U divw %si
+# CHECK-NEXT: 2 14 4.00 * U divw (%rax)
+# CHECK-NEXT: 2 12 7.00 U divl %edx
+# CHECK-NEXT: 2 16 7.00 * U divl (%rax)
+# CHECK-NEXT: 2 18 10.00 U divq %rcx
+# CHECK-NEXT: 2 22 10.00 * U divq (%rax)
+# CHECK-NEXT: 1 100 0.25 U enter $7, $4095
+# CHECK-NEXT: 2 9 4.00 U idivb %dil
+# CHECK-NEXT: 2 13 4.00 * U idivb (%rax)
+# CHECK-NEXT: 2 10 4.00 U idivw %si
+# CHECK-NEXT: 2 14 4.00 * U idivw (%rax)
+# CHECK-NEXT: 2 12 7.00 U idivl %edx
+# CHECK-NEXT: 2 16 7.00 * U idivl (%rax)
+# CHECK-NEXT: 2 18 10.00 U idivq %rcx
+# CHECK-NEXT: 2 22 10.00 * U idivq (%rax)
+# CHECK-NEXT: 1 3 3.00 imulb %dil
+# CHECK-NEXT: 1 7 3.00 * imulb (%rax)
+# CHECK-NEXT: 1 3 3.00 imulw %di
+# CHECK-NEXT: 1 7 3.00 * imulw (%rax)
+# CHECK-NEXT: 1 3 1.00 imulw %si, %di
+# CHECK-NEXT: 1 7 1.00 * imulw (%rax), %di
+# CHECK-NEXT: 2 4 3.00 imulw $511, %si, %di
+# CHECK-NEXT: 2 8 3.00 * imulw $511, (%rax), %di
+# CHECK-NEXT: 2 4 3.00 imulw $7, %si, %di
+# CHECK-NEXT: 2 8 3.00 * imulw $7, (%rax), %di
+# CHECK-NEXT: 1 3 3.00 imull %edi
+# CHECK-NEXT: 1 7 3.00 * imull (%rax)
+# CHECK-NEXT: 1 3 1.00 imull %esi, %edi
+# CHECK-NEXT: 1 7 1.00 * imull (%rax), %edi
+# CHECK-NEXT: 2 3 3.00 imull $665536, %esi, %edi
+# CHECK-NEXT: 2 7 3.00 * imull $665536, (%rax), %edi
+# CHECK-NEXT: 2 3 3.00 imull $7, %esi, %edi
+# CHECK-NEXT: 2 7 3.00 * imull $7, (%rax), %edi
+# CHECK-NEXT: 1 3 4.00 imulq %rdi
+# CHECK-NEXT: 1 7 4.00 * imulq (%rax)
+# CHECK-NEXT: 1 3 1.00 imulq %rsi, %rdi
+# CHECK-NEXT: 1 7 1.00 * imulq (%rax), %rdi
+# CHECK-NEXT: 2 3 4.00 imulq $665536, %rsi, %rdi
+# CHECK-NEXT: 2 7 4.00 * imulq $665536, (%rax), %rdi
+# CHECK-NEXT: 2 3 4.00 imulq $7, %rsi, %rdi
+# CHECK-NEXT: 2 7 4.00 * imulq $7, (%rax), %rdi
+# CHECK-NEXT: 1 100 0.25 U inb $7, %al
+# CHECK-NEXT: 1 100 0.25 U inb %dx, %al
+# CHECK-NEXT: 1 100 0.25 U inw $7, %ax
+# CHECK-NEXT: 1 100 0.25 U inw %dx, %ax
+# CHECK-NEXT: 1 100 0.25 U inl $7, %eax
+# CHECK-NEXT: 1 100 0.25 U inl %dx, %eax
+# CHECK-NEXT: 1 1 0.25 incb %dil
+# CHECK-NEXT: 1 6 0.67 * * incb (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock incb (%rax)
+# CHECK-NEXT: 1 1 0.25 incw %di
+# CHECK-NEXT: 1 6 0.67 * * incw (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock incw (%rax)
+# CHECK-NEXT: 1 1 0.25 incl %edi
+# CHECK-NEXT: 1 6 0.67 * * incl (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock incl (%rax)
+# CHECK-NEXT: 1 1 0.25 incq %rdi
+# CHECK-NEXT: 1 6 0.67 * * incq (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock incq (%rax)
+# CHECK-NEXT: 1 100 0.25 U insb %dx, %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 U insw %dx, %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 U insl %dx, %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 * * U int $7
+# CHECK-NEXT: 1 100 0.25 U invlpg (%rax)
+# CHECK-NEXT: 1 100 0.25 U invlpga
+# CHECK-NEXT: 4 2 0.50 lahf
+# CHECK-NEXT: 1 1 0.25 * leave
+# CHECK-NEXT: 1 100 0.25 U lodsb (%rsi), %al
+# CHECK-NEXT: 1 100 0.25 U lodsw (%rsi), %ax
+# CHECK-NEXT: 1 100 0.25 U lodsl (%rsi), %eax
+# CHECK-NEXT: 1 100 0.25 U lodsq (%rsi), %rax
+# CHECK-NEXT: 1 1 0.25 U loop 0
+# CHECK-NEXT: 1 1 0.25 U loope 0
+# CHECK-NEXT: 1 1 0.25 U loopne 0
+# CHECK-NEXT: 1 100 0.25 U movsb (%rsi), %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 U movsw (%rsi), %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 U movsl (%rsi), %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 U movsq (%rsi), %es:(%rdi)
+# CHECK-NEXT: 1 1 1.00 movsbw %al, %di
+# CHECK-NEXT: 1 1 1.00 movzbw %al, %di
+# CHECK-NEXT: 1 5 0.33 * movsbw (%rax), %di
+# CHECK-NEXT: 1 5 0.33 * movzbw (%rax), %di
+# CHECK-NEXT: 1 1 0.25 movsbl %al, %edi
+# CHECK-NEXT: 1 1 0.25 movzbl %al, %edi
+# CHECK-NEXT: 1 5 0.33 * movsbl (%rax), %edi
+# CHECK-NEXT: 1 5 0.33 * movzbl (%rax), %edi
+# CHECK-NEXT: 1 1 0.25 movsbq %al, %rdi
+# CHECK-NEXT: 1 1 0.25 movzbq %al, %rdi
+# CHECK-NEXT: 1 5 0.33 * movsbq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.33 * movzbq (%rax), %rdi
+# CHECK-NEXT: 1 1 0.25 movswl %ax, %edi
+# CHECK-NEXT: 1 1 0.25 movzwl %ax, %edi
+# CHECK-NEXT: 1 5 0.33 * movswl (%rax), %edi
+# CHECK-NEXT: 1 5 0.33 * movzwl (%rax), %edi
+# CHECK-NEXT: 1 1 0.25 movswq %ax, %rdi
+# CHECK-NEXT: 1 1 0.25 movzwq %ax, %rdi
+# CHECK-NEXT: 1 5 0.33 * movswq (%rax), %rdi
+# CHECK-NEXT: 1 5 0.33 * movzwq (%rax), %rdi
+# CHECK-NEXT: 1 1 0.25 movslq %eax, %rdi
+# CHECK-NEXT: 1 5 0.33 * movslq (%rax), %rdi
+# CHECK-NEXT: 1 3 3.00 mulb %dil
+# CHECK-NEXT: 1 7 3.00 * mulb (%rax)
+# CHECK-NEXT: 1 3 3.00 mulw %si
+# CHECK-NEXT: 1 7 3.00 * mulw (%rax)
+# CHECK-NEXT: 1 3 3.00 mull %edx
+# CHECK-NEXT: 1 7 3.00 * mull (%rax)
+# CHECK-NEXT: 1 3 4.00 mulq %rcx
+# CHECK-NEXT: 1 7 4.00 * mulq (%rax)
+# CHECK-NEXT: 1 1 0.25 negb %dil
+# CHECK-NEXT: 1 6 0.67 * * negb (%r8)
+# CHECK-NEXT: 1 6 0.67 * * lock negb (%r8)
+# CHECK-NEXT: 1 1 0.25 negw %si
+# CHECK-NEXT: 1 6 0.67 * * negw (%r9)
+# CHECK-NEXT: 1 6 0.67 * * lock negw (%r9)
+# CHECK-NEXT: 1 1 0.25 negl %edx
+# CHECK-NEXT: 1 6 0.67 * * negl (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock negl (%rax)
+# CHECK-NEXT: 1 1 0.25 negq %rcx
+# CHECK-NEXT: 1 6 0.67 * * negq (%r10)
+# CHECK-NEXT: 1 6 0.67 * * lock negq (%r10)
+# CHECK-NEXT: 1 1 0.25 nop
+# CHECK-NEXT: 1 1 0.25 nopw %di
+# CHECK-NEXT: 1 1 0.25 nopw (%rcx)
+# CHECK-NEXT: 1 1 0.25 nopl %esi
+# CHECK-NEXT: 1 1 0.25 nopl (%r8)
+# CHECK-NEXT: 1 1 0.25 nopq %rdx
+# CHECK-NEXT: 1 1 0.25 nopq (%r9)
+# CHECK-NEXT: 1 1 0.25 notb %dil
+# CHECK-NEXT: 1 6 0.67 * * notb (%r8)
+# CHECK-NEXT: 1 6 0.67 * * lock notb (%r8)
+# CHECK-NEXT: 1 1 0.25 notw %si
+# CHECK-NEXT: 1 6 0.67 * * notw (%r9)
+# CHECK-NEXT: 1 6 0.67 * * lock notw (%r9)
+# CHECK-NEXT: 1 1 0.25 notl %edx
+# CHECK-NEXT: 1 6 0.67 * * notl (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock notl (%rax)
+# CHECK-NEXT: 1 1 0.25 notq %rcx
+# CHECK-NEXT: 1 6 0.67 * * notq (%r10)
+# CHECK-NEXT: 1 6 0.67 * * lock notq (%r10)
+# CHECK-NEXT: 1 1 0.25 orb $7, %al
+# CHECK-NEXT: 1 1 0.25 orb $7, %dil
+# CHECK-NEXT: 1 6 0.67 * * orb $7, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock orb $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 orb %sil, %dil
+# CHECK-NEXT: 1 6 0.67 * * orb %sil, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock orb %sil, (%rax)
+# CHECK-NEXT: 1 5 0.33 * orb (%rax), %dil
+# CHECK-NEXT: 1 1 0.25 orw $511, %ax
+# CHECK-NEXT: 1 1 0.25 orw $511, %di
+# CHECK-NEXT: 1 6 0.67 * * orw $511, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock orw $511, (%rax)
+# CHECK-NEXT: 1 1 0.25 orw $7, %di
+# CHECK-NEXT: 1 6 0.67 * * orw $7, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock orw $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 orw %si, %di
+# CHECK-NEXT: 1 6 0.67 * * orw %si, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock orw %si, (%rax)
+# CHECK-NEXT: 1 5 0.33 * orw (%rax), %di
+# CHECK-NEXT: 1 1 0.25 orl $665536, %eax
+# CHECK-NEXT: 1 1 0.25 orl $665536, %edi
+# CHECK-NEXT: 1 6 0.67 * * orl $665536, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock orl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.25 orl $7, %edi
+# CHECK-NEXT: 1 6 0.67 * * orl $7, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock orl $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 orl %esi, %edi
+# CHECK-NEXT: 1 6 0.67 * * orl %esi, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock orl %esi, (%rax)
+# CHECK-NEXT: 1 5 0.33 * orl (%rax), %edi
+# CHECK-NEXT: 1 1 0.25 orq $665536, %rax
+# CHECK-NEXT: 1 1 0.25 orq $665536, %rdi
+# CHECK-NEXT: 1 6 0.67 * * orq $665536, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock orq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.25 orq $7, %rdi
+# CHECK-NEXT: 1 6 0.67 * * orq $7, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock orq $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 orq %rsi, %rdi
+# CHECK-NEXT: 1 6 0.67 * * orq %rsi, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock orq %rsi, (%rax)
+# CHECK-NEXT: 1 5 0.33 * orq (%rax), %rdi
+# CHECK-NEXT: 1 100 0.25 U outb %al, $7
+# CHECK-NEXT: 1 100 0.25 U outb %al, %dx
+# CHECK-NEXT: 1 100 0.25 U outw %ax, $7
+# CHECK-NEXT: 1 100 0.25 U outw %ax, %dx
+# CHECK-NEXT: 1 100 0.25 U outl %eax, $7
+# CHECK-NEXT: 1 100 0.25 U outl %eax, %dx
+# CHECK-NEXT: 1 100 0.25 U outsb (%rsi), %dx
+# CHECK-NEXT: 1 100 0.25 U outsw (%rsi), %dx
+# CHECK-NEXT: 1 100 0.25 U outsl (%rsi), %dx
+# CHECK-NEXT: 1 1 0.25 * * U pause
+# CHECK-NEXT: 1 1 0.25 rclb %dil
+# CHECK-NEXT: 1 1 0.25 rcrb %dil
+# CHECK-NEXT: 1 5 0.67 * * rclb (%rax)
+# CHECK-NEXT: 1 5 0.67 * * rcrb (%rax)
+# CHECK-NEXT: 1 1 0.25 rclb $7, %dil
+# CHECK-NEXT: 1 1 0.25 rcrb $7, %dil
+# CHECK-NEXT: 1 5 0.67 * * rclb $7, (%rax)
+# CHECK-NEXT: 1 5 0.67 * * rcrb $7, (%rax)
+# CHECK-NEXT: 1 4 0.25 rclb %cl, %dil
+# CHECK-NEXT: 1 3 0.25 rcrb %cl, %dil
+# CHECK-NEXT: 1 11 0.33 * * rclb %cl, (%rax)
+# CHECK-NEXT: 1 10 0.33 * * rcrb %cl, (%rax)
+# CHECK-NEXT: 1 1 0.25 rclw %di
+# CHECK-NEXT: 1 1 0.25 rcrw %di
+# CHECK-NEXT: 1 5 0.67 * * rclw (%rax)
+# CHECK-NEXT: 1 5 0.67 * * rcrw (%rax)
+# CHECK-NEXT: 1 1 0.25 rclw $7, %di
+# CHECK-NEXT: 1 1 0.25 rcrw $7, %di
+# CHECK-NEXT: 1 5 0.67 * * rclw $7, (%rax)
+# CHECK-NEXT: 1 5 0.67 * * rcrw $7, (%rax)
+# CHECK-NEXT: 1 4 0.25 rclw %cl, %di
+# CHECK-NEXT: 1 3 0.25 rcrw %cl, %di
+# CHECK-NEXT: 1 11 0.33 * * rclw %cl, (%rax)
+# CHECK-NEXT: 1 10 0.33 * * rcrw %cl, (%rax)
+# CHECK-NEXT: 1 1 0.25 rcll %edi
+# CHECK-NEXT: 1 1 0.25 rcrl %edi
+# CHECK-NEXT: 1 5 0.67 * * rcll (%rax)
+# CHECK-NEXT: 1 5 0.67 * * rcrl (%rax)
+# CHECK-NEXT: 1 1 0.25 rcll $7, %edi
+# CHECK-NEXT: 1 1 0.25 rcrl $7, %edi
+# CHECK-NEXT: 1 5 0.67 * * rcll $7, (%rax)
+# CHECK-NEXT: 1 5 0.67 * * rcrl $7, (%rax)
+# CHECK-NEXT: 1 4 0.25 rcll %cl, %edi
+# CHECK-NEXT: 1 3 0.25 rcrl %cl, %edi
+# CHECK-NEXT: 1 11 0.33 * * rcll %cl, (%rax)
+# CHECK-NEXT: 1 10 0.33 * * rcrl %cl, (%rax)
+# CHECK-NEXT: 1 1 0.25 rclq %rdi
+# CHECK-NEXT: 1 1 0.25 rcrq %rdi
+# CHECK-NEXT: 1 5 0.67 * * rclq (%rax)
+# CHECK-NEXT: 1 5 0.67 * * rcrq (%rax)
+# CHECK-NEXT: 1 1 0.25 rclq $7, %rdi
+# CHECK-NEXT: 1 1 0.25 rcrq $7, %rdi
+# CHECK-NEXT: 1 5 0.67 * * rclq $7, (%rax)
+# CHECK-NEXT: 1 5 0.67 * * rcrq $7, (%rax)
+# CHECK-NEXT: 1 4 0.25 rclq %cl, %rdi
+# CHECK-NEXT: 1 3 0.25 rcrq %cl, %rdi
+# CHECK-NEXT: 1 11 0.33 * * rclq %cl, (%rax)
+# CHECK-NEXT: 1 10 0.33 * * rcrq %cl, (%rax)
+# CHECK-NEXT: 1 100 0.25 U rdmsr
+# CHECK-NEXT: 1 100 0.25 U rdpmc
+# CHECK-NEXT: 1 100 0.25 U rdtsc
+# CHECK-NEXT: 1 100 0.25 U rdtscp
+# CHECK-NEXT: 1 1 0.25 rolb %dil
+# CHECK-NEXT: 1 1 0.25 rorb %dil
+# CHECK-NEXT: 1 5 0.67 * * rolb (%rax)
+# CHECK-NEXT: 1 5 0.67 * * rorb (%rax)
+# CHECK-NEXT: 1 1 0.25 rolb $7, %dil
+# CHECK-NEXT: 1 1 0.25 rorb $7, %dil
+# CHECK-NEXT: 1 5 0.67 * * rolb $7, (%rax)
+# CHECK-NEXT: 1 5 0.67 * * rorb $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 rolb %cl, %dil
+# CHECK-NEXT: 1 1 0.25 rorb %cl, %dil
+# CHECK-NEXT: 1 5 0.67 * * rolb %cl, (%rax)
+# CHECK-NEXT: 1 5 0.67 * * rorb %cl, (%rax)
+# CHECK-NEXT: 1 1 0.25 rolw %di
+# CHECK-NEXT: 1 1 0.25 rorw %di
+# CHECK-NEXT: 1 5 0.67 * * rolw (%rax)
+# CHECK-NEXT: 1 5 0.67 * * rorw (%rax)
+# CHECK-NEXT: 1 1 0.25 rolw $7, %di
+# CHECK-NEXT: 1 1 0.25 rorw $7, %di
+# CHECK-NEXT: 1 5 0.67 * * rolw $7, (%rax)
+# CHECK-NEXT: 1 5 0.67 * * rorw $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 rolw %cl, %di
+# CHECK-NEXT: 1 1 0.25 rorw %cl, %di
+# CHECK-NEXT: 1 5 0.67 * * rolw %cl, (%rax)
+# CHECK-NEXT: 1 5 0.67 * * rorw %cl, (%rax)
+# CHECK-NEXT: 1 1 0.25 roll %edi
+# CHECK-NEXT: 1 1 0.25 rorl %edi
+# CHECK-NEXT: 1 5 0.67 * * roll (%rax)
+# CHECK-NEXT: 1 5 0.67 * * rorl (%rax)
+# CHECK-NEXT: 1 1 0.25 roll $7, %edi
+# CHECK-NEXT: 1 1 0.25 rorl $7, %edi
+# CHECK-NEXT: 1 5 0.67 * * roll $7, (%rax)
+# CHECK-NEXT: 1 5 0.67 * * rorl $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 roll %cl, %edi
+# CHECK-NEXT: 1 1 0.25 rorl %cl, %edi
+# CHECK-NEXT: 1 5 0.67 * * roll %cl, (%rax)
+# CHECK-NEXT: 1 5 0.67 * * rorl %cl, (%rax)
+# CHECK-NEXT: 1 1 0.25 rolq %rdi
+# CHECK-NEXT: 1 1 0.25 rorq %rdi
+# CHECK-NEXT: 1 5 0.67 * * rolq (%rax)
+# CHECK-NEXT: 1 5 0.67 * * rorq (%rax)
+# CHECK-NEXT: 1 1 0.25 rolq $7, %rdi
+# CHECK-NEXT: 1 1 0.25 rorq $7, %rdi
+# CHECK-NEXT: 1 5 0.67 * * rolq $7, (%rax)
+# CHECK-NEXT: 1 5 0.67 * * rorq $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 rolq %cl, %rdi
+# CHECK-NEXT: 1 1 0.25 rorq %cl, %rdi
+# CHECK-NEXT: 1 5 0.67 * * rolq %cl, (%rax)
+# CHECK-NEXT: 1 5 0.67 * * rorq %cl, (%rax)
+# CHECK-NEXT: 4 2 0.50 sahf
+# CHECK-NEXT: 1 1 0.25 sarb %dil
+# CHECK-NEXT: 1 1 0.25 shlb %dil
+# CHECK-NEXT: 1 1 0.25 shrb %dil
+# CHECK-NEXT: 1 5 0.67 * * sarb (%rax)
+# CHECK-NEXT: 1 5 0.67 * * shlb (%rax)
+# CHECK-NEXT: 1 5 0.67 * * shrb (%rax)
+# CHECK-NEXT: 1 1 0.25 sarb $7, %dil
+# CHECK-NEXT: 1 1 0.25 shlb $7, %dil
+# CHECK-NEXT: 1 1 0.25 shrb $7, %dil
+# CHECK-NEXT: 1 5 0.67 * * sarb $7, (%rax)
+# CHECK-NEXT: 1 5 0.67 * * shlb $7, (%rax)
+# CHECK-NEXT: 1 5 0.67 * * shrb $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 sarb %cl, %dil
+# CHECK-NEXT: 1 1 0.25 shlb %cl, %dil
+# CHECK-NEXT: 1 1 0.25 shrb %cl, %dil
+# CHECK-NEXT: 1 5 0.67 * * sarb %cl, (%rax)
+# CHECK-NEXT: 1 5 0.67 * * shlb %cl, (%rax)
+# CHECK-NEXT: 1 5 0.67 * * shrb %cl, (%rax)
+# CHECK-NEXT: 1 1 0.25 sarw %di
+# CHECK-NEXT: 1 1 0.25 shlw %di
+# CHECK-NEXT: 1 1 0.25 shrw %di
+# CHECK-NEXT: 1 5 0.67 * * sarw (%rax)
+# CHECK-NEXT: 1 5 0.67 * * shlw (%rax)
+# CHECK-NEXT: 1 5 0.67 * * shrw (%rax)
+# CHECK-NEXT: 1 1 0.25 sarw $7, %di
+# CHECK-NEXT: 1 1 0.25 shlw $7, %di
+# CHECK-NEXT: 1 1 0.25 shrw $7, %di
+# CHECK-NEXT: 1 5 0.67 * * sarw $7, (%rax)
+# CHECK-NEXT: 1 5 0.67 * * shlw $7, (%rax)
+# CHECK-NEXT: 1 5 0.67 * * shrw $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 sarw %cl, %di
+# CHECK-NEXT: 1 1 0.25 shlw %cl, %di
+# CHECK-NEXT: 1 1 0.25 shrw %cl, %di
+# CHECK-NEXT: 1 5 0.67 * * sarw %cl, (%rax)
+# CHECK-NEXT: 1 5 0.67 * * shlw %cl, (%rax)
+# CHECK-NEXT: 1 5 0.67 * * shrw %cl, (%rax)
+# CHECK-NEXT: 1 1 0.25 sarl %edi
+# CHECK-NEXT: 1 1 0.25 shll %edi
+# CHECK-NEXT: 1 1 0.25 shrl %edi
+# CHECK-NEXT: 1 5 0.67 * * sarl (%rax)
+# CHECK-NEXT: 1 5 0.67 * * shll (%rax)
+# CHECK-NEXT: 1 5 0.67 * * shrl (%rax)
+# CHECK-NEXT: 1 1 0.25 sarl $7, %edi
+# CHECK-NEXT: 1 1 0.25 shll $7, %edi
+# CHECK-NEXT: 1 1 0.25 shrl $7, %edi
+# CHECK-NEXT: 1 5 0.67 * * sarl $7, (%rax)
+# CHECK-NEXT: 1 5 0.67 * * shll $7, (%rax)
+# CHECK-NEXT: 1 5 0.67 * * shrl $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 sarl %cl, %edi
+# CHECK-NEXT: 1 1 0.25 shll %cl, %edi
+# CHECK-NEXT: 1 1 0.25 shrl %cl, %edi
+# CHECK-NEXT: 1 5 0.67 * * sarl %cl, (%rax)
+# CHECK-NEXT: 1 5 0.67 * * shll %cl, (%rax)
+# CHECK-NEXT: 1 5 0.67 * * shrl %cl, (%rax)
+# CHECK-NEXT: 1 1 0.25 sarq %rdi
+# CHECK-NEXT: 1 1 0.25 shlq %rdi
+# CHECK-NEXT: 1 1 0.25 shrq %rdi
+# CHECK-NEXT: 1 5 0.67 * * sarq (%rax)
+# CHECK-NEXT: 1 5 0.67 * * shlq (%rax)
+# CHECK-NEXT: 1 5 0.67 * * shrq (%rax)
+# CHECK-NEXT: 1 1 0.25 sarq $7, %rdi
+# CHECK-NEXT: 1 1 0.25 shlq $7, %rdi
+# CHECK-NEXT: 1 1 0.25 shrq $7, %rdi
+# CHECK-NEXT: 1 5 0.67 * * sarq $7, (%rax)
+# CHECK-NEXT: 1 5 0.67 * * shlq $7, (%rax)
+# CHECK-NEXT: 1 5 0.67 * * shrq $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 sarq %cl, %rdi
+# CHECK-NEXT: 1 1 0.25 shlq %cl, %rdi
+# CHECK-NEXT: 1 1 0.25 shrq %cl, %rdi
+# CHECK-NEXT: 1 5 0.67 * * sarq %cl, (%rax)
+# CHECK-NEXT: 1 5 0.67 * * shlq %cl, (%rax)
+# CHECK-NEXT: 1 5 0.67 * * shrq %cl, (%rax)
+# CHECK-NEXT: 1 1 0.25 sbbb $0, %al
+# CHECK-NEXT: 1 1 0.25 sbbb $0, %dil
+# CHECK-NEXT: 1 6 0.67 * * sbbb $0, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock sbbb $0, (%rax)
+# CHECK-NEXT: 1 1 0.25 sbbb $7, %al
+# CHECK-NEXT: 1 1 0.25 sbbb $7, %dil
+# CHECK-NEXT: 1 6 0.67 * * sbbb $7, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock sbbb $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 sbbb %sil, %dil
+# CHECK-NEXT: 1 6 0.67 * * sbbb %sil, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock sbbb %sil, (%rax)
+# CHECK-NEXT: 1 5 0.33 * sbbb (%rax), %dil
+# CHECK-NEXT: 1 1 0.25 sbbw $0, %ax
+# CHECK-NEXT: 1 1 0.25 sbbw $0, %di
+# CHECK-NEXT: 1 6 0.67 * * sbbw $0, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock sbbw $0, (%rax)
+# CHECK-NEXT: 1 1 0.25 sbbw $511, %ax
+# CHECK-NEXT: 1 1 0.25 sbbw $511, %di
+# CHECK-NEXT: 1 6 0.67 * * sbbw $511, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock sbbw $511, (%rax)
+# CHECK-NEXT: 1 1 0.25 sbbw $7, %di
+# CHECK-NEXT: 1 6 0.67 * * sbbw $7, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock sbbw $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 sbbw %si, %di
+# CHECK-NEXT: 1 6 0.67 * * sbbw %si, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock sbbw %si, (%rax)
+# CHECK-NEXT: 1 5 0.33 * sbbw (%rax), %di
+# CHECK-NEXT: 1 1 0.25 sbbl $0, %eax
+# CHECK-NEXT: 1 1 0.25 sbbl $0, %edi
+# CHECK-NEXT: 1 6 0.67 * * sbbl $0, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock sbbl $0, (%rax)
+# CHECK-NEXT: 1 1 0.25 sbbl $665536, %eax
+# CHECK-NEXT: 1 1 0.25 sbbl $665536, %edi
+# CHECK-NEXT: 1 6 0.67 * * sbbl $665536, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock sbbl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.25 sbbl $7, %edi
+# CHECK-NEXT: 1 6 0.67 * * sbbl $7, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock sbbl $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 sbbl %esi, %edi
+# CHECK-NEXT: 1 6 0.67 * * sbbl %esi, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock sbbl %esi, (%rax)
+# CHECK-NEXT: 1 5 0.33 * sbbl (%rax), %edi
+# CHECK-NEXT: 1 1 0.25 sbbq $0, %rax
+# CHECK-NEXT: 1 1 0.25 sbbq $0, %rdi
+# CHECK-NEXT: 1 6 0.67 * * sbbq $0, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock sbbq $0, (%rax)
+# CHECK-NEXT: 1 1 0.25 sbbq $665536, %rax
+# CHECK-NEXT: 1 1 0.25 sbbq $665536, %rdi
+# CHECK-NEXT: 1 6 0.67 * * sbbq $665536, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock sbbq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.25 sbbq $7, %rdi
+# CHECK-NEXT: 1 6 0.67 * * sbbq $7, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock sbbq $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 sbbq %rsi, %rdi
+# CHECK-NEXT: 1 6 0.67 * * sbbq %rsi, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock sbbq %rsi, (%rax)
+# CHECK-NEXT: 1 5 0.33 * sbbq (%rax), %rdi
+# CHECK-NEXT: 1 100 0.25 U scasb %es:(%rdi), %al
+# CHECK-NEXT: 1 100 0.25 U scasw %es:(%rdi), %ax
+# CHECK-NEXT: 1 100 0.25 U scasl %es:(%rdi), %eax
+# CHECK-NEXT: 1 100 0.25 U scasq %es:(%rdi), %rax
+# CHECK-NEXT: 1 1 0.25 seto %al
+# CHECK-NEXT: 2 1 0.50 * seto (%rax)
+# CHECK-NEXT: 1 1 0.25 setno %al
+# CHECK-NEXT: 2 1 0.50 * setno (%rax)
+# CHECK-NEXT: 1 1 0.25 setb %al
+# CHECK-NEXT: 2 1 0.50 * setb (%rax)
+# CHECK-NEXT: 1 1 0.25 setae %al
+# CHECK-NEXT: 2 1 0.50 * setae (%rax)
+# CHECK-NEXT: 1 1 0.25 sete %al
+# CHECK-NEXT: 2 1 0.50 * sete (%rax)
+# CHECK-NEXT: 1 1 0.25 setne %al
+# CHECK-NEXT: 2 1 0.50 * setne (%rax)
+# CHECK-NEXT: 1 1 0.25 seta %al
+# CHECK-NEXT: 2 1 0.50 * seta (%rax)
+# CHECK-NEXT: 1 1 0.25 setbe %al
+# CHECK-NEXT: 2 1 0.50 * setbe (%rax)
+# CHECK-NEXT: 1 1 0.25 sets %al
+# CHECK-NEXT: 2 1 0.50 * sets (%rax)
+# CHECK-NEXT: 1 1 0.25 setns %al
+# CHECK-NEXT: 2 1 0.50 * setns (%rax)
+# CHECK-NEXT: 1 1 0.25 setp %al
+# CHECK-NEXT: 2 1 0.50 * setp (%rax)
+# CHECK-NEXT: 1 1 0.25 setnp %al
+# CHECK-NEXT: 2 1 0.50 * setnp (%rax)
+# CHECK-NEXT: 1 1 0.25 setl %al
+# CHECK-NEXT: 2 1 0.50 * setl (%rax)
+# CHECK-NEXT: 1 1 0.25 setge %al
+# CHECK-NEXT: 2 1 0.50 * setge (%rax)
+# CHECK-NEXT: 1 1 0.25 setg %al
+# CHECK-NEXT: 2 1 0.50 * setg (%rax)
+# CHECK-NEXT: 1 1 0.25 setle %al
+# CHECK-NEXT: 2 1 0.50 * setle (%rax)
+# CHECK-NEXT: 7 3 1.00 shldw %cl, %si, %di
+# CHECK-NEXT: 7 3 1.00 shrdw %cl, %si, %di
+# CHECK-NEXT: 8 4 1.00 * * shldw %cl, %si, (%rax)
+# CHECK-NEXT: 8 4 1.00 * * shrdw %cl, %si, (%rax)
+# CHECK-NEXT: 6 3 1.00 shldw $7, %si, %di
+# CHECK-NEXT: 6 3 1.00 shrdw $7, %si, %di
+# CHECK-NEXT: 8 4 1.00 * * shldw $7, %si, (%rax)
+# CHECK-NEXT: 8 4 1.00 * * shrdw $7, %si, (%rax)
+# CHECK-NEXT: 7 3 1.00 shldl %cl, %esi, %edi
+# CHECK-NEXT: 7 3 1.00 shrdl %cl, %esi, %edi
+# CHECK-NEXT: 8 4 1.00 * * shldl %cl, %esi, (%rax)
+# CHECK-NEXT: 8 4 1.00 * * shrdl %cl, %esi, (%rax)
+# CHECK-NEXT: 6 3 1.00 shldl $7, %esi, %edi
+# CHECK-NEXT: 6 3 1.00 shrdl $7, %esi, %edi
+# CHECK-NEXT: 8 4 1.00 * * shldl $7, %esi, (%rax)
+# CHECK-NEXT: 8 4 1.00 * * shrdl $7, %esi, (%rax)
+# CHECK-NEXT: 7 3 1.00 shldq %cl, %rsi, %rdi
+# CHECK-NEXT: 7 3 1.00 shrdq %cl, %rsi, %rdi
+# CHECK-NEXT: 8 4 1.00 * * shldq %cl, %rsi, (%rax)
+# CHECK-NEXT: 8 4 1.00 * * shrdq %cl, %rsi, (%rax)
+# CHECK-NEXT: 6 3 1.00 shldq $7, %rsi, %rdi
+# CHECK-NEXT: 6 3 1.00 shrdq $7, %rsi, %rdi
+# CHECK-NEXT: 8 4 1.00 * * shldq $7, %rsi, (%rax)
+# CHECK-NEXT: 8 4 1.00 * * shrdq $7, %rsi, (%rax)
+# CHECK-NEXT: 1 1 0.25 U stc
+# CHECK-NEXT: 1 1 0.25 U std
+# CHECK-NEXT: 1 100 0.25 U stosb %al, %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 U stosw %ax, %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 U stosl %eax, %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 U stosq %rax, %es:(%rdi)
+# CHECK-NEXT: 1 1 0.25 subb $7, %al
+# CHECK-NEXT: 1 1 0.25 subb $7, %dil
+# CHECK-NEXT: 1 6 0.67 * * subb $7, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock subb $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 subb %sil, %dil
+# CHECK-NEXT: 1 6 0.67 * * subb %sil, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock subb %sil, (%rax)
+# CHECK-NEXT: 1 5 0.33 * subb (%rax), %dil
+# CHECK-NEXT: 1 1 0.25 subw $511, %ax
+# CHECK-NEXT: 1 1 0.25 subw $511, %di
+# CHECK-NEXT: 1 6 0.67 * * subw $511, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock subw $511, (%rax)
+# CHECK-NEXT: 1 1 0.25 subw $7, %di
+# CHECK-NEXT: 1 6 0.67 * * subw $7, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock subw $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 subw %si, %di
+# CHECK-NEXT: 1 6 0.67 * * subw %si, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock subw %si, (%rax)
+# CHECK-NEXT: 1 5 0.33 * subw (%rax), %di
+# CHECK-NEXT: 1 1 0.25 subl $665536, %eax
+# CHECK-NEXT: 1 1 0.25 subl $665536, %edi
+# CHECK-NEXT: 1 6 0.67 * * subl $665536, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock subl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.25 subl $7, %edi
+# CHECK-NEXT: 1 6 0.67 * * subl $7, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock subl $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 subl %esi, %edi
+# CHECK-NEXT: 1 6 0.67 * * subl %esi, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock subl %esi, (%rax)
+# CHECK-NEXT: 1 5 0.33 * subl (%rax), %edi
+# CHECK-NEXT: 1 1 0.25 subq $665536, %rax
+# CHECK-NEXT: 1 1 0.25 subq $665536, %rdi
+# CHECK-NEXT: 1 6 0.67 * * subq $665536, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock subq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.25 subq $7, %rdi
+# CHECK-NEXT: 1 6 0.67 * * subq $7, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock subq $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 subq %rsi, %rdi
+# CHECK-NEXT: 1 6 0.67 * * subq %rsi, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock subq %rsi, (%rax)
+# CHECK-NEXT: 1 5 0.33 * subq (%rax), %rdi
+# CHECK-NEXT: 1 1 0.25 testb $7, %al
+# CHECK-NEXT: 1 1 0.25 testb $7, %dil
+# CHECK-NEXT: 1 5 0.33 * testb $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 testb %sil, %dil
+# CHECK-NEXT: 1 5 0.33 * testb %sil, (%rax)
+# CHECK-NEXT: 1 1 0.25 testw $511, %ax
+# CHECK-NEXT: 1 1 0.25 testw $511, %di
+# CHECK-NEXT: 1 5 0.33 * testw $511, (%rax)
+# CHECK-NEXT: 1 1 0.25 testw $7, %di
+# CHECK-NEXT: 1 5 0.33 * testw $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 testw %si, %di
+# CHECK-NEXT: 1 5 0.33 * testw %si, (%rax)
+# CHECK-NEXT: 1 1 0.25 testl $665536, %eax
+# CHECK-NEXT: 1 1 0.25 testl $665536, %edi
+# CHECK-NEXT: 1 5 0.33 * testl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.25 testl $7, %edi
+# CHECK-NEXT: 1 5 0.33 * testl $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 testl %esi, %edi
+# CHECK-NEXT: 1 5 0.33 * testl %esi, (%rax)
+# CHECK-NEXT: 1 1 0.25 testq $665536, %rax
+# CHECK-NEXT: 1 1 0.25 testq $665536, %rdi
+# CHECK-NEXT: 1 5 0.33 * testq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.25 testq $7, %rdi
+# CHECK-NEXT: 1 5 0.33 * testq $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 testq %rsi, %rdi
+# CHECK-NEXT: 1 5 0.33 * testq %rsi, (%rax)
+# CHECK-NEXT: 1 100 0.25 * U ud2
+# CHECK-NEXT: 1 100 0.25 U wrmsr
+# CHECK-NEXT: 2 1 0.50 xaddb %bl, %cl
+# CHECK-NEXT: 2 5 0.50 * * xaddb %bl, (%rcx)
+# CHECK-NEXT: 2 5 0.50 * * lock xaddb %bl, (%rcx)
+# CHECK-NEXT: 2 1 0.50 xaddw %bx, %cx
+# CHECK-NEXT: 2 5 0.50 * * xaddw %ax, (%rbx)
+# CHECK-NEXT: 2 5 0.50 * * lock xaddw %ax, (%rbx)
+# CHECK-NEXT: 2 1 0.50 xaddl %ebx, %ecx
+# CHECK-NEXT: 2 5 0.50 * * xaddl %eax, (%rbx)
+# CHECK-NEXT: 2 5 0.50 * * lock xaddl %eax, (%rbx)
+# CHECK-NEXT: 2 1 0.50 xaddq %rbx, %rcx
+# CHECK-NEXT: 2 5 0.50 * * xaddq %rax, (%rbx)
+# CHECK-NEXT: 2 5 0.50 * * lock xaddq %rax, (%rbx)
+# CHECK-NEXT: 2 1 0.50 xchgb %bl, %cl
+# CHECK-NEXT: 2 5 0.50 * * xchgb %bl, (%rbx)
+# CHECK-NEXT: 2 5 0.50 * * lock xchgb %bl, (%rbx)
+# CHECK-NEXT: 2 1 0.50 xchgw %bx, %ax
+# CHECK-NEXT: 2 1 0.50 xchgw %bx, %cx
+# CHECK-NEXT: 2 5 0.50 * * xchgw %ax, (%rbx)
+# CHECK-NEXT: 2 5 0.50 * * lock xchgw %ax, (%rbx)
+# CHECK-NEXT: 2 0 0.50 xchgl %ebx, %eax
+# CHECK-NEXT: 2 0 0.50 xchgl %ebx, %ecx
+# CHECK-NEXT: 1 5 0.67 * * xchgl %eax, (%rbx)
+# CHECK-NEXT: 1 5 0.67 * * lock xchgl %eax, (%rbx)
+# CHECK-NEXT: 2 0 0.50 xchgq %rbx, %rax
+# CHECK-NEXT: 2 0 0.50 xchgq %rbx, %rcx
+# CHECK-NEXT: 1 5 0.67 * * xchgq %rax, (%rbx)
+# CHECK-NEXT: 1 5 0.67 * * lock xchgq %rax, (%rbx)
+# CHECK-NEXT: 1 5 0.33 * xlatb
+# CHECK-NEXT: 1 1 0.25 xorb $7, %al
+# CHECK-NEXT: 1 1 0.25 xorb $7, %dil
+# CHECK-NEXT: 1 6 0.67 * * xorb $7, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock xorb $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 xorb %sil, %dil
+# CHECK-NEXT: 1 6 0.67 * * xorb %sil, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock xorb %sil, (%rax)
+# CHECK-NEXT: 1 5 0.33 * xorb (%rax), %dil
+# CHECK-NEXT: 1 1 0.25 xorw $511, %ax
+# CHECK-NEXT: 1 1 0.25 xorw $511, %di
+# CHECK-NEXT: 1 6 0.67 * * xorw $511, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock xorw $511, (%rax)
+# CHECK-NEXT: 1 1 0.25 xorw $7, %di
+# CHECK-NEXT: 1 6 0.67 * * xorw $7, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock xorw $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 xorw %si, %di
+# CHECK-NEXT: 1 6 0.67 * * xorw %si, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock xorw %si, (%rax)
+# CHECK-NEXT: 1 5 0.33 * xorw (%rax), %di
+# CHECK-NEXT: 1 1 0.25 xorl $665536, %eax
+# CHECK-NEXT: 1 1 0.25 xorl $665536, %edi
+# CHECK-NEXT: 1 6 0.67 * * xorl $665536, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock xorl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.25 xorl $7, %edi
+# CHECK-NEXT: 1 6 0.67 * * xorl $7, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock xorl $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 xorl %esi, %edi
+# CHECK-NEXT: 1 6 0.67 * * xorl %esi, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock xorl %esi, (%rax)
+# CHECK-NEXT: 1 5 0.33 * xorl (%rax), %edi
+# CHECK-NEXT: 1 1 0.25 xorq $665536, %rax
+# CHECK-NEXT: 1 1 0.25 xorq $665536, %rdi
+# CHECK-NEXT: 1 6 0.67 * * xorq $665536, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock xorq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.25 xorq $7, %rdi
+# CHECK-NEXT: 1 6 0.67 * * xorq $7, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock xorq $7, (%rax)
+# CHECK-NEXT: 1 1 0.25 xorq %rsi, %rdi
+# CHECK-NEXT: 1 6 0.67 * * xorq %rsi, (%rax)
+# CHECK-NEXT: 1 6 0.67 * * lock xorq %rsi, (%rax)
+# CHECK-NEXT: 1 5 0.33 * xorq (%rax), %rdi
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 263.00 263.00 263.00 298.25 396.25 298.25 398.25 - - - - - 197.25 197.25 197.25 197.25 147.00 147.00 147.00 87.00 87.00 87.00 87.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - adcb $0, %al
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - adcb $0, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 adcb $0, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock adcb $0, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - adcb $7, %al
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - adcb $7, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 adcb $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock adcb $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - adcb %sil, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 adcb %sil, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock adcb %sil, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - adcb (%rax), %dil
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - adcw $0, %ax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - adcw $0, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 adcw $0, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock adcw $0, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - adcw $511, %ax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - adcw $511, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 adcw $511, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock adcw $511, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - adcw $7, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 adcw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock adcw $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - adcw %si, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 adcw %si, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock adcw %si, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - adcw (%rax), %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - adcl $0, %eax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - adcl $0, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 adcl $0, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock adcl $0, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - adcl $665536, %eax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - adcl $665536, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 adcl $665536, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock adcl $665536, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - adcl $7, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 adcl $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock adcl $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - adcl %esi, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 adcl %esi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock adcl %esi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - adcl (%rax), %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - adcq $0, %rax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - adcq $0, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 adcq $0, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock adcq $0, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - adcq $665536, %rax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - adcq $665536, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 adcq $665536, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock adcq $665536, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - adcq $7, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 adcq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock adcq $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - adcq %rsi, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 adcq %rsi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock adcq %rsi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - adcq (%rax), %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - addb $7, %al
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - addb $7, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 addb $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock addb $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - addb %sil, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 addb %sil, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock addb %sil, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - addb (%rax), %dil
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - addw $511, %ax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - addw $511, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 addw $511, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock addw $511, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - addw $7, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 addw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock addw $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - addw %si, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 addw %si, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock addw %si, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - addw (%rax), %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - addl $665536, %eax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - addl $665536, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 addl $665536, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock addl $665536, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - addl $7, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 addl $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock addl $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - addl %esi, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 addl %esi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock addl %esi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - addl (%rax), %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - addq $665536, %rax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - addq $665536, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 addq $665536, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock addq $665536, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - addq $7, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 addq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock addq $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - addq %rsi, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 addq %rsi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock addq %rsi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - addq (%rax), %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - andb $7, %al
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - andb $7, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 andb $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock andb $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - andb %sil, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 andb %sil, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock andb %sil, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - andb (%rax), %dil
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - andw $511, %ax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - andw $511, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 andw $511, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock andw $511, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - andw $7, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 andw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock andw $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - andw %si, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 andw %si, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock andw %si, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - andw (%rax), %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - andl $665536, %eax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - andl $665536, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 andl $665536, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock andl $665536, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - andl $7, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 andl $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock andl $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - andl %esi, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 andl %esi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock andl %esi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - andl (%rax), %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - andq $665536, %rax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - andq $665536, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 andq $665536, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock andq $665536, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - andq $7, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 andq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock andq $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - andq %rsi, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 andq %rsi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock andq %rsi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - andq (%rax), %rdi
+# CHECK-NEXT: - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - - - - - - bsfw %si, %di
+# CHECK-NEXT: - - - 4.00 4.00 4.00 4.00 - - - - - - - - - - - - - - - - bsrw %si, %di
+# CHECK-NEXT: 0.33 0.33 0.33 3.00 3.00 3.00 3.00 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - bsfw (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 4.00 4.00 4.00 4.00 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - bsrw (%rax), %di
+# CHECK-NEXT: - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - - - - - - bsfl %esi, %edi
+# CHECK-NEXT: - - - 4.00 4.00 4.00 4.00 - - - - - - - - - - - - - - - - bsrl %esi, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 3.00 3.00 3.00 3.00 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - bsfl (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 4.00 4.00 4.00 4.00 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - bsrl (%rax), %edi
+# CHECK-NEXT: - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - - - - - - bsfq %rsi, %rdi
+# CHECK-NEXT: - - - 4.00 4.00 4.00 4.00 - - - - - - - - - - - - - - - - bsrq %rsi, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 3.00 3.00 3.00 3.00 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - bsfq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 4.00 4.00 4.00 4.00 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - bsrq (%rax), %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - bswapl %eax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - bswapq %rax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - btw %si, %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - btcw %si, %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - btrw %si, %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - btsw %si, %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - btw %si, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 btcw %si, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 btrw %si, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 btsw %si, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock btcw %si, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock btrw %si, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock btsw %si, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - btw $7, %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - btcw $7, %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - btrw $7, %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - btsw $7, %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - btw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 btcw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 btrw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 btsw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock btcw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock btrw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock btsw $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - btl %esi, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - btcl %esi, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - btrl %esi, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - btsl %esi, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - btl %esi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 btcl %esi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 btrl %esi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 btsl %esi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock btcl %esi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock btrl %esi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock btsl %esi, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - btl $7, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - btcl $7, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - btrl $7, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - btsl $7, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - btl $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 btcl $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 btrl $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 btsl $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock btcl $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock btrl $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock btsl $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - btq %rsi, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - btcq %rsi, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - btrq %rsi, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - btsq %rsi, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - btq %rsi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 btcq %rsi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 btrq %rsi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 btsq %rsi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock btcq %rsi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock btrq %rsi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock btsq %rsi, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - btq $7, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - btcq $7, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - btrq $7, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - btsq $7, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - btq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 btcq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 btrq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 btsq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock btcq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock btrq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock btsq $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cbtw
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cwtl
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cltq
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cwtd
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cltd
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cqto
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - clc
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cld
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmc
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmpb $7, %al
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmpb $7, %dil
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmpb $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmpb %sil, %dil
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmpb %sil, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmpb (%rax), %dil
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmpw $511, %ax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmpw $511, %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmpw $511, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmpw $7, %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmpw $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmpw %si, %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmpw %si, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmpw (%rax), %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmpl $665536, %eax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmpl $665536, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmpl $665536, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmpl $7, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmpl $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmpl %esi, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmpl %esi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmpl (%rax), %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmpq $665536, %rax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmpq $665536, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmpq $665536, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmpq $7, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmpq $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - cmpq %rsi, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmpq %rsi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - cmpq (%rax), %rdi
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - cmpsb %es:(%rdi), (%rsi)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - cmpsw %es:(%rdi), (%rsi)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - cmpsl %es:(%rdi), (%rsi)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - cmpsq %es:(%rdi), (%rsi)
+# CHECK-NEXT: - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - - - - - - cmpxchgb %cl, %bl
+# CHECK-NEXT: 0.33 0.33 0.33 3.00 3.00 3.00 3.00 - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 cmpxchgb %cl, (%rbx)
+# CHECK-NEXT: 0.33 0.33 0.33 3.00 3.00 3.00 3.00 - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 lock cmpxchgb %cl, (%rbx)
+# CHECK-NEXT: - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - - - - - - cmpxchgw %cx, %bx
+# CHECK-NEXT: - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - - - - - - cmpxchgw %cx, (%rbx)
+# CHECK-NEXT: - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - - - - - - lock cmpxchgw %cx, (%rbx)
+# CHECK-NEXT: - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - - - - - - cmpxchgl %ecx, %ebx
+# CHECK-NEXT: - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - - - - - - cmpxchgl %ecx, (%rbx)
+# CHECK-NEXT: - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - - - - - - lock cmpxchgl %ecx, (%rbx)
+# CHECK-NEXT: - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - - - - - - cmpxchgq %rcx, %rbx
+# CHECK-NEXT: - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - - - - - - cmpxchgq %rcx, (%rbx)
+# CHECK-NEXT: - - - 3.00 3.00 3.00 3.00 - - - - - - - - - - - - - - - - lock cmpxchgq %rcx, (%rbx)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - cpuid
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - decb %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 decb (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock decb (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - decw %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 decw (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock decw (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - decl %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 decl (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock decl (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - decq %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 decq (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock decq (%rax)
+# CHECK-NEXT: - - - - - - 4.00 - - - - - - - - - - - - - - - - divb %dil
+# CHECK-NEXT: 0.33 0.33 0.33 - - - 4.00 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - divb (%rax)
+# CHECK-NEXT: - - - - - - 4.00 - - - - - - - - - - - - - - - - divw %si
+# CHECK-NEXT: 0.33 0.33 0.33 - - - 4.00 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - divw (%rax)
+# CHECK-NEXT: - - - - - - 7.00 - - - - - - - - - - - - - - - - divl %edx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - 7.00 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - divl (%rax)
+# CHECK-NEXT: - - - - - - 10.00 - - - - - - - - - - - - - - - - divq %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - 10.00 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - divq (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - enter $7, $4095
+# CHECK-NEXT: - - - - - - 4.00 - - - - - - - - - - - - - - - - idivb %dil
+# CHECK-NEXT: 0.33 0.33 0.33 - - - 4.00 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - idivb (%rax)
+# CHECK-NEXT: - - - - - - 4.00 - - - - - - - - - - - - - - - - idivw %si
+# CHECK-NEXT: 0.33 0.33 0.33 - - - 4.00 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - idivw (%rax)
+# CHECK-NEXT: - - - - - - 7.00 - - - - - - - - - - - - - - - - idivl %edx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - 7.00 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - idivl (%rax)
+# CHECK-NEXT: - - - - - - 10.00 - - - - - - - - - - - - - - - - idivq %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - - - 10.00 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - idivq (%rax)
+# CHECK-NEXT: - - - - 3.00 - - - - - - - - - - - - - - - - - - imulb %dil
+# CHECK-NEXT: 0.33 0.33 0.33 - 3.00 - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - imulb (%rax)
+# CHECK-NEXT: - - - - 3.00 - - - - - - - - - - - - - - - - - - imulw %di
+# CHECK-NEXT: 0.33 0.33 0.33 - 3.00 - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - imulw (%rax)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - - - - imulw %si, %di
+# CHECK-NEXT: 0.33 0.33 0.33 - 1.00 - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - imulw (%rax), %di
+# CHECK-NEXT: - - - - 3.00 - - - - - - - - - - - - - - - - - - imulw $511, %si, %di
+# CHECK-NEXT: 0.33 0.33 0.33 - 3.00 - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - imulw $511, (%rax), %di
+# CHECK-NEXT: - - - - 3.00 - - - - - - - - - - - - - - - - - - imulw $7, %si, %di
+# CHECK-NEXT: 0.33 0.33 0.33 - 3.00 - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - imulw $7, (%rax), %di
+# CHECK-NEXT: - - - - 3.00 - - - - - - - - - - - - - - - - - - imull %edi
+# CHECK-NEXT: 0.33 0.33 0.33 - 3.00 - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - imull (%rax)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - - - - imull %esi, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 - 1.00 - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - imull (%rax), %edi
+# CHECK-NEXT: - - - - 3.00 - - - - - - - - - - - - - - - - - - imull $665536, %esi, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 - 3.00 - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - imull $665536, (%rax), %edi
+# CHECK-NEXT: - - - - 3.00 - - - - - - - - - - - - - - - - - - imull $7, %esi, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 - 3.00 - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - imull $7, (%rax), %edi
+# CHECK-NEXT: - - - - 4.00 - - - - - - - - - - - - - - - - - - imulq %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 - 4.00 - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - imulq (%rax)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - - - - imulq %rsi, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 - 1.00 - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - imulq (%rax), %rdi
+# CHECK-NEXT: - - - - 4.00 - - - - - - - - - - - - - - - - - - imulq $665536, %rsi, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 - 4.00 - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - imulq $665536, (%rax), %rdi
+# CHECK-NEXT: - - - - 4.00 - - - - - - - - - - - - - - - - - - imulq $7, %rsi, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 - 4.00 - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - imulq $7, (%rax), %rdi
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - inb $7, %al
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - inb %dx, %al
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - inw $7, %ax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - inw %dx, %ax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - inl $7, %eax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - inl %dx, %eax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - incb %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 incb (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock incb (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - incw %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 incw (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock incw (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - incl %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 incl (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock incl (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - incq %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 incq (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock incq (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - insb %dx, %es:(%rdi)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - insw %dx, %es:(%rdi)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - insl %dx, %es:(%rdi)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - int $7
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - invlpg (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - invlpga
+# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - - - lahf
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - leave
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - lodsb (%rsi), %al
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - lodsw (%rsi), %ax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - lodsl (%rsi), %eax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - lodsq (%rsi), %rax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - loop 0
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - loope 0
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - loopne 0
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - movsb (%rsi), %es:(%rdi)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - movsw (%rsi), %es:(%rdi)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - movsl (%rsi), %es:(%rdi)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - movsq (%rsi), %es:(%rdi)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - movsbw %al, %di
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - movzbw %al, %di
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movsbw (%rax), %di
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movzbw (%rax), %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - movsbl %al, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - movzbl %al, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movsbl (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movzbl (%rax), %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - movsbq %al, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - movzbq %al, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movsbq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movzbq (%rax), %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - movswl %ax, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - movzwl %ax, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movswl (%rax), %edi
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movzwl (%rax), %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - movswq %ax, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - movzwq %ax, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movswq (%rax), %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movzwq (%rax), %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - movslq %eax, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - movslq (%rax), %rdi
+# CHECK-NEXT: - - - - 3.00 - - - - - - - - - - - - - - - - - - mulb %dil
+# CHECK-NEXT: 0.33 0.33 0.33 - 3.00 - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - mulb (%rax)
+# CHECK-NEXT: - - - - 3.00 - - - - - - - - - - - - - - - - - - mulw %si
+# CHECK-NEXT: 0.33 0.33 0.33 - 3.00 - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - mulw (%rax)
+# CHECK-NEXT: - - - - 3.00 - - - - - - - - - - - - - - - - - - mull %edx
+# CHECK-NEXT: 0.33 0.33 0.33 - 3.00 - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - mull (%rax)
+# CHECK-NEXT: - - - - 4.00 - - - - - - - - - - - - - - - - - - mulq %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 - 4.00 - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - mulq (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - negb %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 negb (%r8)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock negb (%r8)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - negw %si
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 negw (%r9)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock negw (%r9)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - negl %edx
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 negl (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock negl (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - negq %rcx
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 negq (%r10)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock negq (%r10)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - nop
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - nopw %di
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - nopw (%rcx)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - nopl %esi
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - nopl (%r8)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - nopq %rdx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - nopq (%r9)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - notb %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 notb (%r8)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock notb (%r8)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - notw %si
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 notw (%r9)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock notw (%r9)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - notl %edx
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 notl (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock notl (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - notq %rcx
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 notq (%r10)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock notq (%r10)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - orb $7, %al
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - orb $7, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 orb $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock orb $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - orb %sil, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 orb %sil, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock orb %sil, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - orb (%rax), %dil
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - orw $511, %ax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - orw $511, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 orw $511, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock orw $511, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - orw $7, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 orw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock orw $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - orw %si, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 orw %si, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock orw %si, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - orw (%rax), %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - orl $665536, %eax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - orl $665536, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 orl $665536, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock orl $665536, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - orl $7, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 orl $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock orl $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - orl %esi, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 orl %esi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock orl %esi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - orl (%rax), %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - orq $665536, %rax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - orq $665536, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 orq $665536, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock orq $665536, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - orq $7, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 orq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock orq $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - orq %rsi, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 orq %rsi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock orq %rsi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - orq (%rax), %rdi
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - outb %al, $7
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - outb %al, %dx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - outw %ax, $7
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - outw %ax, %dx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - outl %eax, $7
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - outl %eax, %dx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - outsb (%rsi), %dx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - outsw (%rsi), %dx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - outsl (%rsi), %dx
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - pause
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rclb %dil
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rcrb %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rclb (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rcrb (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rclb $7, %dil
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rcrb $7, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rclb $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rcrb $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rclb %cl, %dil
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rcrb %cl, %dil
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - rclb %cl, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - rcrb %cl, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rclw %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rcrw %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rclw (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rcrw (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rclw $7, %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rcrw $7, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rclw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rcrw $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rclw %cl, %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rcrw %cl, %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - rclw %cl, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - rcrw %cl, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rcll %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rcrl %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rcll (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rcrl (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rcll $7, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rcrl $7, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rcll $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rcrl $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rcll %cl, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rcrl %cl, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - rcll %cl, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - rcrl %cl, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rclq %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rcrq %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rclq (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rcrq (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rclq $7, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rcrq $7, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rclq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rcrq $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rclq %cl, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rcrq %cl, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - rclq %cl, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - rcrq %cl, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - rdmsr
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - rdpmc
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - rdtsc
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - rdtscp
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rolb %dil
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rorb %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rolb (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rorb (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rolb $7, %dil
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rorb $7, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rolb $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rorb $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rolb %cl, %dil
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rorb %cl, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rolb %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rorb %cl, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rolw %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rorw %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rolw (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rorw (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rolw $7, %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rorw $7, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rolw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rorw $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rolw %cl, %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rorw %cl, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rolw %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rorw %cl, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - roll %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rorl %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 roll (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rorl (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - roll $7, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rorl $7, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 roll $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rorl $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - roll %cl, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rorl %cl, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 roll %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rorl %cl, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rolq %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rorq %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rolq (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rorq (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rolq $7, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rorq $7, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rolq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rorq $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rolq %cl, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rorq %cl, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rolq %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 rorq %cl, (%rax)
+# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - - - sahf
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sarb %dil
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - shlb %dil
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - shrb %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 sarb (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 shlb (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 shrb (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sarb $7, %dil
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - shlb $7, %dil
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - shrb $7, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 sarb $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 shlb $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 shrb $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sarb %cl, %dil
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - shlb %cl, %dil
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - shrb %cl, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 sarb %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 shlb %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 shrb %cl, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sarw %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - shlw %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - shrw %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 sarw (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 shlw (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 shrw (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sarw $7, %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - shlw $7, %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - shrw $7, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 sarw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 shlw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 shrw $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sarw %cl, %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - shlw %cl, %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - shrw %cl, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 sarw %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 shlw %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 shrw %cl, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sarl %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - shll %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - shrl %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 sarl (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 shll (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 shrl (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sarl $7, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - shll $7, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - shrl $7, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 sarl $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 shll $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 shrl $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sarl %cl, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - shll %cl, %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - shrl %cl, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 sarl %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 shll %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 shrl %cl, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sarq %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - shlq %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - shrq %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 sarq (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 shlq (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 shrq (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sarq $7, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - shlq $7, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - shrq $7, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 sarq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 shlq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 shrq $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sarq %cl, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - shlq %cl, %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - shrq %cl, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 sarq %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 shlq %cl, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 shrq %cl, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sbbb $0, %al
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sbbb $0, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 sbbb $0, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock sbbb $0, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sbbb $7, %al
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sbbb $7, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 sbbb $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock sbbb $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sbbb %sil, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 sbbb %sil, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock sbbb %sil, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - sbbb (%rax), %dil
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sbbw $0, %ax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sbbw $0, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 sbbw $0, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock sbbw $0, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sbbw $511, %ax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sbbw $511, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 sbbw $511, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock sbbw $511, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sbbw $7, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 sbbw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock sbbw $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sbbw %si, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 sbbw %si, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock sbbw %si, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - sbbw (%rax), %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sbbl $0, %eax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sbbl $0, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 sbbl $0, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock sbbl $0, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sbbl $665536, %eax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sbbl $665536, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 sbbl $665536, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock sbbl $665536, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sbbl $7, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 sbbl $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock sbbl $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sbbl %esi, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 sbbl %esi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock sbbl %esi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - sbbl (%rax), %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sbbq $0, %rax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sbbq $0, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 sbbq $0, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock sbbq $0, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sbbq $665536, %rax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sbbq $665536, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 sbbq $665536, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock sbbq $665536, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sbbq $7, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 sbbq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock sbbq $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sbbq %rsi, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 sbbq %rsi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock sbbq %rsi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - sbbq (%rax), %rdi
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - scasb %es:(%rdi), %al
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - scasw %es:(%rdi), %ax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - scasl %es:(%rdi), %eax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - scasq %es:(%rdi), %rax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - seto %al
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 seto (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - setno %al
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 setno (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - setb %al
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 setb (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - setae %al
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 setae (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sete %al
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 sete (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - setne %al
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 setne (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - seta %al
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 seta (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - setbe %al
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 setbe (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sets %al
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 sets (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - setns %al
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 setns (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - setp %al
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 setp (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - setnp %al
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 setnp (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - setl %al
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 setl (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - setge %al
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 setge (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - setg %al
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 setg (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - setle %al
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 setle (%rax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - shldw %cl, %si, %di
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - shrdw %cl, %si, %di
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 1.00 1.00 1.00 - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 shldw %cl, %si, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 1.00 1.00 1.00 - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 shrdw %cl, %si, (%rax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - shldw $7, %si, %di
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - shrdw $7, %si, %di
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 1.00 1.00 1.00 - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 shldw $7, %si, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 1.00 1.00 1.00 - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 shrdw $7, %si, (%rax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - shldl %cl, %esi, %edi
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - shrdl %cl, %esi, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 1.00 1.00 1.00 - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 shldl %cl, %esi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 1.00 1.00 1.00 - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 shrdl %cl, %esi, (%rax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - shldl $7, %esi, %edi
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - shrdl $7, %esi, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 1.00 1.00 1.00 - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 shldl $7, %esi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 1.00 1.00 1.00 - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 shrdl $7, %esi, (%rax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - shldq %cl, %rsi, %rdi
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - shrdq %cl, %rsi, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 1.00 1.00 1.00 - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 shldq %cl, %rsi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 1.00 1.00 1.00 - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 shrdq %cl, %rsi, (%rax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - shldq $7, %rsi, %rdi
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - shrdq $7, %rsi, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 1.00 1.00 1.00 - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 shldq $7, %rsi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 1.00 1.00 1.00 1.00 - - - - - 0.25 0.25 0.25 0.25 - - - 0.25 0.25 0.25 0.25 shrdq $7, %rsi, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - stc
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - std
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - stosb %al, %es:(%rdi)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - stosw %ax, %es:(%rdi)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - stosl %eax, %es:(%rdi)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - stosq %rax, %es:(%rdi)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - subb $7, %al
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - subb $7, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 subb $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock subb $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - subb %sil, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 subb %sil, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock subb %sil, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - subb (%rax), %dil
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - subw $511, %ax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - subw $511, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 subw $511, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock subw $511, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - subw $7, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 subw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock subw $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - subw %si, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 subw %si, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock subw %si, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - subw (%rax), %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - subl $665536, %eax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - subl $665536, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 subl $665536, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock subl $665536, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - subl $7, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 subl $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock subl $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - subl %esi, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 subl %esi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock subl %esi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - subl (%rax), %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - subq $665536, %rax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - subq $665536, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 subq $665536, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock subq $665536, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - subq $7, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 subq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock subq $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - subq %rsi, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 subq %rsi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock subq %rsi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - subq (%rax), %rdi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - testb $7, %al
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - testb $7, %dil
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - testb $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - testb %sil, %dil
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - testb %sil, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - testw $511, %ax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - testw $511, %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - testw $511, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - testw $7, %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - testw $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - testw %si, %di
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - testw %si, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - testl $665536, %eax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - testl $665536, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - testl $665536, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - testl $7, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - testl $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - testl %esi, %edi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - testl %esi, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - testq $665536, %rax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - testq $665536, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - testq $665536, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - testq $7, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - testq $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - testq %rsi, %rdi
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - testq %rsi, (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - ud2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - wrmsr
+# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - - - xaddb %bl, %cl
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - xaddb %bl, (%rcx)
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - lock xaddb %bl, (%rcx)
+# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - - - xaddw %bx, %cx
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - xaddw %ax, (%rbx)
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - lock xaddw %ax, (%rbx)
+# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - - - xaddl %ebx, %ecx
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - xaddl %eax, (%rbx)
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - lock xaddl %eax, (%rbx)
+# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - - - xaddq %rbx, %rcx
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - xaddq %rax, (%rbx)
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - lock xaddq %rax, (%rbx)
+# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - - - xchgb %bl, %cl
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - xchgb %bl, (%rbx)
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - lock xchgb %bl, (%rbx)
+# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - - - xchgw %bx, %ax
+# CHECK-NEXT: - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - - - xchgw %bx, %cx
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - xchgw %ax, (%rbx)
+# CHECK-NEXT: 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - lock xchgw %ax, (%rbx)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - xchgl %ebx, %eax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - xchgl %ebx, %ecx
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 xchgl %eax, (%rbx)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock xchgl %eax, (%rbx)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - xchgq %rbx, %rax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - xchgq %rbx, %rcx
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 xchgq %rax, (%rbx)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock xchgq %rax, (%rbx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - xlatb
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - xorb $7, %al
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - xorb $7, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 xorb $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock xorb $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - xorb %sil, %dil
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 xorb %sil, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock xorb %sil, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - xorb (%rax), %dil
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - xorw $511, %ax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - xorw $511, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 xorw $511, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock xorw $511, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - xorw $7, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 xorw $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock xorw $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - xorw %si, %di
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 xorw %si, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock xorw %si, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - xorw (%rax), %di
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - xorl $665536, %eax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - xorl $665536, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 xorl $665536, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock xorl $665536, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - xorl $7, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 xorl $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock xorl $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - xorl %esi, %edi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 xorl %esi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock xorl %esi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - xorl (%rax), %edi
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - xorq $665536, %rax
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - xorq $665536, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 xorq $665536, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock xorq $665536, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - xorq $7, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 xorq $7, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock xorq $7, (%rax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - xorq %rsi, %rdi
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 xorq %rsi, (%rax)
+# CHECK-NEXT: 0.67 0.67 0.67 0.25 0.25 0.25 0.25 - - - - - 0.50 0.50 0.50 0.50 0.33 0.33 0.33 0.25 0.25 0.25 0.25 lock xorq %rsi, (%rax)
+# CHECK-NEXT: 0.33 0.33 0.33 0.25 0.25 0.25 0.25 - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - xorq (%rax), %rdi
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-x87.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-x87.s
new file mode 100644
index 0000000000000..71b88b2bc9064
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-x87.s
@@ -0,0 +1,536 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+f2xm1
+
+fabs
+
+fadd %st, %st(1)
+fadd %st(2)
+fadds (%ecx)
+faddl (%ecx)
+faddp %st(1)
+faddp %st(2)
+fiadds (%ecx)
+fiaddl (%ecx)
+
+fbld (%ecx)
+fbstp (%eax)
+
+fchs
+
+fnclex
+
+fcmovb %st(1), %st
+fcmovbe %st(1), %st
+fcmove %st(1), %st
+fcmovnb %st(1), %st
+fcmovnbe %st(1), %st
+fcmovne %st(1), %st
+fcmovnu %st(1), %st
+fcmovu %st(1), %st
+
+fcom %st(1)
+fcom %st(3)
+fcoms (%ecx)
+fcoml (%eax)
+fcomp %st(1)
+fcomp %st(3)
+fcomps (%ecx)
+fcompl (%eax)
+fcompp
+
+fcomi %st(3)
+fcompi %st(3)
+
+fcos
+
+fdecstp
+
+fdiv %st, %st(1)
+fdiv %st(2)
+fdivs (%ecx)
+fdivl (%eax)
+fdivp %st(1)
+fdivp %st(2)
+fidivs (%ecx)
+fidivl (%eax)
+
+fdivr %st, %st(1)
+fdivr %st(2)
+fdivrs (%ecx)
+fdivrl (%eax)
+fdivrp %st(1)
+fdivrp %st(2)
+fidivrs (%ecx)
+fidivrl (%eax)
+
+ffree %st(0)
+
+ficoms (%ecx)
+ficoml (%eax)
+ficomps (%ecx)
+ficompl (%eax)
+
+filds (%edx)
+fildl (%ecx)
+fildll (%eax)
+
+fincstp
+
+fninit
+
+fists (%edx)
+fistl (%ecx)
+fistps (%edx)
+fistpl (%ecx)
+fistpll (%eax)
+
+fisttps (%edx)
+fisttpl (%ecx)
+fisttpll (%eax)
+
+fld %st(0)
+flds (%edx)
+fldl (%ecx)
+fldt (%eax)
+
+fldcw (%eax)
+fldenv (%eax)
+
+fld1
+fldl2e
+fldl2t
+fldlg2
+fldln2
+fldpi
+fldz
+
+fmul %st, %st(1)
+fmul %st(2)
+fmuls (%ecx)
+fmull (%eax)
+fmulp %st(1)
+fmulp %st(2)
+fimuls (%ecx)
+fimull (%eax)
+
+fnop
+
+fpatan
+
+fprem
+fprem1
+
+fptan
+
+frndint
+
+frstor (%eax)
+
+fnsave (%eax)
+
+fscale
+
+fsin
+
+fsincos
+
+fsqrt
+
+fst %st(0)
+fsts (%edx)
+fstl (%ecx)
+fstp %st(0)
+fstpl (%edx)
+fstpl (%ecx)
+fstpt (%eax)
+
+fnstcw (%eax)
+fnstenv (%eax)
+fnstsw (%eax)
+
+frstor (%eax)
+fsave (%eax)
+
+fsub %st, %st(1)
+fsub %st(2)
+fsubs (%ecx)
+fsubl (%eax)
+fsubp %st(1)
+fsubp %st(2)
+fisubs (%ecx)
+fisubl (%eax)
+
+fsubr %st, %st(1)
+fsubr %st(2)
+fsubrs (%ecx)
+fsubrl (%eax)
+fsubrp %st(1)
+fsubrp %st(2)
+fisubrs (%ecx)
+fisubrl (%eax)
+
+ftst
+
+fucom %st(1)
+fucom %st(3)
+fucomp %st(1)
+fucomp %st(3)
+fucompp
+
+fucomi %st(3)
+fucompi %st(3)
+
+fwait
+
+fxam
+
+fxch %st(1)
+fxch %st(3)
+
+fxrstor (%eax)
+fxsave (%eax)
+
+fxtract
+
+fyl2x
+fyl2xp1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 100 0.25 U f2xm1
+# CHECK-NEXT: 1 1 1.00 U fabs
+# CHECK-NEXT: 1 3 0.50 U fadd %st, %st(1)
+# CHECK-NEXT: 1 3 0.50 U fadd %st(2), %st
+# CHECK-NEXT: 1 10 0.50 * U fadds (%ecx)
+# CHECK-NEXT: 1 10 0.50 * U faddl (%ecx)
+# CHECK-NEXT: 1 3 0.50 U faddp %st, %st(1)
+# CHECK-NEXT: 1 3 0.50 U faddp %st, %st(2)
+# CHECK-NEXT: 1 10 0.50 * U fiadds (%ecx)
+# CHECK-NEXT: 1 10 0.50 * U fiaddl (%ecx)
+# CHECK-NEXT: 1 100 0.25 * U fbld (%ecx)
+# CHECK-NEXT: 1 100 0.25 * U fbstp (%eax)
+# CHECK-NEXT: 1 1 1.00 U fchs
+# CHECK-NEXT: 1 100 0.25 U fnclex
+# CHECK-NEXT: 1 100 0.25 U fcmovb %st(1), %st
+# CHECK-NEXT: 1 100 0.25 U fcmovbe %st(1), %st
+# CHECK-NEXT: 1 100 0.25 U fcmove %st(1), %st
+# CHECK-NEXT: 1 100 0.25 U fcmovnb %st(1), %st
+# CHECK-NEXT: 1 100 0.25 U fcmovnbe %st(1), %st
+# CHECK-NEXT: 1 100 0.25 U fcmovne %st(1), %st
+# CHECK-NEXT: 1 100 0.25 U fcmovnu %st(1), %st
+# CHECK-NEXT: 1 100 0.25 U fcmovu %st(1), %st
+# CHECK-NEXT: 1 1 0.50 U fcom %st(1)
+# CHECK-NEXT: 1 1 0.50 U fcom %st(3)
+# CHECK-NEXT: 1 8 0.50 * U fcoms (%ecx)
+# CHECK-NEXT: 1 8 0.50 * U fcoml (%eax)
+# CHECK-NEXT: 1 1 0.50 U fcomp %st(1)
+# CHECK-NEXT: 1 1 0.50 U fcomp %st(3)
+# CHECK-NEXT: 1 8 0.50 * U fcomps (%ecx)
+# CHECK-NEXT: 1 8 0.50 * U fcompl (%eax)
+# CHECK-NEXT: 1 100 0.25 U fcompp
+# CHECK-NEXT: 2 2 0.50 U fcomi %st(3), %st
+# CHECK-NEXT: 2 2 0.50 U fcompi %st(3), %st
+# CHECK-NEXT: 1 100 0.25 U fcos
+# CHECK-NEXT: 1 100 0.25 U fdecstp
+# CHECK-NEXT: 1 10 4.50 U fdiv %st, %st(1)
+# CHECK-NEXT: 1 10 4.50 U fdiv %st(2), %st
+# CHECK-NEXT: 1 17 4.50 * U fdivs (%ecx)
+# CHECK-NEXT: 1 17 4.50 * U fdivl (%eax)
+# CHECK-NEXT: 1 10 4.50 U fdivp %st, %st(1)
+# CHECK-NEXT: 1 10 4.50 U fdivp %st, %st(2)
+# CHECK-NEXT: 1 17 4.50 * U fidivs (%ecx)
+# CHECK-NEXT: 1 17 4.50 * U fidivl (%eax)
+# CHECK-NEXT: 1 10 4.50 U fdivr %st, %st(1)
+# CHECK-NEXT: 1 10 4.50 U fdivr %st(2), %st
+# CHECK-NEXT: 1 17 4.50 * U fdivrs (%ecx)
+# CHECK-NEXT: 1 17 4.50 * U fdivrl (%eax)
+# CHECK-NEXT: 1 10 4.50 U fdivrp %st, %st(1)
+# CHECK-NEXT: 1 10 4.50 U fdivrp %st, %st(2)
+# CHECK-NEXT: 1 17 4.50 * U fidivrs (%ecx)
+# CHECK-NEXT: 1 17 4.50 * U fidivrl (%eax)
+# CHECK-NEXT: 1 100 0.25 U ffree %st(0)
+# CHECK-NEXT: 1 8 0.50 * U ficoms (%ecx)
+# CHECK-NEXT: 1 8 0.50 * U ficoml (%eax)
+# CHECK-NEXT: 1 8 0.50 * U ficomps (%ecx)
+# CHECK-NEXT: 1 8 0.50 * U ficompl (%eax)
+# CHECK-NEXT: 1 5 0.33 * U filds (%edx)
+# CHECK-NEXT: 1 5 0.33 * U fildl (%ecx)
+# CHECK-NEXT: 1 5 0.33 * U fildll (%eax)
+# CHECK-NEXT: 1 100 0.25 U fincstp
+# CHECK-NEXT: 1 100 0.25 U fninit
+# CHECK-NEXT: 1 1 0.50 * U fists (%edx)
+# CHECK-NEXT: 1 1 0.50 * U fistl (%ecx)
+# CHECK-NEXT: 1 1 0.50 * U fistps (%edx)
+# CHECK-NEXT: 1 1 0.50 * U fistpl (%ecx)
+# CHECK-NEXT: 1 1 0.50 * U fistpll (%eax)
+# CHECK-NEXT: 1 1 0.50 * U fisttps (%edx)
+# CHECK-NEXT: 1 1 0.50 * U fisttpl (%ecx)
+# CHECK-NEXT: 1 1 0.50 * U fisttpll (%eax)
+# CHECK-NEXT: 1 1 1.00 U fld %st(0)
+# CHECK-NEXT: 1 5 0.33 * U flds (%edx)
+# CHECK-NEXT: 1 5 0.33 * U fldl (%ecx)
+# CHECK-NEXT: 1 5 0.33 * U fldt (%eax)
+# CHECK-NEXT: 1 5 0.33 * U fldcw (%eax)
+# CHECK-NEXT: 1 100 0.25 * U fldenv (%eax)
+# CHECK-NEXT: 1 8 1.00 U fld1
+# CHECK-NEXT: 1 8 1.00 U fldl2e
+# CHECK-NEXT: 1 8 1.00 U fldl2t
+# CHECK-NEXT: 1 8 1.00 U fldlg2
+# CHECK-NEXT: 1 8 1.00 U fldln2
+# CHECK-NEXT: 1 8 1.00 U fldpi
+# CHECK-NEXT: 1 8 1.00 U fldz
+# CHECK-NEXT: 1 3 0.50 U fmul %st, %st(1)
+# CHECK-NEXT: 1 3 0.50 U fmul %st(2), %st
+# CHECK-NEXT: 1 10 0.50 * U fmuls (%ecx)
+# CHECK-NEXT: 1 10 0.50 * U fmull (%eax)
+# CHECK-NEXT: 1 3 0.50 U fmulp %st, %st(1)
+# CHECK-NEXT: 1 3 0.50 U fmulp %st, %st(2)
+# CHECK-NEXT: 1 10 0.50 * U fimuls (%ecx)
+# CHECK-NEXT: 1 10 0.50 * U fimull (%eax)
+# CHECK-NEXT: 1 1 0.25 U fnop
+# CHECK-NEXT: 1 100 0.25 U fpatan
+# CHECK-NEXT: 1 100 0.25 U fprem
+# CHECK-NEXT: 1 100 0.25 U fprem1
+# CHECK-NEXT: 1 100 0.25 U fptan
+# CHECK-NEXT: 1 100 0.25 U frndint
+# CHECK-NEXT: 1 100 0.25 * U frstor (%eax)
+# CHECK-NEXT: 1 100 0.25 * U fnsave (%eax)
+# CHECK-NEXT: 1 100 0.25 U fscale
+# CHECK-NEXT: 1 100 0.25 U fsin
+# CHECK-NEXT: 1 100 0.25 U fsincos
+# CHECK-NEXT: 1 22 11.50 U fsqrt
+# CHECK-NEXT: 1 1 1.00 U fst %st(0)
+# CHECK-NEXT: 1 1 0.50 * U fsts (%edx)
+# CHECK-NEXT: 1 1 0.50 * U fstl (%ecx)
+# CHECK-NEXT: 1 1 1.00 U fstp %st(0)
+# CHECK-NEXT: 1 1 0.50 * U fstpl (%edx)
+# CHECK-NEXT: 1 1 0.50 * U fstpl (%ecx)
+# CHECK-NEXT: 1 1 0.50 * U fstpt (%eax)
+# CHECK-NEXT: 1 1 0.25 * U fnstcw (%eax)
+# CHECK-NEXT: 1 100 0.25 * U fnstenv (%eax)
+# CHECK-NEXT: 1 100 0.25 * U fnstsw (%eax)
+# CHECK-NEXT: 1 100 0.25 * U frstor (%eax)
+# CHECK-NEXT: 1 100 0.25 U wait
+# CHECK-NEXT: 1 100 0.25 * U fnsave (%eax)
+# CHECK-NEXT: 1 3 0.50 U fsub %st, %st(1)
+# CHECK-NEXT: 1 3 0.50 U fsub %st(2), %st
+# CHECK-NEXT: 1 10 0.50 * U fsubs (%ecx)
+# CHECK-NEXT: 1 10 0.50 * U fsubl (%eax)
+# CHECK-NEXT: 1 3 0.50 U fsubp %st, %st(1)
+# CHECK-NEXT: 1 3 0.50 U fsubp %st, %st(2)
+# CHECK-NEXT: 1 10 0.50 * U fisubs (%ecx)
+# CHECK-NEXT: 1 10 0.50 * U fisubl (%eax)
+# CHECK-NEXT: 1 3 0.50 U fsubr %st, %st(1)
+# CHECK-NEXT: 1 3 0.50 U fsubr %st(2), %st
+# CHECK-NEXT: 1 10 0.50 * U fsubrs (%ecx)
+# CHECK-NEXT: 1 10 0.50 * U fsubrl (%eax)
+# CHECK-NEXT: 1 3 0.50 U fsubrp %st, %st(1)
+# CHECK-NEXT: 1 3 0.50 U fsubrp %st, %st(2)
+# CHECK-NEXT: 1 10 0.50 * U fisubrs (%ecx)
+# CHECK-NEXT: 1 10 0.50 * U fisubrl (%eax)
+# CHECK-NEXT: 1 1 0.50 U ftst
+# CHECK-NEXT: 1 1 0.50 U fucom %st(1)
+# CHECK-NEXT: 1 1 0.50 U fucom %st(3)
+# CHECK-NEXT: 1 1 0.50 U fucomp %st(1)
+# CHECK-NEXT: 1 1 0.50 U fucomp %st(3)
+# CHECK-NEXT: 1 1 0.50 U fucompp
+# CHECK-NEXT: 1 1 0.50 U fucomi %st(3), %st
+# CHECK-NEXT: 1 1 0.50 U fucompi %st(3), %st
+# CHECK-NEXT: 1 100 0.25 U wait
+# CHECK-NEXT: 1 1 0.50 U fxam
+# CHECK-NEXT: 1 1 1.00 U fxch %st(1)
+# CHECK-NEXT: 1 1 1.00 U fxch %st(3)
+# CHECK-NEXT: 1 100 0.25 * * U fxrstor (%eax)
+# CHECK-NEXT: 1 100 0.25 * * U fxsave (%eax)
+# CHECK-NEXT: 1 100 0.25 U fxtract
+# CHECK-NEXT: 1 100 0.25 U fyl2x
+# CHECK-NEXT: 1 100 0.25 U fyl2xp1
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: 19.67 19.67 19.67 5.25 5.25 5.25 5.25 - 15.00 106.00 15.00 97.00 18.00 18.00 18.00 18.00 15.33 15.33 15.33 6.50 6.50 6.50 6.50
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - f2xm1
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - - - - fabs
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - fadd %st, %st(1)
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - fadd %st(2), %st
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fadds (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - faddl (%ecx)
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - faddp %st, %st(1)
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - faddp %st, %st(2)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fiadds (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fiaddl (%ecx)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fbld (%ecx)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fbstp (%eax)
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - - - - fchs
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fnclex
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fcmovb %st(1), %st
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fcmovbe %st(1), %st
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fcmove %st(1), %st
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fcmovnb %st(1), %st
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fcmovnbe %st(1), %st
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fcmovne %st(1), %st
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fcmovnu %st(1), %st
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fcmovu %st(1), %st
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - fcom %st(1)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - fcom %st(3)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fcoms (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fcoml (%eax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - fcomp %st(1)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - fcomp %st(3)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fcomps (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fcompl (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fcompp
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - fcomi %st(3), %st
+# CHECK-NEXT: - - - - - - - - 0.50 0.50 0.50 0.50 - - - - - - - - - - - fcompi %st(3), %st
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fcos
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fdecstp
+# CHECK-NEXT: - - - - - - - - - 4.50 - 4.50 - - - - - - - - - - - fdiv %st, %st(1)
+# CHECK-NEXT: - - - - - - - - - 4.50 - 4.50 - - - - - - - - - - - fdiv %st(2), %st
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.50 - 4.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fdivs (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.50 - 4.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fdivl (%eax)
+# CHECK-NEXT: - - - - - - - - - 4.50 - 4.50 - - - - - - - - - - - fdivp %st, %st(1)
+# CHECK-NEXT: - - - - - - - - - 4.50 - 4.50 - - - - - - - - - - - fdivp %st, %st(2)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.50 - 4.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fidivs (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.50 - 4.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fidivl (%eax)
+# CHECK-NEXT: - - - - - - - - - 4.50 - 4.50 - - - - - - - - - - - fdivr %st, %st(1)
+# CHECK-NEXT: - - - - - - - - - 4.50 - 4.50 - - - - - - - - - - - fdivr %st(2), %st
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.50 - 4.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fdivrs (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.50 - 4.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fdivrl (%eax)
+# CHECK-NEXT: - - - - - - - - - 4.50 - 4.50 - - - - - - - - - - - fdivrp %st, %st(1)
+# CHECK-NEXT: - - - - - - - - - 4.50 - 4.50 - - - - - - - - - - - fdivrp %st, %st(2)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.50 - 4.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fidivrs (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 4.50 - 4.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fidivrl (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - ffree %st(0)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - ficoms (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - ficoml (%eax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - ficomps (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - ficompl (%eax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - filds (%edx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fildl (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fildll (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fincstp
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fninit
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 fists (%edx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 fistl (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 fistps (%edx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 fistpl (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 fistpll (%eax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 fisttps (%edx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 fisttpl (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 fisttpll (%eax)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - fld %st(0)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - flds (%edx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fldl (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fldt (%eax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fldcw (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fldenv (%eax)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fld1
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fldl2e
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fldl2t
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fldlg2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fldln2
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fldpi
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 1.00 - - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fldz
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - fmul %st, %st(1)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - fmul %st(2), %st
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fmuls (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fmull (%eax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - fmulp %st, %st(1)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - fmulp %st, %st(2)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fimuls (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - 0.50 - 0.50 - 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fimull (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fnop
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fpatan
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fprem
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fprem1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fptan
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - frndint
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - frstor (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fnsave (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fscale
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fsin
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fsincos
+# CHECK-NEXT: - - - - - - - - - 11.50 - 11.50 - - - - - - - - - - - fsqrt
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - fst %st(0)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 fsts (%edx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 fstl (%ecx)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - fstp %st(0)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 fstpl (%edx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 fstpl (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - - - - 0.50 0.50 0.50 0.50 - - - 0.50 0.50 0.50 0.50 fstpt (%eax)
+# CHECK-NEXT: - - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - fnstcw (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fnstenv (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fnstsw (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - frstor (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - wait
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fnsave (%eax)
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - fsub %st, %st(1)
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - fsub %st(2), %st
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fsubs (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fsubl (%eax)
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - fsubp %st, %st(1)
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - fsubp %st, %st(2)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fisubs (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fisubl (%eax)
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - fsubr %st, %st(1)
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - fsubr %st(2), %st
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fsubrs (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fsubrl (%eax)
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - fsubrp %st, %st(1)
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - fsubrp %st, %st(2)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fisubrs (%ecx)
+# CHECK-NEXT: 0.33 0.33 0.33 - - - - - - 0.50 - 0.50 0.25 0.25 0.25 0.25 0.33 0.33 0.33 - - - - fisubrl (%eax)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - ftst
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - fucom %st(1)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - fucom %st(3)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - fucomp %st(1)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - fucomp %st(3)
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - fucompp
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - fucomi %st(3), %st
+# CHECK-NEXT: - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - - fucompi %st(3), %st
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - wait
+# CHECK-NEXT: - - - - - - - - - 0.50 - 0.50 - - - - - - - - - - - fxam
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - fxch %st(1)
+# CHECK-NEXT: - - - 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - - fxch %st(3)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fxrstor (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fxsave (%eax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fxtract
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fyl2x
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - fyl2xp1
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-xsave.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-xsave.s
new file mode 100644
index 0000000000000..a322cf26008da
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-xsave.s
@@ -0,0 +1,64 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -instruction-tables < %s | FileCheck %s
+
+xgetbv
+
+xrstor (%rax)
+
+xrstors (%rax)
+
+xsave (%rax)
+
+xsetbv
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 100 0.25 U xgetbv
+# CHECK-NEXT: 1 100 0.25 * * U xrstor (%rax)
+# CHECK-NEXT: 1 100 0.25 * * U xrstors (%rax)
+# CHECK-NEXT: 1 100 0.25 * * U xsave (%rax)
+# CHECK-NEXT: 1 100 0.25 * * U xsetbv
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - xgetbv
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - xrstor (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - xrstors (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - xsave (%rax)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - xsetbv
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/zero-idioms.s b/llvm/test/tools/llvm-mca/X86/4GM7/zero-idioms.s
new file mode 100644
index 0000000000000..fbfc06512ab48
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/zero-idioms.s
@@ -0,0 +1,796 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=c86-4g-m7 -timeline -register-file-stats -iterations=1 < %s | FileCheck %s
+
+subl %eax, %eax
+subq %rax, %rax
+xorl %eax, %eax
+xorq %rax, %rax
+
+pcmpgtb %mm2, %mm2
+pcmpgtd %mm2, %mm2
+pcmpgtw %mm2, %mm2
+
+pcmpgtb %xmm2, %xmm2
+pcmpgtd %xmm2, %xmm2
+pcmpgtq %xmm2, %xmm2
+pcmpgtw %xmm2, %xmm2
+
+vpcmpgtb %xmm3, %xmm3, %xmm3
+vpcmpgtd %xmm3, %xmm3, %xmm3
+vpcmpgtq %xmm3, %xmm3, %xmm3
+vpcmpgtw %xmm3, %xmm3, %xmm3
+
+vpcmpgtb %xmm3, %xmm3, %xmm5
+vpcmpgtd %xmm3, %xmm3, %xmm5
+vpcmpgtq %xmm3, %xmm3, %xmm5
+vpcmpgtw %xmm3, %xmm3, %xmm5
+
+vpcmpgtb %ymm3, %ymm3, %ymm3
+vpcmpgtd %ymm3, %ymm3, %ymm3
+vpcmpgtq %ymm3, %ymm3, %ymm3
+vpcmpgtw %ymm3, %ymm3, %ymm3
+
+vpcmpgtb %ymm3, %ymm3, %ymm5
+vpcmpgtd %ymm3, %ymm3, %ymm5
+vpcmpgtq %ymm3, %ymm3, %ymm5
+vpcmpgtw %ymm3, %ymm3, %ymm5
+
+psubb %mm2, %mm2
+psubd %mm2, %mm2
+psubq %mm2, %mm2
+psubw %mm2, %mm2
+psubb %xmm2, %xmm2
+psubd %xmm2, %xmm2
+psubq %xmm2, %xmm2
+psubw %xmm2, %xmm2
+vpsubb %xmm3, %xmm3, %xmm3
+vpsubd %xmm3, %xmm3, %xmm3
+vpsubq %xmm3, %xmm3, %xmm3
+vpsubw %xmm3, %xmm3, %xmm3
+vpsubb %ymm3, %ymm3, %ymm3
+vpsubd %ymm3, %ymm3, %ymm3
+vpsubq %ymm3, %ymm3, %ymm3
+vpsubw %ymm3, %ymm3, %ymm3
+
+vpsubb %xmm3, %xmm3, %xmm5
+vpsubd %xmm3, %xmm3, %xmm5
+vpsubq %xmm3, %xmm3, %xmm5
+vpsubw %xmm3, %xmm3, %xmm5
+vpsubb %ymm3, %ymm3, %ymm5
+vpsubd %ymm3, %ymm3, %ymm5
+vpsubq %ymm3, %ymm3, %ymm5
+vpsubw %ymm3, %ymm3, %ymm5
+
+vpsubb %xmm19, %xmm19, %xmm19
+vpsubd %xmm19, %xmm19, %xmm19
+vpsubq %xmm19, %xmm19, %xmm19
+vpsubw %xmm19, %xmm19, %xmm19
+vpsubb %ymm19, %ymm19, %ymm19
+vpsubd %ymm19, %ymm19, %ymm19
+vpsubq %ymm19, %ymm19, %ymm19
+vpsubw %ymm19, %ymm19, %ymm19
+vpsubb %zmm19, %zmm19, %zmm19
+vpsubd %zmm19, %zmm19, %zmm19
+vpsubq %zmm19, %zmm19, %zmm19
+vpsubw %zmm19, %zmm19, %zmm19
+
+vpsubb %xmm19, %xmm19, %xmm21
+vpsubd %xmm19, %xmm19, %xmm21
+vpsubq %xmm19, %xmm19, %xmm21
+vpsubw %xmm19, %xmm19, %xmm21
+vpsubb %ymm19, %ymm19, %ymm21
+vpsubd %ymm19, %ymm19, %ymm21
+vpsubq %ymm19, %ymm19, %ymm21
+vpsubw %ymm19, %ymm19, %ymm21
+vpsubb %zmm19, %zmm19, %zmm21
+vpsubd %zmm19, %zmm19, %zmm21
+vpsubq %zmm19, %zmm19, %zmm21
+vpsubw %zmm19, %zmm19, %zmm21
+
+andnps %xmm0, %xmm0
+andnpd %xmm1, %xmm1
+vandnps %xmm2, %xmm2, %xmm2
+vandnpd %xmm1, %xmm1, %xmm1
+vandnps %ymm2, %ymm2, %ymm2
+vandnpd %ymm1, %ymm1, %ymm1
+vandnps %zmm2, %zmm2, %zmm2
+vandnpd %zmm1, %zmm1, %zmm1
+pandn %mm2, %mm2
+pandn %xmm2, %xmm2
+vpandn %xmm3, %xmm3, %xmm3
+vpandn %ymm3, %ymm3, %ymm3
+
+vpandnd %xmm19, %xmm19, %xmm19
+vpandnq %xmm19, %xmm19, %xmm19
+vpandnd %ymm19, %ymm19, %ymm19
+vpandnq %ymm19, %ymm19, %ymm19
+vpandnd %zmm19, %zmm19, %zmm19
+vpandnq %zmm19, %zmm19, %zmm19
+
+vandnps %xmm2, %xmm2, %xmm5
+vandnpd %xmm1, %xmm1, %xmm5
+vpandn %xmm3, %xmm3, %xmm5
+vandnps %ymm2, %ymm2, %ymm5
+vandnpd %ymm1, %ymm1, %ymm5
+vpandn %ymm3, %ymm3, %ymm5
+vandnps %zmm2, %zmm2, %zmm5
+vandnpd %zmm1, %zmm1, %zmm5
+
+vpandnd %xmm19, %xmm19, %xmm21
+vpandnq %xmm19, %xmm19, %xmm21
+vpandnd %ymm19, %ymm19, %ymm21
+vpandnq %ymm19, %ymm19, %ymm21
+vpandnd %zmm19, %zmm19, %zmm21
+vpandnq %zmm19, %zmm19, %zmm21
+
+xorps %xmm0, %xmm0
+xorpd %xmm1, %xmm1
+vxorps %xmm2, %xmm2, %xmm2
+vxorpd %xmm1, %xmm1, %xmm1
+vxorps %ymm2, %ymm2, %ymm2
+vxorpd %ymm1, %ymm1, %ymm1
+vxorps %zmm2, %zmm2, %zmm2
+vxorpd %zmm1, %zmm1, %zmm1
+pxor %mm2, %mm2
+pxor %xmm2, %xmm2
+vpxor %xmm3, %xmm3, %xmm3
+vpxor %ymm3, %ymm3, %ymm3
+
+vpxord %xmm19, %xmm19, %xmm19
+vpxorq %xmm19, %xmm19, %xmm19
+vpxord %ymm19, %ymm19, %ymm19
+vpxorq %ymm19, %ymm19, %ymm19
+vpxord %zmm19, %zmm19, %zmm19
+vpxorq %zmm19, %zmm19, %zmm19
+
+vxorps %xmm4, %xmm4, %xmm5
+vxorpd %xmm1, %xmm1, %xmm3
+vxorps %ymm4, %ymm4, %ymm5
+vxorpd %ymm1, %ymm1, %ymm3
+vxorps %zmm4, %zmm4, %zmm5
+vxorpd %zmm1, %zmm1, %zmm3
+vpxor %xmm3, %xmm3, %xmm5
+vpxor %ymm3, %ymm3, %ymm5
+
+vpxord %xmm19, %xmm19, %xmm21
+vpxorq %xmm19, %xmm19, %xmm21
+vpxord %ymm19, %ymm19, %ymm21
+vpxorq %ymm19, %ymm19, %ymm21
+vpxord %zmm19, %zmm19, %zmm21
+vpxorq %zmm19, %zmm19, %zmm21
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 139
+# CHECK-NEXT: Total Cycles: 36
+# CHECK-NEXT: Total uOps: 139
+
+# CHECK: Dispatch Width: 4
+# CHECK-NEXT: uOps Per Cycle: 3.86
+# CHECK-NEXT: IPC: 3.86
+# CHECK-NEXT: Block RThroughput: 34.8
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 0 0.25 subl %eax, %eax
+# CHECK-NEXT: 1 0 0.25 subq %rax, %rax
+# CHECK-NEXT: 1 0 0.25 xorl %eax, %eax
+# CHECK-NEXT: 1 0 0.25 xorq %rax, %rax
+# CHECK-NEXT: 1 1 0.25 pcmpgtb %mm2, %mm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtd %mm2, %mm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtw %mm2, %mm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtb %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtd %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtq %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.25 pcmpgtw %xmm2, %xmm2
+# CHECK-NEXT: 1 0 0.25 vpcmpgtb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 0 0.25 vpcmpgtd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 0 0.25 vpcmpgtq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 0 0.25 vpcmpgtw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 0 0.25 vpcmpgtb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 0 0.25 vpcmpgtd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 0 0.25 vpcmpgtq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 0 0.25 vpcmpgtw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 0 0.25 vpcmpgtb %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 0 0.25 vpcmpgtd %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 0 0.25 vpcmpgtq %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 0 0.25 vpcmpgtw %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 0 0.25 vpcmpgtb %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 0 0.25 vpcmpgtd %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 0 0.25 vpcmpgtq %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 0 0.25 vpcmpgtw %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 1 0.25 psubb %mm2, %mm2
+# CHECK-NEXT: 1 1 0.25 psubd %mm2, %mm2
+# CHECK-NEXT: 1 1 0.25 psubq %mm2, %mm2
+# CHECK-NEXT: 1 1 0.25 psubw %mm2, %mm2
+# CHECK-NEXT: 1 1 0.25 psubb %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.25 psubd %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.25 psubq %xmm2, %xmm2
+# CHECK-NEXT: 1 1 0.25 psubw %xmm2, %xmm2
+# CHECK-NEXT: 1 0 0.25 vpsubb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 0 0.25 vpsubd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 0 0.25 vpsubq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 0 0.25 vpsubw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 0 0.25 vpsubb %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 0 0.25 vpsubd %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 0 0.25 vpsubq %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 0 0.25 vpsubw %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 0 0.25 vpsubb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 0 0.25 vpsubd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 0 0.25 vpsubq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 0 0.25 vpsubw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 0 0.25 vpsubb %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 0 0.25 vpsubd %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 0 0.25 vpsubq %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 0 0.25 vpsubw %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 0 0.25 vpsubb %xmm19, %xmm19, %xmm19
+# CHECK-NEXT: 1 0 0.25 vpsubd %xmm19, %xmm19, %xmm19
+# CHECK-NEXT: 1 0 0.25 vpsubq %xmm19, %xmm19, %xmm19
+# CHECK-NEXT: 1 0 0.25 vpsubw %xmm19, %xmm19, %xmm19
+# CHECK-NEXT: 1 0 0.25 vpsubb %ymm19, %ymm19, %ymm19
+# CHECK-NEXT: 1 0 0.25 vpsubd %ymm19, %ymm19, %ymm19
+# CHECK-NEXT: 1 0 0.25 vpsubq %ymm19, %ymm19, %ymm19
+# CHECK-NEXT: 1 0 0.25 vpsubw %ymm19, %ymm19, %ymm19
+# CHECK-NEXT: 1 0 0.25 vpsubb %zmm19, %zmm19, %zmm19
+# CHECK-NEXT: 1 0 0.25 vpsubd %zmm19, %zmm19, %zmm19
+# CHECK-NEXT: 1 0 0.25 vpsubq %zmm19, %zmm19, %zmm19
+# CHECK-NEXT: 1 0 0.25 vpsubw %zmm19, %zmm19, %zmm19
+# CHECK-NEXT: 1 0 0.25 vpsubb %xmm19, %xmm19, %xmm21
+# CHECK-NEXT: 1 0 0.25 vpsubd %xmm19, %xmm19, %xmm21
+# CHECK-NEXT: 1 0 0.25 vpsubq %xmm19, %xmm19, %xmm21
+# CHECK-NEXT: 1 0 0.25 vpsubw %xmm19, %xmm19, %xmm21
+# CHECK-NEXT: 1 0 0.25 vpsubb %ymm19, %ymm19, %ymm21
+# CHECK-NEXT: 1 0 0.25 vpsubd %ymm19, %ymm19, %ymm21
+# CHECK-NEXT: 1 0 0.25 vpsubq %ymm19, %ymm19, %ymm21
+# CHECK-NEXT: 1 0 0.25 vpsubw %ymm19, %ymm19, %ymm21
+# CHECK-NEXT: 1 0 0.25 vpsubb %zmm19, %zmm19, %zmm21
+# CHECK-NEXT: 1 0 0.25 vpsubd %zmm19, %zmm19, %zmm21
+# CHECK-NEXT: 1 0 0.25 vpsubq %zmm19, %zmm19, %zmm21
+# CHECK-NEXT: 1 0 0.25 vpsubw %zmm19, %zmm19, %zmm21
+# CHECK-NEXT: 1 1 0.25 andnps %xmm0, %xmm0
+# CHECK-NEXT: 1 1 0.25 andnpd %xmm1, %xmm1
+# CHECK-NEXT: 1 0 0.25 vandnps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: 1 0 0.25 vandnpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: 1 0 0.25 vandnps %ymm2, %ymm2, %ymm2
+# CHECK-NEXT: 1 0 0.25 vandnpd %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: 1 0 0.25 vandnps %zmm2, %zmm2, %zmm2
+# CHECK-NEXT: 1 0 0.25 vandnpd %zmm1, %zmm1, %zmm1
+# CHECK-NEXT: 1 1 0.25 pandn %mm2, %mm2
+# CHECK-NEXT: 1 1 0.25 pandn %xmm2, %xmm2
+# CHECK-NEXT: 1 0 0.25 vpandn %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 0 0.25 vpandn %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 0 0.25 vpandnd %xmm19, %xmm19, %xmm19
+# CHECK-NEXT: 1 0 0.25 vpandnq %xmm19, %xmm19, %xmm19
+# CHECK-NEXT: 1 0 0.25 vpandnd %ymm19, %ymm19, %ymm19
+# CHECK-NEXT: 1 0 0.25 vpandnq %ymm19, %ymm19, %ymm19
+# CHECK-NEXT: 1 0 0.25 vpandnd %zmm19, %zmm19, %zmm19
+# CHECK-NEXT: 1 0 0.25 vpandnq %zmm19, %zmm19, %zmm19
+# CHECK-NEXT: 1 0 0.25 vandnps %xmm2, %xmm2, %xmm5
+# CHECK-NEXT: 1 0 0.25 vandnpd %xmm1, %xmm1, %xmm5
+# CHECK-NEXT: 1 0 0.25 vpandn %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 0 0.25 vandnps %ymm2, %ymm2, %ymm5
+# CHECK-NEXT: 1 0 0.25 vandnpd %ymm1, %ymm1, %ymm5
+# CHECK-NEXT: 1 0 0.25 vpandn %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 0 0.25 vandnps %zmm2, %zmm2, %zmm5
+# CHECK-NEXT: 1 0 0.25 vandnpd %zmm1, %zmm1, %zmm5
+# CHECK-NEXT: 1 0 0.25 vpandnd %xmm19, %xmm19, %xmm21
+# CHECK-NEXT: 1 0 0.25 vpandnq %xmm19, %xmm19, %xmm21
+# CHECK-NEXT: 1 0 0.25 vpandnd %ymm19, %ymm19, %ymm21
+# CHECK-NEXT: 1 0 0.25 vpandnq %ymm19, %ymm19, %ymm21
+# CHECK-NEXT: 1 0 0.25 vpandnd %zmm19, %zmm19, %zmm21
+# CHECK-NEXT: 1 0 0.25 vpandnq %zmm19, %zmm19, %zmm21
+# CHECK-NEXT: 1 1 0.25 xorps %xmm0, %xmm0
+# CHECK-NEXT: 1 1 0.25 xorpd %xmm1, %xmm1
+# CHECK-NEXT: 1 0 0.25 vxorps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: 1 0 0.25 vxorpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: 1 0 0.25 vxorps %ymm2, %ymm2, %ymm2
+# CHECK-NEXT: 1 0 0.25 vxorpd %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: 1 0 0.25 vxorps %zmm2, %zmm2, %zmm2
+# CHECK-NEXT: 1 0 0.25 vxorpd %zmm1, %zmm1, %zmm1
+# CHECK-NEXT: 1 1 0.25 pxor %mm2, %mm2
+# CHECK-NEXT: 1 1 0.25 pxor %xmm2, %xmm2
+# CHECK-NEXT: 1 0 0.25 vpxor %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 1 0 0.25 vpxor %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 1 0 0.25 vpxord %xmm19, %xmm19, %xmm19
+# CHECK-NEXT: 1 0 0.25 vpxorq %xmm19, %xmm19, %xmm19
+# CHECK-NEXT: 1 0 0.25 vpxord %ymm19, %ymm19, %ymm19
+# CHECK-NEXT: 1 0 0.25 vpxorq %ymm19, %ymm19, %ymm19
+# CHECK-NEXT: 1 0 0.25 vpxord %zmm19, %zmm19, %zmm19
+# CHECK-NEXT: 1 0 0.25 vpxorq %zmm19, %zmm19, %zmm19
+# CHECK-NEXT: 1 0 0.25 vxorps %xmm4, %xmm4, %xmm5
+# CHECK-NEXT: 1 0 0.25 vxorpd %xmm1, %xmm1, %xmm3
+# CHECK-NEXT: 1 0 0.25 vxorps %ymm4, %ymm4, %ymm5
+# CHECK-NEXT: 1 0 0.25 vxorpd %ymm1, %ymm1, %ymm3
+# CHECK-NEXT: 1 0 0.25 vxorps %zmm4, %zmm4, %zmm5
+# CHECK-NEXT: 1 0 0.25 vxorpd %zmm1, %zmm1, %zmm3
+# CHECK-NEXT: 1 0 0.25 vpxor %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 1 0 0.25 vpxor %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 1 0 0.25 vpxord %xmm19, %xmm19, %xmm21
+# CHECK-NEXT: 1 0 0.25 vpxorq %xmm19, %xmm19, %xmm21
+# CHECK-NEXT: 1 0 0.25 vpxord %ymm19, %ymm19, %ymm21
+# CHECK-NEXT: 1 0 0.25 vpxorq %ymm19, %ymm19, %ymm21
+# CHECK-NEXT: 1 0 0.25 vpxord %zmm19, %zmm19, %zmm21
+# CHECK-NEXT: 1 0 0.25 vpxorq %zmm19, %zmm19, %zmm21
+
+# CHECK: Register File statistics:
+# CHECK-NEXT: Total number of mappings created: 9
+# CHECK-NEXT: Max number of mappings used: 4
+
+# CHECK: * Register File #1 -- 4GM7FpuPRF:
+# CHECK-NEXT: Number of physical registers: 208
+# CHECK-NEXT: Total number of mappings created: 9
+# CHECK-NEXT: Max number of mappings used: 4
+
+# CHECK: * Register File #2 -- 4GM7IntegerPRF:
+# CHECK-NEXT: Number of physical registers: 224
+# CHECK-NEXT: Total number of mappings created: 0
+# CHECK-NEXT: Max number of mappings used: 0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - 4GM7AGU0
+# CHECK-NEXT: [1] - 4GM7AGU1
+# CHECK-NEXT: [2] - 4GM7AGU2
+# CHECK-NEXT: [3] - 4GM7ALU0
+# CHECK-NEXT: [4] - 4GM7ALU1
+# CHECK-NEXT: [5] - 4GM7ALU2
+# CHECK-NEXT: [6] - 4GM7ALU3
+# CHECK-NEXT: [7] - 4GM7BRU1
+# CHECK-NEXT: [8] - 4GM7FPU0
+# CHECK-NEXT: [9] - 4GM7FPU1
+# CHECK-NEXT: [10] - 4GM7FPU2
+# CHECK-NEXT: [11] - 4GM7FPU3
+# CHECK-NEXT: [12.0] - 4GM7LSU
+# CHECK-NEXT: [12.1] - 4GM7LSU
+# CHECK-NEXT: [12.2] - 4GM7LSU
+# CHECK-NEXT: [12.3] - 4GM7LSU
+# CHECK-NEXT: [13.0] - 4GM7Load
+# CHECK-NEXT: [13.1] - 4GM7Load
+# CHECK-NEXT: [13.2] - 4GM7Load
+# CHECK-NEXT: [14.0] - 4GM7Store
+# CHECK-NEXT: [14.1] - 4GM7Store
+# CHECK-NEXT: [14.2] - 4GM7Store
+# CHECK-NEXT: [14.3] - 4GM7Store
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
+# CHECK-NEXT: - - - - - - - - 5.00 6.00 6.00 6.00 - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - subl %eax, %eax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - subq %rax, %rax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - xorl %eax, %eax
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - xorq %rax, %rax
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - - - pcmpgtb %mm2, %mm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - - - - pcmpgtd %mm2, %mm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - - - - pcmpgtw %mm2, %mm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - - - - pcmpgtb %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - - - - pcmpgtd %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - - - pcmpgtq %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - - - - pcmpgtw %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpcmpgtb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpcmpgtd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpcmpgtq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpcmpgtw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpcmpgtb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpcmpgtd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpcmpgtq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpcmpgtw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpcmpgtb %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpcmpgtd %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpcmpgtq %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpcmpgtw %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpcmpgtb %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpcmpgtd %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpcmpgtq %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpcmpgtw %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - - - - psubb %mm2, %mm2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - - - psubd %mm2, %mm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - - - - psubq %mm2, %mm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - - - - psubw %mm2, %mm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - - - - psubb %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - - - - psubd %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - - - psubq %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - - - - psubw %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubb %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubd %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubq %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubw %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubb %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubd %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubq %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubw %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubb %xmm19, %xmm19, %xmm19
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubd %xmm19, %xmm19, %xmm19
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubq %xmm19, %xmm19, %xmm19
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubw %xmm19, %xmm19, %xmm19
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubb %ymm19, %ymm19, %ymm19
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubd %ymm19, %ymm19, %ymm19
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubq %ymm19, %ymm19, %ymm19
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubw %ymm19, %ymm19, %ymm19
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubb %zmm19, %zmm19, %zmm19
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubd %zmm19, %zmm19, %zmm19
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubq %zmm19, %zmm19, %zmm19
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubw %zmm19, %zmm19, %zmm19
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubb %xmm19, %xmm19, %xmm21
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubd %xmm19, %xmm19, %xmm21
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubq %xmm19, %xmm19, %xmm21
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubw %xmm19, %xmm19, %xmm21
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubb %ymm19, %ymm19, %ymm21
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubd %ymm19, %ymm19, %ymm21
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubq %ymm19, %ymm19, %ymm21
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubw %ymm19, %ymm19, %ymm21
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubb %zmm19, %zmm19, %zmm21
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubd %zmm19, %zmm19, %zmm21
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubq %zmm19, %zmm19, %zmm21
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpsubw %zmm19, %zmm19, %zmm21
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - - - - andnps %xmm0, %xmm0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - - - andnpd %xmm1, %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vandnps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vandnpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vandnps %ymm2, %ymm2, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vandnpd %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vandnps %zmm2, %zmm2, %zmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vandnpd %zmm1, %zmm1, %zmm1
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - - - - pandn %mm2, %mm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - - - - pandn %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpandn %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpandn %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpandnd %xmm19, %xmm19, %xmm19
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpandnq %xmm19, %xmm19, %xmm19
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpandnd %ymm19, %ymm19, %ymm19
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpandnq %ymm19, %ymm19, %ymm19
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpandnd %zmm19, %zmm19, %zmm19
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpandnq %zmm19, %zmm19, %zmm19
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vandnps %xmm2, %xmm2, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vandnpd %xmm1, %xmm1, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpandn %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vandnps %ymm2, %ymm2, %ymm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vandnpd %ymm1, %ymm1, %ymm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpandn %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vandnps %zmm2, %zmm2, %zmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vandnpd %zmm1, %zmm1, %zmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpandnd %xmm19, %xmm19, %xmm21
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpandnq %xmm19, %xmm19, %xmm21
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpandnd %ymm19, %ymm19, %ymm21
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpandnq %ymm19, %ymm19, %ymm21
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpandnd %zmm19, %zmm19, %zmm21
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpandnq %zmm19, %zmm19, %zmm21
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - - - - xorps %xmm0, %xmm0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - - - - xorpd %xmm1, %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vxorps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vxorpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vxorps %ymm2, %ymm2, %ymm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vxorpd %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vxorps %zmm2, %zmm2, %zmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vxorpd %zmm1, %zmm1, %zmm1
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - - - - pxor %mm2, %mm2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - - - - pxor %xmm2, %xmm2
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpxor %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpxor %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpxord %xmm19, %xmm19, %xmm19
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpxorq %xmm19, %xmm19, %xmm19
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpxord %ymm19, %ymm19, %ymm19
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpxorq %ymm19, %ymm19, %ymm19
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpxord %zmm19, %zmm19, %zmm19
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpxorq %zmm19, %zmm19, %zmm19
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vxorps %xmm4, %xmm4, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vxorpd %xmm1, %xmm1, %xmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vxorps %ymm4, %ymm4, %ymm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vxorpd %ymm1, %ymm1, %ymm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vxorps %zmm4, %zmm4, %zmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vxorpd %zmm1, %zmm1, %zmm3
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpxor %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpxor %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpxord %xmm19, %xmm19, %xmm21
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpxorq %xmm19, %xmm19, %xmm21
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpxord %ymm19, %ymm19, %ymm21
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpxorq %ymm19, %ymm19, %ymm21
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpxord %zmm19, %zmm19, %zmm21
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - - - - - vpxorq %zmm19, %zmm19, %zmm21
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789 012345
+# CHECK-NEXT: Index 0123456789 0123456789
+
+# CHECK: [0,0] DR . . . . . . . subl %eax, %eax
+# CHECK-NEXT: [0,1] DR . . . . . . . subq %rax, %rax
+# CHECK-NEXT: [0,2] DR . . . . . . . xorl %eax, %eax
+# CHECK-NEXT: [0,3] DR . . . . . . . xorq %rax, %rax
+# CHECK-NEXT: [0,4] .DeER. . . . . . . pcmpgtb %mm2, %mm2
+# CHECK-NEXT: [0,5] .D=eER . . . . . . pcmpgtd %mm2, %mm2
+# CHECK-NEXT: [0,6] .D==eER . . . . . . pcmpgtw %mm2, %mm2
+# CHECK-NEXT: [0,7] .DeE--R . . . . . . pcmpgtb %xmm2, %xmm2
+# CHECK-NEXT: [0,8] . DeE-R . . . . . . pcmpgtd %xmm2, %xmm2
+# CHECK-NEXT: [0,9] . DeE-R . . . . . . pcmpgtq %xmm2, %xmm2
+# CHECK-NEXT: [0,10] . DeE-R . . . . . . pcmpgtw %xmm2, %xmm2
+# CHECK-NEXT: [0,11] . D---R . . . . . . vpcmpgtb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,12] . D--R . . . . . . vpcmpgtd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,13] . D--R . . . . . . vpcmpgtq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,14] . D---R . . . . . . vpcmpgtw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,15] . D---R . . . . . . vpcmpgtb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,16] . D--R . . . . . . vpcmpgtd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,17] . D--R . . . . . . vpcmpgtq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,18] . D--R . . . . . . vpcmpgtw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,19] . D--R . . . . . . vpcmpgtb %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,20] . D-R . . . . . . vpcmpgtd %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,21] . D-R . . . . . . vpcmpgtq %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,22] . D--R . . . . . . vpcmpgtw %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,23] . D--R . . . . . . vpcmpgtb %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,24] . .D-R . . . . . . vpcmpgtd %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,25] . .D-R . . . . . . vpcmpgtq %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,26] . .D-R . . . . . . vpcmpgtw %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,27] . .DeER. . . . . . psubb %mm2, %mm2
+# CHECK-NEXT: [0,28] . . DeER . . . . . psubd %mm2, %mm2
+# CHECK-NEXT: [0,29] . . D=eER . . . . . psubq %mm2, %mm2
+# CHECK-NEXT: [0,30] . . D==eER . . . . . psubw %mm2, %mm2
+# CHECK-NEXT: [0,31] . . DeE--R . . . . . psubb %xmm2, %xmm2
+# CHECK-NEXT: [0,32] . . DeE-R . . . . . psubd %xmm2, %xmm2
+# CHECK-NEXT: [0,33] . . DeE-R . . . . . psubq %xmm2, %xmm2
+# CHECK-NEXT: [0,34] . . DeE-R . . . . . psubw %xmm2, %xmm2
+# CHECK-NEXT: [0,35] . . D---R . . . . . vpsubb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,36] . . D--R . . . . . vpsubd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,37] . . D--R . . . . . vpsubq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,38] . . D---R . . . . . vpsubw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,39] . . D---R . . . . . vpsubb %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,40] . . D--R . . . . . vpsubd %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,41] . . D--R . . . . . vpsubq %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,42] . . D--R . . . . . vpsubw %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,43] . . D--R . . . . . vpsubb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,44] . . .D-R . . . . . vpsubd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,45] . . .D-R . . . . . vpsubq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,46] . . .D--R. . . . . vpsubw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,47] . . .D--R. . . . . vpsubb %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,48] . . . D-R. . . . . vpsubd %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,49] . . . D-R. . . . . vpsubq %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,50] . . . D-R. . . . . vpsubw %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,51] . . . D-R. . . . . vpsubb %xmm19, %xmm19, %xmm19
+# CHECK-NEXT: [0,52] . . . DR. . . . . vpsubd %xmm19, %xmm19, %xmm19
+# CHECK-NEXT: [0,53] . . . DR. . . . . vpsubq %xmm19, %xmm19, %xmm19
+# CHECK-NEXT: [0,54] . . . D-R . . . . vpsubw %xmm19, %xmm19, %xmm19
+# CHECK-NEXT: [0,55] . . . D-R . . . . vpsubb %ymm19, %ymm19, %ymm19
+# CHECK-NEXT: [0,56] . . . DR . . . . vpsubd %ymm19, %ymm19, %ymm19
+# CHECK-NEXT: [0,57] . . . DR . . . . vpsubq %ymm19, %ymm19, %ymm19
+# CHECK-NEXT: [0,58] . . . DR . . . . vpsubw %ymm19, %ymm19, %ymm19
+# CHECK-NEXT: [0,59] . . . DR . . . . vpsubb %zmm19, %zmm19, %zmm19
+# CHECK-NEXT: [0,60] . . . DR . . . . vpsubd %zmm19, %zmm19, %zmm19
+# CHECK-NEXT: [0,61] . . . DR . . . . vpsubq %zmm19, %zmm19, %zmm19
+# CHECK-NEXT: [0,62] . . . DR . . . . vpsubw %zmm19, %zmm19, %zmm19
+# CHECK-NEXT: [0,63] . . . DR . . . . vpsubb %xmm19, %xmm19, %xmm21
+# CHECK-NEXT: [0,64] . . . .DR . . . . vpsubd %xmm19, %xmm19, %xmm21
+# CHECK-NEXT: [0,65] . . . .DR . . . . vpsubq %xmm19, %xmm19, %xmm21
+# CHECK-NEXT: [0,66] . . . .DR . . . . vpsubw %xmm19, %xmm19, %xmm21
+# CHECK-NEXT: [0,67] . . . .DR . . . . vpsubb %ymm19, %ymm19, %ymm21
+# CHECK-NEXT: [0,68] . . . . DR . . . . vpsubd %ymm19, %ymm19, %ymm21
+# CHECK-NEXT: [0,69] . . . . DR . . . . vpsubq %ymm19, %ymm19, %ymm21
+# CHECK-NEXT: [0,70] . . . . DR . . . . vpsubw %ymm19, %ymm19, %ymm21
+# CHECK-NEXT: [0,71] . . . . DR . . . . vpsubb %zmm19, %zmm19, %zmm21
+# CHECK-NEXT: [0,72] . . . . DR. . . . vpsubd %zmm19, %zmm19, %zmm21
+# CHECK-NEXT: [0,73] . . . . DR. . . . vpsubq %zmm19, %zmm19, %zmm21
+# CHECK-NEXT: [0,74] . . . . DR. . . . vpsubw %zmm19, %zmm19, %zmm21
+# CHECK-NEXT: [0,75] . . . . DeER . . . andnps %xmm0, %xmm0
+# CHECK-NEXT: [0,76] . . . . DeER . . . andnpd %xmm1, %xmm1
+# CHECK-NEXT: [0,77] . . . . D--R . . . vandnps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: [0,78] . . . . D--R . . . vandnpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: [0,79] . . . . D--R . . . vandnps %ymm2, %ymm2, %ymm2
+# CHECK-NEXT: [0,80] . . . . D-R . . . vandnpd %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: [0,81] . . . . D-R . . . vandnps %zmm2, %zmm2, %zmm2
+# CHECK-NEXT: [0,82] . . . . D-R . . . vandnpd %zmm1, %zmm1, %zmm1
+# CHECK-NEXT: [0,83] . . . . DeER . . . pandn %mm2, %mm2
+# CHECK-NEXT: [0,84] . . . . .DeER. . . pandn %xmm2, %xmm2
+# CHECK-NEXT: [0,85] . . . . .D--R. . . vpandn %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,86] . . . . .D--R. . . vpandn %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,87] . . . . .D--R. . . vpandnd %xmm19, %xmm19, %xmm19
+# CHECK-NEXT: [0,88] . . . . . D-R. . . vpandnq %xmm19, %xmm19, %xmm19
+# CHECK-NEXT: [0,89] . . . . . D-R. . . vpandnd %ymm19, %ymm19, %ymm19
+# CHECK-NEXT: [0,90] . . . . . D-R. . . vpandnq %ymm19, %ymm19, %ymm19
+# CHECK-NEXT: [0,91] . . . . . D-R. . . vpandnd %zmm19, %zmm19, %zmm19
+# CHECK-NEXT: [0,92] . . . . . D-R . . vpandnq %zmm19, %zmm19, %zmm19
+# CHECK-NEXT: [0,93] . . . . . D-R . . vandnps %xmm2, %xmm2, %xmm5
+# CHECK-NEXT: [0,94] . . . . . D-R . . vandnpd %xmm1, %xmm1, %xmm5
+# CHECK-NEXT: [0,95] . . . . . D-R . . vpandn %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,96] . . . . . DR . . vandnps %ymm2, %ymm2, %ymm5
+# CHECK-NEXT: [0,97] . . . . . DR . . vandnpd %ymm1, %ymm1, %ymm5
+# CHECK-NEXT: [0,98] . . . . . DR . . vpandn %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,99] . . . . . DR . . vandnps %zmm2, %zmm2, %zmm5
+# CHECK-NEXT: [0,100] . . . . . DR . . vandnpd %zmm1, %zmm1, %zmm5
+# CHECK-NEXT: [0,101] . . . . . DR . . vpandnd %xmm19, %xmm19, %xmm21
+# CHECK-NEXT: [0,102] . . . . . DR . . vpandnq %xmm19, %xmm19, %xmm21
+# CHECK-NEXT: [0,103] . . . . . DR . . vpandnd %ymm19, %ymm19, %ymm21
+# CHECK-NEXT: [0,104] . . . . . .DR . . vpandnq %ymm19, %ymm19, %ymm21
+# CHECK-NEXT: [0,105] . . . . . .DR . . vpandnd %zmm19, %zmm19, %zmm21
+# CHECK-NEXT: [0,106] . . . . . .DR . . vpandnq %zmm19, %zmm19, %zmm21
+# CHECK-NEXT: [0,107] . . . . . .DeER. . xorps %xmm0, %xmm0
+# CHECK-NEXT: [0,108] . . . . . . DeER . xorpd %xmm1, %xmm1
+# CHECK-NEXT: [0,109] . . . . . . D--R . vxorps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: [0,110] . . . . . . D--R . vxorpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: [0,111] . . . . . . D--R . vxorps %ymm2, %ymm2, %ymm2
+# CHECK-NEXT: [0,112] . . . . . . D-R . vxorpd %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: [0,113] . . . . . . D-R . vxorps %zmm2, %zmm2, %zmm2
+# CHECK-NEXT: [0,114] . . . . . . D-R . vxorpd %zmm1, %zmm1, %zmm1
+# CHECK-NEXT: [0,115] . . . . . . DeER . pxor %mm2, %mm2
+# CHECK-NEXT: [0,116] . . . . . . DeER . pxor %xmm2, %xmm2
+# CHECK-NEXT: [0,117] . . . . . . D--R . vpxor %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,118] . . . . . . D--R . vpxor %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: [0,119] . . . . . . D--R . vpxord %xmm19, %xmm19, %xmm19
+# CHECK-NEXT: [0,120] . . . . . . D-R . vpxorq %xmm19, %xmm19, %xmm19
+# CHECK-NEXT: [0,121] . . . . . . D-R . vpxord %ymm19, %ymm19, %ymm19
+# CHECK-NEXT: [0,122] . . . . . . D-R . vpxorq %ymm19, %ymm19, %ymm19
+# CHECK-NEXT: [0,123] . . . . . . D-R . vpxord %zmm19, %zmm19, %zmm19
+# CHECK-NEXT: [0,124] . . . . . . .D-R . vpxorq %zmm19, %zmm19, %zmm19
+# CHECK-NEXT: [0,125] . . . . . . .D-R . vxorps %xmm4, %xmm4, %xmm5
+# CHECK-NEXT: [0,126] . . . . . . .D-R . vxorpd %xmm1, %xmm1, %xmm3
+# CHECK-NEXT: [0,127] . . . . . . .D-R . vxorps %ymm4, %ymm4, %ymm5
+# CHECK-NEXT: [0,128] . . . . . . . DR . vxorpd %ymm1, %ymm1, %ymm3
+# CHECK-NEXT: [0,129] . . . . . . . DR . vxorps %zmm4, %zmm4, %zmm5
+# CHECK-NEXT: [0,130] . . . . . . . DR . vxorpd %zmm1, %zmm1, %zmm3
+# CHECK-NEXT: [0,131] . . . . . . . DR . vpxor %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,132] . . . . . . . DR. vpxor %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: [0,133] . . . . . . . DR. vpxord %xmm19, %xmm19, %xmm21
+# CHECK-NEXT: [0,134] . . . . . . . DR. vpxorq %xmm19, %xmm19, %xmm21
+# CHECK-NEXT: [0,135] . . . . . . . DR. vpxord %ymm19, %ymm19, %ymm21
+# CHECK-NEXT: [0,136] . . . . . . . DR vpxorq %ymm19, %ymm19, %ymm21
+# CHECK-NEXT: [0,137] . . . . . . . DR vpxord %zmm19, %zmm19, %zmm21
+# CHECK-NEXT: [0,138] . . . . . . . DR vpxorq %zmm19, %zmm19, %zmm21
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 0.0 0.0 0.0 subl %eax, %eax
+# CHECK-NEXT: 1. 1 0.0 0.0 0.0 subq %rax, %rax
+# CHECK-NEXT: 2. 1 0.0 0.0 0.0 xorl %eax, %eax
+# CHECK-NEXT: 3. 1 0.0 0.0 0.0 xorq %rax, %rax
+# CHECK-NEXT: 4. 1 1.0 1.0 0.0 pcmpgtb %mm2, %mm2
+# CHECK-NEXT: 5. 1 2.0 0.0 0.0 pcmpgtd %mm2, %mm2
+# CHECK-NEXT: 6. 1 3.0 0.0 0.0 pcmpgtw %mm2, %mm2
+# CHECK-NEXT: 7. 1 1.0 1.0 2.0 pcmpgtb %xmm2, %xmm2
+# CHECK-NEXT: 8. 1 1.0 1.0 1.0 pcmpgtd %xmm2, %xmm2
+# CHECK-NEXT: 9. 1 1.0 1.0 1.0 pcmpgtq %xmm2, %xmm2
+# CHECK-NEXT: 10. 1 1.0 1.0 1.0 pcmpgtw %xmm2, %xmm2
+# CHECK-NEXT: 11. 1 0.0 0.0 3.0 vpcmpgtb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 12. 1 0.0 0.0 2.0 vpcmpgtd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 13. 1 0.0 0.0 2.0 vpcmpgtq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 14. 1 0.0 0.0 3.0 vpcmpgtw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 15. 1 0.0 0.0 3.0 vpcmpgtb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 16. 1 0.0 0.0 2.0 vpcmpgtd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 17. 1 0.0 0.0 2.0 vpcmpgtq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 18. 1 0.0 0.0 2.0 vpcmpgtw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 19. 1 0.0 0.0 2.0 vpcmpgtb %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 20. 1 0.0 0.0 1.0 vpcmpgtd %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 21. 1 0.0 0.0 1.0 vpcmpgtq %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 22. 1 0.0 0.0 2.0 vpcmpgtw %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 23. 1 0.0 0.0 2.0 vpcmpgtb %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 24. 1 0.0 0.0 1.0 vpcmpgtd %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 25. 1 0.0 0.0 1.0 vpcmpgtq %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 26. 1 0.0 0.0 1.0 vpcmpgtw %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 27. 1 1.0 1.0 0.0 psubb %mm2, %mm2
+# CHECK-NEXT: 28. 1 1.0 0.0 0.0 psubd %mm2, %mm2
+# CHECK-NEXT: 29. 1 2.0 0.0 0.0 psubq %mm2, %mm2
+# CHECK-NEXT: 30. 1 3.0 0.0 0.0 psubw %mm2, %mm2
+# CHECK-NEXT: 31. 1 1.0 1.0 2.0 psubb %xmm2, %xmm2
+# CHECK-NEXT: 32. 1 1.0 1.0 1.0 psubd %xmm2, %xmm2
+# CHECK-NEXT: 33. 1 1.0 1.0 1.0 psubq %xmm2, %xmm2
+# CHECK-NEXT: 34. 1 1.0 1.0 1.0 psubw %xmm2, %xmm2
+# CHECK-NEXT: 35. 1 0.0 0.0 3.0 vpsubb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 36. 1 0.0 0.0 2.0 vpsubd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 37. 1 0.0 0.0 2.0 vpsubq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 38. 1 0.0 0.0 3.0 vpsubw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 39. 1 0.0 0.0 3.0 vpsubb %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 40. 1 0.0 0.0 2.0 vpsubd %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 41. 1 0.0 0.0 2.0 vpsubq %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 42. 1 0.0 0.0 2.0 vpsubw %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 43. 1 0.0 0.0 2.0 vpsubb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 44. 1 0.0 0.0 1.0 vpsubd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 45. 1 0.0 0.0 1.0 vpsubq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 46. 1 0.0 0.0 2.0 vpsubw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 47. 1 0.0 0.0 2.0 vpsubb %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 48. 1 0.0 0.0 1.0 vpsubd %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 49. 1 0.0 0.0 1.0 vpsubq %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 50. 1 0.0 0.0 1.0 vpsubw %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 51. 1 0.0 0.0 1.0 vpsubb %xmm19, %xmm19, %xmm19
+# CHECK-NEXT: 52. 1 0.0 0.0 0.0 vpsubd %xmm19, %xmm19, %xmm19
+# CHECK-NEXT: 53. 1 0.0 0.0 0.0 vpsubq %xmm19, %xmm19, %xmm19
+# CHECK-NEXT: 54. 1 0.0 0.0 1.0 vpsubw %xmm19, %xmm19, %xmm19
+# CHECK-NEXT: 55. 1 0.0 0.0 1.0 vpsubb %ymm19, %ymm19, %ymm19
+# CHECK-NEXT: 56. 1 0.0 0.0 0.0 vpsubd %ymm19, %ymm19, %ymm19
+# CHECK-NEXT: 57. 1 0.0 0.0 0.0 vpsubq %ymm19, %ymm19, %ymm19
+# CHECK-NEXT: 58. 1 0.0 0.0 0.0 vpsubw %ymm19, %ymm19, %ymm19
+# CHECK-NEXT: 59. 1 0.0 0.0 0.0 vpsubb %zmm19, %zmm19, %zmm19
+# CHECK-NEXT: 60. 1 0.0 0.0 0.0 vpsubd %zmm19, %zmm19, %zmm19
+# CHECK-NEXT: 61. 1 0.0 0.0 0.0 vpsubq %zmm19, %zmm19, %zmm19
+# CHECK-NEXT: 62. 1 0.0 0.0 0.0 vpsubw %zmm19, %zmm19, %zmm19
+# CHECK-NEXT: 63. 1 0.0 0.0 0.0 vpsubb %xmm19, %xmm19, %xmm21
+# CHECK-NEXT: 64. 1 0.0 0.0 0.0 vpsubd %xmm19, %xmm19, %xmm21
+# CHECK-NEXT: 65. 1 0.0 0.0 0.0 vpsubq %xmm19, %xmm19, %xmm21
+# CHECK-NEXT: 66. 1 0.0 0.0 0.0 vpsubw %xmm19, %xmm19, %xmm21
+# CHECK-NEXT: 67. 1 0.0 0.0 0.0 vpsubb %ymm19, %ymm19, %ymm21
+# CHECK-NEXT: 68. 1 0.0 0.0 0.0 vpsubd %ymm19, %ymm19, %ymm21
+# CHECK-NEXT: 69. 1 0.0 0.0 0.0 vpsubq %ymm19, %ymm19, %ymm21
+# CHECK-NEXT: 70. 1 0.0 0.0 0.0 vpsubw %ymm19, %ymm19, %ymm21
+# CHECK-NEXT: 71. 1 0.0 0.0 0.0 vpsubb %zmm19, %zmm19, %zmm21
+# CHECK-NEXT: 72. 1 0.0 0.0 0.0 vpsubd %zmm19, %zmm19, %zmm21
+# CHECK-NEXT: 73. 1 0.0 0.0 0.0 vpsubq %zmm19, %zmm19, %zmm21
+# CHECK-NEXT: 74. 1 0.0 0.0 0.0 vpsubw %zmm19, %zmm19, %zmm21
+# CHECK-NEXT: 75. 1 1.0 1.0 0.0 andnps %xmm0, %xmm0
+# CHECK-NEXT: 76. 1 1.0 1.0 0.0 andnpd %xmm1, %xmm1
+# CHECK-NEXT: 77. 1 0.0 0.0 2.0 vandnps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: 78. 1 0.0 0.0 2.0 vandnpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: 79. 1 0.0 0.0 2.0 vandnps %ymm2, %ymm2, %ymm2
+# CHECK-NEXT: 80. 1 0.0 0.0 1.0 vandnpd %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: 81. 1 0.0 0.0 1.0 vandnps %zmm2, %zmm2, %zmm2
+# CHECK-NEXT: 82. 1 0.0 0.0 1.0 vandnpd %zmm1, %zmm1, %zmm1
+# CHECK-NEXT: 83. 1 1.0 1.0 0.0 pandn %mm2, %mm2
+# CHECK-NEXT: 84. 1 1.0 1.0 0.0 pandn %xmm2, %xmm2
+# CHECK-NEXT: 85. 1 0.0 0.0 2.0 vpandn %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 86. 1 0.0 0.0 2.0 vpandn %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 87. 1 0.0 0.0 2.0 vpandnd %xmm19, %xmm19, %xmm19
+# CHECK-NEXT: 88. 1 0.0 0.0 1.0 vpandnq %xmm19, %xmm19, %xmm19
+# CHECK-NEXT: 89. 1 0.0 0.0 1.0 vpandnd %ymm19, %ymm19, %ymm19
+# CHECK-NEXT: 90. 1 0.0 0.0 1.0 vpandnq %ymm19, %ymm19, %ymm19
+# CHECK-NEXT: 91. 1 0.0 0.0 1.0 vpandnd %zmm19, %zmm19, %zmm19
+# CHECK-NEXT: 92. 1 0.0 0.0 1.0 vpandnq %zmm19, %zmm19, %zmm19
+# CHECK-NEXT: 93. 1 0.0 0.0 1.0 vandnps %xmm2, %xmm2, %xmm5
+# CHECK-NEXT: 94. 1 0.0 0.0 1.0 vandnpd %xmm1, %xmm1, %xmm5
+# CHECK-NEXT: 95. 1 0.0 0.0 1.0 vpandn %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 96. 1 0.0 0.0 0.0 vandnps %ymm2, %ymm2, %ymm5
+# CHECK-NEXT: 97. 1 0.0 0.0 0.0 vandnpd %ymm1, %ymm1, %ymm5
+# CHECK-NEXT: 98. 1 0.0 0.0 0.0 vpandn %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 99. 1 0.0 0.0 0.0 vandnps %zmm2, %zmm2, %zmm5
+# CHECK-NEXT: 100. 1 0.0 0.0 0.0 vandnpd %zmm1, %zmm1, %zmm5
+# CHECK-NEXT: 101. 1 0.0 0.0 0.0 vpandnd %xmm19, %xmm19, %xmm21
+# CHECK-NEXT: 102. 1 0.0 0.0 0.0 vpandnq %xmm19, %xmm19, %xmm21
+# CHECK-NEXT: 103. 1 0.0 0.0 0.0 vpandnd %ymm19, %ymm19, %ymm21
+# CHECK-NEXT: 104. 1 0.0 0.0 0.0 vpandnq %ymm19, %ymm19, %ymm21
+# CHECK-NEXT: 105. 1 0.0 0.0 0.0 vpandnd %zmm19, %zmm19, %zmm21
+# CHECK-NEXT: 106. 1 0.0 0.0 0.0 vpandnq %zmm19, %zmm19, %zmm21
+# CHECK-NEXT: 107. 1 1.0 1.0 0.0 xorps %xmm0, %xmm0
+# CHECK-NEXT: 108. 1 1.0 1.0 0.0 xorpd %xmm1, %xmm1
+# CHECK-NEXT: 109. 1 0.0 0.0 2.0 vxorps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: 110. 1 0.0 0.0 2.0 vxorpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: 111. 1 0.0 0.0 2.0 vxorps %ymm2, %ymm2, %ymm2
+# CHECK-NEXT: 112. 1 0.0 0.0 1.0 vxorpd %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: 113. 1 0.0 0.0 1.0 vxorps %zmm2, %zmm2, %zmm2
+# CHECK-NEXT: 114. 1 0.0 0.0 1.0 vxorpd %zmm1, %zmm1, %zmm1
+# CHECK-NEXT: 115. 1 1.0 1.0 0.0 pxor %mm2, %mm2
+# CHECK-NEXT: 116. 1 1.0 1.0 0.0 pxor %xmm2, %xmm2
+# CHECK-NEXT: 117. 1 0.0 0.0 2.0 vpxor %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: 118. 1 0.0 0.0 2.0 vpxor %ymm3, %ymm3, %ymm3
+# CHECK-NEXT: 119. 1 0.0 0.0 2.0 vpxord %xmm19, %xmm19, %xmm19
+# CHECK-NEXT: 120. 1 0.0 0.0 1.0 vpxorq %xmm19, %xmm19, %xmm19
+# CHECK-NEXT: 121. 1 0.0 0.0 1.0 vpxord %ymm19, %ymm19, %ymm19
+# CHECK-NEXT: 122. 1 0.0 0.0 1.0 vpxorq %ymm19, %ymm19, %ymm19
+# CHECK-NEXT: 123. 1 0.0 0.0 1.0 vpxord %zmm19, %zmm19, %zmm19
+# CHECK-NEXT: 124. 1 0.0 0.0 1.0 vpxorq %zmm19, %zmm19, %zmm19
+# CHECK-NEXT: 125. 1 0.0 0.0 1.0 vxorps %xmm4, %xmm4, %xmm5
+# CHECK-NEXT: 126. 1 0.0 0.0 1.0 vxorpd %xmm1, %xmm1, %xmm3
+# CHECK-NEXT: 127. 1 0.0 0.0 1.0 vxorps %ymm4, %ymm4, %ymm5
+# CHECK-NEXT: 128. 1 0.0 0.0 0.0 vxorpd %ymm1, %ymm1, %ymm3
+# CHECK-NEXT: 129. 1 0.0 0.0 0.0 vxorps %zmm4, %zmm4, %zmm5
+# CHECK-NEXT: 130. 1 0.0 0.0 0.0 vxorpd %zmm1, %zmm1, %zmm3
+# CHECK-NEXT: 131. 1 0.0 0.0 0.0 vpxor %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: 132. 1 0.0 0.0 0.0 vpxor %ymm3, %ymm3, %ymm5
+# CHECK-NEXT: 133. 1 0.0 0.0 0.0 vpxord %xmm19, %xmm19, %xmm21
+# CHECK-NEXT: 134. 1 0.0 0.0 0.0 vpxorq %xmm19, %xmm19, %xmm21
+# CHECK-NEXT: 135. 1 0.0 0.0 0.0 vpxord %ymm19, %ymm19, %ymm21
+# CHECK-NEXT: 136. 1 0.0 0.0 0.0 vpxorq %ymm19, %ymm19, %ymm21
+# CHECK-NEXT: 137. 1 0.0 0.0 0.0 vpxord %zmm19, %zmm19, %zmm21
+# CHECK-NEXT: 138. 1 0.0 0.0 0.0 vpxorq %zmm19, %zmm19, %zmm21
+# CHECK-NEXT: 1 0.2 0.1 0.9 <total>
>From 884bef72ad71cfa26ea1d799d9b117da8553080a Mon Sep 17 00:00:00 2001
From: zhangxiaomeng <zhangxiaomeng at hygon.cn>
Date: Fri, 15 May 2026 18:09:50 +0800
Subject: [PATCH 09/11] Use a new prefix in schedule model.
---
llvm/lib/Target/X86/X86ScheduleC864GM4.td | 912 ++--
llvm/lib/Target/X86/X86ScheduleC864GM7.td | 3690 ++++++++---------
.../tools/llvm-mca/X86/4GM4/resources-adx.s | 38 +-
.../tools/llvm-mca/X86/4GM4/resources-aes.s | 38 +-
.../tools/llvm-mca/X86/4GM4/resources-avx1.s | 38 +-
.../tools/llvm-mca/X86/4GM4/resources-avx2.s | 38 +-
.../tools/llvm-mca/X86/4GM4/resources-bmi1.s | 38 +-
.../tools/llvm-mca/X86/4GM4/resources-bmi2.s | 38 +-
.../llvm-mca/X86/4GM4/resources-clflushopt.s | 38 +-
.../llvm-mca/X86/4GM4/resources-clzero.s | 38 +-
.../tools/llvm-mca/X86/4GM4/resources-cmov.s | 38 +-
.../llvm-mca/X86/4GM4/resources-cmpxchg.s | 38 +-
.../tools/llvm-mca/X86/4GM4/resources-f16c.s | 38 +-
.../tools/llvm-mca/X86/4GM4/resources-fma.s | 38 +-
.../llvm-mca/X86/4GM4/resources-fsgsbase.s | 38 +-
.../tools/llvm-mca/X86/4GM4/resources-lea.s | 38 +-
.../tools/llvm-mca/X86/4GM4/resources-lzcnt.s | 38 +-
.../tools/llvm-mca/X86/4GM4/resources-mmx.s | 38 +-
.../tools/llvm-mca/X86/4GM4/resources-movbe.s | 38 +-
.../llvm-mca/X86/4GM4/resources-mwaitx.s | 38 +-
.../llvm-mca/X86/4GM4/resources-pclmul.s | 38 +-
.../llvm-mca/X86/4GM4/resources-popcnt.s | 38 +-
.../llvm-mca/X86/4GM4/resources-prefetchw.s | 38 +-
.../llvm-mca/X86/4GM4/resources-rdrand.s | 38 +-
.../llvm-mca/X86/4GM4/resources-rdseed.s | 38 +-
.../tools/llvm-mca/X86/4GM4/resources-sha.s | 38 +-
.../tools/llvm-mca/X86/4GM4/resources-sse1.s | 38 +-
.../tools/llvm-mca/X86/4GM4/resources-sse2.s | 38 +-
.../tools/llvm-mca/X86/4GM4/resources-sse3.s | 38 +-
.../tools/llvm-mca/X86/4GM4/resources-sse41.s | 38 +-
.../tools/llvm-mca/X86/4GM4/resources-sse42.s | 38 +-
.../tools/llvm-mca/X86/4GM4/resources-sse4a.s | 38 +-
.../tools/llvm-mca/X86/4GM4/resources-ssse3.s | 38 +-
.../llvm-mca/X86/4GM4/resources-x86_32.s | 38 +-
.../llvm-mca/X86/4GM4/resources-x86_64.s | 78 +-
.../tools/llvm-mca/X86/4GM4/resources-x87.s | 38 +-
.../tools/llvm-mca/X86/4GM4/resources-xsave.s | 38 +-
.../tools/llvm-mca/X86/4GM4/zero-idioms.s | 42 +-
.../X86/4GM7/independent-load-stores.s | 46 +-
.../partially-overlapping-group-resources.s | 46 +-
.../tools/llvm-mca/X86/4GM7/resources-adx.s | 46 +-
.../tools/llvm-mca/X86/4GM7/resources-aes.s | 46 +-
.../tools/llvm-mca/X86/4GM7/resources-avx1.s | 46 +-
.../tools/llvm-mca/X86/4GM7/resources-avx2.s | 46 +-
.../llvm-mca/X86/4GM7/resources-avx512.s | 46 +-
.../X86/4GM7/resources-avx512bitalg.s | 46 +-
.../X86/4GM7/resources-avx512bitalgvl.s | 46 +-
.../llvm-mca/X86/4GM7/resources-avx512bw.s | 46 +-
.../llvm-mca/X86/4GM7/resources-avx512bwvl.s | 46 +-
.../llvm-mca/X86/4GM7/resources-avx512cd.s | 46 +-
.../llvm-mca/X86/4GM7/resources-avx512cdvl.s | 46 +-
.../llvm-mca/X86/4GM7/resources-avx512dq.s | 46 +-
.../llvm-mca/X86/4GM7/resources-avx512dqvl.s | 46 +-
.../llvm-mca/X86/4GM7/resources-avx512gfni.s | 46 +-
.../X86/4GM7/resources-avx512gfnivl.s | 46 +-
.../llvm-mca/X86/4GM7/resources-avx512ifma.s | 46 +-
.../X86/4GM7/resources-avx512ifmavl.s | 46 +-
.../llvm-mca/X86/4GM7/resources-avx512vaes.s | 46 +-
.../X86/4GM7/resources-avx512vaesvl.s | 46 +-
.../llvm-mca/X86/4GM7/resources-avx512vbmi.s | 46 +-
.../llvm-mca/X86/4GM7/resources-avx512vbmi2.s | 46 +-
.../X86/4GM7/resources-avx512vbmi2vl.s | 46 +-
.../X86/4GM7/resources-avx512vbmivl.s | 46 +-
.../llvm-mca/X86/4GM7/resources-avx512vl.s | 46 +-
.../llvm-mca/X86/4GM7/resources-avx512vnni.s | 46 +-
.../X86/4GM7/resources-avx512vnnivl.s | 46 +-
.../X86/4GM7/resources-avx512vpclmulqdq.s | 46 +-
.../X86/4GM7/resources-avx512vpclmulqdqvl.s | 46 +-
.../X86/4GM7/resources-avx512vpopcntdq.s | 46 +-
.../X86/4GM7/resources-avx512vpopcntdqvl.s | 46 +-
.../llvm-mca/X86/4GM7/resources-avxgfni.s | 46 +-
.../llvm-mca/X86/4GM7/resources-avxvnni.s | 46 +-
.../tools/llvm-mca/X86/4GM7/resources-bmi1.s | 46 +-
.../tools/llvm-mca/X86/4GM7/resources-bmi2.s | 46 +-
.../llvm-mca/X86/4GM7/resources-clflushopt.s | 46 +-
.../tools/llvm-mca/X86/4GM7/resources-clwb.s | 46 +-
.../tools/llvm-mca/X86/4GM7/resources-cmov.s | 46 +-
.../llvm-mca/X86/4GM7/resources-cmpxchg.s | 46 +-
.../tools/llvm-mca/X86/4GM7/resources-f16c.s | 46 +-
.../tools/llvm-mca/X86/4GM7/resources-fma.s | 46 +-
.../llvm-mca/X86/4GM7/resources-fsgsbase.s | 46 +-
.../tools/llvm-mca/X86/4GM7/resources-gfni.s | 46 +-
.../tools/llvm-mca/X86/4GM7/resources-lea.s | 46 +-
.../tools/llvm-mca/X86/4GM7/resources-lzcnt.s | 46 +-
.../tools/llvm-mca/X86/4GM7/resources-mmx.s | 46 +-
.../tools/llvm-mca/X86/4GM7/resources-movbe.s | 46 +-
.../llvm-mca/X86/4GM7/resources-mwaitx.s | 46 +-
.../llvm-mca/X86/4GM7/resources-pclmul.s | 46 +-
.../llvm-mca/X86/4GM7/resources-popcnt.s | 46 +-
.../llvm-mca/X86/4GM7/resources-prefetchw.s | 46 +-
.../llvm-mca/X86/4GM7/resources-rdrand.s | 46 +-
.../llvm-mca/X86/4GM7/resources-rdseed.s | 46 +-
.../tools/llvm-mca/X86/4GM7/resources-sha.s | 46 +-
.../tools/llvm-mca/X86/4GM7/resources-sse1.s | 46 +-
.../tools/llvm-mca/X86/4GM7/resources-sse2.s | 46 +-
.../tools/llvm-mca/X86/4GM7/resources-sse3.s | 46 +-
.../tools/llvm-mca/X86/4GM7/resources-sse41.s | 46 +-
.../tools/llvm-mca/X86/4GM7/resources-sse42.s | 46 +-
.../tools/llvm-mca/X86/4GM7/resources-sse4a.s | 46 +-
.../tools/llvm-mca/X86/4GM7/resources-ssse3.s | 46 +-
.../tools/llvm-mca/X86/4GM7/resources-vaes.s | 46 +-
.../llvm-mca/X86/4GM7/resources-vpclmulqdq.s | 46 +-
.../llvm-mca/X86/4GM7/resources-x86_32.s | 46 +-
.../llvm-mca/X86/4GM7/resources-x86_64.s | 86 +-
.../tools/llvm-mca/X86/4GM7/resources-x87.s | 46 +-
.../tools/llvm-mca/X86/4GM7/resources-xsave.s | 46 +-
.../tools/llvm-mca/X86/4GM7/zero-idioms.s | 50 +-
107 files changed, 4616 insertions(+), 4616 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ScheduleC864GM4.td b/llvm/lib/Target/X86/X86ScheduleC864GM4.td
index b1a9d4b8bafde..eea3e1bbaf337 100644
--- a/llvm/lib/Target/X86/X86ScheduleC864GM4.td
+++ b/llvm/lib/Target/X86/X86ScheduleC864GM4.td
@@ -37,42 +37,42 @@ let SchedModel = C864GM4Model in {
//===----------------------------------------------------------------------===//
// The C864GM4 has 4 ALUs.
-def 4GM4ALU0 : ProcResource<1>;
-def 4GM4ALU1 : ProcResource<1>;
-def 4GM4ALU2 : ProcResource<1>;
-def 4GM4ALU3 : ProcResource<1>;
+def C4GM4ALU0 : ProcResource<1>;
+def C4GM4ALU1 : ProcResource<1>;
+def C4GM4ALU2 : ProcResource<1>;
+def C4GM4ALU3 : ProcResource<1>;
-def 4GM4ALU23 : ProcResGroup<[4GM4ALU2, 4GM4ALU3]>;
+def C4GM4ALU23 : ProcResGroup<[C4GM4ALU2, C4GM4ALU3]>;
// BRU on ALU0 and ALU3.
-defvar 4GM4BRU0 = 4GM4ALU0;
-defvar 4GM4BRU1 = 4GM4ALU3;
+defvar C4GM4BRU0 = C4GM4ALU0;
+defvar C4GM4BRU1 = C4GM4ALU3;
-def 4GM4BRU01 : ProcResGroup<[4GM4BRU0, 4GM4BRU1]>;
+def C4GM4BRU01 : ProcResGroup<[C4GM4BRU0, C4GM4BRU1]>;
// 72 Entry (4x18 entries) integer Scheduler.
-def 4GM4ALU : ProcResGroup<[4GM4ALU0, 4GM4BRU0,
- 4GM4ALU1,
- 4GM4ALU2,
- 4GM4ALU3, 4GM4BRU1]> {
+def C4GM4ALU : ProcResGroup<[C4GM4ALU0, C4GM4BRU0,
+ C4GM4ALU1,
+ C4GM4ALU2,
+ C4GM4ALU3, C4GM4BRU1]> {
let BufferSize = 72;
}
// The integer physical register file consists of 192 registers.
-def 4GM4IntegerPRF : RegisterFile<192,
- [GR64, CCR],
- [1, 1],
- [1, 0],
- 6, // Max moves that can be eliminated per cycle.
- 0>; // Restrict move elimination to zero regs.
+def C4GM4IntegerPRF : RegisterFile<192,
+ [GR64, CCR],
+ [1, 1],
+ [1, 0],
+ 6, // Max moves that can be eliminated per cycle.
+ 0>; // Restrict move elimination to zero regs.
// AGU
// The C864GM4 has 3 AGUs.
-def 4GM4AGU0 : ProcResource<1>;
-def 4GM4AGU1 : ProcResource<1>;
-def 4GM4AGU2 : ProcResource<1>;
+def C4GM4AGU0 : ProcResource<1>;
+def C4GM4AGU1 : ProcResource<1>;
+def C4GM4AGU2 : ProcResource<1>;
// 28 Entry (1x28 entries) AGU group.
-def 4GM4AGU : ProcResGroup<[4GM4AGU0, 4GM4AGU1, 4GM4AGU2]> {
+def C4GM4AGU : ProcResGroup<[C4GM4AGU0, C4GM4AGU1, C4GM4AGU2]> {
let BufferSize = 28;
}
@@ -81,28 +81,28 @@ def 4GM4AGU : ProcResGroup<[4GM4AGU0, 4GM4AGU1, 4GM4AGU2]> {
//===----------------------------------------------------------------------===//
// The C864GM4 has 4 FPUs.
-def 4GM4FPU0 : ProcResource<1>;
-def 4GM4FPU1 : ProcResource<1>;
-def 4GM4FPU2 : ProcResource<1>;
-def 4GM4FPU3 : ProcResource<1>;
+def C4GM4FPU0 : ProcResource<1>;
+def C4GM4FPU1 : ProcResource<1>;
+def C4GM4FPU2 : ProcResource<1>;
+def C4GM4FPU3 : ProcResource<1>;
-def 4GM4FPU01 : ProcResGroup<[4GM4FPU0, 4GM4FPU1]>;
-def 4GM4FPU13 : ProcResGroup<[4GM4FPU1, 4GM4FPU3]>;
-def 4GM4FPU23 : ProcResGroup<[4GM4FPU2, 4GM4FPU3]>;
-def 4GM4FPU02 : ProcResGroup<[4GM4FPU0, 4GM4FPU2]>;
+def C4GM4FPU01 : ProcResGroup<[C4GM4FPU0, C4GM4FPU1]>;
+def C4GM4FPU13 : ProcResGroup<[C4GM4FPU1, C4GM4FPU3]>;
+def C4GM4FPU23 : ProcResGroup<[C4GM4FPU2, C4GM4FPU3]>;
+def C4GM4FPU02 : ProcResGroup<[C4GM4FPU0, C4GM4FPU2]>;
// 48 Entry (4x12 entries) floating-point Scheduler.
-def 4GM4FPU : ProcResGroup<[4GM4FPU0, 4GM4FPU1, 4GM4FPU2, 4GM4FPU3]> {
+def C4GM4FPU : ProcResGroup<[C4GM4FPU0, C4GM4FPU1, C4GM4FPU2, C4GM4FPU3]> {
let BufferSize = 48;
}
// The floating point physical register file consists of 176 registers.
-def 4GM4FpuPRF : RegisterFile<176,
- [VR64, VR128, VR256],
- [1, 1, 1],
- [0, 1, 1],
- 6, // Max moves that can be eliminated per cycle.
- 0>; // Restrict move elimination to zero regs.
+def C4GM4FpuPRF : RegisterFile<176,
+ [VR64, VR128, VR256],
+ [1, 1, 1],
+ [0, 1, 1],
+ 6, // Max moves that can be eliminated per cycle.
+ 0>; // Restrict move elimination to zero regs.
//===----------------------------------------------------------------------===//
// Load-Store Unit
@@ -110,23 +110,23 @@ def 4GM4FpuPRF : RegisterFile<176,
// Load/Store Units and Memory Queues
// The C864GM4 has 3 LS Units.
-def 4GM4LSU : ProcResource<3>;
+def C4GM4LSU : ProcResource<3>;
// The two of LSU can be loads.
-let Super = 4GM4LSU in
-def 4GM4Load : ProcResource<2> {
+let Super = C4GM4LSU in
+def C4GM4Load : ProcResource<2> {
// The LDQ is 50.
let BufferSize = 50;
}
-def 4GM4LoadQueue : LoadQueue<4GM4Load>;
+def C4GM4LoadQueue : LoadQueue<C4GM4Load>;
// All three of LSU can be loads.
-let Super = 4GM4LSU in
-def 4GM4Store : ProcResource<3> {
+let Super = C4GM4LSU in
+def C4GM4Store : ProcResource<3> {
// The STQ is 52.
let BufferSize = 52;
}
-def 4GM4StoreQueue : StoreQueue<4GM4Store>;
+def C4GM4StoreQueue : StoreQueue<C4GM4Store>;
def : ReadAdvance<ReadAfterLd, C864GM4Model.LoadLatency>;
def : ReadAdvance<ReadAfterVecLd, C864GM4Model.VecLoadLatency>;
@@ -138,7 +138,7 @@ def : ReadAdvance<ReadInt2Fpu, 0>;
// Retire Control Unit
//===----------------------------------------------------------------------===//
-def 4GM4RCU : RetireControlUnit<C864GM4Model.MicroOpBufferSize, 8>;
+def C4GM4RCU : RetireControlUnit<C864GM4Model.MicroOpBufferSize, 8>;
//===----------------------------------------------------------------------===//
// Basic helper classes.
@@ -151,7 +151,7 @@ def 4GM4RCU : RetireControlUnit<C864GM4Model.MicroOpBufferSize, 8>;
// folded loads.
-multiclass __4GM4WriteRes<SchedWrite SchedRW, list<ProcResourceKind> ExePorts,
+multiclass __C4GM4WriteRes<SchedWrite SchedRW, list<ProcResourceKind> ExePorts,
int Lat = 1, list<int> Res = [], int UOps = 1> {
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
@@ -160,14 +160,14 @@ multiclass __4GM4WriteRes<SchedWrite SchedRW, list<ProcResourceKind> ExePorts,
}
}
-multiclass __4GM4WriteResPair<X86FoldableSchedWrite SchedRW,
+multiclass __C4GM4WriteResPair<X86FoldableSchedWrite SchedRW,
list<ProcResourceKind> ExePorts, int Lat,
list<int> Res, int UOps, int LoadLat, int LoadUOps,
ProcResourceKind AGU, int LoadRes> {
- defm : __4GM4WriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
+ defm : __C4GM4WriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
- defm : __4GM4WriteRes<SchedRW.Folded,
- !listconcat([AGU, 4GM4Load], ExePorts),
+ defm : __C4GM4WriteRes<SchedRW.Folded,
+ !listconcat([AGU, C4GM4Load], ExePorts),
!add(LoadLat, Lat),
!if(!and(!empty(Res), !eq(LoadRes, 1)),
[],
@@ -179,80 +179,80 @@ multiclass __4GM4WriteResPair<X86FoldableSchedWrite SchedRW,
}
// For classes without folded loads.
-multiclass 4GM4WriteRes<SchedWrite SchedRW,
+multiclass C4GM4WriteRes<SchedWrite SchedRW,
list<ProcResourceKind> ExePorts, int Lat = 1,
list<int> Res = [], int UOps = 1> {
- defm : __4GM4WriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
+ defm : __C4GM4WriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
}
// For classes with folded loads.
-multiclass 4GM4WriteResIntPair<X86FoldableSchedWrite SchedRW,
+multiclass C4GM4WriteResIntPair<X86FoldableSchedWrite SchedRW,
list<ProcResourceKind> ExePorts, int Lat = 1,
list<int> Res = [], int UOps = 1,
int LoadUOps = 0, int LoadRes = 1> {
- defm : __4GM4WriteResPair<SchedRW, ExePorts, Lat, Res, UOps,
+ defm : __C4GM4WriteResPair<SchedRW, ExePorts, Lat, Res, UOps,
C864GM4Model.LoadLatency,
- LoadUOps, 4GM4AGU, LoadRes>;
+ LoadUOps, C4GM4AGU, LoadRes>;
}
-multiclass 4GM4WriteResFPPair<X86FoldableSchedWrite SchedRW,
+multiclass C4GM4WriteResFPPair<X86FoldableSchedWrite SchedRW,
list<ProcResourceKind> ExePorts, int Lat = 1,
list<int> Res = [], int UOps = 1,
int LoadUOps = 0, int LoadRes = 1> {
- defm : __4GM4WriteResPair<SchedRW, ExePorts, Lat, Res, UOps,
+ defm : __C4GM4WriteResPair<SchedRW, ExePorts, Lat, Res, UOps,
C864GM4Model.VecLoadLatency,
- LoadUOps, 4GM4AGU, LoadRes>;
+ LoadUOps, C4GM4AGU, LoadRes>;
}
// Microcoded Instructions
-def 4GM4WriteMicrocoded : SchedWriteRes<[]> {
+def C4GM4WriteMicrocoded : SchedWriteRes<[]> {
let Latency = 100;
}
-def : SchedAlias<WriteMicrocoded, 4GM4WriteMicrocoded>;
-def : SchedAlias<WriteSystem, 4GM4WriteMicrocoded>;
-def : SchedAlias<WriteFCMOV, 4GM4WriteMicrocoded>;
-def : SchedAlias<WriteLDMXCSR, 4GM4WriteMicrocoded>;
-def : SchedAlias<WriteSTMXCSR, 4GM4WriteMicrocoded>;
-def : SchedAlias<WriteDPPS, 4GM4WriteMicrocoded>;
-def : SchedAlias<WriteDPPSY, 4GM4WriteMicrocoded>;
-def : SchedAlias<WriteDPPSLd, 4GM4WriteMicrocoded>;
-def : SchedAlias<WriteDPPSYLd,4GM4WriteMicrocoded>;
-
-def 4GM4WritePDEP_PEXT : SchedWriteRes<[]>;
-def : InstRW<[4GM4WritePDEP_PEXT], (instregex "PDEP(32|64)rr",
- "PEXT(32|64)rr")>;
-def : SchedAlias<4GM4WritePDEP_PEXT, 4GM4WriteMicrocoded>;
-def 4GM4WritePDEP_PEXTLd : SchedWriteRes<[]>;
-def : InstRW<[4GM4WritePDEP_PEXTLd], (instregex "PDEP(32|64)rm",
- "PEXT(32|64)rm")>;
-def : SchedAlias<4GM4WritePDEP_PEXTLd, 4GM4WriteMicrocoded>;
+def : SchedAlias<WriteMicrocoded, C4GM4WriteMicrocoded>;
+def : SchedAlias<WriteSystem, C4GM4WriteMicrocoded>;
+def : SchedAlias<WriteFCMOV, C4GM4WriteMicrocoded>;
+def : SchedAlias<WriteLDMXCSR, C4GM4WriteMicrocoded>;
+def : SchedAlias<WriteSTMXCSR, C4GM4WriteMicrocoded>;
+def : SchedAlias<WriteDPPS, C4GM4WriteMicrocoded>;
+def : SchedAlias<WriteDPPSY, C4GM4WriteMicrocoded>;
+def : SchedAlias<WriteDPPSLd, C4GM4WriteMicrocoded>;
+def : SchedAlias<WriteDPPSYLd,C4GM4WriteMicrocoded>;
+
+def C4GM4WritePDEP_PEXT : SchedWriteRes<[]>;
+def : InstRW<[C4GM4WritePDEP_PEXT], (instregex "PDEP(32|64)rr",
+ "PEXT(32|64)rr")>;
+def : SchedAlias<C4GM4WritePDEP_PEXT, C4GM4WriteMicrocoded>;
+def C4GM4WritePDEP_PEXTLd : SchedWriteRes<[]>;
+def : InstRW<[C4GM4WritePDEP_PEXTLd], (instregex "PDEP(32|64)rm",
+ "PEXT(32|64)rm")>;
+def : SchedAlias<C4GM4WritePDEP_PEXTLd, C4GM4WriteMicrocoded>;
// Integer Instructions
-defm : 4GM4WriteRes<WriteRMW, [4GM4AGU, 4GM4Store]>;
+defm : C4GM4WriteRes<WriteRMW, [C4GM4AGU, C4GM4Store]>;
-defm : 4GM4WriteRes<WriteStore, [4GM4AGU, 4GM4Store]>;
-defm : 4GM4WriteRes<WriteStoreNT, [4GM4AGU, 4GM4Store]>;
-defm : 4GM4WriteRes<WriteMove, [4GM4ALU]>;
-defm : 4GM4WriteRes<WriteLoad, [4GM4AGU, 4GM4Load], !add(1, C864GM4Model.LoadLatency)>;
+defm : C4GM4WriteRes<WriteStore, [C4GM4AGU, C4GM4Store]>;
+defm : C4GM4WriteRes<WriteStoreNT, [C4GM4AGU, C4GM4Store]>;
+defm : C4GM4WriteRes<WriteMove, [C4GM4ALU]>;
+defm : C4GM4WriteRes<WriteLoad, [C4GM4AGU, C4GM4Load], !add(1, C864GM4Model.LoadLatency)>;
-defm : 4GM4WriteRes<WriteVecMaskedGatherWriteback, [], !add(1, C864GM4Model.VecLoadLatency)>;
+defm : C4GM4WriteRes<WriteVecMaskedGatherWriteback, [], !add(1, C864GM4Model.VecLoadLatency)>;
-defm : 4GM4WriteRes<WriteZero, [], 0, [], 1>;
-defm : 4GM4WriteRes<WriteLEA, [4GM4ALU]>;
-defm : 4GM4WriteResIntPair<WriteALU, [4GM4ALU], 1>;
-defm : 4GM4WriteResIntPair<WriteADC, [4GM4ALU], 1>;
+defm : C4GM4WriteRes<WriteZero, [], 0, [], 1>;
+defm : C4GM4WriteRes<WriteLEA, [C4GM4ALU]>;
+defm : C4GM4WriteResIntPair<WriteALU, [C4GM4ALU], 1>;
+defm : C4GM4WriteResIntPair<WriteADC, [C4GM4ALU], 1>;
// This write is used for slow LEA instructions.
-def 4GM4Write3OpsLEA : SchedWriteRes<[4GM4ALU23]> {
+def C4GM4Write3OpsLEA : SchedWriteRes<[C4GM4ALU23]> {
let Latency = 2;
let ReleaseAtCycles = [1];
let NumMicroOps = 2;
}
// a slow LEA is either a 3Ops LEA (base, index, offset),
// or an LEA with a `Scale` value different than 1.
-def 4GM4SlowLEAPredicate : MCSchedPredicate<
+def C4GM4SlowLEAPredicate : MCSchedPredicate<
CheckAny<[
IsThreeOperandsLEAFn,
CheckAll<[
@@ -262,564 +262,564 @@ def 4GM4SlowLEAPredicate : MCSchedPredicate<
]>
>;
-def 4GM4WriteLEA : SchedWriteVariant<[
- SchedVar<4GM4SlowLEAPredicate, [4GM4Write3OpsLEA]>,
- SchedVar<NoSchedPred, [WriteLEA]>
+def C4GM4WriteLEA : SchedWriteVariant<[
+ SchedVar<C4GM4SlowLEAPredicate, [C4GM4Write3OpsLEA]>,
+ SchedVar<NoSchedPred, [WriteLEA]>
]>;
-def : InstRW<[4GM4WriteLEA], (instrs LEA64r, LEA64_32r)>;
+def : InstRW<[C4GM4WriteLEA], (instrs LEA64r, LEA64_32r)>;
// MUL IMUL MULX
-defm : 4GM4WriteResIntPair<WriteIMul8, [4GM4ALU1], 3, [3], 1>;
-defm : 4GM4WriteResIntPair<WriteIMul16, [4GM4ALU1], 3, [3], 1>;
-defm : 4GM4WriteResIntPair<WriteIMul16Imm, [4GM4ALU1], 4, [4], 2>;
-defm : 4GM4WriteResIntPair<WriteIMul16Reg, [4GM4ALU1], 3>;
-defm : 4GM4WriteResIntPair<WriteIMul32, [4GM4ALU1], 3, [3], 1>;
-defm : 4GM4WriteResIntPair<WriteIMul32Imm, [4GM4ALU1], 3, [3], 2>;
-defm : 4GM4WriteResIntPair<WriteIMul32Reg, [4GM4ALU1], 3>;
-defm : 4GM4WriteResIntPair<WriteIMul64, [4GM4ALU1], 3, [3], 1>;
-defm : 4GM4WriteResIntPair<WriteIMul64Imm, [4GM4ALU1], 3, [3], 2>;
-defm : 4GM4WriteResIntPair<WriteIMul64Reg, [4GM4ALU1], 3>;
-
-defm : 4GM4WriteResIntPair<WriteMULX32, [4GM4ALU1], 3>;
-defm : 4GM4WriteResIntPair<WriteMULX64, [4GM4ALU1], 3>;
-defm : 4GM4WriteRes<WriteIMulHLd, [4GM4ALU1], !add(3, C864GM4Model.LoadLatency), [], 0>;
-defm : 4GM4WriteRes<WriteIMulH, [4GM4ALU1], 3, [], 0>;
-
-def 4GM4WriteMULX:SchedWriteRes<[4GM4ALU1]> {
+defm : C4GM4WriteResIntPair<WriteIMul8, [C4GM4ALU1], 3, [3], 1>;
+defm : C4GM4WriteResIntPair<WriteIMul16, [C4GM4ALU1], 3, [3], 1>;
+defm : C4GM4WriteResIntPair<WriteIMul16Imm, [C4GM4ALU1], 4, [4], 2>;
+defm : C4GM4WriteResIntPair<WriteIMul16Reg, [C4GM4ALU1], 3>;
+defm : C4GM4WriteResIntPair<WriteIMul32, [C4GM4ALU1], 3, [3], 1>;
+defm : C4GM4WriteResIntPair<WriteIMul32Imm, [C4GM4ALU1], 3, [3], 2>;
+defm : C4GM4WriteResIntPair<WriteIMul32Reg, [C4GM4ALU1], 3>;
+defm : C4GM4WriteResIntPair<WriteIMul64, [C4GM4ALU1], 3, [3], 1>;
+defm : C4GM4WriteResIntPair<WriteIMul64Imm, [C4GM4ALU1], 3, [3], 2>;
+defm : C4GM4WriteResIntPair<WriteIMul64Reg, [C4GM4ALU1], 3>;
+
+defm : C4GM4WriteResIntPair<WriteMULX32, [C4GM4ALU1], 3>;
+defm : C4GM4WriteResIntPair<WriteMULX64, [C4GM4ALU1], 3>;
+defm : C4GM4WriteRes<WriteIMulHLd, [C4GM4ALU1], !add(3, C864GM4Model.LoadLatency), [], 0>;
+defm : C4GM4WriteRes<WriteIMulH, [C4GM4ALU1], 3, [], 0>;
+
+def C4GM4WriteMULX:SchedWriteRes<[C4GM4ALU1]> {
let Latency = 4;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM4WriteMULX], (instregex "MULX(32|64)rr")>;
+def : InstRW<[C4GM4WriteMULX], (instregex "MULX(32|64)rr")>;
-def 4GM4WriteMULXLd:SchedWriteRes<[4GM4AGU, 4GM4Load, 4GM4ALU1]> {
- let Latency = !add(C864GM4Model.VecLoadLatency, 4GM4WriteMULX.Latency);
+def C4GM4WriteMULXLd:SchedWriteRes<[C4GM4AGU, C4GM4Load, C4GM4ALU1]> {
+ let Latency = !add(C864GM4Model.VecLoadLatency, C4GM4WriteMULX.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM4WriteMULXLd], (instregex "MULX(32|64)rm")>;
+def : InstRW<[C4GM4WriteMULXLd], (instregex "MULX(32|64)rm")>;
// DIV IDIV
-defm : 4GM4WriteResIntPair<WriteDiv8, [4GM4ALU2], 12, [12], 2>;
-defm : 4GM4WriteResIntPair<WriteDiv16, [4GM4ALU2], 17, [17], 2>;
-defm : 4GM4WriteResIntPair<WriteDiv32, [4GM4ALU2], 25, [25], 2>;
-defm : 4GM4WriteResIntPair<WriteDiv64, [4GM4ALU2], 41, [41], 1>;
-defm : 4GM4WriteResIntPair<WriteIDiv8, [4GM4ALU2], 12, [12], 2>;
-defm : 4GM4WriteResIntPair<WriteIDiv16, [4GM4ALU2], 17, [17], 2>;
-defm : 4GM4WriteResIntPair<WriteIDiv32, [4GM4ALU2], 25, [25], 2>;
-defm : 4GM4WriteResIntPair<WriteIDiv64, [4GM4ALU2], 41, [41], 1>;
-
-defm : 4GM4WriteRes<WriteBSWAP32, [4GM4ALU], 1, [4], 1>;
-defm : 4GM4WriteRes<WriteBSWAP64, [4GM4ALU], 1, [4], 1>;
-defm : 4GM4WriteRes<WriteCMPXCHG, [4GM4ALU], 3>;
-defm : 4GM4WriteRes<WriteCMPXCHGRMW,[4GM4ALU, 4GM4AGU], 5, [1,1], 3>;
-
-def 4GM4WriteXCHGrm : SchedWriteRes<[4GM4AGU, 4GM4Load, 4GM4ALU]> {
+defm : C4GM4WriteResIntPair<WriteDiv8, [C4GM4ALU2], 12, [12], 2>;
+defm : C4GM4WriteResIntPair<WriteDiv16, [C4GM4ALU2], 17, [17], 2>;
+defm : C4GM4WriteResIntPair<WriteDiv32, [C4GM4ALU2], 25, [25], 2>;
+defm : C4GM4WriteResIntPair<WriteDiv64, [C4GM4ALU2], 41, [41], 1>;
+defm : C4GM4WriteResIntPair<WriteIDiv8, [C4GM4ALU2], 12, [12], 2>;
+defm : C4GM4WriteResIntPair<WriteIDiv16, [C4GM4ALU2], 17, [17], 2>;
+defm : C4GM4WriteResIntPair<WriteIDiv32, [C4GM4ALU2], 25, [25], 2>;
+defm : C4GM4WriteResIntPair<WriteIDiv64, [C4GM4ALU2], 41, [41], 1>;
+
+defm : C4GM4WriteRes<WriteBSWAP32, [C4GM4ALU], 1, [4], 1>;
+defm : C4GM4WriteRes<WriteBSWAP64, [C4GM4ALU], 1, [4], 1>;
+defm : C4GM4WriteRes<WriteCMPXCHG, [C4GM4ALU], 3>;
+defm : C4GM4WriteRes<WriteCMPXCHGRMW,[C4GM4ALU, C4GM4AGU], 5, [1,1], 3>;
+
+def C4GM4WriteXCHGrm : SchedWriteRes<[C4GM4AGU, C4GM4Load, C4GM4ALU]> {
let Latency = !add(C864GM4Model.LoadLatency, 1);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM4WriteXCHGrm], (instregex "XCHG(8|16|32|64)rm")>;
+def : InstRW<[C4GM4WriteXCHGrm], (instregex "XCHG(8|16|32|64)rm")>;
-defm : 4GM4WriteResIntPair<WriteShift, [4GM4ALU], 1>;
-defm : 4GM4WriteResIntPair<WriteShiftCL, [4GM4ALU], 1>;
-defm : 4GM4WriteResIntPair<WriteRotate, [4GM4ALU], 1>;
-defm : 4GM4WriteResIntPair<WriteRotateCL, [4GM4ALU], 1>;
+defm : C4GM4WriteResIntPair<WriteShift, [C4GM4ALU], 1>;
+defm : C4GM4WriteResIntPair<WriteShiftCL, [C4GM4ALU], 1>;
+defm : C4GM4WriteResIntPair<WriteRotate, [C4GM4ALU], 1>;
+defm : C4GM4WriteResIntPair<WriteRotateCL, [C4GM4ALU], 1>;
-def 4GM4WriteRCR:SchedWriteRes<[4GM4ALU]> {
+def C4GM4WriteRCR:SchedWriteRes<[C4GM4ALU]> {
let Latency = 3;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM4WriteRCR], (instregex "RCR(8|16|32|64)rCL")>;
+def : InstRW<[C4GM4WriteRCR], (instregex "RCR(8|16|32|64)rCL")>;
-def 4GM4WriteRCRLd:SchedWriteRes<[4GM4AGU, 4GM4Load, 4GM4ALU]> {
- let Latency = !add(C864GM4Model.VecLoadLatency, 4GM4WriteRCR.Latency);
+def C4GM4WriteRCRLd:SchedWriteRes<[C4GM4AGU, C4GM4Load, C4GM4ALU]> {
+ let Latency = !add(C864GM4Model.VecLoadLatency, C4GM4WriteRCR.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM4WriteRCRLd], (instregex "RCR(8|16|32|64)mCL")>;
+def : InstRW<[C4GM4WriteRCRLd], (instregex "RCR(8|16|32|64)mCL")>;
-def 4GM4WriteRCL:SchedWriteRes<[4GM4ALU]> {
+def C4GM4WriteRCL:SchedWriteRes<[C4GM4ALU]> {
let Latency = 4;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM4WriteRCL], (instregex "RCL(8|16|32|64)rCL")>;
+def : InstRW<[C4GM4WriteRCL], (instregex "RCL(8|16|32|64)rCL")>;
-def 4GM4WriteRCLLd:SchedWriteRes<[4GM4AGU, 4GM4Load, 4GM4ALU]> {
- let Latency = !add(C864GM4Model.VecLoadLatency, 4GM4WriteRCL.Latency);
+def C4GM4WriteRCLLd:SchedWriteRes<[C4GM4AGU, C4GM4Load, C4GM4ALU]> {
+ let Latency = !add(C864GM4Model.VecLoadLatency, C4GM4WriteRCL.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM4WriteRCLLd], (instregex "RCL(8|16|32|64)mCL")>;
+def : InstRW<[C4GM4WriteRCLLd], (instregex "RCL(8|16|32|64)mCL")>;
-defm : 4GM4WriteRes<WriteSHDrri, [4GM4ALU], 3, [3], 6>;
-defm : 4GM4WriteRes<WriteSHDrrcl, [4GM4ALU], 3, [5], 7>;
-defm : 4GM4WriteRes<WriteSHDmri, [4GM4ALU], 5, [5], 8>;
-defm : 4GM4WriteRes<WriteSHDmrcl, [4GM4ALU], 5, [5], 8>;
+defm : C4GM4WriteRes<WriteSHDrri, [C4GM4ALU], 3, [3], 6>;
+defm : C4GM4WriteRes<WriteSHDrrcl, [C4GM4ALU], 3, [5], 7>;
+defm : C4GM4WriteRes<WriteSHDmri, [C4GM4ALU], 5, [5], 8>;
+defm : C4GM4WriteRes<WriteSHDmrcl, [C4GM4ALU], 5, [5], 8>;
-defm : 4GM4WriteResIntPair<WriteJump, [4GM4ALU], 1>;
-defm : 4GM4WriteResIntPair<WriteCRC32, [4GM4ALU3], 3, [3], 3>;
+defm : C4GM4WriteResIntPair<WriteJump, [C4GM4ALU], 1>;
+defm : C4GM4WriteResIntPair<WriteCRC32, [C4GM4ALU3], 3, [3], 3>;
-defm : 4GM4WriteResIntPair<WriteCMOV, [4GM4ALU], 1>;
-defm : 4GM4WriteRes<WriteSETCC, [4GM4ALU]>;
-defm : 4GM4WriteRes<WriteSETCCStore, [4GM4ALU, 4GM4AGU, 4GM4Store]>;
-defm : 4GM4WriteRes<WriteLAHFSAHF, [4GM4ALU], 2, [1], 2>;
+defm : C4GM4WriteResIntPair<WriteCMOV, [C4GM4ALU], 1>;
+defm : C4GM4WriteRes<WriteSETCC, [C4GM4ALU]>;
+defm : C4GM4WriteRes<WriteSETCCStore, [C4GM4ALU, C4GM4AGU, C4GM4Store]>;
+defm : C4GM4WriteRes<WriteLAHFSAHF, [C4GM4ALU], 2, [1], 2>;
-defm : 4GM4WriteRes<WriteBitTest, [4GM4ALU], 1>;
-defm : 4GM4WriteRes<WriteBitTestImmLd, [4GM4AGU, 4GM4Load, 4GM4ALU], !add(C864GM4Model.LoadLatency, 1), [1,1,1], 2>;
-defm : 4GM4WriteRes<WriteBitTestRegLd, [4GM4AGU, 4GM4Load, 4GM4ALU], !add(C864GM4Model.LoadLatency, 1), [1,1,1], 7>;
-defm : 4GM4WriteRes<WriteBitTestSet, [4GM4ALU], 2, [1], 2>;
-defm : 4GM4WriteRes<WriteBitTestSetImmLd, [4GM4AGU, 4GM4Load, 4GM4ALU], !add(C864GM4Model.LoadLatency, 2), [1, 1, 1], 2>;
-defm : 4GM4WriteRes<WriteBitTestSetRegLd, [4GM4AGU, 4GM4Load, 4GM4ALU], !add(C864GM4Model.LoadLatency, 2), [1, 1, 1], 7>;
+defm : C4GM4WriteRes<WriteBitTest, [C4GM4ALU], 1>;
+defm : C4GM4WriteRes<WriteBitTestImmLd, [C4GM4AGU, C4GM4Load, C4GM4ALU], !add(C864GM4Model.LoadLatency, 1), [1,1,1], 2>;
+defm : C4GM4WriteRes<WriteBitTestRegLd, [C4GM4AGU, C4GM4Load, C4GM4ALU], !add(C864GM4Model.LoadLatency, 1), [1,1,1], 7>;
+defm : C4GM4WriteRes<WriteBitTestSet, [C4GM4ALU], 2, [1], 2>;
+defm : C4GM4WriteRes<WriteBitTestSetImmLd, [C4GM4AGU, C4GM4Load, C4GM4ALU], !add(C864GM4Model.LoadLatency, 2), [1, 1, 1], 2>;
+defm : C4GM4WriteRes<WriteBitTestSetRegLd, [C4GM4AGU, C4GM4Load, C4GM4ALU], !add(C864GM4Model.LoadLatency, 2), [1, 1, 1], 7>;
// Bit counts.
-defm : 4GM4WriteResIntPair<WriteBSF, [4GM4ALU], 3, [12], 6, 4, 2>;
-defm : 4GM4WriteResIntPair<WriteBSR, [4GM4ALU], 4, [16], 6, 4, 2>;
-defm : 4GM4WriteResIntPair<WriteLZCNT, [4GM4ALU], 1>;
-defm : 4GM4WriteResIntPair<WriteTZCNT, [4GM4ALU], 2, [2], 2, 4, 0>;
-defm : 4GM4WriteResIntPair<WritePOPCNT, [4GM4ALU], 1, [1], 1, 4, 0>;
+defm : C4GM4WriteResIntPair<WriteBSF, [C4GM4ALU], 3, [12], 6, 4, 2>;
+defm : C4GM4WriteResIntPair<WriteBSR, [C4GM4ALU], 4, [16], 6, 4, 2>;
+defm : C4GM4WriteResIntPair<WriteLZCNT, [C4GM4ALU], 1>;
+defm : C4GM4WriteResIntPair<WriteTZCNT, [C4GM4ALU], 2, [2], 2, 4, 0>;
+defm : C4GM4WriteResIntPair<WritePOPCNT, [C4GM4ALU], 1, [1], 1, 4, 0>;
// Treat misc copies as a move.
def : InstRW<[WriteMove], (instrs COPY)>;
// BMI1 BEXTR, BMI2 BZHI
-defm : 4GM4WriteResIntPair<WriteBEXTR, [4GM4ALU], 1, [1], 1, 4, 1>;
-defm : 4GM4WriteResIntPair<WriteBLS, [4GM4ALU], 2, [2], 2, 4, 1>;
-defm : 4GM4WriteResIntPair<WriteBZHI, [4GM4ALU], 1>;
+defm : C4GM4WriteResIntPair<WriteBEXTR, [C4GM4ALU], 1, [1], 1, 4, 1>;
+defm : C4GM4WriteResIntPair<WriteBLS, [C4GM4ALU], 2, [2], 2, 4, 1>;
+defm : C4GM4WriteResIntPair<WriteBZHI, [C4GM4ALU], 1>;
// Floating Point Instructions
-defm : 4GM4WriteRes<WriteFLD0, [4GM4AGU, 4GM4AGU, 4GM4FPU1], !add(C864GM4Model.LoadLatency, 4), [1, 1, 1], 1>;
-defm : 4GM4WriteRes<WriteFLD1, [4GM4AGU, 4GM4AGU, 4GM4FPU1], !add(C864GM4Model.LoadLatency, 4), [1, 1, 1], 1>;
-defm : 4GM4WriteRes<WriteFLDC, [4GM4AGU, 4GM4AGU, 4GM4FPU1], !add(C864GM4Model.LoadLatency, 4), [1, 1, 1], 1>;
-defm : 4GM4WriteRes<WriteFLoad, [4GM4AGU, 4GM4Load], !add(C864GM4Model.VecLoadLatency, 1)>;
-defm : 4GM4WriteRes<WriteFLoadX, [4GM4AGU, 4GM4Load], !add(C864GM4Model.VecLoadLatency, 1)>;
-defm : 4GM4WriteRes<WriteFLoadY, [4GM4AGU, 4GM4Load], !add(C864GM4Model.VecLoadLatency, 1)>;
-defm : 4GM4WriteRes<WriteFMaskedLoad, [4GM4AGU, 4GM4Load, 4GM4FPU02], !add(C864GM4Model.VecLoadLatency, 1)>;
-defm : 4GM4WriteRes<WriteFMaskedLoadY, [4GM4AGU, 4GM4Load, 4GM4FPU02], !add(C864GM4Model.VecLoadLatency, 1), [1, 1, 1], 2>;
-
-defm : 4GM4WriteRes<WriteFStore, [4GM4AGU, 4GM4Store], C864GM4Model.StoreLatency>;
-defm : 4GM4WriteRes<WriteFStoreX, [4GM4AGU, 4GM4Store], C864GM4Model.StoreLatency>;
-defm : 4GM4WriteRes<WriteFStoreY, [4GM4AGU, 4GM4Store], C864GM4Model.StoreLatency>;
-defm : 4GM4WriteRes<WriteFStoreNT, [4GM4FPU1, 4GM4AGU, 4GM4Store], !add(C864GM4Model.StoreLatency, 4)>;
-defm : 4GM4WriteRes<WriteFStoreNTX, [4GM4FPU1, 4GM4AGU, 4GM4Store], !add(C864GM4Model.StoreLatency, 4)>;
-defm : 4GM4WriteRes<WriteFStoreNTY, [4GM4FPU1, 4GM4AGU, 4GM4Store], !add(C864GM4Model.StoreLatency, 4)>;
-defm : 4GM4WriteRes<WriteFMaskedStore32, [4GM4FPU02, 4GM4AGU, 4GM4Store], C864GM4Model.StoreLatency>;
-defm : 4GM4WriteRes<WriteFMaskedStore32Y, [4GM4FPU02, 4GM4AGU, 4GM4Store], C864GM4Model.StoreLatency>;
-defm : 4GM4WriteRes<WriteFMaskedStore64, [4GM4FPU02, 4GM4AGU, 4GM4Store], C864GM4Model.StoreLatency>;
-defm : 4GM4WriteRes<WriteFMaskedStore64Y, [4GM4FPU02, 4GM4AGU, 4GM4Store], C864GM4Model.StoreLatency>;
-
-defm : 4GM4WriteResFPPair<WriteFAdd, [4GM4FPU13], 3>;
-defm : 4GM4WriteResFPPair<WriteFAddX, [4GM4FPU13], 3>;
-defm : 4GM4WriteResFPPair<WriteFAddY, [4GM4FPU13], 3>;
+defm : C4GM4WriteRes<WriteFLD0, [C4GM4AGU, C4GM4AGU, C4GM4FPU1], !add(C864GM4Model.LoadLatency, 4), [1, 1, 1], 1>;
+defm : C4GM4WriteRes<WriteFLD1, [C4GM4AGU, C4GM4AGU, C4GM4FPU1], !add(C864GM4Model.LoadLatency, 4), [1, 1, 1], 1>;
+defm : C4GM4WriteRes<WriteFLDC, [C4GM4AGU, C4GM4AGU, C4GM4FPU1], !add(C864GM4Model.LoadLatency, 4), [1, 1, 1], 1>;
+defm : C4GM4WriteRes<WriteFLoad, [C4GM4AGU, C4GM4Load], !add(C864GM4Model.VecLoadLatency, 1)>;
+defm : C4GM4WriteRes<WriteFLoadX, [C4GM4AGU, C4GM4Load], !add(C864GM4Model.VecLoadLatency, 1)>;
+defm : C4GM4WriteRes<WriteFLoadY, [C4GM4AGU, C4GM4Load], !add(C864GM4Model.VecLoadLatency, 1)>;
+defm : C4GM4WriteRes<WriteFMaskedLoad, [C4GM4AGU, C4GM4Load, C4GM4FPU02], !add(C864GM4Model.VecLoadLatency, 1)>;
+defm : C4GM4WriteRes<WriteFMaskedLoadY, [C4GM4AGU, C4GM4Load, C4GM4FPU02], !add(C864GM4Model.VecLoadLatency, 1), [1, 1, 1], 2>;
+
+defm : C4GM4WriteRes<WriteFStore, [C4GM4AGU, C4GM4Store], C864GM4Model.StoreLatency>;
+defm : C4GM4WriteRes<WriteFStoreX, [C4GM4AGU, C4GM4Store], C864GM4Model.StoreLatency>;
+defm : C4GM4WriteRes<WriteFStoreY, [C4GM4AGU, C4GM4Store], C864GM4Model.StoreLatency>;
+defm : C4GM4WriteRes<WriteFStoreNT, [C4GM4FPU1, C4GM4AGU, C4GM4Store], !add(C864GM4Model.StoreLatency, 4)>;
+defm : C4GM4WriteRes<WriteFStoreNTX, [C4GM4FPU1, C4GM4AGU, C4GM4Store], !add(C864GM4Model.StoreLatency, 4)>;
+defm : C4GM4WriteRes<WriteFStoreNTY, [C4GM4FPU1, C4GM4AGU, C4GM4Store], !add(C864GM4Model.StoreLatency, 4)>;
+defm : C4GM4WriteRes<WriteFMaskedStore32, [C4GM4FPU02, C4GM4AGU, C4GM4Store], C864GM4Model.StoreLatency>;
+defm : C4GM4WriteRes<WriteFMaskedStore32Y, [C4GM4FPU02, C4GM4AGU, C4GM4Store], C864GM4Model.StoreLatency>;
+defm : C4GM4WriteRes<WriteFMaskedStore64, [C4GM4FPU02, C4GM4AGU, C4GM4Store], C864GM4Model.StoreLatency>;
+defm : C4GM4WriteRes<WriteFMaskedStore64Y, [C4GM4FPU02, C4GM4AGU, C4GM4Store], C864GM4Model.StoreLatency>;
+
+defm : C4GM4WriteResFPPair<WriteFAdd, [C4GM4FPU13], 3>;
+defm : C4GM4WriteResFPPair<WriteFAddX, [C4GM4FPU13], 3>;
+defm : C4GM4WriteResFPPair<WriteFAddY, [C4GM4FPU13], 3>;
defm : X86WriteResPairUnsupported<WriteFAddZ>;
-defm : 4GM4WriteResFPPair<WriteFAdd64, [4GM4FPU13], 3>;
-defm : 4GM4WriteResFPPair<WriteFAdd64X, [4GM4FPU13], 3>;
-defm : 4GM4WriteResFPPair<WriteFAdd64Y, [4GM4FPU13], 3>;
+defm : C4GM4WriteResFPPair<WriteFAdd64, [C4GM4FPU13], 3>;
+defm : C4GM4WriteResFPPair<WriteFAdd64X, [C4GM4FPU13], 3>;
+defm : C4GM4WriteResFPPair<WriteFAdd64Y, [C4GM4FPU13], 3>;
defm : X86WriteResPairUnsupported<WriteFAdd64Z>;
-defm : 4GM4WriteResFPPair<WriteFHAdd, [4GM4FPU13], 7, [8], 4, 3>;
-defm : 4GM4WriteResFPPair<WriteFHAddY, [4GM4FPU13], 7, [8], 4, 3>;
+defm : C4GM4WriteResFPPair<WriteFHAdd, [C4GM4FPU13], 7, [8], 4, 3>;
+defm : C4GM4WriteResFPPair<WriteFHAddY, [C4GM4FPU13], 7, [8], 4, 3>;
defm : X86WriteResPairUnsupported<WriteFHAddZ>;
-defm : 4GM4WriteResFPPair<WritePHAdd, [4GM4FPU13], 3, [8], 4, 3>;
-defm : 4GM4WriteResFPPair<WritePHAddX, [4GM4FPU13], 3, [8], 4, 3>;
-defm : 4GM4WriteResFPPair<WritePHAddY, [4GM4FPU13], 3, [8], 4, 3>;
+defm : C4GM4WriteResFPPair<WritePHAdd, [C4GM4FPU13], 3, [8], 4, 3>;
+defm : C4GM4WriteResFPPair<WritePHAddX, [C4GM4FPU13], 3, [8], 4, 3>;
+defm : C4GM4WriteResFPPair<WritePHAddY, [C4GM4FPU13], 3, [8], 4, 3>;
defm : X86WriteResPairUnsupported<WritePHAddZ>;
-defm : 4GM4WriteResFPPair<WriteFCmp, [4GM4FPU02], 1>;
-defm : 4GM4WriteResFPPair<WriteFCmpX, [4GM4FPU02], 1>;
-defm : 4GM4WriteResFPPair<WriteFCmpY, [4GM4FPU02], 1>;
+defm : C4GM4WriteResFPPair<WriteFCmp, [C4GM4FPU02], 1>;
+defm : C4GM4WriteResFPPair<WriteFCmpX, [C4GM4FPU02], 1>;
+defm : C4GM4WriteResFPPair<WriteFCmpY, [C4GM4FPU02], 1>;
defm : X86WriteResPairUnsupported<WriteFCmpZ>;
-defm : 4GM4WriteResFPPair<WriteFCmp64, [4GM4FPU02], 1>;
-defm : 4GM4WriteResFPPair<WriteFCmp64X, [4GM4FPU02], 1>;
-defm : 4GM4WriteResFPPair<WriteFCmp64Y, [4GM4FPU02], 1>;
+defm : C4GM4WriteResFPPair<WriteFCmp64, [C4GM4FPU02], 1>;
+defm : C4GM4WriteResFPPair<WriteFCmp64X, [C4GM4FPU02], 1>;
+defm : C4GM4WriteResFPPair<WriteFCmp64Y, [C4GM4FPU02], 1>;
defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
-defm : 4GM4WriteResFPPair<WriteFCom, [4GM4FPU02,4GM4FPU1], 5>;
-defm : 4GM4WriteResFPPair<WriteFComX, [4GM4FPU02,4GM4FPU1], 5>;
-defm : 4GM4WriteResFPPair<WriteFBlend, [4GM4FPU02], 1>;
-defm : 4GM4WriteResFPPair<WriteFBlendY, [4GM4FPU02], 1>;
+defm : C4GM4WriteResFPPair<WriteFCom, [C4GM4FPU02,C4GM4FPU1], 5>;
+defm : C4GM4WriteResFPPair<WriteFComX, [C4GM4FPU02,C4GM4FPU1], 5>;
+defm : C4GM4WriteResFPPair<WriteFBlend, [C4GM4FPU02], 1>;
+defm : C4GM4WriteResFPPair<WriteFBlendY, [C4GM4FPU02], 1>;
defm : X86WriteResPairUnsupported<WriteFBlendZ>;
-defm : 4GM4WriteResFPPair<WriteFVarBlend, [4GM4FPU02], 1>;
-defm : 4GM4WriteResFPPair<WriteFVarBlendY,[4GM4FPU02], 1>;
+defm : C4GM4WriteResFPPair<WriteFVarBlend, [C4GM4FPU02], 1>;
+defm : C4GM4WriteResFPPair<WriteFVarBlendY,[C4GM4FPU02], 1>;
defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
-defm : 4GM4WriteResFPPair<WriteCvtSS2I, [4GM4FPU1, 4GM4FPU1], 2, [1, 1], 2>;
-defm : 4GM4WriteResFPPair<WriteCvtPS2I, [4GM4FPU1], 4, [1], 2>;
-defm : 4GM4WriteResFPPair<WriteCvtPS2IY, [4GM4FPU1], 4, [1], 2>;
+defm : C4GM4WriteResFPPair<WriteCvtSS2I, [C4GM4FPU1, C4GM4FPU1], 2, [1, 1], 2>;
+defm : C4GM4WriteResFPPair<WriteCvtPS2I, [C4GM4FPU1], 4, [1], 2>;
+defm : C4GM4WriteResFPPair<WriteCvtPS2IY, [C4GM4FPU1], 4, [1], 2>;
defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
-defm : 4GM4WriteResFPPair<WriteCvtSD2I, [4GM4FPU1, 4GM4FPU1], 2, [1, 2], 2>;
-defm : 4GM4WriteResFPPair<WriteCvtPD2I, [4GM4FPU01, 4GM4FPU1], 7, [1, 2], 2>;
-defm : 4GM4WriteResFPPair<WriteCvtPD2IY, [4GM4FPU01, 4GM4FPU1], 9, [1, 2], 2>;
+defm : C4GM4WriteResFPPair<WriteCvtSD2I, [C4GM4FPU1, C4GM4FPU1], 2, [1, 2], 2>;
+defm : C4GM4WriteResFPPair<WriteCvtPD2I, [C4GM4FPU01, C4GM4FPU1], 7, [1, 2], 2>;
+defm : C4GM4WriteResFPPair<WriteCvtPD2IY, [C4GM4FPU01, C4GM4FPU1], 9, [1, 2], 2>;
defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
-defm : 4GM4WriteResFPPair<WriteCvtSS2SD, [4GM4FPU1], 4, [1], 1>;
-defm : 4GM4WriteResFPPair<WriteCvtPS2PD, [4GM4FPU13], 3, [1], 1>;
-defm : 4GM4WriteResFPPair<WriteCvtPS2PDY, [4GM4FPU13], 3, [1], 1>;
+defm : C4GM4WriteResFPPair<WriteCvtSS2SD, [C4GM4FPU1], 4, [1], 1>;
+defm : C4GM4WriteResFPPair<WriteCvtPS2PD, [C4GM4FPU13], 3, [1], 1>;
+defm : C4GM4WriteResFPPair<WriteCvtPS2PDY, [C4GM4FPU13], 3, [1], 1>;
defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;
-defm : 4GM4WriteResFPPair<WriteCvtSD2SS, [4GM4FPU1], 4, [1], 1>;
-defm : 4GM4WriteResFPPair<WriteCvtPD2PS, [4GM4FPU1, 4GM4FPU13], 3, [1, 1], 2>;
-defm : 4GM4WriteResFPPair<WriteCvtPD2PSY, [4GM4FPU1, 4GM4FPU13], 3, [1, 1], 2>;
+defm : C4GM4WriteResFPPair<WriteCvtSD2SS, [C4GM4FPU1], 4, [1], 1>;
+defm : C4GM4WriteResFPPair<WriteCvtPD2PS, [C4GM4FPU1, C4GM4FPU13], 3, [1, 1], 2>;
+defm : C4GM4WriteResFPPair<WriteCvtPD2PSY, [C4GM4FPU1, C4GM4FPU13], 3, [1, 1], 2>;
defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;
-defm : 4GM4WriteResFPPair<WriteCvtI2SS, [4GM4ALU2, 4GM4FPU1], 4, [1, 1], 2>;
-defm : 4GM4WriteResFPPair<WriteCvtI2PS, [4GM4FPU1], 4>;
-defm : 4GM4WriteResFPPair<WriteCvtI2PSY, [4GM4FPU1], 4>;
+defm : C4GM4WriteResFPPair<WriteCvtI2SS, [C4GM4ALU2, C4GM4FPU1], 4, [1, 1], 2>;
+defm : C4GM4WriteResFPPair<WriteCvtI2PS, [C4GM4FPU1], 4>;
+defm : C4GM4WriteResFPPair<WriteCvtI2PSY, [C4GM4FPU1], 4>;
defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
-defm : 4GM4WriteResFPPair<WriteCvtI2SD, [4GM4ALU2, 4GM4FPU1], 4, [1, 2], 2>;
-defm : 4GM4WriteResFPPair<WriteCvtI2PD, [4GM4FPU01, 4GM4FPU1], 7, [1, 2], 2>;
-defm : 4GM4WriteResFPPair<WriteCvtI2PDY, [4GM4FPU01, 4GM4FPU1], 9, [1, 2], 2>;
+defm : C4GM4WriteResFPPair<WriteCvtI2SD, [C4GM4ALU2, C4GM4FPU1], 4, [1, 2], 2>;
+defm : C4GM4WriteResFPPair<WriteCvtI2PD, [C4GM4FPU01, C4GM4FPU1], 7, [1, 2], 2>;
+defm : C4GM4WriteResFPPair<WriteCvtI2PDY, [C4GM4FPU01, C4GM4FPU1], 9, [1, 2], 2>;
defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
-defm : 4GM4WriteResFPPair<WriteCvtPH2PS, [4GM4FPU1], 7, [2], 1>;
-defm : 4GM4WriteResFPPair<WriteCvtPH2PSY, [4GM4FPU0], 9, [1], 1>;
+defm : C4GM4WriteResFPPair<WriteCvtPH2PS, [C4GM4FPU1], 7, [2], 1>;
+defm : C4GM4WriteResFPPair<WriteCvtPH2PSY, [C4GM4FPU0], 9, [1], 1>;
defm : X86WriteResPairUnsupported<WriteCvtPH2PSZ>;
-defm : 4GM4WriteRes<WriteCvtPS2PH, [4GM4FPU0], 7, [1], 1>;
-defm : 4GM4WriteRes<WriteCvtPS2PHY, [4GM4FPU1], 9, [2], 1>;
+defm : C4GM4WriteRes<WriteCvtPS2PH, [C4GM4FPU0], 7, [1], 1>;
+defm : C4GM4WriteRes<WriteCvtPS2PHY, [C4GM4FPU1], 9, [2], 1>;
defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;
-defm : 4GM4WriteRes<WriteCvtPS2PHSt, [4GM4FPU0, 4GM4AGU, 4GM4Store], !add(7, C864GM4Model.StoreLatency), [1, 1, 1], 2>;
-defm : 4GM4WriteRes<WriteCvtPS2PHYSt, [4GM4FPU1, 4GM4AGU, 4GM4Store], !add(9, C864GM4Model.StoreLatency), [2, 1, 1], 3>;
+defm : C4GM4WriteRes<WriteCvtPS2PHSt, [C4GM4FPU0, C4GM4AGU, C4GM4Store], !add(7, C864GM4Model.StoreLatency), [1, 1, 1], 2>;
+defm : C4GM4WriteRes<WriteCvtPS2PHYSt, [C4GM4FPU1, C4GM4AGU, C4GM4Store], !add(9, C864GM4Model.StoreLatency), [2, 1, 1], 3>;
defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;
-defm : 4GM4WriteResFPPair<WriteFDiv, [4GM4FPU1], 10, [5], 1>;
-defm : 4GM4WriteResFPPair<WriteFDivX, [4GM4FPU1], 10, [5], 1>;
-defm : 4GM4WriteResFPPair<WriteFDivY, [4GM4FPU1], 10, [5], 1>;
+defm : C4GM4WriteResFPPair<WriteFDiv, [C4GM4FPU1], 10, [5], 1>;
+defm : C4GM4WriteResFPPair<WriteFDivX, [C4GM4FPU1], 10, [5], 1>;
+defm : C4GM4WriteResFPPair<WriteFDivY, [C4GM4FPU1], 10, [5], 1>;
defm : X86WriteResPairUnsupported<WriteFDivZ>;
-defm : 4GM4WriteResFPPair<WriteFDiv64, [4GM4FPU1], 8, [6], 1>;
-defm : 4GM4WriteResFPPair<WriteFDiv64X, [4GM4FPU1], 8, [6], 1>;
-defm : 4GM4WriteResFPPair<WriteFDiv64Y, [4GM4FPU1], 8, [6], 1>;
+defm : C4GM4WriteResFPPair<WriteFDiv64, [C4GM4FPU1], 8, [6], 1>;
+defm : C4GM4WriteResFPPair<WriteFDiv64X, [C4GM4FPU1], 8, [6], 1>;
+defm : C4GM4WriteResFPPair<WriteFDiv64Y, [C4GM4FPU1], 8, [6], 1>;
defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
-defm : 4GM4WriteResFPPair<WriteFSign, [4GM4FPU13], 1>;
-defm : 4GM4WriteResFPPair<WriteFRnd, [4GM4FPU1], 4, [1], 1, C864GM4Model.VecLoadLatency, 0>;
-defm : 4GM4WriteResFPPair<WriteFRndY, [4GM4FPU1], 4, [1], 1, C864GM4Model.VecLoadLatency, 0>;
+defm : C4GM4WriteResFPPair<WriteFSign, [C4GM4FPU13], 1>;
+defm : C4GM4WriteResFPPair<WriteFRnd, [C4GM4FPU1], 4, [1], 1, C864GM4Model.VecLoadLatency, 0>;
+defm : C4GM4WriteResFPPair<WriteFRndY, [C4GM4FPU1], 4, [1], 1, C864GM4Model.VecLoadLatency, 0>;
defm : X86WriteResPairUnsupported<WriteFRndZ>;
-defm : 4GM4WriteResFPPair<WriteFLogic, [4GM4FPU], 1>;
-defm : 4GM4WriteResFPPair<WriteFLogicY, [4GM4FPU], 1>;
+defm : C4GM4WriteResFPPair<WriteFLogic, [C4GM4FPU], 1>;
+defm : C4GM4WriteResFPPair<WriteFLogicY, [C4GM4FPU], 1>;
defm : X86WriteResPairUnsupported<WriteFLogicZ>;
-defm : 4GM4WriteResFPPair<WriteFTest, [4GM4FPU01, 4GM4FPU1], 4, [1, 2], 1, C864GM4Model.VecLoadLatency, 1>;
-defm : 4GM4WriteResFPPair<WriteFTestY, [4GM4FPU01, 4GM4FPU1], 8, [1, 2], 1, C864GM4Model.VecLoadLatency, 1>;
+defm : C4GM4WriteResFPPair<WriteFTest, [C4GM4FPU01, C4GM4FPU1], 4, [1, 2], 1, C864GM4Model.VecLoadLatency, 1>;
+defm : C4GM4WriteResFPPair<WriteFTestY, [C4GM4FPU01, C4GM4FPU1], 8, [1, 2], 1, C864GM4Model.VecLoadLatency, 1>;
defm : X86WriteResPairUnsupported<WriteFTestZ>;
-defm : 4GM4WriteResFPPair<WriteFShuffle, [4GM4FPU01], 1>;
-defm : 4GM4WriteResFPPair<WriteFShuffleY, [4GM4FPU01], 1>;
+defm : C4GM4WriteResFPPair<WriteFShuffle, [C4GM4FPU01], 1>;
+defm : C4GM4WriteResFPPair<WriteFShuffleY, [C4GM4FPU01], 1>;
defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
-defm : 4GM4WriteResFPPair<WriteFVarShuffle, [4GM4FPU01], 3>;
-defm : 4GM4WriteResFPPair<WriteFVarShuffleY,[4GM4FPU01], 3>;
+defm : C4GM4WriteResFPPair<WriteFVarShuffle, [C4GM4FPU01], 3>;
+defm : C4GM4WriteResFPPair<WriteFVarShuffleY,[C4GM4FPU01], 3>;
defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
-defm : 4GM4WriteResFPPair<WriteFMul, [4GM4FPU02], 3>;
-defm : 4GM4WriteResFPPair<WriteFMulX, [4GM4FPU02], 3>;
-defm : 4GM4WriteResFPPair<WriteFMulY, [4GM4FPU02], 3>;
+defm : C4GM4WriteResFPPair<WriteFMul, [C4GM4FPU02], 3>;
+defm : C4GM4WriteResFPPair<WriteFMulX, [C4GM4FPU02], 3>;
+defm : C4GM4WriteResFPPair<WriteFMulY, [C4GM4FPU02], 3>;
defm : X86WriteResPairUnsupported<WriteFMulZ>;
-defm : 4GM4WriteResFPPair<WriteFMul64, [4GM4FPU02], 4>;
-defm : 4GM4WriteResFPPair<WriteFMul64X, [4GM4FPU02], 4>;
-defm : 4GM4WriteResFPPair<WriteFMul64Y, [4GM4FPU02], 4>;
+defm : C4GM4WriteResFPPair<WriteFMul64, [C4GM4FPU02], 4>;
+defm : C4GM4WriteResFPPair<WriteFMul64X, [C4GM4FPU02], 4>;
+defm : C4GM4WriteResFPPair<WriteFMul64Y, [C4GM4FPU02], 4>;
defm : X86WriteResPairUnsupported<WriteFMul64Z>;
-defm : 4GM4WriteResFPPair<WriteFMA, [4GM4FPU02], 5>;
-defm : 4GM4WriteResFPPair<WriteFMAX, [4GM4FPU02], 5>;
-defm : 4GM4WriteResFPPair<WriteFMAY, [4GM4FPU02], 5>;
+defm : C4GM4WriteResFPPair<WriteFMA, [C4GM4FPU02], 5>;
+defm : C4GM4WriteResFPPair<WriteFMAX, [C4GM4FPU02], 5>;
+defm : C4GM4WriteResFPPair<WriteFMAY, [C4GM4FPU02], 5>;
defm : X86WriteResPairUnsupported<WriteFMAZ>;
-defm : 4GM4WriteResFPPair<WriteFRcp, [4GM4FPU02], 5>;
-defm : 4GM4WriteResFPPair<WriteFRcpX, [4GM4FPU02], 5>;
-defm : 4GM4WriteResFPPair<WriteFRcpY, [4GM4FPU02], 5>;
+defm : C4GM4WriteResFPPair<WriteFRcp, [C4GM4FPU02], 5>;
+defm : C4GM4WriteResFPPair<WriteFRcpX, [C4GM4FPU02], 5>;
+defm : C4GM4WriteResFPPair<WriteFRcpY, [C4GM4FPU02], 5>;
defm : X86WriteResPairUnsupported<WriteFRcpZ>;
-defm : 4GM4WriteResFPPair<WriteFRsqrt, [4GM4FPU02], 5>;
-defm : 4GM4WriteResFPPair<WriteFRsqrtX, [4GM4FPU02], 5>;
-defm : 4GM4WriteResFPPair<WriteFRsqrtY, [4GM4FPU02], 5>;
+defm : C4GM4WriteResFPPair<WriteFRsqrt, [C4GM4FPU02], 5>;
+defm : C4GM4WriteResFPPair<WriteFRsqrtX, [C4GM4FPU02], 5>;
+defm : C4GM4WriteResFPPair<WriteFRsqrtY, [C4GM4FPU02], 5>;
defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
-defm : 4GM4WriteResFPPair<WriteFSqrt, [4GM4FPU1], 8, [7]>;
-defm : 4GM4WriteResFPPair<WriteFSqrtX, [4GM4FPU1], 8, [7]>;
-defm : 4GM4WriteResFPPair<WriteFSqrtY, [4GM4FPU1], 8, [7]>;
+defm : C4GM4WriteResFPPair<WriteFSqrt, [C4GM4FPU1], 8, [7]>;
+defm : C4GM4WriteResFPPair<WriteFSqrtX, [C4GM4FPU1], 8, [7]>;
+defm : C4GM4WriteResFPPair<WriteFSqrtY, [C4GM4FPU1], 8, [7]>;
defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
-defm : 4GM4WriteResFPPair<WriteFSqrt64, [4GM4FPU1], 8, [10]>;
-defm : 4GM4WriteResFPPair<WriteFSqrt64X, [4GM4FPU1], 8, [10]>;
-defm : 4GM4WriteResFPPair<WriteFSqrt64Y, [4GM4FPU1], 8, [10]>;
+defm : C4GM4WriteResFPPair<WriteFSqrt64, [C4GM4FPU1], 8, [10]>;
+defm : C4GM4WriteResFPPair<WriteFSqrt64X, [C4GM4FPU1], 8, [10]>;
+defm : C4GM4WriteResFPPair<WriteFSqrt64Y, [C4GM4FPU1], 8, [10]>;
defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
-defm : 4GM4WriteResFPPair<WriteFSqrt80, [4GM4FPU1], 22, [22]>;
-defm : 4GM4WriteResFPPair<WriteFShuffle256, [4GM4FPU0], 3>;
-defm : 4GM4WriteResFPPair<WriteFVarShuffle256, [4GM4FPU0], 3>;
-defm : 4GM4WriteResFPPair<WriteDPPD, [4GM4FPU1], 10, [8], 4>;
+defm : C4GM4WriteResFPPair<WriteFSqrt80, [C4GM4FPU1], 22, [22]>;
+defm : C4GM4WriteResFPPair<WriteFShuffle256, [C4GM4FPU0], 3>;
+defm : C4GM4WriteResFPPair<WriteFVarShuffle256, [C4GM4FPU0], 3>;
+defm : C4GM4WriteResFPPair<WriteDPPD, [C4GM4FPU1], 10, [8], 4>;
-def 4GM4WriteVPERM:SchedWriteRes<[4GM4FPU01]> {
+def C4GM4WriteVPERM:SchedWriteRes<[C4GM4FPU01]> {
let Latency = 7;
let ReleaseAtCycles = [1];
let NumMicroOps = 3;
}
-def : InstRW<[4GM4WriteVPERM], (instrs VPERM2I128rri, VPERM2F128rri)>;
+def : InstRW<[C4GM4WriteVPERM], (instrs VPERM2I128rri, VPERM2F128rri)>;
-def 4GM4WriteVPERMLd:SchedWriteRes<[4GM4AGU, 4GM4Load, 4GM4FPU01]> {
- let Latency = !add(C864GM4Model.VecLoadLatency, 4GM4WriteVPERM.Latency);
+def C4GM4WriteVPERMLd:SchedWriteRes<[C4GM4AGU, C4GM4Load, C4GM4FPU01]> {
+ let Latency = !add(C864GM4Model.VecLoadLatency, C4GM4WriteVPERM.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 3;
}
-def : InstRW<[4GM4WriteVPERMLd], (instrs VPERM2I128rmi, VPERM2F128rmi)>;
+def : InstRW<[C4GM4WriteVPERMLd], (instrs VPERM2I128rmi, VPERM2F128rmi)>;
-def 4GM4WriteVPERMDY:SchedWriteRes<[4GM4FPU0]> {
+def C4GM4WriteVPERMDY:SchedWriteRes<[C4GM4FPU0]> {
let Latency = 3;
let ReleaseAtCycles = [1];
let NumMicroOps = 3;
}
-def : InstRW<[4GM4WriteVPERMDY], (instrs VPERMDYrr)>;
+def : InstRW<[C4GM4WriteVPERMDY], (instrs VPERMDYrr)>;
-def 4GM4WriteVPERMDYLd:SchedWriteRes<[4GM4AGU, 4GM4Load, 4GM4FPU0]> {
- let Latency = !add(C864GM4Model.VecLoadLatency, 4GM4WriteVPERMDY.Latency);
+def C4GM4WriteVPERMDYLd:SchedWriteRes<[C4GM4AGU, C4GM4Load, C4GM4FPU0]> {
+ let Latency = !add(C864GM4Model.VecLoadLatency, C4GM4WriteVPERMDY.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM4WriteVPERMDYLd], (instrs VPERMDYrm)>;
-
-defm : 4GM4WriteRes<WriteVecLoad, [4GM4AGU, 4GM4Load], !add(C864GM4Model.VecLoadLatency, 1), [1, 1], 1>;
-defm : 4GM4WriteRes<WriteVecLoadX, [4GM4AGU, 4GM4Load], !add(C864GM4Model.VecLoadLatency, 1), [1, 1], 1>;
-defm : 4GM4WriteRes<WriteVecLoadY, [4GM4AGU, 4GM4Load], !add(C864GM4Model.VecLoadLatency, 1), [1, 1], 1>;
-defm : 4GM4WriteRes<WriteVecLoadNT, [4GM4AGU, 4GM4Load], !add(C864GM4Model.VecLoadLatency, 1), [1, 1], 1>;
-defm : 4GM4WriteRes<WriteVecLoadNTY, [4GM4AGU, 4GM4Load], !add(C864GM4Model.VecLoadLatency, 1), [1, 1], 1>;
-defm : 4GM4WriteRes<WriteVecMaskedLoad, [4GM4AGU, 4GM4Load, 4GM4FPU02], !add(C864GM4Model.VecLoadLatency, 1), [1, 1, 2], 1>;
-defm : 4GM4WriteRes<WriteVecMaskedLoadY, [4GM4AGU, 4GM4Load, 4GM4FPU02], !add(C864GM4Model.VecLoadLatency, 1), [1, 1, 2], 1>;
-defm : 4GM4WriteRes<WriteVecStore, [4GM4AGU, 4GM4Store], C864GM4Model.StoreLatency>;
-defm : 4GM4WriteRes<WriteVecStoreX, [4GM4AGU, 4GM4Store], C864GM4Model.StoreLatency>;
-defm : 4GM4WriteRes<WriteVecStoreY, [4GM4AGU, 4GM4Store], C864GM4Model.StoreLatency>;
-defm : 4GM4WriteRes<WriteVecStoreNT, [4GM4FPU1, 4GM4AGU, 4GM4Store], !add(C864GM4Model.StoreLatency, 4)>;
-defm : 4GM4WriteRes<WriteVecStoreNTY, [4GM4FPU1, 4GM4AGU, 4GM4Store], !add(C864GM4Model.StoreLatency, 4)>;
-defm : 4GM4WriteRes<WriteVecMaskedStore32, [4GM4FPU02, 4GM4AGU, 4GM4Store], !add(C864GM4Model.StoreLatency, 1)>;
-defm : 4GM4WriteRes<WriteVecMaskedStore32Y, [4GM4FPU02, 4GM4AGU, 4GM4Store], !add(C864GM4Model.StoreLatency, 1)>;
-defm : 4GM4WriteRes<WriteVecMaskedStore64, [4GM4FPU02, 4GM4AGU, 4GM4Store], !add(C864GM4Model.StoreLatency, 1)>;
-defm : 4GM4WriteRes<WriteVecMaskedStore64Y, [4GM4FPU02, 4GM4AGU, 4GM4Store], !add(C864GM4Model.StoreLatency, 1)>;
-defm : 4GM4WriteRes<WriteVecMoveToGpr, [4GM4FPU1], 1>;
-defm : 4GM4WriteRes<WriteVecMoveFromGpr, [4GM4FPU1], 1>;
-defm : 4GM4WriteRes<WriteEMMS, [4GM4FPU], 0>;
-
-defm : 4GM4WriteResFPPair<WriteVecShift, [4GM4FPU1], 1>;
-defm : 4GM4WriteResFPPair<WriteVecShiftX, [4GM4FPU1], 1>;
-defm : 4GM4WriteResFPPair<WriteVecShiftY, [4GM4FPU1], 1>;
+def : InstRW<[C4GM4WriteVPERMDYLd], (instrs VPERMDYrm)>;
+
+defm : C4GM4WriteRes<WriteVecLoad, [C4GM4AGU, C4GM4Load], !add(C864GM4Model.VecLoadLatency, 1), [1, 1], 1>;
+defm : C4GM4WriteRes<WriteVecLoadX, [C4GM4AGU, C4GM4Load], !add(C864GM4Model.VecLoadLatency, 1), [1, 1], 1>;
+defm : C4GM4WriteRes<WriteVecLoadY, [C4GM4AGU, C4GM4Load], !add(C864GM4Model.VecLoadLatency, 1), [1, 1], 1>;
+defm : C4GM4WriteRes<WriteVecLoadNT, [C4GM4AGU, C4GM4Load], !add(C864GM4Model.VecLoadLatency, 1), [1, 1], 1>;
+defm : C4GM4WriteRes<WriteVecLoadNTY, [C4GM4AGU, C4GM4Load], !add(C864GM4Model.VecLoadLatency, 1), [1, 1], 1>;
+defm : C4GM4WriteRes<WriteVecMaskedLoad, [C4GM4AGU, C4GM4Load, C4GM4FPU02], !add(C864GM4Model.VecLoadLatency, 1), [1, 1, 2], 1>;
+defm : C4GM4WriteRes<WriteVecMaskedLoadY, [C4GM4AGU, C4GM4Load, C4GM4FPU02], !add(C864GM4Model.VecLoadLatency, 1), [1, 1, 2], 1>;
+defm : C4GM4WriteRes<WriteVecStore, [C4GM4AGU, C4GM4Store], C864GM4Model.StoreLatency>;
+defm : C4GM4WriteRes<WriteVecStoreX, [C4GM4AGU, C4GM4Store], C864GM4Model.StoreLatency>;
+defm : C4GM4WriteRes<WriteVecStoreY, [C4GM4AGU, C4GM4Store], C864GM4Model.StoreLatency>;
+defm : C4GM4WriteRes<WriteVecStoreNT, [C4GM4FPU1, C4GM4AGU, C4GM4Store], !add(C864GM4Model.StoreLatency, 4)>;
+defm : C4GM4WriteRes<WriteVecStoreNTY, [C4GM4FPU1, C4GM4AGU, C4GM4Store], !add(C864GM4Model.StoreLatency, 4)>;
+defm : C4GM4WriteRes<WriteVecMaskedStore32, [C4GM4FPU02, C4GM4AGU, C4GM4Store], !add(C864GM4Model.StoreLatency, 1)>;
+defm : C4GM4WriteRes<WriteVecMaskedStore32Y, [C4GM4FPU02, C4GM4AGU, C4GM4Store], !add(C864GM4Model.StoreLatency, 1)>;
+defm : C4GM4WriteRes<WriteVecMaskedStore64, [C4GM4FPU02, C4GM4AGU, C4GM4Store], !add(C864GM4Model.StoreLatency, 1)>;
+defm : C4GM4WriteRes<WriteVecMaskedStore64Y, [C4GM4FPU02, C4GM4AGU, C4GM4Store], !add(C864GM4Model.StoreLatency, 1)>;
+defm : C4GM4WriteRes<WriteVecMoveToGpr, [C4GM4FPU1], 1>;
+defm : C4GM4WriteRes<WriteVecMoveFromGpr, [C4GM4FPU1], 1>;
+defm : C4GM4WriteRes<WriteEMMS, [C4GM4FPU], 0>;
+
+defm : C4GM4WriteResFPPair<WriteVecShift, [C4GM4FPU1], 1>;
+defm : C4GM4WriteResFPPair<WriteVecShiftX, [C4GM4FPU1], 1>;
+defm : C4GM4WriteResFPPair<WriteVecShiftY, [C4GM4FPU1], 1>;
defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
-defm : 4GM4WriteResFPPair<WriteVecShiftImm, [4GM4FPU1], 1>;
-defm : 4GM4WriteResFPPair<WriteVecShiftImmX, [4GM4FPU1], 1>;
-defm : 4GM4WriteResFPPair<WriteVecShiftImmY, [4GM4FPU1], 1>;
+defm : C4GM4WriteResFPPair<WriteVecShiftImm, [C4GM4FPU1], 1>;
+defm : C4GM4WriteResFPPair<WriteVecShiftImmX, [C4GM4FPU1], 1>;
+defm : C4GM4WriteResFPPair<WriteVecShiftImmY, [C4GM4FPU1], 1>;
defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
-defm : 4GM4WriteResFPPair<WriteVarVecShift, [4GM4FPU0], 3, [2], 1>;
-defm : 4GM4WriteResFPPair<WriteVarVecShiftY, [4GM4FPU0], 3, [2], 1>;
+defm : C4GM4WriteResFPPair<WriteVarVecShift, [C4GM4FPU0], 3, [2], 1>;
+defm : C4GM4WriteResFPPair<WriteVarVecShiftY, [C4GM4FPU0], 3, [2], 1>;
defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
-defm : 4GM4WriteResFPPair<WriteVecLogic, [4GM4FPU], 1>;
-defm : 4GM4WriteResFPPair<WriteVecLogicX, [4GM4FPU], 1>;
-defm : 4GM4WriteResFPPair<WriteVecLogicY, [4GM4FPU], 1>;
+defm : C4GM4WriteResFPPair<WriteVecLogic, [C4GM4FPU], 1>;
+defm : C4GM4WriteResFPPair<WriteVecLogicX, [C4GM4FPU], 1>;
+defm : C4GM4WriteResFPPair<WriteVecLogicY, [C4GM4FPU], 1>;
defm : X86WriteResPairUnsupported<WriteVecLogicZ>;
-defm : 4GM4WriteResFPPair<WriteVecTest, [4GM4FPU01, 4GM4FPU1], 4, [1, 2], 1, 7, 1>;
-defm : 4GM4WriteResFPPair<WriteVecTestY, [4GM4FPU01, 4GM4FPU1], 8, [1, 2], 1, 7, 1>;
+defm : C4GM4WriteResFPPair<WriteVecTest, [C4GM4FPU01, C4GM4FPU1], 4, [1, 2], 1, 7, 1>;
+defm : C4GM4WriteResFPPair<WriteVecTestY, [C4GM4FPU01, C4GM4FPU1], 8, [1, 2], 1, 7, 1>;
defm : X86WriteResPairUnsupported<WriteVecTestZ>;
-defm : 4GM4WriteResFPPair<WriteVecALU, [4GM4FPU], 1>;
-defm : 4GM4WriteResFPPair<WriteVecALUX, [4GM4FPU], 1>;
-defm : 4GM4WriteResFPPair<WriteVecALUY, [4GM4FPU], 1>;
+defm : C4GM4WriteResFPPair<WriteVecALU, [C4GM4FPU], 1>;
+defm : C4GM4WriteResFPPair<WriteVecALUX, [C4GM4FPU], 1>;
+defm : C4GM4WriteResFPPair<WriteVecALUY, [C4GM4FPU], 1>;
defm : X86WriteResPairUnsupported<WriteVecALUZ>;
-defm : 4GM4WriteResFPPair<WriteVecIMul, [4GM4FPU0], 3>;
-defm : 4GM4WriteResFPPair<WriteVecIMulX, [4GM4FPU0], 3>;
-defm : 4GM4WriteResFPPair<WriteVecIMulY, [4GM4FPU0], 3>;
-defm : 4GM4WriteRes<WriteCLMul, [4GM4FPU3], 3>;
-defm : 4GM4WriteRes<WriteCLMulLd, [4GM4AGU, 4GM4Load, 4GM4FPU3], !add(C864GM4Model.VecLoadLatency, 3)>;
+defm : C4GM4WriteResFPPair<WriteVecIMul, [C4GM4FPU0], 3>;
+defm : C4GM4WriteResFPPair<WriteVecIMulX, [C4GM4FPU0], 3>;
+defm : C4GM4WriteResFPPair<WriteVecIMulY, [C4GM4FPU0], 3>;
+defm : C4GM4WriteRes<WriteCLMul, [C4GM4FPU3], 3>;
+defm : C4GM4WriteRes<WriteCLMulLd, [C4GM4AGU, C4GM4Load, C4GM4FPU3], !add(C864GM4Model.VecLoadLatency, 3)>;
defm : X86WriteResPairUnsupported<WriteVecIMulZ>;
-defm : 4GM4WriteResFPPair<WritePMULLD, [4GM4FPU0], 4, [2]>;
-defm : 4GM4WriteResFPPair<WritePMULLDY, [4GM4FPU0], 4, [2]>;
+defm : C4GM4WriteResFPPair<WritePMULLD, [C4GM4FPU0], 4, [2]>;
+defm : C4GM4WriteResFPPair<WritePMULLDY, [C4GM4FPU0], 4, [2]>;
defm : X86WriteResPairUnsupported<WritePMULLDZ>;
-defm : 4GM4WriteResFPPair<WriteShuffle, [4GM4FPU01], 1>;
-defm : 4GM4WriteResFPPair<WriteShuffleX, [4GM4FPU01], 1>;
-defm : 4GM4WriteResFPPair<WriteShuffleY, [4GM4FPU01], 1>;
+defm : C4GM4WriteResFPPair<WriteShuffle, [C4GM4FPU01], 1>;
+defm : C4GM4WriteResFPPair<WriteShuffleX, [C4GM4FPU01], 1>;
+defm : C4GM4WriteResFPPair<WriteShuffleY, [C4GM4FPU01], 1>;
defm : X86WriteResPairUnsupported<WriteShuffleZ>;
-defm : 4GM4WriteResFPPair<WriteVarShuffle, [4GM4FPU01], 1>;
-defm : 4GM4WriteResFPPair<WriteVarShuffleX,[4GM4FPU01], 1>;
-defm : 4GM4WriteResFPPair<WriteVarShuffleY,[4GM4FPU01], 1>;
+defm : C4GM4WriteResFPPair<WriteVarShuffle, [C4GM4FPU01], 1>;
+defm : C4GM4WriteResFPPair<WriteVarShuffleX,[C4GM4FPU01], 1>;
+defm : C4GM4WriteResFPPair<WriteVarShuffleY,[C4GM4FPU01], 1>;
defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
-defm : 4GM4WriteResFPPair<WriteBlend, [4GM4FPU], 1>;
-defm : 4GM4WriteResFPPair<WriteBlendY, [4GM4FPU], 1>;
+defm : C4GM4WriteResFPPair<WriteBlend, [C4GM4FPU], 1>;
+defm : C4GM4WriteResFPPair<WriteBlendY, [C4GM4FPU], 1>;
defm : X86WriteResPairUnsupported<WriteBlendZ>;
-defm : 4GM4WriteResFPPair<WriteVarBlend, [4GM4FPU0], 1>;
-defm : 4GM4WriteResFPPair<WriteVarBlendY, [4GM4FPU0], 1>;
+defm : C4GM4WriteResFPPair<WriteVarBlend, [C4GM4FPU0], 1>;
+defm : C4GM4WriteResFPPair<WriteVarBlendY, [C4GM4FPU0], 1>;
defm : X86WriteResPairUnsupported<WriteVarBlendZ>;
-defm : 4GM4WriteResFPPair<WriteShuffle256, [4GM4FPU01], 3>;
-defm : 4GM4WriteResFPPair<WriteVPMOV256, [4GM4FPU01], 1>;
-defm : 4GM4WriteResFPPair<WriteVarShuffle256, [4GM4FPU01], 2>;
-defm : 4GM4WriteResFPPair<WritePSADBW, [4GM4FPU0], 3>;
-defm : 4GM4WriteResFPPair<WritePSADBWX, [4GM4FPU0], 3>;
-defm : 4GM4WriteResFPPair<WritePSADBWY, [4GM4FPU0], 3>;
+defm : C4GM4WriteResFPPair<WriteShuffle256, [C4GM4FPU01], 3>;
+defm : C4GM4WriteResFPPair<WriteVPMOV256, [C4GM4FPU01], 1>;
+defm : C4GM4WriteResFPPair<WriteVarShuffle256, [C4GM4FPU01], 2>;
+defm : C4GM4WriteResFPPair<WritePSADBW, [C4GM4FPU0], 3>;
+defm : C4GM4WriteResFPPair<WritePSADBWX, [C4GM4FPU0], 3>;
+defm : C4GM4WriteResFPPair<WritePSADBWY, [C4GM4FPU0], 3>;
defm : X86WriteResPairUnsupported<WritePSADBWZ>;
-defm : 4GM4WriteResFPPair<WriteMPSAD, [4GM4FPU], 4, [8], 1>;
-defm : 4GM4WriteResFPPair<WriteMPSADY, [4GM4FPU], 4, [8], 1>;
-defm : 4GM4WriteResFPPair<WriteMPSADZ, [4GM4FPU], 4, [16], 1>;
-defm : 4GM4WriteResFPPair<WritePHMINPOS, [4GM4FPU0], 3>;
+defm : C4GM4WriteResFPPair<WriteMPSAD, [C4GM4FPU], 4, [8], 1>;
+defm : C4GM4WriteResFPPair<WriteMPSADY, [C4GM4FPU], 4, [8], 1>;
+defm : C4GM4WriteResFPPair<WriteMPSADZ, [C4GM4FPU], 4, [16], 1>;
+defm : C4GM4WriteResFPPair<WritePHMINPOS, [C4GM4FPU0], 3>;
// EXTRQ INSERTQ
-def 4GM4WriteEXTRQ_INSERTQ:SchedWriteRes<[4GM4FPU]> {
+def C4GM4WriteEXTRQ_INSERTQ:SchedWriteRes<[C4GM4FPU]> {
let Latency = 3;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM4WriteEXTRQ_INSERTQ], (instrs EXTRQ, EXTRQI, INSERTQ, INSERTQI)>;
+def : InstRW<[C4GM4WriteEXTRQ_INSERTQ], (instrs EXTRQ, EXTRQI, INSERTQ, INSERTQI)>;
-def 4GM4WriteVPMOVY:SchedWriteRes<[4GM4FPU01]> {
+def C4GM4WriteVPMOVY:SchedWriteRes<[C4GM4FPU01]> {
let Latency = 3;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM4WriteVPMOVY], (instregex "VPMOV(S|Z)X(BD|BQ|BW|DQ|WD|WQ)Yrr")>;
+def : InstRW<[C4GM4WriteVPMOVY], (instregex "VPMOV(S|Z)X(BD|BQ|BW|DQ|WD|WQ)Yrr")>;
-def 4GM4WriteVPMOVYLd:SchedWriteRes<[4GM4AGU, 4GM4Load, 4GM4FPU01]> {
- let Latency = !add(C864GM4Model.VecLoadLatency, 4GM4WriteVPMOVY.Latency);
+def C4GM4WriteVPMOVYLd:SchedWriteRes<[C4GM4AGU, C4GM4Load, C4GM4FPU01]> {
+ let Latency = !add(C864GM4Model.VecLoadLatency, C4GM4WriteVPMOVY.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM4WriteVPMOVYLd], (instregex "VPMOV(S|Z)X(BD|BQ|BW|DQ|WD|WQ)Yrm")>;
+def : InstRW<[C4GM4WriteVPMOVYLd], (instregex "VPMOV(S|Z)X(BD|BQ|BW|DQ|WD|WQ)Yrm")>;
-def 4GM4WriteVPS:SchedWriteRes<[4GM4FPU1]> {
+def C4GM4WriteVPS:SchedWriteRes<[C4GM4FPU1]> {
let Latency = 3;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM4WriteVPS], (instregex "VPS(LL|RA|RL)(D|Q|W)Yrr")>;
+def : InstRW<[C4GM4WriteVPS], (instregex "VPS(LL|RA|RL)(D|Q|W)Yrr")>;
-def 4GM4WriteVPSLd:SchedWriteRes<[4GM4AGU, 4GM4Load, 4GM4FPU1]> {
- let Latency = !add(C864GM4Model.VecLoadLatency, 4GM4WriteVPS.Latency);
+def C4GM4WriteVPSLd:SchedWriteRes<[C4GM4AGU, C4GM4Load, C4GM4FPU1]> {
+ let Latency = !add(C864GM4Model.VecLoadLatency, C4GM4WriteVPS.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM4WriteVPSLd], (instregex "VPS(LL|RA|RL)(D|Q|W)Yrm")>;
+def : InstRW<[C4GM4WriteVPSLd], (instregex "VPS(LL|RA|RL)(D|Q|W)Yrm")>;
-def 4GM4WritePMADDUBSW_PMULHRSW:SchedWriteRes<[4GM4FPU0]> {
+def C4GM4WritePMADDUBSW_PMULHRSW:SchedWriteRes<[C4GM4FPU0]> {
let Latency = 4;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM4WritePMADDUBSW_PMULHRSW], (instregex "(V?)PMADDUBSW(Y)?rr",
- "(V?)PMULHRSW(Y)?rr")>;
+def : InstRW<[C4GM4WritePMADDUBSW_PMULHRSW], (instregex "(V?)PMADDUBSW(Y)?rr",
+ "(V?)PMULHRSW(Y)?rr")>;
-def 4GM4WritePMADDUBSW_PMULHRSWLd:SchedWriteRes<[4GM4AGU, 4GM4Load, 4GM4FPU0]> {
- let Latency = !add(C864GM4Model.VecLoadLatency, 4GM4WritePMADDUBSW_PMULHRSW.Latency);
+def C4GM4WritePMADDUBSW_PMULHRSWLd:SchedWriteRes<[C4GM4AGU, C4GM4Load, C4GM4FPU0]> {
+ let Latency = !add(C864GM4Model.VecLoadLatency, C4GM4WritePMADDUBSW_PMULHRSW.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM4WritePMADDUBSW_PMULHRSWLd], (instregex "(V?)PMADDUBSW(Y)?rm",
- "(V?)PMULHRSW(Y)?rm")>;
+def : InstRW<[C4GM4WritePMADDUBSW_PMULHRSWLd], (instregex "(V?)PMADDUBSW(Y)?rm",
+ "(V?)PMULHRSW(Y)?rm")>;
// Vector insert/extract operations.
-defm : 4GM4WriteResFPPair<WriteVecInsert, [4GM4FPU01], 1>;
-defm : 4GM4WriteRes<WriteVecExtract, [4GM4FPU01, 4GM4FPU1], 2, [1, 2], 2>;
-defm : 4GM4WriteRes<WriteVecExtractSt, [4GM4FPU01, 4GM4FPU1, 4GM4AGU, 4GM4Store], 2, [1, 1, 1, 2], 2>;
+defm : C4GM4WriteResFPPair<WriteVecInsert, [C4GM4FPU01], 1>;
+defm : C4GM4WriteRes<WriteVecExtract, [C4GM4FPU01, C4GM4FPU1], 2, [1, 2], 2>;
+defm : C4GM4WriteRes<WriteVecExtractSt, [C4GM4FPU01, C4GM4FPU1, C4GM4AGU, C4GM4Store], 2, [1, 1, 1, 2], 2>;
-def 4GM4WritePINSR:SchedWriteRes<[4GM4FPU01]> {
+def C4GM4WritePINSR:SchedWriteRes<[C4GM4FPU01]> {
let Latency = 2;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM4WritePINSR], (instregex "(V?)PINSR(B|D|Q|W)rri")>;
+def : InstRW<[C4GM4WritePINSR], (instregex "(V?)PINSR(B|D|Q|W)rri")>;
-def 4GM4WritePINSRLd:SchedWriteRes<[4GM4AGU, 4GM4Load, 4GM4FPU01]> {
- let Latency = !add(C864GM4Model.VecLoadLatency, 4GM4WritePINSR.Latency);
+def C4GM4WritePINSRLd:SchedWriteRes<[C4GM4AGU, C4GM4Load, C4GM4FPU01]> {
+ let Latency = !add(C864GM4Model.VecLoadLatency, C4GM4WritePINSR.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM4WritePINSRLd], (instregex "(V?)PINSR(B|D|Q|W)rmi")>;
+def : InstRW<[C4GM4WritePINSRLd], (instregex "(V?)PINSR(B|D|Q|W)rmi")>;
// MOVMSK Instructions.
-defm : 4GM4WriteRes<WriteFMOVMSK, [4GM4FPU1], 1>;
-defm : 4GM4WriteRes<WriteMMXMOVMSK, [4GM4FPU1], 1>;
-defm : 4GM4WriteRes<WriteVecMOVMSK, [4GM4FPU1], 1>;
-defm : 4GM4WriteRes<WriteVecMOVMSKY, [4GM4FPU1], 1>;
+defm : C4GM4WriteRes<WriteFMOVMSK, [C4GM4FPU1], 1>;
+defm : C4GM4WriteRes<WriteMMXMOVMSK, [C4GM4FPU1], 1>;
+defm : C4GM4WriteRes<WriteVecMOVMSK, [C4GM4FPU1], 1>;
+defm : C4GM4WriteRes<WriteVecMOVMSKY, [C4GM4FPU1], 1>;
// Strings instructions.
-defm : 4GM4WriteResFPPair<WritePCmpIStrM, [4GM4FPU], 7, [25], 3>;
-defm : 4GM4WriteResFPPair<WritePCmpEStrM, [4GM4FPU], 8, [25], 8>;
-defm : 4GM4WriteResFPPair<WritePCmpIStrI, [4GM4FPU], 1, [8], 2>;
-defm : 4GM4WriteResFPPair<WritePCmpEStrI, [4GM4FPU], 2, [13], 8>;
+defm : C4GM4WriteResFPPair<WritePCmpIStrM, [C4GM4FPU], 7, [25], 3>;
+defm : C4GM4WriteResFPPair<WritePCmpEStrM, [C4GM4FPU], 8, [25], 8>;
+defm : C4GM4WriteResFPPair<WritePCmpIStrI, [C4GM4FPU], 1, [8], 2>;
+defm : C4GM4WriteResFPPair<WritePCmpEStrI, [C4GM4FPU], 2, [13], 8>;
// AES Instructions.
-defm : 4GM4WriteResFPPair<WriteAESDecEnc, [4GM4FPU23], 4>;
-defm : 4GM4WriteResFPPair<WriteAESIMC, [4GM4FPU23], 4>;
-defm : 4GM4WriteResFPPair<WriteAESKeyGen, [4GM4FPU23], 4>;
+defm : C4GM4WriteResFPPair<WriteAESDecEnc, [C4GM4FPU23], 4>;
+defm : C4GM4WriteResFPPair<WriteAESIMC, [C4GM4FPU23], 4>;
+defm : C4GM4WriteResFPPair<WriteAESKeyGen, [C4GM4FPU23], 4>;
-defm : 4GM4WriteRes<WriteFence, [4GM4AGU]>;
-defm : 4GM4WriteRes<WriteNop, []>;
+defm : C4GM4WriteRes<WriteFence, [C4GM4AGU]>;
+defm : C4GM4WriteRes<WriteNop, []>;
// SHA Instructions.
-def 4GM4WriteSHA1:SchedWriteRes<[4GM4FPU2]> {
+def C4GM4WriteSHA1:SchedWriteRes<[C4GM4FPU2]> {
let Latency = 1;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM4WriteSHA1], (instrs SHA1MSG1rr, SHA1MSG2rr, SHA1NEXTErr)>;
+def : InstRW<[C4GM4WriteSHA1], (instrs SHA1MSG1rr, SHA1MSG2rr, SHA1NEXTErr)>;
-def 4GM4WriteSHA1Ld:SchedWriteRes<[4GM4AGU, 4GM4Load, 4GM4FPU2]> {
- let Latency = !add(C864GM4Model.VecLoadLatency, 4GM4WriteSHA1.Latency);
+def C4GM4WriteSHA1Ld:SchedWriteRes<[C4GM4AGU, C4GM4Load, C4GM4FPU2]> {
+ let Latency = !add(C864GM4Model.VecLoadLatency, C4GM4WriteSHA1.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM4WriteSHA1Ld], (instrs SHA1MSG1rm, SHA1MSG2rm, SHA1NEXTErm)>;
+def : InstRW<[C4GM4WriteSHA1Ld], (instrs SHA1MSG1rm, SHA1MSG2rm, SHA1NEXTErm)>;
-def 4GM4WriteSHA1RNDS4rri:SchedWriteRes<[4GM4FPU2]> {
+def C4GM4WriteSHA1RNDS4rri:SchedWriteRes<[C4GM4FPU2]> {
let Latency = 6;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM4WriteSHA1RNDS4rri], (instrs SHA1RNDS4rri)>;
+def : InstRW<[C4GM4WriteSHA1RNDS4rri], (instrs SHA1RNDS4rri)>;
-def 4GM4WriteSHA1RNDS4rmi:SchedWriteRes<[4GM4AGU, 4GM4Load, 4GM4FPU2]> {
- let Latency = !add(C864GM4Model.VecLoadLatency, 4GM4WriteSHA1RNDS4rri.Latency);
+def C4GM4WriteSHA1RNDS4rmi:SchedWriteRes<[C4GM4AGU, C4GM4Load, C4GM4FPU2]> {
+ let Latency = !add(C864GM4Model.VecLoadLatency, C4GM4WriteSHA1RNDS4rri.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM4WriteSHA1RNDS4rmi], (instrs SHA1RNDS4rmi)>;
+def : InstRW<[C4GM4WriteSHA1RNDS4rmi], (instrs SHA1RNDS4rmi)>;
-def 4GM4WriteSHA256MSG1rr:SchedWriteRes<[4GM4FPU2]> {
+def C4GM4WriteSHA256MSG1rr:SchedWriteRes<[C4GM4FPU2]> {
let Latency = 2;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM4WriteSHA256MSG1rr], (instrs SHA256MSG1rr)>;
+def : InstRW<[C4GM4WriteSHA256MSG1rr], (instrs SHA256MSG1rr)>;
-def 4GM4WriteSHA256MSG1rm:SchedWriteRes<[4GM4AGU, 4GM4Load, 4GM4FPU2]> {
- let Latency = !add(C864GM4Model.VecLoadLatency, 4GM4WriteSHA256MSG1rr.Latency);
+def C4GM4WriteSHA256MSG1rm:SchedWriteRes<[C4GM4AGU, C4GM4Load, C4GM4FPU2]> {
+ let Latency = !add(C864GM4Model.VecLoadLatency, C4GM4WriteSHA256MSG1rr.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM4WriteSHA256MSG1rm], (instrs SHA256MSG1rm)>;
+def : InstRW<[C4GM4WriteSHA256MSG1rm], (instrs SHA256MSG1rm)>;
-def 4GM4WriteSHA256:SchedWriteRes<[4GM4FPU2]> {
+def C4GM4WriteSHA256:SchedWriteRes<[C4GM4FPU2]> {
let Latency = 4;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM4WriteSHA256], (instrs SHA256MSG2rr, SHA256RNDS2rr)>;
+def : InstRW<[C4GM4WriteSHA256], (instrs SHA256MSG2rr, SHA256RNDS2rr)>;
-def 4GM4WriteSHA256Ld:SchedWriteRes<[4GM4AGU, 4GM4Load, 4GM4FPU2]> {
- let Latency = !add(C864GM4Model.VecLoadLatency, 4GM4WriteSHA256.Latency);
+def C4GM4WriteSHA256Ld:SchedWriteRes<[C4GM4AGU, C4GM4Load, C4GM4FPU2]> {
+ let Latency = !add(C864GM4Model.VecLoadLatency, C4GM4WriteSHA256.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM4WriteSHA256Ld], (instrs SHA256MSG2rm, SHA256RNDS2rm)>;
+def : InstRW<[C4GM4WriteSHA256Ld], (instrs SHA256MSG2rm, SHA256RNDS2rm)>;
//===----------------------------------------------------------------------===//
// Zero Cycle Move
//===----------------------------------------------------------------------===//
-def 4GM4WriteZeroLatency : SchedWriteRes<[]> {
+def C4GM4WriteZeroLatency : SchedWriteRes<[]> {
let Latency = 0;
let ReleaseAtCycles = [];
let NumMicroOps = 1;
}
-def : InstRW<[4GM4WriteZeroLatency], (instrs MOV32rr, MOV32rr_REV,
- MOV64rr, MOV64rr_REV,
- MOVSX32rr32)>;
+def : InstRW<[C4GM4WriteZeroLatency], (instrs MOV32rr, MOV32rr_REV,
+ MOV64rr, MOV64rr_REV,
+ MOVSX32rr32)>;
-def 4GM4WriteSwapRenameable : SchedWriteRes<[]> {
+def C4GM4WriteSwapRenameable : SchedWriteRes<[]> {
let Latency = 0;
let ReleaseAtCycles = [];
let NumMicroOps = 2;
}
-def : InstRW<[4GM4WriteSwapRenameable], (instrs XCHG32rr, XCHG32ar,
- XCHG64rr, XCHG64ar)>;
+def : InstRW<[C4GM4WriteSwapRenameable], (instrs XCHG32rr, XCHG32ar,
+ XCHG64rr, XCHG64ar)>;
-defm : 4GM4WriteRes<WriteXCHG, [4GM4ALU], 1, [2], 1>;
+defm : C4GM4WriteRes<WriteXCHG, [C4GM4ALU], 1, [2], 1>;
-defm : 4GM4WriteRes<WriteFMoveX, [], 0, [], 1>;
-defm : 4GM4WriteRes<WriteFMoveY, [], 0, [], 1>;
+defm : C4GM4WriteRes<WriteFMoveX, [], 0, [], 1>;
+defm : C4GM4WriteRes<WriteFMoveY, [], 0, [], 1>;
defm : X86WriteResUnsupported<WriteFMoveZ>;
-defm : 4GM4WriteRes<WriteVecMove, [], 0, [], 1>;
-defm : 4GM4WriteRes<WriteVecMoveX, [], 0, [], 1>;
-defm : 4GM4WriteRes<WriteVecMoveY, [], 0, [], 1>;
+defm : C4GM4WriteRes<WriteVecMove, [], 0, [], 1>;
+defm : C4GM4WriteRes<WriteVecMoveX, [], 0, [], 1>;
+defm : C4GM4WriteRes<WriteVecMoveY, [], 0, [], 1>;
defm : X86WriteResUnsupported<WriteVecMoveZ>;
def : IsOptimizableRegisterMove<[
@@ -864,67 +864,67 @@ def : IsOptimizableRegisterMove<[
// Dependency breaking instructions.
//===----------------------------------------------------------------------===//
-def 4GM4WriteZeroIdiom : SchedWriteVariant<[
- SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM4WriteZeroLatency]>,
+def C4GM4WriteZeroIdiom : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [C4GM4WriteZeroLatency]>,
SchedVar<NoSchedPred, [WriteALU]>
]>;
-def : InstRW<[4GM4WriteZeroIdiom], (instrs XOR32rr, XOR32rr_REV,
- XOR64rr, XOR64rr_REV,
- SUB32rr, SUB32rr_REV,
- SUB64rr, SUB64rr_REV)>;
+def : InstRW<[C4GM4WriteZeroIdiom], (instrs XOR32rr, XOR32rr_REV,
+ XOR64rr, XOR64rr_REV,
+ SUB32rr, SUB32rr_REV,
+ SUB64rr, SUB64rr_REV)>;
-def 4GM4WriteZeroIdiomEFLAGS : SchedWriteVariant<[
- SchedVar<MCSchedPredicate<CheckSameRegOperand<0, 1>>, [4GM4WriteZeroLatency]>,
+def C4GM4WriteZeroIdiomEFLAGS : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<CheckSameRegOperand<0, 1>>, [C4GM4WriteZeroLatency]>,
SchedVar<NoSchedPred, [WriteALU]>
]>;
-def : InstRW<[4GM4WriteZeroIdiomEFLAGS], (instrs CMP8rr, CMP8rr_REV,
- CMP16rr, CMP16rr_REV,
- CMP32rr, CMP32rr_REV,
- CMP64rr, CMP64rr_REV)>;
+def : InstRW<[C4GM4WriteZeroIdiomEFLAGS], (instrs CMP8rr, CMP8rr_REV,
+ CMP16rr, CMP16rr_REV,
+ CMP32rr, CMP32rr_REV,
+ CMP64rr, CMP64rr_REV)>;
-def 4GM4WriteFZeroIdiom : SchedWriteVariant<[
- SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM4WriteZeroLatency]>,
+def C4GM4WriteFZeroIdiom : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [C4GM4WriteZeroLatency]>,
SchedVar<NoSchedPred, [WriteFLogic]>
]>;
-def : InstRW<[4GM4WriteFZeroIdiom], (instrs VXORPSrr, VXORPDrr,
- VANDNPSrr, VANDNPDrr)>;
+def : InstRW<[C4GM4WriteFZeroIdiom], (instrs VXORPSrr, VXORPDrr,
+ VANDNPSrr, VANDNPDrr)>;
-def 4GM4WriteFZeroIdiomY : SchedWriteVariant<[
- SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM4WriteZeroLatency]>,
+def C4GM4WriteFZeroIdiomY : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [C4GM4WriteZeroLatency]>,
SchedVar<NoSchedPred, [WriteFLogicY]>
]>;
-def : InstRW<[4GM4WriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr,
- VANDNPSYrr, VANDNPDYrr)>;
+def : InstRW<[C4GM4WriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr,
+ VANDNPSYrr, VANDNPDYrr)>;
-def 4GM4WriteVZeroIdiomLogicX : SchedWriteVariant<[
- SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM4WriteZeroLatency]>,
+def C4GM4WriteVZeroIdiomLogicX : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [C4GM4WriteZeroLatency]>,
SchedVar<NoSchedPred, [WriteVecLogicX]>
]>;
-def : InstRW<[4GM4WriteVZeroIdiomLogicX], (instrs VPXORrr, VPANDNrr)>;
+def : InstRW<[C4GM4WriteVZeroIdiomLogicX], (instrs VPXORrr, VPANDNrr)>;
-def 4GM4WriteVZeroIdiomLogicY : SchedWriteVariant<[
- SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM4WriteZeroLatency]>,
+def C4GM4WriteVZeroIdiomLogicY : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [C4GM4WriteZeroLatency]>,
SchedVar<NoSchedPred, [WriteVecLogicY]>
]>;
-def : InstRW<[4GM4WriteVZeroIdiomLogicY], (instrs VPXORYrr, VPANDNYrr)>;
+def : InstRW<[C4GM4WriteVZeroIdiomLogicY], (instrs VPXORYrr, VPANDNYrr)>;
-def 4GM4WriteVZeroIdiomALUX : SchedWriteVariant<[
- SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM4WriteZeroLatency]>,
+def C4GM4WriteVZeroIdiomALUX : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [C4GM4WriteZeroLatency]>,
SchedVar<NoSchedPred, [WriteVecALUX]>
]>;
-def : InstRW<[4GM4WriteVZeroIdiomALUX],
+def : InstRW<[C4GM4WriteVZeroIdiomALUX],
(instrs VPSUBBrr, VPSUBWrr, VPSUBDrr, VPSUBQrr,
VPCMPGTBrr, VPCMPGTWrr, VPCMPGTDrr, VPCMPGTQrr)>;
-def 4GM4WriteVZeroIdiomALUY : SchedWriteVariant<[
- SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM4WriteZeroLatency]>,
+def C4GM4WriteVZeroIdiomALUY : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [C4GM4WriteZeroLatency]>,
SchedVar<NoSchedPred, [WriteVecALUY]>
]>;
-def : InstRW<[4GM4WriteVZeroIdiomALUY],
+def : InstRW<[C4GM4WriteVZeroIdiomALUY],
(instrs VPSUBBYrr, VPSUBWYrr, VPSUBDYrr, VPSUBQYrr,
VPCMPGTBYrr, VPCMPGTWYrr, VPCMPGTDYrr, VPCMPGTQYrr)>;
diff --git a/llvm/lib/Target/X86/X86ScheduleC864GM7.td b/llvm/lib/Target/X86/X86ScheduleC864GM7.td
index 4d6270373cb62..7e1d964526ffa 100644
--- a/llvm/lib/Target/X86/X86ScheduleC864GM7.td
+++ b/llvm/lib/Target/X86/X86ScheduleC864GM7.td
@@ -37,75 +37,75 @@ let SchedModel = C864GM7Model in {
//===----------------------------------------------------------------------===//
// The C864GM7 has 4 ALUs.
-def 4GM7ALU0 : ProcResource<1>;
-def 4GM7ALU1 : ProcResource<1>;
-def 4GM7ALU2 : ProcResource<1>;
-def 4GM7ALU3 : ProcResource<1>;
+def C4GM7ALU0 : ProcResource<1>;
+def C4GM7ALU1 : ProcResource<1>;
+def C4GM7ALU2 : ProcResource<1>;
+def C4GM7ALU3 : ProcResource<1>;
-def 4GM7ALU : ProcResGroup<[4GM7ALU0, 4GM7ALU1, 4GM7ALU2, 4GM7ALU3]>;
-def 4GM7ALU12 : ProcResGroup<[4GM7ALU1, 4GM7ALU2]>;
-def 4GM7ALU03 : ProcResGroup<[4GM7ALU0, 4GM7ALU3]>;
+def C4GM7ALU : ProcResGroup<[C4GM7ALU0, C4GM7ALU1, C4GM7ALU2, C4GM7ALU3]>;
+def C4GM7ALU12 : ProcResGroup<[C4GM7ALU1, C4GM7ALU2]>;
+def C4GM7ALU03 : ProcResGroup<[C4GM7ALU0, C4GM7ALU3]>;
// BRU0 on ALU0.
-defvar 4GM7BRU0 = 4GM7ALU0;
+defvar C4GM7BRU0 = C4GM7ALU0;
// BRU1 is a separate branch execution unit.
-def 4GM7BRU1 : ProcResource<1>;
+def C4GM7BRU1 : ProcResource<1>;
-def 4GM7BRU : ProcResGroup<[4GM7BRU0, 4GM7BRU1]>;
+def C4GM7BRU : ProcResGroup<[C4GM7BRU0, C4GM7BRU1]>;
// The C864GM7 has 3 AGUs.
-def 4GM7AGU0 : ProcResource<1>;
-def 4GM7AGU1 : ProcResource<1>;
-def 4GM7AGU2 : ProcResource<1>;
+def C4GM7AGU0 : ProcResource<1>;
+def C4GM7AGU1 : ProcResource<1>;
+def C4GM7AGU2 : ProcResource<1>;
-def 4GM7AGU : ProcResGroup<[4GM7AGU0, 4GM7AGU1, 4GM7AGU2]>;
+def C4GM7AGU : ProcResGroup<[C4GM7AGU0, C4GM7AGU1, C4GM7AGU2]>;
// 96 Entry (4x24 entries) integer Scheduler.
-def 4GM7Int : ProcResGroup<[4GM7ALU0, 4GM7AGU0, 4GM7BRU0,
- 4GM7ALU1, 4GM7AGU1,
- 4GM7ALU2, 4GM7AGU2,
- 4GM7ALU3, 4GM7BRU1]> {
+def C4GM7Int : ProcResGroup<[C4GM7ALU0, C4GM7AGU0, C4GM7BRU0,
+ C4GM7ALU1, C4GM7AGU1,
+ C4GM7ALU2, C4GM7AGU2,
+ C4GM7ALU3, C4GM7BRU1]> {
let BufferSize = 96;
}
// The integer physical register file consists of 224 registers.
-def 4GM7IntegerPRF : RegisterFile<224,
- [GR64, CCR],
- [1, 1],
- [1, 0],
- 6, // Max moves that can be eliminated per cycle.
- 0>; // Restrict move elimination to zero regs.
+def C4GM7IntegerPRF : RegisterFile<224,
+ [GR64, CCR],
+ [1, 1],
+ [1, 0],
+ 6, // Max moves that can be eliminated per cycle.
+ 0>; // Restrict move elimination to zero regs.
//===----------------------------------------------------------------------===//
// Floating-Point Unit
//===----------------------------------------------------------------------===//
// The C864GM7 has 4 FPUs.
-def 4GM7FPU0 : ProcResource<1>;
-def 4GM7FPU1 : ProcResource<1>;
-def 4GM7FPU2 : ProcResource<1>;
-def 4GM7FPU3 : ProcResource<1>;
-
-def 4GM7FPU013 : ProcResGroup<[4GM7FPU0, 4GM7FPU1, 4GM7FPU3]>;
-def 4GM7FPU01 : ProcResGroup<[4GM7FPU0, 4GM7FPU1]>;
-def 4GM7FPU12 : ProcResGroup<[4GM7FPU1, 4GM7FPU2]>;
-def 4GM7FPU13 : ProcResGroup<[4GM7FPU1, 4GM7FPU3]>;
-def 4GM7FPU23 : ProcResGroup<[4GM7FPU2, 4GM7FPU3]>;
-def 4GM7FPU02 : ProcResGroup<[4GM7FPU0, 4GM7FPU2]>;
-def 4GM7FPU03 : ProcResGroup<[4GM7FPU0, 4GM7FPU3]>;
+def C4GM7FPU0 : ProcResource<1>;
+def C4GM7FPU1 : ProcResource<1>;
+def C4GM7FPU2 : ProcResource<1>;
+def C4GM7FPU3 : ProcResource<1>;
+
+def C4GM7FPU013 : ProcResGroup<[C4GM7FPU0, C4GM7FPU1, C4GM7FPU3]>;
+def C4GM7FPU01 : ProcResGroup<[C4GM7FPU0, C4GM7FPU1]>;
+def C4GM7FPU12 : ProcResGroup<[C4GM7FPU1, C4GM7FPU2]>;
+def C4GM7FPU13 : ProcResGroup<[C4GM7FPU1, C4GM7FPU3]>;
+def C4GM7FPU23 : ProcResGroup<[C4GM7FPU2, C4GM7FPU3]>;
+def C4GM7FPU02 : ProcResGroup<[C4GM7FPU0, C4GM7FPU2]>;
+def C4GM7FPU03 : ProcResGroup<[C4GM7FPU0, C4GM7FPU3]>;
// 48 Entry (4x12 entries) floating-point Scheduler.
-def 4GM7FPU : ProcResGroup<[4GM7FPU0, 4GM7FPU1, 4GM7FPU2, 4GM7FPU3]> {
+def C4GM7FPU : ProcResGroup<[C4GM7FPU0, C4GM7FPU1, C4GM7FPU2, C4GM7FPU3]> {
let BufferSize = 48;
}
// The floating point physical register file consists of 256 bits x 208 registers.
-def 4GM7FpuPRF : RegisterFile<208,
- [VR64, VR128, VR256, VR512],
- [1, 1, 1, 2],
- [0, 1, 1, 0],
- 6, // Max moves that can be eliminated per cycle.
- 0>; // Restrict move elimination to zero regs.
+def C4GM7FpuPRF : RegisterFile<208,
+ [VR64, VR128, VR256, VR512],
+ [1, 1, 1, 2],
+ [0, 1, 1, 0],
+ 6, // Max moves that can be eliminated per cycle.
+ 0>; // Restrict move elimination to zero regs.
//===----------------------------------------------------------------------===//
@@ -114,23 +114,23 @@ def 4GM7FpuPRF : RegisterFile<208,
// Load/Store Units and Memory Queues
// The C864GM7 has 4 LS Units.
-def 4GM7LSU : ProcResource<4>;
+def C4GM7LSU : ProcResource<4>;
// The three of LSU can be loads.
-let Super = 4GM7LSU in
-def 4GM7Load : ProcResource<3> {
+let Super = C4GM7LSU in
+def C4GM7Load : ProcResource<3> {
// The LDQ is 54.
let BufferSize = 54;
}
-def 4GM7LoadQueue : LoadQueue<4GM7Load>;
+def C4GM7LoadQueue : LoadQueue<C4GM7Load>;
// All four of LSU can be loads.
-let Super = 4GM7LSU in
-def 4GM7Store : ProcResource<4> {
+let Super = C4GM7LSU in
+def C4GM7Store : ProcResource<4> {
// The STQ is 52.
let BufferSize = 52;
}
-def 4GM7StoreQueue : StoreQueue<4GM7Store>;
+def C4GM7StoreQueue : StoreQueue<C4GM7Store>;
def : ReadAdvance<ReadAfterLd, C864GM7Model.LoadLatency>;
def : ReadAdvance<ReadAfterVecLd, C864GM7Model.VecLoadLatency>;
@@ -142,7 +142,7 @@ def : ReadAdvance<ReadInt2Fpu, 0>;
//===----------------------------------------------------------------------===//
// Retire Control Unit
//===----------------------------------------------------------------------===//
-def 4GM7RCU : RetireControlUnit<C864GM7Model.MicroOpBufferSize, 8>;
+def C4GM7RCU : RetireControlUnit<C864GM7Model.MicroOpBufferSize, 8>;
//===----------------------------------------------------------------------===//
// Basic helper classes.
@@ -155,7 +155,7 @@ def 4GM7RCU : RetireControlUnit<C864GM7Model.MicroOpBufferSize, 8>;
// folded loads.
-multiclass __4GM7WriteRes<SchedWrite SchedRW, list<ProcResourceKind> ExePorts,
+multiclass __C4GM7WriteRes<SchedWrite SchedRW, list<ProcResourceKind> ExePorts,
int Lat = 1, list<int> Res = [], int UOps = 1> {
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
@@ -164,14 +164,14 @@ multiclass __4GM7WriteRes<SchedWrite SchedRW, list<ProcResourceKind> ExePorts,
}
}
-multiclass __4GM7WriteResPair<X86FoldableSchedWrite SchedRW,
+multiclass __C4GM7WriteResPair<X86FoldableSchedWrite SchedRW,
list<ProcResourceKind> ExePorts, int Lat,
list<int> Res, int UOps, int LoadLat, int LoadUOps,
ProcResourceKind AGU, int LoadRes> {
- defm : __4GM7WriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
+ defm : __C4GM7WriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
- defm : __4GM7WriteRes<SchedRW.Folded,
- !listconcat([AGU, 4GM7Load], ExePorts),
+ defm : __C4GM7WriteRes<SchedRW.Folded,
+ !listconcat([AGU, C4GM7Load], ExePorts),
!add(LoadLat, Lat),
!if(!and(!empty(Res), !eq(LoadRes, 1)),
[],
@@ -183,70 +183,70 @@ multiclass __4GM7WriteResPair<X86FoldableSchedWrite SchedRW,
}
// For classes without folded loads.
-multiclass 4GM7WriteRes<SchedWrite SchedRW,
+multiclass C4GM7WriteRes<SchedWrite SchedRW,
list<ProcResourceKind> ExePorts, int Lat = 1,
list<int> Res = [], int UOps = 1> {
- defm : __4GM7WriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
+ defm : __C4GM7WriteRes<SchedRW, ExePorts, Lat, Res, UOps>;
}
// For classes with folded loads.
-multiclass 4GM7WriteResIntPair<X86FoldableSchedWrite SchedRW,
+multiclass C4GM7WriteResIntPair<X86FoldableSchedWrite SchedRW,
list<ProcResourceKind> ExePorts, int Lat = 1,
list<int> Res = [], int UOps = 1,
int LoadUOps = 0, int LoadRes = 1> {
- defm : __4GM7WriteResPair<SchedRW, ExePorts, Lat, Res, UOps,
+ defm : __C4GM7WriteResPair<SchedRW, ExePorts, Lat, Res, UOps,
C864GM7Model.LoadLatency,
- LoadUOps, 4GM7AGU, LoadRes>;
+ LoadUOps, C4GM7AGU, LoadRes>;
}
-multiclass 4GM7WriteResFPPair<X86FoldableSchedWrite SchedRW,
+multiclass C4GM7WriteResFPPair<X86FoldableSchedWrite SchedRW,
list<ProcResourceKind> ExePorts, int Lat = 1,
list<int> Res = [], int UOps = 1,
int LoadUOps = 0, int LoadRes = 1> {
- defm : __4GM7WriteResPair<SchedRW, ExePorts, Lat, Res, UOps,
+ defm : __C4GM7WriteResPair<SchedRW, ExePorts, Lat, Res, UOps,
C864GM7Model.VecLoadLatency,
- LoadUOps, 4GM7AGU, LoadRes>;
+ LoadUOps, C4GM7AGU, LoadRes>;
}
// Microcoded Instructions
-def 4GM7WriteMicrocoded : SchedWriteRes<[]> {
+def C4GM7WriteMicrocoded : SchedWriteRes<[]> {
let Latency = 100;
}
-def : SchedAlias<WriteMicrocoded, 4GM7WriteMicrocoded>;
-def : SchedAlias<WriteSystem, 4GM7WriteMicrocoded>;
-def : SchedAlias<WriteFCMOV, 4GM7WriteMicrocoded>;
-def : SchedAlias<WriteLDMXCSR, 4GM7WriteMicrocoded>;
-def : SchedAlias<WriteSTMXCSR, 4GM7WriteMicrocoded>;
+def : SchedAlias<WriteMicrocoded, C4GM7WriteMicrocoded>;
+def : SchedAlias<WriteSystem, C4GM7WriteMicrocoded>;
+def : SchedAlias<WriteFCMOV, C4GM7WriteMicrocoded>;
+def : SchedAlias<WriteLDMXCSR, C4GM7WriteMicrocoded>;
+def : SchedAlias<WriteSTMXCSR, C4GM7WriteMicrocoded>;
// Integer Instructions
-defm : 4GM7WriteRes<WriteRMW, [4GM7AGU, 4GM7Store], C864GM7Model.StoreLatency, [1, 1], 0>;
+defm : C4GM7WriteRes<WriteRMW, [C4GM7AGU, C4GM7Store], C864GM7Model.StoreLatency, [1, 1], 0>;
-defm : 4GM7WriteRes<WriteStore, [4GM7AGU, 4GM7Store], C864GM7Model.StoreLatency, [1, 2], 1>;
-defm : 4GM7WriteRes<WriteStoreNT, [4GM7AGU, 4GM7Store], C864GM7Model.StoreLatency, [1, 2], 1>;
-defm : 4GM7WriteRes<WriteLoad, [4GM7AGU, 4GM7Load], !add(C864GM7Model.LoadLatency, 1), [1, 1], 1>;
-defm : 4GM7WriteRes<WriteMove, [4GM7ALU], 1, [4], 1>;
+defm : C4GM7WriteRes<WriteStore, [C4GM7AGU, C4GM7Store], C864GM7Model.StoreLatency, [1, 2], 1>;
+defm : C4GM7WriteRes<WriteStoreNT, [C4GM7AGU, C4GM7Store], C864GM7Model.StoreLatency, [1, 2], 1>;
+defm : C4GM7WriteRes<WriteLoad, [C4GM7AGU, C4GM7Load], !add(C864GM7Model.LoadLatency, 1), [1, 1], 1>;
+defm : C4GM7WriteRes<WriteMove, [C4GM7ALU], 1, [4], 1>;
def : InstRW<[WriteMove], (instrs COPY, MOVSX16rr16, MOVSX16rr32,
MOVZX16rr16, MOVSX16rr8, MOVZX16rr8)>;
-defm : 4GM7WriteRes<WriteVecMaskedGatherWriteback, [], !add(1, C864GM7Model.VecLoadLatency)>;
+defm : C4GM7WriteRes<WriteVecMaskedGatherWriteback, [], !add(1, C864GM7Model.VecLoadLatency)>;
-defm : 4GM7WriteRes<WriteZero, [], 0, [], 1>;
-defm : 4GM7WriteRes<WriteLEA, [4GM7AGU]>;
-defm : 4GM7WriteResIntPair<WriteALU, [4GM7ALU], 1>;
-defm : 4GM7WriteResIntPair<WriteADC, [4GM7ALU], 1>;
+defm : C4GM7WriteRes<WriteZero, [], 0, [], 1>;
+defm : C4GM7WriteRes<WriteLEA, [C4GM7AGU]>;
+defm : C4GM7WriteResIntPair<WriteALU, [C4GM7ALU], 1>;
+defm : C4GM7WriteResIntPair<WriteADC, [C4GM7ALU], 1>;
// This write is used for slow LEA instructions.
-def 4GM7Write3OpsLEA : SchedWriteRes<[4GM7ALU]> {
+def C4GM7Write3OpsLEA : SchedWriteRes<[C4GM7ALU]> {
let Latency = 2;
let ReleaseAtCycles = [1];
let NumMicroOps = 2;
}
// a slow LEA is either a 3Ops LEA (base, index, offset),
// or an LEA with a `Scale` value different than 1.
-def 4GM7SlowLEAPredicate : MCSchedPredicate<
+def C4GM7SlowLEAPredicate : MCSchedPredicate<
CheckAny<[
IsThreeOperandsLEAFn,
CheckAll<[
@@ -256,3016 +256,3016 @@ def 4GM7SlowLEAPredicate : MCSchedPredicate<
]>
>;
-def 4GM7WriteLEA : SchedWriteVariant<[
- SchedVar<4GM7SlowLEAPredicate, [4GM7Write3OpsLEA]>,
+def C4GM7WriteLEA : SchedWriteVariant<[
+ SchedVar<C4GM7SlowLEAPredicate, [C4GM7Write3OpsLEA]>,
SchedVar<NoSchedPred, [WriteLEA]>
]>;
-def : InstRW<[4GM7WriteLEA], (instrs LEA64r, LEA64_32r)>;
+def : InstRW<[C4GM7WriteLEA], (instrs LEA64r, LEA64_32r)>;
// MUL IMUL MULX
-defm : 4GM7WriteResIntPair<WriteIMul8, [4GM7ALU1], 3, [3], 1>;
-defm : 4GM7WriteResIntPair<WriteIMul16, [4GM7ALU1], 3, [3], 1>;
-defm : 4GM7WriteResIntPair<WriteIMul16Imm, [4GM7ALU1], 4, [3], 2>;
-defm : 4GM7WriteResIntPair<WriteIMul16Reg, [4GM7ALU1], 3>;
-defm : 4GM7WriteResIntPair<WriteIMul32, [4GM7ALU1], 3, [3], 1>;
-defm : 4GM7WriteResIntPair<WriteIMul32Imm, [4GM7ALU1], 3, [3], 2>;
-defm : 4GM7WriteResIntPair<WriteIMul32Reg, [4GM7ALU1], 3>;
-defm : 4GM7WriteResIntPair<WriteIMul64, [4GM7ALU1], 3, [4], 1>;
-defm : 4GM7WriteResIntPair<WriteIMul64Imm, [4GM7ALU1], 3, [4], 2>;
-defm : 4GM7WriteResIntPair<WriteIMul64Reg, [4GM7ALU1], 3>;
-
-defm : 4GM7WriteResIntPair<WriteMULX32, [4GM7ALU1], 3, [2], 2>;
-defm : 4GM7WriteResIntPair<WriteMULX64, [4GM7ALU1], 4, [2], 2>;
-defm : 4GM7WriteRes<WriteIMulHLd, [4GM7ALU1], !add(3, C864GM7Model.LoadLatency), [], 0>;
-defm : 4GM7WriteRes<WriteIMulH, [4GM7ALU1], 3, [], 0>;
+defm : C4GM7WriteResIntPair<WriteIMul8, [C4GM7ALU1], 3, [3], 1>;
+defm : C4GM7WriteResIntPair<WriteIMul16, [C4GM7ALU1], 3, [3], 1>;
+defm : C4GM7WriteResIntPair<WriteIMul16Imm, [C4GM7ALU1], 4, [3], 2>;
+defm : C4GM7WriteResIntPair<WriteIMul16Reg, [C4GM7ALU1], 3>;
+defm : C4GM7WriteResIntPair<WriteIMul32, [C4GM7ALU1], 3, [3], 1>;
+defm : C4GM7WriteResIntPair<WriteIMul32Imm, [C4GM7ALU1], 3, [3], 2>;
+defm : C4GM7WriteResIntPair<WriteIMul32Reg, [C4GM7ALU1], 3>;
+defm : C4GM7WriteResIntPair<WriteIMul64, [C4GM7ALU1], 3, [4], 1>;
+defm : C4GM7WriteResIntPair<WriteIMul64Imm, [C4GM7ALU1], 3, [4], 2>;
+defm : C4GM7WriteResIntPair<WriteIMul64Reg, [C4GM7ALU1], 3>;
+
+defm : C4GM7WriteResIntPair<WriteMULX32, [C4GM7ALU1], 3, [2], 2>;
+defm : C4GM7WriteResIntPair<WriteMULX64, [C4GM7ALU1], 4, [2], 2>;
+defm : C4GM7WriteRes<WriteIMulHLd, [C4GM7ALU1], !add(3, C864GM7Model.LoadLatency), [], 0>;
+defm : C4GM7WriteRes<WriteIMulH, [C4GM7ALU1], 3, [], 0>;
// IDIV
-defm : 4GM7WriteResIntPair<WriteDiv8, [4GM7ALU3], 9, [4], 2>;
-defm : 4GM7WriteResIntPair<WriteDiv16, [4GM7ALU3], 10, [4], 2>;
-defm : 4GM7WriteResIntPair<WriteDiv32, [4GM7ALU3], 12, [7], 2>;
-defm : 4GM7WriteResIntPair<WriteDiv64, [4GM7ALU3], 18, [10], 2>;
-defm : 4GM7WriteResIntPair<WriteIDiv8, [4GM7ALU3], 9, [4], 2>;
-defm : 4GM7WriteResIntPair<WriteIDiv16, [4GM7ALU3], 10, [4], 2>;
-defm : 4GM7WriteResIntPair<WriteIDiv32, [4GM7ALU3], 12, [7], 2>;
-defm : 4GM7WriteResIntPair<WriteIDiv64, [4GM7ALU3], 18, [10], 2>;
-
-defm : 4GM7WriteRes<WriteBSWAP32, [4GM7ALU], 1, [1], 1>;
-defm : 4GM7WriteRes<WriteBSWAP64, [4GM7ALU], 1, [1], 1>;
-defm : 4GM7WriteRes<WriteCMPXCHG, [4GM7ALU], 3, [12], 5>;
-defm : 4GM7WriteRes<WriteCMPXCHGRMW,[4GM7ALU], 3, [12], 6>;
-
-def 4GM7WriteXADD : SchedWriteRes<[4GM7ALU]> {
+defm : C4GM7WriteResIntPair<WriteDiv8, [C4GM7ALU3], 9, [4], 2>;
+defm : C4GM7WriteResIntPair<WriteDiv16, [C4GM7ALU3], 10, [4], 2>;
+defm : C4GM7WriteResIntPair<WriteDiv32, [C4GM7ALU3], 12, [7], 2>;
+defm : C4GM7WriteResIntPair<WriteDiv64, [C4GM7ALU3], 18, [10], 2>;
+defm : C4GM7WriteResIntPair<WriteIDiv8, [C4GM7ALU3], 9, [4], 2>;
+defm : C4GM7WriteResIntPair<WriteIDiv16, [C4GM7ALU3], 10, [4], 2>;
+defm : C4GM7WriteResIntPair<WriteIDiv32, [C4GM7ALU3], 12, [7], 2>;
+defm : C4GM7WriteResIntPair<WriteIDiv64, [C4GM7ALU3], 18, [10], 2>;
+
+defm : C4GM7WriteRes<WriteBSWAP32, [C4GM7ALU], 1, [1], 1>;
+defm : C4GM7WriteRes<WriteBSWAP64, [C4GM7ALU], 1, [1], 1>;
+defm : C4GM7WriteRes<WriteCMPXCHG, [C4GM7ALU], 3, [12], 5>;
+defm : C4GM7WriteRes<WriteCMPXCHGRMW,[C4GM7ALU], 3, [12], 6>;
+
+def C4GM7WriteXADD : SchedWriteRes<[C4GM7ALU]> {
let Latency = 1;
let ReleaseAtCycles = [2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteXADD], (instrs XADD8rr, XADD16rr, XADD32rr, XADD64rr)>;
+def : InstRW<[C4GM7WriteXADD], (instrs XADD8rr, XADD16rr, XADD32rr, XADD64rr)>;
-def 4GM7WriteXADDLd : SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7ALU]> {
- let Latency = !add(C864GM7Model.LoadLatency, 4GM7WriteXADD.Latency);
+def C4GM7WriteXADDLd : SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7ALU]> {
+ let Latency = !add(C864GM7Model.LoadLatency, C4GM7WriteXADD.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteXADDLd], (instrs XADD8rm, XADD16rm, XADD32rm, XADD64rm)>;
+def : InstRW<[C4GM7WriteXADDLd], (instrs XADD8rm, XADD16rm, XADD32rm, XADD64rm)>;
-def 4GM7WriteCMPXCHG8rr : SchedWriteRes<[4GM7ALU]> {
+def C4GM7WriteCMPXCHG8rr : SchedWriteRes<[C4GM7ALU]> {
let Latency = 3;
let ReleaseAtCycles = [12];
let NumMicroOps = 3;
}
-def : InstRW<[4GM7WriteCMPXCHG8rr], (instrs CMPXCHG8rr)>;
+def : InstRW<[C4GM7WriteCMPXCHG8rr], (instrs CMPXCHG8rr)>;
-def 4GM7WriteCMPXCHG8mr : SchedWriteRes<[4GM7ALU, 4GM7AGU, 4GM7Store]> {
- let Latency = !add(4GM7WriteCMPXCHG8rr.Latency, C864GM7Model.StoreLatency);
+def C4GM7WriteCMPXCHG8mr : SchedWriteRes<[C4GM7ALU, C4GM7AGU, C4GM7Store]> {
+ let Latency = !add(C4GM7WriteCMPXCHG8rr.Latency, C864GM7Model.StoreLatency);
let ReleaseAtCycles = [12, 1, 1];
let NumMicroOps = 5;
}
-def : InstRW<[4GM7WriteCMPXCHG8mr], (instrs CMPXCHG8rm, LCMPXCHG8)>;
+def : InstRW<[C4GM7WriteCMPXCHG8mr], (instrs CMPXCHG8rm, LCMPXCHG8)>;
-def 4GM7WriteXCHG : SchedWriteRes<[4GM7ALU]> {
+def C4GM7WriteXCHG : SchedWriteRes<[C4GM7ALU]> {
let Latency = 1;
let ReleaseAtCycles = [2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteXCHG], (instrs XCHG8rr, XCHG16ar, XCHG16rr)>;
+def : InstRW<[C4GM7WriteXCHG], (instrs XCHG8rr, XCHG16ar, XCHG16rr)>;
-def 4GM7WriteXCHGLd : SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7ALU]> {
- let Latency = !add(C864GM7Model.LoadLatency, 4GM7WriteXCHG.Latency);
+def C4GM7WriteXCHGLd : SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7ALU]> {
+ let Latency = !add(C864GM7Model.LoadLatency, C4GM7WriteXCHG.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteXCHGLd], (instrs XCHG8rm, XCHG16rm)>;
+def : InstRW<[C4GM7WriteXCHGLd], (instrs XCHG8rm, XCHG16rm)>;
-defm : 4GM7WriteResIntPair<WriteShift, [4GM7ALU], 1>;
-defm : 4GM7WriteResIntPair<WriteShiftCL, [4GM7ALU], 1>;
-defm : 4GM7WriteResIntPair<WriteRotate, [4GM7ALU], 1>;
-defm : 4GM7WriteResIntPair<WriteRotateCL, [4GM7ALU], 1>;
+defm : C4GM7WriteResIntPair<WriteShift, [C4GM7ALU], 1>;
+defm : C4GM7WriteResIntPair<WriteShiftCL, [C4GM7ALU], 1>;
+defm : C4GM7WriteResIntPair<WriteRotate, [C4GM7ALU], 1>;
+defm : C4GM7WriteResIntPair<WriteRotateCL, [C4GM7ALU], 1>;
-def 4GM7WriteRCR:SchedWriteRes<[4GM7ALU]> {
+def C4GM7WriteRCR:SchedWriteRes<[C4GM7ALU]> {
let Latency = 3;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteRCR], (instregex "RCR(8|16|32|64)rCL")>;
+def : InstRW<[C4GM7WriteRCR], (instregex "RCR(8|16|32|64)rCL")>;
-def 4GM7WriteRCRLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7ALU]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteRCR.Latency);
+def C4GM7WriteRCRLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7ALU]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteRCR.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteRCRLd], (instregex "RCR(8|16|32|64)mCL")>;
+def : InstRW<[C4GM7WriteRCRLd], (instregex "RCR(8|16|32|64)mCL")>;
-def 4GM7WriteRCL:SchedWriteRes<[4GM7ALU]> {
+def C4GM7WriteRCL:SchedWriteRes<[C4GM7ALU]> {
let Latency = 4;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteRCL], (instregex "RCL(8|16|32|64)rCL")>;
+def : InstRW<[C4GM7WriteRCL], (instregex "RCL(8|16|32|64)rCL")>;
-def 4GM7WriteRCLLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7ALU]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteRCL.Latency);
+def C4GM7WriteRCLLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7ALU]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteRCL.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteRCLLd], (instregex "RCL(8|16|32|64)mCL")>;
+def : InstRW<[C4GM7WriteRCLLd], (instregex "RCL(8|16|32|64)mCL")>;
-defm : 4GM7WriteRes<WriteSHDrri, [4GM7ALU], 3, [4], 6>;
-defm : 4GM7WriteRes<WriteSHDrrcl, [4GM7ALU], 3, [4], 7>;
-defm : 4GM7WriteRes<WriteSHDmri, [4GM7ALU, 4GM7AGU, 4GM7Store], !add(3, C864GM7Model.StoreLatency), [4, 1, 1], 8>;
-defm : 4GM7WriteRes<WriteSHDmrcl, [4GM7ALU, 4GM7AGU, 4GM7Store], !add(3, C864GM7Model.StoreLatency), [4, 1, 1], 8>;
+defm : C4GM7WriteRes<WriteSHDrri, [C4GM7ALU], 3, [4], 6>;
+defm : C4GM7WriteRes<WriteSHDrrcl, [C4GM7ALU], 3, [4], 7>;
+defm : C4GM7WriteRes<WriteSHDmri, [C4GM7ALU, C4GM7AGU, C4GM7Store], !add(3, C864GM7Model.StoreLatency), [4, 1, 1], 8>;
+defm : C4GM7WriteRes<WriteSHDmrcl, [C4GM7ALU, C4GM7AGU, C4GM7Store], !add(3, C864GM7Model.StoreLatency), [4, 1, 1], 8>;
-defm : 4GM7WriteResIntPair<WriteJump, [4GM7ALU], 1>;
-defm : 4GM7WriteResIntPair<WriteCRC32, [4GM7ALU], 3, [12], 3>;
+defm : C4GM7WriteResIntPair<WriteJump, [C4GM7ALU], 1>;
+defm : C4GM7WriteResIntPair<WriteCRC32, [C4GM7ALU], 3, [12], 3>;
-defm : 4GM7WriteResIntPair<WriteCMOV, [4GM7ALU], 1>;
-defm : 4GM7WriteRes<WriteSETCC, [4GM7ALU], 1, [1], 1>;
-defm : 4GM7WriteRes<WriteSETCCStore, [4GM7ALU, 4GM7AGU, 4GM7Store], 1, [2, 1, 1], 2>;
-defm : 4GM7WriteRes<WriteLAHFSAHF, [4GM7ALU], 2, [2], 4>;
+defm : C4GM7WriteResIntPair<WriteCMOV, [C4GM7ALU], 1>;
+defm : C4GM7WriteRes<WriteSETCC, [C4GM7ALU], 1, [1], 1>;
+defm : C4GM7WriteRes<WriteSETCCStore, [C4GM7ALU, C4GM7AGU, C4GM7Store], 1, [2, 1, 1], 2>;
+defm : C4GM7WriteRes<WriteLAHFSAHF, [C4GM7ALU], 2, [2], 4>;
-defm : 4GM7WriteRes<WriteBitTest, [4GM7ALU], 1, [1], 1>;
-defm : 4GM7WriteRes<WriteBitTestImmLd, [4GM7AGU, 4GM7Load, 4GM7ALU], !add(C864GM7Model.LoadLatency, 1), [1,1,1], 2>;
-defm : 4GM7WriteRes<WriteBitTestRegLd, [4GM7AGU, 4GM7Load, 4GM7ALU], !add(C864GM7Model.LoadLatency, 1), [1,1,1], 6>;
-defm : 4GM7WriteRes<WriteBitTestSet, [4GM7ALU], 2, [1], 2>;
-defm : 4GM7WriteRes<WriteBitTestSetImmLd, [4GM7AGU, 4GM7Load, 4GM7ALU], !add(C864GM7Model.LoadLatency, 2), [1, 1, 1], 4>;
-defm : 4GM7WriteRes<WriteBitTestSetRegLd, [4GM7AGU, 4GM7Load, 4GM7ALU], !add(C864GM7Model.LoadLatency, 2), [1, 1, 1], 8>;
+defm : C4GM7WriteRes<WriteBitTest, [C4GM7ALU], 1, [1], 1>;
+defm : C4GM7WriteRes<WriteBitTestImmLd, [C4GM7AGU, C4GM7Load, C4GM7ALU], !add(C864GM7Model.LoadLatency, 1), [1,1,1], 2>;
+defm : C4GM7WriteRes<WriteBitTestRegLd, [C4GM7AGU, C4GM7Load, C4GM7ALU], !add(C864GM7Model.LoadLatency, 1), [1,1,1], 6>;
+defm : C4GM7WriteRes<WriteBitTestSet, [C4GM7ALU], 2, [1], 2>;
+defm : C4GM7WriteRes<WriteBitTestSetImmLd, [C4GM7AGU, C4GM7Load, C4GM7ALU], !add(C864GM7Model.LoadLatency, 2), [1, 1, 1], 4>;
+defm : C4GM7WriteRes<WriteBitTestSetRegLd, [C4GM7AGU, C4GM7Load, C4GM7ALU], !add(C864GM7Model.LoadLatency, 2), [1, 1, 1], 8>;
// Bit counts.
-defm : 4GM7WriteResIntPair<WriteBSF, [4GM7ALU], 3, [12], 6, -2>;
-defm : 4GM7WriteResIntPair<WriteBSR, [4GM7ALU], 4, [16], 6, -3>;
-defm : 4GM7WriteResIntPair<WriteLZCNT, [4GM7ALU], 1>;
-defm : 4GM7WriteResIntPair<WriteTZCNT, [4GM7ALU], 2, [2], 2>;
-defm : 4GM7WriteResIntPair<WritePOPCNT, [4GM7ALU], 1>;
+defm : C4GM7WriteResIntPair<WriteBSF, [C4GM7ALU], 3, [12], 6, -2>;
+defm : C4GM7WriteResIntPair<WriteBSR, [C4GM7ALU], 4, [16], 6, -3>;
+defm : C4GM7WriteResIntPair<WriteLZCNT, [C4GM7ALU], 1>;
+defm : C4GM7WriteResIntPair<WriteTZCNT, [C4GM7ALU], 2, [2], 2>;
+defm : C4GM7WriteResIntPair<WritePOPCNT, [C4GM7ALU], 1>;
// PLZCNT
-def 4GM7WritePLZCNTXY:SchedWriteRes<[4GM7FPU]> {
+def C4GM7WritePLZCNTXY:SchedWriteRes<[C4GM7FPU]> {
let Latency = 1;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WritePLZCNTXY], (instregex "VPLZCNT(D|Q)(Z128|Z256)rr(k|kz)")>;
+def : InstRW<[C4GM7WritePLZCNTXY], (instregex "VPLZCNT(D|Q)(Z128|Z256)rr(k|kz)")>;
-def 4GM7WritePLZCNTXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WritePLZCNTXY.Latency);
+def C4GM7WritePLZCNTXYLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WritePLZCNTXY.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WritePLZCNTXYLd], (instregex "VPLZCNT(D|Q)(Z128|Z256)rm(k|kz)")>;
+def : InstRW<[C4GM7WritePLZCNTXYLd], (instregex "VPLZCNT(D|Q)(Z128|Z256)rm(k|kz)")>;
-def 4GM7WritePLZCNTZ:SchedWriteRes<[4GM7FPU]> {
+def C4GM7WritePLZCNTZ:SchedWriteRes<[C4GM7FPU]> {
let Latency = 1;
let ReleaseAtCycles = [2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WritePLZCNTZ], (instregex "VPLZCNT(D|Q)Zrr(k|kz)")>;
+def : InstRW<[C4GM7WritePLZCNTZ], (instregex "VPLZCNT(D|Q)Zrr(k|kz)")>;
-def 4GM7WritePLZCNTZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WritePLZCNTZ.Latency);
+def C4GM7WritePLZCNTZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WritePLZCNTZ.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WritePLZCNTZLd], (instregex "VPLZCNT(D|Q)Zrm(k|kz)")>;
+def : InstRW<[C4GM7WritePLZCNTZLd], (instregex "VPLZCNT(D|Q)Zrm(k|kz)")>;
// BMI1 BEXTR, BMI2 BZHI
-defm : 4GM7WriteResIntPair<WriteBEXTR, [4GM7ALU], 1, [1], 1>;
-defm : 4GM7WriteResIntPair<WriteBLS, [4GM7ALU], 2, [2], 3>;
-defm : 4GM7WriteResIntPair<WriteBZHI, [4GM7ALU], 1>;
+defm : C4GM7WriteResIntPair<WriteBEXTR, [C4GM7ALU], 1, [1], 1>;
+defm : C4GM7WriteResIntPair<WriteBLS, [C4GM7ALU], 2, [2], 3>;
+defm : C4GM7WriteResIntPair<WriteBZHI, [C4GM7ALU], 1>;
// Floating Point Instructions
-defm : 4GM7WriteRes<WriteFLD0, [4GM7AGU, 4GM7Load, 4GM7FPU1], !add(C864GM7Model.LoadLatency, 4), [1, 1, 1], 1>;
-defm : 4GM7WriteRes<WriteFLD1, [4GM7AGU, 4GM7Load, 4GM7FPU1], !add(C864GM7Model.LoadLatency, 4), [1, 1, 1], 1>;
-defm : 4GM7WriteRes<WriteFLDC, [4GM7AGU, 4GM7Load, 4GM7FPU1], !add(C864GM7Model.LoadLatency, 4), [1, 1, 1], 1>;
-defm : 4GM7WriteRes<WriteFLoad, [4GM7AGU, 4GM7Load], !add(C864GM7Model.VecLoadLatency, 1)>;
-defm : 4GM7WriteRes<WriteFLoadX, [4GM7AGU, 4GM7Load], !add(C864GM7Model.VecLoadLatency, 1)>;
-defm : 4GM7WriteRes<WriteFLoadY, [4GM7AGU, 4GM7Load], !add(C864GM7Model.VecLoadLatency, 1)>;
-defm : 4GM7WriteRes<WriteFMaskedLoad, [4GM7AGU, 4GM7Load, 4GM7FPU01], !add(C864GM7Model.VecLoadLatency, 1)>;
-defm : 4GM7WriteRes<WriteFMaskedLoadY, [4GM7AGU, 4GM7Load, 4GM7FPU01], !add(C864GM7Model.VecLoadLatency, 1), [1, 1, 1], 2>;
-
-defm : 4GM7WriteRes<WriteFStore, [4GM7AGU, 4GM7Store], C864GM7Model.StoreLatency>;
-defm : 4GM7WriteRes<WriteFStoreX, [4GM7AGU, 4GM7Store], C864GM7Model.StoreLatency>;
-defm : 4GM7WriteRes<WriteFStoreY, [4GM7AGU, 4GM7Store], C864GM7Model.StoreLatency>;
-defm : 4GM7WriteRes<WriteFStoreNT, [4GM7FPU1, 4GM7AGU, 4GM7Store], !add(1, C864GM7Model.StoreLatency)>;
-defm : 4GM7WriteRes<WriteFStoreNTX, [4GM7FPU1, 4GM7AGU, 4GM7Store], !add(1, C864GM7Model.StoreLatency)>;
-defm : 4GM7WriteRes<WriteFStoreNTY, [4GM7FPU1, 4GM7AGU, 4GM7Store], !add(1, C864GM7Model.StoreLatency)>;
-defm : 4GM7WriteRes<WriteFMaskedStore32, [4GM7FPU01, 4GM7AGU, 4GM7Store], C864GM7Model.StoreLatency>;
-defm : 4GM7WriteRes<WriteFMaskedStore32Y, [4GM7FPU01, 4GM7AGU, 4GM7Store], C864GM7Model.StoreLatency>;
-defm : 4GM7WriteRes<WriteFMaskedStore64, [4GM7FPU01, 4GM7AGU, 4GM7Store], C864GM7Model.StoreLatency>;
-defm : 4GM7WriteRes<WriteFMaskedStore64Y, [4GM7FPU01, 4GM7AGU, 4GM7Store], C864GM7Model.StoreLatency>;
-
-defm : 4GM7WriteResFPPair<WriteFAdd, [4GM7FPU13], 3>;
-defm : 4GM7WriteResFPPair<WriteFAddX, [4GM7FPU13], 3>;
-defm : 4GM7WriteResFPPair<WriteFAddY, [4GM7FPU13], 3>;
-defm : 4GM7WriteResFPPair<WriteFAddZ, [4GM7FPU13], 3, [2], 1>;
-defm : 4GM7WriteResFPPair<WriteFAdd64, [4GM7FPU13], 3>;
-defm : 4GM7WriteResFPPair<WriteFAdd64X, [4GM7FPU13], 3>;
-defm : 4GM7WriteResFPPair<WriteFAdd64Y, [4GM7FPU13], 3>;
-defm : 4GM7WriteResFPPair<WriteFAdd64Z, [4GM7FPU13], 3, [2], 1>;
-defm : 4GM7WriteResFPPair<WriteFHAdd, [4GM7FPU13], 7, [8], 4, 3>;
-defm : 4GM7WriteResFPPair<WriteFHAddY, [4GM7FPU13], 7, [8], 4, 3>;
+defm : C4GM7WriteRes<WriteFLD0, [C4GM7AGU, C4GM7Load, C4GM7FPU1], !add(C864GM7Model.LoadLatency, 4), [1, 1, 1], 1>;
+defm : C4GM7WriteRes<WriteFLD1, [C4GM7AGU, C4GM7Load, C4GM7FPU1], !add(C864GM7Model.LoadLatency, 4), [1, 1, 1], 1>;
+defm : C4GM7WriteRes<WriteFLDC, [C4GM7AGU, C4GM7Load, C4GM7FPU1], !add(C864GM7Model.LoadLatency, 4), [1, 1, 1], 1>;
+defm : C4GM7WriteRes<WriteFLoad, [C4GM7AGU, C4GM7Load], !add(C864GM7Model.VecLoadLatency, 1)>;
+defm : C4GM7WriteRes<WriteFLoadX, [C4GM7AGU, C4GM7Load], !add(C864GM7Model.VecLoadLatency, 1)>;
+defm : C4GM7WriteRes<WriteFLoadY, [C4GM7AGU, C4GM7Load], !add(C864GM7Model.VecLoadLatency, 1)>;
+defm : C4GM7WriteRes<WriteFMaskedLoad, [C4GM7AGU, C4GM7Load, C4GM7FPU01], !add(C864GM7Model.VecLoadLatency, 1)>;
+defm : C4GM7WriteRes<WriteFMaskedLoadY, [C4GM7AGU, C4GM7Load, C4GM7FPU01], !add(C864GM7Model.VecLoadLatency, 1), [1, 1, 1], 2>;
+
+defm : C4GM7WriteRes<WriteFStore, [C4GM7AGU, C4GM7Store], C864GM7Model.StoreLatency>;
+defm : C4GM7WriteRes<WriteFStoreX, [C4GM7AGU, C4GM7Store], C864GM7Model.StoreLatency>;
+defm : C4GM7WriteRes<WriteFStoreY, [C4GM7AGU, C4GM7Store], C864GM7Model.StoreLatency>;
+defm : C4GM7WriteRes<WriteFStoreNT, [C4GM7FPU1, C4GM7AGU, C4GM7Store], !add(1, C864GM7Model.StoreLatency)>;
+defm : C4GM7WriteRes<WriteFStoreNTX, [C4GM7FPU1, C4GM7AGU, C4GM7Store], !add(1, C864GM7Model.StoreLatency)>;
+defm : C4GM7WriteRes<WriteFStoreNTY, [C4GM7FPU1, C4GM7AGU, C4GM7Store], !add(1, C864GM7Model.StoreLatency)>;
+defm : C4GM7WriteRes<WriteFMaskedStore32, [C4GM7FPU01, C4GM7AGU, C4GM7Store], C864GM7Model.StoreLatency>;
+defm : C4GM7WriteRes<WriteFMaskedStore32Y, [C4GM7FPU01, C4GM7AGU, C4GM7Store], C864GM7Model.StoreLatency>;
+defm : C4GM7WriteRes<WriteFMaskedStore64, [C4GM7FPU01, C4GM7AGU, C4GM7Store], C864GM7Model.StoreLatency>;
+defm : C4GM7WriteRes<WriteFMaskedStore64Y, [C4GM7FPU01, C4GM7AGU, C4GM7Store], C864GM7Model.StoreLatency>;
+
+defm : C4GM7WriteResFPPair<WriteFAdd, [C4GM7FPU13], 3>;
+defm : C4GM7WriteResFPPair<WriteFAddX, [C4GM7FPU13], 3>;
+defm : C4GM7WriteResFPPair<WriteFAddY, [C4GM7FPU13], 3>;
+defm : C4GM7WriteResFPPair<WriteFAddZ, [C4GM7FPU13], 3, [2], 1>;
+defm : C4GM7WriteResFPPair<WriteFAdd64, [C4GM7FPU13], 3>;
+defm : C4GM7WriteResFPPair<WriteFAdd64X, [C4GM7FPU13], 3>;
+defm : C4GM7WriteResFPPair<WriteFAdd64Y, [C4GM7FPU13], 3>;
+defm : C4GM7WriteResFPPair<WriteFAdd64Z, [C4GM7FPU13], 3, [2], 1>;
+defm : C4GM7WriteResFPPair<WriteFHAdd, [C4GM7FPU13], 7, [8], 4, 3>;
+defm : C4GM7WriteResFPPair<WriteFHAddY, [C4GM7FPU13], 7, [8], 4, 3>;
defm : X86WriteResPairUnsupported<WriteFHAddZ>;
-defm : 4GM7WriteResFPPair<WritePHAdd, [4GM7FPU13], 3, [8], 4, 3>;
-defm : 4GM7WriteResFPPair<WritePHAddX, [4GM7FPU13], 3, [8], 4, 3>;
-defm : 4GM7WriteResFPPair<WritePHAddY, [4GM7FPU13], 3, [8], 4, 3>;
+defm : C4GM7WriteResFPPair<WritePHAdd, [C4GM7FPU13], 3, [8], 4, 3>;
+defm : C4GM7WriteResFPPair<WritePHAddX, [C4GM7FPU13], 3, [8], 4, 3>;
+defm : C4GM7WriteResFPPair<WritePHAddY, [C4GM7FPU13], 3, [8], 4, 3>;
defm : X86WriteResPairUnsupported<WritePHAddZ>;
-defm : 4GM7WriteResFPPair<WriteFMul, [4GM7FPU02], 3>;
-defm : 4GM7WriteResFPPair<WriteFMulX, [4GM7FPU02], 3>;
-defm : 4GM7WriteResFPPair<WriteFMulY, [4GM7FPU02], 3>;
-defm : 4GM7WriteResFPPair<WriteFMulZ, [4GM7FPU02], 3, [2], 1>;
-defm : 4GM7WriteResFPPair<WriteFMul64, [4GM7FPU02], 3>;
-defm : 4GM7WriteResFPPair<WriteFMul64X, [4GM7FPU02], 3>;
-defm : 4GM7WriteResFPPair<WriteFMul64Y, [4GM7FPU02], 3>;
-defm : 4GM7WriteResFPPair<WriteFMul64Z, [4GM7FPU02], 3, [2], 1>;
-defm : 4GM7WriteResFPPair<WriteFMA, [4GM7FPU02], 4>;
-defm : 4GM7WriteResFPPair<WriteFMAX, [4GM7FPU02], 4>;
-defm : 4GM7WriteResFPPair<WriteFMAY, [4GM7FPU02], 4>;
-defm : 4GM7WriteResFPPair<WriteFMAZ, [4GM7FPU02], 4, [2], 2>;
-defm : 4GM7WriteResFPPair<WriteFRcp, [4GM7FPU02], 5, [2], 1>;
-defm : 4GM7WriteResFPPair<WriteFRcpX, [4GM7FPU02], 5, [2], 1>;
-defm : 4GM7WriteResFPPair<WriteFRcpY, [4GM7FPU02], 5, [2], 1>;
-defm : 4GM7WriteResFPPair<WriteFRcpZ, [4GM7FPU02], 5, [2], 1>;
-defm : 4GM7WriteResFPPair<WriteFRsqrt, [4GM7FPU02], 5, [2], 1>;
-defm : 4GM7WriteResFPPair<WriteFRsqrtX, [4GM7FPU02], 5, [2], 1>;
-defm : 4GM7WriteResFPPair<WriteFRsqrtY, [4GM7FPU02], 5, [2], 1>;
-defm : 4GM7WriteResFPPair<WriteFRsqrtZ, [4GM7FPU02], 5, [2], 1>;
-defm : 4GM7WriteResFPPair<WriteFSqrt, [4GM7FPU13], 8, [13]>;
-defm : 4GM7WriteResFPPair<WriteFSqrtX, [4GM7FPU13], 8, [13]>;
-defm : 4GM7WriteResFPPair<WriteFSqrtY, [4GM7FPU13], 8, [13]>;
-defm : 4GM7WriteResFPPair<WriteFSqrtZ, [4GM7FPU13], 16, [13]>;
-defm : 4GM7WriteResFPPair<WriteFSqrt64, [4GM7FPU13], 8, [19]>;
-defm : 4GM7WriteResFPPair<WriteFSqrt64X, [4GM7FPU13], 8, [19]>;
-defm : 4GM7WriteResFPPair<WriteFSqrt64Y, [4GM7FPU13], 8, [19]>;
-defm : 4GM7WriteResFPPair<WriteFSqrt64Z, [4GM7FPU13], 16, [19]>;
-defm : 4GM7WriteResFPPair<WriteFSqrt80, [4GM7FPU13], 22, [23]>;
-defm : 4GM7WriteResFPPair<WriteFDiv, [4GM7FPU13], 10, [9], 1>;
-defm : 4GM7WriteResFPPair<WriteFDivX, [4GM7FPU13], 10, [9], 1>;
-defm : 4GM7WriteResFPPair<WriteFDivY, [4GM7FPU13], 10, [9], 1>;
-defm : 4GM7WriteResFPPair<WriteFDivZ, [4GM7FPU13], 18, [18], 2>;
-defm : 4GM7WriteResFPPair<WriteFDiv64, [4GM7FPU13], 8, [12], 1>;
-defm : 4GM7WriteResFPPair<WriteFDiv64X, [4GM7FPU13], 8, [12], 1>;
-defm : 4GM7WriteResFPPair<WriteFDiv64Y, [4GM7FPU13], 8, [12], 1>;
-defm : 4GM7WriteResFPPair<WriteFDiv64Z, [4GM7FPU13], 16, [24], 2>;
-defm : 4GM7WriteResFPPair<WriteDPPD, [4GM7FPU13], 9, [8], 4>;
-defm : 4GM7WriteResFPPair<WriteDPPS, [4GM7FPU13], 14, [8], 8>;
-defm : 4GM7WriteResFPPair<WriteDPPSY, [4GM7FPU13], 14, [8], 8>;
+defm : C4GM7WriteResFPPair<WriteFMul, [C4GM7FPU02], 3>;
+defm : C4GM7WriteResFPPair<WriteFMulX, [C4GM7FPU02], 3>;
+defm : C4GM7WriteResFPPair<WriteFMulY, [C4GM7FPU02], 3>;
+defm : C4GM7WriteResFPPair<WriteFMulZ, [C4GM7FPU02], 3, [2], 1>;
+defm : C4GM7WriteResFPPair<WriteFMul64, [C4GM7FPU02], 3>;
+defm : C4GM7WriteResFPPair<WriteFMul64X, [C4GM7FPU02], 3>;
+defm : C4GM7WriteResFPPair<WriteFMul64Y, [C4GM7FPU02], 3>;
+defm : C4GM7WriteResFPPair<WriteFMul64Z, [C4GM7FPU02], 3, [2], 1>;
+defm : C4GM7WriteResFPPair<WriteFMA, [C4GM7FPU02], 4>;
+defm : C4GM7WriteResFPPair<WriteFMAX, [C4GM7FPU02], 4>;
+defm : C4GM7WriteResFPPair<WriteFMAY, [C4GM7FPU02], 4>;
+defm : C4GM7WriteResFPPair<WriteFMAZ, [C4GM7FPU02], 4, [2], 2>;
+defm : C4GM7WriteResFPPair<WriteFRcp, [C4GM7FPU02], 5, [2], 1>;
+defm : C4GM7WriteResFPPair<WriteFRcpX, [C4GM7FPU02], 5, [2], 1>;
+defm : C4GM7WriteResFPPair<WriteFRcpY, [C4GM7FPU02], 5, [2], 1>;
+defm : C4GM7WriteResFPPair<WriteFRcpZ, [C4GM7FPU02], 5, [2], 1>;
+defm : C4GM7WriteResFPPair<WriteFRsqrt, [C4GM7FPU02], 5, [2], 1>;
+defm : C4GM7WriteResFPPair<WriteFRsqrtX, [C4GM7FPU02], 5, [2], 1>;
+defm : C4GM7WriteResFPPair<WriteFRsqrtY, [C4GM7FPU02], 5, [2], 1>;
+defm : C4GM7WriteResFPPair<WriteFRsqrtZ, [C4GM7FPU02], 5, [2], 1>;
+defm : C4GM7WriteResFPPair<WriteFSqrt, [C4GM7FPU13], 8, [13]>;
+defm : C4GM7WriteResFPPair<WriteFSqrtX, [C4GM7FPU13], 8, [13]>;
+defm : C4GM7WriteResFPPair<WriteFSqrtY, [C4GM7FPU13], 8, [13]>;
+defm : C4GM7WriteResFPPair<WriteFSqrtZ, [C4GM7FPU13], 16, [13]>;
+defm : C4GM7WriteResFPPair<WriteFSqrt64, [C4GM7FPU13], 8, [19]>;
+defm : C4GM7WriteResFPPair<WriteFSqrt64X, [C4GM7FPU13], 8, [19]>;
+defm : C4GM7WriteResFPPair<WriteFSqrt64Y, [C4GM7FPU13], 8, [19]>;
+defm : C4GM7WriteResFPPair<WriteFSqrt64Z, [C4GM7FPU13], 16, [19]>;
+defm : C4GM7WriteResFPPair<WriteFSqrt80, [C4GM7FPU13], 22, [23]>;
+defm : C4GM7WriteResFPPair<WriteFDiv, [C4GM7FPU13], 10, [9], 1>;
+defm : C4GM7WriteResFPPair<WriteFDivX, [C4GM7FPU13], 10, [9], 1>;
+defm : C4GM7WriteResFPPair<WriteFDivY, [C4GM7FPU13], 10, [9], 1>;
+defm : C4GM7WriteResFPPair<WriteFDivZ, [C4GM7FPU13], 18, [18], 2>;
+defm : C4GM7WriteResFPPair<WriteFDiv64, [C4GM7FPU13], 8, [12], 1>;
+defm : C4GM7WriteResFPPair<WriteFDiv64X, [C4GM7FPU13], 8, [12], 1>;
+defm : C4GM7WriteResFPPair<WriteFDiv64Y, [C4GM7FPU13], 8, [12], 1>;
+defm : C4GM7WriteResFPPair<WriteFDiv64Z, [C4GM7FPU13], 16, [24], 2>;
+defm : C4GM7WriteResFPPair<WriteDPPD, [C4GM7FPU13], 9, [8], 4>;
+defm : C4GM7WriteResFPPair<WriteDPPS, [C4GM7FPU13], 14, [8], 8>;
+defm : C4GM7WriteResFPPair<WriteDPPSY, [C4GM7FPU13], 14, [8], 8>;
// PMADD
-def 4GM7WriteVPMADDXYrrk:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVPMADDXYrrk:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPMADDXYrrk], (instrs VPMADDWDZ128rrk, VPMADDWDZ256rrk)>;
+def : InstRW<[C4GM7WriteVPMADDXYrrk], (instrs VPMADDWDZ128rrk, VPMADDWDZ256rrk)>;
-def 4GM7WriteVPMADDXYrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPMADDXYrrk.Latency);
+def C4GM7WriteVPMADDXYrmk:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPMADDXYrrk.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPMADDXYrmk], (instrs VPMADDWDZ128rmk, VPMADDWDZ256rmk)>;
+def : InstRW<[C4GM7WriteVPMADDXYrmk], (instrs VPMADDWDZ128rmk, VPMADDWDZ256rmk)>;
-def 4GM7WriteVPMADDZrrk:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVPMADDZrrk:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPMADDZrrk], (instrs VPMADDWDZrrk)>;
+def : InstRW<[C4GM7WriteVPMADDZrrk], (instrs VPMADDWDZrrk)>;
-def 4GM7WriteVPMADDZrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPMADDZrrk.Latency);
+def C4GM7WriteVPMADDZrmk:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPMADDZrrk.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPMADDZrmk], (instrs VPMADDWDZrmk)>;
+def : InstRW<[C4GM7WriteVPMADDZrmk], (instrs VPMADDWDZrmk)>;
// PMADD52
-def 4GM7WriteVPMADD52XY:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVPMADD52XY:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPMADD52XY], (instregex "VPMADD52(L|H)UQ(Z128|Z256)(r|rkz)$")>;
+def : InstRW<[C4GM7WriteVPMADD52XY], (instregex "VPMADD52(L|H)UQ(Z128|Z256)(r|rkz)$")>;
-def 4GM7WriteVPMADD52XYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPMADD52XY.Latency);
+def C4GM7WriteVPMADD52XYLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPMADD52XY.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPMADD52XYLd], (instregex "VPMADD52(L|H)UQ(Z128|Z256)(m|mkz)$")>;
+def : InstRW<[C4GM7WriteVPMADD52XYLd], (instregex "VPMADD52(L|H)UQ(Z128|Z256)(m|mkz)$")>;
-def 4GM7WriteVPMADD52XYrk:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVPMADD52XYrk:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 5;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPMADD52XYrk], (instregex "VPMADD52(L|H)UQ(Z128|Z256)rk$")>;
+def : InstRW<[C4GM7WriteVPMADD52XYrk], (instregex "VPMADD52(L|H)UQ(Z128|Z256)rk$")>;
-def 4GM7WriteVPMADD52XYmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPMADD52XYrk.Latency);
+def C4GM7WriteVPMADD52XYmk:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPMADD52XYrk.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPMADD52XYmk], (instregex "VPMADD52(L|H)UQ(Z128|Z256)mk$")>;
+def : InstRW<[C4GM7WriteVPMADD52XYmk], (instregex "VPMADD52(L|H)UQ(Z128|Z256)mk$")>;
-def 4GM7WriteVPMADD52Z:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVPMADD52Z:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPMADD52Z], (instregex "VPMADD52(L|H)UQZ(r|rkz)$")>;
+def : InstRW<[C4GM7WriteVPMADD52Z], (instregex "VPMADD52(L|H)UQZ(r|rkz)$")>;
-def 4GM7WriteVPMADD52ZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPMADD52Z.Latency);
+def C4GM7WriteVPMADD52ZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPMADD52Z.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPMADD52ZLd], (instregex "VPMADD52(L|H)UQZ(m|mkz)$")>;
+def : InstRW<[C4GM7WriteVPMADD52ZLd], (instregex "VPMADD52(L|H)UQZ(m|mkz)$")>;
-def 4GM7WriteVPMADD52Zrk:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVPMADD52Zrk:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 5;
let ReleaseAtCycles = [2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPMADD52Zrk], (instregex "VPMADD52(L|H)UQZrk$")>;
+def : InstRW<[C4GM7WriteVPMADD52Zrk], (instregex "VPMADD52(L|H)UQZrk$")>;
-def 4GM7WriteVPMADD52Zmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPMADD52Zrk.Latency);
+def C4GM7WriteVPMADD52Zmk:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPMADD52Zrk.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPMADD52Zmk], (instregex "VPMADD52(L|H)UQZmk$")>;
+def : InstRW<[C4GM7WriteVPMADD52Zmk], (instregex "VPMADD52(L|H)UQZmk$")>;
// VMULZ VPMULZ
-def 4GM7WriteVMULZ_VPMULZ:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVMULZ_VPMULZ:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVMULZ_VPMULZ], (instrs VMULPSZ128rrk, VMULPDZ128rrk,
- VMULPSZ256rrk, VMULPDZ256rrk,
- VMULPSZrrbk, VMULPSZrrk,
- VMULPDZrrbk, VMULPDZrrk,
- VMULSSZrrbk_Int, VMULSSZrrk_Int,
- VMULSDZrrbk_Int, VMULSDZrrk_Int,
- VPMULDQZrrk, VPMULDQZ128rrk, VPMULDQZ256rrk,
- VPMULHRSWZrrk, VPMULHRSWZ128rrk, VPMULHRSWZ256rrk,
- VPMULHUWZrrk, VPMULHUWZ128rrk, VPMULHUWZ256rrk,
- VPMULHWZrrk, VPMULHWZ128rrk, VPMULHWZ256rrk,
- VPMULLDZrrk, VPMULLDZ128rrk, VPMULLDZ256rrk,
- VPMULLQZrr, VPMULLQZrrkz,
- VPMULLQZ128rr, VPMULLQZ128rrkz,
- VPMULLQZ256rr, VPMULLQZ256rrkz,
- VPMULLWZrrk, VPMULLWZ128rrk, VPMULLWZ256rrk,
- VPMULUDQZrrk, VPMULUDQZ128rrk, VPMULUDQZ256rrk)>;
-
-def 4GM7WriteVMULZ_VPMULZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVMULZ_VPMULZ.Latency);
+def : InstRW<[C4GM7WriteVMULZ_VPMULZ], (instrs VMULPSZ128rrk, VMULPDZ128rrk,
+ VMULPSZ256rrk, VMULPDZ256rrk,
+ VMULPSZrrbk, VMULPSZrrk,
+ VMULPDZrrbk, VMULPDZrrk,
+ VMULSSZrrbk_Int, VMULSSZrrk_Int,
+ VMULSDZrrbk_Int, VMULSDZrrk_Int,
+ VPMULDQZrrk, VPMULDQZ128rrk, VPMULDQZ256rrk,
+ VPMULHRSWZrrk, VPMULHRSWZ128rrk, VPMULHRSWZ256rrk,
+ VPMULHUWZrrk, VPMULHUWZ128rrk, VPMULHUWZ256rrk,
+ VPMULHWZrrk, VPMULHWZ128rrk, VPMULHWZ256rrk,
+ VPMULLDZrrk, VPMULLDZ128rrk, VPMULLDZ256rrk,
+ VPMULLQZrr, VPMULLQZrrkz,
+ VPMULLQZ128rr, VPMULLQZ128rrkz,
+ VPMULLQZ256rr, VPMULLQZ256rrkz,
+ VPMULLWZrrk, VPMULLWZ128rrk, VPMULLWZ256rrk,
+ VPMULUDQZrrk, VPMULUDQZ128rrk, VPMULUDQZ256rrk)>;
+
+def C4GM7WriteVMULZ_VPMULZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVMULZ_VPMULZ.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVMULZ_VPMULZLd], (instrs VMULPSZ128rmk, VMULPDZ128rmk,
- VMULPSZ256rmk, VMULPDZ256rmk,
- VMULPSZrmbk, VMULPSZrmk,
- VMULPDZrmbk, VMULPDZrmk,
- VPMULDQZrmk, VPMULDQZ128rmk, VPMULDQZ256rmk,
- VPMULHRSWZrmk, VPMULHRSWZ128rmk, VPMULHRSWZ256rmk,
- VPMULHUWZrmk, VPMULHUWZ128rmk, VPMULHUWZ256rmk,
- VPMULHWZrmk, VPMULHWZ128rmk, VPMULHWZ256rmk,
- VPMULLDZrmk, VPMULLDZ128rmk, VPMULLDZ256rmk,
- VPMULLQZrm, VPMULLQZrmkz,
- VPMULLQZ128rm, VPMULLQZ128rmkz,
- VPMULLQZ256rm, VPMULLQZ256rmkz,
- VPMULLWZrmk, VPMULLWZ128rmk, VPMULLWZ256rmk,
- VPMULUDQZrmk, VPMULUDQZ128rmk, VPMULUDQZ256rmk)>;
-
-def 4GM7WriteVPMULLQZrrk:SchedWriteRes<[4GM7FPU02]> {
+def : InstRW<[C4GM7WriteVMULZ_VPMULZLd], (instrs VMULPSZ128rmk, VMULPDZ128rmk,
+ VMULPSZ256rmk, VMULPDZ256rmk,
+ VMULPSZrmbk, VMULPSZrmk,
+ VMULPDZrmbk, VMULPDZrmk,
+ VPMULDQZrmk, VPMULDQZ128rmk, VPMULDQZ256rmk,
+ VPMULHRSWZrmk, VPMULHRSWZ128rmk, VPMULHRSWZ256rmk,
+ VPMULHUWZrmk, VPMULHUWZ128rmk, VPMULHUWZ256rmk,
+ VPMULHWZrmk, VPMULHWZ128rmk, VPMULHWZ256rmk,
+ VPMULLDZrmk, VPMULLDZ128rmk, VPMULLDZ256rmk,
+ VPMULLQZrm, VPMULLQZrmkz,
+ VPMULLQZ128rm, VPMULLQZ128rmkz,
+ VPMULLQZ256rm, VPMULLQZ256rmkz,
+ VPMULLWZrmk, VPMULLWZ128rmk, VPMULLWZ256rmk,
+ VPMULUDQZrmk, VPMULUDQZ128rmk, VPMULUDQZ256rmk)>;
+
+def C4GM7WriteVPMULLQZrrk:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 5;
let ReleaseAtCycles = [2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPMULLQZrrk], (instrs VPMULLQZrrk, VPMULLQZ128rrk, VPMULLQZ256rrk)>;
+def : InstRW<[C4GM7WriteVPMULLQZrrk], (instrs VPMULLQZrrk, VPMULLQZ128rrk, VPMULLQZ256rrk)>;
-def 4GM7WriteVPMULLQZrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPMULLQZrrk.Latency);
+def C4GM7WriteVPMULLQZrmk:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPMULLQZrrk.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPMULLQZrmk], (instrs VPMULLQZrmk, VPMULLQZ128rmk, VPMULLQZ256rmk)>;
+def : InstRW<[C4GM7WriteVPMULLQZrmk], (instrs VPMULLQZrmk, VPMULLQZ128rmk, VPMULLQZ256rmk)>;
// VPMULTISHIFTQB
-def 4GM7WriteVPMULTISHIFTQBZ:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVPMULTISHIFTQBZ:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 3;
let ReleaseAtCycles = [8];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPMULTISHIFTQBZ], (instrs VPMULTISHIFTQBZ128rr, VPMULTISHIFTQBZ128rrkz,
- VPMULTISHIFTQBZ256rr, VPMULTISHIFTQBZ256rrkz)>;
+def : InstRW<[C4GM7WriteVPMULTISHIFTQBZ], (instrs VPMULTISHIFTQBZ128rr, VPMULTISHIFTQBZ128rrkz,
+ VPMULTISHIFTQBZ256rr, VPMULTISHIFTQBZ256rrkz)>;
-def 4GM7WriteVPMULTISHIFTQBZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPMULTISHIFTQBZ.Latency);
+def C4GM7WriteVPMULTISHIFTQBZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPMULTISHIFTQBZ.Latency);
let ReleaseAtCycles = [1, 1, 8];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPMULTISHIFTQBZLd], (instrs VPMULTISHIFTQBZ128rm, VPMULTISHIFTQBZ128rmkz,
- VPMULTISHIFTQBZ256rm, VPMULTISHIFTQBZ256rmkz)>;
+def : InstRW<[C4GM7WriteVPMULTISHIFTQBZLd], (instrs VPMULTISHIFTQBZ128rm, VPMULTISHIFTQBZ128rmkz,
+ VPMULTISHIFTQBZ256rm, VPMULTISHIFTQBZ256rmkz)>;
-def 4GM7WriteVPMULTISHIFTQBZrrk:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVPMULTISHIFTQBZrrk:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [8];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPMULTISHIFTQBZrrk], (instrs VPMULTISHIFTQBZ128rrk, VPMULTISHIFTQBZ256rrk,
- VPMULTISHIFTQBZrr, VPMULTISHIFTQBZrrk, VPMULTISHIFTQBZrrkz)>;
+def : InstRW<[C4GM7WriteVPMULTISHIFTQBZrrk], (instrs VPMULTISHIFTQBZ128rrk, VPMULTISHIFTQBZ256rrk,
+ VPMULTISHIFTQBZrr, VPMULTISHIFTQBZrrk, VPMULTISHIFTQBZrrkz)>;
-def 4GM7WriteVPMULTISHIFTQBZrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPMULTISHIFTQBZrrk.Latency);
+def C4GM7WriteVPMULTISHIFTQBZrmk:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPMULTISHIFTQBZrrk.Latency);
let ReleaseAtCycles = [1, 1, 8];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPMULTISHIFTQBZrmk], (instrs VPMULTISHIFTQBZ128rmk, VPMULTISHIFTQBZ256rmk,
- VPMULTISHIFTQBZrm, VPMULTISHIFTQBZrmk, VPMULTISHIFTQBZrmkz)>;
+def : InstRW<[C4GM7WriteVPMULTISHIFTQBZrmk], (instrs VPMULTISHIFTQBZ128rmk, VPMULTISHIFTQBZ256rmk,
+ VPMULTISHIFTQBZrm, VPMULTISHIFTQBZrmk, VPMULTISHIFTQBZrmkz)>;
// VPMADDUBSWZ
-def 4GM7WriteVPMADDUBSWZrrk:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVPMADDUBSWZrrk:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPMADDUBSWZrrk], (instrs VPMADDUBSWZrrk, VPMADDUBSWZ128rrk, VPMADDUBSWZ256rrk)>;
+def : InstRW<[C4GM7WriteVPMADDUBSWZrrk], (instrs VPMADDUBSWZrrk, VPMADDUBSWZ128rrk, VPMADDUBSWZ256rrk)>;
-def 4GM7WriteVPMADDUBSWZrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPMADDUBSWZrrk.Latency);
+def C4GM7WriteVPMADDUBSWZrmk:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPMADDUBSWZrrk.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPMADDUBSWZrmk], (instrs VPMADDUBSWZrmk, VPMADDUBSWZ128rmk, VPMADDUBSWZ256rmk)>;
+def : InstRW<[C4GM7WriteVPMADDUBSWZrmk], (instrs VPMADDUBSWZrmk, VPMADDUBSWZ128rmk, VPMADDUBSWZ256rmk)>;
// FADD rrb rrbk
-def 4GM7WriteFADD:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteFADD:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteFADD], (instregex "VADD(S|P)(S|D)(Z|Z128|Z256)rr(bk|k)$",
- "VSUB(S|P)(S|D)(Z|Z128|Z256)rr(bk|k)$")>;
+def : InstRW<[C4GM7WriteFADD], (instregex "VADD(S|P)(S|D)(Z|Z128|Z256)rr(bk|k)$",
+ "VSUB(S|P)(S|D)(Z|Z128|Z256)rr(bk|k)$")>;
-def 4GM7WriteFADDLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteFADD.Latency);
+def C4GM7WriteFADDLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteFADD.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteFADDLd], (instregex "VADD(S|P)(S|D)(Z|Z128|Z256)rm(bk|k)$",
- "VSUB(S|P)(S|D)(Z|Z128|Z256)rm(bk|k)$")>;
+def : InstRW<[C4GM7WriteFADDLd], (instregex "VADD(S|P)(S|D)(Z|Z128|Z256)rm(bk|k)$",
+ "VSUB(S|P)(S|D)(Z|Z128|Z256)rm(bk|k)$")>;
// FADD rrb rrbk Int
-def 4GM7WriteFADD_Int:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteFADD_Int:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteFADD_Int], (instregex "VADD(SD|SS)Zrr(bk|k)_Int",
- "VSUB(SD|SS)Zrr(bk|k)_Int")>;
+def : InstRW<[C4GM7WriteFADD_Int], (instregex "VADD(SD|SS)Zrr(bk|k)_Int",
+ "VSUB(SD|SS)Zrr(bk|k)_Int")>;
-def 4GM7WriteFADDLd_Int:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteFADD_Int.Latency);
+def C4GM7WriteFADDLd_Int:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteFADD_Int.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteFADDLd_Int], (instregex "VADD(SD|SS)Zrm(bk|k)_Int",
- "VSUB(SD|SS)Zrm(bk|k)_Int")>;
+def : InstRW<[C4GM7WriteFADDLd_Int], (instregex "VADD(SD|SS)Zrm(bk|k)_Int",
+ "VSUB(SD|SS)Zrm(bk|k)_Int")>;
// RCP14
-def 4GM7WriteVRCP14:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVRCP14:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVRCP14], (instrs VRCP14SSZrr, VRCP14SSZrrk, VRCP14SSZrrkz,
- VRCP14SDZrr, VRCP14SDZrrk, VRCP14SDZrrkz)>;
+def : InstRW<[C4GM7WriteVRCP14], (instrs VRCP14SSZrr, VRCP14SSZrrk, VRCP14SSZrrkz,
+ VRCP14SDZrr, VRCP14SDZrrk, VRCP14SDZrrkz)>;
-def 4GM7WriteVRCP14Ld:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVRCP14.Latency);
+def C4GM7WriteVRCP14Ld:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVRCP14.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVRCP14Ld], (instrs VRCP14SDZrm, VRCP14SDZrmk, VRCP14SDZrmkz,
- VRCP14SSZrm, VRCP14SSZrmk, VRCP14SSZrmkz)>;
+def : InstRW<[C4GM7WriteVRCP14Ld], (instrs VRCP14SDZrm, VRCP14SDZrmk, VRCP14SDZrmkz,
+ VRCP14SSZrm, VRCP14SSZrmk, VRCP14SSZrmkz)>;
-def 4GM7WriteVRCP14X:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVRCP14X:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVRCP14X], (instrs VRCP14PSZ128r, VRCP14PSZ128rk, VRCP14PSZ128rkz,
- VRCP14PDZ128r, VRCP14PDZ128rk, VRCP14PDZ128rkz)>;
+def : InstRW<[C4GM7WriteVRCP14X], (instrs VRCP14PSZ128r, VRCP14PSZ128rk, VRCP14PSZ128rkz,
+ VRCP14PDZ128r, VRCP14PDZ128rk, VRCP14PDZ128rkz)>;
-def 4GM7WriteVRCP14XLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVRCP14X.Latency);
+def C4GM7WriteVRCP14XLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVRCP14X.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVRCP14XLd], (instrs VRCP14PDZ128m, VRCP14PDZ128mb, VRCP14PDZ128mbk,
- VRCP14PDZ128mbkz, VRCP14PDZ128mk, VRCP14PDZ128mkz,
- VRCP14PSZ128m, VRCP14PSZ128mb, VRCP14PSZ128mbk,
- VRCP14PSZ128mbkz, VRCP14PSZ128mk, VRCP14PSZ128mkz)>;
+def : InstRW<[C4GM7WriteVRCP14XLd], (instrs VRCP14PDZ128m, VRCP14PDZ128mb, VRCP14PDZ128mbk,
+ VRCP14PDZ128mbkz, VRCP14PDZ128mk, VRCP14PDZ128mkz,
+ VRCP14PSZ128m, VRCP14PSZ128mb, VRCP14PSZ128mbk,
+ VRCP14PSZ128mbkz, VRCP14PSZ128mk, VRCP14PSZ128mkz)>;
-def 4GM7WriteVRCP14Y:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVRCP14Y:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVRCP14Y], (instrs VRCP14PSZ256r, VRCP14PSZ256rk, VRCP14PSZ256rkz,
- VRCP14PDZ256r, VRCP14PDZ256rk, VRCP14PDZ256rkz)>;
+def : InstRW<[C4GM7WriteVRCP14Y], (instrs VRCP14PSZ256r, VRCP14PSZ256rk, VRCP14PSZ256rkz,
+ VRCP14PDZ256r, VRCP14PDZ256rk, VRCP14PDZ256rkz)>;
-def 4GM7WriteVRCP14YLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVRCP14Y.Latency);
+def C4GM7WriteVRCP14YLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVRCP14Y.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVRCP14YLd], (instrs VRCP14PDZ256m, VRCP14PDZ256mb, VRCP14PDZ256mbk,
- VRCP14PDZ256mbkz, VRCP14PDZ256mk, VRCP14PDZ256mkz,
- VRCP14PSZ256m, VRCP14PSZ256mb, VRCP14PSZ256mbk,
- VRCP14PSZ256mbkz, VRCP14PSZ256mk, VRCP14PSZ256mkz)>;
+def : InstRW<[C4GM7WriteVRCP14YLd], (instrs VRCP14PDZ256m, VRCP14PDZ256mb, VRCP14PDZ256mbk,
+ VRCP14PDZ256mbkz, VRCP14PDZ256mk, VRCP14PDZ256mkz,
+ VRCP14PSZ256m, VRCP14PSZ256mb, VRCP14PSZ256mbk,
+ VRCP14PSZ256mbkz, VRCP14PSZ256mk, VRCP14PSZ256mkz)>;
-def 4GM7WriteVRCP14Z:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVRCP14Z:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVRCP14Z], (instrs VRCP14PDZr, VRCP14PDZrk, VRCP14PDZrkz,
- VRCP14PSZr, VRCP14PSZrk, VRCP14PSZrkz)>;
+def : InstRW<[C4GM7WriteVRCP14Z], (instrs VRCP14PDZr, VRCP14PDZrk, VRCP14PDZrkz,
+ VRCP14PSZr, VRCP14PSZrk, VRCP14PSZrkz)>;
-def 4GM7WriteVRCP14ZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVRCP14Z.Latency);
+def C4GM7WriteVRCP14ZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVRCP14Z.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVRCP14ZLd], (instrs VRCP14PDZm, VRCP14PDZmb, VRCP14PDZmbk,
- VRCP14PDZmbkz, VRCP14PDZmk, VRCP14PDZmkz,
- VRCP14PSZm, VRCP14PSZmb, VRCP14PSZmbk,
- VRCP14PSZmbkz, VRCP14PSZmk, VRCP14PSZmkz)>;
+def : InstRW<[C4GM7WriteVRCP14ZLd], (instrs VRCP14PDZm, VRCP14PDZmb, VRCP14PDZmbk,
+ VRCP14PDZmbkz, VRCP14PDZmk, VRCP14PDZmkz,
+ VRCP14PSZm, VRCP14PSZmb, VRCP14PSZmbk,
+ VRCP14PSZmbkz, VRCP14PSZmk, VRCP14PSZmkz)>;
// RSQRT14
-def 4GM7WriteRSQRT14:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteRSQRT14:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteRSQRT14], (instrs VRSQRT14SDZrr, VRSQRT14SDZrrk, VRSQRT14SDZrrkz,
- VRSQRT14SSZrr, VRSQRT14SSZrrk, VRSQRT14SSZrrkz)>;
+def : InstRW<[C4GM7WriteRSQRT14], (instrs VRSQRT14SDZrr, VRSQRT14SDZrrk, VRSQRT14SDZrrkz,
+ VRSQRT14SSZrr, VRSQRT14SSZrrk, VRSQRT14SSZrrkz)>;
-def 4GM7WriteRSQRT14Ld:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteRSQRT14.Latency);
+def C4GM7WriteRSQRT14Ld:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteRSQRT14.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteRSQRT14Ld], (instrs VRSQRT14SDZrm, VRSQRT14SDZrmk, VRSQRT14SDZrmkz,
- VRSQRT14SSZrm, VRSQRT14SSZrmk, VRSQRT14SSZrmkz)>;
+def : InstRW<[C4GM7WriteRSQRT14Ld], (instrs VRSQRT14SDZrm, VRSQRT14SDZrmk, VRSQRT14SDZrmkz,
+ VRSQRT14SSZrm, VRSQRT14SSZrmk, VRSQRT14SSZrmkz)>;
-def 4GM7WriteRSQRT14X:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteRSQRT14X:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteRSQRT14X], (instrs VRSQRT14PDZ128r, VRSQRT14PDZ128rk, VRSQRT14PDZ128rkz,
- VRSQRT14PSZ128r, VRSQRT14PSZ128rk, VRSQRT14PSZ128rkz)>;
+def : InstRW<[C4GM7WriteRSQRT14X], (instrs VRSQRT14PDZ128r, VRSQRT14PDZ128rk, VRSQRT14PDZ128rkz,
+ VRSQRT14PSZ128r, VRSQRT14PSZ128rk, VRSQRT14PSZ128rkz)>;
-def 4GM7WriteRSQRT14XLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteRSQRT14X.Latency);
+def C4GM7WriteRSQRT14XLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteRSQRT14X.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteRSQRT14XLd], (instrs VRSQRT14PDZ128m, VRSQRT14PDZ128mb, VRSQRT14PDZ128mbk,
- VRSQRT14PDZ128mbkz, VRSQRT14PDZ128mk, VRSQRT14PDZ128mkz,
- VRSQRT14PSZ128m, VRSQRT14PSZ128mb, VRSQRT14PSZ128mbk,
- VRSQRT14PSZ128mbkz, VRSQRT14PSZ128mk, VRSQRT14PSZ128mkz)>;
+def : InstRW<[C4GM7WriteRSQRT14XLd], (instrs VRSQRT14PDZ128m, VRSQRT14PDZ128mb, VRSQRT14PDZ128mbk,
+ VRSQRT14PDZ128mbkz, VRSQRT14PDZ128mk, VRSQRT14PDZ128mkz,
+ VRSQRT14PSZ128m, VRSQRT14PSZ128mb, VRSQRT14PSZ128mbk,
+ VRSQRT14PSZ128mbkz, VRSQRT14PSZ128mk, VRSQRT14PSZ128mkz)>;
-def 4GM7WriteRSQRT14Y:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteRSQRT14Y:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteRSQRT14Y], (instrs VRSQRT14PDZ256r, VRSQRT14PDZ256rk, VRSQRT14PDZ256rkz,
- VRSQRT14PSZ256r, VRSQRT14PSZ256rk, VRSQRT14PSZ256rkz)>;
+def : InstRW<[C4GM7WriteRSQRT14Y], (instrs VRSQRT14PDZ256r, VRSQRT14PDZ256rk, VRSQRT14PDZ256rkz,
+ VRSQRT14PSZ256r, VRSQRT14PSZ256rk, VRSQRT14PSZ256rkz)>;
-def 4GM7WriteRSQRT14YLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteRSQRT14Y.Latency);
+def C4GM7WriteRSQRT14YLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteRSQRT14Y.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteRSQRT14YLd], (instrs VRSQRT14PDZ256m, VRSQRT14PDZ256mb, VRSQRT14PDZ256mbk,
- VRSQRT14PDZ256mbkz, VRSQRT14PDZ256mk, VRSQRT14PDZ256mkz,
- VRSQRT14PSZ256m, VRSQRT14PSZ256mb, VRSQRT14PSZ256mbk,
- VRSQRT14PSZ256mbkz, VRSQRT14PSZ256mk, VRSQRT14PSZ256mkz)>;
+def : InstRW<[C4GM7WriteRSQRT14YLd], (instrs VRSQRT14PDZ256m, VRSQRT14PDZ256mb, VRSQRT14PDZ256mbk,
+ VRSQRT14PDZ256mbkz, VRSQRT14PDZ256mk, VRSQRT14PDZ256mkz,
+ VRSQRT14PSZ256m, VRSQRT14PSZ256mb, VRSQRT14PSZ256mbk,
+ VRSQRT14PSZ256mbkz, VRSQRT14PSZ256mk, VRSQRT14PSZ256mkz)>;
-def 4GM7WriteRSQRT14Z:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteRSQRT14Z:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteRSQRT14Z], (instrs VRSQRT14PDZr, VRSQRT14PDZrk, VRSQRT14PDZrkz,
- VRSQRT14PSZr, VRSQRT14PSZrk, VRSQRT14PSZrkz)>;
+def : InstRW<[C4GM7WriteRSQRT14Z], (instrs VRSQRT14PDZr, VRSQRT14PDZrk, VRSQRT14PDZrkz,
+ VRSQRT14PSZr, VRSQRT14PSZrk, VRSQRT14PSZrkz)>;
-def 4GM7WriteRSQRT14ZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteRSQRT14Z.Latency);
+def C4GM7WriteRSQRT14ZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteRSQRT14Z.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteRSQRT14ZLd], (instrs VRSQRT14PDZm, VRSQRT14PDZmb, VRSQRT14PDZmbk,
- VRSQRT14PDZmbkz, VRSQRT14PDZmk, VRSQRT14PDZmkz,
- VRSQRT14PSZm, VRSQRT14PSZmb, VRSQRT14PSZmbk,
- VRSQRT14PSZmbkz, VRSQRT14PSZmk, VRSQRT14PSZmkz)>;
-
-defm : 4GM7WriteResFPPair<WriteFCmp, [4GM7FPU02], 1>;
-defm : 4GM7WriteResFPPair<WriteFCmpX, [4GM7FPU02], 1>;
-defm : 4GM7WriteResFPPair<WriteFCmpY, [4GM7FPU02], 1>;
-defm : 4GM7WriteResFPPair<WriteFCmpZ, [4GM7FPU02], 1>;
-defm : 4GM7WriteResFPPair<WriteFCmp64, [4GM7FPU02], 1>;
-defm : 4GM7WriteResFPPair<WriteFCmp64X, [4GM7FPU02], 1>;
-defm : 4GM7WriteResFPPair<WriteFCmp64Y, [4GM7FPU02], 1>;
-defm : 4GM7WriteResFPPair<WriteFCmp64Z, [4GM7FPU02], 1>;
-defm : 4GM7WriteResFPPair<WriteFCom, [4GM7FPU02], 1>;
-defm : 4GM7WriteResFPPair<WriteFComX, [4GM7FPU], 1, [2], 2>;
-defm : 4GM7WriteResFPPair<WriteFBlend, [4GM7FPU], 1>;
-defm : 4GM7WriteResFPPair<WriteFBlendY, [4GM7FPU], 1>;
-defm : 4GM7WriteResFPPair<WriteFBlendZ, [4GM7FPU], 1>;
-defm : 4GM7WriteResFPPair<WriteFVarBlend, [4GM7FPU], 1>;
-defm : 4GM7WriteResFPPair<WriteFVarBlendY, [4GM7FPU], 1>;
-defm : 4GM7WriteResFPPair<WriteFVarBlendZ, [4GM7FPU], 1>;
-
-def 4GM7WriteFCOMI_FCOMIP:SchedWriteRes<[4GM7FPU02, 4GM7FPU13]> {
+def : InstRW<[C4GM7WriteRSQRT14ZLd], (instrs VRSQRT14PDZm, VRSQRT14PDZmb, VRSQRT14PDZmbk,
+ VRSQRT14PDZmbkz, VRSQRT14PDZmk, VRSQRT14PDZmkz,
+ VRSQRT14PSZm, VRSQRT14PSZmb, VRSQRT14PSZmbk,
+ VRSQRT14PSZmbkz, VRSQRT14PSZmk, VRSQRT14PSZmkz)>;
+
+defm : C4GM7WriteResFPPair<WriteFCmp, [C4GM7FPU02], 1>;
+defm : C4GM7WriteResFPPair<WriteFCmpX, [C4GM7FPU02], 1>;
+defm : C4GM7WriteResFPPair<WriteFCmpY, [C4GM7FPU02], 1>;
+defm : C4GM7WriteResFPPair<WriteFCmpZ, [C4GM7FPU02], 1>;
+defm : C4GM7WriteResFPPair<WriteFCmp64, [C4GM7FPU02], 1>;
+defm : C4GM7WriteResFPPair<WriteFCmp64X, [C4GM7FPU02], 1>;
+defm : C4GM7WriteResFPPair<WriteFCmp64Y, [C4GM7FPU02], 1>;
+defm : C4GM7WriteResFPPair<WriteFCmp64Z, [C4GM7FPU02], 1>;
+defm : C4GM7WriteResFPPair<WriteFCom, [C4GM7FPU02], 1>;
+defm : C4GM7WriteResFPPair<WriteFComX, [C4GM7FPU], 1, [2], 2>;
+defm : C4GM7WriteResFPPair<WriteFBlend, [C4GM7FPU], 1>;
+defm : C4GM7WriteResFPPair<WriteFBlendY, [C4GM7FPU], 1>;
+defm : C4GM7WriteResFPPair<WriteFBlendZ, [C4GM7FPU], 1>;
+defm : C4GM7WriteResFPPair<WriteFVarBlend, [C4GM7FPU], 1>;
+defm : C4GM7WriteResFPPair<WriteFVarBlendY, [C4GM7FPU], 1>;
+defm : C4GM7WriteResFPPair<WriteFVarBlendZ, [C4GM7FPU], 1>;
+
+def C4GM7WriteFCOMI_FCOMIP:SchedWriteRes<[C4GM7FPU02, C4GM7FPU13]> {
let Latency = 2;
let ReleaseAtCycles = [1, 1];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteFCOMI_FCOMIP], (instrs COM_FIPr, COM_FIr)>;
+def : InstRW<[C4GM7WriteFCOMI_FCOMIP], (instrs COM_FIPr, COM_FIr)>;
// VMAX VMIN
-def 4GM7WriteVMAXXY_VMINXY:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVMAXXY_VMINXY:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 2;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVMAXXY_VMINXY], (instrs VMAXPSZ128rrk, VMAXPDZ128rrk,
- VMINPSZ128rrk, VMINPDZ128rrk,
- VMAXCPSZ128rrk, VMAXCPDZ128rrk,
- VMINCPSZ128rrk, VMINCPDZ128rrk,
- VMAXPSZ256rrk, VMAXPDZ256rrk,
- VMINPSZ256rrk, VMINPDZ256rrk,
- VMAXCPSZ256rrk, VMAXCPDZ256rrk,
- VMINCPSZ256rrk, VMINCPDZ256rrk)>;
+def : InstRW<[C4GM7WriteVMAXXY_VMINXY], (instrs VMAXPSZ128rrk, VMAXPDZ128rrk,
+ VMINPSZ128rrk, VMINPDZ128rrk,
+ VMAXCPSZ128rrk, VMAXCPDZ128rrk,
+ VMINCPSZ128rrk, VMINCPDZ128rrk,
+ VMAXPSZ256rrk, VMAXPDZ256rrk,
+ VMINPSZ256rrk, VMINPDZ256rrk,
+ VMAXCPSZ256rrk, VMAXCPDZ256rrk,
+ VMINCPSZ256rrk, VMINCPDZ256rrk)>;
-def 4GM7WriteVMAXXY_VMINXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVMAXXY_VMINXY.Latency);
+def C4GM7WriteVMAXXY_VMINXYLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVMAXXY_VMINXY.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVMAXXY_VMINXYLd], (instrs VMAXPSZ128rmk, VMAXPDZ128rmk,
- VMINPSZ128rmk, VMINPDZ128rmk,
- VMAXCPSZ128rmk, VMAXCPDZ128rmk,
- VMINCPSZ128rmk, VMINCPDZ128rmk,
- VMAXPSZ256rmk, VMAXPDZ256rmk,
- VMINPSZ256rmk, VMINPDZ256rmk,
- VMAXCPSZ256rmk, VMAXCPDZ256rmk,
- VMINCPSZ256rmk, VMINCPDZ256rmk)>;
+def : InstRW<[C4GM7WriteVMAXXY_VMINXYLd], (instrs VMAXPSZ128rmk, VMAXPDZ128rmk,
+ VMINPSZ128rmk, VMINPDZ128rmk,
+ VMAXCPSZ128rmk, VMAXCPDZ128rmk,
+ VMINCPSZ128rmk, VMINCPDZ128rmk,
+ VMAXPSZ256rmk, VMAXPDZ256rmk,
+ VMINPSZ256rmk, VMINPDZ256rmk,
+ VMAXCPSZ256rmk, VMAXCPDZ256rmk,
+ VMINCPSZ256rmk, VMINCPDZ256rmk)>;
-def 4GM7WriteVMAXZ_VMINZ:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVMAXZ_VMINZ:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVMAXZ_VMINZ], (instrs VMAXPSZrrk, VMAXPSZrrbk,
- VMAXPDZrrk, VMAXPDZrrbk,
- VMINPSZrrk, VMINPSZrrbk,
- VMINPDZrrk, VMINPDZrrbk,
- VMAXCPSZrrk, VMAXCPDZrrk,
- VMINCPSZrrk, VMINCPDZrrk,
- VMAXSSZrrk_Int, VMAXSSZrrbk_Int,
- VMAXSDZrrk_Int, VMAXSDZrrbk_Int,
- VMINSSZrrk_Int, VMINSSZrrbk_Int,
- VMINSDZrrk_Int, VMINSDZrrbk_Int)>;
+def : InstRW<[C4GM7WriteVMAXZ_VMINZ], (instrs VMAXPSZrrk, VMAXPSZrrbk,
+ VMAXPDZrrk, VMAXPDZrrbk,
+ VMINPSZrrk, VMINPSZrrbk,
+ VMINPDZrrk, VMINPDZrrbk,
+ VMAXCPSZrrk, VMAXCPDZrrk,
+ VMINCPSZrrk, VMINCPDZrrk,
+ VMAXSSZrrk_Int, VMAXSSZrrbk_Int,
+ VMAXSDZrrk_Int, VMAXSDZrrbk_Int,
+ VMINSSZrrk_Int, VMINSSZrrbk_Int,
+ VMINSDZrrk_Int, VMINSDZrrbk_Int)>;
-def 4GM7WriteVMAXZ_VMINZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVMAXZ_VMINZ.Latency);
+def C4GM7WriteVMAXZ_VMINZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVMAXZ_VMINZ.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVMAXZ_VMINZLd], (instrs VMAXPSZrmk, VMAXPSZrmbk,
- VMAXPDZrmk, VMAXPDZrmbk,
- VMINPSZrmk, VMINPSZrmbk,
- VMINPDZrmk, VMINPDZrmbk,
- VMAXCPSZrmk, VMAXCPDZrmk,
- VMINCPSZrmk, VMINCPDZrmk,
- VMAXSSZrmk_Int, VMAXSDZrmk_Int,
- VMINSSZrmk_Int, VMINSDZrmk_Int)>;
+def : InstRW<[C4GM7WriteVMAXZ_VMINZLd], (instrs VMAXPSZrmk, VMAXPSZrmbk,
+ VMAXPDZrmk, VMAXPDZrmbk,
+ VMINPSZrmk, VMINPSZrmbk,
+ VMINPDZrmk, VMINPDZrmbk,
+ VMAXCPSZrmk, VMAXCPDZrmk,
+ VMINCPSZrmk, VMINCPDZrmk,
+ VMAXSSZrmk_Int, VMAXSDZrmk_Int,
+ VMINSSZrmk_Int, VMINSDZrmk_Int)>;
// VBLEND
-def 4GM7WriteVBLENDrrk:SchedWriteRes<[4GM7FPU]> {
+def C4GM7WriteVBLENDrrk:SchedWriteRes<[C4GM7FPU]> {
let Latency = 2;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVBLENDrrk], (instregex "VPBLENDM(B|D|W|Q)Z(128|256)?rrk$",
- "VBLENDM(PS|PD)Zrrk$")>;
+def : InstRW<[C4GM7WriteVBLENDrrk], (instregex "VPBLENDM(B|D|W|Q)Z(128|256)?rrk$",
+ "VBLENDM(PS|PD)Zrrk$")>;
-def 4GM7WriteVBLENDrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVBLENDrrk.Latency);
+def C4GM7WriteVBLENDrmk:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVBLENDrrk.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVBLENDrmk], (instregex "VPBLENDM(B|D|W|Q)Z(128|256)?rmk$",
- "VBLENDM(PS|PD)Zrmk$")>;
-
-defm : 4GM7WriteResFPPair<WriteCvtSS2I, [4GM7FPU13], 2, [2], 2>;
-defm : 4GM7WriteResFPPair<WriteCvtPS2I, [4GM7FPU13], 4, [1], 1>;
-defm : 4GM7WriteResFPPair<WriteCvtPS2IY, [4GM7FPU13], 4, [1], 1>;
-defm : 4GM7WriteResFPPair<WriteCvtPS2IZ, [4GM7FPU13], 4, [2], 2>;
-defm : 4GM7WriteResFPPair<WriteCvtSD2I, [4GM7FPU13], 2, [2], 2>;
-defm : 4GM7WriteResFPPair<WriteCvtPD2I, [4GM7FPU13], 4, [1], 1>;
-defm : 4GM7WriteResFPPair<WriteCvtPD2IY, [4GM7FPU13], 4, [1], 1>;
-defm : 4GM7WriteResFPPair<WriteCvtPD2IZ, [4GM7FPU13], 8, [2], 2>;
-defm : 4GM7WriteResFPPair<WriteCvtSS2SD, [4GM7FPU13], 4, [1], 1>;
-defm : 4GM7WriteResFPPair<WriteCvtPS2PD, [4GM7FPU13], 4, [1], 1>;
-defm : 4GM7WriteResFPPair<WriteCvtPS2PDY, [4GM7FPU13], 4, [1], 1>;
-defm : 4GM7WriteResFPPair<WriteCvtPS2PDZ, [4GM7FPU13], 5, [2], 2>;
-defm : 4GM7WriteResFPPair<WriteCvtSD2SS, [4GM7FPU13], 4, [1], 1>;
-defm : 4GM7WriteResFPPair<WriteCvtPD2PS, [4GM7FPU13], 4, [1], 1>;
-defm : 4GM7WriteResFPPair<WriteCvtPD2PSY, [4GM7FPU13], 4, [1], 1>;
-defm : 4GM7WriteResFPPair<WriteCvtPD2PSZ, [4GM7FPU13], 8, [2], 2>;
-defm : 4GM7WriteResFPPair<WriteCvtI2SS, [4GM7FPU13], 4, [3], 2>;
-defm : 4GM7WriteResFPPair<WriteCvtI2PS, [4GM7FPU13], 4>;
-defm : 4GM7WriteResFPPair<WriteCvtI2PSY, [4GM7FPU13], 4>;
-defm : 4GM7WriteResFPPair<WriteCvtI2PSZ, [4GM7FPU13], 4, [2], 2>;
-defm : 4GM7WriteResFPPair<WriteCvtI2SD, [4GM7FPU13], 4, [3], 2>;
-defm : 4GM7WriteResFPPair<WriteCvtI2PD, [4GM7FPU13], 4>;
-defm : 4GM7WriteResFPPair<WriteCvtI2PDY, [4GM7FPU13], 4>;
-defm : 4GM7WriteResFPPair<WriteCvtI2PDZ, [4GM7FPU13], 5, [2], 2>;
-defm : 4GM7WriteResFPPair<WriteCvtPH2PS, [4GM7FPU13], 4, [1], 1>;
-defm : 4GM7WriteResFPPair<WriteCvtPH2PSY, [4GM7FPU13], 4, [1], 1>;
-defm : 4GM7WriteResFPPair<WriteCvtPH2PSZ, [4GM7FPU13], 5, [2], 2>;
-defm : 4GM7WriteRes<WriteCvtPS2PH, [4GM7FPU13], 4, [1], 1>;
-defm : 4GM7WriteRes<WriteCvtPS2PHY, [4GM7FPU13], 4, [1], 1>;
-defm : 4GM7WriteRes<WriteCvtPS2PHZ, [4GM7FPU13], 8, [2], 2>;
-defm : 4GM7WriteRes<WriteCvtPS2PHSt, [4GM7FPU13, 4GM7AGU, 4GM7Store], !add(4, C864GM7Model.StoreLatency), [1, 1, 1], 2>;
-defm : 4GM7WriteRes<WriteCvtPS2PHYSt, [4GM7FPU13, 4GM7AGU, 4GM7Store], !add(4, C864GM7Model.StoreLatency), [1, 1, 1], 2>;
-defm : 4GM7WriteRes<WriteCvtPS2PHZSt, [4GM7FPU13, 4GM7AGU, 4GM7Store], !add(8, C864GM7Model.StoreLatency), [2, 1, 1], 3>;
+def : InstRW<[C4GM7WriteVBLENDrmk], (instregex "VPBLENDM(B|D|W|Q)Z(128|256)?rmk$",
+ "VBLENDM(PS|PD)Zrmk$")>;
+
+defm : C4GM7WriteResFPPair<WriteCvtSS2I, [C4GM7FPU13], 2, [2], 2>;
+defm : C4GM7WriteResFPPair<WriteCvtPS2I, [C4GM7FPU13], 4, [1], 1>;
+defm : C4GM7WriteResFPPair<WriteCvtPS2IY, [C4GM7FPU13], 4, [1], 1>;
+defm : C4GM7WriteResFPPair<WriteCvtPS2IZ, [C4GM7FPU13], 4, [2], 2>;
+defm : C4GM7WriteResFPPair<WriteCvtSD2I, [C4GM7FPU13], 2, [2], 2>;
+defm : C4GM7WriteResFPPair<WriteCvtPD2I, [C4GM7FPU13], 4, [1], 1>;
+defm : C4GM7WriteResFPPair<WriteCvtPD2IY, [C4GM7FPU13], 4, [1], 1>;
+defm : C4GM7WriteResFPPair<WriteCvtPD2IZ, [C4GM7FPU13], 8, [2], 2>;
+defm : C4GM7WriteResFPPair<WriteCvtSS2SD, [C4GM7FPU13], 4, [1], 1>;
+defm : C4GM7WriteResFPPair<WriteCvtPS2PD, [C4GM7FPU13], 4, [1], 1>;
+defm : C4GM7WriteResFPPair<WriteCvtPS2PDY, [C4GM7FPU13], 4, [1], 1>;
+defm : C4GM7WriteResFPPair<WriteCvtPS2PDZ, [C4GM7FPU13], 5, [2], 2>;
+defm : C4GM7WriteResFPPair<WriteCvtSD2SS, [C4GM7FPU13], 4, [1], 1>;
+defm : C4GM7WriteResFPPair<WriteCvtPD2PS, [C4GM7FPU13], 4, [1], 1>;
+defm : C4GM7WriteResFPPair<WriteCvtPD2PSY, [C4GM7FPU13], 4, [1], 1>;
+defm : C4GM7WriteResFPPair<WriteCvtPD2PSZ, [C4GM7FPU13], 8, [2], 2>;
+defm : C4GM7WriteResFPPair<WriteCvtI2SS, [C4GM7FPU13], 4, [3], 2>;
+defm : C4GM7WriteResFPPair<WriteCvtI2PS, [C4GM7FPU13], 4>;
+defm : C4GM7WriteResFPPair<WriteCvtI2PSY, [C4GM7FPU13], 4>;
+defm : C4GM7WriteResFPPair<WriteCvtI2PSZ, [C4GM7FPU13], 4, [2], 2>;
+defm : C4GM7WriteResFPPair<WriteCvtI2SD, [C4GM7FPU13], 4, [3], 2>;
+defm : C4GM7WriteResFPPair<WriteCvtI2PD, [C4GM7FPU13], 4>;
+defm : C4GM7WriteResFPPair<WriteCvtI2PDY, [C4GM7FPU13], 4>;
+defm : C4GM7WriteResFPPair<WriteCvtI2PDZ, [C4GM7FPU13], 5, [2], 2>;
+defm : C4GM7WriteResFPPair<WriteCvtPH2PS, [C4GM7FPU13], 4, [1], 1>;
+defm : C4GM7WriteResFPPair<WriteCvtPH2PSY, [C4GM7FPU13], 4, [1], 1>;
+defm : C4GM7WriteResFPPair<WriteCvtPH2PSZ, [C4GM7FPU13], 5, [2], 2>;
+defm : C4GM7WriteRes<WriteCvtPS2PH, [C4GM7FPU13], 4, [1], 1>;
+defm : C4GM7WriteRes<WriteCvtPS2PHY, [C4GM7FPU13], 4, [1], 1>;
+defm : C4GM7WriteRes<WriteCvtPS2PHZ, [C4GM7FPU13], 8, [2], 2>;
+defm : C4GM7WriteRes<WriteCvtPS2PHSt, [C4GM7FPU13, C4GM7AGU, C4GM7Store], !add(4, C864GM7Model.StoreLatency), [1, 1, 1], 2>;
+defm : C4GM7WriteRes<WriteCvtPS2PHYSt, [C4GM7FPU13, C4GM7AGU, C4GM7Store], !add(4, C864GM7Model.StoreLatency), [1, 1, 1], 2>;
+defm : C4GM7WriteRes<WriteCvtPS2PHZSt, [C4GM7FPU13, C4GM7AGU, C4GM7Store], !add(8, C864GM7Model.StoreLatency), [2, 1, 1], 3>;
// CVTPD2QQ
-def 4GM7WritePD2QQ:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WritePD2QQ:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 4;
let ReleaseAtCycles = [2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WritePD2QQ], (instregex "VCVT(T?)PD2(U?)QQ(Z|Z128|Z256)(rr$|rrkz)")>;
+def : InstRW<[C4GM7WritePD2QQ], (instregex "VCVT(T?)PD2(U?)QQ(Z|Z128|Z256)(rr$|rrkz)")>;
-def 4GM7WritePD2QQLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WritePD2QQ.Latency);
+def C4GM7WritePD2QQLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WritePD2QQ.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WritePD2QQLd], (instregex "VCVT(T?)PD2(U?)QQ(Z|Z128|Z256)(rm$|rmkz)")>;
+def : InstRW<[C4GM7WritePD2QQLd], (instregex "VCVT(T?)PD2(U?)QQ(Z|Z128|Z256)(rm$|rmkz)")>;
// CVTSI2SS
-def 4GM7WriteSI2SSrr:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteSI2SSrr:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 4;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteSI2SSrr], (instregex "VCVT(U?)SI2SS(Z?)rr")>;
+def : InstRW<[C4GM7WriteSI2SSrr], (instregex "VCVT(U?)SI2SS(Z?)rr")>;
-def 4GM7WriteSI2SSrm:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteSI2SSrr.Latency);
+def C4GM7WriteSI2SSrm:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteSI2SSrr.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteSI2SSrm], (instregex "VCVT(U?)SI2SS(Z?)rm")>;
+def : InstRW<[C4GM7WriteSI2SSrm], (instregex "VCVT(U?)SI2SS(Z?)rm")>;
// SI2SD
-def 4GM7WriteSI2SD:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteSI2SD:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 4;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteSI2SD], (instregex "VCVT(U?)SI2SD(Z?)rr")>;
+def : InstRW<[C4GM7WriteSI2SD], (instregex "VCVT(U?)SI2SD(Z?)rr")>;
-def 4GM7WriteSI2SDLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteSI2SD.Latency);
+def C4GM7WriteSI2SDLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteSI2SD.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteSI2SDLd], (instregex "VCVT(U?)SI2SD(Z?)rm")>;
+def : InstRW<[C4GM7WriteSI2SDLd], (instregex "VCVT(U?)SI2SD(Z?)rm")>;
// CVT BF16
-def 4GM7WriteCVTBF16:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteCVTBF16:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 4;
let ReleaseAtCycles = [6];
let NumMicroOps = 7;
}
-def : InstRW<[4GM7WriteCVTBF16], (instrs VCVTNE2PS2BF16Z256rr, VCVTNE2PS2BF16Z256rrkz,
- VCVTNE2PS2BF16Zrrkz)>;
+def : InstRW<[C4GM7WriteCVTBF16], (instrs VCVTNE2PS2BF16Z256rr, VCVTNE2PS2BF16Z256rrkz,
+ VCVTNE2PS2BF16Zrrkz)>;
-def 4GM7WriteCVTBF16Ld:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteCVTBF16.Latency);
+def C4GM7WriteCVTBF16Ld:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteCVTBF16.Latency);
let ReleaseAtCycles = [1, 1, 6];
let NumMicroOps = 7;
}
-def : InstRW<[4GM7WriteCVTBF16Ld], (instrs VCVTNE2PS2BF16Z256rm, VCVTNE2PS2BF16Z256rmkz,
- VCVTNE2PS2BF16Zrmkz)>;
+def : InstRW<[C4GM7WriteCVTBF16Ld], (instrs VCVTNE2PS2BF16Z256rm, VCVTNE2PS2BF16Z256rmkz,
+ VCVTNE2PS2BF16Zrmkz)>;
// CVT BF16
-def 4GM7WriteCVTBF16rrk:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteCVTBF16rrk:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 5;
let ReleaseAtCycles = [6];
let NumMicroOps = 7;
}
-def : InstRW<[4GM7WriteCVTBF16rrk], (instrs VCVTNE2PS2BF16Z128rrk, VCVTNEPS2BF16Zrrk,
- VCVTNE2PS2BF16Zrrk)>;
+def : InstRW<[C4GM7WriteCVTBF16rrk], (instrs VCVTNE2PS2BF16Z128rrk, VCVTNEPS2BF16Zrrk,
+ VCVTNE2PS2BF16Zrrk)>;
-def 4GM7WriteCVTBF16rmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteCVTBF16rrk.Latency);
+def C4GM7WriteCVTBF16rmk:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteCVTBF16rrk.Latency);
let ReleaseAtCycles = [1, 1, 6];
let NumMicroOps = 7;
}
-def : InstRW<[4GM7WriteCVTBF16rmk], (instrs VCVTNE2PS2BF16Z128rmk, VCVTNEPS2BF16Zrmk)>;
+def : InstRW<[C4GM7WriteCVTBF16rmk], (instrs VCVTNE2PS2BF16Z128rmk, VCVTNEPS2BF16Zrmk)>;
// CVT BF16
-def 4GM7WriteCVTBF16rr:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteCVTBF16rr:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 8;
let ReleaseAtCycles = [6];
let NumMicroOps = 7;
}
-def : InstRW<[4GM7WriteCVTBF16rr], (instrs VCVTNE2PS2BF16Zrr)>;
+def : InstRW<[C4GM7WriteCVTBF16rr], (instrs VCVTNE2PS2BF16Zrr)>;
-def 4GM7WriteCVTBF16rm:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteCVTBF16rr.Latency);
+def C4GM7WriteCVTBF16rm:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteCVTBF16rr.Latency);
let ReleaseAtCycles = [1, 1, 6];
let NumMicroOps = 7;
}
-def : InstRW<[4GM7WriteCVTBF16rm], (instrs VCVTNE2PS2BF16Zrm)>;
+def : InstRW<[C4GM7WriteCVTBF16rm], (instrs VCVTNE2PS2BF16Zrm)>;
// VDPBF16
-def 4GM7WriteVDPBF16:SchedWriteRes<[4GM7FPU02, 4GM7FPU02]> {
+def C4GM7WriteVDPBF16:SchedWriteRes<[C4GM7FPU02, C4GM7FPU02]> {
let Latency = 8;
let ReleaseAtCycles = [4, 4];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVDPBF16], (instrs VDPBF16PSZr, VDPBF16PSZrkz,
- VDPBF16PSZ128r, VDPBF16PSZ128rkz,
- VDPBF16PSZ256r, VDPBF16PSZ256rkz)>;
+def : InstRW<[C4GM7WriteVDPBF16], (instrs VDPBF16PSZr, VDPBF16PSZrkz,
+ VDPBF16PSZ128r, VDPBF16PSZ128rkz,
+ VDPBF16PSZ256r, VDPBF16PSZ256rkz)>;
-def 4GM7WriteVDPBF16Ld:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVDPBF16.Latency);
+def C4GM7WriteVDPBF16Ld:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVDPBF16.Latency);
let ReleaseAtCycles = [1, 1, 4, 4];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVDPBF16Ld], (instrs VDPBF16PSZm, VDPBF16PSZmkz,
- VDPBF16PSZ128m, VDPBF16PSZ128mkz,
- VDPBF16PSZ256m, VDPBF16PSZ256mkz)>;
+def : InstRW<[C4GM7WriteVDPBF16Ld], (instrs VDPBF16PSZm, VDPBF16PSZmkz,
+ VDPBF16PSZ128m, VDPBF16PSZ128mkz,
+ VDPBF16PSZ256m, VDPBF16PSZ256mkz)>;
// VDPBF16
-def 4GM7WriteVDPBF16rk:SchedWriteRes<[4GM7FPU02, 4GM7FPU02]> {
+def C4GM7WriteVDPBF16rk:SchedWriteRes<[C4GM7FPU02, C4GM7FPU02]> {
let Latency = 10;
let ReleaseAtCycles = [4, 4];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVDPBF16rk], (instrs VDPBF16PSZrk, VDPBF16PSZ128rk, VDPBF16PSZ256rk)>;
+def : InstRW<[C4GM7WriteVDPBF16rk], (instrs VDPBF16PSZrk, VDPBF16PSZ128rk, VDPBF16PSZ256rk)>;
-def 4GM7WriteVDPBF16mk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVDPBF16rk.Latency);
+def C4GM7WriteVDPBF16mk:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVDPBF16rk.Latency);
let ReleaseAtCycles = [1, 1, 4, 4];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVDPBF16mk], (instrs VDPBF16PSZmk, VDPBF16PSZ128mk, VDPBF16PSZ256mk)>;
+def : InstRW<[C4GM7WriteVDPBF16mk], (instrs VDPBF16PSZmk, VDPBF16PSZ128mk, VDPBF16PSZ256mk)>;
// VCVT rrk
-def 4GM7WriteVCVTrrk:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteVCVTrrk:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 5;
let ReleaseAtCycles = [2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVCVTrrk], (instrs VCVTPD2PSZ128rrk, VCVTPD2PSZ128rrk, VCVTSD2SSZrrbk_Int,
- VCVTSD2SSZrrk_Int, VCVTSS2SDZrrbk_Int, VCVTSS2SDZrrk_Int,
- VCVTDQ2PDZ128rrk, VCVTUDQ2PDZ128rrk, VCVTDQ2PDZ256rrk,
- VCVTUDQ2PDZ256rrk, VCVTDQ2PSZ128rrk, VCVTUDQ2PSZ128rrk,
- VCVTDQ2PSZ256rrk, VCVTUDQ2PSZ256rrk, VCVTDQ2PSZrrbk,
- VCVTDQ2PSZrrk, VCVTUDQ2PSZrrbk, VCVTUDQ2PSZrrk,
- VCVTPD2DQZ128rrk, VCVTPD2UDQZ128rrk, VCVTTPD2DQZ128rrk,
- VCVTTPD2UDQZ128rrk, VCVTPD2DQZ256rrk, VCVTPD2UDQZ256rrk,
- VCVTTPD2DQZ256rrk, VCVTTPD2UDQZ256rrk, VCVTPD2DQZrrbk,
- VCVTPD2DQZrrk, VCVTPD2UDQZrrbk, VCVTPD2UDQZrrk,
- VCVTTPD2DQZrrbk, VCVTTPD2DQZrrk, VCVTTPD2UDQZrrbk,
- VCVTTPD2UDQZrrk, VCVTPD2PSZ256rrk, VCVTPD2PSZrrbk,
- VCVTPD2PSZrrk, VCVTPD2QQZ128rrk, VCVTPD2UQQZ128rrk,
- VCVTTPD2QQZ128rrk, VCVTTPD2UQQZ128rrk, VCVTPD2QQZ256rrk,
- VCVTPD2UQQZ256rrk, VCVTTPD2QQZ256rrk, VCVTTPD2UQQZ256rrk,
- VCVTPD2QQZrrbk, VCVTPD2QQZrrk, VCVTPD2UQQZrrbk,
- VCVTPD2UQQZrrk, VCVTTPD2QQZrrbk, VCVTTPD2QQZrrk,
- VCVTTPD2UQQZrrbk, VCVTTPD2UQQZrrk, VCVTPH2PSZ128rrk,
- VCVTPH2PSZ256rrk, VCVTPS2DQZ256rrk, VCVTPS2UDQZ256rrk,
- VCVTTPS2DQZ256rrk, VCVTTPS2UDQZ256rrk, VCVTPS2DQZ128rrk,
- VCVTPS2UDQZ128rrk, VCVTTPS2DQZ128rrk, VCVTTPS2UDQZ128rrk,
- VCVTPS2DQZrrbk, VCVTPS2DQZrrk, VCVTPS2UDQZrrbk,
- VCVTPS2UDQZrrk, VCVTTPS2DQZrrbk, VCVTTPS2DQZrrk,
- VCVTTPS2UDQZrrbk, VCVTTPS2UDQZrrk, VCVTPS2PDZ256rrk,
- VCVTPS2PHZ128rrk, VCVTPS2PHZ256rrk, VCVTPS2PHZrrbk,
- VCVTPS2PHZrrk, VCVTPS2QQZ128rrk, VCVTPS2UQQZ128rrk,
- VCVTTPS2QQZ128rrk, VCVTTPS2UQQZ128rrk, VCVTPS2QQZ256rrk,
- VCVTPS2UQQZ256rrk, VCVTTPS2QQZ256rrk, VCVTTPS2UQQZ256rrk,
- VCVTQQ2PDZ128rrk, VCVTUQQ2PDZ128rrk, VCVTQQ2PDZ256rrk,
- VCVTUQQ2PDZ256rrk, VCVTQQ2PDZrrbk, VCVTQQ2PDZrrk,
- VCVTUQQ2PDZrrbk, VCVTUQQ2PDZrrk, VCVTQQ2PSZ128rrk,
- VCVTUQQ2PSZ128rrk, VCVTQQ2PSZ256rrk, VCVTUQQ2PSZ256rrk,
- VCVTQQ2PSZrrbk, VCVTQQ2PSZrrk, VCVTUQQ2PSZrrbk,
- VCVTUQQ2PSZrrk, VCVTPS2PDZ128rrk, VCVTPS2QQZrr,
- VCVTPS2UQQZrr, VCVTTPS2QQZrr, VCVTTPS2UQQZrr,
- VCVTPS2QQZrrb, VCVTPS2QQZrrbkz, VCVTPS2QQZrrkz,
- VCVTPS2UQQZrrb, VCVTPS2UQQZrrbkz, VCVTPS2UQQZrrkz,
- VCVTTPS2QQZrrb, VCVTTPS2QQZrrbkz, VCVTTPS2QQZrrkz,
- VCVTTPS2UQQZrrb, VCVTTPS2UQQZrrbkz, VCVTTPS2UQQZrrkz,
- VCVTPS2QQZrrbk, VCVTPS2QQZrrk, VCVTPS2UQQZrrbk,
- VCVTPS2UQQZrrk, VCVTTPS2QQZrrbk, VCVTTPS2QQZrrk,
- VCVTTPS2UQQZrrbk, VCVTTPS2UQQZrrk)>;
-
-def 4GM7WriteVCVTrrkLD:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVCVTrrk.Latency);
+def : InstRW<[C4GM7WriteVCVTrrk], (instrs VCVTPD2PSZ128rrk, VCVTPD2PSZ128rrk, VCVTSD2SSZrrbk_Int,
+ VCVTSD2SSZrrk_Int, VCVTSS2SDZrrbk_Int, VCVTSS2SDZrrk_Int,
+ VCVTDQ2PDZ128rrk, VCVTUDQ2PDZ128rrk, VCVTDQ2PDZ256rrk,
+ VCVTUDQ2PDZ256rrk, VCVTDQ2PSZ128rrk, VCVTUDQ2PSZ128rrk,
+ VCVTDQ2PSZ256rrk, VCVTUDQ2PSZ256rrk, VCVTDQ2PSZrrbk,
+ VCVTDQ2PSZrrk, VCVTUDQ2PSZrrbk, VCVTUDQ2PSZrrk,
+ VCVTPD2DQZ128rrk, VCVTPD2UDQZ128rrk, VCVTTPD2DQZ128rrk,
+ VCVTTPD2UDQZ128rrk, VCVTPD2DQZ256rrk, VCVTPD2UDQZ256rrk,
+ VCVTTPD2DQZ256rrk, VCVTTPD2UDQZ256rrk, VCVTPD2DQZrrbk,
+ VCVTPD2DQZrrk, VCVTPD2UDQZrrbk, VCVTPD2UDQZrrk,
+ VCVTTPD2DQZrrbk, VCVTTPD2DQZrrk, VCVTTPD2UDQZrrbk,
+ VCVTTPD2UDQZrrk, VCVTPD2PSZ256rrk, VCVTPD2PSZrrbk,
+ VCVTPD2PSZrrk, VCVTPD2QQZ128rrk, VCVTPD2UQQZ128rrk,
+ VCVTTPD2QQZ128rrk, VCVTTPD2UQQZ128rrk, VCVTPD2QQZ256rrk,
+ VCVTPD2UQQZ256rrk, VCVTTPD2QQZ256rrk, VCVTTPD2UQQZ256rrk,
+ VCVTPD2QQZrrbk, VCVTPD2QQZrrk, VCVTPD2UQQZrrbk,
+ VCVTPD2UQQZrrk, VCVTTPD2QQZrrbk, VCVTTPD2QQZrrk,
+ VCVTTPD2UQQZrrbk, VCVTTPD2UQQZrrk, VCVTPH2PSZ128rrk,
+ VCVTPH2PSZ256rrk, VCVTPS2DQZ256rrk, VCVTPS2UDQZ256rrk,
+ VCVTTPS2DQZ256rrk, VCVTTPS2UDQZ256rrk, VCVTPS2DQZ128rrk,
+ VCVTPS2UDQZ128rrk, VCVTTPS2DQZ128rrk, VCVTTPS2UDQZ128rrk,
+ VCVTPS2DQZrrbk, VCVTPS2DQZrrk, VCVTPS2UDQZrrbk,
+ VCVTPS2UDQZrrk, VCVTTPS2DQZrrbk, VCVTTPS2DQZrrk,
+ VCVTTPS2UDQZrrbk, VCVTTPS2UDQZrrk, VCVTPS2PDZ256rrk,
+ VCVTPS2PHZ128rrk, VCVTPS2PHZ256rrk, VCVTPS2PHZrrbk,
+ VCVTPS2PHZrrk, VCVTPS2QQZ128rrk, VCVTPS2UQQZ128rrk,
+ VCVTTPS2QQZ128rrk, VCVTTPS2UQQZ128rrk, VCVTPS2QQZ256rrk,
+ VCVTPS2UQQZ256rrk, VCVTTPS2QQZ256rrk, VCVTTPS2UQQZ256rrk,
+ VCVTQQ2PDZ128rrk, VCVTUQQ2PDZ128rrk, VCVTQQ2PDZ256rrk,
+ VCVTUQQ2PDZ256rrk, VCVTQQ2PDZrrbk, VCVTQQ2PDZrrk,
+ VCVTUQQ2PDZrrbk, VCVTUQQ2PDZrrk, VCVTQQ2PSZ128rrk,
+ VCVTUQQ2PSZ128rrk, VCVTQQ2PSZ256rrk, VCVTUQQ2PSZ256rrk,
+ VCVTQQ2PSZrrbk, VCVTQQ2PSZrrk, VCVTUQQ2PSZrrbk,
+ VCVTUQQ2PSZrrk, VCVTPS2PDZ128rrk, VCVTPS2QQZrr,
+ VCVTPS2UQQZrr, VCVTTPS2QQZrr, VCVTTPS2UQQZrr,
+ VCVTPS2QQZrrb, VCVTPS2QQZrrbkz, VCVTPS2QQZrrkz,
+ VCVTPS2UQQZrrb, VCVTPS2UQQZrrbkz, VCVTPS2UQQZrrkz,
+ VCVTTPS2QQZrrb, VCVTTPS2QQZrrbkz, VCVTTPS2QQZrrkz,
+ VCVTTPS2UQQZrrb, VCVTTPS2UQQZrrbkz, VCVTTPS2UQQZrrkz,
+ VCVTPS2QQZrrbk, VCVTPS2QQZrrk, VCVTPS2UQQZrrbk,
+ VCVTPS2UQQZrrk, VCVTTPS2QQZrrbk, VCVTTPS2QQZrrk,
+ VCVTTPS2UQQZrrbk, VCVTTPS2UQQZrrk)>;
+
+def C4GM7WriteVCVTrrkLD:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVCVTrrk.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVCVTrrkLD], (instrs VCVTPD2PSZ128rmk, VCVTPD2PSZ128rmk,
- VCVTSD2SSZrmk_Int, VCVTSS2SDZrmk_Int,
- VCVTDQ2PDZ128rmk, VCVTUDQ2PDZ128rmk, VCVTDQ2PDZ256rmk,
- VCVTUDQ2PDZ256rmk, VCVTDQ2PSZ128rmk, VCVTUDQ2PSZ128rmk,
- VCVTDQ2PSZ256rmk, VCVTUDQ2PSZ256rmk, VCVTDQ2PSZrmbk,
- VCVTDQ2PSZrmk, VCVTUDQ2PSZrmbk, VCVTUDQ2PSZrmk,
- VCVTPD2DQZ128rmk, VCVTPD2UDQZ128rmk, VCVTTPD2DQZ128rmk,
- VCVTTPD2UDQZ128rmk, VCVTPD2DQZ256rmk, VCVTPD2UDQZ256rmk,
- VCVTTPD2DQZ256rmk, VCVTTPD2UDQZ256rmk, VCVTPD2DQZrmbk,
- VCVTPD2DQZrmk, VCVTPD2UDQZrmbk, VCVTPD2UDQZrmk,
- VCVTTPD2DQZrmbk, VCVTTPD2DQZrmk, VCVTTPD2UDQZrmbk,
- VCVTTPD2UDQZrmk, VCVTPD2PSZ256rmk, VCVTPD2PSZrmbk,
- VCVTPD2PSZrmk, VCVTPD2QQZ128rmk, VCVTPD2UQQZ128rmk,
- VCVTTPD2QQZ128rmk, VCVTTPD2UQQZ128rmk, VCVTPD2QQZ256rmk,
- VCVTPD2UQQZ256rmk, VCVTTPD2QQZ256rmk, VCVTTPD2UQQZ256rmk,
- VCVTPD2QQZrmbk, VCVTPD2QQZrmk, VCVTPD2UQQZrmbk,
- VCVTPD2UQQZrmk, VCVTTPD2QQZrmbk, VCVTTPD2QQZrmk,
- VCVTTPD2UQQZrmbk, VCVTTPD2UQQZrmk, VCVTPH2PSZ128rmk,
- VCVTPH2PSZ256rmk, VCVTPS2DQZ256rmk, VCVTPS2UDQZ256rmk,
- VCVTTPS2DQZ256rmk, VCVTTPS2UDQZ256rmk, VCVTPS2DQZ128rmk,
- VCVTPS2UDQZ128rmk, VCVTTPS2DQZ128rmk, VCVTTPS2UDQZ128rmk,
- VCVTPS2DQZrmbk, VCVTPS2DQZrmk, VCVTPS2UDQZrmbk,
- VCVTPS2UDQZrmk, VCVTTPS2DQZrmbk, VCVTTPS2DQZrmk,
- VCVTTPS2UDQZrmbk, VCVTTPS2UDQZrmk, VCVTPS2PDZ256rmk,
- VCVTPS2QQZ128rmk, VCVTPS2UQQZ128rmk,
- VCVTTPS2QQZ128rmk, VCVTTPS2UQQZ128rmk, VCVTPS2QQZ256rmk,
- VCVTPS2UQQZ256rmk, VCVTTPS2QQZ256rmk, VCVTTPS2UQQZ256rmk,
- VCVTQQ2PDZ128rmk, VCVTUQQ2PDZ128rmk, VCVTQQ2PDZ256rmk,
- VCVTUQQ2PDZ256rmk, VCVTQQ2PDZrmbk, VCVTQQ2PDZrmk,
- VCVTUQQ2PDZrmbk, VCVTUQQ2PDZrmk, VCVTQQ2PSZ128rmk,
- VCVTUQQ2PSZ128rmk, VCVTQQ2PSZ256rmk, VCVTUQQ2PSZ256rmk,
- VCVTQQ2PSZrmbk, VCVTQQ2PSZrmk, VCVTUQQ2PSZrmbk,
- VCVTUQQ2PSZrmk, VCVTPS2PDZ128rmk, VCVTPS2QQZrm,
- VCVTPS2UQQZrm, VCVTTPS2QQZrm, VCVTTPS2UQQZrm,
- VCVTPS2QQZrmb, VCVTPS2QQZrmbkz, VCVTPS2QQZrmkz,
- VCVTPS2UQQZrmb, VCVTPS2UQQZrmbkz, VCVTPS2UQQZrmkz,
- VCVTTPS2QQZrmb, VCVTTPS2QQZrmbkz, VCVTTPS2QQZrmkz,
- VCVTTPS2UQQZrmb, VCVTTPS2UQQZrmbkz, VCVTTPS2UQQZrmkz,
- VCVTPS2QQZrmbk, VCVTPS2QQZrmk, VCVTPS2UQQZrmbk,
- VCVTPS2UQQZrmk, VCVTTPS2QQZrmbk, VCVTTPS2QQZrmk,
- VCVTTPS2UQQZrmbk, VCVTTPS2UQQZrmk)>;
+def : InstRW<[C4GM7WriteVCVTrrkLD], (instrs VCVTPD2PSZ128rmk, VCVTPD2PSZ128rmk,
+ VCVTSD2SSZrmk_Int, VCVTSS2SDZrmk_Int,
+ VCVTDQ2PDZ128rmk, VCVTUDQ2PDZ128rmk, VCVTDQ2PDZ256rmk,
+ VCVTUDQ2PDZ256rmk, VCVTDQ2PSZ128rmk, VCVTUDQ2PSZ128rmk,
+ VCVTDQ2PSZ256rmk, VCVTUDQ2PSZ256rmk, VCVTDQ2PSZrmbk,
+ VCVTDQ2PSZrmk, VCVTUDQ2PSZrmbk, VCVTUDQ2PSZrmk,
+ VCVTPD2DQZ128rmk, VCVTPD2UDQZ128rmk, VCVTTPD2DQZ128rmk,
+ VCVTTPD2UDQZ128rmk, VCVTPD2DQZ256rmk, VCVTPD2UDQZ256rmk,
+ VCVTTPD2DQZ256rmk, VCVTTPD2UDQZ256rmk, VCVTPD2DQZrmbk,
+ VCVTPD2DQZrmk, VCVTPD2UDQZrmbk, VCVTPD2UDQZrmk,
+ VCVTTPD2DQZrmbk, VCVTTPD2DQZrmk, VCVTTPD2UDQZrmbk,
+ VCVTTPD2UDQZrmk, VCVTPD2PSZ256rmk, VCVTPD2PSZrmbk,
+ VCVTPD2PSZrmk, VCVTPD2QQZ128rmk, VCVTPD2UQQZ128rmk,
+ VCVTTPD2QQZ128rmk, VCVTTPD2UQQZ128rmk, VCVTPD2QQZ256rmk,
+ VCVTPD2UQQZ256rmk, VCVTTPD2QQZ256rmk, VCVTTPD2UQQZ256rmk,
+ VCVTPD2QQZrmbk, VCVTPD2QQZrmk, VCVTPD2UQQZrmbk,
+ VCVTPD2UQQZrmk, VCVTTPD2QQZrmbk, VCVTTPD2QQZrmk,
+ VCVTTPD2UQQZrmbk, VCVTTPD2UQQZrmk, VCVTPH2PSZ128rmk,
+ VCVTPH2PSZ256rmk, VCVTPS2DQZ256rmk, VCVTPS2UDQZ256rmk,
+ VCVTTPS2DQZ256rmk, VCVTTPS2UDQZ256rmk, VCVTPS2DQZ128rmk,
+ VCVTPS2UDQZ128rmk, VCVTTPS2DQZ128rmk, VCVTTPS2UDQZ128rmk,
+ VCVTPS2DQZrmbk, VCVTPS2DQZrmk, VCVTPS2UDQZrmbk,
+ VCVTPS2UDQZrmk, VCVTTPS2DQZrmbk, VCVTTPS2DQZrmk,
+ VCVTTPS2UDQZrmbk, VCVTTPS2UDQZrmk, VCVTPS2PDZ256rmk,
+ VCVTPS2QQZ128rmk, VCVTPS2UQQZ128rmk,
+ VCVTTPS2QQZ128rmk, VCVTTPS2UQQZ128rmk, VCVTPS2QQZ256rmk,
+ VCVTPS2UQQZ256rmk, VCVTTPS2QQZ256rmk, VCVTTPS2UQQZ256rmk,
+ VCVTQQ2PDZ128rmk, VCVTUQQ2PDZ128rmk, VCVTQQ2PDZ256rmk,
+ VCVTUQQ2PDZ256rmk, VCVTQQ2PDZrmbk, VCVTQQ2PDZrmk,
+ VCVTUQQ2PDZrmbk, VCVTUQQ2PDZrmk, VCVTQQ2PSZ128rmk,
+ VCVTUQQ2PSZ128rmk, VCVTQQ2PSZ256rmk, VCVTUQQ2PSZ256rmk,
+ VCVTQQ2PSZrmbk, VCVTQQ2PSZrmk, VCVTUQQ2PSZrmbk,
+ VCVTUQQ2PSZrmk, VCVTPS2PDZ128rmk, VCVTPS2QQZrm,
+ VCVTPS2UQQZrm, VCVTTPS2QQZrm, VCVTTPS2UQQZrm,
+ VCVTPS2QQZrmb, VCVTPS2QQZrmbkz, VCVTPS2QQZrmkz,
+ VCVTPS2UQQZrmb, VCVTPS2UQQZrmbkz, VCVTPS2UQQZrmkz,
+ VCVTTPS2QQZrmb, VCVTTPS2QQZrmbkz, VCVTTPS2QQZrmkz,
+ VCVTTPS2UQQZrmb, VCVTTPS2UQQZrmbkz, VCVTTPS2UQQZrmkz,
+ VCVTPS2QQZrmbk, VCVTPS2QQZrmk, VCVTPS2UQQZrmbk,
+ VCVTPS2UQQZrmk, VCVTTPS2QQZrmbk, VCVTTPS2QQZrmk,
+ VCVTTPS2UQQZrmbk, VCVTTPS2UQQZrmk)>;
// VCVT
-def 4GM7WriteVCVTrr:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteVCVTrr:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 4;
let ReleaseAtCycles = [2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVCVTrr], (instrs VCVTPD2QQZrrb, VCVTPD2QQZrrbkz, VCVTPD2UQQZrrb,
- VCVTPD2UQQZrrbkz, VCVTTPD2QQZrrb, VCVTTPD2QQZrrbkz,
- VCVTTPD2UQQZrrb, VCVTTPD2UQQZrrbkz, VCVTQQ2PDZrr,
- VCVTQQ2PDZrrb, VCVTQQ2PDZrrbkz, VCVTQQ2PDZrrkz,
- VCVTUQQ2PDZrr, VCVTUQQ2PDZrrb, VCVTUQQ2PDZrrbkz,
- VCVTUQQ2PDZrrkz)>;
+def : InstRW<[C4GM7WriteVCVTrr], (instrs VCVTPD2QQZrrb, VCVTPD2QQZrrbkz, VCVTPD2UQQZrrb,
+ VCVTPD2UQQZrrbkz, VCVTTPD2QQZrrb, VCVTTPD2QQZrrbkz,
+ VCVTTPD2UQQZrrb, VCVTTPD2UQQZrrbkz, VCVTQQ2PDZrr,
+ VCVTQQ2PDZrrb, VCVTQQ2PDZrrbkz, VCVTQQ2PDZrrkz,
+ VCVTUQQ2PDZrr, VCVTUQQ2PDZrrb, VCVTUQQ2PDZrrbkz,
+ VCVTUQQ2PDZrrkz)>;
-def 4GM7WriteVCVTrm:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVCVTrr.Latency);
+def C4GM7WriteVCVTrm:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVCVTrr.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVCVTrm], (instrs VCVTPD2QQZrmb, VCVTPD2QQZrmbkz, VCVTPD2UQQZrmb,
- VCVTPD2UQQZrmbkz, VCVTTPD2QQZrmb, VCVTTPD2QQZrmbkz,
- VCVTTPD2UQQZrmb, VCVTTPD2UQQZrmbkz, VCVTQQ2PDZrm,
- VCVTQQ2PDZrmb, VCVTQQ2PDZrmbkz, VCVTQQ2PDZrmkz,
- VCVTUQQ2PDZrm, VCVTUQQ2PDZrmb, VCVTUQQ2PDZrmbkz,
- VCVTUQQ2PDZrmkz)>;
+def : InstRW<[C4GM7WriteVCVTrm], (instrs VCVTPD2QQZrmb, VCVTPD2QQZrmbkz, VCVTPD2UQQZrmb,
+ VCVTPD2UQQZrmbkz, VCVTTPD2QQZrmb, VCVTTPD2QQZrmbkz,
+ VCVTTPD2UQQZrmb, VCVTTPD2UQQZrmbkz, VCVTQQ2PDZrm,
+ VCVTQQ2PDZrmb, VCVTQQ2PDZrmbkz, VCVTQQ2PDZrmkz,
+ VCVTUQQ2PDZrm, VCVTUQQ2PDZrmb, VCVTUQQ2PDZrmbkz,
+ VCVTUQQ2PDZrmkz)>;
// VCVTQQ2PS
-def 4GM7WriteVCVTQQ2PS:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteVCVTQQ2PS:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 8;
let ReleaseAtCycles = [2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVCVTQQ2PS], (instrs VCVTQQ2PSZrr, VCVTQQ2PSZrrb, VCVTQQ2PSZrrbkz, VCVTQQ2PSZrrkz,
- VCVTUQQ2PSZrr, VCVTUQQ2PSZrrb, VCVTUQQ2PSZrrbkz, VCVTUQQ2PSZrrkz)>;
+def : InstRW<[C4GM7WriteVCVTQQ2PS], (instrs VCVTQQ2PSZrr, VCVTQQ2PSZrrb, VCVTQQ2PSZrrbkz, VCVTQQ2PSZrrkz,
+ VCVTUQQ2PSZrr, VCVTUQQ2PSZrrb, VCVTUQQ2PSZrrbkz, VCVTUQQ2PSZrrkz)>;
-def 4GM7WriteVCVTQQ2PSLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVCVTQQ2PS.Latency);
+def C4GM7WriteVCVTQQ2PSLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVCVTQQ2PS.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVCVTQQ2PSLd], (instrs VCVTQQ2PSZrm, VCVTQQ2PSZrmb, VCVTQQ2PSZrmbkz, VCVTQQ2PSZrmkz,
- VCVTUQQ2PSZrm, VCVTUQQ2PSZrmb, VCVTUQQ2PSZrmbkz, VCVTUQQ2PSZrmkz)>;
+def : InstRW<[C4GM7WriteVCVTQQ2PSLd], (instrs VCVTQQ2PSZrm, VCVTQQ2PSZrmb, VCVTQQ2PSZrmbkz, VCVTQQ2PSZrmkz,
+ VCVTUQQ2PSZrm, VCVTUQQ2PSZrmb, VCVTUQQ2PSZrmbkz, VCVTUQQ2PSZrmkz)>;
// VCVTNE2PS2BF16Z128
-def 4GM7WriteVCVTNE2PS2BF16Z128:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteVCVTNE2PS2BF16Z128:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 9;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVCVTNE2PS2BF16Z128], (instrs VCVTNE2PS2BF16Z128rr,
- VCVTNE2PS2BF16Z128rrkz)>;
+def : InstRW<[C4GM7WriteVCVTNE2PS2BF16Z128], (instrs VCVTNE2PS2BF16Z128rr,
+ VCVTNE2PS2BF16Z128rrkz)>;
-def 4GM7WriteVCVTNE2PS2BF16Z128Ld:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVCVTNE2PS2BF16Z128.Latency);
+def C4GM7WriteVCVTNE2PS2BF16Z128Ld:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVCVTNE2PS2BF16Z128.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVCVTNE2PS2BF16Z128Ld], (instrs VCVTNE2PS2BF16Z128rm,
- VCVTNE2PS2BF16Z128rmkz)>;
+def : InstRW<[C4GM7WriteVCVTNE2PS2BF16Z128Ld], (instrs VCVTNE2PS2BF16Z128rm,
+ VCVTNE2PS2BF16Z128rmkz)>;
// VCVTNE2PS2BF16Z VCVTNE2PS2BF16Z256 VCVTNEPS2BF16
-def 4GM7WriteVCVTNEPS2BF16:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteVCVTNEPS2BF16:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 5;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVCVTNEPS2BF16], (instrs VCVTNE2PS2BF16Z256rrk,
- VCVTNEPS2BF16Z128rrk, VCVTNEPS2BF16Z256rrk)>;
+def : InstRW<[C4GM7WriteVCVTNEPS2BF16], (instrs VCVTNE2PS2BF16Z256rrk,
+ VCVTNEPS2BF16Z128rrk, VCVTNEPS2BF16Z256rrk)>;
-def 4GM7WriteVCVTNEPS2BF16Ld:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVCVTNEPS2BF16.Latency);
+def C4GM7WriteVCVTNEPS2BF16Ld:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVCVTNEPS2BF16.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVCVTNEPS2BF16Ld], (instrs VCVTNE2PS2BF16Z256rmk,
- VCVTNEPS2BF16Z128rmk, VCVTNEPS2BF16Z256rmk)>;
-
-
-defm : 4GM7WriteResFPPair<WriteFSign, [4GM7FPU1], 1>;
-defm : 4GM7WriteResFPPair<WriteFRnd, [4GM7FPU13], 4, [1], 1>;
-defm : 4GM7WriteResFPPair<WriteFRndY, [4GM7FPU13], 4, [1], 1>;
-defm : 4GM7WriteResFPPair<WriteFRndZ, [4GM7FPU13], 4, [2], 2>;
-defm : 4GM7WriteResFPPair<WriteFLogic, [4GM7FPU], 1>;
-defm : 4GM7WriteResFPPair<WriteFLogicY, [4GM7FPU], 1>;
-defm : 4GM7WriteResFPPair<WriteFLogicZ, [4GM7FPU], 1>;
-defm : 4GM7WriteResFPPair<WriteFTest, [4GM7FPU13], 1, [1], 1>;
-defm : 4GM7WriteResFPPair<WriteFTestY, [4GM7FPU13], 1, [1], 1>;
-defm : 4GM7WriteResFPPair<WriteFTestZ, [4GM7FPU13], 1, [2], 2>;
-defm : 4GM7WriteResFPPair<WriteFShuffle, [4GM7FPU13], 1, [1], 1>;
-defm : 4GM7WriteResFPPair<WriteFShuffleY, [4GM7FPU13], 1, [1], 1>;
-defm : 4GM7WriteResFPPair<WriteFShuffleZ, [4GM7FPU13], 1, [2], 1>;
-defm : 4GM7WriteResFPPair<WriteFVarShuffle, [4GM7FPU02], 3, [4], 1>;
-defm : 4GM7WriteResFPPair<WriteFVarShuffleY,[4GM7FPU02], 3, [4], 1>;
-defm : 4GM7WriteResFPPair<WriteFVarShuffleZ,[4GM7FPU02], 5, [8], 1>;
-defm : 4GM7WriteResFPPair<WriteFShuffle256, [4GM7FPU02], 3>;
-defm : 4GM7WriteResFPPair<WriteFVarShuffle256, [4GM7FPU02], 3>;
-
-defm : 4GM7WriteRes<WriteVecLoad, [4GM7AGU, 4GM7Load], !add(C864GM7Model.VecLoadLatency, 1), [1, 1], 1>;
-defm : 4GM7WriteRes<WriteVecLoadX, [4GM7AGU, 4GM7Load], !add(C864GM7Model.VecLoadLatency, 1), [1, 1], 1>;
-defm : 4GM7WriteRes<WriteVecLoadY, [4GM7AGU, 4GM7Load], !add(C864GM7Model.VecLoadLatency, 1), [1, 1], 1>;
-defm : 4GM7WriteRes<WriteVecLoadNT, [4GM7AGU, 4GM7Load], !add(C864GM7Model.VecLoadLatency, 1), [1, 1], 1>;
-defm : 4GM7WriteRes<WriteVecLoadNTY, [4GM7AGU, 4GM7Load], !add(C864GM7Model.VecLoadLatency, 1), [1, 1], 1>;
-defm : 4GM7WriteRes<WriteVecMaskedLoad, [4GM7AGU, 4GM7Load, 4GM7FPU01], !add(C864GM7Model.VecLoadLatency, 1), [1, 1, 2], 1>;
-defm : 4GM7WriteRes<WriteVecMaskedLoadY, [4GM7AGU, 4GM7Load, 4GM7FPU01], !add(C864GM7Model.VecLoadLatency, 1), [1, 1, 2], 1>;
-defm : 4GM7WriteRes<WriteVecStore, [4GM7AGU, 4GM7Store], C864GM7Model.StoreLatency>;
-defm : 4GM7WriteRes<WriteVecStoreX, [4GM7AGU, 4GM7Store], C864GM7Model.StoreLatency>;
-defm : 4GM7WriteRes<WriteVecStoreY, [4GM7AGU, 4GM7Store], C864GM7Model.StoreLatency>;
-defm : 4GM7WriteRes<WriteVecStoreNT, [4GM7FPU1, 4GM7AGU, 4GM7Store], !add(1, C864GM7Model.StoreLatency)>;
-defm : 4GM7WriteRes<WriteVecStoreNTY, [4GM7FPU1, 4GM7AGU, 4GM7Store], !add(1, C864GM7Model.StoreLatency)>;
-defm : 4GM7WriteRes<WriteVecMaskedStore32, [4GM7FPU01, 4GM7AGU, 4GM7Store], !add(1, C864GM7Model.StoreLatency)>;
-defm : 4GM7WriteRes<WriteVecMaskedStore32Y, [4GM7FPU01, 4GM7AGU, 4GM7Store], !add(1, C864GM7Model.StoreLatency)>;
-defm : 4GM7WriteRes<WriteVecMaskedStore64, [4GM7FPU01, 4GM7AGU, 4GM7Store], !add(1, C864GM7Model.StoreLatency)>;
-defm : 4GM7WriteRes<WriteVecMaskedStore64Y, [4GM7FPU01, 4GM7AGU, 4GM7Store], !add(1, C864GM7Model.StoreLatency)>;
-defm : 4GM7WriteRes<WriteVecMoveToGpr, [4GM7FPU13], 1, [2], 1>;
-defm : 4GM7WriteRes<WriteVecMoveFromGpr, [4GM7FPU], 1, [4], 2>;
-defm : 4GM7WriteRes<WriteEMMS, [], 0, [], 1>;
-
-defm : 4GM7WriteResFPPair<WriteVecShift, [4GM7FPU02], 1>; // from llvm-exegesis
-defm : 4GM7WriteResFPPair<WriteVecShiftX, [4GM7FPU02], 3>;
-defm : 4GM7WriteResFPPair<WriteVecShiftY, [4GM7FPU02], 3>;
-defm : 4GM7WriteResFPPair<WriteVecShiftZ, [4GM7FPU02], 3, [2], 1>;
-defm : 4GM7WriteResFPPair<WriteVecShiftImm, [4GM7FPU02], 1>;
-defm : 4GM7WriteResFPPair<WriteVecShiftImmX, [4GM7FPU02], 1>;
-defm : 4GM7WriteResFPPair<WriteVecShiftImmY, [4GM7FPU02], 1>;
-defm : 4GM7WriteResFPPair<WriteVecShiftImmZ, [4GM7FPU02], 1, [2], 1>;
-defm : 4GM7WriteResFPPair<WriteVarVecShift, [4GM7FPU02], 1, [4], 1>;
-defm : 4GM7WriteResFPPair<WriteVarVecShiftY, [4GM7FPU02], 1, [4], 1>;
-defm : 4GM7WriteResFPPair<WriteVarVecShiftZ, [4GM7FPU02], 1, [8], 1>;
-defm : 4GM7WriteResFPPair<WriteVecLogic, [4GM7FPU], 1>;
-defm : 4GM7WriteResFPPair<WriteVecLogicX, [4GM7FPU], 1>;
-defm : 4GM7WriteResFPPair<WriteVecLogicY, [4GM7FPU], 1>;
-defm : 4GM7WriteResFPPair<WriteVecLogicZ, [4GM7FPU], 1>;
-defm : 4GM7WriteResFPPair<WriteVecTest, [4GM7FPU13], 1>;
-defm : 4GM7WriteResFPPair<WriteVecTestY, [4GM7FPU13], 1>;
-defm : 4GM7WriteResFPPair<WriteVecTestZ, [4GM7FPU13], 1, [2], 1>;
-defm : 4GM7WriteResFPPair<WriteVecALU, [4GM7FPU], 1>;
-defm : 4GM7WriteResFPPair<WriteVecALUX, [4GM7FPU], 1>;
-defm : 4GM7WriteResFPPair<WriteVecALUY, [4GM7FPU], 1>;
-defm : 4GM7WriteResFPPair<WriteVecALUZ, [4GM7FPU], 1, [2], 1>;
-defm : 4GM7WriteResFPPair<WriteVecIMul, [4GM7FPU02], 3>;
-defm : 4GM7WriteResFPPair<WriteVecIMulX, [4GM7FPU02], 3>;
-defm : 4GM7WriteResFPPair<WriteVecIMulY, [4GM7FPU02], 3>;
-defm : 4GM7WriteResFPPair<WriteVecIMulZ, [4GM7FPU02], 3, [2], 1>;
-defm : 4GM7WriteRes<WriteCLMul, [4GM7FPU02], 3>;
-defm : 4GM7WriteRes<WriteCLMulLd, [4GM7AGU, 4GM7Load, 4GM7FPU02], !add(C864GM7Model.VecLoadLatency, 3)>;
-defm : 4GM7WriteResFPPair<WritePMULLD, [4GM7FPU02], 3>;
-defm : 4GM7WriteResFPPair<WritePMULLDY, [4GM7FPU02], 3>;
-defm : 4GM7WriteResFPPair<WritePMULLDZ, [4GM7FPU02], 3, [2], 1>;
-defm : 4GM7WriteResFPPair<WriteShuffle, [4GM7FPU13], 1>;
-defm : 4GM7WriteResFPPair<WriteShuffleX, [4GM7FPU13], 1>;
-defm : 4GM7WriteResFPPair<WriteShuffleY, [4GM7FPU13], 1>;
-defm : 4GM7WriteResFPPair<WriteShuffleZ, [4GM7FPU13], 1, [2], 1>;
-defm : 4GM7WriteResFPPair<WriteVarShuffle, [4GM7FPU13], 1>;
-defm : 4GM7WriteResFPPair<WriteVarShuffleX,[4GM7FPU13], 1>;
-defm : 4GM7WriteResFPPair<WriteVarShuffleY,[4GM7FPU13], 1>;
-defm : 4GM7WriteResFPPair<WriteVarShuffleZ,[4GM7FPU13], 1, [2], 1>;
-defm : 4GM7WriteResFPPair<WriteBlend, [4GM7FPU], 1>;
-defm : 4GM7WriteResFPPair<WriteBlendY, [4GM7FPU], 1>;
-defm : 4GM7WriteResFPPair<WriteBlendZ, [4GM7FPU], 1, [2], 1>;
-defm : 4GM7WriteResFPPair<WriteVarBlend, [4GM7FPU], 1>;
-defm : 4GM7WriteResFPPair<WriteVarBlendY, [4GM7FPU], 1>;
-defm : 4GM7WriteResFPPair<WriteVarBlendZ, [4GM7FPU], 1, [2], 1>;
-defm : 4GM7WriteResFPPair<WriteShuffle256, [4GM7FPU01], 3>;
-defm : 4GM7WriteResFPPair<WriteVPMOV256, [4GM7FPU02], 3>;
-defm : 4GM7WriteResFPPair<WriteVarShuffle256, [4GM7FPU3, 4GM7FPU02], 2, [2, 2], 2>;
-defm : 4GM7WriteResFPPair<WritePSADBW, [4GM7FPU02], 3, [2], 1>;
-defm : 4GM7WriteResFPPair<WritePSADBWX, [4GM7FPU02], 3, [2], 1>;
-defm : 4GM7WriteResFPPair<WritePSADBWY, [4GM7FPU02], 3, [2], 1>;
-defm : 4GM7WriteResFPPair<WritePSADBWZ, [4GM7FPU02], 3, [4], 1>;
-defm : 4GM7WriteResFPPair<WriteMPSAD, [4GM7FPU], 4, [8], 1>;
-defm : 4GM7WriteResFPPair<WriteMPSADY, [4GM7FPU], 4, [8], 1>;
-defm : 4GM7WriteResFPPair<WriteMPSADZ, [4GM7FPU], 4, [16], 1>;
-defm : 4GM7WriteResFPPair<WritePHMINPOS, [4GM7FPU02], 3, [2], 1>;
+def : InstRW<[C4GM7WriteVCVTNEPS2BF16Ld], (instrs VCVTNE2PS2BF16Z256rmk,
+ VCVTNEPS2BF16Z128rmk, VCVTNEPS2BF16Z256rmk)>;
+
+
+defm : C4GM7WriteResFPPair<WriteFSign, [C4GM7FPU1], 1>;
+defm : C4GM7WriteResFPPair<WriteFRnd, [C4GM7FPU13], 4, [1], 1>;
+defm : C4GM7WriteResFPPair<WriteFRndY, [C4GM7FPU13], 4, [1], 1>;
+defm : C4GM7WriteResFPPair<WriteFRndZ, [C4GM7FPU13], 4, [2], 2>;
+defm : C4GM7WriteResFPPair<WriteFLogic, [C4GM7FPU], 1>;
+defm : C4GM7WriteResFPPair<WriteFLogicY, [C4GM7FPU], 1>;
+defm : C4GM7WriteResFPPair<WriteFLogicZ, [C4GM7FPU], 1>;
+defm : C4GM7WriteResFPPair<WriteFTest, [C4GM7FPU13], 1, [1], 1>;
+defm : C4GM7WriteResFPPair<WriteFTestY, [C4GM7FPU13], 1, [1], 1>;
+defm : C4GM7WriteResFPPair<WriteFTestZ, [C4GM7FPU13], 1, [2], 2>;
+defm : C4GM7WriteResFPPair<WriteFShuffle, [C4GM7FPU13], 1, [1], 1>;
+defm : C4GM7WriteResFPPair<WriteFShuffleY, [C4GM7FPU13], 1, [1], 1>;
+defm : C4GM7WriteResFPPair<WriteFShuffleZ, [C4GM7FPU13], 1, [2], 1>;
+defm : C4GM7WriteResFPPair<WriteFVarShuffle, [C4GM7FPU02], 3, [4], 1>;
+defm : C4GM7WriteResFPPair<WriteFVarShuffleY,[C4GM7FPU02], 3, [4], 1>;
+defm : C4GM7WriteResFPPair<WriteFVarShuffleZ,[C4GM7FPU02], 5, [8], 1>;
+defm : C4GM7WriteResFPPair<WriteFShuffle256, [C4GM7FPU02], 3>;
+defm : C4GM7WriteResFPPair<WriteFVarShuffle256, [C4GM7FPU02], 3>;
+
+defm : C4GM7WriteRes<WriteVecLoad, [C4GM7AGU, C4GM7Load], !add(C864GM7Model.VecLoadLatency, 1), [1, 1], 1>;
+defm : C4GM7WriteRes<WriteVecLoadX, [C4GM7AGU, C4GM7Load], !add(C864GM7Model.VecLoadLatency, 1), [1, 1], 1>;
+defm : C4GM7WriteRes<WriteVecLoadY, [C4GM7AGU, C4GM7Load], !add(C864GM7Model.VecLoadLatency, 1), [1, 1], 1>;
+defm : C4GM7WriteRes<WriteVecLoadNT, [C4GM7AGU, C4GM7Load], !add(C864GM7Model.VecLoadLatency, 1), [1, 1], 1>;
+defm : C4GM7WriteRes<WriteVecLoadNTY, [C4GM7AGU, C4GM7Load], !add(C864GM7Model.VecLoadLatency, 1), [1, 1], 1>;
+defm : C4GM7WriteRes<WriteVecMaskedLoad, [C4GM7AGU, C4GM7Load, C4GM7FPU01], !add(C864GM7Model.VecLoadLatency, 1), [1, 1, 2], 1>;
+defm : C4GM7WriteRes<WriteVecMaskedLoadY, [C4GM7AGU, C4GM7Load, C4GM7FPU01], !add(C864GM7Model.VecLoadLatency, 1), [1, 1, 2], 1>;
+defm : C4GM7WriteRes<WriteVecStore, [C4GM7AGU, C4GM7Store], C864GM7Model.StoreLatency>;
+defm : C4GM7WriteRes<WriteVecStoreX, [C4GM7AGU, C4GM7Store], C864GM7Model.StoreLatency>;
+defm : C4GM7WriteRes<WriteVecStoreY, [C4GM7AGU, C4GM7Store], C864GM7Model.StoreLatency>;
+defm : C4GM7WriteRes<WriteVecStoreNT, [C4GM7FPU1, C4GM7AGU, C4GM7Store], !add(1, C864GM7Model.StoreLatency)>;
+defm : C4GM7WriteRes<WriteVecStoreNTY, [C4GM7FPU1, C4GM7AGU, C4GM7Store], !add(1, C864GM7Model.StoreLatency)>;
+defm : C4GM7WriteRes<WriteVecMaskedStore32, [C4GM7FPU01, C4GM7AGU, C4GM7Store], !add(1, C864GM7Model.StoreLatency)>;
+defm : C4GM7WriteRes<WriteVecMaskedStore32Y, [C4GM7FPU01, C4GM7AGU, C4GM7Store], !add(1, C864GM7Model.StoreLatency)>;
+defm : C4GM7WriteRes<WriteVecMaskedStore64, [C4GM7FPU01, C4GM7AGU, C4GM7Store], !add(1, C864GM7Model.StoreLatency)>;
+defm : C4GM7WriteRes<WriteVecMaskedStore64Y, [C4GM7FPU01, C4GM7AGU, C4GM7Store], !add(1, C864GM7Model.StoreLatency)>;
+defm : C4GM7WriteRes<WriteVecMoveToGpr, [C4GM7FPU13], 1, [2], 1>;
+defm : C4GM7WriteRes<WriteVecMoveFromGpr, [C4GM7FPU], 1, [4], 2>;
+defm : C4GM7WriteRes<WriteEMMS, [], 0, [], 1>;
+
+defm : C4GM7WriteResFPPair<WriteVecShift, [C4GM7FPU02], 1>; // from llvm-exegesis
+defm : C4GM7WriteResFPPair<WriteVecShiftX, [C4GM7FPU02], 3>;
+defm : C4GM7WriteResFPPair<WriteVecShiftY, [C4GM7FPU02], 3>;
+defm : C4GM7WriteResFPPair<WriteVecShiftZ, [C4GM7FPU02], 3, [2], 1>;
+defm : C4GM7WriteResFPPair<WriteVecShiftImm, [C4GM7FPU02], 1>;
+defm : C4GM7WriteResFPPair<WriteVecShiftImmX, [C4GM7FPU02], 1>;
+defm : C4GM7WriteResFPPair<WriteVecShiftImmY, [C4GM7FPU02], 1>;
+defm : C4GM7WriteResFPPair<WriteVecShiftImmZ, [C4GM7FPU02], 1, [2], 1>;
+defm : C4GM7WriteResFPPair<WriteVarVecShift, [C4GM7FPU02], 1, [4], 1>;
+defm : C4GM7WriteResFPPair<WriteVarVecShiftY, [C4GM7FPU02], 1, [4], 1>;
+defm : C4GM7WriteResFPPair<WriteVarVecShiftZ, [C4GM7FPU02], 1, [8], 1>;
+defm : C4GM7WriteResFPPair<WriteVecLogic, [C4GM7FPU], 1>;
+defm : C4GM7WriteResFPPair<WriteVecLogicX, [C4GM7FPU], 1>;
+defm : C4GM7WriteResFPPair<WriteVecLogicY, [C4GM7FPU], 1>;
+defm : C4GM7WriteResFPPair<WriteVecLogicZ, [C4GM7FPU], 1>;
+defm : C4GM7WriteResFPPair<WriteVecTest, [C4GM7FPU13], 1>;
+defm : C4GM7WriteResFPPair<WriteVecTestY, [C4GM7FPU13], 1>;
+defm : C4GM7WriteResFPPair<WriteVecTestZ, [C4GM7FPU13], 1, [2], 1>;
+defm : C4GM7WriteResFPPair<WriteVecALU, [C4GM7FPU], 1>;
+defm : C4GM7WriteResFPPair<WriteVecALUX, [C4GM7FPU], 1>;
+defm : C4GM7WriteResFPPair<WriteVecALUY, [C4GM7FPU], 1>;
+defm : C4GM7WriteResFPPair<WriteVecALUZ, [C4GM7FPU], 1, [2], 1>;
+defm : C4GM7WriteResFPPair<WriteVecIMul, [C4GM7FPU02], 3>;
+defm : C4GM7WriteResFPPair<WriteVecIMulX, [C4GM7FPU02], 3>;
+defm : C4GM7WriteResFPPair<WriteVecIMulY, [C4GM7FPU02], 3>;
+defm : C4GM7WriteResFPPair<WriteVecIMulZ, [C4GM7FPU02], 3, [2], 1>;
+defm : C4GM7WriteRes<WriteCLMul, [C4GM7FPU02], 3>;
+defm : C4GM7WriteRes<WriteCLMulLd, [C4GM7AGU, C4GM7Load, C4GM7FPU02], !add(C864GM7Model.VecLoadLatency, 3)>;
+defm : C4GM7WriteResFPPair<WritePMULLD, [C4GM7FPU02], 3>;
+defm : C4GM7WriteResFPPair<WritePMULLDY, [C4GM7FPU02], 3>;
+defm : C4GM7WriteResFPPair<WritePMULLDZ, [C4GM7FPU02], 3, [2], 1>;
+defm : C4GM7WriteResFPPair<WriteShuffle, [C4GM7FPU13], 1>;
+defm : C4GM7WriteResFPPair<WriteShuffleX, [C4GM7FPU13], 1>;
+defm : C4GM7WriteResFPPair<WriteShuffleY, [C4GM7FPU13], 1>;
+defm : C4GM7WriteResFPPair<WriteShuffleZ, [C4GM7FPU13], 1, [2], 1>;
+defm : C4GM7WriteResFPPair<WriteVarShuffle, [C4GM7FPU13], 1>;
+defm : C4GM7WriteResFPPair<WriteVarShuffleX,[C4GM7FPU13], 1>;
+defm : C4GM7WriteResFPPair<WriteVarShuffleY,[C4GM7FPU13], 1>;
+defm : C4GM7WriteResFPPair<WriteVarShuffleZ,[C4GM7FPU13], 1, [2], 1>;
+defm : C4GM7WriteResFPPair<WriteBlend, [C4GM7FPU], 1>;
+defm : C4GM7WriteResFPPair<WriteBlendY, [C4GM7FPU], 1>;
+defm : C4GM7WriteResFPPair<WriteBlendZ, [C4GM7FPU], 1, [2], 1>;
+defm : C4GM7WriteResFPPair<WriteVarBlend, [C4GM7FPU], 1>;
+defm : C4GM7WriteResFPPair<WriteVarBlendY, [C4GM7FPU], 1>;
+defm : C4GM7WriteResFPPair<WriteVarBlendZ, [C4GM7FPU], 1, [2], 1>;
+defm : C4GM7WriteResFPPair<WriteShuffle256, [C4GM7FPU01], 3>;
+defm : C4GM7WriteResFPPair<WriteVPMOV256, [C4GM7FPU02], 3>;
+defm : C4GM7WriteResFPPair<WriteVarShuffle256, [C4GM7FPU3, C4GM7FPU02], 2, [2, 2], 2>;
+defm : C4GM7WriteResFPPair<WritePSADBW, [C4GM7FPU02], 3, [2], 1>;
+defm : C4GM7WriteResFPPair<WritePSADBWX, [C4GM7FPU02], 3, [2], 1>;
+defm : C4GM7WriteResFPPair<WritePSADBWY, [C4GM7FPU02], 3, [2], 1>;
+defm : C4GM7WriteResFPPair<WritePSADBWZ, [C4GM7FPU02], 3, [4], 1>;
+defm : C4GM7WriteResFPPair<WriteMPSAD, [C4GM7FPU], 4, [8], 1>;
+defm : C4GM7WriteResFPPair<WriteMPSADY, [C4GM7FPU], 4, [8], 1>;
+defm : C4GM7WriteResFPPair<WriteMPSADZ, [C4GM7FPU], 4, [16], 1>;
+defm : C4GM7WriteResFPPair<WritePHMINPOS, [C4GM7FPU02], 3, [2], 1>;
// EXTRQ INSERTQ
-def 4GM7WriteEXTRQ_INSERTQ:SchedWriteRes<[4GM7FPU]> {
+def C4GM7WriteEXTRQ_INSERTQ:SchedWriteRes<[C4GM7FPU]> {
let Latency = 3;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteEXTRQ_INSERTQ], (instrs EXTRQ, EXTRQI, INSERTQ, INSERTQI)>;
+def : InstRW<[C4GM7WriteEXTRQ_INSERTQ], (instrs EXTRQ, EXTRQI, INSERTQ, INSERTQI)>;
// VPCMP
-def 4GM7WriteVPCMPXY:SchedWriteRes<[4GM7FPU, 4GM7FPU13]> {
+def C4GM7WriteVPCMPXY:SchedWriteRes<[C4GM7FPU, C4GM7FPU13]> {
let Latency = 6;
let ReleaseAtCycles = [2, 1];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVPCMPXY], (instregex "VPCMPEQ(B|D|Q|W)(Z128|Z256)rrk$",
- "VPCMPGT(B|D|Q|W)(Z128|Z256)rrk$",
- "VPCMP(U)?(B|D|Q|W)(Z128|Z256)rrik$")>;
+def : InstRW<[C4GM7WriteVPCMPXY], (instregex "VPCMPEQ(B|D|Q|W)(Z128|Z256)rrk$",
+ "VPCMPGT(B|D|Q|W)(Z128|Z256)rrk$",
+ "VPCMP(U)?(B|D|Q|W)(Z128|Z256)rrik$")>;
-def 4GM7WriteVPCMPXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPCMPXY.Latency);
+def C4GM7WriteVPCMPXYLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPCMPXY.Latency);
let ReleaseAtCycles = [1, 1, 2, 1];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVPCMPXYLd], (instregex "VPCMPEQ(B|D|Q|W)(Z128|Z256)rmk$",
- "VPCMPGT(B|D|Q|W)(Z128|Z256)rmk$",
- "VPCMP(U)?(B|D|Q|W)(Z128|Z256)rmik$")>;
+def : InstRW<[C4GM7WriteVPCMPXYLd], (instregex "VPCMPEQ(B|D|Q|W)(Z128|Z256)rmk$",
+ "VPCMPGT(B|D|Q|W)(Z128|Z256)rmk$",
+ "VPCMP(U)?(B|D|Q|W)(Z128|Z256)rmik$")>;
-def 4GM7WriteVPCMPZ:SchedWriteRes<[4GM7FPU, 4GM7FPU13]> {
+def C4GM7WriteVPCMPZ:SchedWriteRes<[C4GM7FPU, C4GM7FPU13]> {
let Latency = 4;
let ReleaseAtCycles = [12, 6];
let NumMicroOps = 4;
}
-def : InstRW<[4GM7WriteVPCMPZ], (instregex "VPCMPEQ(B|D|Q|W)Zrrk$",
- "VPCMPGT(B|D|Q|W)Zrrk$",
- "VPCMP(U)?(B|D|Q|W)Zrrik$")>;
+def : InstRW<[C4GM7WriteVPCMPZ], (instregex "VPCMPEQ(B|D|Q|W)Zrrk$",
+ "VPCMPGT(B|D|Q|W)Zrrk$",
+ "VPCMP(U)?(B|D|Q|W)Zrrik$")>;
-def 4GM7WriteVPCMPZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPCMPZ.Latency);
+def C4GM7WriteVPCMPZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPCMPZ.Latency);
let ReleaseAtCycles = [1, 1, 12, 6];
let NumMicroOps = 4;
}
-def : InstRW<[4GM7WriteVPCMPZLd], (instregex "VPCMPEQ(B|D|Q|W)Zrmk$",
- "VPCMPGT(B|D|Q|W)Zrmk$",
- "VPCMP(U)?(B|D|Q|W)Zrmik$")>;
+def : InstRW<[C4GM7WriteVPCMPZLd], (instregex "VPCMPEQ(B|D|Q|W)Zrmk$",
+ "VPCMPGT(B|D|Q|W)Zrmk$",
+ "VPCMP(U)?(B|D|Q|W)Zrmik$")>;
// VPSHUFBIT
-def 4GM7WriteVPSHUFBIT:SchedWriteRes<[4GM7FPU02, 4GM7FPU13]> {
+def C4GM7WriteVPSHUFBIT:SchedWriteRes<[C4GM7FPU02, C4GM7FPU13]> {
let Latency = 8;
let ReleaseAtCycles = [4, 4];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVPSHUFBIT], (instrs VPSHUFBITQMBZ128rrk, VPSHUFBITQMBZ256rrk)>;
+def : InstRW<[C4GM7WriteVPSHUFBIT], (instrs VPSHUFBITQMBZ128rrk, VPSHUFBITQMBZ256rrk)>;
-def 4GM7WriteVPSHUFBITLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPSHUFBIT.Latency);
+def C4GM7WriteVPSHUFBITLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPSHUFBIT.Latency);
let ReleaseAtCycles = [1, 1, 4, 4];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVPSHUFBITLd], (instrs VPSHUFBITQMBZ128rmk, VPSHUFBITQMBZ256rmk)>;
+def : InstRW<[C4GM7WriteVPSHUFBITLd], (instrs VPSHUFBITQMBZ128rmk, VPSHUFBITQMBZ256rmk)>;
-def 4GM7WriteVPSHUFBITZ:SchedWriteRes<[4GM7FPU02, 4GM7FPU13]> {
+def C4GM7WriteVPSHUFBITZ:SchedWriteRes<[C4GM7FPU02, C4GM7FPU13]> {
let Latency = 10;
let ReleaseAtCycles = [8, 8];
let NumMicroOps = 4;
}
-def : InstRW<[4GM7WriteVPSHUFBITZ], (instrs VPSHUFBITQMBZrrk)>;
+def : InstRW<[C4GM7WriteVPSHUFBITZ], (instrs VPSHUFBITQMBZrrk)>;
-def 4GM7WriteVPSHUFBITZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPSHUFBITZ.Latency);
+def C4GM7WriteVPSHUFBITZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPSHUFBITZ.Latency);
let ReleaseAtCycles = [1, 1, 8, 8];
let NumMicroOps = 3;
}
-def : InstRW<[4GM7WriteVPSHUFBITZLd], (instrs VPSHUFBITQMBZrmk)>;
+def : InstRW<[C4GM7WriteVPSHUFBITZLd], (instrs VPSHUFBITQMBZrmk)>;
// VSHUF VPSHUFB VPSHUFLW VPSHUFHW
-def 4GM7WriteVPSHUFXY:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteVPSHUFXY:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 2;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPSHUFXY], (instrs VSHUFPSZ128rrik, VSHUFPDZ128rrik,
- VSHUFPSZ256rrik, VSHUFPDZ256rrik,
- VPSHUFBZ128rrk, VPSHUFBZ128rrkz,
- VPSHUFHWZ128rik, VPSHUFHWZ128rikz,
- VPSHUFLWZ128rik, VPSHUFLWZ128rikz,
- VPSHUFBZ256rrk, VPSHUFBZ256rrkz,
- VPSHUFHWZ256rik, VPSHUFHWZ256rikz,
- VPSHUFLWZ256rik, VPSHUFLWZ256rikz)>;
+def : InstRW<[C4GM7WriteVPSHUFXY], (instrs VSHUFPSZ128rrik, VSHUFPDZ128rrik,
+ VSHUFPSZ256rrik, VSHUFPDZ256rrik,
+ VPSHUFBZ128rrk, VPSHUFBZ128rrkz,
+ VPSHUFHWZ128rik, VPSHUFHWZ128rikz,
+ VPSHUFLWZ128rik, VPSHUFLWZ128rikz,
+ VPSHUFBZ256rrk, VPSHUFBZ256rrkz,
+ VPSHUFHWZ256rik, VPSHUFHWZ256rikz,
+ VPSHUFLWZ256rik, VPSHUFLWZ256rikz)>;
-def 4GM7WriteVPSHUFXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPSHUFXY.Latency);
+def C4GM7WriteVPSHUFXYLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPSHUFXY.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPSHUFXYLd], (instrs VSHUFPSZ128rmik, VSHUFPDZ128rmik,
- VSHUFPSZ256rmik, VSHUFPDZ256rmik,
- VPSHUFBZ128rmk, VPSHUFBZ128rmkz,
- VPSHUFHWZ128mik, VPSHUFHWZ128mikz,
- VPSHUFLWZ128mik, VPSHUFLWZ128mikz,
- VPSHUFBZ256rmk, VPSHUFBZ256rmkz,
- VPSHUFHWZ256mik, VPSHUFHWZ256mikz,
- VPSHUFLWZ256mik, VPSHUFLWZ256mikz)>;
+def : InstRW<[C4GM7WriteVPSHUFXYLd], (instrs VSHUFPSZ128rmik, VSHUFPDZ128rmik,
+ VSHUFPSZ256rmik, VSHUFPDZ256rmik,
+ VPSHUFBZ128rmk, VPSHUFBZ128rmkz,
+ VPSHUFHWZ128mik, VPSHUFHWZ128mikz,
+ VPSHUFLWZ128mik, VPSHUFLWZ128mikz,
+ VPSHUFBZ256rmk, VPSHUFBZ256rmkz,
+ VPSHUFHWZ256mik, VPSHUFHWZ256mikz,
+ VPSHUFLWZ256mik, VPSHUFLWZ256mikz)>;
-def 4GM7WriteVPSHUFZ:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteVPSHUFZ:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPSHUFZ], (instrs VSHUFPSZrrik, VSHUFPDZrrik,
- VPSHUFBZrrk, VPSHUFBZrrkz,
- VPSHUFHWZrik, VPSHUFHWZrikz,
- VPSHUFLWZrik, VPSHUFLWZrikz)>;
+def : InstRW<[C4GM7WriteVPSHUFZ], (instrs VSHUFPSZrrik, VSHUFPDZrrik,
+ VPSHUFBZrrk, VPSHUFBZrrkz,
+ VPSHUFHWZrik, VPSHUFHWZrikz,
+ VPSHUFLWZrik, VPSHUFLWZrikz)>;
-def 4GM7WriteVPSHUFZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPSHUFZ.Latency);
+def C4GM7WriteVPSHUFZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPSHUFZ.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPSHUFZLd], (instrs VSHUFPSZrmik, VSHUFPDZrmik,
- VPSHUFBZrmk, VPSHUFBZrmkz,
- VPSHUFHWZmik, VPSHUFHWZmikz,
- VPSHUFLWZmik, VPSHUFLWZmikz)>;
+def : InstRW<[C4GM7WriteVPSHUFZLd], (instrs VSHUFPSZrmik, VSHUFPDZrmik,
+ VPSHUFBZrmk, VPSHUFBZrmkz,
+ VPSHUFHWZmik, VPSHUFHWZmikz,
+ VPSHUFLWZmik, VPSHUFLWZmikz)>;
// VSHUFF VSHUFI
-def 4GM7WriteVSHUFFY_VSHUFIY:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVSHUFFY_VSHUFIY:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 3;
let ReleaseAtCycles = [4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVSHUFFY_VSHUFIY], (instrs VSHUFF32X4Z256rrik, VSHUFF64X2Z256rrik,
- VSHUFI32X4Z256rrik, VSHUFI64X2Z256rrik)>;
+def : InstRW<[C4GM7WriteVSHUFFY_VSHUFIY], (instrs VSHUFF32X4Z256rrik, VSHUFF64X2Z256rrik,
+ VSHUFI32X4Z256rrik, VSHUFI64X2Z256rrik)>;
-def 4GM7WriteVSHUFFY_VSHUFIYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVSHUFFY_VSHUFIY.Latency);
+def C4GM7WriteVSHUFFY_VSHUFIYLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVSHUFFY_VSHUFIY.Latency);
let ReleaseAtCycles = [1, 1, 4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVSHUFFY_VSHUFIYLd], (instrs VSHUFF32X4Z256rmik, VSHUFF64X2Z256rmik,
- VSHUFI32X4Z256rmik, VSHUFI64X2Z256rmik)>;
+def : InstRW<[C4GM7WriteVSHUFFY_VSHUFIYLd], (instrs VSHUFF32X4Z256rmik, VSHUFF64X2Z256rmik,
+ VSHUFI32X4Z256rmik, VSHUFI64X2Z256rmik)>;
-def 4GM7WriteVSHUFFZ_VSHUFIZ:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVSHUFFZ_VSHUFIZ:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 3;
let ReleaseAtCycles = [8];
let NumMicroOps = 4;
}
-def : InstRW<[4GM7WriteVSHUFFZ_VSHUFIZ], (instrs VSHUFF32X4Zrri, VSHUFF32X4Zrrik, VSHUFF32X4Zrrikz,
- VSHUFF64X2Zrri, VSHUFF64X2Zrrik, VSHUFF64X2Zrrikz,
- VSHUFI32X4Zrri, VSHUFI32X4Zrrik, VSHUFI32X4Zrrikz,
- VSHUFI64X2Zrri, VSHUFI64X2Zrrik, VSHUFI64X2Zrrikz)>;
+def : InstRW<[C4GM7WriteVSHUFFZ_VSHUFIZ], (instrs VSHUFF32X4Zrri, VSHUFF32X4Zrrik, VSHUFF32X4Zrrikz,
+ VSHUFF64X2Zrri, VSHUFF64X2Zrrik, VSHUFF64X2Zrrikz,
+ VSHUFI32X4Zrri, VSHUFI32X4Zrrik, VSHUFI32X4Zrrikz,
+ VSHUFI64X2Zrri, VSHUFI64X2Zrrik, VSHUFI64X2Zrrikz)>;
-def 4GM7WriteVSHUFFZ_VSHUFIZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVSHUFFZ_VSHUFIZ.Latency);
+def C4GM7WriteVSHUFFZ_VSHUFIZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVSHUFFZ_VSHUFIZ.Latency);
let ReleaseAtCycles = [1, 1, 8];
let NumMicroOps = 4;
}
-def : InstRW<[4GM7WriteVSHUFFZ_VSHUFIZLd], (instrs VSHUFF32X4Zrmi, VSHUFF32X4Zrmik, VSHUFF32X4Zrmikz,
- VSHUFF64X2Zrmi, VSHUFF64X2Zrmik, VSHUFF64X2Zrmikz,
- VSHUFI32X4Zrmi, VSHUFI32X4Zrmik, VSHUFI32X4Zrmikz,
- VSHUFI64X2Zrmi, VSHUFI64X2Zrmik, VSHUFI64X2Zrmikz)>;
+def : InstRW<[C4GM7WriteVSHUFFZ_VSHUFIZLd], (instrs VSHUFF32X4Zrmi, VSHUFF32X4Zrmik, VSHUFF32X4Zrmikz,
+ VSHUFF64X2Zrmi, VSHUFF64X2Zrmik, VSHUFF64X2Zrmikz,
+ VSHUFI32X4Zrmi, VSHUFI32X4Zrmik, VSHUFI32X4Zrmikz,
+ VSHUFI64X2Zrmi, VSHUFI64X2Zrmik, VSHUFI64X2Zrmikz)>;
// UNPCK
-def 4GM7WriteUNPCKXY:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteUNPCKXY:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 2;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteUNPCKXY], (instrs VUNPCKLPSZ128rrk, VUNPCKLPDZ128rrk,
- VUNPCKHPSZ128rrk, VUNPCKHPDZ128rrk,
- VUNPCKLPSZ256rrk, VUNPCKLPDZ256rrk,
- VUNPCKHPSZ256rrk, VUNPCKHPDZ256rrk,
- VPUNPCKHBWZ128rrk, VPUNPCKHBWZ128rrkz,
- VPUNPCKHWDZ128rrk, VPUNPCKHWDZ128rrkz,
- VPUNPCKLBWZ128rrk, VPUNPCKLBWZ128rrkz,
- VPUNPCKLWDZ128rrk, VPUNPCKLWDZ128rrkz,
- VPUNPCKHBWZ256rrk, VPUNPCKHBWZ256rrkz,
- VPUNPCKHWDZ256rrk, VPUNPCKHWDZ256rrkz,
- VPUNPCKLBWZ256rrk, VPUNPCKLBWZ256rrkz,
- VPUNPCKLWDZ256rrk, VPUNPCKLWDZ256rrkz)>;
-
-def 4GM7WriteUNPCKXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteUNPCKXY.Latency);
+def : InstRW<[C4GM7WriteUNPCKXY], (instrs VUNPCKLPSZ128rrk, VUNPCKLPDZ128rrk,
+ VUNPCKHPSZ128rrk, VUNPCKHPDZ128rrk,
+ VUNPCKLPSZ256rrk, VUNPCKLPDZ256rrk,
+ VUNPCKHPSZ256rrk, VUNPCKHPDZ256rrk,
+ VPUNPCKHBWZ128rrk, VPUNPCKHBWZ128rrkz,
+ VPUNPCKHWDZ128rrk, VPUNPCKHWDZ128rrkz,
+ VPUNPCKLBWZ128rrk, VPUNPCKLBWZ128rrkz,
+ VPUNPCKLWDZ128rrk, VPUNPCKLWDZ128rrkz,
+ VPUNPCKHBWZ256rrk, VPUNPCKHBWZ256rrkz,
+ VPUNPCKHWDZ256rrk, VPUNPCKHWDZ256rrkz,
+ VPUNPCKLBWZ256rrk, VPUNPCKLBWZ256rrkz,
+ VPUNPCKLWDZ256rrk, VPUNPCKLWDZ256rrkz)>;
+
+def C4GM7WriteUNPCKXYLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteUNPCKXY.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteUNPCKXYLd], (instrs VUNPCKLPSZ128rmk, VUNPCKLPDZ128rmk,
- VUNPCKHPSZ128rmk, VUNPCKHPDZ128rmk,
- VUNPCKLPSZ256rmk, VUNPCKLPDZ256rmk,
- VUNPCKHPSZ256rmk, VUNPCKHPDZ256rmk,
- VPUNPCKHBWZ128rmk, VPUNPCKHBWZ128rmkz,
- VPUNPCKHWDZ128rmk, VPUNPCKHWDZ128rmkz,
- VPUNPCKLBWZ128rmk, VPUNPCKLBWZ128rmkz,
- VPUNPCKLWDZ128rmk, VPUNPCKLWDZ128rmkz,
- VPUNPCKHBWZ256rmk, VPUNPCKHBWZ256rmkz,
- VPUNPCKHWDZ256rmk, VPUNPCKHWDZ256rmkz,
- VPUNPCKLBWZ256rmk, VPUNPCKLBWZ256rmkz,
- VPUNPCKLWDZ256rmk, VPUNPCKLWDZ256rmkz)>;
+def : InstRW<[C4GM7WriteUNPCKXYLd], (instrs VUNPCKLPSZ128rmk, VUNPCKLPDZ128rmk,
+ VUNPCKHPSZ128rmk, VUNPCKHPDZ128rmk,
+ VUNPCKLPSZ256rmk, VUNPCKLPDZ256rmk,
+ VUNPCKHPSZ256rmk, VUNPCKHPDZ256rmk,
+ VPUNPCKHBWZ128rmk, VPUNPCKHBWZ128rmkz,
+ VPUNPCKHWDZ128rmk, VPUNPCKHWDZ128rmkz,
+ VPUNPCKLBWZ128rmk, VPUNPCKLBWZ128rmkz,
+ VPUNPCKLWDZ128rmk, VPUNPCKLWDZ128rmkz,
+ VPUNPCKHBWZ256rmk, VPUNPCKHBWZ256rmkz,
+ VPUNPCKHWDZ256rmk, VPUNPCKHWDZ256rmkz,
+ VPUNPCKLBWZ256rmk, VPUNPCKLBWZ256rmkz,
+ VPUNPCKLWDZ256rmk, VPUNPCKLWDZ256rmkz)>;
-def 4GM7WriteUNPCKZ:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteUNPCKZ:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteUNPCKZ], (instrs VUNPCKLPSZrrk, VUNPCKLPDZrrk,
- VUNPCKHPSZrrk, VUNPCKHPDZrrk,
- VPUNPCKHBWZrrk, VPUNPCKHBWZrrkz,
- VPUNPCKHWDZrrk, VPUNPCKHWDZrrkz,
- VPUNPCKLBWZrrk, VPUNPCKLBWZrrkz,
- VPUNPCKLWDZrrk, VPUNPCKLWDZrrkz)>;
+def : InstRW<[C4GM7WriteUNPCKZ], (instrs VUNPCKLPSZrrk, VUNPCKLPDZrrk,
+ VUNPCKHPSZrrk, VUNPCKHPDZrrk,
+ VPUNPCKHBWZrrk, VPUNPCKHBWZrrkz,
+ VPUNPCKHWDZrrk, VPUNPCKHWDZrrkz,
+ VPUNPCKLBWZrrk, VPUNPCKLBWZrrkz,
+ VPUNPCKLWDZrrk, VPUNPCKLWDZrrkz)>;
-def 4GM7WriteUNPCKZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteUNPCKZ.Latency);
+def C4GM7WriteUNPCKZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteUNPCKZ.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteUNPCKZLd], (instrs VUNPCKLPSZrmk, VUNPCKLPDZrmk,
- VUNPCKHPSZrmk, VUNPCKHPDZrmk,
- VPUNPCKHBWZrmk, VPUNPCKHBWZrmkz,
- VPUNPCKHWDZrmk, VPUNPCKHWDZrmkz,
- VPUNPCKLBWZrmk, VPUNPCKLBWZrmkz,
- VPUNPCKLWDZrmk, VPUNPCKLWDZrmkz)>;
+def : InstRW<[C4GM7WriteUNPCKZLd], (instrs VUNPCKLPSZrmk, VUNPCKLPDZrmk,
+ VUNPCKHPSZrmk, VUNPCKHPDZrmk,
+ VPUNPCKHBWZrmk, VPUNPCKHBWZrmkz,
+ VPUNPCKHWDZrmk, VPUNPCKHWDZrmkz,
+ VPUNPCKLBWZrmk, VPUNPCKLBWZrmkz,
+ VPUNPCKLWDZrmk, VPUNPCKLWDZrmkz)>;
// POPCNT
-def 4GM7WritePOPCNTZ:SchedWriteRes<[4GM7FPU]> {
+def C4GM7WritePOPCNTZ:SchedWriteRes<[C4GM7FPU]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WritePOPCNTZ], (instrs VPOPCNTBZrrk, VPOPCNTBZrrkz,
- VPOPCNTWZrrk, VPOPCNTWZrrkz,
- VPOPCNTBZ128rrk, VPOPCNTBZ128rrkz,
- VPOPCNTWZ128rrk, VPOPCNTWZ128rrkz,
- VPOPCNTBZ256rrk, VPOPCNTBZ256rrkz,
- VPOPCNTWZ256rrk, VPOPCNTWZ256rrkz)>;
+def : InstRW<[C4GM7WritePOPCNTZ], (instrs VPOPCNTBZrrk, VPOPCNTBZrrkz,
+ VPOPCNTWZrrk, VPOPCNTWZrrkz,
+ VPOPCNTBZ128rrk, VPOPCNTBZ128rrkz,
+ VPOPCNTWZ128rrk, VPOPCNTWZ128rrkz,
+ VPOPCNTBZ256rrk, VPOPCNTBZ256rrkz,
+ VPOPCNTWZ256rrk, VPOPCNTWZ256rrkz)>;
-def 4GM7WritePOPCNTZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WritePOPCNTZ.Latency);
+def C4GM7WritePOPCNTZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WritePOPCNTZ.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WritePOPCNTZLd], (instrs VPOPCNTBZrmk, VPOPCNTBZrmkz,
- VPOPCNTWZrmk, VPOPCNTWZrmkz,
- VPOPCNTBZ128rmk, VPOPCNTBZ128rmkz,
- VPOPCNTWZ128rmk, VPOPCNTWZ128rmkz,
- VPOPCNTBZ256rmk, VPOPCNTBZ256rmkz,
- VPOPCNTWZ256rmk, VPOPCNTWZ256rmkz)>;
+def : InstRW<[C4GM7WritePOPCNTZLd], (instrs VPOPCNTBZrmk, VPOPCNTBZrmkz,
+ VPOPCNTWZrmk, VPOPCNTWZrmkz,
+ VPOPCNTBZ128rmk, VPOPCNTBZ128rmkz,
+ VPOPCNTWZ128rmk, VPOPCNTWZ128rmkz,
+ VPOPCNTBZ256rmk, VPOPCNTBZ256rmkz,
+ VPOPCNTWZ256rmk, VPOPCNTWZ256rmkz)>;
// VPABS VPADDS VPADDUS VPAVG VPMAX VPMIN VPADD VPSUB VPTERNLOG
-def 4GM7WriteVecALUZ:SchedWriteRes<[4GM7FPU]> {
+def C4GM7WriteVecALUZ:SchedWriteRes<[C4GM7FPU]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVecALUZ], (instregex "VPABS(B|W)Z(128|256)?rrk$",
- "VPADD(U)?S(B|W)Z(128|256)?rrk$",
- "VPAVG(B|W)Z(128|256)?rrk$",
- "VPSUB(U)?S(B|W)Z(128|256)?rrk$",
- "VPMAX(SD|UD|SB|SW|UB|UW)Z(256)?rrk$",
- "VPMIN(SD|UD|SB|SW|UB|UW)Z(256)?rrk$",
- "VPADD(B|W)Z(128)?rrk$",
- "VPADD(D|Q)Zrr(k)?",
- "VPSUB(B|W)Z(128)?rrk$",
- "VPSUB(D|Q)Zrrk$",
- "VPTERNLOG(D|Q)Zrri(k)?")>;
-
-def 4GM7WriteVecALUZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVecALUZ.Latency);
+def : InstRW<[C4GM7WriteVecALUZ], (instregex "VPABS(B|W)Z(128|256)?rrk$",
+ "VPADD(U)?S(B|W)Z(128|256)?rrk$",
+ "VPAVG(B|W)Z(128|256)?rrk$",
+ "VPSUB(U)?S(B|W)Z(128|256)?rrk$",
+ "VPMAX(SD|UD|SB|SW|UB|UW)Z(256)?rrk$",
+ "VPMIN(SD|UD|SB|SW|UB|UW)Z(256)?rrk$",
+ "VPADD(B|W)Z(128)?rrk$",
+ "VPADD(D|Q)Zrr(k)?",
+ "VPSUB(B|W)Z(128)?rrk$",
+ "VPSUB(D|Q)Zrrk$",
+ "VPTERNLOG(D|Q)Zrri(k)?")>;
+
+def C4GM7WriteVecALUZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVecALUZ.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVecALUZLd], (instregex "VPABS(B|W)Z(128|256)?rmk$",
- "VPADD(U)?S(B|W)Z(128|256)?rmk$",
- "VPAVG(B|W)Z(128|256)?rmk$",
- "VPSUB(U)?S(B|W)Z(128|256)?rmk$",
- "VPMAX(SD|UD|SB|SW|UB|UW)Z(256)?rmk$",
- "VPMIN(SD|UD|SB|SW|UB|UW)Z(256)?rmk$",
- "VPADD(B|W)Z(128)?rmk$",
- "VPADD(D|Q)Zrm(k)?$",
- "VPSUB(B|W)Z(128)?rmk$",
- "VPSUB(D|Q)Zrmk$",
- "VPTERNLOG(D|Q)Zrmi(k)?")>;
+def : InstRW<[C4GM7WriteVecALUZLd], (instregex "VPABS(B|W)Z(128|256)?rmk$",
+ "VPADD(U)?S(B|W)Z(128|256)?rmk$",
+ "VPAVG(B|W)Z(128|256)?rmk$",
+ "VPSUB(U)?S(B|W)Z(128|256)?rmk$",
+ "VPMAX(SD|UD|SB|SW|UB|UW)Z(256)?rmk$",
+ "VPMIN(SD|UD|SB|SW|UB|UW)Z(256)?rmk$",
+ "VPADD(B|W)Z(128)?rmk$",
+ "VPADD(D|Q)Zrm(k)?$",
+ "VPSUB(B|W)Z(128)?rmk$",
+ "VPSUB(D|Q)Zrmk$",
+ "VPTERNLOG(D|Q)Zrmi(k)?")>;
// WriteVecShift WriteVecShiftImm
-def 4GM7WriteVecShiftZ:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVecShiftZ:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVecShiftZ], (instrs VPSHLDDZ128rrik, VPSHLDDZ128rrikz, VPSHLDDZ256rrik,
- VPSHLDDZ256rrikz, VPSHLDDZrrik, VPSHLDDZrrikz,
- VPSHLDQZ128rrik, VPSHLDQZ128rrikz, VPSHLDQZ256rrik,
- VPSHLDQZ256rrikz, VPSHLDQZrrik, VPSHLDQZrrikz,
- VPSHLDVWZ128rk, VPSHLDVWZ128rkz, VPSHLDVWZ256rk,
- VPSHLDVWZ256rkz, VPSHLDVWZrk, VPSHLDVWZrkz,
- VPSHLDWZ128rrik, VPSHLDWZ128rrikz, VPSHLDWZ256rrik,
- VPSHLDWZ256rrikz, VPSHLDWZrrik, VPSHLDWZrrikz,
- VPSHRDDZ128rrik, VPSHRDDZ128rrikz, VPSHRDDZ256rrik,
- VPSHRDDZ256rrikz, VPSHRDDZrrik, VPSHRDDZrrikz,
- VPSHRDQZ128rrik, VPSHRDQZ128rrikz, VPSHRDQZ256rrik,
- VPSHRDQZ256rrikz, VPSHRDQZrrik, VPSHRDQZrrikz,
- VPSHRDVWZ128rk, VPSHRDVWZ128rkz, VPSHRDVWZ256rk,
- VPSHRDVWZ256rkz, VPSHRDVWZrk, VPSHRDVWZrkz,
- VPSHRDWZ128rrik, VPSHRDWZ128rrikz, VPSHRDWZ256rrik,
- VPSHRDWZ256rrikz, VPSHRDWZrrik, VPSHRDWZrrikz,
- VPSLLVWZ128rrk, VPSLLVWZ128rrkz, VPSLLVWZ256rrk,
- VPSLLVWZ256rrkz, VPSLLVWZrrk, VPSLLVWZrrkz,
- VPSLLWZ128rik, VPSLLWZ128rikz, VPSLLWZ128rrk,
- VPSLLWZ128rrkz, VPSLLWZ256rik, VPSLLWZ256rikz,
- VPSLLWZrik, VPSLLWZrikz, VPSRAVWZ128rrk,
- VPSRAVWZ128rrkz, VPSRAVWZ256rrk, VPSRAVWZ256rrkz,
- VPSRAVWZrrk, VPSRAVWZrrkz, VPSRAWZ128rik,
- VPSRAWZ128rikz, VPSRAWZ128rrk, VPSRAWZ128rrkz,
- VPSRAWZ256rik, VPSRAWZ256rikz, VPSRAWZrik,
- VPSRAWZrikz, VPSRLVWZ128rrk, VPSRLVWZ128rrkz,
- VPSRLVWZ256rrk, VPSRLVWZ256rrkz, VPSRLVWZrrk,
- VPSRLVWZrrkz, VPSRLWZ128rik, VPSRLWZ128rikz,
- VPSRLWZ128rrk, VPSRLWZ128rrkz, VPSRLWZ256rik,
- VPSRLWZ256rikz, VPSRLWZrik, VPSRLWZrikz)>;
-
-def 4GM7WriteVecShiftZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVecShiftZ.Latency);
+def : InstRW<[C4GM7WriteVecShiftZ], (instrs VPSHLDDZ128rrik, VPSHLDDZ128rrikz, VPSHLDDZ256rrik,
+ VPSHLDDZ256rrikz, VPSHLDDZrrik, VPSHLDDZrrikz,
+ VPSHLDQZ128rrik, VPSHLDQZ128rrikz, VPSHLDQZ256rrik,
+ VPSHLDQZ256rrikz, VPSHLDQZrrik, VPSHLDQZrrikz,
+ VPSHLDVWZ128rk, VPSHLDVWZ128rkz, VPSHLDVWZ256rk,
+ VPSHLDVWZ256rkz, VPSHLDVWZrk, VPSHLDVWZrkz,
+ VPSHLDWZ128rrik, VPSHLDWZ128rrikz, VPSHLDWZ256rrik,
+ VPSHLDWZ256rrikz, VPSHLDWZrrik, VPSHLDWZrrikz,
+ VPSHRDDZ128rrik, VPSHRDDZ128rrikz, VPSHRDDZ256rrik,
+ VPSHRDDZ256rrikz, VPSHRDDZrrik, VPSHRDDZrrikz,
+ VPSHRDQZ128rrik, VPSHRDQZ128rrikz, VPSHRDQZ256rrik,
+ VPSHRDQZ256rrikz, VPSHRDQZrrik, VPSHRDQZrrikz,
+ VPSHRDVWZ128rk, VPSHRDVWZ128rkz, VPSHRDVWZ256rk,
+ VPSHRDVWZ256rkz, VPSHRDVWZrk, VPSHRDVWZrkz,
+ VPSHRDWZ128rrik, VPSHRDWZ128rrikz, VPSHRDWZ256rrik,
+ VPSHRDWZ256rrikz, VPSHRDWZrrik, VPSHRDWZrrikz,
+ VPSLLVWZ128rrk, VPSLLVWZ128rrkz, VPSLLVWZ256rrk,
+ VPSLLVWZ256rrkz, VPSLLVWZrrk, VPSLLVWZrrkz,
+ VPSLLWZ128rik, VPSLLWZ128rikz, VPSLLWZ128rrk,
+ VPSLLWZ128rrkz, VPSLLWZ256rik, VPSLLWZ256rikz,
+ VPSLLWZrik, VPSLLWZrikz, VPSRAVWZ128rrk,
+ VPSRAVWZ128rrkz, VPSRAVWZ256rrk, VPSRAVWZ256rrkz,
+ VPSRAVWZrrk, VPSRAVWZrrkz, VPSRAWZ128rik,
+ VPSRAWZ128rikz, VPSRAWZ128rrk, VPSRAWZ128rrkz,
+ VPSRAWZ256rik, VPSRAWZ256rikz, VPSRAWZrik,
+ VPSRAWZrikz, VPSRLVWZ128rrk, VPSRLVWZ128rrkz,
+ VPSRLVWZ256rrk, VPSRLVWZ256rrkz, VPSRLVWZrrk,
+ VPSRLVWZrrkz, VPSRLWZ128rik, VPSRLWZ128rikz,
+ VPSRLWZ128rrk, VPSRLWZ128rrkz, VPSRLWZ256rik,
+ VPSRLWZ256rikz, VPSRLWZrik, VPSRLWZrikz)>;
+
+def C4GM7WriteVecShiftZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVecShiftZ.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVecShiftZLd], (instrs VPSHLDDZ128rmik, VPSHLDDZ128rmikz, VPSHLDDZ256rmik,
- VPSHLDDZ256rmikz, VPSHLDDZrmik, VPSHLDDZrmikz,
- VPSHLDQZ128rmik, VPSHLDQZ128rmikz, VPSHLDQZ256rmik,
- VPSHLDQZ256rmikz, VPSHLDQZrmik, VPSHLDQZrmikz,
- VPSHLDVWZ128mk, VPSHLDVWZ128mkz, VPSHLDVWZ256mk,
- VPSHLDVWZ256mkz, VPSHLDVWZmk, VPSHLDVWZmkz,
- VPSHLDWZ128rmik, VPSHLDWZ128rmikz, VPSHLDWZ256rmik,
- VPSHLDWZ256rmikz, VPSHLDWZrmik, VPSHLDWZrmikz,
- VPSHRDDZ128rmik, VPSHRDDZ128rmikz, VPSHRDDZ256rmik,
- VPSHRDDZ256rmikz, VPSHRDDZrmik, VPSHRDDZrmikz,
- VPSHRDQZ128rmik, VPSHRDQZ128rmikz, VPSHRDQZ256rmik,
- VPSHRDQZ256rmikz, VPSHRDQZrmik, VPSHRDQZrmikz,
- VPSHRDVWZ128mk, VPSHRDVWZ128mkz, VPSHRDVWZ256mk,
- VPSHRDVWZ256mkz, VPSHRDVWZmk, VPSHRDVWZmkz,
- VPSHRDWZ128rmik, VPSHRDWZ128rmikz, VPSHRDWZ256rmik,
- VPSHRDWZ256rmikz, VPSHRDWZrmik, VPSHRDWZrmikz,
- VPSLLVWZ128rmk, VPSLLVWZ128rmkz, VPSLLVWZ256rmk,
- VPSLLVWZ256rmkz, VPSLLVWZrmk, VPSLLVWZrmkz,
- VPSLLWZ128mik, VPSLLWZ128mikz, VPSLLWZ128rmk,
- VPSLLWZ128rmkz, VPSLLWZ256mik, VPSLLWZ256mikz,
- VPSLLWZmik, VPSLLWZmikz, VPSRAVWZ128rmk,
- VPSRAVWZ128rmkz, VPSRAVWZ256rmk, VPSRAVWZ256rmkz,
- VPSRAVWZrmk, VPSRAVWZrmkz, VPSRAWZ128mik,
- VPSRAWZ128mikz, VPSRAWZ128rmk, VPSRAWZ128rmkz,
- VPSRAWZ256mik, VPSRAWZ256mikz, VPSRAWZmik,
- VPSRAWZmikz, VPSRLVWZ128rmk, VPSRLVWZ128rmkz,
- VPSRLVWZ256rmk, VPSRLVWZ256rmkz, VPSRLVWZrmk,
- VPSRLVWZrmkz, VPSRLWZ128mik, VPSRLWZ128mikz,
- VPSRLWZ128rmk, VPSRLWZ128rmkz, VPSRLWZ256mik,
- VPSRLWZ256mikz, VPSRLWZmik, VPSRLWZmikz)>;
-
-def 4GM7WriteVecShiftZrrk:SchedWriteRes<[4GM7FPU02]> {
+def : InstRW<[C4GM7WriteVecShiftZLd], (instrs VPSHLDDZ128rmik, VPSHLDDZ128rmikz, VPSHLDDZ256rmik,
+ VPSHLDDZ256rmikz, VPSHLDDZrmik, VPSHLDDZrmikz,
+ VPSHLDQZ128rmik, VPSHLDQZ128rmikz, VPSHLDQZ256rmik,
+ VPSHLDQZ256rmikz, VPSHLDQZrmik, VPSHLDQZrmikz,
+ VPSHLDVWZ128mk, VPSHLDVWZ128mkz, VPSHLDVWZ256mk,
+ VPSHLDVWZ256mkz, VPSHLDVWZmk, VPSHLDVWZmkz,
+ VPSHLDWZ128rmik, VPSHLDWZ128rmikz, VPSHLDWZ256rmik,
+ VPSHLDWZ256rmikz, VPSHLDWZrmik, VPSHLDWZrmikz,
+ VPSHRDDZ128rmik, VPSHRDDZ128rmikz, VPSHRDDZ256rmik,
+ VPSHRDDZ256rmikz, VPSHRDDZrmik, VPSHRDDZrmikz,
+ VPSHRDQZ128rmik, VPSHRDQZ128rmikz, VPSHRDQZ256rmik,
+ VPSHRDQZ256rmikz, VPSHRDQZrmik, VPSHRDQZrmikz,
+ VPSHRDVWZ128mk, VPSHRDVWZ128mkz, VPSHRDVWZ256mk,
+ VPSHRDVWZ256mkz, VPSHRDVWZmk, VPSHRDVWZmkz,
+ VPSHRDWZ128rmik, VPSHRDWZ128rmikz, VPSHRDWZ256rmik,
+ VPSHRDWZ256rmikz, VPSHRDWZrmik, VPSHRDWZrmikz,
+ VPSLLVWZ128rmk, VPSLLVWZ128rmkz, VPSLLVWZ256rmk,
+ VPSLLVWZ256rmkz, VPSLLVWZrmk, VPSLLVWZrmkz,
+ VPSLLWZ128mik, VPSLLWZ128mikz, VPSLLWZ128rmk,
+ VPSLLWZ128rmkz, VPSLLWZ256mik, VPSLLWZ256mikz,
+ VPSLLWZmik, VPSLLWZmikz, VPSRAVWZ128rmk,
+ VPSRAVWZ128rmkz, VPSRAVWZ256rmk, VPSRAVWZ256rmkz,
+ VPSRAVWZrmk, VPSRAVWZrmkz, VPSRAWZ128mik,
+ VPSRAWZ128mikz, VPSRAWZ128rmk, VPSRAWZ128rmkz,
+ VPSRAWZ256mik, VPSRAWZ256mikz, VPSRAWZmik,
+ VPSRAWZmikz, VPSRLVWZ128rmk, VPSRLVWZ128rmkz,
+ VPSRLVWZ256rmk, VPSRLVWZ256rmkz, VPSRLVWZrmk,
+ VPSRLVWZrmkz, VPSRLWZ128mik, VPSRLWZ128mikz,
+ VPSRLWZ128rmk, VPSRLWZ128rmkz, VPSRLWZ256mik,
+ VPSRLWZ256mikz, VPSRLWZmik, VPSRLWZmikz)>;
+
+def C4GM7WriteVecShiftZrrk:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVecShiftZrrk], (instrs VPSLLDZrrk, VPSLLQZrrk, VPSRADZrrk,
- VPSRAQZrrk, VPSRLDZrrk, VPSRLQZrrk,
- VPSLLWZrrk, VPSRAWZrrk, VPSRLWZrrk,
- VPSLLDZ256rrk, VPSLLQZ256rrk, VPSRADZ256rrk,
- VPSRAQZ256rrk, VPSRLDZ256rrk, VPSRLQZ256rrk,
- VPSLLWZ256rrk, VPSRAWZ256rrk, VPSRLWZ256rrk)>;
+def : InstRW<[C4GM7WriteVecShiftZrrk], (instrs VPSLLDZrrk, VPSLLQZrrk, VPSRADZrrk,
+ VPSRAQZrrk, VPSRLDZrrk, VPSRLQZrrk,
+ VPSLLWZrrk, VPSRAWZrrk, VPSRLWZrrk,
+ VPSLLDZ256rrk, VPSLLQZ256rrk, VPSRADZ256rrk,
+ VPSRAQZ256rrk, VPSRLDZ256rrk, VPSRLQZ256rrk,
+ VPSLLWZ256rrk, VPSRAWZ256rrk, VPSRLWZ256rrk)>;
-def 4GM7WriteVecShiftZrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVecShiftZrrk.Latency);
+def C4GM7WriteVecShiftZrmk:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVecShiftZrrk.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVecShiftZrmk], (instrs VPSLLDZrmk, VPSLLQZrmk, VPSRADZrmk,
- VPSRAQZrmk, VPSRLDZrmk, VPSRLQZrmk,
- VPSLLWZrmk, VPSRAWZrmk, VPSRLWZrmk,
- VPSLLDZ256rmk, VPSLLQZ256rmk, VPSRADZ256rmk,
- VPSRAQZ256rmk, VPSRLDZ256rmk, VPSRLQZ256rmk,
- VPSLLWZ256rmk, VPSRAWZ256rmk, VPSRLWZ256rmk)>;
+def : InstRW<[C4GM7WriteVecShiftZrmk], (instrs VPSLLDZrmk, VPSLLQZrmk, VPSRADZrmk,
+ VPSRAQZrmk, VPSRLDZrmk, VPSRLQZrmk,
+ VPSLLWZrmk, VPSRAWZrmk, VPSRLWZrmk,
+ VPSLLDZ256rmk, VPSLLQZ256rmk, VPSRADZ256rmk,
+ VPSRAQZ256rmk, VPSRLDZ256rmk, VPSRLQZ256rmk,
+ VPSLLWZ256rmk, VPSRAWZ256rmk, VPSRLWZ256rmk)>;
-def 4GM7WriteVecShift:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVecShift:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 1;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVecShift], (instrs PSLLDrr, PSLLQrr, PSLLWrr, PSRADrr,
- PSRAWrr, PSRLDrr,PSRLQrr, PSRLWrr,
- VPSHLDDZ128rri, VPSHLDDZ256rri, VPSHLDDZrri,
- VPSHLDQZ128rri, VPSHLDQZ256rri, VPSHLDQZrri,
- VPSHLDVDZ128r, VPSHLDVDZ128rk, VPSHLDVDZ128rkz,
- VPSHLDVDZ256r, VPSHLDVDZ256rk, VPSHLDVDZ256rkz,
- VPSHLDVDZr, VPSHLDVDZrk, VPSHLDVDZrkz,
- VPSHLDVQZ128r, VPSHLDVQZ128rk, VPSHLDVQZ128rkz,
- VPSHLDVQZ256r, VPSHLDVQZ256rk, VPSHLDVQZ256rkz,
- VPSHLDVQZr, VPSHLDVQZrk, VPSHLDVQZrkz,
- VPSHLDVWZ128r, VPSHLDVWZ256r, VPSHLDVWZr,
- VPSHLDWZ128rri, VPSHLDWZ256rri, VPSHLDWZrri,
- VPSHRDDZ128rri, VPSHRDDZ256rri, VPSHRDDZrri,
- VPSHRDQZ128rri, VPSHRDQZ256rri, VPSHRDQZrri,
- VPSHRDVDZ128r, VPSHRDVDZ128rk, VPSHRDVDZ128rkz,
- VPSHRDVDZ256r, VPSHRDVDZ256rk, VPSHRDVDZ256rkz,
- VPSHRDVDZr, VPSHRDVDZrk, VPSHRDVDZrkz,
- VPSHRDVQZ128r, VPSHRDVQZ128rk, VPSHRDVQZ128rkz,
- VPSHRDVQZ256r, VPSHRDVQZ256rk, VPSHRDVQZ256rkz,
- VPSHRDVQZr, VPSHRDVQZrk, VPSHRDVQZrkz,
- VPSHRDVWZ128r, VPSHRDVWZ256r, VPSHRDVWZr,
- VPSHRDWZ128rri, VPSHRDWZ256rri, VPSHRDWZrri,
- VPSLLDrr, VPSLLDZ128rr, VPSLLDZ128rrk,
- VPSLLDZ128rrkz, VPSLLQrr, VPSLLQZ128rr,
- VPSLLQZ128rrk, VPSLLQZ128rrkz, VPSLLWrr,
- VPSLLWZ128rr, VPSRADrr, VPSRADZ128rr,
- VPSRADZ128rrk, VPSRADZ128rrkz, VPSRAQZ128rr,
- VPSRAQZ128rrk, VPSRAQZ128rrkz, VPSRAWrr,
- VPSRAWZ128rr, VPSRLDrr, VPSRLDZ128rr,
- VPSRLDZ128rrk, VPSRLDZ128rrkz, VPSRLQrr,
- VPSRLQZ128rr, VPSRLQZ128rrk, VPSRLQZ128rrkz,
- VPSRLWrr, VPSRLWZ128rr)>;
-
-def 4GM7WriteVecShiftLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVecShift.Latency);
+def : InstRW<[C4GM7WriteVecShift], (instrs PSLLDrr, PSLLQrr, PSLLWrr, PSRADrr,
+ PSRAWrr, PSRLDrr,PSRLQrr, PSRLWrr,
+ VPSHLDDZ128rri, VPSHLDDZ256rri, VPSHLDDZrri,
+ VPSHLDQZ128rri, VPSHLDQZ256rri, VPSHLDQZrri,
+ VPSHLDVDZ128r, VPSHLDVDZ128rk, VPSHLDVDZ128rkz,
+ VPSHLDVDZ256r, VPSHLDVDZ256rk, VPSHLDVDZ256rkz,
+ VPSHLDVDZr, VPSHLDVDZrk, VPSHLDVDZrkz,
+ VPSHLDVQZ128r, VPSHLDVQZ128rk, VPSHLDVQZ128rkz,
+ VPSHLDVQZ256r, VPSHLDVQZ256rk, VPSHLDVQZ256rkz,
+ VPSHLDVQZr, VPSHLDVQZrk, VPSHLDVQZrkz,
+ VPSHLDVWZ128r, VPSHLDVWZ256r, VPSHLDVWZr,
+ VPSHLDWZ128rri, VPSHLDWZ256rri, VPSHLDWZrri,
+ VPSHRDDZ128rri, VPSHRDDZ256rri, VPSHRDDZrri,
+ VPSHRDQZ128rri, VPSHRDQZ256rri, VPSHRDQZrri,
+ VPSHRDVDZ128r, VPSHRDVDZ128rk, VPSHRDVDZ128rkz,
+ VPSHRDVDZ256r, VPSHRDVDZ256rk, VPSHRDVDZ256rkz,
+ VPSHRDVDZr, VPSHRDVDZrk, VPSHRDVDZrkz,
+ VPSHRDVQZ128r, VPSHRDVQZ128rk, VPSHRDVQZ128rkz,
+ VPSHRDVQZ256r, VPSHRDVQZ256rk, VPSHRDVQZ256rkz,
+ VPSHRDVQZr, VPSHRDVQZrk, VPSHRDVQZrkz,
+ VPSHRDVWZ128r, VPSHRDVWZ256r, VPSHRDVWZr,
+ VPSHRDWZ128rri, VPSHRDWZ256rri, VPSHRDWZrri,
+ VPSLLDrr, VPSLLDZ128rr, VPSLLDZ128rrk,
+ VPSLLDZ128rrkz, VPSLLQrr, VPSLLQZ128rr,
+ VPSLLQZ128rrk, VPSLLQZ128rrkz, VPSLLWrr,
+ VPSLLWZ128rr, VPSRADrr, VPSRADZ128rr,
+ VPSRADZ128rrk, VPSRADZ128rrkz, VPSRAQZ128rr,
+ VPSRAQZ128rrk, VPSRAQZ128rrkz, VPSRAWrr,
+ VPSRAWZ128rr, VPSRLDrr, VPSRLDZ128rr,
+ VPSRLDZ128rrk, VPSRLDZ128rrkz, VPSRLQrr,
+ VPSRLQZ128rr, VPSRLQZ128rrk, VPSRLQZ128rrkz,
+ VPSRLWrr, VPSRLWZ128rr)>;
+
+def C4GM7WriteVecShiftLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVecShift.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVecShiftLd], (instrs PSLLDrm, PSLLQrm, PSLLWrm, PSRADrm,
- PSRAWrm, PSRLDrm,PSRLQrm, PSRLWrm,
- VPSHLDDZ128rmi, VPSHLDDZ256rmi, VPSHLDDZrmi,
- VPSHLDQZ128rmi, VPSHLDQZ256rmi, VPSHLDQZrmi,
- VPSHLDVDZ128m, VPSHLDVDZ128mk, VPSHLDVDZ128mkz,
- VPSHLDVDZ256m, VPSHLDVDZ256mk, VPSHLDVDZ256mkz,
- VPSHLDVDZm, VPSHLDVDZmk, VPSHLDVDZmkz,
- VPSHLDVQZ128m, VPSHLDVQZ128mk, VPSHLDVQZ128mkz,
- VPSHLDVQZ256m, VPSHLDVQZ256mk, VPSHLDVQZ256mkz,
- VPSHLDVQZm, VPSHLDVQZmk, VPSHLDVQZmkz,
- VPSHLDVWZ128m, VPSHLDVWZ256m, VPSHLDVWZm,
- VPSHLDWZ128rmi, VPSHLDWZ256rmi, VPSHLDWZrmi,
- VPSHRDDZ128rmi, VPSHRDDZ256rmi, VPSHRDDZrmi,
- VPSHRDQZ128rmi, VPSHRDQZ256rmi, VPSHRDQZrmi,
- VPSHRDVDZ128m, VPSHRDVDZ128mk, VPSHRDVDZ128mkz,
- VPSHRDVDZ256m, VPSHRDVDZ256mk, VPSHRDVDZ256mkz,
- VPSHRDVDZm, VPSHRDVDZmk, VPSHRDVDZmkz,
- VPSHRDVQZ128m, VPSHRDVQZ128mk, VPSHRDVQZ128mkz,
- VPSHRDVQZ256m, VPSHRDVQZ256mk, VPSHRDVQZ256mkz,
- VPSHRDVQZm, VPSHRDVQZmk, VPSHRDVQZmkz,
- VPSHRDVWZ128m, VPSHRDVWZ256m, VPSHRDVWZm,
- VPSHRDWZ128rmi, VPSHRDWZ256rmi, VPSHRDWZrmi,
- VPSLLDrm, VPSLLDZ128rm, VPSLLDZ128rmk,
- VPSLLDZ128rmkz, VPSLLQrm, VPSLLQZ128rm,
- VPSLLQZ128rmk, VPSLLQZ128rmkz, VPSLLWrm,
- VPSLLWZ128rm, VPSRADrm, VPSRADZ128rm,
- VPSRADZ128rmk, VPSRADZ128rmkz, VPSRAQZ128rm,
- VPSRAQZ128rmk, VPSRAQZ128rmkz, VPSRAWrm,
- VPSRAWZ128rm, VPSRLDrm, VPSRLDZ128rm,
- VPSRLDZ128rmk, VPSRLDZ128rmkz, VPSRLQrm,
- VPSRLQZ128rm, VPSRLQZ128rmk, VPSRLQZ128rmkz,
- VPSRLWrm, VPSRLWZ128rm)>;
+def : InstRW<[C4GM7WriteVecShiftLd], (instrs PSLLDrm, PSLLQrm, PSLLWrm, PSRADrm,
+ PSRAWrm, PSRLDrm,PSRLQrm, PSRLWrm,
+ VPSHLDDZ128rmi, VPSHLDDZ256rmi, VPSHLDDZrmi,
+ VPSHLDQZ128rmi, VPSHLDQZ256rmi, VPSHLDQZrmi,
+ VPSHLDVDZ128m, VPSHLDVDZ128mk, VPSHLDVDZ128mkz,
+ VPSHLDVDZ256m, VPSHLDVDZ256mk, VPSHLDVDZ256mkz,
+ VPSHLDVDZm, VPSHLDVDZmk, VPSHLDVDZmkz,
+ VPSHLDVQZ128m, VPSHLDVQZ128mk, VPSHLDVQZ128mkz,
+ VPSHLDVQZ256m, VPSHLDVQZ256mk, VPSHLDVQZ256mkz,
+ VPSHLDVQZm, VPSHLDVQZmk, VPSHLDVQZmkz,
+ VPSHLDVWZ128m, VPSHLDVWZ256m, VPSHLDVWZm,
+ VPSHLDWZ128rmi, VPSHLDWZ256rmi, VPSHLDWZrmi,
+ VPSHRDDZ128rmi, VPSHRDDZ256rmi, VPSHRDDZrmi,
+ VPSHRDQZ128rmi, VPSHRDQZ256rmi, VPSHRDQZrmi,
+ VPSHRDVDZ128m, VPSHRDVDZ128mk, VPSHRDVDZ128mkz,
+ VPSHRDVDZ256m, VPSHRDVDZ256mk, VPSHRDVDZ256mkz,
+ VPSHRDVDZm, VPSHRDVDZmk, VPSHRDVDZmkz,
+ VPSHRDVQZ128m, VPSHRDVQZ128mk, VPSHRDVQZ128mkz,
+ VPSHRDVQZ256m, VPSHRDVQZ256mk, VPSHRDVQZ256mkz,
+ VPSHRDVQZm, VPSHRDVQZmk, VPSHRDVQZmkz,
+ VPSHRDVWZ128m, VPSHRDVWZ256m, VPSHRDVWZm,
+ VPSHRDWZ128rmi, VPSHRDWZ256rmi, VPSHRDWZrmi,
+ VPSLLDrm, VPSLLDZ128rm, VPSLLDZ128rmk,
+ VPSLLDZ128rmkz, VPSLLQrm, VPSLLQZ128rm,
+ VPSLLQZ128rmk, VPSLLQZ128rmkz, VPSLLWrm,
+ VPSLLWZ128rm, VPSRADrm, VPSRADZ128rm,
+ VPSRADZ128rmk, VPSRADZ128rmkz, VPSRAQZ128rm,
+ VPSRAQZ128rmk, VPSRAQZ128rmkz, VPSRAWrm,
+ VPSRAWZ128rm, VPSRLDrm, VPSRLDZ128rm,
+ VPSRLDZ128rmk, VPSRLDZ128rmkz, VPSRLQrm,
+ VPSRLQZ128rm, VPSRLQZ128rmk, VPSRLQZ128rmkz,
+ VPSRLWrm, VPSRLWZ128rm)>;
// VCMP
-def 4GM7WriteVCMPXY:SchedWriteRes<[4GM7FPU02, 4GM7FPU13]> {
+def C4GM7WriteVCMPXY:SchedWriteRes<[C4GM7FPU02, C4GM7FPU13]> {
let Latency = 5;
let ReleaseAtCycles = [1, 1];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVCMPXY], (instrs VCMPPDZ128rrik, VCMPPSZ128rrik,
- VCMPPDZ256rrik, VCMPPSZ256rrik)>;
+def : InstRW<[C4GM7WriteVCMPXY], (instrs VCMPPDZ128rrik, VCMPPSZ128rrik,
+ VCMPPDZ256rrik, VCMPPSZ256rrik)>;
-def 4GM7WriteVCMPXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVCMPXY.Latency);
+def C4GM7WriteVCMPXYLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVCMPXY.Latency);
let ReleaseAtCycles = [1, 1, 1, 1];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVCMPXYLd], (instrs VCMPPDZ128rmik, VCMPPSZ128rmik,
+def : InstRW<[C4GM7WriteVCMPXYLd], (instrs VCMPPDZ128rmik, VCMPPSZ128rmik,
VCMPPDZ256rmik, VCMPPSZ256rmik)>;
-def 4GM7WriteVCMPZ:SchedWriteRes<[4GM7FPU02, 4GM7FPU13]> {
+def C4GM7WriteVCMPZ:SchedWriteRes<[C4GM7FPU02, C4GM7FPU13]> {
let Latency = 5;
let ReleaseAtCycles = [10, 10];
let NumMicroOps = 4;
}
-def : InstRW<[4GM7WriteVCMPZ], (instrs VCMPPSZrribk, VCMPPSZrrik,
- VCMPPDZrribk, VCMPPDZrrik,
- VCMPSSZrrik_Int, VCMPSSZrribk_Int,
- VCMPSDZrribk_Int, VCMPSDZrrik_Int)>;
+def : InstRW<[C4GM7WriteVCMPZ], (instrs VCMPPSZrribk, VCMPPSZrrik,
+ VCMPPDZrribk, VCMPPDZrrik,
+ VCMPSSZrrik_Int, VCMPSSZrribk_Int,
+ VCMPSDZrribk_Int, VCMPSDZrrik_Int)>;
-def 4GM7WriteVCMPZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVCMPZ.Latency);
+def C4GM7WriteVCMPZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVCMPZ.Latency);
let ReleaseAtCycles = [1, 1, 10, 10];
let NumMicroOps = 4;
}
-def : InstRW<[4GM7WriteVCMPZLd], (instrs VCMPPSZrmik, VCMPPDZrmik,
- VCMPSSZrmik_Int, VCMPSDZrmik_Int)>;
+def : InstRW<[C4GM7WriteVCMPZLd], (instrs VCMPPSZrmik, VCMPPDZrmik,
+ VCMPSSZrmik_Int, VCMPSDZrmik_Int)>;
// VFPCLASS
-def 4GM7WriteVFPCLASSXY:SchedWriteRes<[4GM7FPU13, 4GM7FPU13]> {
+def C4GM7WriteVFPCLASSXY:SchedWriteRes<[C4GM7FPU13, C4GM7FPU13]> {
let Latency = 5;
let ReleaseAtCycles = [2, 2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVFPCLASSXY], (instrs VFPCLASSPDZ128rik, VFPCLASSPSZ128rik,
- VFPCLASSPDZ256rik, VFPCLASSPSZ256rik)>;
+def : InstRW<[C4GM7WriteVFPCLASSXY], (instrs VFPCLASSPDZ128rik, VFPCLASSPSZ128rik,
+ VFPCLASSPDZ256rik, VFPCLASSPSZ256rik)>;
-def 4GM7WriteVFPCLASSXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVFPCLASSXY.Latency);
+def C4GM7WriteVFPCLASSXYLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVFPCLASSXY.Latency);
let ReleaseAtCycles = [1, 1, 2, 2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVFPCLASSXYLd], (instrs VFPCLASSPDZ128mik, VFPCLASSPSZ128mik,
- VFPCLASSPDZ256mik, VFPCLASSPSZ256mik)>;
+def : InstRW<[C4GM7WriteVFPCLASSXYLd], (instrs VFPCLASSPDZ128mik, VFPCLASSPSZ128mik,
+ VFPCLASSPDZ256mik, VFPCLASSPSZ256mik)>;
-def 4GM7WriteVFPCLASSZ:SchedWriteRes<[4GM7FPU13, 4GM7FPU13]> {
+def C4GM7WriteVFPCLASSZ:SchedWriteRes<[C4GM7FPU13, C4GM7FPU13]> {
let Latency = 5;
let ReleaseAtCycles = [4, 4];
let NumMicroOps = 4;
}
-def : InstRW<[4GM7WriteVFPCLASSZ], (instrs VFPCLASSSDZrik, VFPCLASSSSZrik)>;
+def : InstRW<[C4GM7WriteVFPCLASSZ], (instrs VFPCLASSSDZrik, VFPCLASSSSZrik)>;
-def 4GM7WriteVFPCLASSZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVFPCLASSZ.Latency);
+def C4GM7WriteVFPCLASSZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVFPCLASSZ.Latency);
let ReleaseAtCycles = [1, 1, 4, 4];
let NumMicroOps = 4;
}
-def : InstRW<[4GM7WriteVFPCLASSZLd], (instrs VFPCLASSSDZmik, VFPCLASSSSZmik)>;
+def : InstRW<[C4GM7WriteVFPCLASSZLd], (instrs VFPCLASSSDZmik, VFPCLASSSSZmik)>;
-def 4GM7WriteVFPCLASSZrik:SchedWriteRes<[4GM7FPU13, 4GM7FPU13]> {
+def C4GM7WriteVFPCLASSZrik:SchedWriteRes<[C4GM7FPU13, C4GM7FPU13]> {
let Latency = 4;
let ReleaseAtCycles = [4, 4];
let NumMicroOps = 4;
}
-def : InstRW<[4GM7WriteVFPCLASSZrik], (instrs VFPCLASSPDZrik, VFPCLASSPSZrik)>;
+def : InstRW<[C4GM7WriteVFPCLASSZrik], (instrs VFPCLASSPDZrik, VFPCLASSPSZrik)>;
-def 4GM7WriteVFPCLASSZrikLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVFPCLASSZrik.Latency);
+def C4GM7WriteVFPCLASSZrikLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVFPCLASSZrik.Latency);
let ReleaseAtCycles = [1, 1, 4, 4];
let NumMicroOps = 4;
}
-def : InstRW<[4GM7WriteVFPCLASSZrikLd], (instrs VFPCLASSPDZmik, VFPCLASSPSZmik)>;
+def : InstRW<[C4GM7WriteVFPCLASSZrikLd], (instrs VFPCLASSPDZmik, VFPCLASSPSZmik)>;
// VRNDSCALE
-def 4GM7WriteVRNDSCALEXY:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteVRNDSCALEXY:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 5;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVRNDSCALEXY], (instrs VRNDSCALEPDZ128rrik, VRNDSCALEPSZ128rrik,
- VRNDSCALEPDZ256rrik, VRNDSCALEPSZ256rrik)>;
+def : InstRW<[C4GM7WriteVRNDSCALEXY], (instrs VRNDSCALEPDZ128rrik, VRNDSCALEPSZ128rrik,
+ VRNDSCALEPDZ256rrik, VRNDSCALEPSZ256rrik)>;
-def 4GM7WriteVRNDSCALEXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVRNDSCALEXY.Latency);
+def C4GM7WriteVRNDSCALEXYLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVRNDSCALEXY.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVRNDSCALEXYLd], (instrs VRNDSCALEPDZ128rmik, VRNDSCALEPSZ128rmik,
- VRNDSCALEPDZ256rmik, VRNDSCALEPSZ256rmik)>;
+def : InstRW<[C4GM7WriteVRNDSCALEXYLd], (instrs VRNDSCALEPDZ128rmik, VRNDSCALEPSZ128rmik,
+ VRNDSCALEPDZ256rmik, VRNDSCALEPSZ256rmik)>;
-def 4GM7WriteVRNDSCALEZ:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteVRNDSCALEZ:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 5;
let ReleaseAtCycles = [2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVRNDSCALEZ], (instrs VRNDSCALESDZrribk_Int, VRNDSCALESDZrrik_Int,
- VRNDSCALESSZrribk_Int, VRNDSCALESSZrrik_Int,
- VRNDSCALEPDZrribk, VRNDSCALEPDZrrik,
- VRNDSCALEPSZrribk, VRNDSCALEPSZrrik)>;
+def : InstRW<[C4GM7WriteVRNDSCALEZ], (instrs VRNDSCALESDZrribk_Int, VRNDSCALESDZrrik_Int,
+ VRNDSCALESSZrribk_Int, VRNDSCALESSZrrik_Int,
+ VRNDSCALEPDZrribk, VRNDSCALEPDZrrik,
+ VRNDSCALEPSZrribk, VRNDSCALEPSZrrik)>;
-def 4GM7WriteVRNDSCALEZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVRNDSCALEZ.Latency);
+def C4GM7WriteVRNDSCALEZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVRNDSCALEZ.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVRNDSCALEZLd], (instrs VRNDSCALESDZrmik_Int, VRNDSCALESSZrmik_Int,
- VRNDSCALEPDZrmik, VRNDSCALEPSZrmik)>;
+def : InstRW<[C4GM7WriteVRNDSCALEZLd], (instrs VRNDSCALESDZrmik_Int, VRNDSCALESSZrmik_Int,
+ VRNDSCALEPDZrmik, VRNDSCALEPSZrmik)>;
// VREDUCE
-def 4GM7WriteVREDUCEXY:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteVREDUCEXY:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 5;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVREDUCEXY], (instrs VREDUCEPDZ128rrik, VREDUCEPSZ128rrik,
- VREDUCEPDZ256rrik, VREDUCEPSZ256rrik)>;
+def : InstRW<[C4GM7WriteVREDUCEXY], (instrs VREDUCEPDZ128rrik, VREDUCEPSZ128rrik,
+ VREDUCEPDZ256rrik, VREDUCEPSZ256rrik)>;
-def 4GM7WriteVREDUCEXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVREDUCEXY.Latency);
+def C4GM7WriteVREDUCEXYLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVREDUCEXY.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVREDUCEXYLd], (instrs VREDUCEPDZ128rmik, VREDUCEPSZ128rmik,
- VREDUCEPDZ256rmik, VREDUCEPSZ256rmik)>;
+def : InstRW<[C4GM7WriteVREDUCEXYLd], (instrs VREDUCEPDZ128rmik, VREDUCEPSZ128rmik,
+ VREDUCEPDZ256rmik, VREDUCEPSZ256rmik)>;
-def 4GM7WriteVREDUCEZ:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteVREDUCEZ:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 5;
let ReleaseAtCycles = [2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVREDUCEZ], (instrs VREDUCESDZrribk, VREDUCESDZrrik,
- VREDUCESSZrribk, VREDUCESSZrrik,
- VREDUCEPDZrribk, VREDUCEPDZrrik,
- VREDUCEPSZrribk, VREDUCEPSZrrik)>;
+def : InstRW<[C4GM7WriteVREDUCEZ], (instrs VREDUCESDZrribk, VREDUCESDZrrik,
+ VREDUCESSZrribk, VREDUCESSZrrik,
+ VREDUCEPDZrribk, VREDUCEPDZrrik,
+ VREDUCEPSZrribk, VREDUCEPSZrrik)>;
-def 4GM7WriteVREDUCEZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVREDUCEZ.Latency);
+def C4GM7WriteVREDUCEZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVREDUCEZ.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVREDUCEZLd], (instrs VREDUCESSZrmik, VREDUCESDZrmik,
- VREDUCEPSZrmik, VREDUCEPDZrmik)>;
+def : InstRW<[C4GM7WriteVREDUCEZLd], (instrs VREDUCESSZrmik, VREDUCESDZrmik,
+ VREDUCEPSZrmik, VREDUCEPDZrmik)>;
// VGETEXP VGETMANT
-def 4GM7WriteVGETEXPXY_VGETMANTXY:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteVGETEXPXY_VGETMANTXY:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 5;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVGETEXPXY_VGETMANTXY], (instrs VGETEXPPSZ128rk, VGETEXPPDZ128rk,
- VGETEXPPSZ256rk, VGETEXPPDZ256rk,
- VGETMANTPSZ128rrik, VGETMANTPDZ128rrik,
- VGETMANTPSZ256rrik, VGETMANTPDZ256rrik)>;
+def : InstRW<[C4GM7WriteVGETEXPXY_VGETMANTXY], (instrs VGETEXPPSZ128rk, VGETEXPPDZ128rk,
+ VGETEXPPSZ256rk, VGETEXPPDZ256rk,
+ VGETMANTPSZ128rrik, VGETMANTPDZ128rrik,
+ VGETMANTPSZ256rrik, VGETMANTPDZ256rrik)>;
-def 4GM7WriteVGETEXPXY_VGETMANTXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVGETEXPXY_VGETMANTXY.Latency);
+def C4GM7WriteVGETEXPXY_VGETMANTXYLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVGETEXPXY_VGETMANTXY.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVGETEXPXY_VGETMANTXYLd], (instrs VGETEXPPSZ128mk, VGETEXPPDZ128mk,
- VGETEXPPSZ256mk, VGETEXPPDZ256mk,
- VGETMANTPSZ128rmik, VGETMANTPDZ128rmik,
- VGETMANTPSZ256rmik, VGETMANTPDZ256rmik)>;
+def : InstRW<[C4GM7WriteVGETEXPXY_VGETMANTXYLd], (instrs VGETEXPPSZ128mk, VGETEXPPDZ128mk,
+ VGETEXPPSZ256mk, VGETEXPPDZ256mk,
+ VGETMANTPSZ128rmik, VGETMANTPDZ128rmik,
+ VGETMANTPSZ256rmik, VGETMANTPDZ256rmik)>;
-def 4GM7WriteVGETEXPZ_VGETMANTZ:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteVGETEXPZ_VGETMANTZ:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 5;
let ReleaseAtCycles = [2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVGETEXPZ_VGETMANTZ], (instrs VGETEXPSSZrbk, VGETEXPSSZrk,
- VGETEXPSDZrbk, VGETEXPSDZrk,
- VGETEXPPSZrbk, VGETEXPPSZrk,
- VGETEXPPDZrbk, VGETEXPPDZrk,
- VGETMANTSSZrribk, VGETMANTSSZrrik,
- VGETMANTSDZrribk, VGETMANTSDZrrik,
- VGETMANTPSZrribk, VGETMANTPSZrrik,
- VGETMANTPDZrribk, VGETMANTPDZrrik)>;
+def : InstRW<[C4GM7WriteVGETEXPZ_VGETMANTZ], (instrs VGETEXPSSZrbk, VGETEXPSSZrk,
+ VGETEXPSDZrbk, VGETEXPSDZrk,
+ VGETEXPPSZrbk, VGETEXPPSZrk,
+ VGETEXPPDZrbk, VGETEXPPDZrk,
+ VGETMANTSSZrribk, VGETMANTSSZrrik,
+ VGETMANTSDZrribk, VGETMANTSDZrrik,
+ VGETMANTPSZrribk, VGETMANTPSZrrik,
+ VGETMANTPDZrribk, VGETMANTPDZrrik)>;
-def 4GM7WriteVGETEXPZ_VGETMANTZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVGETEXPZ_VGETMANTZ.Latency);
+def C4GM7WriteVGETEXPZ_VGETMANTZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVGETEXPZ_VGETMANTZ.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVGETEXPZ_VGETMANTZLd], (instrs VGETEXPSSZmk, VGETEXPSDZmk,
- VGETEXPPSZmbk, VGETEXPPSZmk,
- VGETEXPPDZmbk, VGETEXPPDZmk,
- VGETMANTSSZrmik, VGETMANTSDZrmik,
- VGETMANTPSZrmik, VGETMANTPDZrmik)>;
+def : InstRW<[C4GM7WriteVGETEXPZ_VGETMANTZLd], (instrs VGETEXPSSZmk, VGETEXPSDZmk,
+ VGETEXPPSZmbk, VGETEXPPSZmk,
+ VGETEXPPDZmbk, VGETEXPPDZmk,
+ VGETMANTSSZrmik, VGETMANTSDZrmik,
+ VGETMANTPSZrmik, VGETMANTPDZrmik)>;
// VSCALEF
-def 4GM7WriteVSCALEFXY:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVSCALEFXY:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVSCALEFXY], (instrs VSCALEFPSZ128rr, VSCALEFPSZ128rrkz,
- VSCALEFPSZ256rr, VSCALEFPSZ256rrkz,
- VSCALEFPDZ128rr, VSCALEFPDZ128rrkz,
- VSCALEFPDZ256rr, VSCALEFPDZ256rrkz)>;
+def : InstRW<[C4GM7WriteVSCALEFXY], (instrs VSCALEFPSZ128rr, VSCALEFPSZ128rrkz,
+ VSCALEFPSZ256rr, VSCALEFPSZ256rrkz,
+ VSCALEFPDZ128rr, VSCALEFPDZ128rrkz,
+ VSCALEFPDZ256rr, VSCALEFPDZ256rrkz)>;
-def 4GM7WriteVSCALEFXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVSCALEFXY.Latency);
+def C4GM7WriteVSCALEFXYLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVSCALEFXY.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVSCALEFXYLd], (instrs VSCALEFPSZ128rm, VSCALEFPSZ128rmkz,
- VSCALEFPSZ256rm, VSCALEFPSZ256rmkz,
- VSCALEFPDZ128rm, VSCALEFPDZ128rmkz,
- VSCALEFPDZ256rm, VSCALEFPDZ256rmkz)>;
+def : InstRW<[C4GM7WriteVSCALEFXYLd], (instrs VSCALEFPSZ128rm, VSCALEFPSZ128rmkz,
+ VSCALEFPSZ256rm, VSCALEFPSZ256rmkz,
+ VSCALEFPDZ128rm, VSCALEFPDZ128rmkz,
+ VSCALEFPDZ256rm, VSCALEFPDZ256rmkz)>;
-def 4GM7WriteVSCALEFZ:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVSCALEFZ:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVSCALEFZ], (instrs VSCALEFSSZrr, VSCALEFSSZrrkz,
- VSCALEFSSZrrb_Int, VSCALEFSSZrrbkz_Int,
- VSCALEFSDZrr, VSCALEFSDZrrkz,
- VSCALEFSDZrrb_Int, VSCALEFSDZrrbkz_Int,
- VSCALEFPSZrr, VSCALEFPSZrrkz,
- VSCALEFPSZrrb, VSCALEFPSZrrbkz,
- VSCALEFPDZrr, VSCALEFPDZrrkz,
- VSCALEFPDZrrb, VSCALEFPDZrrbkz)>;
+def : InstRW<[C4GM7WriteVSCALEFZ], (instrs VSCALEFSSZrr, VSCALEFSSZrrkz,
+ VSCALEFSSZrrb_Int, VSCALEFSSZrrbkz_Int,
+ VSCALEFSDZrr, VSCALEFSDZrrkz,
+ VSCALEFSDZrrb_Int, VSCALEFSDZrrbkz_Int,
+ VSCALEFPSZrr, VSCALEFPSZrrkz,
+ VSCALEFPSZrrb, VSCALEFPSZrrbkz,
+ VSCALEFPDZrr, VSCALEFPDZrrkz,
+ VSCALEFPDZrrb, VSCALEFPDZrrbkz)>;
-def 4GM7WriteVSCALEFZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVSCALEFZ.Latency);
+def C4GM7WriteVSCALEFZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVSCALEFZ.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVSCALEFZLd], (instrs VSCALEFSSZrm, VSCALEFSSZrmkz,
- VSCALEFSDZrm,
- VSCALEFPSZrm, VSCALEFPSZrmkz,
- VSCALEFPSZrmb, VSCALEFPSZrmbkz,
- VSCALEFPDZrm, VSCALEFPDZrmkz,
- VSCALEFPDZrmb, VSCALEFPDZrmbkz)>;
+def : InstRW<[C4GM7WriteVSCALEFZLd], (instrs VSCALEFSSZrm, VSCALEFSSZrmkz,
+ VSCALEFSDZrm,
+ VSCALEFPSZrm, VSCALEFPSZrmkz,
+ VSCALEFPSZrmb, VSCALEFPSZrmbkz,
+ VSCALEFPDZrm, VSCALEFPDZrmkz,
+ VSCALEFPDZrmb, VSCALEFPDZrmbkz)>;
-def 4GM7WriteVSCALEFXYrrk:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVSCALEFXYrrk:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 5;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVSCALEFXYrrk], (instrs VSCALEFPSZ128rrk, VSCALEFPDZ128rrk,
- VSCALEFPSZ256rrk, VSCALEFPDZ256rrk)>;
+def : InstRW<[C4GM7WriteVSCALEFXYrrk], (instrs VSCALEFPSZ128rrk, VSCALEFPDZ128rrk,
+ VSCALEFPSZ256rrk, VSCALEFPDZ256rrk)>;
-def 4GM7WriteVSCALEFXYrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVSCALEFXYrrk.Latency);
+def C4GM7WriteVSCALEFXYrmk:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVSCALEFXYrrk.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVSCALEFXYrmk], (instrs VSCALEFPSZ128rmk, VSCALEFPDZ128rmk,
- VSCALEFPSZ256rmk, VSCALEFPDZ256rmk)>;
+def : InstRW<[C4GM7WriteVSCALEFXYrmk], (instrs VSCALEFPSZ128rmk, VSCALEFPDZ128rmk,
+ VSCALEFPSZ256rmk, VSCALEFPDZ256rmk)>;
-def 4GM7WriteVSCALEFZrrk:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVSCALEFZrrk:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 5;
let ReleaseAtCycles = [2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVSCALEFZrrk], (instrs VSCALEFSSZrrk, VSCALEFSSZrrbk_Int,
- VSCALEFSDZrrk, VSCALEFSDZrrbk_Int,
- VSCALEFPSZrrk, VSCALEFPSZrrbk,
- VSCALEFPDZrrk, VSCALEFPDZrrbk)>;
+def : InstRW<[C4GM7WriteVSCALEFZrrk], (instrs VSCALEFSSZrrk, VSCALEFSSZrrbk_Int,
+ VSCALEFSDZrrk, VSCALEFSDZrrbk_Int,
+ VSCALEFPSZrrk, VSCALEFPSZrrbk,
+ VSCALEFPDZrrk, VSCALEFPDZrrbk)>;
-def 4GM7WriteVSCALEFZrmkLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVSCALEFZrrk.Latency);
+def C4GM7WriteVSCALEFZrmkLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVSCALEFZrrk.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVSCALEFZrmkLd], (instrs VSCALEFSSZrmk, VSCALEFSDZrmk,
- VSCALEFPSZrmk, VSCALEFPSZrmbk,
- VSCALEFPDZrmk, VSCALEFPDZrmbk)>;
+def : InstRW<[C4GM7WriteVSCALEFZrmkLd], (instrs VSCALEFSSZrmk, VSCALEFSDZrmk,
+ VSCALEFPSZrmk, VSCALEFPSZrmbk,
+ VSCALEFPDZrmk, VSCALEFPDZrmbk)>;
// VFMA
-def 4GM7WriteVFMAXY:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVFMAXY:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 5;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVFMAXY], (instregex "VF(MADD|MSUB|MADDSUB|MSUBADD|NMADD|NMSUB)(132|213|231)(PD|PS)(Z128|Z256)r(bk|k)$")>;
+def : InstRW<[C4GM7WriteVFMAXY], (instregex "VF(MADD|MSUB|MADDSUB|MSUBADD|NMADD|NMSUB)(132|213|231)(PD|PS)(Z128|Z256)r(bk|k)$")>;
-def 4GM7WriteVFMAXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVFMAXY.Latency);
+def C4GM7WriteVFMAXYLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVFMAXY.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVFMAXYLd], (instregex "VF(MADD|MSUB|MADDSUB|MSUBADD|NMADD|NMSUB)(132|213|231)(PD|PS)(Z128|Z256)m(bk|k)$")>;
+def : InstRW<[C4GM7WriteVFMAXYLd], (instregex "VF(MADD|MSUB|MADDSUB|MSUBADD|NMADD|NMSUB)(132|213|231)(PD|PS)(Z128|Z256)m(bk|k)$")>;
-def 4GM7WriteVFMAZ:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVFMAZ:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 5;
let ReleaseAtCycles = [2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVFMAZ], (instregex "VF(MADD|MSUB|MADDSUB|MSUBADD|NMADD|NMSUB)(132|213|231)(PD|PS)Zr(bk|k)$",
- "VF(MADD|MSUB|NMADD|NMSUB)(132|213|231)(SD|SS)Zr(bk|k)_Int")>;
+def : InstRW<[C4GM7WriteVFMAZ], (instregex "VF(MADD|MSUB|MADDSUB|MSUBADD|NMADD|NMSUB)(132|213|231)(PD|PS)Zr(bk|k)$",
+ "VF(MADD|MSUB|NMADD|NMSUB)(132|213|231)(SD|SS)Zr(bk|k)_Int")>;
-def 4GM7WriteVFMAZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVFMAZ.Latency);
+def C4GM7WriteVFMAZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVFMAZ.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVFMAZLd], (instregex "VF(MADD|MSUB|MADDSUB|MSUBADD|NMADD|NMSUB)(132|213|231)(PD|PS)Zm(bk|k)$",
- "VF(MADD|MSUB|NMADD|NMSUB)(132|213|231)(SD|SS)Zm(bk|k)_Int")>;
+def : InstRW<[C4GM7WriteVFMAZLd], (instregex "VF(MADD|MSUB|MADDSUB|MSUBADD|NMADD|NMSUB)(132|213|231)(PD|PS)Zm(bk|k)$",
+ "VF(MADD|MSUB|NMADD|NMSUB)(132|213|231)(SD|SS)Zm(bk|k)_Int")>;
// VPROL VPROR
-def 4GM7WriteVPROLXY_VPRORXY:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVPROLXY_VPRORXY:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 3;
let ReleaseAtCycles = [4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPROLXY_VPRORXY], (instregex "VPRO(L|R)V(D|Q)(Z128|Z256)(rr|rrkz)$")>;
+def : InstRW<[C4GM7WriteVPROLXY_VPRORXY], (instregex "VPRO(L|R)V(D|Q)(Z128|Z256)(rr|rrkz)$")>;
-def 4GM7WriteVPROLXY_VPRORXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPROLXY_VPRORXY.Latency);
+def C4GM7WriteVPROLXY_VPRORXYLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPROLXY_VPRORXY.Latency);
let ReleaseAtCycles = [1, 1, 4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPROLXY_VPRORXYLd], (instregex "VPRO(L|R)V(D|Q)(Z128|Z256)(rm|rmkz)$")>;
+def : InstRW<[C4GM7WriteVPROLXY_VPRORXYLd], (instregex "VPRO(L|R)V(D|Q)(Z128|Z256)(rm|rmkz)$")>;
-def 4GM7WriteVPROLXY_VPRORXYrrk:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVPROLXY_VPRORXYrrk:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPROLXY_VPRORXYrrk], (instregex "VPRO(L|R)V(D|Q)(Z128|Z256)rrk$")>;
+def : InstRW<[C4GM7WriteVPROLXY_VPRORXYrrk], (instregex "VPRO(L|R)V(D|Q)(Z128|Z256)rrk$")>;
-def 4GM7WriteVPROLXY_VPRORXYrmkLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPROLXY_VPRORXYrrk.Latency);
+def C4GM7WriteVPROLXY_VPRORXYrmkLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPROLXY_VPRORXYrrk.Latency);
let ReleaseAtCycles = [1, 1, 4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPROLXY_VPRORXYrmkLd], (instregex "VPRO(L|R)V(D|Q)(Z128|Z256)rmk$")>;
+def : InstRW<[C4GM7WriteVPROLXY_VPRORXYrmkLd], (instregex "VPRO(L|R)V(D|Q)(Z128|Z256)rmk$")>;
-def 4GM7WriteVPROLZ_VPRORZ:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVPROLZ_VPRORZ:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [8];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPROLZ_VPRORZ], (instregex "VPRO(L|R)V(D|Q)Z(rr|rrk|rrkz)")>;
+def : InstRW<[C4GM7WriteVPROLZ_VPRORZ], (instregex "VPRO(L|R)V(D|Q)Z(rr|rrk|rrkz)")>;
-def 4GM7WriteVPROLZ_VPRORZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPROLZ_VPRORZ.Latency);
+def C4GM7WriteVPROLZ_VPRORZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPROLZ_VPRORZ.Latency);
let ReleaseAtCycles = [1, 1, 8];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPROLZ_VPRORZLd], (instregex "VPRO(L|R)V(D|Q)Z(rm|rmk|rmkz)")>;
+def : InstRW<[C4GM7WriteVPROLZ_VPRORZLd], (instregex "VPRO(L|R)V(D|Q)Z(rm|rmk|rmkz)")>;
-def 4GM7WriteVPROLImmZ_VPRORImmZ:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVPROLImmZ_VPRORImmZ:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPROLImmZ_VPRORImmZ], (instregex "VPRO(L|R)(D|Q)Z(ri|rik|rikz)")>;
+def : InstRW<[C4GM7WriteVPROLImmZ_VPRORImmZ], (instregex "VPRO(L|R)(D|Q)Z(ri|rik|rikz)")>;
-def 4GM7WriteVPROLImmZ_VPRORImmZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPROLImmZ_VPRORImmZ.Latency);
+def C4GM7WriteVPROLImmZ_VPRORImmZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPROLImmZ_VPRORImmZ.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPROLImmZ_VPRORImmZLd], (instregex "VPRO(L|R)(D|Q)Z(mi|mik|mikz)")>;
+def : InstRW<[C4GM7WriteVPROLImmZ_VPRORImmZLd], (instregex "VPRO(L|R)(D|Q)Z(mi|mik|mikz)")>;
// VPTEST
-def 4GM7WriteVPTESTXY:SchedWriteRes<[4GM7FPU, 4GM7FPU13]> {
+def C4GM7WriteVPTESTXY:SchedWriteRes<[C4GM7FPU, C4GM7FPU13]> {
let Latency = 6;
let ReleaseAtCycles = [3, 1];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVPTESTXY], (instregex "VPTEST(N)?M(B|D|Q|W)(Z128|Z256)rrk")>;
+def : InstRW<[C4GM7WriteVPTESTXY], (instregex "VPTEST(N)?M(B|D|Q|W)(Z128|Z256)rrk")>;
-def 4GM7WriteVPTESTXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPTESTXY.Latency);
+def C4GM7WriteVPTESTXYLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPTESTXY.Latency);
let ReleaseAtCycles = [1, 1, 3, 1];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVPTESTXYLd], (instregex "VPTEST(N)?M(B|D|Q|W)(Z128|Z256)rmk")>;
+def : InstRW<[C4GM7WriteVPTESTXYLd], (instregex "VPTEST(N)?M(B|D|Q|W)(Z128|Z256)rmk")>;
-def 4GM7WriteVPTESTZ:SchedWriteRes<[4GM7FPU, 4GM7FPU13]> {
+def C4GM7WriteVPTESTZ:SchedWriteRes<[C4GM7FPU, C4GM7FPU13]> {
let Latency = 4;
let ReleaseAtCycles = [8, 4];
let NumMicroOps = 4;
}
-def : InstRW<[4GM7WriteVPTESTZ], (instregex "VPTEST(N)?M(B|D|Q|W)Zrrk")>;
+def : InstRW<[C4GM7WriteVPTESTZ], (instregex "VPTEST(N)?M(B|D|Q|W)Zrrk")>;
-def 4GM7WriteVPTESTZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPTESTZ.Latency);
+def C4GM7WriteVPTESTZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPTESTZ.Latency);
let ReleaseAtCycles = [1, 1, 12, 6];
let NumMicroOps = 3;
}
-def : InstRW<[4GM7WriteVPTESTZLd], (instregex "VPTEST(N)?M(B|D|Q|W)Zrmk")>;
+def : InstRW<[C4GM7WriteVPTESTZLd], (instregex "VPTEST(N)?M(B|D|Q|W)Zrmk")>;
// VPACK
-def 4GM7WriteVPACKXY:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteVPACKXY:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 2;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPACKXY], (instrs VPACKSSDWZ128rrk, VPACKSSWBZ128rrk,
- VPACKUSDWZ128rrk, VPACKUSWBZ128rrk,
- VPACKSSDWZ256rrk, VPACKSSWBZ256rrk,
- VPACKUSDWZ256rrk, VPACKUSWBZ256rrk)>;
+def : InstRW<[C4GM7WriteVPACKXY], (instrs VPACKSSDWZ128rrk, VPACKSSWBZ128rrk,
+ VPACKUSDWZ128rrk, VPACKUSWBZ128rrk,
+ VPACKSSDWZ256rrk, VPACKSSWBZ256rrk,
+ VPACKUSDWZ256rrk, VPACKUSWBZ256rrk)>;
-def 4GM7WriteVPACKXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPACKXY.Latency);
+def C4GM7WriteVPACKXYLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPACKXY.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPACKXYLd], (instrs VPACKSSDWZ128rmk, VPACKSSWBZ128rmk,
- VPACKUSDWZ128rmk, VPACKUSWBZ128rmk,
- VPACKSSDWZ256rmk, VPACKSSWBZ256rmk,
- VPACKUSDWZ256rmk, VPACKUSWBZ256rmk)>;
+def : InstRW<[C4GM7WriteVPACKXYLd], (instrs VPACKSSDWZ128rmk, VPACKSSWBZ128rmk,
+ VPACKUSDWZ128rmk, VPACKUSWBZ128rmk,
+ VPACKSSDWZ256rmk, VPACKSSWBZ256rmk,
+ VPACKUSDWZ256rmk, VPACKUSWBZ256rmk)>;
-def 4GM7WriteVPACKZ:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteVPACKZ:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPACKZ], (instrs VPACKSSDWZrrk, VPACKSSWBZrrk,
- VPACKUSDWZrrk, VPACKUSWBZrrk)>;
+def : InstRW<[C4GM7WriteVPACKZ], (instrs VPACKSSDWZrrk, VPACKSSWBZrrk,
+ VPACKUSDWZrrk, VPACKUSWBZrrk)>;
-def 4GM7WriteVPACKZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPACKZ.Latency);
+def C4GM7WriteVPACKZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPACKZ.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPACKZLd], (instrs VPACKSSDWZrmk, VPACKSSWBZrmk,
- VPACKUSDWZrmk, VPACKUSWBZrmk)>;
+def : InstRW<[C4GM7WriteVPACKZLd], (instrs VPACKSSDWZrmk, VPACKSSWBZrmk,
+ VPACKUSDWZrmk, VPACKUSWBZrmk)>;
// VRANGE
-def 4GM7WriteVRANGEXY:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVRANGEXY:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 1;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVRANGEXY], (instregex "VRANGE(PS|PD)(Z128|Z256)(rri|rrikz)$",
- "VRANGE(SS|SD)Z(rri|rrib|rribkz|rrikz)$")>;
+def : InstRW<[C4GM7WriteVRANGEXY], (instregex "VRANGE(PS|PD)(Z128|Z256)(rri|rrikz)$",
+ "VRANGE(SS|SD)Z(rri|rrib|rribkz|rrikz)$")>;
-def 4GM7WriteVRANGEXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVRANGEXY.Latency);
+def C4GM7WriteVRANGEXYLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVRANGEXY.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVRANGEXYLd], (instregex "VRANGE(PS|PD)(Z128|Z256)(rmi|rmikz)$",
- "VRANGE(SS|SD)Z(rmi|rmib|rmibkz|rmikz)$")>;
+def : InstRW<[C4GM7WriteVRANGEXYLd], (instregex "VRANGE(PS|PD)(Z128|Z256)(rmi|rmikz)$",
+ "VRANGE(SS|SD)Z(rmi|rmib|rmibkz|rmikz)$")>;
-def 4GM7WriteVRANGEZ:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVRANGEZ:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 1;
let ReleaseAtCycles = [2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVRANGEZ], (instregex "VRANGE(PS|PD)Z(rri|rrib|rribkz|rrikz)$")>;
+def : InstRW<[C4GM7WriteVRANGEZ], (instregex "VRANGE(PS|PD)Z(rri|rrib|rribkz|rrikz)$")>;
-def 4GM7WriteVRANGEZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVRANGEZ.Latency);
+def C4GM7WriteVRANGEZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVRANGEZ.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVRANGEZLd], (instregex "VRANGE(PS|PD)Z(rmi|rmib|rmibkz|rmikz)$")>;
+def : InstRW<[C4GM7WriteVRANGEZLd], (instregex "VRANGE(PS|PD)Z(rmi|rmib|rmibkz|rmikz)$")>;
-def 4GM7WriteVRANGEXYrrik:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVRANGEXYrrik:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 2;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVRANGEXYrrik], (instregex "VRANGE(PS|PD)(Z128|Z256)rrik$",
- "VRANGE(SS|SD)Z(rrik|rribk)$")>;
+def : InstRW<[C4GM7WriteVRANGEXYrrik], (instregex "VRANGE(PS|PD)(Z128|Z256)rrik$",
+ "VRANGE(SS|SD)Z(rrik|rribk)$")>;
-def 4GM7WriteVRANGEXYrmikLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVRANGEXYrrik.Latency);
+def C4GM7WriteVRANGEXYrmikLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVRANGEXYrrik.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVRANGEXYrmikLd], (instregex "VRANGE(PS|PD)(Z128|Z256)rmik$",
- "VRANGE(SS|SD)Z(rmik|rmibk)$")>;
+def : InstRW<[C4GM7WriteVRANGEXYrmikLd], (instregex "VRANGE(PS|PD)(Z128|Z256)rmik$",
+ "VRANGE(SS|SD)Z(rmik|rmibk)$")>;
-def 4GM7WriteVRANGEZrrik:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVRANGEZrrik:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVRANGEZrrik], (instregex "VRANGE(PS|PD)Z(rrik|rribk)$")>;
+def : InstRW<[C4GM7WriteVRANGEZrrik], (instregex "VRANGE(PS|PD)Z(rrik|rribk)$")>;
-def 4GM7WriteVRANGEZrmikLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVRANGEZrrik.Latency);
+def C4GM7WriteVRANGEZrmikLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVRANGEZrrik.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVRANGEZrmikLd], (instregex "VRANGE(PS|PD)Z(rmik|rmibk)$")>;
+def : InstRW<[C4GM7WriteVRANGEZrmikLd], (instregex "VRANGE(PS|PD)Z(rmik|rmibk)$")>;
// VFIXUPIMM
-def 4GM7WriteVFIXUPIMMXY:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVFIXUPIMMXY:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVFIXUPIMMXY], (instregex "VFIXUPIMM(PS|PD)(Z128|Z256)rrik$")>;
+def : InstRW<[C4GM7WriteVFIXUPIMMXY], (instregex "VFIXUPIMM(PS|PD)(Z128|Z256)rrik$")>;
-def 4GM7WriteVFIXUPIMMXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVFIXUPIMMXY.Latency);
+def C4GM7WriteVFIXUPIMMXYLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVFIXUPIMMXY.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVFIXUPIMMXYLd], (instregex "VFIXUPIMM(PS|PD)(Z128|Z256)rmik$")>;
+def : InstRW<[C4GM7WriteVFIXUPIMMXYLd], (instregex "VFIXUPIMM(PS|PD)(Z128|Z256)rmik$")>;
-def 4GM7WriteVFIXUPIMMZ:SchedWriteRes<[4GM7FPU02, 4GM7FPU02]> {
+def C4GM7WriteVFIXUPIMMZ:SchedWriteRes<[C4GM7FPU02, C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [2, 2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVFIXUPIMMZ], (instregex "VFIXUPIMM(SS|SD|PS|PD)Z(rrik|rribk)$",
- "VFIXUPIMM(SS|SD)Z(rrik|rribk)$")>;
+def : InstRW<[C4GM7WriteVFIXUPIMMZ], (instregex "VFIXUPIMM(SS|SD|PS|PD)Z(rrik|rribk)$",
+ "VFIXUPIMM(SS|SD)Z(rrik|rribk)$")>;
-def 4GM7WriteVFIXUPIMMZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVFIXUPIMMZ.Latency);
+def C4GM7WriteVFIXUPIMMZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVFIXUPIMMZ.Latency);
let ReleaseAtCycles = [1, 1, 2, 2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVFIXUPIMMZLd], (instregex "VFIXUPIMM(SS|SD|PS|PD)Z(rmik|rmibk)$",
- "VFIXUPIMM(SS|SD)Z(rmik|rmibk)$")>;
+def : InstRW<[C4GM7WriteVFIXUPIMMZLd], (instregex "VFIXUPIMM(SS|SD|PS|PD)Z(rmik|rmibk)$",
+ "VFIXUPIMM(SS|SD)Z(rmik|rmibk)$")>;
-def 4GM7WriteVFIXUPIMMZrribkz:SchedWriteRes<[4GM7FPU02, 4GM7FPU02]> {
+def C4GM7WriteVFIXUPIMMZrribkz:SchedWriteRes<[C4GM7FPU02, C4GM7FPU02]> {
let Latency = 3;
let ReleaseAtCycles = [2, 2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVFIXUPIMMZrribkz], (instregex "VFIXUPIMM(SS|SD)Z(rrib|rribkz)$")>;
+def : InstRW<[C4GM7WriteVFIXUPIMMZrribkz], (instregex "VFIXUPIMM(SS|SD)Z(rrib|rribkz)$")>;
// VCOMPRESS VPCOMPRESS
-def 4GM7WriteCOMPRESSXYrrkz:SchedWriteRes<[4GM7FPU3, 4GM7FPU02]> {
+def C4GM7WriteCOMPRESSXYrrkz:SchedWriteRes<[C4GM7FPU3, C4GM7FPU02]> {
let Latency = 3;
let ReleaseAtCycles = [2, 4];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteCOMPRESSXYrrkz], (instrs VCOMPRESSPSZ128rrkz, VCOMPRESSPDZ128rrkz,
- VPCOMPRESSBZ128rrkz, VPCOMPRESSWZ128rrkz,
- VPCOMPRESSDZ128rrkz, VPCOMPRESSQZ128rrkz,
- VCOMPRESSPSZ256rrkz, VCOMPRESSPDZ256rrkz,
- VPCOMPRESSBZ256rrkz, VPCOMPRESSWZ256rrkz,
- VPCOMPRESSDZ256rrkz, VPCOMPRESSQZ256rrkz)>;
+def : InstRW<[C4GM7WriteCOMPRESSXYrrkz], (instrs VCOMPRESSPSZ128rrkz, VCOMPRESSPDZ128rrkz,
+ VPCOMPRESSBZ128rrkz, VPCOMPRESSWZ128rrkz,
+ VPCOMPRESSDZ128rrkz, VPCOMPRESSQZ128rrkz,
+ VCOMPRESSPSZ256rrkz, VCOMPRESSPDZ256rrkz,
+ VPCOMPRESSBZ256rrkz, VPCOMPRESSWZ256rrkz,
+ VPCOMPRESSDZ256rrkz, VPCOMPRESSQZ256rrkz)>;
-def 4GM7WriteCOMPRESSXYrrk:SchedWriteRes<[4GM7FPU3, 4GM7FPU02]> {
+def C4GM7WriteCOMPRESSXYrrk:SchedWriteRes<[C4GM7FPU3, C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [2, 4];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteCOMPRESSXYrrk], (instrs VCOMPRESSPSZ128rrk, VCOMPRESSPDZ128rrk,
- VPCOMPRESSBZ128rrk, VPCOMPRESSWZ128rrk,
- VPCOMPRESSDZ128rrk, VPCOMPRESSQZ128rrk,
- VCOMPRESSPSZ256rrk, VCOMPRESSPDZ256rrk,
- VPCOMPRESSBZ256rrk, VPCOMPRESSWZ256rrk,
- VPCOMPRESSDZ256rrk, VPCOMPRESSQZ256rrk)>;
+def : InstRW<[C4GM7WriteCOMPRESSXYrrk], (instrs VCOMPRESSPSZ128rrk, VCOMPRESSPDZ128rrk,
+ VPCOMPRESSBZ128rrk, VPCOMPRESSWZ128rrk,
+ VPCOMPRESSDZ128rrk, VPCOMPRESSQZ128rrk,
+ VCOMPRESSPSZ256rrk, VCOMPRESSPDZ256rrk,
+ VPCOMPRESSBZ256rrk, VPCOMPRESSWZ256rrk,
+ VPCOMPRESSDZ256rrk, VPCOMPRESSQZ256rrk)>;
-def 4GM7WriteCOMPRESSXYmrk:SchedWriteRes<[4GM7FPU3, 4GM7FPU02, 4GM7AGU, 4GM7Store]> {
- let Latency = !add(4GM7WriteCOMPRESSXYrrk.Latency, C864GM7Model.StoreLatency);
+def C4GM7WriteCOMPRESSXYmrk:SchedWriteRes<[C4GM7FPU3, C4GM7FPU02, C4GM7AGU, C4GM7Store]> {
+ let Latency = !add(C4GM7WriteCOMPRESSXYrrk.Latency, C864GM7Model.StoreLatency);
let ReleaseAtCycles = [2, 4, 1, 1];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteCOMPRESSXYmrk], (instrs VCOMPRESSPSZ128mrk, VCOMPRESSPDZ128mrk,
- VPCOMPRESSBZ128mrk, VPCOMPRESSWZ128mrk,
- VPCOMPRESSDZ128mrk, VPCOMPRESSQZ128mrk,
- VCOMPRESSPSZ256mrk, VCOMPRESSPDZ256mrk,
- VPCOMPRESSBZ256mrk, VPCOMPRESSWZ256mrk,
- VPCOMPRESSDZ256mrk, VPCOMPRESSQZ256mrk)>;
+def : InstRW<[C4GM7WriteCOMPRESSXYmrk], (instrs VCOMPRESSPSZ128mrk, VCOMPRESSPDZ128mrk,
+ VPCOMPRESSBZ128mrk, VPCOMPRESSWZ128mrk,
+ VPCOMPRESSDZ128mrk, VPCOMPRESSQZ128mrk,
+ VCOMPRESSPSZ256mrk, VCOMPRESSPDZ256mrk,
+ VPCOMPRESSBZ256mrk, VPCOMPRESSWZ256mrk,
+ VPCOMPRESSDZ256mrk, VPCOMPRESSQZ256mrk)>;
-def 4GM7WriteCOMPRESSXY:SchedWriteRes<[4GM7FPU3, 4GM7FPU02]> {
+def C4GM7WriteCOMPRESSXY:SchedWriteRes<[C4GM7FPU3, C4GM7FPU02]> {
let Latency = 1;
let ReleaseAtCycles = [2, 4];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteCOMPRESSXY], (instrs VCOMPRESSPSZ128rr, VCOMPRESSPDZ128rr,
- VPCOMPRESSBZ128rr, VPCOMPRESSWZ128rr,
- VPCOMPRESSDZ128rr, VPCOMPRESSQZ128rr,
- VCOMPRESSPSZ256rr, VCOMPRESSPDZ256rr,
- VPCOMPRESSBZ256rr, VPCOMPRESSWZ256rr,
- VPCOMPRESSDZ256rr, VPCOMPRESSQZ256rr)>;
+def : InstRW<[C4GM7WriteCOMPRESSXY], (instrs VCOMPRESSPSZ128rr, VCOMPRESSPDZ128rr,
+ VPCOMPRESSBZ128rr, VPCOMPRESSWZ128rr,
+ VPCOMPRESSDZ128rr, VPCOMPRESSQZ128rr,
+ VCOMPRESSPSZ256rr, VCOMPRESSPDZ256rr,
+ VPCOMPRESSBZ256rr, VPCOMPRESSWZ256rr,
+ VPCOMPRESSDZ256rr, VPCOMPRESSQZ256rr)>;
-def 4GM7WriteCOMPRESSXYLd:SchedWriteRes<[4GM7FPU3, 4GM7FPU02, 4GM7AGU, 4GM7Store]> {
- let Latency = !add(4GM7WriteCOMPRESSXY.Latency, C864GM7Model.StoreLatency);
+def C4GM7WriteCOMPRESSXYLd:SchedWriteRes<[C4GM7FPU3, C4GM7FPU02, C4GM7AGU, C4GM7Store]> {
+ let Latency = !add(C4GM7WriteCOMPRESSXY.Latency, C864GM7Model.StoreLatency);
let ReleaseAtCycles = [2, 4, 1, 1];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteCOMPRESSXYLd], (instrs VCOMPRESSPSZ128mr, VCOMPRESSPDZ128mr,
- VPCOMPRESSBZ128mr, VPCOMPRESSWZ128mr,
- VPCOMPRESSDZ128mr, VPCOMPRESSQZ128mr,
- VCOMPRESSPSZ256mr, VCOMPRESSPDZ256mr,
- VPCOMPRESSBZ256mr, VPCOMPRESSWZ256mr,
- VPCOMPRESSDZ256mr, VPCOMPRESSQZ256mr)>;
+def : InstRW<[C4GM7WriteCOMPRESSXYLd], (instrs VCOMPRESSPSZ128mr, VCOMPRESSPDZ128mr,
+ VPCOMPRESSBZ128mr, VPCOMPRESSWZ128mr,
+ VPCOMPRESSDZ128mr, VPCOMPRESSQZ128mr,
+ VCOMPRESSPSZ256mr, VCOMPRESSPDZ256mr,
+ VPCOMPRESSBZ256mr, VPCOMPRESSWZ256mr,
+ VPCOMPRESSDZ256mr, VPCOMPRESSQZ256mr)>;
-def 4GM7WriteCOMPRESSZrrkz:SchedWriteRes<[4GM7FPU3, 4GM7FPU02]> {
+def C4GM7WriteCOMPRESSZrrkz:SchedWriteRes<[C4GM7FPU3, C4GM7FPU02]> {
let Latency = 10;
let ReleaseAtCycles = [6, 12];
let NumMicroOps = 4;
}
-def : InstRW<[4GM7WriteCOMPRESSZrrkz], (instrs VCOMPRESSPSZrrkz, VCOMPRESSPDZrrkz,
- VPCOMPRESSBZrrkz, VPCOMPRESSWZrrkz,
- VPCOMPRESSDZrrkz, VPCOMPRESSQZrrkz)>;
+def : InstRW<[C4GM7WriteCOMPRESSZrrkz], (instrs VCOMPRESSPSZrrkz, VCOMPRESSPDZrrkz,
+ VPCOMPRESSBZrrkz, VPCOMPRESSWZrrkz,
+ VPCOMPRESSDZrrkz, VPCOMPRESSQZrrkz)>;
-def 4GM7WriteCOMPRESSZrrk:SchedWriteRes<[4GM7FPU3, 4GM7FPU02]> {
+def C4GM7WriteCOMPRESSZrrk:SchedWriteRes<[C4GM7FPU3, C4GM7FPU02]> {
let Latency = 7;
let ReleaseAtCycles = [6, 12];
let NumMicroOps = 4;
}
-def : InstRW<[4GM7WriteCOMPRESSZrrk], (instrs VCOMPRESSPSZrrk, VCOMPRESSPDZrrk,
- VPCOMPRESSBZrrk, VPCOMPRESSDZrrk,
- VPCOMPRESSWZrrk, VPCOMPRESSQZrrk)>;
+def : InstRW<[C4GM7WriteCOMPRESSZrrk], (instrs VCOMPRESSPSZrrk, VCOMPRESSPDZrrk,
+ VPCOMPRESSBZrrk, VPCOMPRESSDZrrk,
+ VPCOMPRESSWZrrk, VPCOMPRESSQZrrk)>;
-def 4GM7WriteCOMPRESSZmrk:SchedWriteRes<[4GM7FPU3, 4GM7FPU02, 4GM7AGU, 4GM7Store]> {
- let Latency = !add(4GM7WriteCOMPRESSZrrk.Latency, C864GM7Model.StoreLatency);
+def C4GM7WriteCOMPRESSZmrk:SchedWriteRes<[C4GM7FPU3, C4GM7FPU02, C4GM7AGU, C4GM7Store]> {
+ let Latency = !add(C4GM7WriteCOMPRESSZrrk.Latency, C864GM7Model.StoreLatency);
let ReleaseAtCycles = [6, 12, 1, 1];
let NumMicroOps = 4;
}
-def : InstRW<[4GM7WriteCOMPRESSZmrk], (instrs VCOMPRESSPSZmrk, VCOMPRESSPDZmrk,
- VPCOMPRESSBZmrk, VPCOMPRESSDZmrk,
- VPCOMPRESSWZmrk, VPCOMPRESSQZmrk)>;
+def : InstRW<[C4GM7WriteCOMPRESSZmrk], (instrs VCOMPRESSPSZmrk, VCOMPRESSPDZmrk,
+ VPCOMPRESSBZmrk, VPCOMPRESSDZmrk,
+ VPCOMPRESSWZmrk, VPCOMPRESSQZmrk)>;
-def 4GM7WriteCOMPRESSZ:SchedWriteRes<[4GM7FPU3, 4GM7FPU02]> {
+def C4GM7WriteCOMPRESSZ:SchedWriteRes<[C4GM7FPU3, C4GM7FPU02]> {
let Latency = 1;
let ReleaseAtCycles = [6, 12];
let NumMicroOps = 4;
}
-def : InstRW<[4GM7WriteCOMPRESSZ], (instrs VCOMPRESSPSZrr, VCOMPRESSPDZrr,
- VPCOMPRESSBZrr, VPCOMPRESSWZrr,
- VPCOMPRESSDZrr, VPCOMPRESSQZrr)>;
+def : InstRW<[C4GM7WriteCOMPRESSZ], (instrs VCOMPRESSPSZrr, VCOMPRESSPDZrr,
+ VPCOMPRESSBZrr, VPCOMPRESSWZrr,
+ VPCOMPRESSDZrr, VPCOMPRESSQZrr)>;
-def 4GM7WriteCOMPRESSZLd:SchedWriteRes<[4GM7FPU3, 4GM7FPU02, 4GM7AGU, 4GM7Store]> {
- let Latency = !add(4GM7WriteCOMPRESSZ.Latency, C864GM7Model.StoreLatency);
+def C4GM7WriteCOMPRESSZLd:SchedWriteRes<[C4GM7FPU3, C4GM7FPU02, C4GM7AGU, C4GM7Store]> {
+ let Latency = !add(C4GM7WriteCOMPRESSZ.Latency, C864GM7Model.StoreLatency);
let ReleaseAtCycles = [6, 12, 1, 1];
let NumMicroOps = 4;
}
-def : InstRW<[4GM7WriteCOMPRESSZLd], (instrs VCOMPRESSPSZmr, VCOMPRESSPDZmr,
- VPCOMPRESSBZmr, VPCOMPRESSWZmr,
- VPCOMPRESSDZmr, VPCOMPRESSQZmr)>;
+def : InstRW<[C4GM7WriteCOMPRESSZLd], (instrs VCOMPRESSPSZmr, VCOMPRESSPDZmr,
+ VPCOMPRESSBZmr, VPCOMPRESSWZmr,
+ VPCOMPRESSDZmr, VPCOMPRESSQZmr)>;
// EXPAND
-def 4GM7WriteEXPANDXYrrkz:SchedWriteRes<[4GM7FPU3, 4GM7FPU02]> {
+def C4GM7WriteEXPANDXYrrkz:SchedWriteRes<[C4GM7FPU3, C4GM7FPU02]> {
let Latency = 3;
let ReleaseAtCycles = [2, 4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteEXPANDXYrrkz], (instrs VEXPANDPSZ128rrkz, VEXPANDPDZ128rrkz,
- VPEXPANDBZ128rrkz, VPEXPANDWZ128rrkz,
- VPEXPANDDZ128rrkz, VPEXPANDQZ128rrkz,
- VEXPANDPSZ256rrkz, VEXPANDPDZ256rrkz,
- VPEXPANDBZ256rrkz, VPEXPANDWZ256rrkz,
- VPEXPANDDZ256rrkz, VPEXPANDQZ256rrkz)>;
+def : InstRW<[C4GM7WriteEXPANDXYrrkz], (instrs VEXPANDPSZ128rrkz, VEXPANDPDZ128rrkz,
+ VPEXPANDBZ128rrkz, VPEXPANDWZ128rrkz,
+ VPEXPANDDZ128rrkz, VPEXPANDQZ128rrkz,
+ VEXPANDPSZ256rrkz, VEXPANDPDZ256rrkz,
+ VPEXPANDBZ256rrkz, VPEXPANDWZ256rrkz,
+ VPEXPANDDZ256rrkz, VPEXPANDQZ256rrkz)>;
-def 4GM7WriteEXPANDXYrmkz:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU3, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteEXPANDXYrrkz.Latency);
+def C4GM7WriteEXPANDXYrmkz:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU3, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteEXPANDXYrrkz.Latency);
let ReleaseAtCycles = [1, 1, 2, 4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteEXPANDXYrmkz], (instrs VEXPANDPSZ128rmkz, VEXPANDPDZ128rmkz,
- VPEXPANDBZ128rmkz, VPEXPANDWZ128rmkz,
- VPEXPANDDZ128rmkz, VPEXPANDQZ128rmkz,
- VEXPANDPSZ256rmkz, VEXPANDPDZ256rmkz,
- VPEXPANDBZ256rmkz, VPEXPANDWZ256rmkz,
- VPEXPANDDZ256rmkz, VPEXPANDQZ256rmkz)>;
+def : InstRW<[C4GM7WriteEXPANDXYrmkz], (instrs VEXPANDPSZ128rmkz, VEXPANDPDZ128rmkz,
+ VPEXPANDBZ128rmkz, VPEXPANDWZ128rmkz,
+ VPEXPANDDZ128rmkz, VPEXPANDQZ128rmkz,
+ VEXPANDPSZ256rmkz, VEXPANDPDZ256rmkz,
+ VPEXPANDBZ256rmkz, VPEXPANDWZ256rmkz,
+ VPEXPANDDZ256rmkz, VPEXPANDQZ256rmkz)>;
-def 4GM7WriteEXPANDXYrrk:SchedWriteRes<[4GM7FPU3, 4GM7FPU02]> {
+def C4GM7WriteEXPANDXYrrk:SchedWriteRes<[C4GM7FPU3, C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [2, 4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteEXPANDXYrrk], (instrs VEXPANDPSZ128rrk, VEXPANDPDZ128rrk,
- VPEXPANDBZ128rrk, VPEXPANDWZ128rrk,
- VPEXPANDDZ128rrk, VPEXPANDQZ128rrk,
- VEXPANDPSZ256rrk, VEXPANDPDZ256rrk,
- VPEXPANDBZ256rrk, VPEXPANDWZ256rrk,
- VPEXPANDDZ256rrk, VPEXPANDQZ256rrk)>;
+def : InstRW<[C4GM7WriteEXPANDXYrrk], (instrs VEXPANDPSZ128rrk, VEXPANDPDZ128rrk,
+ VPEXPANDBZ128rrk, VPEXPANDWZ128rrk,
+ VPEXPANDDZ128rrk, VPEXPANDQZ128rrk,
+ VEXPANDPSZ256rrk, VEXPANDPDZ256rrk,
+ VPEXPANDBZ256rrk, VPEXPANDWZ256rrk,
+ VPEXPANDDZ256rrk, VPEXPANDQZ256rrk)>;
-def 4GM7WriteEXPANDXYrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU3, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteEXPANDXYrrk.Latency);
+def C4GM7WriteEXPANDXYrmk:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU3, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteEXPANDXYrrk.Latency);
let ReleaseAtCycles = [1, 1, 2, 4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteEXPANDXYrmk], (instrs VEXPANDPSZ128rmk, VEXPANDPDZ128rmk,
- VPEXPANDBZ128rmk, VPEXPANDWZ128rmk,
- VPEXPANDDZ128rmk, VPEXPANDQZ128rmk,
- VEXPANDPSZ256rmk, VEXPANDPDZ256rmk,
- VPEXPANDBZ256rmk, VPEXPANDWZ256rmk,
- VPEXPANDDZ256rmk, VPEXPANDQZ256rmk)>;
+def : InstRW<[C4GM7WriteEXPANDXYrmk], (instrs VEXPANDPSZ128rmk, VEXPANDPDZ128rmk,
+ VPEXPANDBZ128rmk, VPEXPANDWZ128rmk,
+ VPEXPANDDZ128rmk, VPEXPANDQZ128rmk,
+ VEXPANDPSZ256rmk, VEXPANDPDZ256rmk,
+ VPEXPANDBZ256rmk, VPEXPANDWZ256rmk,
+ VPEXPANDDZ256rmk, VPEXPANDQZ256rmk)>;
-def 4GM7WriteEXPANDXY:SchedWriteRes<[4GM7FPU3, 4GM7FPU02]> {
+def C4GM7WriteEXPANDXY:SchedWriteRes<[C4GM7FPU3, C4GM7FPU02]> {
let Latency = 1;
let ReleaseAtCycles = [2, 4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteEXPANDXY], (instrs VEXPANDPSZ128rr, VEXPANDPDZ128rr,
- VPEXPANDBZ128rr, VPEXPANDWZ128rr,
- VPEXPANDDZ128rr, VPEXPANDQZ128rr,
- VEXPANDPSZ256rr, VEXPANDPDZ256rr,
- VPEXPANDBZ256rr, VPEXPANDWZ256rr,
- VPEXPANDDZ256rr, VPEXPANDQZ256rr)>;
+def : InstRW<[C4GM7WriteEXPANDXY], (instrs VEXPANDPSZ128rr, VEXPANDPDZ128rr,
+ VPEXPANDBZ128rr, VPEXPANDWZ128rr,
+ VPEXPANDDZ128rr, VPEXPANDQZ128rr,
+ VEXPANDPSZ256rr, VEXPANDPDZ256rr,
+ VPEXPANDBZ256rr, VPEXPANDWZ256rr,
+ VPEXPANDDZ256rr, VPEXPANDQZ256rr)>;
-def 4GM7WriteEXPANDXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU3, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteEXPANDXY.Latency);
+def C4GM7WriteEXPANDXYLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU3, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteEXPANDXY.Latency);
let ReleaseAtCycles = [1, 1, 2, 4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteEXPANDXYLd], (instrs VEXPANDPSZ128rm, VEXPANDPDZ128rm,
- VPEXPANDBZ128rm, VPEXPANDWZ128rm,
- VPEXPANDDZ128rm, VPEXPANDQZ128rm,
- VEXPANDPSZ256rm, VEXPANDPDZ256rm,
- VPEXPANDBZ256rm, VPEXPANDWZ256rm,
- VPEXPANDDZ256rm, VPEXPANDQZ256rm)>;
+def : InstRW<[C4GM7WriteEXPANDXYLd], (instrs VEXPANDPSZ128rm, VEXPANDPDZ128rm,
+ VPEXPANDBZ128rm, VPEXPANDWZ128rm,
+ VPEXPANDDZ128rm, VPEXPANDQZ128rm,
+ VEXPANDPSZ256rm, VEXPANDPDZ256rm,
+ VPEXPANDBZ256rm, VPEXPANDWZ256rm,
+ VPEXPANDDZ256rm, VPEXPANDQZ256rm)>;
-def 4GM7WriteEXPANDZrrkz:SchedWriteRes<[4GM7FPU3, 4GM7FPU02]> {
+def C4GM7WriteEXPANDZrrkz:SchedWriteRes<[C4GM7FPU3, C4GM7FPU02]> {
let Latency = 10;
let ReleaseAtCycles = [8, 16];
let NumMicroOps = 10;
}
-def : InstRW<[4GM7WriteEXPANDZrrkz], (instrs VEXPANDPSZrrkz, VEXPANDPDZrrkz,
- VPEXPANDBZrrkz, VPEXPANDWZrrkz,
- VPEXPANDDZrrkz, VPEXPANDQZrrkz)>;
+def : InstRW<[C4GM7WriteEXPANDZrrkz], (instrs VEXPANDPSZrrkz, VEXPANDPDZrrkz,
+ VPEXPANDBZrrkz, VPEXPANDWZrrkz,
+ VPEXPANDDZrrkz, VPEXPANDQZrrkz)>;
-def 4GM7WriteEXPANDZrmkz:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU3, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteEXPANDZrrkz.Latency);
+def C4GM7WriteEXPANDZrmkz:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU3, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteEXPANDZrrkz.Latency);
let ReleaseAtCycles = [1, 1, 8, 16];
let NumMicroOps = 10;
}
-def : InstRW<[4GM7WriteEXPANDZrmkz], (instrs VEXPANDPSZrmkz, VEXPANDPDZrmkz,
- VPEXPANDBZrmkz, VPEXPANDWZrmkz,
- VPEXPANDDZrmkz, VPEXPANDQZrmkz)>;
+def : InstRW<[C4GM7WriteEXPANDZrmkz], (instrs VEXPANDPSZrmkz, VEXPANDPDZrmkz,
+ VPEXPANDBZrmkz, VPEXPANDWZrmkz,
+ VPEXPANDDZrmkz, VPEXPANDQZrmkz)>;
-def 4GM7WriteEXPANDZrrk:SchedWriteRes<[4GM7FPU3, 4GM7FPU02]> {
+def C4GM7WriteEXPANDZrrk:SchedWriteRes<[C4GM7FPU3, C4GM7FPU02]> {
let Latency = 8;
let ReleaseAtCycles = [8, 16];
let NumMicroOps = 10;
}
-def : InstRW<[4GM7WriteEXPANDZrrk], (instrs VEXPANDPSZrrk, VEXPANDPDZrrk,
- VPEXPANDBZrrk, VPEXPANDDZrrk,
- VPEXPANDWZrrk, VPEXPANDQZrrk)>;
+def : InstRW<[C4GM7WriteEXPANDZrrk], (instrs VEXPANDPSZrrk, VEXPANDPDZrrk,
+ VPEXPANDBZrrk, VPEXPANDDZrrk,
+ VPEXPANDWZrrk, VPEXPANDQZrrk)>;
-def 4GM7WriteEXPANDZrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU3, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteEXPANDZrrk.Latency);
+def C4GM7WriteEXPANDZrmk:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU3, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteEXPANDZrrk.Latency);
let ReleaseAtCycles = [1, 1, 8, 16];
let NumMicroOps = 10;
}
-def : InstRW<[4GM7WriteEXPANDZrmk], (instrs VEXPANDPSZrmk, VEXPANDPDZrmk,
- VPEXPANDBZrmk, VPEXPANDDZrmk,
- VPEXPANDWZrmk, VPEXPANDQZrmk)>;
+def : InstRW<[C4GM7WriteEXPANDZrmk], (instrs VEXPANDPSZrmk, VEXPANDPDZrmk,
+ VPEXPANDBZrmk, VPEXPANDDZrmk,
+ VPEXPANDWZrmk, VPEXPANDQZrmk)>;
-def 4GM7WriteEXPANDZ:SchedWriteRes<[4GM7FPU3, 4GM7FPU02]> {
+def C4GM7WriteEXPANDZ:SchedWriteRes<[C4GM7FPU3, C4GM7FPU02]> {
let Latency = 1;
let ReleaseAtCycles = [8, 16];
let NumMicroOps = 10;
}
-def : InstRW<[4GM7WriteEXPANDZ], (instrs VEXPANDPSZrr, VEXPANDPDZrr,
- VPEXPANDBZrr, VPEXPANDWZrr,
- VPEXPANDDZrr, VPEXPANDQZrr)>;
+def : InstRW<[C4GM7WriteEXPANDZ], (instrs VEXPANDPSZrr, VEXPANDPDZrr,
+ VPEXPANDBZrr, VPEXPANDWZrr,
+ VPEXPANDDZrr, VPEXPANDQZrr)>;
-def 4GM7WriteEXPANDZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU3, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteEXPANDZ.Latency);
+def C4GM7WriteEXPANDZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU3, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteEXPANDZ.Latency);
let ReleaseAtCycles = [1, 1, 8, 16];
let NumMicroOps = 10;
}
-def : InstRW<[4GM7WriteEXPANDZLd], (instrs VEXPANDPSZrm, VEXPANDPDZrm,
- VPEXPANDBZrm, VPEXPANDWZrm,
- VPEXPANDDZrm, VPEXPANDQZrm)>;
+def : InstRW<[C4GM7WriteEXPANDZLd], (instrs VEXPANDPSZrm, VEXPANDPDZrm,
+ VPEXPANDBZrm, VPEXPANDWZrm,
+ VPEXPANDDZrm, VPEXPANDQZrm)>;
// VINSERT
-def 4GM7WriteVINSERT256Z:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteVINSERT256Z:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVINSERT256Z], (instregex "VINSERT(F|I)(32X8|64X4)Zrri(k|kz)?")>;
+def : InstRW<[C4GM7WriteVINSERT256Z], (instregex "VINSERT(F|I)(32X8|64X4)Zrri(k|kz)?")>;
-def 4GM7WriteVINSERT256ZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVINSERT256Z.Latency);
+def C4GM7WriteVINSERT256ZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVINSERT256Z.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVINSERT256ZLd], (instregex "VINSERT(F|I)(32X8|64X4)Zrmi(k|kz)?")>;
+def : InstRW<[C4GM7WriteVINSERT256ZLd], (instregex "VINSERT(F|I)(32X8|64X4)Zrmi(k|kz)?")>;
-def 4GM7WriteVINSERTY:SchedWriteRes<[4GM7FPU02, 4GM7FPU02]> {
+def C4GM7WriteVINSERTY:SchedWriteRes<[C4GM7FPU02, C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [4, 4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVINSERTY], (instregex "VINSERT(F|I)(32X4|64X2)Z256rrik")>;
+def : InstRW<[C4GM7WriteVINSERTY], (instregex "VINSERT(F|I)(32X4|64X2)Z256rrik")>;
-def 4GM7WriteVINSERTYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVINSERTY.Latency);
+def C4GM7WriteVINSERTYLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVINSERTY.Latency);
let ReleaseAtCycles = [1, 1, 4, 4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVINSERTYLd], (instregex "VINSERT(F|I)(32X4|64X2)Z256rmik")>;
+def : InstRW<[C4GM7WriteVINSERTYLd], (instregex "VINSERT(F|I)(32X4|64X2)Z256rmik")>;
-def 4GM7WriteVINSERTZ:SchedWriteRes<[4GM7FPU02, 4GM7FPU02]> {
+def C4GM7WriteVINSERTZ:SchedWriteRes<[C4GM7FPU02, C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [8, 8];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVINSERTZ], (instregex "VINSERT(F|I)(32X4|64X2)Zrrik")>;
+def : InstRW<[C4GM7WriteVINSERTZ], (instregex "VINSERT(F|I)(32X4|64X2)Zrrik")>;
-def 4GM7WriteVINSERTZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVINSERTZ.Latency);
+def C4GM7WriteVINSERTZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVINSERTZ.Latency);
let ReleaseAtCycles = [1, 1, 8, 8];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVINSERTZLd], (instregex "VINSERT(F|I)(32X4|64X2)Zrmik")>;
+def : InstRW<[C4GM7WriteVINSERTZLd], (instregex "VINSERT(F|I)(32X4|64X2)Zrmik")>;
-def 4GM7WriteVINSERTZrri:SchedWriteRes<[4GM7FPU02, 4GM7FPU02]> {
+def C4GM7WriteVINSERTZrri:SchedWriteRes<[C4GM7FPU02, C4GM7FPU02]> {
let Latency = 5;
let ReleaseAtCycles = [8, 8];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVINSERTZrri], (instregex "VINSERT(F|I)(32X4|64X2)Zrri$")>;
+def : InstRW<[C4GM7WriteVINSERTZrri], (instregex "VINSERT(F|I)(32X4|64X2)Zrri$")>;
-def 4GM7WriteVINSERTZrmi:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVINSERTZrri.Latency);
+def C4GM7WriteVINSERTZrmi:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVINSERTZrri.Latency);
let ReleaseAtCycles = [1, 1, 8, 8];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVINSERTZrmi], (instregex "VINSERT(F|I)(32X4|64X2)Zrmi$")>;
+def : InstRW<[C4GM7WriteVINSERTZrmi], (instregex "VINSERT(F|I)(32X4|64X2)Zrmi$")>;
// VEXTRACT
-def 4GM7WriteVEXTRACTZ:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteVEXTRACTZ:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 1;
let ReleaseAtCycles = [1];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVEXTRACTZ], (instregex "VEXTRACT(F|I)(32X8|64X4)Z(rri|rrikz)$")>;
+def : InstRW<[C4GM7WriteVEXTRACTZ], (instregex "VEXTRACT(F|I)(32X8|64X4)Z(rri|rrikz)$")>;
-def 4GM7WriteVEXTRACTZLd:SchedWriteRes<[4GM7FPU13, 4GM7AGU, 4GM7Store]> {
- let Latency = !add(4GM7WriteVEXTRACTZ.Latency, C864GM7Model.StoreLatency);
+def C4GM7WriteVEXTRACTZLd:SchedWriteRes<[C4GM7FPU13, C4GM7AGU, C4GM7Store]> {
+ let Latency = !add(C4GM7WriteVEXTRACTZ.Latency, C864GM7Model.StoreLatency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVEXTRACTZLd], (instregex "VEXTRACT(F|I)(32X8|64X4)Z(mri|mrikz)$")>;
+def : InstRW<[C4GM7WriteVEXTRACTZLd], (instregex "VEXTRACT(F|I)(32X8|64X4)Z(mri|mrikz)$")>;
-def 4GM7WriteVEXTRACTZrrik:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteVEXTRACTZrrik:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 2;
let ReleaseAtCycles = [1];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVEXTRACTZrrik], (instregex "VEXTRACT(F|I)(32X8|64X4)Zrrik$")>;
+def : InstRW<[C4GM7WriteVEXTRACTZrrik], (instregex "VEXTRACT(F|I)(32X8|64X4)Zrrik$")>;
-def 4GM7WriteVEXTRACTZmrik:SchedWriteRes<[4GM7FPU13, 4GM7AGU, 4GM7Store]> {
- let Latency = !add(4GM7WriteVEXTRACTZrrik.Latency, C864GM7Model.StoreLatency);
+def C4GM7WriteVEXTRACTZmrik:SchedWriteRes<[C4GM7FPU13, C4GM7AGU, C4GM7Store]> {
+ let Latency = !add(C4GM7WriteVEXTRACTZrrik.Latency, C864GM7Model.StoreLatency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVEXTRACTZmrik], (instregex "VEXTRACT(F|I)(32X8|64X4)Zmrik$")>;
+def : InstRW<[C4GM7WriteVEXTRACTZmrik], (instregex "VEXTRACT(F|I)(32X8|64X4)Zmrik$")>;
-def 4GM7WriteVEXTRACTY:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVEXTRACTY:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVEXTRACTY], (instregex "VEXTRACT(F|I)(32X4|64X2)(Z|Z256)rrik$")>;
+def : InstRW<[C4GM7WriteVEXTRACTY], (instregex "VEXTRACT(F|I)(32X4|64X2)(Z|Z256)rrik$")>;
-def 4GM7WriteVEXTRACTYLd:SchedWriteRes<[4GM7FPU02, 4GM7AGU, 4GM7Store]> {
- let Latency = !add(4GM7WriteVEXTRACTY.Latency, C864GM7Model.StoreLatency);
+def C4GM7WriteVEXTRACTYLd:SchedWriteRes<[C4GM7FPU02, C4GM7AGU, C4GM7Store]> {
+ let Latency = !add(C4GM7WriteVEXTRACTY.Latency, C864GM7Model.StoreLatency);
let ReleaseAtCycles = [4, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVEXTRACTYLd], (instregex "VEXTRACT(F|I)(32X4|64X2)(Z|Z256)mrik$")>;
+def : InstRW<[C4GM7WriteVEXTRACTYLd], (instregex "VEXTRACT(F|I)(32X4|64X2)(Z|Z256)mrik$")>;
// VPCONFLIC
-def 4GM7WriteVPCONFLICX:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteVPCONFLICX:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 2;
let ReleaseAtCycles = [4];
let NumMicroOps = 4;
}
-def : InstRW<[4GM7WriteVPCONFLICX], (instregex "VPCONFLICT(D|Q)Z128(rr|rrk|rrkz)")>;
+def : InstRW<[C4GM7WriteVPCONFLICX], (instregex "VPCONFLICT(D|Q)Z128(rr|rrk|rrkz)")>;
-def 4GM7WriteVPCONFLICXLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPCONFLICX.Latency);
+def C4GM7WriteVPCONFLICXLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPCONFLICX.Latency);
let ReleaseAtCycles = [1, 1, 4];
let NumMicroOps = 4;
}
-def : InstRW<[4GM7WriteVPCONFLICXLd], (instregex "VPCONFLICT(D|Q)Z128(rm|rmk|rmkz)")>;
+def : InstRW<[C4GM7WriteVPCONFLICXLd], (instregex "VPCONFLICT(D|Q)Z128(rm|rmk|rmkz)")>;
-def 4GM7WriteVPCONFLICY:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteVPCONFLICY:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 5;
let ReleaseAtCycles = [6];
let NumMicroOps = 5;
}
-def : InstRW<[4GM7WriteVPCONFLICY], (instregex "VPCONFLICT(D|Q)Z256(rr|rrkz)$")>;
+def : InstRW<[C4GM7WriteVPCONFLICY], (instregex "VPCONFLICT(D|Q)Z256(rr|rrkz)$")>;
-def 4GM7WriteVPCONFLICYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPCONFLICY.Latency);
+def C4GM7WriteVPCONFLICYLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPCONFLICY.Latency);
let ReleaseAtCycles = [1, 1, 6];
let NumMicroOps = 8;
}
-def : InstRW<[4GM7WriteVPCONFLICYLd], (instregex "VPCONFLICT(D|Q)Z256(rm|rmkz)$")>;
+def : InstRW<[C4GM7WriteVPCONFLICYLd], (instregex "VPCONFLICT(D|Q)Z256(rm|rmkz)$")>;
-def 4GM7WriteVPCONFLICYrrk:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteVPCONFLICYrrk:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 3;
let ReleaseAtCycles = [6];
let NumMicroOps = 4;
}
-def : InstRW<[4GM7WriteVPCONFLICYrrk], (instregex "VPCONFLICT(D|Q)Z256rrk$")>;
+def : InstRW<[C4GM7WriteVPCONFLICYrrk], (instregex "VPCONFLICT(D|Q)Z256rrk$")>;
-def 4GM7WriteVPCONFLICYrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPCONFLICYrrk.Latency);
+def C4GM7WriteVPCONFLICYrmk:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPCONFLICYrrk.Latency);
let ReleaseAtCycles = [1, 1, 6];
let NumMicroOps = 4;
}
-def : InstRW<[4GM7WriteVPCONFLICYrmk], (instregex "VPCONFLICT(D|Q)Z256rmk$")>;
+def : InstRW<[C4GM7WriteVPCONFLICYrmk], (instregex "VPCONFLICT(D|Q)Z256rmk$")>;
-def 4GM7WriteVPCONFLICZ:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteVPCONFLICZ:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 7;
let ReleaseAtCycles = [12];
let NumMicroOps = 16;
}
-def : InstRW<[4GM7WriteVPCONFLICZ], (instregex "VPCONFLICT(D|Q)Z(rr|rrkz)$")>;
+def : InstRW<[C4GM7WriteVPCONFLICZ], (instregex "VPCONFLICT(D|Q)Z(rr|rrkz)$")>;
-def 4GM7WriteVPCONFLICZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPCONFLICZ.Latency);
+def C4GM7WriteVPCONFLICZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPCONFLICZ.Latency);
let ReleaseAtCycles = [1, 1, 12];
let NumMicroOps = 16;
}
-def : InstRW<[4GM7WriteVPCONFLICZLd], (instregex "VPCONFLICT(D|Q)Z(rm|rmkz)$")>;
+def : InstRW<[C4GM7WriteVPCONFLICZLd], (instregex "VPCONFLICT(D|Q)Z(rm|rmkz)$")>;
-def 4GM7WriteVPCONFLICZrrk:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteVPCONFLICZrrk:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 6;
let ReleaseAtCycles = [12];
let NumMicroOps = 16;
}
-def : InstRW<[4GM7WriteVPCONFLICZrrk], (instregex "VPCONFLICT(D|Q)Zrrk$")>;
+def : InstRW<[C4GM7WriteVPCONFLICZrrk], (instregex "VPCONFLICT(D|Q)Zrrk$")>;
-def 4GM7WriteVPCONFLICZrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPCONFLICZrrk.Latency);
+def C4GM7WriteVPCONFLICZrmk:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPCONFLICZrrk.Latency);
let ReleaseAtCycles = [1, 1, 12];
let NumMicroOps = 16;
}
-def : InstRW<[4GM7WriteVPCONFLICZrmk], (instregex "VPCONFLICT(D|Q)Zrmk$")>;
+def : InstRW<[C4GM7WriteVPCONFLICZrmk], (instregex "VPCONFLICT(D|Q)Zrmk$")>;
// VPDP
-def 4GM7WriteVPDPXY:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVPDPXY:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPDPXY], (instregex "VPDP(BUSDS|BUSD|WSSDS|WSSD)(Z128|Z256)rrk$")>;
+def : InstRW<[C4GM7WriteVPDPXY], (instregex "VPDP(BUSDS|BUSD|WSSDS|WSSD)(Z128|Z256)rrk$")>;
-def 4GM7WriteVPDPXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPDPXY.Latency);
+def C4GM7WriteVPDPXYLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPDPXY.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPDPXYLd], (instregex "VPDP(BUSDS|BUSD|WSSDS|WSSD)(Z128|Z256)rmk$")>;
+def : InstRW<[C4GM7WriteVPDPXYLd], (instregex "VPDP(BUSDS|BUSD|WSSDS|WSSD)(Z128|Z256)rmk$")>;
-def 4GM7WriteVPDPZ:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVPDPZ:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPDPZ], (instregex "VPDP(BUSDS|BUSD|WSSDS|WSSD)Zrrk$")>;
+def : InstRW<[C4GM7WriteVPDPZ], (instregex "VPDP(BUSDS|BUSD|WSSDS|WSSD)Zrrk$")>;
-def 4GM7WriteVPDPZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPDPZ.Latency);
+def C4GM7WriteVPDPZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPDPZ.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPDPZLd], (instregex "VPDP(BUSDS|BUSD|WSSDS|WSSD)Zrmk$")>;
+def : InstRW<[C4GM7WriteVPDPZLd], (instregex "VPDP(BUSDS|BUSD|WSSDS|WSSD)Zrmk$")>;
// VBROADCAST VPBROADCAST
-def 4GM7WriteVBROADCASTX:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteVBROADCASTX:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 1;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVBROADCASTX], (instregex "V(P)?BROADCAST(SS|B|W)Z128(rr|rrkz)$")>;
+def : InstRW<[C4GM7WriteVBROADCASTX], (instregex "V(P)?BROADCAST(SS|B|W)Z128(rr|rrkz)$")>;
-def 4GM7WriteVBROADCASTXLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVBROADCASTX.Latency);
+def C4GM7WriteVBROADCASTXLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVBROADCASTX.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVBROADCASTXLd], (instregex "V(P)?BROADCAST(SS|B|W)Z128(rm|rmkz)$")>;
+def : InstRW<[C4GM7WriteVBROADCASTXLd], (instregex "V(P)?BROADCAST(SS|B|W)Z128(rm|rmkz)$")>;
-def 4GM7WriteVBROADCASTXrrk:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteVBROADCASTXrrk:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 2;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVBROADCASTXrrk], (instregex "V(P)?BROADCAST(SS|SD|I32X2|B|W|D|Q)(r)?Z128rrk$")>;
+def : InstRW<[C4GM7WriteVBROADCASTXrrk], (instregex "V(P)?BROADCAST(SS|SD|I32X2|B|W|D|Q)(r)?Z128rrk$")>;
-def 4GM7WriteVBROADCASTXrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVBROADCASTXrrk.Latency);
+def C4GM7WriteVBROADCASTXrmk:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVBROADCASTXrrk.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVBROADCASTXrmk], (instregex "V(P)?BROADCAST(SS|SD|I32X2|B|W|D|Q)(r)?Z128rmk$")>;
+def : InstRW<[C4GM7WriteVBROADCASTXrmk], (instregex "V(P)?BROADCAST(SS|SD|I32X2|B|W|D|Q)(r)?Z128rmk$")>;
-def 4GM7WriteVBROADCASTY:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVBROADCASTY:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVBROADCASTY], (instregex "V(P)?BROADCAST(SS|SD|F32X2|I32X2|B|W|D|Q)(r)?Z256rrk$")>;
+def : InstRW<[C4GM7WriteVBROADCASTY], (instregex "V(P)?BROADCAST(SS|SD|F32X2|I32X2|B|W|D|Q)(r)?Z256rrk$")>;
-def 4GM7WriteVBROADCASTYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVBROADCASTY.Latency);
+def C4GM7WriteVBROADCASTYLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVBROADCASTY.Latency);
let ReleaseAtCycles = [1, 1, 4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVBROADCASTYLd], (instregex "V(P)?BROADCAST(SS|SD|F32X2|I32X2|B|W|D|Q)(r)?Z256rmk$")>;
+def : InstRW<[C4GM7WriteVBROADCASTYLd], (instregex "V(P)?BROADCAST(SS|SD|F32X2|I32X2|B|W|D|Q)(r)?Z256rmk$")>;
-def 4GM7WriteVBROADCASTZ:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVBROADCASTZ:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 5;
let ReleaseAtCycles = [8];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVBROADCASTZ], (instregex "V(P)?BROADCAST(SS|SD|F32X2|I32X2|B|W|D|Q)Z(rr|rrkz)$")>;
+def : InstRW<[C4GM7WriteVBROADCASTZ], (instregex "V(P)?BROADCAST(SS|SD|F32X2|I32X2|B|W|D|Q)Z(rr|rrkz)$")>;
-def 4GM7WriteVBROADCASTZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVBROADCASTZ.Latency);
+def C4GM7WriteVBROADCASTZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVBROADCASTZ.Latency);
let ReleaseAtCycles = [1, 1, 8];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVBROADCASTZLd], (instregex "V(P)?BROADCAST(SS|SD|F32X2|I32X2|B|W|D|Q)Z(rm|rmkz)$")>;
+def : InstRW<[C4GM7WriteVBROADCASTZLd], (instregex "V(P)?BROADCAST(SS|SD|F32X2|I32X2|B|W|D|Q)Z(rm|rmkz)$")>;
-def 4GM7WriteVBROADCASTZrrk:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVBROADCASTZrrk:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [8];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVBROADCASTZrrk], (instregex "V(P)?BROADCAST(SS|SD|F32X2|I32X2|B|W|D|Q)(r)?Zrrk$")>;
+def : InstRW<[C4GM7WriteVBROADCASTZrrk], (instregex "V(P)?BROADCAST(SS|SD|F32X2|I32X2|B|W|D|Q)(r)?Zrrk$")>;
-def 4GM7WriteVBROADCASTZrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVBROADCASTZrrk.Latency);
+def C4GM7WriteVBROADCASTZrmk:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVBROADCASTZrrk.Latency);
let ReleaseAtCycles = [1, 1, 8];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVBROADCASTZrmk], (instregex "V(P)?BROADCAST(SS|SD|F32X2|I32X2|B|W|D|Q)(r)?Zrmk$")>;
+def : InstRW<[C4GM7WriteVBROADCASTZrmk], (instregex "V(P)?BROADCAST(SS|SD|F32X2|I32X2|B|W|D|Q)(r)?Zrmk$")>;
// VPERM
-def 4GM7WriteVPERMXY:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVPERMXY:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 3;
let ReleaseAtCycles = [4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPERMXY], (instregex "VPERM(PS|PD|B|W|D|Q)(Z128|Z256)(rr|rrkz)$")>;
+def : InstRW<[C4GM7WriteVPERMXY], (instregex "VPERM(PS|PD|B|W|D|Q)(Z128|Z256)(rr|rrkz)$")>;
-def 4GM7WriteVPERMXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPERMXY.Latency);
+def C4GM7WriteVPERMXYLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPERMXY.Latency);
let ReleaseAtCycles = [1, 1, 4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPERMXYLd], (instregex "VPERM(PS|PD|B|W|D|Q)(Z128|Z256)(rm|rmkz)$")>;
+def : InstRW<[C4GM7WriteVPERMXYLd], (instregex "VPERM(PS|PD|B|W|D|Q)(Z128|Z256)(rm|rmkz)$")>;
-def 4GM7WriteVPERMXYrrk:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVPERMXYrrk:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPERMXYrrk], (instregex "VPERM(PS|PD|B|W|D|Q)(Z128|Z256)rrk$")>;
+def : InstRW<[C4GM7WriteVPERMXYrrk], (instregex "VPERM(PS|PD|B|W|D|Q)(Z128|Z256)rrk$")>;
-def 4GM7WriteVPERMXYrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPERMXYrrk.Latency);
+def C4GM7WriteVPERMXYrmk:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPERMXYrrk.Latency);
let ReleaseAtCycles = [1, 1, 4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPERMXYrmk], (instregex "VPERM(PS|PD|B|W|D|Q)(Z128|Z256)rmk$")>;
+def : InstRW<[C4GM7WriteVPERMXYrmk], (instregex "VPERM(PS|PD|B|W|D|Q)(Z128|Z256)rmk$")>;
-def 4GM7WriteVPERMZ:SchedWriteRes<[4GM7FPU]> {
+def C4GM7WriteVPERMZ:SchedWriteRes<[C4GM7FPU]> {
let Latency = 8;
let ReleaseAtCycles = [32];
let NumMicroOps = 8;
}
-def : InstRW<[4GM7WriteVPERMZ], (instregex "VPERM(PS|PD|B|W|D|Q)Zrr(k|kz)?",
- "VPERM2(F|I)128rri")>;
+def : InstRW<[C4GM7WriteVPERMZ], (instregex "VPERM(PS|PD|B|W|D|Q)Zrr(k|kz)?",
+ "VPERM2(F|I)128rri")>;
-def 4GM7WriteVPERMZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPERMZ.Latency);
+def C4GM7WriteVPERMZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPERMZ.Latency);
let ReleaseAtCycles = [1, 1, 32];
let NumMicroOps = 8;
}
-def : InstRW<[4GM7WriteVPERMZLd], (instregex "VPERM(PS|PD|B|W|D|Q)Zrm(k|kz)?",
- "VPERM2(F|I)128rmi")>;
+def : InstRW<[C4GM7WriteVPERMZLd], (instregex "VPERM(PS|PD|B|W|D|Q)Zrm(k|kz)?",
+ "VPERM2(F|I)128rmi")>;
-def 4GM7WriteVPERMImmY:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVPERMImmY:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 3;
let ReleaseAtCycles = [4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPERMImmY], (instregex "VPERM(PD|Q)Z256(ri|rikz)$")>;
+def : InstRW<[C4GM7WriteVPERMImmY], (instregex "VPERM(PD|Q)Z256(ri|rikz)$")>;
-def 4GM7WriteVPERMImmYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPERMImmY.Latency);
+def C4GM7WriteVPERMImmYLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPERMImmY.Latency);
let ReleaseAtCycles = [1, 1, 4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPERMImmYLd], (instregex "VPERM(PD|Q)Z256(mi|mikz)$")>;
+def : InstRW<[C4GM7WriteVPERMImmYLd], (instregex "VPERM(PD|Q)Z256(mi|mikz)$")>;
-def 4GM7WriteVPERMImmYrik:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVPERMImmYrik:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPERMImmYrik], (instregex "VPERM(PD|Q)Z256rik$")>;
+def : InstRW<[C4GM7WriteVPERMImmYrik], (instregex "VPERM(PD|Q)Z256rik$")>;
-def 4GM7WriteVPERMImmYmik:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPERMImmYrik.Latency);
+def C4GM7WriteVPERMImmYmik:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPERMImmYrik.Latency);
let ReleaseAtCycles = [1, 1, 4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPERMImmYmik], (instregex "VPERM(PD|Q)Z256mik$")>;
+def : InstRW<[C4GM7WriteVPERMImmYmik], (instregex "VPERM(PD|Q)Z256mik$")>;
-def 4GM7WriteVPERMImmZ:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVPERMImmZ:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [8];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPERMImmZ], (instregex "VPERM(PD|Q)Zri(k|kz)?")>;
+def : InstRW<[C4GM7WriteVPERMImmZ], (instregex "VPERM(PD|Q)Zri(k|kz)?")>;
-def 4GM7WriteVPERMImmZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPERMImmZ.Latency);
+def C4GM7WriteVPERMImmZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPERMImmZ.Latency);
let ReleaseAtCycles = [1, 1, 8];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPERMImmZLd], (instregex "VPERM(PD|Q)Zmi(k|kz)?")>;
+def : InstRW<[C4GM7WriteVPERMImmZLd], (instregex "VPERM(PD|Q)Zmi(k|kz)?")>;
// VPERMI2 VPERMT2
-def 4GM7WriteVPERMI2X_VPERMT2X:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVPERMI2X_VPERMT2X:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 3;
let ReleaseAtCycles = [4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPERMI2X_VPERMT2X], (instregex "VPERM(I|T)2(PS|PD|B|W|D|Q)Z128(rr|rrkz)$")>;
+def : InstRW<[C4GM7WriteVPERMI2X_VPERMT2X], (instregex "VPERM(I|T)2(PS|PD|B|W|D|Q)Z128(rr|rrkz)$")>;
-def 4GM7WriteVPERMI2X_VPERMT2XLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPERMI2X_VPERMT2X.Latency);
+def C4GM7WriteVPERMI2X_VPERMT2XLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPERMI2X_VPERMT2X.Latency);
let ReleaseAtCycles = [1, 1, 4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPERMI2X_VPERMT2XLd], (instregex "VPERM(I|T)2(PS|PD|B|W|D|Q)Z128(rm|rmkz)$")>;
+def : InstRW<[C4GM7WriteVPERMI2X_VPERMT2XLd], (instregex "VPERM(I|T)2(PS|PD|B|W|D|Q)Z128(rm|rmkz)$")>;
-def 4GM7WriteVPERMI2X_VPERMT2Xrrk:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVPERMI2X_VPERMT2Xrrk:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPERMI2X_VPERMT2Xrrk], (instregex "VPERM(I|T)2(PS|PD|B|D|W|Q)Z128rrk$")>;
+def : InstRW<[C4GM7WriteVPERMI2X_VPERMT2Xrrk], (instregex "VPERM(I|T)2(PS|PD|B|D|W|Q)Z128rrk$")>;
-def 4GM7WriteVPERMI2X_VPERMT2Xrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPERMI2X_VPERMT2Xrrk.Latency);
+def C4GM7WriteVPERMI2X_VPERMT2Xrmk:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPERMI2X_VPERMT2Xrrk.Latency);
let ReleaseAtCycles = [1, 1, 4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPERMI2X_VPERMT2Xrmk], (instregex "VPERM(I|T)2(PS|PD|B|D|W|Q)Z128rmk$")>;
+def : InstRW<[C4GM7WriteVPERMI2X_VPERMT2Xrmk], (instregex "VPERM(I|T)2(PS|PD|B|D|W|Q)Z128rmk$")>;
-def 4GM7WriteVPERMT2Y:SchedWriteRes<[4GM7FPU]> {
+def C4GM7WriteVPERMT2Y:SchedWriteRes<[C4GM7FPU]> {
let Latency = 4;
let ReleaseAtCycles = [16];
let NumMicroOps = 4;
}
-def : InstRW<[4GM7WriteVPERMT2Y], (instregex "VPERMT2(PS|PD|B|W|D|Q)Z256rr(kz)?")>;
+def : InstRW<[C4GM7WriteVPERMT2Y], (instregex "VPERMT2(PS|PD|B|W|D|Q)Z256rr(kz)?")>;
-def 4GM7WriteVPERMT2YLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPERMT2Y.Latency);
+def C4GM7WriteVPERMT2YLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPERMT2Y.Latency);
let ReleaseAtCycles = [1, 1, 16];
let NumMicroOps = 4;
}
-def : InstRW<[4GM7WriteVPERMT2YLd], (instregex "VPERMT2(PS|PD|B|W|D|Q)Z256rm(kz)?")>;
+def : InstRW<[C4GM7WriteVPERMT2YLd], (instregex "VPERMT2(PS|PD|B|W|D|Q)Z256rm(kz)?")>;
-def 4GM7WriteVPERMI2Y:SchedWriteRes<[4GM7FPU]> {
+def C4GM7WriteVPERMI2Y:SchedWriteRes<[C4GM7FPU]> {
let Latency = 6;
let ReleaseAtCycles = [16];
let NumMicroOps = 4;
}
-def : InstRW<[4GM7WriteVPERMI2Y], (instregex "VPERMI2(PS|PD|B|W|D|Q)Z256rr(kz)?")>;
+def : InstRW<[C4GM7WriteVPERMI2Y], (instregex "VPERMI2(PS|PD|B|W|D|Q)Z256rr(kz)?")>;
-def 4GM7WriteVPERMI2YLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPERMI2Y.Latency);
+def C4GM7WriteVPERMI2YLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPERMI2Y.Latency);
let ReleaseAtCycles = [1, 1, 16];
let NumMicroOps = 4;
}
-def : InstRW<[4GM7WriteVPERMI2YLd], (instregex "VPERMI2(PS|PD|B|W|D|Q)Z256rm(kz)?")>;
+def : InstRW<[C4GM7WriteVPERMI2YLd], (instregex "VPERMI2(PS|PD|B|W|D|Q)Z256rm(kz)?")>;
-def 4GM7WriteVPERMI2Z_VPERMT2Z:SchedWriteRes<[4GM7FPU]> {
+def C4GM7WriteVPERMI2Z_VPERMT2Z:SchedWriteRes<[C4GM7FPU]> {
let Latency = 16;
let ReleaseAtCycles = [64];
let NumMicroOps = 16;
}
-def : InstRW<[4GM7WriteVPERMI2Z_VPERMT2Z], (instregex "VPERM(I|T)2(PS|PD|B|W|D|Q)Zrr(kz)?")>;
+def : InstRW<[C4GM7WriteVPERMI2Z_VPERMT2Z], (instregex "VPERM(I|T)2(PS|PD|B|W|D|Q)Zrr(kz)?")>;
-def 4GM7WriteVPERMI2Z_VPERMT2ZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPERMI2Z_VPERMT2Z.Latency);
+def C4GM7WriteVPERMI2Z_VPERMT2ZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPERMI2Z_VPERMT2Z.Latency);
let ReleaseAtCycles = [1, 1, 64];
let NumMicroOps = 16;
}
-def : InstRW<[4GM7WriteVPERMI2Z_VPERMT2ZLd], (instregex "VPERM(I|T)2(PS|PD|B|W|D|Q)Zrm(kz)?")>;
+def : InstRW<[C4GM7WriteVPERMI2Z_VPERMT2ZLd], (instregex "VPERM(I|T)2(PS|PD|B|W|D|Q)Zrm(kz)?")>;
// VPERMIL
-def 4GM7WriteVPERMILXY:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVPERMILXY:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPERMILXY], (instregex "VPERMIL(PS|PD)(Z128|Z256)rrk$")>;
+def : InstRW<[C4GM7WriteVPERMILXY], (instregex "VPERMIL(PS|PD)(Z128|Z256)rrk$")>;
-def 4GM7WriteVPERMILXYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPERMILXY.Latency);
+def C4GM7WriteVPERMILXYLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPERMILXY.Latency);
let ReleaseAtCycles = [1, 1, 4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPERMILXYLd], (instregex "VPERMIL(PS|PD)(Z128|Z256)rmk$")>;
+def : InstRW<[C4GM7WriteVPERMILXYLd], (instregex "VPERMIL(PS|PD)(Z128|Z256)rmk$")>;
-def 4GM7WriteVPERMILZ:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVPERMILZ:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 3;
let ReleaseAtCycles = [8];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPERMILZ], (instregex "VPERMIL(PS|PD)Z(rr|rrkz)$")>;
+def : InstRW<[C4GM7WriteVPERMILZ], (instregex "VPERMIL(PS|PD)Z(rr|rrkz)$")>;
-def 4GM7WriteVPERMILZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPERMILZ.Latency);
+def C4GM7WriteVPERMILZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPERMILZ.Latency);
let ReleaseAtCycles = [1, 1, 8];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPERMILZLd], (instregex "VPERMIL(PS|PD)Z(rm|rmkz)$")>;
+def : InstRW<[C4GM7WriteVPERMILZLd], (instregex "VPERMIL(PS|PD)Z(rm|rmkz)$")>;
-def 4GM7WriteVPERMILZrrk:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteVPERMILZrrk:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [8];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPERMILZrrk], (instregex "VPERMIL(PS|PD)Zrrk$")>;
+def : InstRW<[C4GM7WriteVPERMILZrrk], (instregex "VPERMIL(PS|PD)Zrrk$")>;
-def 4GM7WriteVPERMILZrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPERMILZrrk.Latency);
+def C4GM7WriteVPERMILZrmk:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPERMILZrrk.Latency);
let ReleaseAtCycles = [1, 1, 8];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPERMILZrmk], (instregex "VPERMIL(PS|PD)Zrmk$")>;
+def : InstRW<[C4GM7WriteVPERMILZrmk], (instregex "VPERMIL(PS|PD)Zrmk$")>;
-def 4GM7WriteVPERMILZrik:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteVPERMILZrik:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPERMILZrik], (instregex "VPERMIL(PS|PD)Zri(k|kz)?")>;
+def : InstRW<[C4GM7WriteVPERMILZrik], (instregex "VPERMIL(PS|PD)Zri(k|kz)?")>;
-def 4GM7WriteVPERMILZmik:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVPERMILZrik.Latency);
+def C4GM7WriteVPERMILZmik:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVPERMILZrik.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteVPERMILZmik], (instregex "VPERMIL(PS|PD)Zmi(k|kz)?")>;
+def : InstRW<[C4GM7WriteVPERMILZmik], (instregex "VPERMIL(PS|PD)Zmi(k|kz)?")>;
// ALIGN
-def 4GM7WriteALIGNX:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteALIGNX:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 2;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteALIGNX], (instrs VALIGNDZ128rrik, VALIGNDZ128rrikz,
- VALIGNQZ128rrik, VALIGNQZ128rrikz)>;
+def : InstRW<[C4GM7WriteALIGNX], (instrs VALIGNDZ128rrik, VALIGNDZ128rrikz,
+ VALIGNQZ128rrik, VALIGNQZ128rrikz)>;
-def 4GM7WriteALIGNXLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteALIGNX.Latency);
+def C4GM7WriteALIGNXLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteALIGNX.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteALIGNXLd], (instrs VALIGNDZ128rmik, VALIGNDZ128rmikz,
- VALIGNQZ128rmik, VALIGNQZ128rmikz)>;
+def : InstRW<[C4GM7WriteALIGNXLd], (instrs VALIGNDZ128rmik, VALIGNDZ128rmikz,
+ VALIGNQZ128rmik, VALIGNQZ128rmikz)>;
-def 4GM7WriteALIGNY:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteALIGNY:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 3;
let ReleaseAtCycles = [4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteALIGNY], (instrs VALIGNDZ256rri, VALIGNDZ256rrikz,
- VALIGNQZ256rri, VALIGNQZ256rrikz)>;
+def : InstRW<[C4GM7WriteALIGNY], (instrs VALIGNDZ256rri, VALIGNDZ256rrikz,
+ VALIGNQZ256rri, VALIGNQZ256rrikz)>;
-def 4GM7WriteALIGNYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteALIGNY.Latency);
+def C4GM7WriteALIGNYLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteALIGNY.Latency);
let ReleaseAtCycles = [1, 1, 4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteALIGNYLd], (instrs VALIGNDZ256rmi, VALIGNDZ256rmikz,
- VALIGNQZ256rmi, VALIGNQZ256rmikz)>;
+def : InstRW<[C4GM7WriteALIGNYLd], (instrs VALIGNDZ256rmi, VALIGNDZ256rmikz,
+ VALIGNQZ256rmi, VALIGNQZ256rmikz)>;
-def 4GM7WriteALIGNYrrik:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteALIGNYrrik:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteALIGNYrrik], (instrs VALIGNDZ256rrik, VALIGNQZ256rrik)>;
+def : InstRW<[C4GM7WriteALIGNYrrik], (instrs VALIGNDZ256rrik, VALIGNQZ256rrik)>;
-def 4GM7WriteALIGNYrmik:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteALIGNYrrik.Latency);
+def C4GM7WriteALIGNYrmik:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteALIGNYrrik.Latency);
let ReleaseAtCycles = [1, 1, 4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteALIGNYrmik], (instrs VALIGNDZ256rmik, VALIGNQZ256rmik)>;
+def : InstRW<[C4GM7WriteALIGNYrmik], (instrs VALIGNDZ256rmik, VALIGNQZ256rmik)>;
-def 4GM7WriteALIGNZ:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteALIGNZ:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 4;
let ReleaseAtCycles = [8];
let NumMicroOps = 8;
}
-def : InstRW<[4GM7WriteALIGNZ], (instrs VALIGNDZrri, VALIGNQZrri,
- VALIGNDZrrik, VALIGNQZrrik,
- VALIGNDZrrikz, VALIGNQZrrikz)>;
+def : InstRW<[C4GM7WriteALIGNZ], (instrs VALIGNDZrri, VALIGNQZrri,
+ VALIGNDZrrik, VALIGNQZrrik,
+ VALIGNDZrrikz, VALIGNQZrrikz)>;
-def 4GM7WriteALIGNZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteALIGNZ.Latency);
+def C4GM7WriteALIGNZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteALIGNZ.Latency);
let ReleaseAtCycles = [1, 1, 8];
let NumMicroOps = 8;
}
-def : InstRW<[4GM7WriteALIGNZLd], (instrs VALIGNDZrmi, VALIGNQZrmi,
- VALIGNDZrmik, VALIGNQZrmik,
- VALIGNDZrmikz, VALIGNQZrmikz)>;
+def : InstRW<[C4GM7WriteALIGNZLd], (instrs VALIGNDZrmi, VALIGNQZrmi,
+ VALIGNDZrmik, VALIGNQZrmik,
+ VALIGNDZrmikz, VALIGNQZrmikz)>;
// PALIGN
-def 4GM7WritePALIGNX:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WritePALIGNX:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 2;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WritePALIGNX], (instrs VPALIGNRZrrik, VPALIGNRZrrikz)>;
+def : InstRW<[C4GM7WritePALIGNX], (instrs VPALIGNRZrrik, VPALIGNRZrrikz)>;
-def 4GM7WritePALIGNXLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WritePALIGNX.Latency);
+def C4GM7WritePALIGNXLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WritePALIGNX.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WritePALIGNXLd], (instrs VPALIGNRZrmik, VPALIGNRZrmikz)>;
+def : InstRW<[C4GM7WritePALIGNXLd], (instrs VPALIGNRZrmik, VPALIGNRZrmikz)>;
-def 4GM7WritePALIGNY:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WritePALIGNY:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 2;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WritePALIGNY], (instrs VPALIGNRZ128rrik, VPALIGNRZ128rrikz)>;
+def : InstRW<[C4GM7WritePALIGNY], (instrs VPALIGNRZ128rrik, VPALIGNRZ128rrikz)>;
-def 4GM7WritePALIGNYLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WritePALIGNY.Latency);
+def C4GM7WritePALIGNYLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WritePALIGNY.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WritePALIGNYLd], (instrs VPALIGNRZ128rmik, VPALIGNRZ128rmikz)>;
+def : InstRW<[C4GM7WritePALIGNYLd], (instrs VPALIGNRZ128rmik, VPALIGNRZ128rmikz)>;
-def 4GM7WritePALIGNZ:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WritePALIGNZ:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WritePALIGNZ], (instrs VPALIGNRZ256rrik, VPALIGNRZ256rrikz)>;
+def : InstRW<[C4GM7WritePALIGNZ], (instrs VPALIGNRZ256rrik, VPALIGNRZ256rrikz)>;
-def 4GM7WritePALIGNZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WritePALIGNZ.Latency);
+def C4GM7WritePALIGNZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WritePALIGNZ.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WritePALIGNZLd], (instrs VPALIGNRZ256rmik, VPALIGNRZ256rmikz)>;
+def : InstRW<[C4GM7WritePALIGNZLd], (instrs VPALIGNRZ256rmik, VPALIGNRZ256rmikz)>;
// DBPSADBWZ
-def 4GM7WriteDBPSADBWZ:SchedWriteRes<[4GM7FPU02, 4GM7FPU13]> {
+def C4GM7WriteDBPSADBWZ:SchedWriteRes<[C4GM7FPU02, C4GM7FPU13]> {
let Latency = 3;
let ReleaseAtCycles = [6, 6];
let NumMicroOps = 5;
}
-def : InstRW<[4GM7WriteDBPSADBWZ], (instrs VDBPSADBWZrri, VDBPSADBWZrrikz,
- VDBPSADBWZ128rri, VDBPSADBWZ128rrikz,
- VDBPSADBWZ256rri, VDBPSADBWZ256rrikz)>;
+def : InstRW<[C4GM7WriteDBPSADBWZ], (instrs VDBPSADBWZrri, VDBPSADBWZrrikz,
+ VDBPSADBWZ128rri, VDBPSADBWZ128rrikz,
+ VDBPSADBWZ256rri, VDBPSADBWZ256rrikz)>;
-def 4GM7WriteDBPSADBWZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteDBPSADBWZ.Latency);
+def C4GM7WriteDBPSADBWZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteDBPSADBWZ.Latency);
let ReleaseAtCycles = [1, 1, 6, 6];
let NumMicroOps = 5;
}
-def : InstRW<[4GM7WriteDBPSADBWZLd], (instrs VDBPSADBWZrmi, VDBPSADBWZrmikz,
- VDBPSADBWZ128rmi, VDBPSADBWZ128rmikz,
- VDBPSADBWZ256rmi, VDBPSADBWZ256rmikz)>;
+def : InstRW<[C4GM7WriteDBPSADBWZLd], (instrs VDBPSADBWZrmi, VDBPSADBWZrmikz,
+ VDBPSADBWZ128rmi, VDBPSADBWZ128rmikz,
+ VDBPSADBWZ256rmi, VDBPSADBWZ256rmikz)>;
-def 4GM7WriteDBPSADBWZrrik:SchedWriteRes<[4GM7FPU02, 4GM7FPU13]> {
+def C4GM7WriteDBPSADBWZrrik:SchedWriteRes<[C4GM7FPU02, C4GM7FPU13]> {
let Latency = 4;
let ReleaseAtCycles = [6, 6];
let NumMicroOps = 5;
}
-def : InstRW<[4GM7WriteDBPSADBWZrrik], (instrs VDBPSADBWZrrik, VDBPSADBWZ128rrik, VDBPSADBWZ256rrik)>;
+def : InstRW<[C4GM7WriteDBPSADBWZrrik], (instrs VDBPSADBWZrrik, VDBPSADBWZ128rrik, VDBPSADBWZ256rrik)>;
-def 4GM7WriteDBPSADBWZrmikLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteDBPSADBWZrrik.Latency);
+def C4GM7WriteDBPSADBWZrmikLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteDBPSADBWZrrik.Latency);
let ReleaseAtCycles = [1, 1, 6, 6];
let NumMicroOps = 5;
}
-def : InstRW<[4GM7WriteDBPSADBWZrmikLd], (instrs VDBPSADBWZrmik, VDBPSADBWZ128rmik, VDBPSADBWZ256rmik)>;
+def : InstRW<[C4GM7WriteDBPSADBWZrmikLd], (instrs VDBPSADBWZrmik, VDBPSADBWZ128rmik, VDBPSADBWZ256rmik)>;
// VecLogicZ rrk
-def 4GM7WriteVecLogicZ:SchedWriteRes<[4GM7FPU]> {
+def C4GM7WriteVecLogicZ:SchedWriteRes<[C4GM7FPU]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVecLogicZ], (instregex "VPAND(D|Q)Z(128|256)?rrk$",
+def : InstRW<[C4GM7WriteVecLogicZ], (instregex "VPAND(D|Q)Z(128|256)?rrk$",
"VPANDN(D|Q)Z(128|256)?rrk$",
"VPOR(D|Q)Z(128|256)?rrk$",
"VPXOR(D|Q)Z(128|256)?rrk$",
@@ -3274,199 +3274,199 @@ def : InstRW<[4GM7WriteVecLogicZ], (instregex "VPAND(D|Q)Z(128|256)?rrk$",
"VORP(D|S)Z(128|256)?rrk$",
"VXORP(D|S)Z(128|256)?rrk$")>;
-def 4GM7WriteVecLogicZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVecLogicZ.Latency);
+def C4GM7WriteVecLogicZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVecLogicZ.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVecLogicZLd], (instregex "VPAND(D|Q)Z(128|256)?rmk$",
- "VPANDN(D|Q)Z(128|256)?rmk$",
- "VPOR(D|Q)Z(128|256)?rmk$",
- "VPXOR(D|Q)Z(128|256)?rmk$",
- "VANDNP(D|S)Z(128|256)?rmk$",
- "VANDP(D|S)Z(128|256)?rmk$",
- "VORP(D|S)Z(128|256)?rmk$",
- "VXORP(D|S)Z(128|256)?rmk$")>;
+def : InstRW<[C4GM7WriteVecLogicZLd], (instregex "VPAND(D|Q)Z(128|256)?rmk$",
+ "VPANDN(D|Q)Z(128|256)?rmk$",
+ "VPOR(D|Q)Z(128|256)?rmk$",
+ "VPXOR(D|Q)Z(128|256)?rmk$",
+ "VANDNP(D|S)Z(128|256)?rmk$",
+ "VANDP(D|S)Z(128|256)?rmk$",
+ "VORP(D|S)Z(128|256)?rmk$",
+ "VXORP(D|S)Z(128|256)?rmk$")>;
// GF2P8MULB
-def 4GM7WriteGF2P8MULB:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteGF2P8MULB:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 3;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteGF2P8MULB], (instrs GF2P8MULBrr, VGF2P8MULBrr, VGF2P8MULBYrr)>;
+def : InstRW<[C4GM7WriteGF2P8MULB], (instrs GF2P8MULBrr, VGF2P8MULBrr, VGF2P8MULBYrr)>;
-def 4GM7WriteGF2P8MULBLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteGF2P8MULB.Latency);
+def C4GM7WriteGF2P8MULBLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteGF2P8MULB.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteGF2P8MULBLd], (instrs GF2P8MULBrm, VGF2P8MULBrm, VGF2P8MULBYrm)>;
+def : InstRW<[C4GM7WriteGF2P8MULBLd], (instrs GF2P8MULBrm, VGF2P8MULBrm, VGF2P8MULBYrm)>;
-def 4GM7WriteGF2P8MULBXYZ:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteGF2P8MULBXYZ:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 3;
let ReleaseAtCycles = [2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteGF2P8MULBXYZ], (instrs VGF2P8MULBZrr, VGF2P8MULBZrrkz,
- VGF2P8MULBZ128rr, VGF2P8MULBZ128rrkz,
- VGF2P8MULBZ256rr, VGF2P8MULBZ256rrkz)>;
+def : InstRW<[C4GM7WriteGF2P8MULBXYZ], (instrs VGF2P8MULBZrr, VGF2P8MULBZrrkz,
+ VGF2P8MULBZ128rr, VGF2P8MULBZ128rrkz,
+ VGF2P8MULBZ256rr, VGF2P8MULBZ256rrkz)>;
-def 4GM7WriteGF2P8MULBXYZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteGF2P8MULBXYZ.Latency);
+def C4GM7WriteGF2P8MULBXYZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteGF2P8MULBXYZ.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteGF2P8MULBXYZLd], (instrs VGF2P8MULBZrm, VGF2P8MULBZrmkz,
- VGF2P8MULBZ128rm, VGF2P8MULBZ128rmkz,
- VGF2P8MULBZ256rm, VGF2P8MULBZ256rmkz)>;
+def : InstRW<[C4GM7WriteGF2P8MULBXYZLd], (instrs VGF2P8MULBZrm, VGF2P8MULBZrmkz,
+ VGF2P8MULBZ128rm, VGF2P8MULBZ128rmkz,
+ VGF2P8MULBZ256rm, VGF2P8MULBZ256rmkz)>;
-def 4GM7WriteGF2P8MULBXYZrrk:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteGF2P8MULBXYZrrk:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 4;
let ReleaseAtCycles = [2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteGF2P8MULBXYZrrk], (instrs VGF2P8MULBZrrk, VGF2P8MULBZ128rrk, VGF2P8MULBZ256rrk)>;
+def : InstRW<[C4GM7WriteGF2P8MULBXYZrrk], (instrs VGF2P8MULBZrrk, VGF2P8MULBZ128rrk, VGF2P8MULBZ256rrk)>;
-def 4GM7WriteGF2P8MULBXYZrmk:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteGF2P8MULBXYZrrk.Latency);
+def C4GM7WriteGF2P8MULBXYZrmk:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteGF2P8MULBXYZrrk.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteGF2P8MULBXYZrmk], (instrs VGF2P8MULBZrmk, VGF2P8MULBZ128rmk, VGF2P8MULBZ256rmk)>;
+def : InstRW<[C4GM7WriteGF2P8MULBXYZrmk], (instrs VGF2P8MULBZrmk, VGF2P8MULBZ128rmk, VGF2P8MULBZ256rmk)>;
// VGF2P8AFFINE
-def 4GM7WriteVGF2P8AFFINEZ:SchedWriteRes<[4GM7FPU13]> {
+def C4GM7WriteVGF2P8AFFINEZ:SchedWriteRes<[C4GM7FPU13]> {
let Latency = 4;
let ReleaseAtCycles = [2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVGF2P8AFFINEZ], (instrs VGF2P8AFFINEQBZrrik, VGF2P8AFFINEQBZ128rrik, VGF2P8AFFINEQBZ256rrik,
- VGF2P8AFFINEINVQBZrrik, VGF2P8AFFINEINVQBZ128rrik, VGF2P8AFFINEINVQBZ256rrik)>;
+def : InstRW<[C4GM7WriteVGF2P8AFFINEZ], (instrs VGF2P8AFFINEQBZrrik, VGF2P8AFFINEQBZ128rrik, VGF2P8AFFINEQBZ256rrik,
+ VGF2P8AFFINEINVQBZrrik, VGF2P8AFFINEINVQBZ128rrik, VGF2P8AFFINEINVQBZ256rrik)>;
-def 4GM7WriteVGF2P8AFFINEZLd:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU13]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteVGF2P8AFFINEZ.Latency);
+def C4GM7WriteVGF2P8AFFINEZLd:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU13]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteVGF2P8AFFINEZ.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteVGF2P8AFFINEZLd], (instrs VGF2P8AFFINEQBZrmik, VGF2P8AFFINEQBZ128rmik, VGF2P8AFFINEQBZ256rmik,
- VGF2P8AFFINEINVQBZrmik, VGF2P8AFFINEINVQBZ128rmik, VGF2P8AFFINEINVQBZ256rmik)>;
+def : InstRW<[C4GM7WriteVGF2P8AFFINEZLd], (instrs VGF2P8AFFINEQBZrmik, VGF2P8AFFINEQBZ128rmik, VGF2P8AFFINEQBZ256rmik,
+ VGF2P8AFFINEINVQBZrmik, VGF2P8AFFINEINVQBZ128rmik, VGF2P8AFFINEINVQBZ256rmik)>;
// Vector insert/extract operations.
-defm : 4GM7WriteResFPPair<WriteVecInsert, [4GM7FPU13], 2>;
-defm : 4GM7WriteRes<WriteVecExtract, [4GM7FPU02], 1, [4], 1>;
-defm : 4GM7WriteRes<WriteVecExtractSt, [4GM7FPU02, 4GM7AGU, 4GM7Store], 3, [4, 1, 1], 1>;
+defm : C4GM7WriteResFPPair<WriteVecInsert, [C4GM7FPU13], 2>;
+defm : C4GM7WriteRes<WriteVecExtract, [C4GM7FPU02], 1, [4], 1>;
+defm : C4GM7WriteRes<WriteVecExtractSt, [C4GM7FPU02, C4GM7AGU, C4GM7Store], 3, [4, 1, 1], 1>;
// MOVMSK Instructions.
-defm : 4GM7WriteRes<WriteFMOVMSK, [4GM7FPU13], 1>;
-defm : 4GM7WriteRes<WriteMMXMOVMSK, [4GM7FPU13], 1>;
-defm : 4GM7WriteRes<WriteVecMOVMSK, [4GM7FPU13], 1>;
-defm : 4GM7WriteRes<WriteVecMOVMSKY, [4GM7FPU13], 1>;
+defm : C4GM7WriteRes<WriteFMOVMSK, [C4GM7FPU13], 1>;
+defm : C4GM7WriteRes<WriteMMXMOVMSK, [C4GM7FPU13], 1>;
+defm : C4GM7WriteRes<WriteVecMOVMSK, [C4GM7FPU13], 1>;
+defm : C4GM7WriteRes<WriteVecMOVMSKY, [C4GM7FPU13], 1>;
// Strings instructions.
-defm : 4GM7WriteResFPPair<WritePCmpIStrM, [4GM7FPU], 7, [25], 3>;
-defm : 4GM7WriteResFPPair<WritePCmpEStrM, [4GM7FPU], 7, [25], 8>;
-defm : 4GM7WriteResFPPair<WritePCmpIStrI, [4GM7FPU], 2, [8], 2>;
-defm : 4GM7WriteResFPPair<WritePCmpEStrI, [4GM7FPU], 8, [13], 8>;
+defm : C4GM7WriteResFPPair<WritePCmpIStrM, [C4GM7FPU], 7, [25], 3>;
+defm : C4GM7WriteResFPPair<WritePCmpEStrM, [C4GM7FPU], 7, [25], 8>;
+defm : C4GM7WriteResFPPair<WritePCmpIStrI, [C4GM7FPU], 2, [8], 2>;
+defm : C4GM7WriteResFPPair<WritePCmpEStrI, [C4GM7FPU], 8, [13], 8>;
// AES Instructions.
-defm : 4GM7WriteResFPPair<WriteAESDecEnc, [4GM7FPU13], 3>;
-defm : 4GM7WriteResFPPair<WriteAESIMC, [4GM7FPU13], 3>;
-defm : 4GM7WriteResFPPair<WriteAESKeyGen, [4GM7FPU13], 3>;
+defm : C4GM7WriteResFPPair<WriteAESDecEnc, [C4GM7FPU13], 3>;
+defm : C4GM7WriteResFPPair<WriteAESIMC, [C4GM7FPU13], 3>;
+defm : C4GM7WriteResFPPair<WriteAESKeyGen, [C4GM7FPU13], 3>;
// SHA Instructions.
-def 4GM7WriteSHA1rr:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteSHA1rr:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 1;
let ReleaseAtCycles = [1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteSHA1rr], (instrs SHA1MSG1rr, SHA1MSG2rr, SHA1NEXTErr)>;
+def : InstRW<[C4GM7WriteSHA1rr], (instrs SHA1MSG1rr, SHA1MSG2rr, SHA1NEXTErr)>;
-def 4GM7WriteSHA1rm:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteSHA1rr.Latency);
+def C4GM7WriteSHA1rm:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteSHA1rr.Latency);
let ReleaseAtCycles = [1, 1, 1];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteSHA1rm], (instrs SHA1MSG1rm, SHA1MSG2rm, SHA1NEXTErm)>;
+def : InstRW<[C4GM7WriteSHA1rm], (instrs SHA1MSG1rm, SHA1MSG2rm, SHA1NEXTErm)>;
-def 4GM7WriteSHA256MSG1rr:SchedWriteRes<[4GM7FPU]> {
+def C4GM7WriteSHA256MSG1rr:SchedWriteRes<[C4GM7FPU]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteSHA256MSG1rr], (instrs SHA256MSG1rr)>;
+def : InstRW<[C4GM7WriteSHA256MSG1rr], (instrs SHA256MSG1rr)>;
-def 4GM7WriteSHA256MSG1rm:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteSHA256MSG1rr.Latency);
+def C4GM7WriteSHA256MSG1rm:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteSHA256MSG1rr.Latency);
let ReleaseAtCycles = [1, 1, 2];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteSHA256MSG1rm], (instrs SHA256MSG1rm)>;
+def : InstRW<[C4GM7WriteSHA256MSG1rm], (instrs SHA256MSG1rm)>;
-def 4GM7WriteSHA256rr:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteSHA256rr:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 4;
let ReleaseAtCycles = [4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteSHA256rr], (instrs SHA256MSG2rr, SHA256RNDS2rr)>;
+def : InstRW<[C4GM7WriteSHA256rr], (instrs SHA256MSG2rr, SHA256RNDS2rr)>;
-def 4GM7WriteSHA256rm:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteSHA256rr.Latency);
+def C4GM7WriteSHA256rm:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteSHA256rr.Latency);
let ReleaseAtCycles = [1, 1, 4];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteSHA256rm], (instrs SHA256MSG2rm, SHA256RNDS2rm)>;
+def : InstRW<[C4GM7WriteSHA256rm], (instrs SHA256MSG2rm, SHA256RNDS2rm)>;
-def 4GM7WriteSHA1RNDS4rri:SchedWriteRes<[4GM7FPU02]> {
+def C4GM7WriteSHA1RNDS4rri:SchedWriteRes<[C4GM7FPU02]> {
let Latency = 5;
let ReleaseAtCycles = [8];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteSHA1RNDS4rri], (instrs SHA1RNDS4rri)>;
+def : InstRW<[C4GM7WriteSHA1RNDS4rri], (instrs SHA1RNDS4rri)>;
-def 4GM7WriteSHA1RNDS4rmi:SchedWriteRes<[4GM7AGU, 4GM7Load, 4GM7FPU02]> {
- let Latency = !add(C864GM7Model.VecLoadLatency, 4GM7WriteSHA1RNDS4rri.Latency);
+def C4GM7WriteSHA1RNDS4rmi:SchedWriteRes<[C4GM7AGU, C4GM7Load, C4GM7FPU02]> {
+ let Latency = !add(C864GM7Model.VecLoadLatency, C4GM7WriteSHA1RNDS4rri.Latency);
let ReleaseAtCycles = [1, 1, 8];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteSHA1RNDS4rmi], (instrs SHA1RNDS4rmi)>;
+def : InstRW<[C4GM7WriteSHA1RNDS4rmi], (instrs SHA1RNDS4rmi)>;
-defm : 4GM7WriteRes<WriteFence, [4GM7AGU]>;
-defm : 4GM7WriteRes<WriteNop, []>;
+defm : C4GM7WriteRes<WriteFence, [C4GM7AGU]>;
+defm : C4GM7WriteRes<WriteNop, []>;
//===----------------------------------------------------------------------===//
// Zero Cycle Move
//===----------------------------------------------------------------------===//
-def 4GM7WriteZeroLatency : SchedWriteRes<[]> {
+def C4GM7WriteZeroLatency : SchedWriteRes<[]> {
let Latency = 0;
let ReleaseAtCycles = [];
let NumMicroOps = 1;
}
-def : InstRW<[4GM7WriteZeroLatency], (instrs MOV32rr, MOV32rr_REV,
- MOV64rr, MOV64rr_REV,
- MOVSX32rr32)>;
+def : InstRW<[C4GM7WriteZeroLatency], (instrs MOV32rr, MOV32rr_REV,
+ MOV64rr, MOV64rr_REV,
+ MOVSX32rr32)>;
-def 4GM7WriteSwapRenameable : SchedWriteRes<[]> {
+def C4GM7WriteSwapRenameable : SchedWriteRes<[]> {
let Latency = 0;
let ReleaseAtCycles = [];
let NumMicroOps = 2;
}
-def : InstRW<[4GM7WriteSwapRenameable], (instrs XCHG32rr, XCHG32ar,
- XCHG64rr, XCHG64ar)>;
+def : InstRW<[C4GM7WriteSwapRenameable], (instrs XCHG32rr, XCHG32ar,
+ XCHG64rr, XCHG64ar)>;
-defm : 4GM7WriteRes<WriteXCHG, [4GM7ALU], 0, [8], 2>;
+defm : C4GM7WriteRes<WriteXCHG, [C4GM7ALU], 0, [8], 2>;
-defm : 4GM7WriteRes<WriteFMoveX, [], 0, [], 1>;
-defm : 4GM7WriteRes<WriteFMoveY, [], 0, [], 1>;
-defm : 4GM7WriteRes<WriteFMoveZ, [], 0, [], 1>;
+defm : C4GM7WriteRes<WriteFMoveX, [], 0, [], 1>;
+defm : C4GM7WriteRes<WriteFMoveY, [], 0, [], 1>;
+defm : C4GM7WriteRes<WriteFMoveZ, [], 0, [], 1>;
-defm : 4GM7WriteRes<WriteVecMove, [], 0, [], 1>;
-defm : 4GM7WriteRes<WriteVecMoveX, [], 0, [], 1>;
-defm : 4GM7WriteRes<WriteVecMoveY, [], 0, [], 1>;
-defm : 4GM7WriteRes<WriteVecMoveZ, [], 0, [], 1>;
+defm : C4GM7WriteRes<WriteVecMove, [], 0, [], 1>;
+defm : C4GM7WriteRes<WriteVecMoveX, [], 0, [], 1>;
+defm : C4GM7WriteRes<WriteVecMoveY, [], 0, [], 1>;
+defm : C4GM7WriteRes<WriteVecMoveZ, [], 0, [], 1>;
def : IsOptimizableRegisterMove<[
InstructionEquivalenceClass<[
@@ -3510,113 +3510,113 @@ def : IsOptimizableRegisterMove<[
// Dependency breaking instructions.
//===----------------------------------------------------------------------===//
-def 4GM7WriteZeroIdiom : SchedWriteVariant<[
- SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM7WriteZeroLatency]>,
+def C4GM7WriteZeroIdiom : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [C4GM7WriteZeroLatency]>,
SchedVar<NoSchedPred, [WriteALU]>
]>;
-def : InstRW<[4GM7WriteZeroIdiom], (instrs XOR32rr, XOR32rr_REV,
- XOR64rr, XOR64rr_REV,
- SUB32rr, SUB32rr_REV,
- SUB64rr, SUB64rr_REV)>;
+def : InstRW<[C4GM7WriteZeroIdiom], (instrs XOR32rr, XOR32rr_REV,
+ XOR64rr, XOR64rr_REV,
+ SUB32rr, SUB32rr_REV,
+ SUB64rr, SUB64rr_REV)>;
-def 4GM7WriteZeroIdiomEFLAGS : SchedWriteVariant<[
- SchedVar<MCSchedPredicate<CheckSameRegOperand<0, 1>>, [4GM7WriteZeroLatency]>,
+def C4GM7WriteZeroIdiomEFLAGS : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<CheckSameRegOperand<0, 1>>, [C4GM7WriteZeroLatency]>,
SchedVar<NoSchedPred, [WriteALU]>
]>;
-def : InstRW<[4GM7WriteZeroIdiomEFLAGS], (instrs CMP8rr, CMP8rr_REV,
- CMP16rr, CMP16rr_REV,
- CMP32rr, CMP32rr_REV,
- CMP64rr, CMP64rr_REV)>;
+def : InstRW<[C4GM7WriteZeroIdiomEFLAGS], (instrs CMP8rr, CMP8rr_REV,
+ CMP16rr, CMP16rr_REV,
+ CMP32rr, CMP32rr_REV,
+ CMP64rr, CMP64rr_REV)>;
-def 4GM7WriteFZeroIdiom : SchedWriteVariant<[
- SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM7WriteZeroLatency]>,
+def C4GM7WriteFZeroIdiom : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [C4GM7WriteZeroLatency]>,
SchedVar<NoSchedPred, [WriteFLogic]>
]>;
-def : InstRW<[4GM7WriteFZeroIdiom], (instrs VXORPSrr, VXORPDrr,
- VXORPSZ128rr,
- VXORPDZ128rr,
- VANDNPSrr, VANDNPDrr,
- VANDNPSZ128rr,
- VANDNPDZ128rr)>;
+def : InstRW<[C4GM7WriteFZeroIdiom], (instrs VXORPSrr, VXORPDrr,
+ VXORPSZ128rr,
+ VXORPDZ128rr,
+ VANDNPSrr, VANDNPDrr,
+ VANDNPSZ128rr,
+ VANDNPDZ128rr)>;
-def 4GM7WriteFZeroIdiomY : SchedWriteVariant<[
- SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM7WriteZeroLatency]>,
+def C4GM7WriteFZeroIdiomY : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [C4GM7WriteZeroLatency]>,
SchedVar<NoSchedPred, [WriteFLogicY]>
]>;
-def : InstRW<[4GM7WriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr,
- VXORPSZ256rr,
- VXORPDZ256rr,
- VANDNPSYrr, VANDNPDYrr,
- VANDNPSZ256rr,
- VANDNPDZ256rr)>;
-
-def 4GM7WriteFZeroIdiomZ : SchedWriteVariant<[
- SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM7WriteZeroLatency]>,
+def : InstRW<[C4GM7WriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr,
+ VXORPSZ256rr,
+ VXORPDZ256rr,
+ VANDNPSYrr, VANDNPDYrr,
+ VANDNPSZ256rr,
+ VANDNPDZ256rr)>;
+
+def C4GM7WriteFZeroIdiomZ : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [C4GM7WriteZeroLatency]>,
SchedVar<NoSchedPred, [WriteFLogicZ]>
]>;
-def : InstRW<[4GM7WriteFZeroIdiomZ], (instrs VXORPSZrr, VXORPDZrr,
- VANDNPSZrr, VANDNPDZrr)>;
+def : InstRW<[C4GM7WriteFZeroIdiomZ], (instrs VXORPSZrr, VXORPDZrr,
+ VANDNPSZrr, VANDNPDZrr)>;
-def 4GM7WriteVZeroIdiomLogicX : SchedWriteVariant<[
- SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM7WriteZeroLatency]>,
+def C4GM7WriteVZeroIdiomLogicX : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [C4GM7WriteZeroLatency]>,
SchedVar<NoSchedPred, [WriteVecLogicX]>
]>;
-def : InstRW<[4GM7WriteVZeroIdiomLogicX], (instrs VPXORrr,
- VPXORDZ128rr,
- VPXORQZ128rr,
- VPANDNrr,
- VPANDNDZ128rr,
- VPANDNQZ128rr)>;
+def : InstRW<[C4GM7WriteVZeroIdiomLogicX], (instrs VPXORrr,
+ VPXORDZ128rr,
+ VPXORQZ128rr,
+ VPANDNrr,
+ VPANDNDZ128rr,
+ VPANDNQZ128rr)>;
-def 4GM7WriteVZeroIdiomLogicY : SchedWriteVariant<[
- SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM7WriteZeroLatency]>,
+def C4GM7WriteVZeroIdiomLogicY : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [C4GM7WriteZeroLatency]>,
SchedVar<NoSchedPred, [WriteVecLogicY]>
]>;
-def : InstRW<[4GM7WriteVZeroIdiomLogicY], (instrs VPXORYrr,
- VPXORDZ256rr,
- VPXORQZ256rr,
- VPANDNYrr,
- VPANDNDZ256rr,
- VPANDNQZ256rr)>;
-
-def 4GM7WriteVZeroIdiomLogicZ : SchedWriteVariant<[
- SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM7WriteZeroLatency]>,
+def : InstRW<[C4GM7WriteVZeroIdiomLogicY], (instrs VPXORYrr,
+ VPXORDZ256rr,
+ VPXORQZ256rr,
+ VPANDNYrr,
+ VPANDNDZ256rr,
+ VPANDNQZ256rr)>;
+
+def C4GM7WriteVZeroIdiomLogicZ : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [C4GM7WriteZeroLatency]>,
SchedVar<NoSchedPred, [WriteVecLogicZ]>
]>;
-def : InstRW<[4GM7WriteVZeroIdiomLogicZ], (instrs VPXORDZrr, VPXORQZrr,
- VPANDNDZrr, VPANDNQZrr)>;
+def : InstRW<[C4GM7WriteVZeroIdiomLogicZ], (instrs VPXORDZrr, VPXORQZrr,
+ VPANDNDZrr, VPANDNQZrr)>;
-def 4GM7WriteVZeroIdiomALUX : SchedWriteVariant<[
- SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM7WriteZeroLatency]>,
+def C4GM7WriteVZeroIdiomALUX : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [C4GM7WriteZeroLatency]>,
SchedVar<NoSchedPred, [WriteVecALUX]>
]>;
-def : InstRW<[4GM7WriteVZeroIdiomALUX],
+def : InstRW<[C4GM7WriteVZeroIdiomALUX],
(instrs VPSUBBrr, VPSUBWrr, VPSUBDrr, VPSUBQrr,
VPSUBBZ128rr, VPSUBWZ128rr, VPSUBDZ128rr, VPSUBQZ128rr,
VPCMPGTBrr, VPCMPGTWrr, VPCMPGTDrr, VPCMPGTQrr,
VPCMPGTBZ128rr, VPCMPGTWZ128rr,
VPCMPGTDZ128rr, VPCMPGTQZ128rr)>;
-def 4GM7WriteVZeroIdiomALUY : SchedWriteVariant<[
- SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM7WriteZeroLatency]>,
+def C4GM7WriteVZeroIdiomALUY : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [C4GM7WriteZeroLatency]>,
SchedVar<NoSchedPred, [WriteVecALUY]>
]>;
-def : InstRW<[4GM7WriteVZeroIdiomALUY],
+def : InstRW<[C4GM7WriteVZeroIdiomALUY],
(instrs VPSUBBYrr, VPSUBWYrr, VPSUBDYrr, VPSUBQYrr,
VPSUBBZ256rr, VPSUBWZ256rr, VPSUBDZ256rr, VPSUBQZ256rr,
VPCMPGTBYrr, VPCMPGTWYrr, VPCMPGTDYrr, VPCMPGTQYrr,
VPCMPGTBZ256rr, VPCMPGTWZ256rr,
VPCMPGTDZ256rr, VPCMPGTQZ256rr)>;
-def 4GM7WriteVZeroIdiomALUZ : SchedWriteVariant<[
- SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [4GM7WriteZeroLatency]>,
+def C4GM7WriteVZeroIdiomALUZ : SchedWriteVariant<[
+ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [C4GM7WriteZeroLatency]>,
SchedVar<NoSchedPred, [WriteVecALUZ]>
]>;
-def : InstRW<[4GM7WriteVZeroIdiomALUY],
+def : InstRW<[C4GM7WriteVZeroIdiomALUY],
(instrs VPSUBBZrr, VPSUBWZrr, VPSUBDZrr, VPSUBQZrr,
VPCMPGTBZrr, VPCMPGTWZrr, VPCMPGTDZrr, VPCMPGTQZrr)>;
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-adx.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-adx.s
index 97ac4c0b59242..d058e86ad2e82 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-adx.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-adx.s
@@ -30,25 +30,25 @@ adox (%rbx), %rcx
# CHECK-NEXT: 1 5 0.50 * adoxq (%rbx), %rcx
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-aes.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-aes.s
index 7d15f2c3b0e2b..ba27ced8de06a 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-aes.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-aes.s
@@ -42,25 +42,25 @@ aeskeygenassist $22, (%rax), %xmm2
# CHECK-NEXT: 1 11 0.50 * aeskeygenassist $22, (%rax), %xmm2
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-avx1.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-avx1.s
index 89282a4c67e16..25c20d347b185 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-avx1.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-avx1.s
@@ -1723,25 +1723,25 @@ vzeroupper
# CHECK-NEXT: 1 100 0.25 U vzeroupper
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-avx2.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-avx2.s
index bf21daa91aa1d..9ec1cc9d2a3c8 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-avx2.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-avx2.s
@@ -763,25 +763,25 @@ vpxor (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 8 0.50 * vpxor (%rax), %ymm1, %ymm2
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-bmi1.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-bmi1.s
index 9390c311497ee..3782f6951356c 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-bmi1.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-bmi1.s
@@ -77,25 +77,25 @@ tzcnt (%rax), %rcx
# CHECK-NEXT: 6 6 0.33 * tzcntq (%rax), %rcx
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-bmi2.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-bmi2.s
index dda307e7f47a2..e39c767bb04cb 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-bmi2.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-bmi2.s
@@ -92,25 +92,25 @@ shrx %rax, (%rbx), %rcx
# CHECK-NEXT: 1 5 0.50 * shrxq %rax, (%rbx), %rcx
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-clflushopt.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-clflushopt.s
index c30b36d482d99..3ad3ffe62c3aa 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-clflushopt.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-clflushopt.s
@@ -15,25 +15,25 @@ clflushopt (%rax)
# CHECK-NEXT: 1 5 0.50 * * U clflushopt (%rax)
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-clzero.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-clzero.s
index 49cfad21a0dcd..a0be79ec3e498 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-clzero.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-clzero.s
@@ -15,25 +15,25 @@ clzero
# CHECK-NEXT: 1 5 0.50 U clzero
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-cmov.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-cmov.s
index 299eaeb410909..c8cf3db0956e3 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-cmov.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-cmov.s
@@ -210,25 +210,25 @@ cmovgq (%rax), %rdi
# CHECK-NEXT: 1 5 0.50 * cmovgq (%rax), %rdi
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-cmpxchg.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-cmpxchg.s
index e95bb3c77a268..11c58e5f10431 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-cmpxchg.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-cmpxchg.s
@@ -21,25 +21,25 @@ lock cmpxchg16b (%rax)
# CHECK-NEXT: 3 5 0.33 * * lock cmpxchg16b (%rax)
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-f16c.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-f16c.s
index cd714d5b9daf7..aece24a9e0132 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-f16c.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-f16c.s
@@ -32,25 +32,25 @@ vcvtps2ph $0, %ymm0, (%rax)
# CHECK-NEXT: 3 10 2.00 * vcvtps2ph $0, %ymm0, (%rax)
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-fma.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-fma.s
index 9695dad251087..eefe7e1cc4292 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-fma.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-fma.s
@@ -492,25 +492,25 @@ vfnmsub231ss (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 12 0.50 * vfnmsub231ss (%rax), %xmm1, %xmm2
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-fsgsbase.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-fsgsbase.s
index 2081e76900ad2..7831bbbba9066 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-fsgsbase.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-fsgsbase.s
@@ -32,25 +32,25 @@ wrgsbase %rdi
# CHECK-NEXT: 1 100 0.25 * * U wrgsbaseq %rdi
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-lea.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-lea.s
index 1d107c38784e8..98b1a357c3f8a 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-lea.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-lea.s
@@ -285,25 +285,25 @@ lea 1024(%rax, %rbx, 2), %rcx
# CHECK-NEXT: 2 2 0.50 leaq 1024(%rax,%rbx,2), %rcx
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-lzcnt.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-lzcnt.s
index 6477fc7c1a809..e8aa8ef5f1bb5 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-lzcnt.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-lzcnt.s
@@ -27,25 +27,25 @@ lzcntq (%rax), %rcx
# CHECK-NEXT: 1 5 0.50 * lzcntq (%rax), %rcx
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-mmx.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-mmx.s
index b28973e12b598..cd6855eb1fd7f 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-mmx.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-mmx.s
@@ -271,25 +271,25 @@ pxor (%rax), %mm2
# CHECK-NEXT: 1 8 0.50 * pxor (%rax), %mm2
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-movbe.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-movbe.s
index 3cdc93d6cb4a2..ee80c35a6a356 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-movbe.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-movbe.s
@@ -27,25 +27,25 @@ movbe (%rax), %rcx
# CHECK-NEXT: 1 5 0.50 * movbeq (%rax), %rcx
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-mwaitx.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-mwaitx.s
index e362aae6586d9..d30315f56ac4c 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-mwaitx.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-mwaitx.s
@@ -17,25 +17,25 @@ mwaitx
# CHECK-NEXT: 1 100 0.25 U mwaitx
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-pclmul.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-pclmul.s
index 2710726ce22ce..17d4034689804 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-pclmul.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-pclmul.s
@@ -17,25 +17,25 @@ pclmulqdq $11, (%rax), %xmm2
# CHECK-NEXT: 1 10 1.00 * pclmulqdq $11, (%rax), %xmm2
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-popcnt.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-popcnt.s
index 73d184b8e2b90..cdc4d1ac29d10 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-popcnt.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-popcnt.s
@@ -27,25 +27,25 @@ popcntq (%rax), %rcx
# CHECK-NEXT: 5 5 0.33 * popcntq (%rax), %rcx
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-prefetchw.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-prefetchw.s
index 6304f7d3ec5cb..e2e97306f3c50 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-prefetchw.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-prefetchw.s
@@ -17,25 +17,25 @@ prefetchw (%rax)
# CHECK-NEXT: 1 5 0.50 * * prefetchw (%rax)
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-rdrand.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-rdrand.s
index 9a1515bf77083..6f96fdfa7d4e1 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-rdrand.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-rdrand.s
@@ -19,25 +19,25 @@ rdrand %rax
# CHECK-NEXT: 1 100 0.25 U rdrandq %rax
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-rdseed.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-rdseed.s
index 8761f20a3545b..11f50ab8c0454 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-rdseed.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-rdseed.s
@@ -19,25 +19,25 @@ rdseed %rax
# CHECK-NEXT: 1 100 0.25 U rdseedq %rax
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-sha.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-sha.s
index b026d9f733c7e..0b073af6de095 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-sha.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-sha.s
@@ -47,25 +47,25 @@ sha256rnds2 (%rax), %xmm2
# CHECK-NEXT: 1 11 1.00 * sha256rnds2 %xmm0, (%rax), %xmm2
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse1.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse1.s
index 0f141a305d666..e396f0281498f 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse1.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse1.s
@@ -320,25 +320,25 @@ xorps (%rax), %xmm2
# CHECK-NEXT: 1 8 0.50 * xorps (%rax), %xmm2
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse2.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse2.s
index d269e853b7535..99c7d0da6b54a 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse2.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse2.s
@@ -676,25 +676,25 @@ xorpd (%rax), %xmm2
# CHECK-NEXT: 1 8 0.50 * xorpd (%rax), %xmm2
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse3.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse3.s
index fc6ed3f89a153..bac9c3479f016 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse3.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse3.s
@@ -66,25 +66,25 @@ mwait
# CHECK-NEXT: 1 100 0.25 * * U mwait
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse41.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse41.s
index 78ac11ad6f163..a82d1f18bace4 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse41.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse41.s
@@ -253,25 +253,25 @@ roundss $1, (%rax), %xmm2
# CHECK-NEXT: 8 11 1.00 * roundss $1, (%rax), %xmm2
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse42.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse42.s
index 070b0aac36cbc..ac2d7eedb9093 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse42.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse42.s
@@ -62,25 +62,25 @@ pcmpgtq (%rax), %xmm2
# CHECK-NEXT: 1 8 0.50 * pcmpgtq (%rax), %xmm2
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse4a.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse4a.s
index 6ac045f4f3640..edd42fe07de5f 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse4a.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse4a.s
@@ -27,25 +27,25 @@ movntss %xmm0, (%rax)
# CHECK-NEXT: 1 5 1.00 * movntss %xmm0, (%rax)
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-ssse3.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-ssse3.s
index c9408d820add8..1cf417e5ced60 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-ssse3.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-ssse3.s
@@ -172,25 +172,25 @@ psignw (%rax), %xmm2
# CHECK-NEXT: 1 8 0.50 * psignw (%rax), %xmm2
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-x86_32.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-x86_32.s
index 8a35d6e33c0b7..ae53862b89da4 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-x86_32.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-x86_32.s
@@ -48,25 +48,25 @@ salc
# CHECK-NEXT: 1 1 0.17 U salc
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-x86_64.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-x86_64.s
index 516ab85e6dba8..1d85010030af4 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-x86_64.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-x86_64.s
@@ -1292,10 +1292,10 @@ xorq (%rax), %rdi
# CHECK-NEXT: 1 1 0.17 cmpq %rsi, %rdi
# CHECK-NEXT: 1 5 0.50 * cmpq %rsi, (%rax)
# CHECK-NEXT: 1 5 0.50 * cmpq (%rax), %rdi
-# CHECK-NEXT: 1 100 0.25 U cmpsb %es:(%rdi), (%rsi)
-# CHECK-NEXT: 1 100 0.25 U cmpsw %es:(%rdi), (%rsi)
-# CHECK-NEXT: 1 100 0.25 U cmpsl %es:(%rdi), (%rsi)
-# CHECK-NEXT: 1 100 0.25 U cmpsq %es:(%rdi), (%rsi)
+# CHECK-NEXT: 1 100 0.25 * U cmpsb %es:(%rdi), (%rsi)
+# CHECK-NEXT: 1 100 0.25 * U cmpsw %es:(%rdi), (%rsi)
+# CHECK-NEXT: 1 100 0.25 * U cmpsl %es:(%rdi), (%rsi)
+# CHECK-NEXT: 1 100 0.25 * U cmpsq %es:(%rdi), (%rsi)
# CHECK-NEXT: 1 3 0.17 cmpxchgb %cl, %bl
# CHECK-NEXT: 3 5 0.33 * * cmpxchgb %cl, (%rbx)
# CHECK-NEXT: 3 5 0.33 * * lock cmpxchgb %cl, (%rbx)
@@ -1390,17 +1390,17 @@ xorq (%rax), %rdi
# CHECK-NEXT: 1 100 0.25 U invlpga
# CHECK-NEXT: 2 2 0.17 lahf
# CHECK-NEXT: 1 1 0.17 * leave
-# CHECK-NEXT: 1 100 0.25 U lodsb (%rsi), %al
-# CHECK-NEXT: 1 100 0.25 U lodsw (%rsi), %ax
-# CHECK-NEXT: 1 100 0.25 U lodsl (%rsi), %eax
-# CHECK-NEXT: 1 100 0.25 U lodsq (%rsi), %rax
+# CHECK-NEXT: 1 100 0.25 * U lodsb (%rsi), %al
+# CHECK-NEXT: 1 100 0.25 * U lodsw (%rsi), %ax
+# CHECK-NEXT: 1 100 0.25 * U lodsl (%rsi), %eax
+# CHECK-NEXT: 1 100 0.25 * U lodsq (%rsi), %rax
# CHECK-NEXT: 1 1 0.17 U loop 0
# CHECK-NEXT: 1 1 0.17 U loope 0
# CHECK-NEXT: 1 1 0.17 U loopne 0
-# CHECK-NEXT: 1 100 0.25 U movsb (%rsi), %es:(%rdi)
-# CHECK-NEXT: 1 100 0.25 U movsw (%rsi), %es:(%rdi)
-# CHECK-NEXT: 1 100 0.25 U movsl (%rsi), %es:(%rdi)
-# CHECK-NEXT: 1 100 0.25 U movsq (%rsi), %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 * * U movsb (%rsi), %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 * * U movsw (%rsi), %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 * * U movsl (%rsi), %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 * * U movsq (%rsi), %es:(%rdi)
# CHECK-NEXT: 1 1 0.17 movsbw %al, %di
# CHECK-NEXT: 1 1 0.17 movzbw %al, %di
# CHECK-NEXT: 1 5 0.50 * movsbw (%rax), %di
@@ -1743,10 +1743,10 @@ xorq (%rax), %rdi
# CHECK-NEXT: 2 6 0.67 * * sbbq %rsi, (%rax)
# CHECK-NEXT: 2 6 0.67 * * lock sbbq %rsi, (%rax)
# CHECK-NEXT: 1 5 0.50 * sbbq (%rax), %rdi
-# CHECK-NEXT: 1 100 0.25 U scasb %es:(%rdi), %al
-# CHECK-NEXT: 1 100 0.25 U scasw %es:(%rdi), %ax
-# CHECK-NEXT: 1 100 0.25 U scasl %es:(%rdi), %eax
-# CHECK-NEXT: 1 100 0.25 U scasq %es:(%rdi), %rax
+# CHECK-NEXT: 1 100 0.25 * U scasb %es:(%rdi), %al
+# CHECK-NEXT: 1 100 0.25 * U scasw %es:(%rdi), %ax
+# CHECK-NEXT: 1 100 0.25 * U scasl %es:(%rdi), %eax
+# CHECK-NEXT: 1 100 0.25 * U scasq %es:(%rdi), %rax
# CHECK-NEXT: 1 1 0.17 seto %al
# CHECK-NEXT: 1 1 0.33 * seto (%rax)
# CHECK-NEXT: 1 1 0.17 setno %al
@@ -1805,10 +1805,10 @@ xorq (%rax), %rdi
# CHECK-NEXT: 8 5 0.83 * * shrdq $7, %rsi, (%rax)
# CHECK-NEXT: 1 1 0.17 U stc
# CHECK-NEXT: 1 1 0.17 U std
-# CHECK-NEXT: 1 100 0.25 U stosb %al, %es:(%rdi)
-# CHECK-NEXT: 1 100 0.25 U stosw %ax, %es:(%rdi)
-# CHECK-NEXT: 1 100 0.25 U stosl %eax, %es:(%rdi)
-# CHECK-NEXT: 1 100 0.25 U stosq %rax, %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 * U stosb %al, %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 * U stosw %ax, %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 * U stosl %eax, %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 * U stosq %rax, %es:(%rdi)
# CHECK-NEXT: 1 1 0.17 subb $7, %al
# CHECK-NEXT: 1 1 0.17 subb $7, %dil
# CHECK-NEXT: 2 6 0.67 * * subb $7, (%rax)
@@ -1949,25 +1949,25 @@ xorq (%rax), %rdi
# CHECK-NEXT: 1 5 0.50 * xorq (%rax), %rdi
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-x87.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-x87.s
index 137fe8dc521ec..0d7e38ceb2835 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-x87.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-x87.s
@@ -356,25 +356,25 @@ fyl2xp1
# CHECK-NEXT: 1 100 0.25 U fyl2xp1
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-xsave.s b/llvm/test/tools/llvm-mca/X86/4GM4/resources-xsave.s
index dabd74a11c322..a6964880c1ef9 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/resources-xsave.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/resources-xsave.s
@@ -27,25 +27,25 @@ xsetbv
# CHECK-NEXT: 1 100 0.25 * * U xsetbv
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/zero-idioms.s b/llvm/test/tools/llvm-mca/X86/4GM4/zero-idioms.s
index fa96aa36589b6..5a4a528a5be29 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/zero-idioms.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM4/zero-idioms.s
@@ -205,36 +205,36 @@ vpxor %ymm3, %ymm3, %ymm5
# CHECK-NEXT: Total number of mappings created: 9
# CHECK-NEXT: Max number of mappings used: 4
-# CHECK: * Register File #1 -- 4GM4FpuPRF:
+# CHECK: * Register File #1 -- C4GM4FpuPRF:
# CHECK-NEXT: Number of physical registers: 176
# CHECK-NEXT: Total number of mappings created: 9
# CHECK-NEXT: Max number of mappings used: 4
-# CHECK: * Register File #2 -- 4GM4IntegerPRF:
+# CHECK: * Register File #2 -- C4GM4IntegerPRF:
# CHECK-NEXT: Number of physical registers: 192
# CHECK-NEXT: Total number of mappings created: 0
# CHECK-NEXT: Max number of mappings used: 0
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM4AGU0
-# CHECK-NEXT: [1] - 4GM4AGU1
-# CHECK-NEXT: [2] - 4GM4AGU2
-# CHECK-NEXT: [3] - 4GM4ALU0
-# CHECK-NEXT: [4] - 4GM4ALU1
-# CHECK-NEXT: [5] - 4GM4ALU2
-# CHECK-NEXT: [6] - 4GM4ALU3
-# CHECK-NEXT: [7] - 4GM4FPU0
-# CHECK-NEXT: [8] - 4GM4FPU1
-# CHECK-NEXT: [9] - 4GM4FPU2
-# CHECK-NEXT: [10] - 4GM4FPU3
-# CHECK-NEXT: [11.0] - 4GM4LSU
-# CHECK-NEXT: [11.1] - 4GM4LSU
-# CHECK-NEXT: [11.2] - 4GM4LSU
-# CHECK-NEXT: [12.0] - 4GM4Load
-# CHECK-NEXT: [12.1] - 4GM4Load
-# CHECK-NEXT: [13.0] - 4GM4Store
-# CHECK-NEXT: [13.1] - 4GM4Store
-# CHECK-NEXT: [13.2] - 4GM4Store
+# CHECK-NEXT: [0] - C4GM4AGU0
+# CHECK-NEXT: [1] - C4GM4AGU1
+# CHECK-NEXT: [2] - C4GM4AGU2
+# CHECK-NEXT: [3] - C4GM4ALU0
+# CHECK-NEXT: [4] - C4GM4ALU1
+# CHECK-NEXT: [5] - C4GM4ALU2
+# CHECK-NEXT: [6] - C4GM4ALU3
+# CHECK-NEXT: [7] - C4GM4FPU0
+# CHECK-NEXT: [8] - C4GM4FPU1
+# CHECK-NEXT: [9] - C4GM4FPU2
+# CHECK-NEXT: [10] - C4GM4FPU3
+# CHECK-NEXT: [11.0] - C4GM4LSU
+# CHECK-NEXT: [11.1] - C4GM4LSU
+# CHECK-NEXT: [11.2] - C4GM4LSU
+# CHECK-NEXT: [12.0] - C4GM4Load
+# CHECK-NEXT: [12.1] - C4GM4Load
+# CHECK-NEXT: [13.0] - C4GM4Store
+# CHECK-NEXT: [13.1] - C4GM4Store
+# CHECK-NEXT: [13.2] - C4GM4Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [11.2] [12.0] [12.1] [13.0] [13.1] [13.2]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/independent-load-stores.s b/llvm/test/tools/llvm-mca/X86/4GM7/independent-load-stores.s
index bd3e2c7626ad3..51fba2a2b5cb5 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/independent-load-stores.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/independent-load-stores.s
@@ -52,29 +52,29 @@
# ALL-NEXT: 1 6 0.67 * * addq $44, 640(%r14)
# ALL: Resources:
-# ALL-NEXT: [0] - 4GM7AGU0
-# ALL-NEXT: [1] - 4GM7AGU1
-# ALL-NEXT: [2] - 4GM7AGU2
-# ALL-NEXT: [3] - 4GM7ALU0
-# ALL-NEXT: [4] - 4GM7ALU1
-# ALL-NEXT: [5] - 4GM7ALU2
-# ALL-NEXT: [6] - 4GM7ALU3
-# ALL-NEXT: [7] - 4GM7BRU1
-# ALL-NEXT: [8] - 4GM7FPU0
-# ALL-NEXT: [9] - 4GM7FPU1
-# ALL-NEXT: [10] - 4GM7FPU2
-# ALL-NEXT: [11] - 4GM7FPU3
-# ALL-NEXT: [12.0] - 4GM7LSU
-# ALL-NEXT: [12.1] - 4GM7LSU
-# ALL-NEXT: [12.2] - 4GM7LSU
-# ALL-NEXT: [12.3] - 4GM7LSU
-# ALL-NEXT: [13.0] - 4GM7Load
-# ALL-NEXT: [13.1] - 4GM7Load
-# ALL-NEXT: [13.2] - 4GM7Load
-# ALL-NEXT: [14.0] - 4GM7Store
-# ALL-NEXT: [14.1] - 4GM7Store
-# ALL-NEXT: [14.2] - 4GM7Store
-# ALL-NEXT: [14.3] - 4GM7Store
+# ALL-NEXT: [0] - C4GM7AGU0
+# ALL-NEXT: [1] - C4GM7AGU1
+# ALL-NEXT: [2] - C4GM7AGU2
+# ALL-NEXT: [3] - C4GM7ALU0
+# ALL-NEXT: [4] - C4GM7ALU1
+# ALL-NEXT: [5] - C4GM7ALU2
+# ALL-NEXT: [6] - C4GM7ALU3
+# ALL-NEXT: [7] - C4GM7BRU1
+# ALL-NEXT: [8] - C4GM7FPU0
+# ALL-NEXT: [9] - C4GM7FPU1
+# ALL-NEXT: [10] - C4GM7FPU2
+# ALL-NEXT: [11] - C4GM7FPU3
+# ALL-NEXT: [12.0] - C4GM7LSU
+# ALL-NEXT: [12.1] - C4GM7LSU
+# ALL-NEXT: [12.2] - C4GM7LSU
+# ALL-NEXT: [12.3] - C4GM7LSU
+# ALL-NEXT: [13.0] - C4GM7Load
+# ALL-NEXT: [13.1] - C4GM7Load
+# ALL-NEXT: [13.2] - C4GM7Load
+# ALL-NEXT: [14.0] - C4GM7Store
+# ALL-NEXT: [14.1] - C4GM7Store
+# ALL-NEXT: [14.2] - C4GM7Store
+# ALL-NEXT: [14.3] - C4GM7Store
# ALL: Resource pressure per iteration:
# ALL-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/partially-overlapping-group-resources.s b/llvm/test/tools/llvm-mca/X86/4GM7/partially-overlapping-group-resources.s
index 595bc4c310586..cdcbddf762de8 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/partially-overlapping-group-resources.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/partially-overlapping-group-resources.s
@@ -37,29 +37,29 @@ vpxord zmm1, zmm1, zmm1
# CHECK-NEXT: 1 0 0.25 vpxord zmm1, zmm1, zmm1
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-adx.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-adx.s
index fbc39b5675ebb..07fa181160de6 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-adx.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-adx.s
@@ -30,29 +30,29 @@ adox (%rbx), %rcx
# CHECK-NEXT: 1 5 0.33 * adoxq (%rbx), %rcx
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-aes.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-aes.s
index 485a87bd3510b..1b6e65e7f1940 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-aes.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-aes.s
@@ -42,29 +42,29 @@ aeskeygenassist $22, (%rax), %xmm2
# CHECK-NEXT: 1 10 0.50 * aeskeygenassist $22, (%rax), %xmm2
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx1.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx1.s
index 298157418cef0..b9ac41ea902f7 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx1.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx1.s
@@ -1723,29 +1723,29 @@ vzeroupper
# CHECK-NEXT: 1 100 0.25 U vzeroupper
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx2.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx2.s
index 7a7be4de64f7f..abcab4f45dda3 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx2.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx2.s
@@ -763,29 +763,29 @@ vpxor (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 8 0.33 * vpxor (%rax), %ymm1, %ymm2
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512.s
index 3351cc25b2cf3..853f88db8da0a 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512.s
@@ -2207,29 +2207,29 @@ vunpcklps (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
# CHECK-NEXT: 1 8 1.00 * vunpcklps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bitalg.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bitalg.s
index ebe71e453be60..04549fc661907 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bitalg.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bitalg.s
@@ -47,29 +47,29 @@ vpshufbitqmb (%rdi), %zmm17, %k2 {%k1}
# CHECK-NEXT: 3 17 4.00 * vpshufbitqmb (%rdi), %zmm17, %k2 {%k1}
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bitalgvl.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bitalgvl.s
index 313ddcd4328fc..4b50fd08f1e2d 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bitalgvl.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bitalgvl.s
@@ -82,29 +82,29 @@ vpshufbitqmb (%rdi), %ymm17, %k2 {%k1}
# CHECK-NEXT: 2 15 2.00 * vpshufbitqmb (%rdi), %ymm17, %k2 {%k1}
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bw.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bw.s
index 04cca64162749..7ae6c0a591bb0 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bw.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bw.s
@@ -1119,29 +1119,29 @@ vpunpcklwd (%rax), %zmm17, %zmm19 {z}{k1}
# CHECK-NEXT: 1 9 1.00 * vpunpcklwd (%rax), %zmm17, %zmm19 {%k1} {z}
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bwvl.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bwvl.s
index befca44e4e112..c16344f1ef982 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bwvl.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bwvl.s
@@ -2022,29 +2022,29 @@ vpunpcklwd (%rax), %ymm17, %ymm19 {z}{k1}
# CHECK-NEXT: 1 9 0.50 * vpunpcklwd (%rax), %ymm17, %ymm19 {%k1} {z}
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512cd.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512cd.s
index e87aad4ba99ad..b43a06c5ca1f7 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512cd.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512cd.s
@@ -94,29 +94,29 @@ vplzcntq (%rax){1to8}, %zmm19 {z}{k1}
# CHECK-NEXT: 1 10 1.00 * vplzcntq (%rax){1to8}, %zmm19 {%k1} {z}
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512cdvl.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512cdvl.s
index 05198c2143416..14edcff734f16 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512cdvl.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512cdvl.s
@@ -174,29 +174,29 @@ vplzcntq (%rax){1to4}, %ymm19 {z}{k1}
# CHECK-NEXT: 1 10 0.50 * vplzcntq (%rax){1to4}, %ymm19 {%k1} {z}
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512dq.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512dq.s
index 05f181620aa46..df39e42f9fcf5 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512dq.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512dq.s
@@ -857,29 +857,29 @@ vxorps (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
# CHECK-NEXT: 1 8 0.33 * vxorps (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512dqvl.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512dqvl.s
index c126778216035..6a25c7ab81d8d 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512dqvl.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512dqvl.s
@@ -1123,29 +1123,29 @@ vxorps (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
# CHECK-NEXT: 1 8 0.33 * vxorps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512gfni.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512gfni.s
index 2e011ea7eb66e..ebc7a36508476 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512gfni.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512gfni.s
@@ -63,29 +63,29 @@ vgf2p8mulb (%rax), %zmm17, %zmm19 {z}{k1}
# CHECK-NEXT: 2 10 1.00 * vgf2p8mulb (%rax), %zmm17, %zmm19 {%k1} {z}
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512gfnivl.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512gfnivl.s
index 35185f58fbb4f..9e650f12cd6d9 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512gfnivl.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512gfnivl.s
@@ -114,29 +114,29 @@ vgf2p8mulb (%rax), %ymm17, %ymm19 {z}{k1}
# CHECK-NEXT: 2 10 1.00 * vgf2p8mulb (%rax), %ymm17, %ymm19 {%k1} {z}
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512ifma.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512ifma.s
index 94e562a6fae33..7c183dd9f5b9c 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512ifma.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512ifma.s
@@ -50,29 +50,29 @@ vpmadd52luq (%rdi){1to8}, %zmm17, %zmm19 {%k1} {z}
# CHECK-NEXT: 1 10 1.00 * vpmadd52luq (%rdi){1to8}, %zmm17, %zmm19 {%k1} {z}
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512ifmavl.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512ifmavl.s
index e906c7f7ab655..a5fd5383573f8 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512ifmavl.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512ifmavl.s
@@ -88,29 +88,29 @@ vpmadd52luq (%rdi){1to4}, %ymm17, %ymm19 {%k1} {z}
# CHECK-NEXT: 1 10 0.50 * vpmadd52luq (%rdi){1to4}, %ymm17, %ymm19 {%k1} {z}
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vaes.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vaes.s
index 3a2e4fca0640e..aded5713430f3 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vaes.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vaes.s
@@ -32,29 +32,29 @@ vaesenclast (%rax), %zmm17, %zmm19
# CHECK-NEXT: 1 10 0.50 * vaesenclast (%rax), %zmm17, %zmm19
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vaesvl.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vaesvl.s
index 2877300ccbf56..cfc1a35719233 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vaesvl.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vaesvl.s
@@ -52,29 +52,29 @@ vaesenclast (%rax), %ymm17, %ymm19
# CHECK-NEXT: 1 10 0.50 * vaesenclast (%rax), %ymm17, %ymm19
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmi.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmi.s
index b4529c0b99e3c..f1f185d7fa8ec 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmi.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmi.s
@@ -70,29 +70,29 @@ vpmultishiftqb (%rax){1to8}, %zmm17, %zmm19 {k1}{z}
# CHECK-NEXT: 1 8 0.50 * vpmultishiftqb (%rax){1to8}, %zmm17, %zmm19 {%k1} {z}
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmi2.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmi2.s
index 6e04f81bd41a6..c39e816ea37f7 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmi2.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmi2.s
@@ -260,29 +260,29 @@ vpshrdw $1, (%rax), %zmm17, %zmm19 {k1}{z}
# CHECK-NEXT: 1 9 1.00 * vpshrdw $1, (%rax), %zmm17, %zmm19 {%k1} {z}
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmi2vl.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmi2vl.s
index 910db11f7213e..a6f1ffecf906b 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmi2vl.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmi2vl.s
@@ -508,29 +508,29 @@ vpshrdw $1, (%rax), %ymm17, %ymm19 {k1}{z}
# CHECK-NEXT: 1 9 1.00 * vpshrdw $1, (%rax), %ymm17, %ymm19 {%k1} {z}
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmivl.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmivl.s
index 75947526d47a6..9ac77fbc06c60 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmivl.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmivl.s
@@ -128,29 +128,29 @@ vpmultishiftqb (%rax){1to4}, %ymm17, %ymm19 {k1}{z}
# CHECK-NEXT: 1 8 0.33 * vpmultishiftqb (%rax){1to4}, %ymm17, %ymm19 {%k1} {z}
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vl.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vl.s
index 719c45f7ebf89..3bfd3845254ba 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vl.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vl.s
@@ -3588,29 +3588,29 @@ vunpcklps (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
# CHECK-NEXT: 1 8 0.50 * vunpcklps (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vnni.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vnni.s
index 8ec67dfe701f0..47c96616fc00b 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vnni.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vnni.s
@@ -88,29 +88,29 @@ vpdpwssds (%rax){1to16}, %zmm17, %zmm19 {z}{k1}
# CHECK-NEXT: 1 10 1.00 * vpdpwssds (%rax){1to16}, %zmm17, %zmm19 {%k1} {z}
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vnnivl.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vnnivl.s
index 13a71f6b4bbdf..40492bf2c8592 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vnnivl.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vnnivl.s
@@ -164,29 +164,29 @@ vpdpwssds (%rax){1to8}, %ymm17, %ymm19 {z}{k1}
# CHECK-NEXT: 1 10 0.50 * vpdpwssds (%rax){1to8}, %ymm17, %ymm19 {%k1} {z}
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpclmulqdq.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpclmulqdq.s
index df38ed8ed9033..07d57231d07df 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpclmulqdq.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpclmulqdq.s
@@ -17,29 +17,29 @@ vpclmulqdq $11, (%rax), %zmm17, %zmm19
# CHECK-NEXT: 1 10 0.50 * vpclmulqdq $11, (%rax), %zmm17, %zmm19
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpclmulqdqvl.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpclmulqdqvl.s
index 469ef374dd14d..3113c61521ac6 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpclmulqdqvl.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpclmulqdqvl.s
@@ -22,29 +22,29 @@ vpclmulqdq $11, (%rax), %ymm17, %ymm19
# CHECK-NEXT: 1 10 0.50 * vpclmulqdq $11, (%rax), %ymm17, %ymm19
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpopcntdq.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpopcntdq.s
index 7900e3d4af92e..cb7bf888cb7ab 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpopcntdq.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpopcntdq.s
@@ -54,29 +54,29 @@ vpopcntq (%rdi){1to8}, %zmm0 {%k1} {z}
# CHECK-NEXT: 1 8 0.50 * vpopcntq (%rdi){1to8}, %zmm0 {%k1} {z}
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpopcntdqvl.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpopcntdqvl.s
index aaa146ea5d952..64ac23226db42 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpopcntdqvl.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpopcntdqvl.s
@@ -96,29 +96,29 @@ vpopcntq (%rdi){1to4}, %ymm0 {%k1} {z}
# CHECK-NEXT: 1 8 0.33 * vpopcntq (%rdi){1to4}, %ymm0 {%k1} {z}
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avxgfni.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avxgfni.s
index 995659f21b7d8..2158f04749ff7 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avxgfni.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avxgfni.s
@@ -42,29 +42,29 @@ vgf2p8mulb (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 10 0.50 * vgf2p8mulb (%rax), %ymm1, %ymm2
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avxvnni.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avxvnni.s
index e18e84da8b886..7b2189940a7ed 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avxvnni.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-avxvnni.s
@@ -52,29 +52,29 @@
# CHECK-NEXT: 1 10 0.50 * {vex} vpdpwssds (%rax), %ymm1, %ymm2
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-bmi1.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-bmi1.s
index 36ca3d688af2c..38d894efadf86 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-bmi1.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-bmi1.s
@@ -77,29 +77,29 @@ tzcnt (%rax), %rcx
# CHECK-NEXT: 2 6 0.50 * tzcntq (%rax), %rcx
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-bmi2.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-bmi2.s
index 6696c6c73fbcf..130dfaccb8b47 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-bmi2.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-bmi2.s
@@ -92,29 +92,29 @@ shrx %rax, (%rbx), %rcx
# CHECK-NEXT: 1 5 0.33 * shrxq %rax, (%rbx), %rcx
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-clflushopt.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-clflushopt.s
index e76f8fee7d7f9..66d75d7f0535a 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-clflushopt.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-clflushopt.s
@@ -15,29 +15,29 @@ clflushopt (%rax)
# CHECK-NEXT: 1 5 0.33 * * U clflushopt (%rax)
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-clwb.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-clwb.s
index dd065ff35f5b9..6644e88ab5b48 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-clwb.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-clwb.s
@@ -15,29 +15,29 @@ clwb (%rax)
# CHECK-NEXT: 1 5 0.33 * * U clwb (%rax)
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-cmov.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-cmov.s
index 37f30f3715f1f..ed3d729208a47 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-cmov.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-cmov.s
@@ -210,29 +210,29 @@ cmovgq (%rax), %rdi
# CHECK-NEXT: 1 5 0.33 * cmovgq (%rax), %rdi
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-cmpxchg.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-cmpxchg.s
index d45d287c0c702..eccf2acef1f1e 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-cmpxchg.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-cmpxchg.s
@@ -21,29 +21,29 @@ lock cmpxchg16b (%rax)
# CHECK-NEXT: 6 3 3.00 * * lock cmpxchg16b (%rax)
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-f16c.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-f16c.s
index b7b2d4aaa8403..108a3fe5f4829 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-f16c.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-f16c.s
@@ -32,29 +32,29 @@ vcvtps2ph $0, %ymm0, (%rax)
# CHECK-NEXT: 2 5 0.50 * vcvtps2ph $0, %ymm0, (%rax)
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-fma.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-fma.s
index eee4d6c7eb177..b043c21be4b2c 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-fma.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-fma.s
@@ -492,29 +492,29 @@ vfnmsub231ss (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 11 0.50 * vfnmsub231ss (%rax), %xmm1, %xmm2
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-fsgsbase.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-fsgsbase.s
index e711c8ce42597..e8f61f8a0e068 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-fsgsbase.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-fsgsbase.s
@@ -32,29 +32,29 @@ wrgsbase %rdi
# CHECK-NEXT: 1 100 0.25 * * U wrgsbaseq %rdi
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-gfni.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-gfni.s
index bff9238601630..dc19b64895ec6 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-gfni.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-gfni.s
@@ -27,29 +27,29 @@ gf2p8mulb (%rax), %xmm1
# CHECK-NEXT: 1 10 0.50 * gf2p8mulb (%rax), %xmm1
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-lea.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-lea.s
index d996afee688c2..601253a7c1747 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-lea.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-lea.s
@@ -285,29 +285,29 @@ lea 1024(%rax, %rbx, 2), %rcx
# CHECK-NEXT: 2 2 0.25 leaq 1024(%rax,%rbx,2), %rcx
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-lzcnt.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-lzcnt.s
index acc58ea3c4a1e..e8042848284b8 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-lzcnt.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-lzcnt.s
@@ -27,29 +27,29 @@ lzcntq (%rax), %rcx
# CHECK-NEXT: 1 5 0.33 * lzcntq (%rax), %rcx
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-mmx.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-mmx.s
index e1e38b868bdf3..c1a532eb4a927 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-mmx.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-mmx.s
@@ -271,29 +271,29 @@ pxor (%rax), %mm2
# CHECK-NEXT: 1 8 0.33 * pxor (%rax), %mm2
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-movbe.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-movbe.s
index e3ef3769b68e6..45a28e2e17afd 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-movbe.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-movbe.s
@@ -27,29 +27,29 @@ movbe (%rax), %rcx
# CHECK-NEXT: 1 5 0.33 * movbeq (%rax), %rcx
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-mwaitx.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-mwaitx.s
index 0e0588cbe9df7..f5fe153dc55cc 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-mwaitx.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-mwaitx.s
@@ -17,29 +17,29 @@ mwaitx
# CHECK-NEXT: 1 100 0.25 U mwaitx
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-pclmul.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-pclmul.s
index 821e9e29a2747..825152f563865 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-pclmul.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-pclmul.s
@@ -17,29 +17,29 @@ pclmulqdq $11, (%rax), %xmm2
# CHECK-NEXT: 1 10 0.50 * pclmulqdq $11, (%rax), %xmm2
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-popcnt.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-popcnt.s
index ef88fc50deb8a..38123d7aa1ec3 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-popcnt.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-popcnt.s
@@ -27,29 +27,29 @@ popcntq (%rax), %rcx
# CHECK-NEXT: 1 5 0.33 * popcntq (%rax), %rcx
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-prefetchw.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-prefetchw.s
index 73f7f7c96ebb8..7a14593b0e311 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-prefetchw.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-prefetchw.s
@@ -17,29 +17,29 @@ prefetchw (%rax)
# CHECK-NEXT: 1 5 0.33 * * prefetchw (%rax)
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-rdrand.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-rdrand.s
index e11150c4d504e..20d31b6e510bb 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-rdrand.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-rdrand.s
@@ -19,29 +19,29 @@ rdrand %rax
# CHECK-NEXT: 1 100 0.25 U rdrandq %rax
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-rdseed.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-rdseed.s
index ca5bdfd7ac250..7491c2bb86dc3 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-rdseed.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-rdseed.s
@@ -19,29 +19,29 @@ rdseed %rax
# CHECK-NEXT: 1 100 0.25 U rdseedq %rax
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-sha.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-sha.s
index f23598bf6fe0a..0a42aaa2bc4a9 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-sha.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-sha.s
@@ -47,29 +47,29 @@ sha256rnds2 (%rax), %xmm2
# CHECK-NEXT: 1 11 2.00 * sha256rnds2 %xmm0, (%rax), %xmm2
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse1.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse1.s
index e0fc977b27aa9..ca2bd3465de3a 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse1.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse1.s
@@ -320,29 +320,29 @@ xorps (%rax), %xmm2
# CHECK-NEXT: 1 8 0.33 * xorps (%rax), %xmm2
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse2.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse2.s
index 63eda51da975b..dcd4d97b24698 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse2.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse2.s
@@ -676,29 +676,29 @@ xorpd (%rax), %xmm2
# CHECK-NEXT: 1 8 0.33 * xorpd (%rax), %xmm2
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse3.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse3.s
index 8b210aede2178..53748930a9f28 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse3.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse3.s
@@ -66,29 +66,29 @@ mwait
# CHECK-NEXT: 1 100 0.25 * * U mwait
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse41.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse41.s
index bdaf851fb47c1..52b926083d046 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse41.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse41.s
@@ -253,29 +253,29 @@ roundss $1, (%rax), %xmm2
# CHECK-NEXT: 1 11 0.50 * roundss $1, (%rax), %xmm2
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse42.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse42.s
index 5131206715004..651ff27d639ba 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse42.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse42.s
@@ -62,29 +62,29 @@ pcmpgtq (%rax), %xmm2
# CHECK-NEXT: 1 8 0.33 * pcmpgtq (%rax), %xmm2
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse4a.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse4a.s
index e1b6784322802..5ea6abca45f71 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse4a.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse4a.s
@@ -27,29 +27,29 @@ movntss %xmm0, (%rax)
# CHECK-NEXT: 1 2 1.00 * movntss %xmm0, (%rax)
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-ssse3.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-ssse3.s
index 20f93557d8abe..fe5d18e508370 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-ssse3.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-ssse3.s
@@ -172,29 +172,29 @@ psignw (%rax), %xmm2
# CHECK-NEXT: 1 8 0.33 * psignw (%rax), %xmm2
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-vaes.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-vaes.s
index 1a9d48741d04e..7f67c13eb4ef6 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-vaes.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-vaes.s
@@ -32,29 +32,29 @@ vaesenclast (%rax), %ymm1, %ymm3
# CHECK-NEXT: 1 10 0.50 * vaesenclast (%rax), %ymm1, %ymm3
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-vpclmulqdq.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-vpclmulqdq.s
index 577932a44ab4d..646638da9cd94 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-vpclmulqdq.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-vpclmulqdq.s
@@ -17,29 +17,29 @@ vpclmulqdq $11, (%rax), %ymm1, %ymm3
# CHECK-NEXT: 1 10 0.50 * vpclmulqdq $11, (%rax), %ymm1, %ymm3
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-x86_32.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-x86_32.s
index 0b2f8aacd9fa5..e111c1cb292ea 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-x86_32.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-x86_32.s
@@ -48,29 +48,29 @@ salc
# CHECK-NEXT: 1 1 0.25 U salc
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-x86_64.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-x86_64.s
index c4284ca25d5a9..23831cd1e83b0 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-x86_64.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-x86_64.s
@@ -1292,10 +1292,10 @@ xorq (%rax), %rdi
# CHECK-NEXT: 1 1 0.25 cmpq %rsi, %rdi
# CHECK-NEXT: 1 5 0.33 * cmpq %rsi, (%rax)
# CHECK-NEXT: 1 5 0.33 * cmpq (%rax), %rdi
-# CHECK-NEXT: 1 100 0.25 U cmpsb %es:(%rdi), (%rsi)
-# CHECK-NEXT: 1 100 0.25 U cmpsw %es:(%rdi), (%rsi)
-# CHECK-NEXT: 1 100 0.25 U cmpsl %es:(%rdi), (%rsi)
-# CHECK-NEXT: 1 100 0.25 U cmpsq %es:(%rdi), (%rsi)
+# CHECK-NEXT: 1 100 0.25 * U cmpsb %es:(%rdi), (%rsi)
+# CHECK-NEXT: 1 100 0.25 * U cmpsw %es:(%rdi), (%rsi)
+# CHECK-NEXT: 1 100 0.25 * U cmpsl %es:(%rdi), (%rsi)
+# CHECK-NEXT: 1 100 0.25 * U cmpsq %es:(%rdi), (%rsi)
# CHECK-NEXT: 3 3 3.00 cmpxchgb %cl, %bl
# CHECK-NEXT: 5 4 3.00 * * cmpxchgb %cl, (%rbx)
# CHECK-NEXT: 5 4 3.00 * * lock cmpxchgb %cl, (%rbx)
@@ -1390,17 +1390,17 @@ xorq (%rax), %rdi
# CHECK-NEXT: 1 100 0.25 U invlpga
# CHECK-NEXT: 4 2 0.50 lahf
# CHECK-NEXT: 1 1 0.25 * leave
-# CHECK-NEXT: 1 100 0.25 U lodsb (%rsi), %al
-# CHECK-NEXT: 1 100 0.25 U lodsw (%rsi), %ax
-# CHECK-NEXT: 1 100 0.25 U lodsl (%rsi), %eax
-# CHECK-NEXT: 1 100 0.25 U lodsq (%rsi), %rax
+# CHECK-NEXT: 1 100 0.25 * U lodsb (%rsi), %al
+# CHECK-NEXT: 1 100 0.25 * U lodsw (%rsi), %ax
+# CHECK-NEXT: 1 100 0.25 * U lodsl (%rsi), %eax
+# CHECK-NEXT: 1 100 0.25 * U lodsq (%rsi), %rax
# CHECK-NEXT: 1 1 0.25 U loop 0
# CHECK-NEXT: 1 1 0.25 U loope 0
# CHECK-NEXT: 1 1 0.25 U loopne 0
-# CHECK-NEXT: 1 100 0.25 U movsb (%rsi), %es:(%rdi)
-# CHECK-NEXT: 1 100 0.25 U movsw (%rsi), %es:(%rdi)
-# CHECK-NEXT: 1 100 0.25 U movsl (%rsi), %es:(%rdi)
-# CHECK-NEXT: 1 100 0.25 U movsq (%rsi), %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 * * U movsb (%rsi), %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 * * U movsw (%rsi), %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 * * U movsl (%rsi), %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 * * U movsq (%rsi), %es:(%rdi)
# CHECK-NEXT: 1 1 1.00 movsbw %al, %di
# CHECK-NEXT: 1 1 1.00 movzbw %al, %di
# CHECK-NEXT: 1 5 0.33 * movsbw (%rax), %di
@@ -1743,10 +1743,10 @@ xorq (%rax), %rdi
# CHECK-NEXT: 1 6 0.67 * * sbbq %rsi, (%rax)
# CHECK-NEXT: 1 6 0.67 * * lock sbbq %rsi, (%rax)
# CHECK-NEXT: 1 5 0.33 * sbbq (%rax), %rdi
-# CHECK-NEXT: 1 100 0.25 U scasb %es:(%rdi), %al
-# CHECK-NEXT: 1 100 0.25 U scasw %es:(%rdi), %ax
-# CHECK-NEXT: 1 100 0.25 U scasl %es:(%rdi), %eax
-# CHECK-NEXT: 1 100 0.25 U scasq %es:(%rdi), %rax
+# CHECK-NEXT: 1 100 0.25 * U scasb %es:(%rdi), %al
+# CHECK-NEXT: 1 100 0.25 * U scasw %es:(%rdi), %ax
+# CHECK-NEXT: 1 100 0.25 * U scasl %es:(%rdi), %eax
+# CHECK-NEXT: 1 100 0.25 * U scasq %es:(%rdi), %rax
# CHECK-NEXT: 1 1 0.25 seto %al
# CHECK-NEXT: 2 1 0.50 * seto (%rax)
# CHECK-NEXT: 1 1 0.25 setno %al
@@ -1805,10 +1805,10 @@ xorq (%rax), %rdi
# CHECK-NEXT: 8 4 1.00 * * shrdq $7, %rsi, (%rax)
# CHECK-NEXT: 1 1 0.25 U stc
# CHECK-NEXT: 1 1 0.25 U std
-# CHECK-NEXT: 1 100 0.25 U stosb %al, %es:(%rdi)
-# CHECK-NEXT: 1 100 0.25 U stosw %ax, %es:(%rdi)
-# CHECK-NEXT: 1 100 0.25 U stosl %eax, %es:(%rdi)
-# CHECK-NEXT: 1 100 0.25 U stosq %rax, %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 * U stosb %al, %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 * U stosw %ax, %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 * U stosl %eax, %es:(%rdi)
+# CHECK-NEXT: 1 100 0.25 * U stosq %rax, %es:(%rdi)
# CHECK-NEXT: 1 1 0.25 subb $7, %al
# CHECK-NEXT: 1 1 0.25 subb $7, %dil
# CHECK-NEXT: 1 6 0.67 * * subb $7, (%rax)
@@ -1949,29 +1949,29 @@ xorq (%rax), %rdi
# CHECK-NEXT: 1 5 0.33 * xorq (%rax), %rdi
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-x87.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-x87.s
index 71b88b2bc9064..9da97a5f5c51e 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-x87.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-x87.s
@@ -356,29 +356,29 @@ fyl2xp1
# CHECK-NEXT: 1 100 0.25 U fyl2xp1
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-xsave.s b/llvm/test/tools/llvm-mca/X86/4GM7/resources-xsave.s
index a322cf26008da..bee1a460a5342 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/resources-xsave.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/resources-xsave.s
@@ -27,29 +27,29 @@ xsetbv
# CHECK-NEXT: 1 100 0.25 * * U xsetbv
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/zero-idioms.s b/llvm/test/tools/llvm-mca/X86/4GM7/zero-idioms.s
index fbfc06512ab48..db4d4c5123733 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/zero-idioms.s
+++ b/llvm/test/tools/llvm-mca/X86/4GM7/zero-idioms.s
@@ -322,40 +322,40 @@ vpxorq %zmm19, %zmm19, %zmm21
# CHECK-NEXT: Total number of mappings created: 9
# CHECK-NEXT: Max number of mappings used: 4
-# CHECK: * Register File #1 -- 4GM7FpuPRF:
+# CHECK: * Register File #1 -- C4GM7FpuPRF:
# CHECK-NEXT: Number of physical registers: 208
# CHECK-NEXT: Total number of mappings created: 9
# CHECK-NEXT: Max number of mappings used: 4
-# CHECK: * Register File #2 -- 4GM7IntegerPRF:
+# CHECK: * Register File #2 -- C4GM7IntegerPRF:
# CHECK-NEXT: Number of physical registers: 224
# CHECK-NEXT: Total number of mappings created: 0
# CHECK-NEXT: Max number of mappings used: 0
# CHECK: Resources:
-# CHECK-NEXT: [0] - 4GM7AGU0
-# CHECK-NEXT: [1] - 4GM7AGU1
-# CHECK-NEXT: [2] - 4GM7AGU2
-# CHECK-NEXT: [3] - 4GM7ALU0
-# CHECK-NEXT: [4] - 4GM7ALU1
-# CHECK-NEXT: [5] - 4GM7ALU2
-# CHECK-NEXT: [6] - 4GM7ALU3
-# CHECK-NEXT: [7] - 4GM7BRU1
-# CHECK-NEXT: [8] - 4GM7FPU0
-# CHECK-NEXT: [9] - 4GM7FPU1
-# CHECK-NEXT: [10] - 4GM7FPU2
-# CHECK-NEXT: [11] - 4GM7FPU3
-# CHECK-NEXT: [12.0] - 4GM7LSU
-# CHECK-NEXT: [12.1] - 4GM7LSU
-# CHECK-NEXT: [12.2] - 4GM7LSU
-# CHECK-NEXT: [12.3] - 4GM7LSU
-# CHECK-NEXT: [13.0] - 4GM7Load
-# CHECK-NEXT: [13.1] - 4GM7Load
-# CHECK-NEXT: [13.2] - 4GM7Load
-# CHECK-NEXT: [14.0] - 4GM7Store
-# CHECK-NEXT: [14.1] - 4GM7Store
-# CHECK-NEXT: [14.2] - 4GM7Store
-# CHECK-NEXT: [14.3] - 4GM7Store
+# CHECK-NEXT: [0] - C4GM7AGU0
+# CHECK-NEXT: [1] - C4GM7AGU1
+# CHECK-NEXT: [2] - C4GM7AGU2
+# CHECK-NEXT: [3] - C4GM7ALU0
+# CHECK-NEXT: [4] - C4GM7ALU1
+# CHECK-NEXT: [5] - C4GM7ALU2
+# CHECK-NEXT: [6] - C4GM7ALU3
+# CHECK-NEXT: [7] - C4GM7BRU1
+# CHECK-NEXT: [8] - C4GM7FPU0
+# CHECK-NEXT: [9] - C4GM7FPU1
+# CHECK-NEXT: [10] - C4GM7FPU2
+# CHECK-NEXT: [11] - C4GM7FPU3
+# CHECK-NEXT: [12.0] - C4GM7LSU
+# CHECK-NEXT: [12.1] - C4GM7LSU
+# CHECK-NEXT: [12.2] - C4GM7LSU
+# CHECK-NEXT: [12.3] - C4GM7LSU
+# CHECK-NEXT: [13.0] - C4GM7Load
+# CHECK-NEXT: [13.1] - C4GM7Load
+# CHECK-NEXT: [13.2] - C4GM7Load
+# CHECK-NEXT: [14.0] - C4GM7Store
+# CHECK-NEXT: [14.1] - C4GM7Store
+# CHECK-NEXT: [14.2] - C4GM7Store
+# CHECK-NEXT: [14.3] - C4GM7Store
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [12.2] [12.3] [13.0] [13.1] [13.2] [14.0] [14.1] [14.2] [14.3]
>From 00dcaa0348d444c639ae4a806ad98ef4026539bf Mon Sep 17 00:00:00 2001
From: zhangxiaomeng <zhangxiaomeng at hygon.cn>
Date: Tue, 19 May 2026 16:23:46 +0800
Subject: [PATCH 10/11] Add a newline at EOF
---
llvm/lib/Target/X86/X86ScheduleC864GM4.td | 2 +-
llvm/lib/Target/X86/X86ScheduleC864GM7.td | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ScheduleC864GM4.td b/llvm/lib/Target/X86/X86ScheduleC864GM4.td
index eea3e1bbaf337..fe157e55fdceb 100644
--- a/llvm/lib/Target/X86/X86ScheduleC864GM4.td
+++ b/llvm/lib/Target/X86/X86ScheduleC864GM4.td
@@ -1011,4 +1011,4 @@ def : IsDepBreakingFunction<[
], ZeroIdiomPredicate>,
]>;
-} // SchedModel
\ No newline at end of file
+} // SchedModel
diff --git a/llvm/lib/Target/X86/X86ScheduleC864GM7.td b/llvm/lib/Target/X86/X86ScheduleC864GM7.td
index 7e1d964526ffa..79a77b3309571 100644
--- a/llvm/lib/Target/X86/X86ScheduleC864GM7.td
+++ b/llvm/lib/Target/X86/X86ScheduleC864GM7.td
@@ -3718,4 +3718,4 @@ def : IsDepBreakingFunction<[
], ZeroIdiomPredicate>,
]>;
-} // SchedModel
\ No newline at end of file
+} // SchedModel
>From 613f4c556021780e7cfe8a8828c489183c27e5cd Mon Sep 17 00:00:00 2001
From: zhangxiaomeng <zhangxiaomeng at hygon.cn>
Date: Wed, 3 Jun 2026 15:03:38 +0800
Subject: [PATCH 11/11] Rename llvm-mca test directories and update regression
tests
Change-Id: I8c09ab1c5652a1980a3d0b640f93a8eb2dca5058
---
.../test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-adx.s | 0
.../test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-aes.s | 0
.../tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-avx1.s | 0
.../tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-avx2.s | 0
.../tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-bmi1.s | 0
.../tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-bmi2.s | 0
.../llvm-mca/X86/{4GM4 => C864GM4}/resources-clflushopt.s | 0
.../tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-clzero.s | 0
.../tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-cmov.s | 0
.../tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-cmpxchg.s | 0
.../tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-f16c.s | 0
.../test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-fma.s | 0
.../tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-fsgsbase.s | 0
.../test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-lea.s | 0
.../tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-lzcnt.s | 0
.../test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-mmx.s | 0
.../tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-movbe.s | 0
.../tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-mwaitx.s | 0
.../tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-pclmul.s | 0
.../tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-popcnt.s | 0
.../llvm-mca/X86/{4GM4 => C864GM4}/resources-prefetchw.s | 0
.../tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-rdrand.s | 0
.../tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-rdseed.s | 0
.../test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-sha.s | 0
.../tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-sse1.s | 0
.../tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-sse2.s | 0
.../tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-sse3.s | 0
.../tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-sse41.s | 0
.../tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-sse42.s | 0
.../tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-sse4a.s | 0
.../tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-ssse3.s | 0
.../tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-x86_32.s | 0
.../tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-x86_64.s | 0
.../test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-x87.s | 0
.../tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-xsave.s | 0
llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/zero-idioms.s | 2 +-
.../llvm-mca/X86/{4GM7 => C864GM7}/independent-load-stores.s | 4 ++--
.../{4GM7 => C864GM7}/partially-overlapping-group-resources.s | 2 +-
.../test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-adx.s | 0
.../test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-aes.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx1.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx2.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512.s | 0
.../llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512bitalg.s | 0
.../llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512bitalgvl.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512bw.s | 0
.../llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512bwvl.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512cd.s | 0
.../llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512cdvl.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512dq.s | 0
.../llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512dqvl.s | 0
.../llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512gfni.s | 0
.../llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512gfnivl.s | 0
.../llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512ifma.s | 0
.../llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512ifmavl.s | 0
.../llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512vaes.s | 0
.../llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512vaesvl.s | 0
.../llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512vbmi.s | 0
.../llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512vbmi2.s | 0
.../llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512vbmi2vl.s | 0
.../llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512vbmivl.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512vl.s | 0
.../llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512vnni.s | 0
.../llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512vnnivl.s | 0
.../X86/{4GM7 => C864GM7}/resources-avx512vp2intersect.s | 0
.../X86/{4GM7 => C864GM7}/resources-avx512vp2intersectvl.s | 0
.../X86/{4GM7 => C864GM7}/resources-avx512vpclmulqdq.s | 0
.../X86/{4GM7 => C864GM7}/resources-avx512vpclmulqdqvl.s | 0
.../X86/{4GM7 => C864GM7}/resources-avx512vpopcntdq.s | 0
.../X86/{4GM7 => C864GM7}/resources-avx512vpopcntdqvl.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avxgfni.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avxvnni.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-bmi1.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-bmi2.s | 0
.../llvm-mca/X86/{4GM7 => C864GM7}/resources-clflushopt.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-clwb.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-cmov.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-cmpxchg.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-f16c.s | 0
.../test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-fma.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-fsgsbase.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-gfni.s | 0
.../test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-lea.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-lzcnt.s | 0
.../test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-mmx.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-movbe.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-mwaitx.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-pclmul.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-popcnt.s | 0
.../llvm-mca/X86/{4GM7 => C864GM7}/resources-prefetchw.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-rdrand.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-rdseed.s | 0
.../test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-sha.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-sse1.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-sse2.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-sse3.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-sse41.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-sse42.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-sse4a.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-ssse3.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-vaes.s | 0
.../llvm-mca/X86/{4GM7 => C864GM7}/resources-vpclmulqdq.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-x86_32.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-x86_64.s | 0
.../test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-x87.s | 0
.../tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-xsave.s | 0
llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/zero-idioms.s | 2 +-
107 files changed, 5 insertions(+), 5 deletions(-)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-adx.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-aes.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-avx1.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-avx2.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-bmi1.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-bmi2.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-clflushopt.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-clzero.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-cmov.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-cmpxchg.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-f16c.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-fma.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-fsgsbase.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-lea.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-lzcnt.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-mmx.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-movbe.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-mwaitx.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-pclmul.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-popcnt.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-prefetchw.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-rdrand.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-rdseed.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-sha.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-sse1.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-sse2.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-sse3.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-sse41.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-sse42.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-sse4a.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-ssse3.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-x86_32.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-x86_64.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-x87.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/resources-xsave.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM4 => C864GM4}/zero-idioms.s (99%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/independent-load-stores.s (98%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/partially-overlapping-group-resources.s (98%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-adx.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-aes.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx1.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx2.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512bitalg.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512bitalgvl.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512bw.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512bwvl.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512cd.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512cdvl.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512dq.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512dqvl.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512gfni.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512gfnivl.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512ifma.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512ifmavl.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512vaes.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512vaesvl.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512vbmi.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512vbmi2.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512vbmi2vl.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512vbmivl.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512vl.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512vnni.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512vnnivl.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512vp2intersect.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512vp2intersectvl.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512vpclmulqdq.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512vpclmulqdqvl.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512vpopcntdq.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avx512vpopcntdqvl.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avxgfni.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-avxvnni.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-bmi1.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-bmi2.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-clflushopt.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-clwb.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-cmov.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-cmpxchg.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-f16c.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-fma.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-fsgsbase.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-gfni.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-lea.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-lzcnt.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-mmx.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-movbe.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-mwaitx.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-pclmul.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-popcnt.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-prefetchw.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-rdrand.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-rdseed.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-sha.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-sse1.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-sse2.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-sse3.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-sse41.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-sse42.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-sse4a.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-ssse3.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-vaes.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-vpclmulqdq.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-x86_32.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-x86_64.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-x87.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/resources-xsave.s (100%)
rename llvm/test/tools/llvm-mca/X86/{4GM7 => C864GM7}/zero-idioms.s (99%)
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-adx.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-adx.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-adx.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-adx.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-aes.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-aes.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-aes.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-aes.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-avx1.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-avx1.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-avx1.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-avx1.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-avx2.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-avx2.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-avx2.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-avx2.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-bmi1.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-bmi1.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-bmi1.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-bmi1.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-bmi2.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-bmi2.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-bmi2.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-bmi2.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-clflushopt.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-clflushopt.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-clflushopt.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-clflushopt.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-clzero.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-clzero.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-clzero.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-clzero.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-cmov.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-cmov.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-cmov.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-cmov.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-cmpxchg.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-cmpxchg.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-cmpxchg.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-cmpxchg.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-f16c.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-f16c.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-f16c.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-f16c.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-fma.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-fma.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-fma.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-fma.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-fsgsbase.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-fsgsbase.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-fsgsbase.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-fsgsbase.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-lea.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-lea.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-lea.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-lea.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-lzcnt.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-lzcnt.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-lzcnt.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-lzcnt.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-mmx.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-mmx.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-mmx.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-mmx.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-movbe.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-movbe.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-movbe.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-movbe.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-mwaitx.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-mwaitx.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-mwaitx.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-mwaitx.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-pclmul.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-pclmul.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-pclmul.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-pclmul.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-popcnt.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-popcnt.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-popcnt.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-popcnt.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-prefetchw.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-prefetchw.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-prefetchw.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-prefetchw.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-rdrand.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-rdrand.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-rdrand.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-rdrand.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-rdseed.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-rdseed.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-rdseed.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-rdseed.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-sha.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-sha.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-sha.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-sha.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse1.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse1.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-sse1.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse1.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse2.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse2.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-sse2.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse2.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse3.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse3.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-sse3.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse3.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse41.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse41.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-sse41.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse41.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse42.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse42.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-sse42.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse42.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-sse4a.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse4a.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-sse4a.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-sse4a.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-ssse3.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-ssse3.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-ssse3.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-ssse3.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-x86_32.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-x86_32.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-x86_32.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-x86_32.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-x86_64.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-x86_64.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-x86_64.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-x86_64.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-x87.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-x87.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-x87.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-x87.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/resources-xsave.s b/llvm/test/tools/llvm-mca/X86/C864GM4/resources-xsave.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM4/resources-xsave.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/resources-xsave.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM4/zero-idioms.s b/llvm/test/tools/llvm-mca/X86/C864GM4/zero-idioms.s
similarity index 99%
rename from llvm/test/tools/llvm-mca/X86/4GM4/zero-idioms.s
rename to llvm/test/tools/llvm-mca/X86/C864GM4/zero-idioms.s
index 5a4a528a5be29..05550a92ca0ed 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM4/zero-idioms.s
+++ b/llvm/test/tools/llvm-mca/X86/C864GM4/zero-idioms.s
@@ -504,4 +504,4 @@ vpxor %ymm3, %ymm3, %ymm5
# CHECK-NEXT: 80. 1 0.0 0.0 0.0 vxorpd %ymm1, %ymm1, %ymm3
# CHECK-NEXT: 81. 1 0.0 0.0 1.0 vpxor %xmm3, %xmm3, %xmm5
# CHECK-NEXT: 82. 1 0.0 0.0 1.0 vpxor %ymm3, %ymm3, %ymm5
-# CHECK-NEXT: 1 0.3 0.2 1.2 <total>
+# CHECK-NEXT: 83 0.3 0.2 1.2 <total>
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/independent-load-stores.s b/llvm/test/tools/llvm-mca/X86/C864GM7/independent-load-stores.s
similarity index 98%
rename from llvm/test/tools/llvm-mca/X86/4GM7/independent-load-stores.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/independent-load-stores.s
index 51fba2a2b5cb5..51a167e161a16 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/independent-load-stores.s
+++ b/llvm/test/tools/llvm-mca/X86/C864GM7/independent-load-stores.s
@@ -141,7 +141,7 @@
# NOALIAS-NEXT: 7. 1 4.0 0.0 0.0 addq $44, 512(%r14)
# NOALIAS-NEXT: 8. 1 3.0 0.0 0.0 addq $44, 576(%r14)
# NOALIAS-NEXT: 9. 1 5.0 2.0 0.0 addq $44, 640(%r14)
-# NOALIAS-NEXT: 1 2.6 0.7 0.0 <total>
+# NOALIAS-NEXT: 10 2.6 0.7 0.0 <total>
# YESALIAS-NEXT: 1. 1 7.0 0.0 0.0 addq $44, 128(%r14)
# YESALIAS-NEXT: 2. 1 13.0 0.0 0.0 addq $44, 192(%r14)
@@ -152,4 +152,4 @@
# YESALIAS-NEXT: 7. 1 42.0 0.0 0.0 addq $44, 512(%r14)
# YESALIAS-NEXT: 8. 1 47.0 0.0 0.0 addq $44, 576(%r14)
# YESALIAS-NEXT: 9. 1 53.0 0.0 0.0 addq $44, 640(%r14)
-# YESALIAS-NEXT: 1 27.2 0.1 0.0 <total>
+# YESALIAS-NEXT: 10 27.2 0.1 0.0 <total>
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/partially-overlapping-group-resources.s b/llvm/test/tools/llvm-mca/X86/C864GM7/partially-overlapping-group-resources.s
similarity index 98%
rename from llvm/test/tools/llvm-mca/X86/4GM7/partially-overlapping-group-resources.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/partially-overlapping-group-resources.s
index cdcbddf762de8..ced42c1f1b346 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/partially-overlapping-group-resources.s
+++ b/llvm/test/tools/llvm-mca/X86/C864GM7/partially-overlapping-group-resources.s
@@ -88,4 +88,4 @@ vpxord zmm1, zmm1, zmm1
# CHECK-NEXT: 0. 1 1.0 1.0 0.0 vpconflictd zmm0, zmm3
# CHECK-NEXT: 1. 1 1.0 1.0 2.0 kxnorw k1, k1, k1
# CHECK-NEXT: 2. 1 0.0 0.0 4.0 vpxord zmm1, zmm1, zmm1
-# CHECK-NEXT: 1 0.7 0.7 2.0 <total>
+# CHECK-NEXT: 3 0.7 0.7 2.0 <total>
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-adx.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-adx.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-adx.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-adx.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-aes.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-aes.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-aes.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-aes.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx1.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx1.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-avx1.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx1.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx2.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx2.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-avx2.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx2.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bitalg.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512bitalg.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bitalg.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512bitalg.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bitalgvl.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512bitalgvl.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bitalgvl.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512bitalgvl.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bw.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512bw.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bw.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512bw.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bwvl.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512bwvl.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512bwvl.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512bwvl.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512cd.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512cd.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512cd.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512cd.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512cdvl.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512cdvl.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512cdvl.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512cdvl.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512dq.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512dq.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512dq.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512dq.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512dqvl.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512dqvl.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512dqvl.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512dqvl.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512gfni.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512gfni.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512gfni.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512gfni.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512gfnivl.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512gfnivl.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512gfnivl.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512gfnivl.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512ifma.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512ifma.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512ifma.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512ifma.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512ifmavl.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512ifmavl.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512ifmavl.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512ifmavl.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vaes.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vaes.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vaes.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vaes.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vaesvl.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vaesvl.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vaesvl.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vaesvl.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmi.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vbmi.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmi.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vbmi.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmi2.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vbmi2.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmi2.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vbmi2.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmi2vl.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vbmi2vl.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmi2vl.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vbmi2vl.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmivl.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vbmivl.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vbmivl.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vbmivl.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vl.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vl.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vl.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vl.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vnni.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vnni.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vnni.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vnni.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vnnivl.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vnnivl.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vnnivl.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vnnivl.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vp2intersect.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vp2intersect.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vp2intersect.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vp2intersect.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vp2intersectvl.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vp2intersectvl.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vp2intersectvl.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vp2intersectvl.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpclmulqdq.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vpclmulqdq.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpclmulqdq.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vpclmulqdq.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpclmulqdqvl.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vpclmulqdqvl.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpclmulqdqvl.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vpclmulqdqvl.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpopcntdq.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vpopcntdq.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpopcntdq.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vpopcntdq.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpopcntdqvl.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vpopcntdqvl.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-avx512vpopcntdqvl.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-avx512vpopcntdqvl.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avxgfni.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-avxgfni.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-avxgfni.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-avxgfni.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-avxvnni.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-avxvnni.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-avxvnni.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-avxvnni.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-bmi1.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-bmi1.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-bmi1.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-bmi1.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-bmi2.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-bmi2.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-bmi2.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-bmi2.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-clflushopt.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-clflushopt.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-clflushopt.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-clflushopt.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-clwb.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-clwb.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-clwb.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-clwb.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-cmov.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-cmov.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-cmov.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-cmov.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-cmpxchg.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-cmpxchg.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-cmpxchg.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-cmpxchg.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-f16c.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-f16c.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-f16c.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-f16c.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-fma.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-fma.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-fma.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-fma.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-fsgsbase.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-fsgsbase.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-fsgsbase.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-fsgsbase.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-gfni.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-gfni.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-gfni.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-gfni.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-lea.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-lea.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-lea.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-lea.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-lzcnt.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-lzcnt.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-lzcnt.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-lzcnt.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-mmx.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-mmx.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-mmx.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-mmx.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-movbe.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-movbe.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-movbe.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-movbe.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-mwaitx.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-mwaitx.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-mwaitx.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-mwaitx.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-pclmul.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-pclmul.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-pclmul.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-pclmul.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-popcnt.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-popcnt.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-popcnt.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-popcnt.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-prefetchw.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-prefetchw.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-prefetchw.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-prefetchw.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-rdrand.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-rdrand.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-rdrand.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-rdrand.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-rdseed.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-rdseed.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-rdseed.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-rdseed.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-sha.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-sha.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-sha.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-sha.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse1.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse1.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-sse1.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse1.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse2.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse2.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-sse2.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse2.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse3.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse3.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-sse3.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse3.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse41.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse41.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-sse41.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse41.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse42.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse42.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-sse42.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse42.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-sse4a.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse4a.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-sse4a.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-sse4a.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-ssse3.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-ssse3.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-ssse3.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-ssse3.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-vaes.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-vaes.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-vaes.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-vaes.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-vpclmulqdq.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-vpclmulqdq.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-vpclmulqdq.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-vpclmulqdq.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-x86_32.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-x86_32.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-x86_32.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-x86_32.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-x86_64.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-x86_64.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-x86_64.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-x86_64.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-x87.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-x87.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-x87.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-x87.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/resources-xsave.s b/llvm/test/tools/llvm-mca/X86/C864GM7/resources-xsave.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/X86/4GM7/resources-xsave.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/resources-xsave.s
diff --git a/llvm/test/tools/llvm-mca/X86/4GM7/zero-idioms.s b/llvm/test/tools/llvm-mca/X86/C864GM7/zero-idioms.s
similarity index 99%
rename from llvm/test/tools/llvm-mca/X86/4GM7/zero-idioms.s
rename to llvm/test/tools/llvm-mca/X86/C864GM7/zero-idioms.s
index db4d4c5123733..caa2b59332f69 100644
--- a/llvm/test/tools/llvm-mca/X86/4GM7/zero-idioms.s
+++ b/llvm/test/tools/llvm-mca/X86/C864GM7/zero-idioms.s
@@ -793,4 +793,4 @@ vpxorq %zmm19, %zmm19, %zmm21
# CHECK-NEXT: 136. 1 0.0 0.0 0.0 vpxorq %ymm19, %ymm19, %ymm21
# CHECK-NEXT: 137. 1 0.0 0.0 0.0 vpxord %zmm19, %zmm19, %zmm21
# CHECK-NEXT: 138. 1 0.0 0.0 0.0 vpxorq %zmm19, %zmm19, %zmm21
-# CHECK-NEXT: 1 0.2 0.1 0.9 <total>
+# CHECK-NEXT: 139 0.2 0.1 0.9 <total>
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