[clang] [CIR][AArch64] Upstream addition NEON builtins (PR #202005)
Vicky Nguyen via cfe-commits
cfe-commits at lists.llvm.org
Mon Jun 8 21:59:57 PDT 2026
https://github.com/iamvickynguyen updated https://github.com/llvm/llvm-project/pull/202005
>From 502866087da7155c5c95c79e44f23937a121535c Mon Sep 17 00:00:00 2001
From: Vicky Nguyen <vicky.trucviennguyen at gmail.com>
Date: Fri, 5 Jun 2026 21:43:44 -0700
Subject: [PATCH] [CIR][AArch64] Upstream addition NEON builtins
---
.../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 15 +-
clang/test/CodeGen/AArch64/neon-intrinsics.c | 222 +---------------
clang/test/CodeGen/AArch64/neon/intrinsics.c | 247 ++++++++++++++++++
3 files changed, 262 insertions(+), 222 deletions(-)
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index be906d0671e3a..aca5ca7b57e90 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -668,8 +668,20 @@ static mlir::Value emitCommonNeonBuiltinExpr(
case NEON::BI__builtin_neon_vpaddq_v:
case NEON::BI__builtin_neon_vabs_v:
case NEON::BI__builtin_neon_vabsq_v:
+ cgf.cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ ctx.BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
case NEON::BI__builtin_neon_vadd_v:
- case NEON::BI__builtin_neon_vaddq_v:
+ case NEON::BI__builtin_neon_vaddq_v: {
+ unsigned numBytes = (builtinID == NEON::BI__builtin_neon_vaddq_v) ? 16 : 8;
+ cir::VectorType byteTy =
+ cir::VectorType::get(cgf.getBuilder().getUInt8Ty(), numBytes);
+ ops[0] = cgf.getBuilder().createBitcast(ops[0], byteTy);
+ ops[1] = cgf.getBuilder().createBitcast(ops[1], byteTy);
+ mlir::Value result = cgf.getBuilder().createXor(loc, ops[0], ops[1]);
+ return cgf.getBuilder().createBitcast(result, ty);
+ }
case NEON::BI__builtin_neon_vaddhn_v:
case NEON::BI__builtin_neon_vcale_v:
case NEON::BI__builtin_neon_vcaleq_v:
@@ -2524,6 +2536,7 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
convertType(expr->getType()), ops);
case NEON::BI__builtin_neon_vaddd_s64:
case NEON::BI__builtin_neon_vaddd_u64:
+ return builder.createAdd(loc, ops[0], ops[1]);
case NEON::BI__builtin_neon_vsubd_s64:
case NEON::BI__builtin_neon_vsubd_u64:
case NEON::BI__builtin_neon_vqdmlalh_s16:
diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c
index 1f6359bbe2c89..013b1cee25224 100644
--- a/clang/test/CodeGen/AArch64/neon-intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c
@@ -5,198 +5,8 @@
#include <arm_neon.h>
-// CHECK-LABEL: define dso_local <8 x i8> @test_vadd_s8(
-// CHECK-SAME: <8 x i8> noundef [[V1:%.*]], <8 x i8> noundef [[V2:%.*]]) #[[ATTR0:[0-9]+]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i8> [[V1]], [[V2]]
-// CHECK-NEXT: ret <8 x i8> [[ADD_I]]
-//
-int8x8_t test_vadd_s8(int8x8_t v1, int8x8_t v2) {
- return vadd_s8(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <4 x i16> @test_vadd_s16(
-// CHECK-SAME: <4 x i16> noundef [[V1:%.*]], <4 x i16> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[V1]], [[V2]]
-// CHECK-NEXT: ret <4 x i16> [[ADD_I]]
-//
-int16x4_t test_vadd_s16(int16x4_t v1, int16x4_t v2) {
- return vadd_s16(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <2 x i32> @test_vadd_s32(
-// CHECK-SAME: <2 x i32> noundef [[V1:%.*]], <2 x i32> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[V1]], [[V2]]
-// CHECK-NEXT: ret <2 x i32> [[ADD_I]]
-//
-int32x2_t test_vadd_s32(int32x2_t v1, int32x2_t v2) {
- return vadd_s32(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <1 x i64> @test_vadd_s64(
-// CHECK-SAME: <1 x i64> noundef [[V1:%.*]], <1 x i64> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[ADD_I:%.*]] = add <1 x i64> [[V1]], [[V2]]
-// CHECK-NEXT: ret <1 x i64> [[ADD_I]]
-//
-int64x1_t test_vadd_s64(int64x1_t v1, int64x1_t v2) {
- return vadd_s64(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <2 x float> @test_vadd_f32(
-// CHECK-SAME: <2 x float> noundef [[V1:%.*]], <2 x float> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[ADD_I:%.*]] = fadd <2 x float> [[V1]], [[V2]]
-// CHECK-NEXT: ret <2 x float> [[ADD_I]]
-//
-float32x2_t test_vadd_f32(float32x2_t v1, float32x2_t v2) {
- return vadd_f32(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <8 x i8> @test_vadd_u8(
-// CHECK-SAME: <8 x i8> noundef [[V1:%.*]], <8 x i8> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i8> [[V1]], [[V2]]
-// CHECK-NEXT: ret <8 x i8> [[ADD_I]]
-//
-uint8x8_t test_vadd_u8(uint8x8_t v1, uint8x8_t v2) {
- return vadd_u8(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <4 x i16> @test_vadd_u16(
-// CHECK-SAME: <4 x i16> noundef [[V1:%.*]], <4 x i16> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[V1]], [[V2]]
-// CHECK-NEXT: ret <4 x i16> [[ADD_I]]
-//
-uint16x4_t test_vadd_u16(uint16x4_t v1, uint16x4_t v2) {
- return vadd_u16(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <2 x i32> @test_vadd_u32(
-// CHECK-SAME: <2 x i32> noundef [[V1:%.*]], <2 x i32> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[V1]], [[V2]]
-// CHECK-NEXT: ret <2 x i32> [[ADD_I]]
-//
-uint32x2_t test_vadd_u32(uint32x2_t v1, uint32x2_t v2) {
- return vadd_u32(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <1 x i64> @test_vadd_u64(
-// CHECK-SAME: <1 x i64> noundef [[V1:%.*]], <1 x i64> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[ADD_I:%.*]] = add <1 x i64> [[V1]], [[V2]]
-// CHECK-NEXT: ret <1 x i64> [[ADD_I]]
-//
-uint64x1_t test_vadd_u64(uint64x1_t v1, uint64x1_t v2) {
- return vadd_u64(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <16 x i8> @test_vaddq_s8(
-// CHECK-SAME: <16 x i8> noundef [[V1:%.*]], <16 x i8> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[ADD_I:%.*]] = add <16 x i8> [[V1]], [[V2]]
-// CHECK-NEXT: ret <16 x i8> [[ADD_I]]
-//
-int8x16_t test_vaddq_s8(int8x16_t v1, int8x16_t v2) {
- return vaddq_s8(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <8 x i16> @test_vaddq_s16(
-// CHECK-SAME: <8 x i16> noundef [[V1:%.*]], <8 x i16> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i16> [[V1]], [[V2]]
-// CHECK-NEXT: ret <8 x i16> [[ADD_I]]
-//
-int16x8_t test_vaddq_s16(int16x8_t v1, int16x8_t v2) {
- return vaddq_s16(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <4 x i32> @test_vaddq_s32(
-// CHECK-SAME: <4 x i32> noundef [[V1:%.*]], <4 x i32> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i32> [[V1]], [[V2]]
-// CHECK-NEXT: ret <4 x i32> [[ADD_I]]
-//
-int32x4_t test_vaddq_s32(int32x4_t v1, int32x4_t v2) {
- return vaddq_s32(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <2 x i64> @test_vaddq_s64(
-// CHECK-SAME: <2 x i64> noundef [[V1:%.*]], <2 x i64> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i64> [[V1]], [[V2]]
-// CHECK-NEXT: ret <2 x i64> [[ADD_I]]
-//
-int64x2_t test_vaddq_s64(int64x2_t v1, int64x2_t v2) {
- return vaddq_s64(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <4 x float> @test_vaddq_f32(
-// CHECK-SAME: <4 x float> noundef [[V1:%.*]], <4 x float> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[ADD_I:%.*]] = fadd <4 x float> [[V1]], [[V2]]
-// CHECK-NEXT: ret <4 x float> [[ADD_I]]
-//
-float32x4_t test_vaddq_f32(float32x4_t v1, float32x4_t v2) {
- return vaddq_f32(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <2 x double> @test_vaddq_f64(
-// CHECK-SAME: <2 x double> noundef [[V1:%.*]], <2 x double> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[ADD_I:%.*]] = fadd <2 x double> [[V1]], [[V2]]
-// CHECK-NEXT: ret <2 x double> [[ADD_I]]
-//
-float64x2_t test_vaddq_f64(float64x2_t v1, float64x2_t v2) {
- return vaddq_f64(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <16 x i8> @test_vaddq_u8(
-// CHECK-SAME: <16 x i8> noundef [[V1:%.*]], <16 x i8> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[ADD_I:%.*]] = add <16 x i8> [[V1]], [[V2]]
-// CHECK-NEXT: ret <16 x i8> [[ADD_I]]
-//
-uint8x16_t test_vaddq_u8(uint8x16_t v1, uint8x16_t v2) {
- return vaddq_u8(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <8 x i16> @test_vaddq_u16(
-// CHECK-SAME: <8 x i16> noundef [[V1:%.*]], <8 x i16> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i16> [[V1]], [[V2]]
-// CHECK-NEXT: ret <8 x i16> [[ADD_I]]
-//
-uint16x8_t test_vaddq_u16(uint16x8_t v1, uint16x8_t v2) {
- return vaddq_u16(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <4 x i32> @test_vaddq_u32(
-// CHECK-SAME: <4 x i32> noundef [[V1:%.*]], <4 x i32> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i32> [[V1]], [[V2]]
-// CHECK-NEXT: ret <4 x i32> [[ADD_I]]
-//
-uint32x4_t test_vaddq_u32(uint32x4_t v1, uint32x4_t v2) {
- return vaddq_u32(v1, v2);
-}
-
-// CHECK-LABEL: define dso_local <2 x i64> @test_vaddq_u64(
-// CHECK-SAME: <2 x i64> noundef [[V1:%.*]], <2 x i64> noundef [[V2:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i64> [[V1]], [[V2]]
-// CHECK-NEXT: ret <2 x i64> [[ADD_I]]
-//
-uint64x2_t test_vaddq_u64(uint64x2_t v1, uint64x2_t v2) {
- return vaddq_u64(v1, v2);
-}
-
// CHECK-LABEL: define dso_local <8 x i8> @test_vsub_s8(
-// CHECK-SAME: <8 x i8> noundef [[V1:%.*]], <8 x i8> noundef [[V2:%.*]]) #[[ATTR0]] {
+// CHECK-SAME: <8 x i8> noundef [[V1:%.*]], <8 x i8> noundef [[V2:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[SUB_I:%.*]] = sub <8 x i8> [[V1]], [[V2]]
// CHECK-NEXT: ret <8 x i8> [[SUB_I]]
@@ -8440,26 +8250,6 @@ int64x2_t test_vqdmlsl_high_s32(int64x2_t a, int32x4_t b, int32x4_t c) {
return vqdmlsl_high_s32(a, b, c);
}
-// CHECK-LABEL: define dso_local i64 @test_vaddd_s64(
-// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VADDD_I:%.*]] = add i64 [[A]], [[B]]
-// CHECK-NEXT: ret i64 [[VADDD_I]]
-//
-int64_t test_vaddd_s64(int64_t a, int64_t b) {
- return vaddd_s64(a, b);
-}
-
-// CHECK-LABEL: define dso_local i64 @test_vaddd_u64(
-// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VADDD_I:%.*]] = add i64 [[A]], [[B]]
-// CHECK-NEXT: ret i64 [[VADDD_I]]
-//
-uint64_t test_vaddd_u64(uint64_t a, uint64_t b) {
- return vaddd_u64(a, b);
-}
-
// CHECK-LABEL: define dso_local i64 @test_vsubd_s64(
// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
@@ -18736,16 +18526,6 @@ uint64_t test_vpaddd_u64(uint64x2_t a) {
return vpaddd_u64(a);
}
-// CHECK-LABEL: define dso_local <1 x double> @test_vadd_f64(
-// CHECK-SAME: <1 x double> noundef [[A:%.*]], <1 x double> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[ADD_I:%.*]] = fadd <1 x double> [[A]], [[B]]
-// CHECK-NEXT: ret <1 x double> [[ADD_I]]
-//
-float64x1_t test_vadd_f64(float64x1_t a, float64x1_t b) {
- return vadd_f64(a, b);
-}
-
// CHECK-LABEL: define dso_local <1 x double> @test_vmul_f64(
// CHECK-SAME: <1 x double> noundef [[A:%.*]], <1 x double> noundef [[B:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c
index aa3213efd1735..6b7150a46360d 100644
--- a/clang/test/CodeGen/AArch64/neon/intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c
@@ -6503,3 +6503,250 @@ uint64_t test_vslid_n_u64(uint64_t a, uint64_t b) {
// LLVM: ret i64 [[RET]]
return (uint64_t)vslid_n_u64(a, b, 63);
}
+
+//===------------------------------------------------------===//
+// 2.1.1.1.1 Addition
+// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#addition
+//===------------------------------------------------------===//
+
+// LLVM-LABEL: @test_vadd_s8(
+// CIR-LABEL: @vadd_s8(
+int8x8_t test_vadd_s8(int8x8_t a, int8x8_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: <8 x i8> {{.*}}[[A:%.*]], <8 x i8> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = add <8 x i8> [[A]], [[B]]
+// LLVM: ret <8 x i8> [[ADD_I]]
+ return vadd_s8(a, b);
+}
+
+// LLVM-LABEL: @test_vadd_s16(
+// CIR-LABEL: @vadd_s16(
+int16x4_t test_vadd_s16(int16x4_t a, int16x4_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: <4 x i16> {{.*}}[[A:%.*]], <4 x i16> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = add <4 x i16> [[A]], [[B]]
+// LLVM: ret <4 x i16> [[ADD_I]]
+ return vadd_s16(a, b);
+}
+
+// LLVM-LABEL: @test_vadd_s32(
+// CIR-LABEL: @vadd_s32(
+int32x2_t test_vadd_s32(int32x2_t a, int32x2_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]], <2 x i32> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = add <2 x i32> [[A]], [[B]]
+// LLVM: ret <2 x i32> [[ADD_I]]
+ return vadd_s32(a, b);
+}
+
+// LLVM-LABEL: @test_vadd_s64(
+// CIR-LABEL: @vadd_s64(
+int64x1_t test_vadd_s64(int64x1_t a, int64x1_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: <1 x i64> {{.*}}[[A:%.*]], <1 x i64> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = add <1 x i64> [[A]], [[B]]
+// LLVM: ret <1 x i64> [[ADD_I]]
+ return vadd_s64(a, b);
+}
+
+// LLVM-LABEL: @test_vadd_f32(
+// CIR-LABEL: @vadd_f32(
+float32x2_t test_vadd_f32(float32x2_t a, float32x2_t b) {
+// CIR: cir.fadd
+
+// LLVM-SAME: <2 x float> {{.*}}[[A:%.*]], <2 x float> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = fadd <2 x float> [[A]], [[B]]
+// LLVM: ret <2 x float> [[ADD_I]]
+ return vadd_f32(a, b);
+}
+
+// LLVM-LABEL: @test_vadd_u8(
+// CIR-LABEL: @vadd_u8(
+uint8x8_t test_vadd_u8(uint8x8_t a, uint8x8_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: <8 x i8> {{.*}}[[A:%.*]], <8 x i8> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = add <8 x i8> [[A]], [[B]]
+// LLVM: ret <8 x i8> [[ADD_I]]
+ return vadd_u8(a, b);
+}
+
+// LLVM-LABEL: @test_vadd_u16(
+// CIR-LABEL: @vadd_u16(
+uint16x4_t test_vadd_u16(uint16x4_t a, uint16x4_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: <4 x i16> {{.*}}[[A:%.*]], <4 x i16> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = add <4 x i16> [[A]], [[B]]
+// LLVM: ret <4 x i16> [[ADD_I]]
+ return vadd_u16(a, b);
+}
+
+// LLVM-LABEL: @test_vadd_u32(
+// CIR-LABEL: @vadd_u32(
+uint32x2_t test_vadd_u32(uint32x2_t a, uint32x2_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]], <2 x i32> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = add <2 x i32> [[A]], [[B]]
+// LLVM: ret <2 x i32> [[ADD_I]]
+ return vadd_u32(a, b);
+}
+
+// LLVM-LABEL: @test_vadd_u64(
+// CIR-LABEL: @vadd_u64(
+uint64x1_t test_vadd_u64(uint64x1_t a, uint64x1_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: <1 x i64> {{.*}}[[A:%.*]], <1 x i64> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = add <1 x i64> [[A]], [[B]]
+// LLVM: ret <1 x i64> [[ADD_I]]
+ return vadd_u64(a, b);
+}
+
+// LLVM-LABEL: @test_vaddq_s8(
+// CIR-LABEL: @vaddq_s8(
+int8x16_t test_vaddq_s8(int8x16_t a, int8x16_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]], <16 x i8> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = add <16 x i8> [[A]], [[B]]
+// LLVM: ret <16 x i8> [[ADD_I]]
+ return vaddq_s8(a, b);
+}
+
+// LLVM-LABEL: @test_vaddq_s16(
+// CIR-LABEL: @vaddq_s16(
+int16x8_t test_vaddq_s16(int16x8_t a, int16x8_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]], <8 x i16> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = add <8 x i16> [[A]], [[B]]
+// LLVM: ret <8 x i16> [[ADD_I]]
+ return vaddq_s16(a, b);
+}
+
+// LLVM-LABEL: @test_vaddq_s32(
+// CIR-LABEL: @vaddq_s32(
+int32x4_t test_vaddq_s32(int32x4_t a, int32x4_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: <4 x i32> {{.*}}[[A:%.*]], <4 x i32> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = add <4 x i32> [[A]], [[B]]
+// LLVM: ret <4 x i32> [[ADD_I]]
+ return vaddq_s32(a, b);
+}
+
+// LLVM-LABEL: @test_vaddq_s64(
+// CIR-LABEL: @vaddq_s64(
+int64x2_t test_vaddq_s64(int64x2_t a, int64x2_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: <2 x i64> {{.*}}[[A:%.*]], <2 x i64> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = add <2 x i64> [[A]], [[B]]
+// LLVM: ret <2 x i64> [[ADD_I]]
+ return vaddq_s64(a, b);
+}
+
+// LLVM-LABEL: @test_vaddq_f32(
+// CIR-LABEL: @vaddq_f32(
+float32x4_t test_vaddq_f32(float32x4_t a, float32x4_t b) {
+// CIR: cir.fadd
+
+// LLVM-SAME: <4 x float> {{.*}}[[A:%.*]], <4 x float> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = fadd <4 x float> [[A]], [[B]]
+// LLVM: ret <4 x float> [[ADD_I]]
+ return vaddq_f32(a, b);
+}
+
+// LLVM-LABEL: @test_vaddq_f64(
+// CIR-LABEL: @vaddq_f64(
+float64x2_t test_vaddq_f64(float64x2_t a, float64x2_t b) {
+// CIR: cir.fadd
+
+// LLVM-SAME: <2 x double> {{.*}}[[A:%.*]], <2 x double> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = fadd <2 x double> [[A]], [[B]]
+// LLVM: ret <2 x double> [[ADD_I]]
+ return vaddq_f64(a, b);
+}
+
+// LLVM-LABEL: @test_vaddq_u8(
+// CIR-LABEL: @vaddq_u8(
+uint8x16_t test_vaddq_u8(uint8x16_t a, uint8x16_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]], <16 x i8> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = add <16 x i8> [[A]], [[B]]
+// LLVM: ret <16 x i8> [[ADD_I]]
+ return vaddq_u8(a, b);
+}
+
+// LLVM-LABEL: @test_vaddq_u16(
+// CIR-LABEL: @vaddq_u16(
+uint16x8_t test_vaddq_u16(uint16x8_t a, uint16x8_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]], <8 x i16> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = add <8 x i16> [[A]], [[B]]
+// LLVM: ret <8 x i16> [[ADD_I]]
+ return vaddq_u16(a, b);
+}
+
+// LLVM-LABEL: @test_vaddq_u32(
+// CIR-LABEL: @vaddq_u32(
+uint32x4_t test_vaddq_u32(uint32x4_t a, uint32x4_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: <4 x i32> {{.*}}[[A:%.*]], <4 x i32> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = add <4 x i32> [[A]], [[B]]
+// LLVM: ret <4 x i32> [[ADD_I]]
+ return vaddq_u32(a, b);
+}
+
+// LLVM-LABEL: @test_vaddq_u64(
+// CIR-LABEL: @vaddq_u64(
+uint64x2_t test_vaddq_u64(uint64x2_t a, uint64x2_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: <2 x i64> {{.*}}[[A:%.*]], <2 x i64> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = add <2 x i64> [[A]], [[B]]
+// LLVM: ret <2 x i64> [[ADD_I]]
+ return vaddq_u64(a, b);
+}
+
+// LLVM-LABEL: @test_vadd_f64(
+// CIR-LABEL: @vadd_f64(
+float64x1_t test_vadd_f64(float64x1_t a, float64x1_t b) {
+// CIR: cir.fadd
+
+// LLVM-SAME: <1 x double> {{.*}}[[A:%.*]], <1 x double> {{.*}}[[B:%.*]])
+// LLVM: [[ADD_I:%.*]] = fadd <1 x double> [[A]], [[B]]
+// LLVM: ret <1 x double> [[ADD_I]]
+ return vadd_f64(a, b);
+}
+
+// LLVM-LABEL: @test_vaddd_s64(
+// CIR-LABEL: @vaddd_s64(
+int64_t test_vaddd_s64(int64_t a, int64_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: i64 {{.*}}[[A:%.*]], i64 {{.*}}[[B:%.*]])
+// LLVM: [[VADDD_I:%.*]] = add i64 [[A]], [[B]]
+// LLVM: ret i64 [[VADDD_I]]
+ return vaddd_s64(a, b);
+}
+
+// LLVM-LABEL: @test_vaddd_u64(
+// CIR-LABEL: @vaddd_u64(
+uint64_t test_vaddd_u64(uint64_t a, uint64_t b) {
+// CIR: cir.add
+
+// LLVM-SAME: i64 {{.*}}[[A:%.*]], i64 {{.*}}[[B:%.*]])
+// LLVM: [[VADDD_I:%.*]] = add i64 [[A]], [[B]]
+// LLVM: ret i64 [[VADDD_I]]
+ return vaddd_u64(a, b);
+}
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