[clang] [llvm] [inlineasm] Improve support for multiple inline asm constraints (e.g. "rm") (PR #197798)

[Nick Desaulniers via cfe-commits]

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@@ -0,0 +1,246 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -O0 < %s | FileCheck --check-prefixes=O0 %s
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu     < %s | FileCheck --check-prefixes=O2 %s
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nickdesaulniers wrote:

@bwendling and I met online last Thursday June 24 to discuss this approach more.

Some call outs from this meeting, specifically these `RUN` lines.

For any patches attempting to resolve this long running issue, the test matrix is pretty large.

At the very least, I expect us to test combinations of the following:
- BOTH ISEL frameworks
- BOTH regalloc frameworks
- At least one CISC arch and one RISC arch
- The happy path (no reg pressure) and the unhappy path (proper fallback to "m" under register pressure)
- inline `asm` and inline `asm goto` (`call` vs `callbr`)

For this test case specifically, rather than `-O0` vs `<nothing>`; I'd rather see 4 explicit `RUN` lines, testing the combinations of ISEL and regalloc frameworks.  In particular, I suspect doing so you will find that the changes necessary to SelectionDAGBuilder MUST be mirrored/handled as well in GlobalISEL.  Not seeing changes to GlobalISEL when there are changes to SelectionDAGBuilder is a red flag that to me implies missing test coverage.

https://github.com/llvm/llvm-project/pull/197798