[clang] [llvm] [CIR] vector-saturating-left vqshl_*/ vqshlu_* (PR #199153)
Kartik Ohlan via cfe-commits
cfe-commits at lists.llvm.org
Sun Jun 7 21:49:33 PDT 2026
https://github.com/Ko496-glitch updated https://github.com/llvm/llvm-project/pull/199153
>From 7f3d9116f86c629003a5a415fb73c0301e59dea3 Mon Sep 17 00:00:00 2001
From: Jannick Kremer <jannick.kremer at mailbox.org>
Date: Mon, 8 Jun 2026 06:10:06 +0200
Subject: [PATCH 1/2] added more test
---
.github/workflows/libclang-python-tests.yml | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/.github/workflows/libclang-python-tests.yml b/.github/workflows/libclang-python-tests.yml
index b417cd74c61a9..ae68132965886 100644
--- a/.github/workflows/libclang-python-tests.yml
+++ b/.github/workflows/libclang-python-tests.yml
@@ -30,7 +30,7 @@ jobs:
strategy:
fail-fast: false
matrix:
- python-version: ["3.8", "3.13"]
+ python-version: ["3.8", "3.14"]
steps:
- uses: actions/checkout at de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2
with:
@@ -38,7 +38,6 @@ jobs:
- name: Setup Python
uses: actions/setup-python at a309ff8b426b58ec0e2a45f0f869d46889d02405 # v6.2.0
with:
- persist-credentials: false
python-version: ${{ matrix.python-version }}
- name: Setup ccache
uses: hendrikmuhs/ccache-action at 33522472633dbd32578e909b315f5ee43ba878ce # v1.2.22
>From 2c20180ff511da67d6580c794a3f125a9792bc9b Mon Sep 17 00:00:00 2001
From: Kartik Ohlan <kartik7ohlan at gmail.com>
Date: Sun, 7 Jun 2026 21:49:06 -0700
Subject: [PATCH 2/2] restore the files
---
.../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 4 +
clang/test/CodeGen/AArch64/neon-intrinsics.c | 50 ---
clang/test/CodeGen/AArch64/neon/intrinsics.c | 317 ++++++++++++++++++
3 files changed, 321 insertions(+), 50 deletions(-)
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index be906d0671e3a..854c30013553c 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -441,6 +441,10 @@ static mlir::Value emitCommonNeonSISDBuiltinExpr(
case NEON::BI__builtin_neon_vsrid_n_u64:
case NEON::BI__builtin_neon_vslid_n_s64:
case NEON::BI__builtin_neon_vslid_n_u64:
+ case NEON::BI__builtin_neon_vqshlh_s16:
+ case NEON::BI__builtin_neon_vqshlh_u16:
+ case NEON::BI__builtin_neon_vqshlh_n_s16:
+ case NEON::BI__builtin_neon_vqshlh_n_u16:
break;
}
diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c
index 1f6359bbe2c89..4145f2e7d3ffe 100644
--- a/clang/test/CodeGen/AArch64/neon-intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c
@@ -8677,19 +8677,6 @@ int8_t test_vqshlb_s8(int8_t a, int8_t b) {
return vqshlb_s8(a, b);
}
-// CHECK-LABEL: define dso_local i16 @test_vqshlh_s16(
-// CHECK-SAME: i16 noundef [[A:%.*]], i16 noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0
-// CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0
-// CHECK-NEXT: [[VQSHLH_S16_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i16> [[VQSHLH_S16_I]], i64 0
-// CHECK-NEXT: ret i16 [[TMP2]]
-//
-int16_t test_vqshlh_s16(int16_t a, int16_t b) {
- return vqshlh_s16(a, b);
-}
-
// CHECK-LABEL: define dso_local i32 @test_vqshls_s32(
// CHECK-SAME: i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
@@ -8723,19 +8710,6 @@ uint8_t test_vqshlb_u8(uint8_t a, int8_t b) {
return vqshlb_u8(a, b);
}
-// CHECK-LABEL: define dso_local i16 @test_vqshlh_u16(
-// CHECK-SAME: i16 noundef [[A:%.*]], i16 noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0
-// CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0
-// CHECK-NEXT: [[VQSHLH_U16_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
-// CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i16> [[VQSHLH_U16_I]], i64 0
-// CHECK-NEXT: ret i16 [[TMP2]]
-//
-uint16_t test_vqshlh_u16(uint16_t a, int16_t b) {
- return vqshlh_u16(a, b);
-}
-
// CHECK-LABEL: define dso_local i32 @test_vqshls_u32(
// CHECK-SAME: i32 noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
@@ -14241,18 +14215,6 @@ int8_t test_vqshlb_n_s8(int8_t a) {
return (int8_t)vqshlb_n_s8(a, 7);
}
-// CHECK-LABEL: define dso_local i16 @test_vqshlh_n_s16(
-// CHECK-SAME: i16 noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0
-// CHECK-NEXT: [[VQSHLH_N_S16:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> [[TMP0]], <4 x i16> <i16 15, i16 poison, i16 poison, i16 poison>)
-// CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i16> [[VQSHLH_N_S16]], i64 0
-// CHECK-NEXT: ret i16 [[TMP1]]
-//
-int16_t test_vqshlh_n_s16(int16_t a) {
- return (int16_t)vqshlh_n_s16(a, 15);
-}
-
// CHECK-LABEL: define dso_local i32 @test_vqshls_n_s32(
// CHECK-SAME: i32 noundef [[A:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
@@ -14447,18 +14409,6 @@ uint8_t test_vqshlb_n_u8(uint8_t a) {
return (uint8_t)vqshlb_n_u8(a, 7);
}
-// CHECK-LABEL: define dso_local i16 @test_vqshlh_n_u16(
-// CHECK-SAME: i16 noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0
-// CHECK-NEXT: [[VQSHLH_N_U16:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16> [[TMP0]], <4 x i16> <i16 15, i16 poison, i16 poison, i16 poison>)
-// CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i16> [[VQSHLH_N_U16]], i64 0
-// CHECK-NEXT: ret i16 [[TMP1]]
-//
-uint16_t test_vqshlh_n_u16(uint16_t a) {
- return (uint16_t)vqshlh_n_u16(a, 15);
-}
-
// CHECK-LABEL: define dso_local i32 @test_vqshls_n_u32(
// CHECK-SAME: i32 noundef [[A:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c
index aa3213efd1735..2a274bd9658af 100644
--- a/clang/test/CodeGen/AArch64/neon/intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c
@@ -494,6 +494,323 @@ float64_t test_vmaxvq_f64(float64x2_t a) {
// TODO: Implement the remaining intrinsics from this group.
//===------------------------------------------------------===//
+<<<<<<< Updated upstream
+=======
+// ALL-LABEL: {{.*}}@test_vqshlh_s16(
+int16_t test_vqshlh_s16(int16_t a, int16_t b) {
+ // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshl" {{%.*}}
+
+ // LLVM-SAME: i16 {{.*}}[[A:%.*]], i16 {{.*}}[[B:%.*]])
+ // LLVM: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0
+ // LLVM: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0
+ // LLVM: [[VQSHLH_S16_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+ // LLVM: [[TMP2:%.*]] = extractelement <4 x i16> [[VQSHLH_S16_I]], i64 0
+ // LLVM: ret i16 [[TMP2]]
+ return vqshlh_s16(a, b);
+}
+
+// ALL-LABEL: {{.*}}@test_vqshlh_u16(
+uint16_t test_vqshlh_u16(uint16_t a, int16_t b) {
+ // CIR: cir.call_llvm_intrinsic "aarch64.neon.uqshl" {{%.*}}
+
+ // LLVM-SAME: i16 {{.*}}[[A:%.*]], i16 {{.*}}[[B:%.*]])
+ // LLVM: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0
+ // LLVM: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0
+ // LLVM: [[VQSHLH_U16_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+ // LLVM: [[TMP2:%.*]] = extractelement <4 x i16> [[VQSHLH_U16_I]], i64 0
+ // LLVM: ret i16 [[TMP2]]
+ return vqshlh_u16(a, b);
+}
+
+// ALL-LABEL: {{.*}}@test_vqshlh_n_s16(
+int16_t test_vqshlh_n_s16(int16_t a) {
+ // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshl" {{%.*}}
+
+ // LLVM-SAME: i16 {{.*}}[[A:%.*]])
+ // LLVM: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i64 0
+ // LLVM: [[VQSHLH_N_S16:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> [[TMP0]], <4 x i16> <i16 15, i16 poison, i16 poison, i16 poison>)
+ // LLVM: [[TMP1:%.*]] = extractelement <4 x i16> [[VQSHLH_N_S16]], i64 0
+ // LLVM: ret i16 [[TMP1]]
+ return (int16_t)vqshlh_n_s16(a, 15);
+}
+
+// ALL-LABEL: {{.*}}@test_vqshl_n_s32(
+int32x2_t test_vqshl_n_s32(int32x2_t a) {
+ // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshl"
+
+ // LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]])
+ // LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>
+ // LLVM: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
+ // LLVM: [[VQSHL_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshl.v2i32(<2 x i32> [[VQSHL_N]], <2 x i32> zeroinitializer)
+ // LLVM: ret <2 x i32> [[VQSHL_N1]]
+ return vqshl_n_s32(a, 0);
+}
+
+// ALL-LABEL: {{.*}}@test_vqshl_n_s64(
+int64x1_t test_vqshl_n_s64(int64x1_t a) {
+ // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshl"
+
+ // LLVM-SAME: <1 x i64> {{.*}}[[A:%.*]])
+ // LLVM: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>
+ // LLVM: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
+ // LLVM: [[VQSHL_N1:%.*]] = call <1 x i64> @llvm.aarch64.neon.sqshl.v1i64(<1 x i64> [[VQSHL_N]], <1 x i64> {{.*}})
+ // LLVM: ret <1 x i64> [[VQSHL_N1]]
+ return vqshl_n_s64(a, 1);
+}
+
+// ALL-LABEL: {{.*}}@test_vqshlq_n_s8(
+int8x16_t test_vqshlq_n_s8(int8x16_t a) {
+ // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshl"
+
+ // LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]])
+ // LLVM: [[VQSHL_N:%.*]] = call <16 x i8> @llvm.aarch64.neon.sqshl.v16i8(<16 x i8> [[A]], <16 x i8> zeroinitializer)
+ // LLVM: ret <16 x i8> [[VQSHL_N]]
+ return vqshlq_n_s8(a, 0);
+}
+
+// ALL-LABEL: {{.*}}@test_vqshlq_n_s16(
+int16x8_t test_vqshlq_n_s16(int16x8_t a) {
+ // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshl"
+
+ // LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]])
+ // LLVM: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
+ // LLVM: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
+ // LLVM: [[VQSHL_N1:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqshl.v8i16(<8 x i16> [[VQSHL_N]], <8 x i16> zeroinitializer)
+ // LLVM: ret <8 x i16> [[VQSHL_N1]]
+ return vqshlq_n_s16(a, 0);
+}
+
+// ALL-LABEL: {{.*}}@test_vqshlq_n_s32(
+int32x4_t test_vqshlq_n_s32(int32x4_t a) {
+ // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshl"
+
+ // LLVM-SAME: <4 x i32> {{.*}}[[A:%.*]])
+ // LLVM: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>
+ // LLVM: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
+ // LLVM: [[VQSHL_N1:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqshl.v4i32(<4 x i32> [[VQSHL_N]], <4 x i32> zeroinitializer)
+ // LLVM: ret <4 x i32> [[VQSHL_N1]]
+ return vqshlq_n_s32(a, 0);
+}
+
+// ALL-LABEL: {{.*}}@test_vqshlq_n_s64(
+int64x2_t test_vqshlq_n_s64(int64x2_t a) {
+ // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshl"
+
+ // LLVM-SAME: <2 x i64> {{.*}}[[A:%.*]])
+ // LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>
+ // LLVM: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
+ // LLVM: [[VQSHL_N1:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqshl.v2i64(<2 x i64> [[VQSHL_N]], <2 x i64> zeroinitializer)
+ // LLVM: ret <2 x i64> [[VQSHL_N1]]
+ return vqshlq_n_s64(a, 0);
+}
+
+// ALL-LABEL: {{.*}}@test_vqshl_n_u8(
+uint8x8_t test_vqshl_n_u8(uint8x8_t a) {
+ // CIR: cir.call_llvm_intrinsic "aarch64.neon.uqshl"
+
+ // LLVM-SAME: <8 x i8> {{.*}}[[A:%.*]])
+ // LLVM: [[VQSHL_N:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> [[A]], <8 x i8> zeroinitializer)
+ // LLVM: ret <8 x i8> [[VQSHL_N]]
+ return vqshl_n_u8(a, 0);
+}
+
+// ALL-LABEL: {{.*}}@test_vqshl_n_u16(
+uint16x4_t test_vqshl_n_u16(uint16x4_t a) {
+ // CIR: cir.call_llvm_intrinsic "aarch64.neon.uqshl"
+
+ // LLVM-SAME: <4 x i16> {{.*}}[[A:%.*]])
+ // LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
+ // LLVM: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
+ // LLVM: [[VQSHL_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16> [[VQSHL_N]], <4 x i16> zeroinitializer)
+ // LLVM: ret <4 x i16> [[VQSHL_N1]]
+ return vqshl_n_u16(a, 0);
+}
+
+// ALL-LABEL: {{.*}}@test_vqshl_n_u32(
+uint32x2_t test_vqshl_n_u32(uint32x2_t a) {
+ // CIR: cir.call_llvm_intrinsic "aarch64.neon.uqshl"
+
+ // LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]])
+ // LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>
+ // LLVM: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
+ // LLVM: [[VQSHL_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqshl.v2i32(<2 x i32> [[VQSHL_N]], <2 x i32> zeroinitializer)
+ // LLVM: ret <2 x i32> [[VQSHL_N1]]
+ return vqshl_n_u32(a, 0);
+}
+
+// ALL-LABEL: {{.*}}@test_vqshl_n_u64(
+uint64x1_t test_vqshl_n_u64(uint64x1_t a) {
+ // CIR: cir.call_llvm_intrinsic "aarch64.neon.uqshl"
+
+ // LLVM-SAME: <1 x i64> {{.*}}[[A:%.*]])
+ // LLVM: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>
+ // LLVM: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
+ // LLVM: [[VQSHL_N1:%.*]] = call <1 x i64> @llvm.aarch64.neon.uqshl.v1i64(<1 x i64> [[VQSHL_N]], <1 x i64> {{.*}})
+ // LLVM: ret <1 x i64> [[VQSHL_N1]]
+ return vqshl_n_u64(a, 1);
+}
+
+// ALL-LABEL: {{.*}}@test_vqshlq_n_u8(
+uint8x16_t test_vqshlq_n_u8(uint8x16_t a) {
+ // CIR: cir.call_llvm_intrinsic "aarch64.neon.uqshl"
+
+ // LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]])
+ // LLVM: [[VQSHL_N:%.*]] = call <16 x i8> @llvm.aarch64.neon.uqshl.v16i8(<16 x i8> [[A]], <16 x i8> zeroinitializer)
+ // LLVM: ret <16 x i8> [[VQSHL_N]]
+ return vqshlq_n_u8(a, 0);
+}
+
+// ALL-LABEL: {{.*}}@test_vqshlq_n_u16(
+uint16x8_t test_vqshlq_n_u16(uint16x8_t a) {
+ // CIR: cir.call_llvm_intrinsic "aarch64.neon.uqshl"
+
+ // LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]])
+ // LLVM: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
+ // LLVM: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
+ // LLVM: [[VQSHL_N1:%.*]] = call <8 x i16> @llvm.aarch64.neon.uqshl.v8i16(<8 x i16> [[VQSHL_N]], <8 x i16> zeroinitializer)
+ // LLVM: ret <8 x i16> [[VQSHL_N1]]
+ return vqshlq_n_u16(a, 0);
+}
+
+// ALL-LABEL: {{.*}}@test_vqshlq_n_u32(
+uint32x4_t test_vqshlq_n_u32(uint32x4_t a) {
+ // CIR: cir.call_llvm_intrinsic "aarch64.neon.uqshl"
+
+ // LLVM-SAME: <4 x i32> {{.*}}[[A:%.*]])
+ // LLVM: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>
+ // LLVM: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
+ // LLVM: [[VQSHL_N1:%.*]] = call <4 x i32> @llvm.aarch64.neon.uqshl.v4i32(<4 x i32> [[VQSHL_N]], <4 x i32> zeroinitializer)
+ // LLVM: ret <4 x i32> [[VQSHL_N1]]
+ return vqshlq_n_u32(a, 0);
+}
+
+// ALL-LABEL: {{.*}}@test_vqshlq_n_u64(
+uint64x2_t test_vqshlq_n_u64(uint64x2_t a) {
+ // CIR: cir.call_llvm_intrinsic "aarch64.neon.uqshl"
+
+ // LLVM-SAME: <2 x i64> {{.*}}[[A:%.*]])
+ // LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>
+ // LLVM: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
+ // LLVM: [[VQSHL_N1:%.*]] = call <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64> [[VQSHL_N]], <2 x i64> zeroinitializer)
+ // LLVM: ret <2 x i64> [[VQSHL_N1]]
+ return vqshlq_n_u64(a, 0);
+}
+
+// ALL-LABEL: {{.*}}@test_vqshlu_n_s8(
+uint8x8_t test_vqshlu_n_s8(int8x8_t a) {
+ // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshlu"
+
+ // LLVM-SAME: <8 x i8> {{.*}}[[A:%.*]])
+ // LLVM: [[VQSHLU_N:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshlu.v8i8(<8 x i8> [[A]], <8 x i8> {{.*}})
+ // LLVM: ret <8 x i8> [[VQSHLU_N]]
+ return vqshlu_n_s8(a, 3);
+}
+
+// ALL-LABEL: {{.*}}@test_vqshlu_n_s16(
+uint16x4_t test_vqshlu_n_s16(int16x4_t a) {
+ // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshlu"
+
+ // LLVM-SAME: <4 x i16> {{.*}}[[A:%.*]])
+ // LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
+ // LLVM: [[VQSHLU_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
+ // LLVM: [[VQSHLU_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshlu.v4i16(<4 x i16> [[VQSHLU_N]], <4 x i16> {{.*}})
+ // LLVM: ret <4 x i16> [[VQSHLU_N1]]
+ return vqshlu_n_s16(a, 3);
+}
+
+// ALL-LABEL: {{.*}}@test_vqshlu_n_s32(
+uint32x2_t test_vqshlu_n_s32(int32x2_t a) {
+ // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshlu"
+
+ // LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]])
+ // LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>
+ // LLVM: [[VQSHLU_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
+ // LLVM: [[VQSHLU_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshlu.v2i32(<2 x i32> [[VQSHLU_N]], <2 x i32> {{.*}})
+ // LLVM: ret <2 x i32> [[VQSHLU_N1]]
+ return vqshlu_n_s32(a, 3);
+}
+
+// ALL-LABEL: {{.*}}@test_vqshlu_n_s64(
+uint64x1_t test_vqshlu_n_s64(int64x1_t a) {
+ // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshlu"
+
+ // LLVM-SAME: <1 x i64> {{.*}}[[A:%.*]])
+ // LLVM: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>
+ // LLVM: [[VQSHLU_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
+ // LLVM: [[VQSHLU_N1:%.*]] = call <1 x i64> @llvm.aarch64.neon.sqshlu.v1i64(<1 x i64> [[VQSHLU_N]], <1 x i64> {{.*}})
+ // LLVM: ret <1 x i64> [[VQSHLU_N1]]
+ return vqshlu_n_s64(a, 1);
+}
+
+// ALL-LABEL: {{.*}}@test_vqshluq_n_s8(
+uint8x16_t test_vqshluq_n_s8(int8x16_t a) {
+ // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshlu"
+
+ // LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]])
+ // LLVM: [[VQSHLU_N:%.*]] = call <16 x i8> @llvm.aarch64.neon.sqshlu.v16i8(<16 x i8> [[A]], <16 x i8> splat (i8 3))
+ // LLVM: ret <16 x i8> [[VQSHLU_N]]
+ return vqshluq_n_s8(a, 3);
+}
+
+// ALL-LABEL: {{.*}}@test_vqshluq_n_s16(
+uint16x8_t test_vqshluq_n_s16(int16x8_t a) {
+ // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshlu"
+
+ // LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]])
+ // LLVM: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
+ // LLVM: [[VQSHLU_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
+ // LLVM: [[VQSHLU_N1:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqshlu.v8i16(<8 x i16> [[VQSHLU_N]], <8 x i16> splat (i16 3))
+ // LLVM: ret <8 x i16> [[VQSHLU_N1]]
+ return vqshluq_n_s16(a, 3);
+}
+
+// ALL-LABEL: {{.*}}@test_vqshluq_n_s32(
+uint32x4_t test_vqshluq_n_s32(int32x4_t a) {
+ // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshlu"
+
+ // LLVM-SAME: <4 x i32> {{.*}}[[A:%.*]])
+ // LLVM: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>
+ // LLVM: [[VQSHLU_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
+ // LLVM: [[VQSHLU_N1:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqshlu.v4i32(<4 x i32> [[VQSHLU_N]], <4 x i32> splat (i32 3))
+ // LLVM: ret <4 x i32> [[VQSHLU_N1]]
+ return vqshluq_n_s32(a, 3);
+}
+
+// ALL-LABEL: {{.*}}@test_vqshluq_n_s64(
+uint64x2_t test_vqshluq_n_s64(int64x2_t a) {
+ // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshlu"
+
+ // LLVM-SAME: <2 x i64> {{.*}}[[A:%.*]])
+ // LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>
+ // LLVM: [[VQSHLU_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
+ // LLVM: [[VQSHLU_N1:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqshlu.v2i64(<2 x i64> [[VQSHLU_N]], <2 x i64> splat (i64 3))
+ // LLVM: ret <2 x i64> [[VQSHLU_N1]]
+ return vqshluq_n_s64(a, 3);
+}
+
+// ALL-LABEL: @test_vqshl_n_s8(
+int8x8_t test_vqshl_n_s8(int8x8_t a) {
+ // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshl"
+
+ // LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]])
+ // LLVM: [[VQSHL_N:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8> [[A]], <8 x i8> zeroinitializer)
+ // LLVM: ret <8 x i8> [[VQSHL_N]]
+ return vqshl_n_s8(a, 0);
+}
+
+// ALL-LABEL: @test_vqshl_n_s16(
+int16x4_t test_vqshl_n_s16(int16x4_t a) {
+ // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshl"
+ //
+ // LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]])
+ // LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
+ // LLVM: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
+ // LLVM: [[VQSHL_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> [[VQSHL_N]], <4 x i16> zeroinitializer)
+ // LLVM: ret <4 x i16> [[VQSHL_N1]]
+ return vqshl_n_s16(a, 0);
+}
+
+>>>>>>> Stashed changes
// ALL-LABEL: @test_vqshlud_n_s64(
int64_t test_vqshlud_n_s64(int64_t a) {
// CIR: [[CONST:%.*]] = cir.const #cir.int<63> : !s64i
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