[clang] [llvm] [AArch64][clang][llvm] Add ACLE Armv9.7 lookup table intrinsics (PR #187046)

[Jonathan Thackray via cfe-commits]

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@@ -3921,15 +3921,19 @@ multiclass sme2_luti4_vector_vg4_index<string mnemonic> {
 }
 
 // 8-bit Look up table
-class sme2_lut_single<string asm>
-  : I<(outs ZPR8:$Zd), (ins ZTR:$ZTt, ZPRAny:$Zn),
-    asm, "\t$Zd, $ZTt, $Zn", "", []>, Sched<[]> {
-  bits<0> ZTt;
-  bits<5> Zd;
-  bits<5> Zn;
-  let Inst{31-10} = 0b1100000011001000010000;
-  let Inst{9-5}   = Zn;
-  let Inst{4-0}   = Zd;
+multiclass sme2_lut_single<string asm, SDPatternOperator intrinsic> {
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jthackray wrote:

Sure, done.

https://github.com/llvm/llvm-project/pull/187046