[clang] 7da29bc - [RISCV][MC] Support experimental Zvdota Family instructions (#195069)
via cfe-commits
cfe-commits at lists.llvm.org
Thu Jun 4 01:45:11 PDT 2026
Author: Liao Chunyu
Date: 2026-06-04T16:45:05+08:00
New Revision: 7da29bc529d74d327804ad25e49e0cdeccfed263
URL: https://github.com/llvm/llvm-project/commit/7da29bc529d74d327804ad25e49e0cdeccfed263
DIFF: https://github.com/llvm/llvm-project/commit/7da29bc529d74d327804ad25e49e0cdeccfed263.diff
LOG: [RISCV][MC] Support experimental Zvdota Family instructions (#195069)
Spec:
https://github.com/aswaterman/riscv-misc/blob/main/isa/ldot-bdot/ldot-bdot.adoc
---------
Co-authored-by: Brandon Wu <songwu0813 at gmail.com>
Co-authored-by: Craig Topper <craig.topper at sifive.com>
Added:
llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td
llvm/test/MC/RISCV/rvv/zvfqwdota8f.s
llvm/test/MC/RISCV/rvv/zvfwdota16bf.s
llvm/test/MC/RISCV/rvv/zvqwdotai8i16.s
Modified:
clang/test/Driver/print-supported-extensions-riscv.c
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/docs/ReleaseNotes.md
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/CodeGen/RISCV/features-info.ll
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Removed:
################################################################################
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 29731e565ecfc..4254009e0fa86 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -255,10 +255,14 @@
// CHECK-NEXT: zvfbfa 0.1 'Zvfbfa' (Additional BF16 vector compute support)
// CHECK-NEXT: zvfofp8min 0.2 'Zvfofp8min' (Vector OFP8 Converts)
// CHECK-NEXT: zvfqwbdota8f 0.2 'Zvfqwbdota8f' (OCP FP8 batched dot-product extension)
+// CHECK-NEXT: zvfqwdota8f 0.2 'Zvfqwdota8f' (OCP FP8 Dot-Product)
// CHECK-NEXT: zvfwbdota16bf 0.2 'Zvfwbdota16bf' (BF16 batched dot-product extension)
+// CHECK-NEXT: zvfwdota16bf 0.2 'Zvfwdota16bf' (BF16 Dot-Product)
// CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)
// CHECK-NEXT: zvqwbdota16i 0.2 'Zvqwbdota16i' (16-bit integer batched dot-product extension)
// CHECK-NEXT: zvqwbdota8i 0.2 'Zvqwbdota8i' (8-bit integer batched dot-product extension)
+// CHECK-NEXT: zvqwdota16i 0.2 'Zvqwdota16i' (16-bit Integer Dot-Product)
+// CHECK-NEXT: zvqwdota8i 0.2 'Zvqwdota8i' (8-bit Integer Dot-Product)
// CHECK-NEXT: zvvfmm 0.1 'Zvvfmm' (Floating-Point Matrix Multiply-Accumulate)
// CHECK-NEXT: zvvmm 0.1 'Zvvmm' (Integer Matrix Multiply-Accumulate)
// CHECK-NEXT: zvzip 0.1 'Zvzip' (Vector Reordering Structured Data)
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index b35ba6fa094a0..28031814da16a 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -150,6 +150,10 @@
// CHECK-NOT: __riscv_zve64d {{.*$}}
// CHECK-NOT: __riscv_zve64f {{.*$}}
// CHECK-NOT: __riscv_zve64x {{.*$}}
+// CHECK-NOT: __riscv_zvqwdota8i {{.*$}}
+// CHECK-NOT: __riscv_zvqwdota16i {{.*$}}
+// CHECK-NOT: __riscv_zvfqwdota8f {{.*$}}
+// CHECK-NOT: __riscv_zvfwdota16bf {{.*$}}
// CHECK-NOT: __riscv_zvfbfmin {{.*$}}
// CHECK-NOT: __riscv_zvfbfwma {{.*$}}
// CHECK-NOT: __riscv_zvfh {{.*$}}
@@ -1696,6 +1700,38 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVDOT4A8I-EXT %s
// CHECK-ZVDOT4A8I-EXT: __riscv_zvdot4a8i 1000{{$}}
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zve32x_zvqwdota8i0p2 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVQWDOTA8I-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zve32x_zvqwdota8i0p2 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVQWDOTA8I-EXT %s
+// CHECK-ZVQWDOTA8I-EXT: __riscv_zvqwdota8i 2000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zve64x_zvqwdota16i0p2 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVQWDOTA16I-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zve64x_zvqwdota16i0p2 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVQWDOTA16I-EXT %s
+// CHECK-ZVQWDOTA16I-EXT: __riscv_zvqwdota16i 2000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zve32f_zvfqwdota8f0p2 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFQWDOTA8F-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zve32f_zvfqwdota8f0p2 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFQWDOTA8F-EXT %s
+// CHECK-ZVFQWDOTA8F-EXT: __riscv_zvfqwdota8f 2000{{$}}
+
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zve32f_zvfwdota16bf0p2 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFWDOTA16BF-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zve32f_zvfwdota16bf0p2 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFWDOTA16BF-EXT %s
+// CHECK-ZVFWDOTA16BF-EXT: __riscv_zvfwdota16bf 2000{{$}}
+
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32i_zve32x_zvzip0p1 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVZVIP-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 166b5dd6352db..058a931ebe318 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -354,6 +354,9 @@ The primary goal of experimental support is to assist in the process of ratifica
``experimental-zvdot4a8i``
LLVM implements the `0.1 draft specification <https://github.com/riscv/riscv-isa-manual/pull/2576>`__.
+``experimental-zvqwdota8i``, ``experimental-zvqwdota16i``, ``experimental-zvfwdota16bf``, ``experimental-zvfqwdota8f``
+ LLVM implements the `0.2 draft specification <https://github.com/aswaterman/riscv-misc/blob/main/isa/ldot-bdot/ldot-bdot.adoc>`__.
+
``experimental-smpmpmt``
LLVM implements the `0.6 draft specification <https://github.com/riscv/riscv-isa-manual/blob/smpmpmt/src/smpmpmt.adoc>`__.
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index b4c15eb0b2fa0..19d51ce17355e 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -240,6 +240,7 @@ Makes programs 10x faster by doing Special New Thing.
* Adds experimental assembler support for the `Xqccmt` (Qualcomm 16-bit Table Jump) vendor extension.
* `-mcpu=sifive-870` has been renamed `-mcpu=sifive-p870-d`.
* Adds experimental assembler support for batched dot-product extensions(Zvqwbdota8i, Zvqwbdota16i, Zvfwbdota16bf, Zvfqwbdota8f and Zvfbdota32f).
+* Adds experimental assembler support for dot-product extensions(Zvqwdota8i, Zvqwdota16i, Zvfwdota16bf and Zvfqwdota8f).
### Changes to the WebAssembly Backend
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 93fb1fa5a889f..988678fce1d8b 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2446,6 +2446,10 @@ ParseStatus RISCVAsmParser::parseVTypeI(OperandVector &Operands) {
bool RISCVAsmParser::generateVTypeError(SMLoc ErrorLoc) {
if (STI->hasFeature(RISCV::FeatureStdExtZvfbfa) ||
+ STI->hasFeature(RISCV::FeatureStdExtZvqwdota8i) ||
+ STI->hasFeature(RISCV::FeatureStdExtZvqwdota16i) ||
+ STI->hasFeature(RISCV::FeatureStdExtZvfwdota16bf) ||
+ STI->hasFeature(RISCV::FeatureStdExtZvfqwdota8f) ||
STI->hasFeature(RISCV::FeatureStdExtZvfofp8min) ||
STI->hasFeature(RISCV::FeatureVendorXSfvfbfexp16e) ||
STI->hasFeature(RISCV::FeatureStdExtZvqwbdota8i) ||
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
index aa7ce5bf5e2a2..6cb0f449fefbb 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
@@ -225,7 +225,11 @@ void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
// above.
if (!RISCVVType::isValidVType(Imm) ||
(RISCVVType::isAltFmt(Imm) &&
- !(STI.hasFeature(RISCV::FeatureStdExtZvfbfa) ||
+ !(STI.hasFeature(RISCV::FeatureStdExtZvqwdota8i) ||
+ STI.hasFeature(RISCV::FeatureStdExtZvqwdota16i) ||
+ STI.hasFeature(RISCV::FeatureStdExtZvfwdota16bf) ||
+ STI.hasFeature(RISCV::FeatureStdExtZvfqwdota8f) ||
+ STI.hasFeature(RISCV::FeatureStdExtZvfbfa) ||
STI.hasFeature(RISCV::FeatureStdExtZvfofp8min) ||
STI.hasFeature(RISCV::FeatureVendorXSfvfbfexp16e) ||
STI.hasFeature(RISCV::FeatureStdExtZvqwbdota8i) ||
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 93392c1b3d402..4da4cd2ebe303 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -689,6 +689,32 @@ def HasStdExtZvabd : Predicate<"Subtarget->hasStdExtZvabd()">,
AssemblerPredicate<(all_of FeatureStdExtZvabd),
"'Zvabd' (Vector Absolute Difference)">;
+def FeatureStdExtZvqwdota8i
+ : RISCVExperimentalExtension<0, 2, "8-bit Integer Dot-Product",
+ [FeatureStdExtZve32x]>;
+
+def FeatureStdExtZvqwdota16i
+ : RISCVExperimentalExtension<0, 2, "16-bit Integer Dot-Product",
+ [FeatureStdExtZve64x]>;
+
+def HasStdExtZvqwdota8iOrZvqwdota16i
+ : Predicate<"Subtarget->hasStdExtZvqwdota8i() || Subtarget->hasStdExtZvqwdota16i()">,
+ AssemblerPredicate<(any_of FeatureStdExtZvqwdota8i, FeatureStdExtZvqwdota16i),
+ "'Zvqwdota8i' (8-bit Integer Dot-Product) or "
+ "'Zvqwdota16i' (16-bit Integer Dot-Product)">;
+
+def FeatureStdExtZvfwdota16bf
+ : RISCVExperimentalExtension<0, 2, "BF16 Dot-Product", [FeatureStdExtZve32f]>;
+def HasStdExtZvfwdota16bf : Predicate<"Subtarget->hasStdExtZvfwdota16bf()">,
+ AssemblerPredicate<(all_of FeatureStdExtZvfwdota16bf),
+ "'Zvfwdota16bf' (BF16 Dot-Product)">;
+
+def FeatureStdExtZvfqwdota8f
+ : RISCVExperimentalExtension<0, 2, "OCP FP8 Dot-Product", [FeatureStdExtZve32f]>;
+def HasStdExtZvfqwdota8f : Predicate<"Subtarget->hasStdExtZvfqwdota8f()">,
+ AssemblerPredicate<(all_of FeatureStdExtZvfqwdota8f),
+ "'Zvfqwdota8f' (OCP FP8 Dot-Product)">;
+
def FeatureStdExtZvfbfa
: RISCVExperimentalExtension<0, 1, "Additional BF16 vector compute support",
[FeatureStdExtZve32f, FeatureStdExtZfbfmin]>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 68f07029e90b0..ffb0d5eeae0f9 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2380,6 +2380,7 @@ include "RISCVInstrInfoZk.td"
// Vector
include "RISCVInstrInfoV.td"
include "RISCVInstrInfoZvabd.td"
+include "RISCVInstrInfoZvdota.td"
include "RISCVInstrInfoZvk.td"
include "RISCVInstrInfoZvdot4a8i.td"
include "RISCVInstrInfoZvfofp8min.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td
new file mode 100644
index 0000000000000..f40cb4f8d7824
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvdota.td
@@ -0,0 +1,42 @@
+//===-- RISCVInstrInfoZvdota.td - 'Zvdota' instructions ----*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// This file describes the RISC-V instructions for 'Zvdota'.
+///
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Instruction Definitions
+//===----------------------------------------------------------------------===//
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+// op vd, vs2, vs1, vm
+class ZvdotVALUVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+ : RVInstVV<funct6, opv, (outs VR:$vd_wb),
+ (ins VR:$vd, VR:$vs2, VR:$vs1, VMaskOp:$vm),
+ opcodestr, "$vd, $vs2, $vs1$vm"> {
+ let Inst{6-0} = OPC_OP_VE.Value;
+ let Constraints = "@earlyclobber $vd_wb, $vd = $vd_wb";
+ let VS1VS2Constraint = Vrgather;
+}
+}
+
+let Predicates = [HasStdExtZvqwdota8iOrZvqwdota16i], DestEEW = EEWSEWx4 in {
+ def VQWDOTAU_VV : ZvdotVALUVV<0b100110, OPIVV, "vqwdotau.vv">;
+ def VQWDOTAS_VV : ZvdotVALUVV<0b100111, OPIVV, "vqwdotas.vv">;
+} // Predicates = [HasStdExtZvqwdota8iOrZvqwdota16i]
+
+let Predicates = [HasStdExtZvfqwdota8f],
+ mayRaiseFPException = true, DestEEW = EEWSEWx4 in {
+ def VFQWDOTA_VV : ZvdotVALUVV<0b100110, OPFVV, "vfqwdota.vv">;
+ def VFQWDOTA_ALT_VV : ZvdotVALUVV<0b100111, OPFVV, "vfqwdota.alt.vv">;
+} // Predicates = [HasStdExtZvfqwdota8f]
+
+let Predicates = [HasStdExtZvfwdota16bf],
+ mayRaiseFPException = true, DestEEW = EEWSEWx2 in {
+ def VFWDOTA_VV : ZvdotVALUVV<0b100100, OPFVV, "vfwdota.vv">;
+} // Predicates = [HasStdExtZvfwdota16bf]
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index f3cec654f57ae..26ffd8bb4ec89 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -275,6 +275,10 @@
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvksh %s -o - | FileCheck --check-prefix=RV64ZVKSH %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck --check-prefix=RV64ZVKT %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvdot4a8i %s -o - | FileCheck --check-prefix=RV64ZVDOT4A8I %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvqwdota8i %s -o - | FileCheck --check-prefix=RV64ZVQWDOTA8I %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvqwdota16i %s -o - | FileCheck --check-prefix=RV64ZVQWDOTA16I %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32f -mattr=+experimental-zvfwdota16bf %s -o - | FileCheck --check-prefix=RV64ZVFWDOTA16BF %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32f -mattr=+experimental-zvfqwdota8f %s -o - | FileCheck --check-prefix=RV64ZVFQWDOTA8F %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvzip %s -o - | FileCheck --check-prefix=RV64ZVZIP %s
; RUN: llc -mtriple=riscv64 -mattr=+zvfh %s -o - | FileCheck --check-prefix=RV64ZVFH %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvabd %s -o - | FileCheck --check-prefix=RV64ZVABD %s
@@ -609,6 +613,10 @@
; RV64ZVKSH: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksh1p0_zvl32b1p0"
; RV64ZVKT: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkt1p0_zvl32b1p0"
; RV64ZVDOT4A8I: .attribute 5, "rv64i2p1_zicsr2p0_zvdot4a8i0p1_zve32x1p0_zvl32b1p0"
+; RV64ZVQWDOTA8I: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvqwdota8i0p2"
+; RV64ZVQWDOTA16I: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_zvqwdota16i0p2"
+; RV64ZVFWDOTA16BF: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfwdota16bf0p2_zvl32b1p0"
+; RV64ZVFQWDOTA8F: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfqwdota8f0p2_zvl32b1p0"
; RV64ZVZIP: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvzip0p1"
; RV64ZVFH: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0"
; RV64ZVABD: .attribute 5, "rv64i2p1_zicsr2p0_zvabd0p7_zve32x1p0_zvl32b1p0"
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index 92a514f932632..5004ba2ce6167 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -40,10 +40,14 @@
; CHECK-NEXT: experimental-zvfbfa - 'Zvfbfa' (Additional BF16 vector compute support).
; CHECK-NEXT: experimental-zvfofp8min - 'Zvfofp8min' (Vector OFP8 Converts).
; CHECK-NEXT: experimental-zvfqwbdota8f - 'Zvfqwbdota8f' (OCP FP8 batched dot-product extension).
+; CHECK-NEXT: experimental-zvfqwdota8f - 'Zvfqwdota8f' (OCP FP8 Dot-Product).
; CHECK-NEXT: experimental-zvfwbdota16bf - 'Zvfwbdota16bf' (BF16 batched dot-product extension).
+; CHECK-NEXT: experimental-zvfwdota16bf - 'Zvfwdota16bf' (BF16 Dot-Product).
; CHECK-NEXT: experimental-zvkgs - 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography).
; CHECK-NEXT: experimental-zvqwbdota16i - 'Zvqwbdota16i' (16-bit integer batched dot-product extension).
; CHECK-NEXT: experimental-zvqwbdota8i - 'Zvqwbdota8i' (8-bit integer batched dot-product extension).
+; CHECK-NEXT: experimental-zvqwdota16i - 'Zvqwdota16i' (16-bit Integer Dot-Product).
+; CHECK-NEXT: experimental-zvqwdota8i - 'Zvqwdota8i' (8-bit Integer Dot-Product).
; CHECK-NEXT: experimental-zvvfmm - 'Zvvfmm' (Floating-Point Matrix Multiply-Accumulate).
; CHECK-NEXT: experimental-zvvmm - 'Zvvmm' (Integer Matrix Multiply-Accumulate).
; CHECK-NEXT: experimental-zvzip - 'Zvzip' (Vector Reordering Structured Data).
diff --git a/llvm/test/MC/RISCV/rvv/zvfqwdota8f.s b/llvm/test/MC/RISCV/rvv/zvfqwdota8f.s
new file mode 100644
index 0000000000000..31140a9c4fb3a
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/zvfqwdota8f.s
@@ -0,0 +1,33 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+v --mattr=+experimental-zvfqwdota8f %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+v --mattr=+experimental-zvfqwdota8f %s \
+# RUN: | llvm-objdump -d --mattr=+v --mattr=+experimental-zvfqwdota8f --no-print-imm-hex - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+
+vsetvli a2, a0, e8alt, m1, ta, ma
+# CHECK-INST: vsetvli a2, a0, e8alt, m1, ta, ma
+# CHECK-ENCODING: [0x57,0x76,0x05,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
+
+vfqwdota.vv v10, v9, v8
+# CHECK-INST: vfqwdota.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x15,0x94,0x9a]
+# CHECK-ERROR: instruction requires the following: 'Zvfqwdota8f' (OCP FP8 Dot-Product)
+
+vfqwdota.vv v10, v9, v8, v0.t
+# CHECK-INST: vfqwdota.vv v10, v9, v8, v0.t
+# CHECK-ENCODING: [0x77,0x15,0x94,0x98]
+# CHECK-ERROR: instruction requires the following: 'Zvfqwdota8f' (OCP FP8 Dot-Product)
+
+vfqwdota.alt.vv v10, v9, v8
+# CHECK-INST: vfqwdota.alt.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x15,0x94,0x9e]
+# CHECK-ERROR: instruction requires the following: 'Zvfqwdota8f' (OCP FP8 Dot-Product)
+
+vfqwdota.alt.vv v10, v9, v8, v0.t
+# CHECK-INST: vfqwdota.alt.vv v10, v9, v8, v0.t
+# CHECK-ENCODING: [0x77,0x15,0x94,0x9c]
+# CHECK-ERROR: instruction requires the following: 'Zvfqwdota8f' (OCP FP8 Dot-Product)
+
diff --git a/llvm/test/MC/RISCV/rvv/zvfwdota16bf.s b/llvm/test/MC/RISCV/rvv/zvfwdota16bf.s
new file mode 100644
index 0000000000000..e1ff3c3d6d0ac
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/zvfwdota16bf.s
@@ -0,0 +1,22 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+v --mattr=+experimental-zvfwdota16bf %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+v --mattr=+experimental-zvfwdota16bf %s \
+# RUN: | llvm-objdump -d --mattr=+v --mattr=+experimental-zvfwdota16bf --no-print-imm-hex - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+
+vsetvli a2, a0, e16alt, m1, ta, ma
+# CHECK-INST: vsetvli a2, a0, e16alt, m1, ta, ma
+# CHECK-ENCODING: [0x57,0x76,0x85,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
+
+vfwdota.vv v10, v9, v8
+# CHECK-INST: vfwdota.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x15,0x94,0x92]
+# CHECK-ERROR: instruction requires the following: 'Zvfwdota16bf' (BF16 Dot-Product)
+
+vfwdota.vv v10, v9, v8, v0.t
+# CHECK-INST: vfwdota.vv v10, v9, v8, v0.t
+# CHECK-ENCODING: [0x77,0x15,0x94,0x90]
+# CHECK-ERROR: instruction requires the following: 'Zvfwdota16bf' (BF16 Dot-Product)
diff --git a/llvm/test/MC/RISCV/rvv/zvqwdotai8i16.s b/llvm/test/MC/RISCV/rvv/zvqwdotai8i16.s
new file mode 100644
index 0000000000000..2cebc3702af34
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/zvqwdotai8i16.s
@@ -0,0 +1,22 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+v --mattr=+experimental-zvqwdota8i %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+v --mattr=+experimental-zvqwdota8i %s \
+# RUN: | llvm-objdump -d --mattr=+v --mattr=+experimental-zvqwdota8i --no-print-imm-hex - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+
+vsetvli a2, a0, e8alt, m1, ta, ma
+# CHECK-INST: vsetvli a2, a0, e8alt, m1, ta, ma
+# CHECK-ENCODING: [0x57,0x76,0x05,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}}
+
+vqwdotau.vv v10, v9, v8
+# CHECK-INST: vqwdotau.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x05,0x94,0x9a]
+# CHECK-ERROR: instruction requires the following: 'Zvqwdota8i' (8-bit Integer Dot-Product) or 'Zvqwdota16i' (16-bit Integer Dot-Product)
+
+vqwdotau.vv v10, v9, v8, v0.t
+# CHECK-INST: vqwdotau.vv v10, v9, v8, v0.t
+# CHECK-ENCODING: [0x77,0x05,0x94,0x98]
+# CHECK-ERROR: instruction requires the following: 'Zvqwdota8i' (8-bit Integer Dot-Product) or 'Zvqwdota16i' (16-bit Integer Dot-Product)
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 9e7f23e2b4f76..feaea1f484e36 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1391,10 +1391,14 @@ Experimental extensions
zvfbfa 0.1
zvfofp8min 0.2
zvfqwbdota8f 0.2
+ zvfqwdota8f 0.2
zvfwbdota16bf 0.2
+ zvfwdota16bf 0.2
zvkgs 0.7
zvqwbdota16i 0.2
zvqwbdota8i 0.2
+ zvqwdota16i 0.2
+ zvqwdota8i 0.2
zvvfmm 0.1
zvvmm 0.1
zvzip 0.1
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