[clang] [llvm][RISCV] Revise xsfmm intrinsic interface. (PR #201527)
Brandon Wu via cfe-commits
cfe-commits at lists.llvm.org
Thu Jun 4 01:36:27 PDT 2026
https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/201527
This patch does 2 things:
1. Change matmul interface to use newly defined OFP8 RVV types.
2. change all of matmul overloaded interfaces to only keep only widen information and eliminate types information.
>From 8b3cdf4dfb927a139b0d7972380f89da3a6b16de Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Tue, 26 May 2026 21:29:54 +0800
Subject: [PATCH] [llvm][RISCV] Revise xsfmm intrinsic interface.
This patch does 2 things:
1. Change matmul interface to use newly defined OFP8 RVV types.
2. change all of matmul overloaded interfaces to only keep only widen
information and eliminate types information.
---
.../clang/Basic/riscv_sifive_vector.td | 13 +++++-----
.../clang/Basic/riscv_vector_common.td | 3 +++
.../clang/Support/RISCVVIntrinsicUtils.h | 10 ++++----
clang/lib/Support/RISCVVIntrinsicUtils.cpp | 11 +++++++++
.../non-overloaded/sf_mm_e4m3_e4m3.c | 11 +++++----
.../non-overloaded/sf_mm_e4m3_e5m2.c | 11 +++++----
.../non-overloaded/sf_mm_e5m2_e4m3.c | 11 +++++----
.../non-overloaded/sf_mm_e5m2_e5m2.c | 11 +++++----
.../non-policy/overloaded/sf_mm_e4m3_e4m3.c | 11 +++++----
.../non-policy/overloaded/sf_mm_e4m3_e5m2.c | 11 +++++----
.../non-policy/overloaded/sf_mm_e5m2_e4m3.c | 11 +++++----
.../non-policy/overloaded/sf_mm_e5m2_e5m2.c | 11 +++++----
.../non-policy/overloaded/sf_mm_f_f.c | 6 ++---
.../non-policy/overloaded/sf_mm_s_s.c | 2 +-
.../non-policy/overloaded/sf_mm_s_u.c | 2 +-
.../non-policy/overloaded/sf_mm_u_s.c | 2 +-
.../non-policy/overloaded/sf_mm_u_u.c | 2 +-
clang/test/Sema/sifive-xsfmm.c | 24 ++++++++++---------
18 files changed, 95 insertions(+), 68 deletions(-)
diff --git a/clang/include/clang/Basic/riscv_sifive_vector.td b/clang/include/clang/Basic/riscv_sifive_vector.td
index 0371279aafc08..01f732c129e2b 100644
--- a/clang/include/clang/Basic/riscv_sifive_vector.td
+++ b/clang/include/clang/Basic/riscv_sifive_vector.td
@@ -298,7 +298,7 @@ multiclass RVVOp0Op1Op2BuiltinSet<string intrinsic_name, string type_range,
multiclass RVVSFMatMulBuiltinSet<string prototype, string suffix,
string type_range, list<int> widens> {
foreach widen = widens in
- let OverloadedName = NAME,
+ let OverloadedName = "sf_mm_w" # !cast<string>(widen),
TWiden = widen,
HasVL = false,
Log2LMUL = [3],
@@ -311,7 +311,7 @@ multiclass RVVSFMatMulFloatBuiltinSet<string name, string prototype, string suff
list<string> type_range, int widen> {
// Currently the XSfmm spec doesn't support w8.
foreach type = type_range in
- let OverloadedName = name # !strconcat("_w", !cast<string>(widen)),
+ let OverloadedName = "sf_mm_w" # !cast<string>(widen),
TWiden = widen,
HasVL = false,
Log2LMUL = [3],
@@ -388,10 +388,11 @@ let RequiredFeatures = ["xsfmm32a32f"] in
let RequiredFeatures = ["xsfmm32a8f"] in
foreach e1 = [5, 4] in
foreach e2 = [5, 4] in
- let OverloadedName = "sf_mm_e" # e1 # "m" # !sub(7, e1) # "_e" # e2 # "m" # !sub(7, e2) in
- defm : RVVSFMatMulFloatBuiltinSet<
- "sf_mm_e" # e1 # "m" # !sub(7, e1) # "_e" # e2 # "m" # !sub(7, e2),
- "0KzUvUvzzz", "UvUv", ["c"], 4>;
+ defm : RVVSFMatMulFloatBuiltinSet<
+ "sf_mm_e" # e1 # "m" # !sub(7, e1) # "_e" # e2 # "m" # !sub(7, e2),
+ !if(!eq(e1, e2), "0Kzvvzzz", "0KzvAvzzz"),
+ !if(!eq(e1, e2), "vv", "vAv"),
+ [!if(!eq(e1, 5), "b", "a")], 4>;
let RequiredFeatures = ["xsfmm64a64f"] in
defm : RVVSFMatMulFloatBuiltinSet<"sf_mm_f_f", "0Kzvvzzz", "v", ["d"], 1>;
diff --git a/clang/include/clang/Basic/riscv_vector_common.td b/clang/include/clang/Basic/riscv_vector_common.td
index f683e7137e1f2..739bbdd6f66e6 100644
--- a/clang/include/clang/Basic/riscv_vector_common.td
+++ b/clang/include/clang/Basic/riscv_vector_common.td
@@ -89,6 +89,9 @@
// of the same width
// S: given a vector type, computes its equivalent one for LMUL=1. This is a
// no-op if the vector was already LMUL=1
+// A: given a vector type whose element type is one of the OFP8 formats
+// (float8e4m3 or float8e5m2), computes the vector type with the
+// alternative OFP8 element type (e4m3 <-> e5m2).
// (Log2EEW:Value): Log2EEW value could be 3/4/5/6 (8/16/32/64), given a
// vector type (SEW and LMUL) and EEW (8/16/32/64), computes its
// equivalent integer vector type with EEW and corresponding ELMUL (elmul =
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
index 678fe22a66e16..3ea5725057f05 100644
--- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -90,7 +90,7 @@ enum class BaseTypeModifier : uint8_t {
};
// Modifier for type, used for both scalar and vector types.
-enum class TypeModifier : uint8_t {
+enum class TypeModifier : uint16_t {
NoModifier = 0,
Pointer = 1 << 0,
Const = 1 << 1,
@@ -105,8 +105,10 @@ enum class TypeModifier : uint8_t {
// simple enum, so we decide keek LMUL1 in TypeModifier for code size
// optimization of clang binary size.
LMUL1 = 1 << 7,
- MaxOffset = 7,
- LLVM_MARK_AS_BITMASK_ENUM(LMUL1),
+ // Toggle between the two OFP8 element types (FloatE4M3 <-> FloatE5M2).
+ AltFP8 = 1 << 8,
+ MaxOffset = 8,
+ LLVM_MARK_AS_BITMASK_ENUM(AltFP8),
};
class Policy {
@@ -175,7 +177,7 @@ struct PrototypeDescriptor {
VectorTypeModifier VTM = VectorTypeModifier::NoModifier,
TypeModifier TM = TypeModifier::NoModifier)
: PT(PT), VTM(VTM), TM(TM) {}
- constexpr PrototypeDescriptor(uint8_t PT, uint8_t VTM, uint8_t TM)
+ constexpr PrototypeDescriptor(uint8_t PT, uint8_t VTM, uint16_t TM)
: PT(static_cast<BaseTypeModifier>(PT)),
VTM(static_cast<VectorTypeModifier>(VTM)),
TM(static_cast<TypeModifier>(TM)) {}
diff --git a/clang/lib/Support/RISCVVIntrinsicUtils.cpp b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
index 1138b9fc12798..5031bf5a1a8ff 100644
--- a/clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -696,6 +696,9 @@ PrototypeDescriptor::parsePrototypeDescriptor(
case 'S':
TM |= TypeModifier::LMUL1;
break;
+ case 'A':
+ TM |= TypeModifier::AltFP8;
+ break;
default:
llvm_unreachable("Illegal non-primitive type transformer!");
}
@@ -913,6 +916,14 @@ void RVVType::applyModifier(const PrototypeDescriptor &Transformer) {
// Update ElementBitwidth need to update Scale too.
Scale = LMUL.getScale(ElementBitwidth);
break;
+ case TypeModifier::AltFP8:
+ if (ScalarType == ScalarTypeKind::FloatE4M3)
+ ScalarType = ScalarTypeKind::FloatE5M2;
+ else if (ScalarType == ScalarTypeKind::FloatE5M2)
+ ScalarType = ScalarTypeKind::FloatE4M3;
+ else
+ llvm_unreachable("AltFP8 modifier requires an OFP8 base type");
+ break;
default:
llvm_unreachable("Unknown type modifier mask!");
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c
index d162f449d9239..540c086c9c1ea 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c
@@ -1,18 +1,19 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmm32a8f \
-// RUN: -disable-O0-optnone -emit-llvm %s -o - | \
-// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+// RUN: -target-feature +experimental-zvfofp8min -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_e4m3_e4m3_w4_u8m8_u8m8(
+// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_e4m3_e4m3_w4_f8e4m3m8_f8e4m3m8(
// CHECK-RV64-SAME: <vscale x 64 x i8> [[vs2:%.*]], <vscale x 64 x i8> [[vs1:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 0, <vscale x 64 x i8> [[vs2]], <vscale x 64 x i8> [[vs1]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4)
// CHECK-RV64-NEXT: ret void
//
-void test_sf_mm_e4m3_e4m3_w4_u8m8_u8m8(vuint8m8_t vs2, vuint8m8_t vs1, size_t tm, size_t tn, size_t tk) {
- return __riscv_sf_mm_e4m3_e4m3_w4_u8m8_u8m8(0, vs2, vs1, tm, tn, tk);
+void test_sf_mm_e4m3_e4m3_w4_f8e4m3m8_f8e4m3m8(vfloat8e4m3m8_t vs2, vfloat8e4m3m8_t vs1, size_t tm, size_t tn, size_t tk) {
+ __riscv_sf_mm_e4m3_e4m3_w4_f8e4m3m8_f8e4m3m8(0, vs2, vs1, tm, tn, tk);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c
index 342af1eca65bf..0c7a18ae5c21d 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c
@@ -1,18 +1,19 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmm32a8f \
-// RUN: -disable-O0-optnone -emit-llvm %s -o - | \
-// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+// RUN: -target-feature +experimental-zvfofp8min -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_e4m3_e5m2_w4_u8m8_u8m8(
+// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_e4m3_e5m2_w4_f8e4m3m8_f8e5m2m8(
// CHECK-RV64-SAME: <vscale x 64 x i8> [[vs2:%.*]], <vscale x 64 x i8> [[vs1:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 0, <vscale x 64 x i8> [[vs2]], <vscale x 64 x i8> [[vs1]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4)
// CHECK-RV64-NEXT: ret void
//
-void test_sf_mm_e4m3_e5m2_w4_u8m8_u8m8(vuint8m8_t vs2, vuint8m8_t vs1, size_t tm, size_t tn, size_t tk) {
- return __riscv_sf_mm_e4m3_e5m2_w4_u8m8_u8m8(0, vs2, vs1, tm, tn, tk);
+void test_sf_mm_e4m3_e5m2_w4_f8e4m3m8_f8e5m2m8(vfloat8e4m3m8_t vs2, vfloat8e5m2m8_t vs1, size_t tm, size_t tn, size_t tk) {
+ __riscv_sf_mm_e4m3_e5m2_w4_f8e4m3m8_f8e5m2m8(0, vs2, vs1, tm, tn, tk);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c
index b8f58fe230b76..56118bad71b1c 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c
@@ -1,18 +1,19 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmm32a8f \
-// RUN: -disable-O0-optnone -emit-llvm %s -o - | \
-// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+// RUN: -target-feature +experimental-zvfofp8min -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_e5m2_e4m3_w4_u8m8_u8m8(
+// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_e5m2_e4m3_w4_f8e5m2m8_f8e4m3m8(
// CHECK-RV64-SAME: <vscale x 64 x i8> [[vs2:%.*]], <vscale x 64 x i8> [[vs1:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 0, <vscale x 64 x i8> [[vs2]], <vscale x 64 x i8> [[vs1]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4)
// CHECK-RV64-NEXT: ret void
//
-void test_sf_mm_e5m2_e4m3_w4_u8m8_u8m8(vuint8m8_t vs2, vuint8m8_t vs1, size_t tm, size_t tn, size_t tk) {
- return __riscv_sf_mm_e5m2_e4m3_w4_u8m8_u8m8(0, vs2, vs1, tm, tn, tk);
+void test_sf_mm_e5m2_e4m3_w4_f8e5m2m8_f8e4m3m8(vfloat8e5m2m8_t vs2, vfloat8e4m3m8_t vs1, size_t tm, size_t tn, size_t tk) {
+ __riscv_sf_mm_e5m2_e4m3_w4_f8e5m2m8_f8e4m3m8(0, vs2, vs1, tm, tn, tk);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c
index 7c2eb3227f004..3785a53818439 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c
@@ -1,18 +1,19 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmm32a8f \
-// RUN: -disable-O0-optnone -emit-llvm %s -o - | \
-// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+// RUN: -target-feature +experimental-zvfofp8min -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_e5m2_e5m2_w4_u8m8_u8m8(
+// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_e5m2_e5m2_w4_f8e5m2m8_f8e5m2m8(
// CHECK-RV64-SAME: <vscale x 64 x i8> [[vs2:%.*]], <vscale x 64 x i8> [[vs1:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 0, <vscale x 64 x i8> [[vs2]], <vscale x 64 x i8> [[vs1]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4)
// CHECK-RV64-NEXT: ret void
//
-void test_sf_mm_e5m2_e5m2_w4_u8m8_u8m8(vuint8m8_t vs2, vuint8m8_t vs1, size_t tm, size_t tn, size_t tk) {
- return __riscv_sf_mm_e5m2_e5m2_w4_u8m8_u8m8(0, vs2, vs1, tm, tn, tk);
+void test_sf_mm_e5m2_e5m2_w4_f8e5m2m8_f8e5m2m8(vfloat8e5m2m8_t vs2, vfloat8e5m2m8_t vs1, size_t tm, size_t tn, size_t tk) {
+ __riscv_sf_mm_e5m2_e5m2_w4_f8e5m2m8_f8e5m2m8(0, vs2, vs1, tm, tn, tk);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c
index 2f6c4dc324d60..cde4bfdad35ea 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c
@@ -1,18 +1,19 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmm32a8f \
-// RUN: -disable-O0-optnone -emit-llvm %s -o - | \
-// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+// RUN: -target-feature +experimental-zvfofp8min -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_e4m3_e4m3_w4_u8m8_u8m8(
+// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_e4m3_e4m3_w4_f8e4m3m8_f8e4m3m8(
// CHECK-RV64-SAME: <vscale x 64 x i8> [[vs2:%.*]], <vscale x 64 x i8> [[vs1:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 0, <vscale x 64 x i8> [[vs2]], <vscale x 64 x i8> [[vs1]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4)
// CHECK-RV64-NEXT: ret void
//
-void test_sf_mm_e4m3_e4m3_w4_u8m8_u8m8(vuint8m8_t vs2, vuint8m8_t vs1, size_t tm, size_t tn, size_t tk) {
- return __riscv_sf_mm_e4m3_e4m3(0, vs2, vs1, tm, tn, tk);
+void test_sf_mm_e4m3_e4m3_w4_f8e4m3m8_f8e4m3m8(vfloat8e4m3m8_t vs2, vfloat8e4m3m8_t vs1, size_t tm, size_t tn, size_t tk) {
+ __riscv_sf_mm_w4(0, vs2, vs1, tm, tn, tk);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c
index 40ae780d6c461..0f822a58621d2 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c
@@ -1,18 +1,19 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmm32a8f \
-// RUN: -disable-O0-optnone -emit-llvm %s -o - | \
-// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+// RUN: -target-feature +experimental-zvfofp8min -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_e4m3_e5m2_w4_u8m8_u8m8(
+// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_e4m3_e5m2_w4_f8e4m3m8_f8e5m2m8(
// CHECK-RV64-SAME: <vscale x 64 x i8> [[vs2:%.*]], <vscale x 64 x i8> [[vs1:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 0, <vscale x 64 x i8> [[vs2]], <vscale x 64 x i8> [[vs1]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4)
// CHECK-RV64-NEXT: ret void
//
-void test_sf_mm_e4m3_e5m2_w4_u8m8_u8m8(vuint8m8_t vs2, vuint8m8_t vs1, size_t tm, size_t tn, size_t tk) {
- return __riscv_sf_mm_e4m3_e5m2(0, vs2, vs1, tm, tn, tk);
+void test_sf_mm_e4m3_e5m2_w4_f8e4m3m8_f8e5m2m8(vfloat8e4m3m8_t vs2, vfloat8e5m2m8_t vs1, size_t tm, size_t tn, size_t tk) {
+ __riscv_sf_mm_w4(0, vs2, vs1, tm, tn, tk);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c
index f4f024cbd0988..0698728b841e7 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c
@@ -1,18 +1,19 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmm32a8f \
-// RUN: -disable-O0-optnone -emit-llvm %s -o - | \
-// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+// RUN: -target-feature +experimental-zvfofp8min -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_e5m2_e4m3_w4_u8m8_u8m8(
+// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_e5m2_e4m3_w4_f8e5m2m8_f8e4m3m8(
// CHECK-RV64-SAME: <vscale x 64 x i8> [[vs2:%.*]], <vscale x 64 x i8> [[vs1:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 0, <vscale x 64 x i8> [[vs2]], <vscale x 64 x i8> [[vs1]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4)
// CHECK-RV64-NEXT: ret void
//
-void test_sf_mm_e5m2_e4m3_w4_u8m8_u8m8(vuint8m8_t vs2, vuint8m8_t vs1, size_t tm, size_t tn, size_t tk) {
- return __riscv_sf_mm_e5m2_e4m3(0, vs2, vs1, tm, tn, tk);
+void test_sf_mm_e5m2_e4m3_w4_f8e5m2m8_f8e4m3m8(vfloat8e5m2m8_t vs2, vfloat8e4m3m8_t vs1, size_t tm, size_t tn, size_t tk) {
+ __riscv_sf_mm_w4(0, vs2, vs1, tm, tn, tk);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c
index 01399d5d81d39..ac685927cccf9 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c
@@ -1,18 +1,19 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +xsfmm32a8f \
-// RUN: -disable-O0-optnone -emit-llvm %s -o - | \
-// RUN: opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+// RUN: -target-feature +experimental-zvfofp8min -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <sifive_vector.h>
-// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_e5m2_e5m2_w4_u8m8_u8m8(
+// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_e5m2_e5m2_w4_f8e5m2m8_f8e5m2m8(
// CHECK-RV64-SAME: <vscale x 64 x i8> [[vs2:%.*]], <vscale x 64 x i8> [[vs1:%.*]], i64 noundef [[TM:%.*]], i64 noundef [[TN:%.*]], i64 noundef [[TK:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 0, <vscale x 64 x i8> [[vs2]], <vscale x 64 x i8> [[vs1]], i64 [[TM]], i64 [[TN]], i64 [[TK]], i64 4)
// CHECK-RV64-NEXT: ret void
//
-void test_sf_mm_e5m2_e5m2_w4_u8m8_u8m8(vuint8m8_t vs2, vuint8m8_t vs1, size_t tm, size_t tn, size_t tk) {
- return __riscv_sf_mm_e5m2_e5m2(0, vs2, vs1, tm, tn, tk);
+void test_sf_mm_e5m2_e5m2_w4_f8e5m2m8_f8e5m2m8(vfloat8e5m2m8_t vs2, vfloat8e5m2m8_t vs1, size_t tm, size_t tn, size_t tk) {
+ __riscv_sf_mm_w4(0, vs2, vs1, tm, tn, tk);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c
index 2371e4ec24fc9..0f3a01c95f886 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c
@@ -15,7 +15,7 @@
// CHECK-RV64-NEXT: ret void
//
void test_sf_mm_f_f_w2_f16m8(vfloat16m8_t vs2, vfloat16m8_t vs1, size_t tm, size_t tn, size_t tk) {
- return __riscv_sf_mm_f_f_w2(0, vs2, vs1, tm, tn, tk);
+ return __riscv_sf_mm_w2(0, vs2, vs1, tm, tn, tk);
}
// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_f_f_w1_f32m8(
@@ -25,7 +25,7 @@ void test_sf_mm_f_f_w2_f16m8(vfloat16m8_t vs2, vfloat16m8_t vs1, size_t tm, size
// CHECK-RV64-NEXT: ret void
//
void test_sf_mm_f_f_w1_f32m8(vfloat32m8_t vs2, vfloat32m8_t vs1, size_t tm, size_t tn, size_t tk) {
- return __riscv_sf_mm_f_f_w1(0, vs2, vs1, tm, tn, tk);
+ return __riscv_sf_mm_w1(0, vs2, vs1, tm, tn, tk);
}
// CHECK-RV64-LABEL: define dso_local void @test_sf_mm_f_f_w1_f64m8(
@@ -35,6 +35,6 @@ void test_sf_mm_f_f_w1_f32m8(vfloat32m8_t vs2, vfloat32m8_t vs1, size_t tm, size
// CHECK-RV64-NEXT: ret void
//
void test_sf_mm_f_f_w1_f64m8(vfloat64m8_t vs2, vfloat64m8_t vs1, size_t tm, size_t tn, size_t tk) {
- return __riscv_sf_mm_f_f_w1(0, vs2, vs1, tm, tn, tk);
+ return __riscv_sf_mm_w1(0, vs2, vs1, tm, tn, tk);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c
index 2d34f7d05060a..68cb007a5f5b8 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c
@@ -13,6 +13,6 @@
// CHECK-RV64-NEXT: ret void
//
void test_sf_mm_s_s_w4_i8m8_i8m8(vint8m8_t vs2, vint8m8_t vs1, size_t tm, size_t tn, size_t tk) {
- return __riscv_sf_mm_s_s(0, vs2, vs1, tm, tn, tk);
+ return __riscv_sf_mm_w4(0, vs2, vs1, tm, tn, tk);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c
index 1f9bc33412871..4ed67810ec03f 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c
@@ -13,6 +13,6 @@
// CHECK-RV64-NEXT: ret void
//
void test_sf_mm_s_u_w4_i8m8_u8m8(vint8m8_t vs2, vuint8m8_t vs1, size_t tm, size_t tn, size_t tk) {
- return __riscv_sf_mm_s_u(0, vs2, vs1, tm, tn, tk);
+ return __riscv_sf_mm_w4(0, vs2, vs1, tm, tn, tk);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c
index 2c6d538821fb2..601d0ede47c28 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c
@@ -13,6 +13,6 @@
// CHECK-RV64-NEXT: ret void
//
void test_sf_mm_u_s_w4_u8m8_i8m8(vuint8m8_t vs2, vint8m8_t vs1, size_t tm, size_t tn, size_t tk) {
- return __riscv_sf_mm_u_s(0, vs2, vs1, tm, tn, tk);
+ return __riscv_sf_mm_w4(0, vs2, vs1, tm, tn, tk);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c
index bb1eaf19b04da..ad497e39f0a6f 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c
@@ -13,6 +13,6 @@
// CHECK-RV64-NEXT: ret void
//
void test_sf_mm_u_u_w4_u8m8_u8m8(vuint8m8_t vs2, vuint8m8_t vs1, size_t tm, size_t tn, size_t tk) {
- return __riscv_sf_mm_u_u(0, vs2, vs1, tm, tn, tk);
+ return __riscv_sf_mm_w4(0, vs2, vs1, tm, tn, tk);
}
diff --git a/clang/test/Sema/sifive-xsfmm.c b/clang/test/Sema/sifive-xsfmm.c
index 7e055dd70c4b1..a53938fdf77aa 100644
--- a/clang/test/Sema/sifive-xsfmm.c
+++ b/clang/test/Sema/sifive-xsfmm.c
@@ -1,23 +1,25 @@
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
// RUN: -target-feature +xsfmmbase -target-feature +xsfmm32a -target-feature +xsfmm32a8f \
// RUN: -target-feature +xsfmm32a16f -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f \
-// RUN: -target-feature +xsfmm32a4f -target-feature +xsfmm32a8i -disable-O0-optnone \
+// RUN: -target-feature +xsfmm32a4f -target-feature +xsfmm32a8i \
+// RUN: -target-feature +experimental-zvfofp8min -disable-O0-optnone \
// RUN: -fsyntax-only %s -verify
// REQUIRES: riscv-registered-target
#include <sifive_vector.h>
-void test(vfloat32m8_t arg0, vuint8m8_t arg1) {
- __riscv_sf_mm_f_f_w1(4, arg0, arg0, 1, 2, 3);
- __riscv_sf_mm_e5m2_e4m3(8, arg1, arg1, 1, 2, 3);
- __riscv_sf_mm_u_u(12, arg1, arg1, 1, 2, 3);
+void test(vfloat32m8_t arg0, vuint8m8_t arg1, vfloat8e5m2m8_t arg2,
+ vfloat8e4m3m8_t arg3) {
+ __riscv_sf_mm_w1(4, arg0, arg0, 1, 2, 3);
+ __riscv_sf_mm_w4(8, arg2, arg3, 1, 2, 3);
+ __riscv_sf_mm_w4(12, arg1, arg1, 1, 2, 3);
__riscv_sf_vtzero_t_e8w1(0, 0, 0);
- __riscv_sf_mm_f_f_w1(5, arg0, arg0, 1, 2, 3); /* expected-error {{argument should be a multiple of 4}} */
- __riscv_sf_mm_e5m2_e4m3(7, arg1, arg1, 1, 2, 3); /* expected-error {{argument should be a multiple of 4}} */
- __riscv_sf_mm_u_u(15, arg1, arg1, 1, 2, 3); /* expected-error {{argument should be a multiple of 4}} */
- __riscv_sf_mm_f_f_w1(16, arg0, arg0, 1, 2, 3); /* expected-error {{argument value 16 is outside the valid range [0, 15]}} */
- __riscv_sf_mm_e5m2_e4m3(20, arg1, arg1, 1, 2, 3); /* expected-error {{argument value 20 is outside the valid range [0, 15]}} */
- __riscv_sf_mm_u_u(24, arg1, arg1, 1, 2, 3); /* expected-error {{argument value 24 is outside the valid range [0, 15]}} */
+ __riscv_sf_mm_w1(5, arg0, arg0, 1, 2, 3); /* expected-error {{argument should be a multiple of 4}} */
+ __riscv_sf_mm_w4(7, arg2, arg3, 1, 2, 3); /* expected-error {{argument should be a multiple of 4}} */
+ __riscv_sf_mm_w4(15, arg1, arg1, 1, 2, 3); /* expected-error {{argument should be a multiple of 4}} */
+ __riscv_sf_mm_w1(16, arg0, arg0, 1, 2, 3); /* expected-error {{argument value 16 is outside the valid range [0, 15]}} */
+ __riscv_sf_mm_w4(20, arg2, arg3, 1, 2, 3); /* expected-error {{argument value 20 is outside the valid range [0, 15]}} */
+ __riscv_sf_mm_w4(24, arg1, arg1, 1, 2, 3); /* expected-error {{argument value 24 is outside the valid range [0, 15]}} */
__riscv_sf_vtzero_t_e8w1(18, 0, 0); /* expected-error {{argument value 18 is outside the valid range [0, 15]}} */
__riscv_sf_vtzero_t_e16w1(3, 0, 0); /* expected-error {{argument should be a multiple of 2}} */
__riscv_sf_vtzero_t_e16w2(3, 0, 0); /* expected-error {{argument should be a multiple of 4}} */
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