[clang] [llvm] [AMDGPU] Add async variants of tensor load/store LDS intrinsics. (PR #200775)

[Shilei Tian via cfe-commits]

shiltian wrote:

> We have absolutely and most definitely moved in that direction, and we intend to keep doing that.

No, we are definitely not. We have pushed back on many intrinsics in the past, and we will continue to do so. Our backend instruction selection can definitely not become a gigantic library provider.

> I can't help but notice the irony that we are discussing this in the context of `@llvm.amdgcn.asyncmark()` which has absolutely no ISA equivalent, and it is managed entirely by the backend. Then we have the new `@llvm.amdgcn.av` intrinsics that add semantics to ordinary load store instructions. With barriers, there will be more such intrinsics.

All of these should eventually move into libraries once the necessary support is available. Until then, we should be very careful about adding library-like intrinsics. Every such intrinsic should be evaluated carefully before being introduced.

https://github.com/llvm/llvm-project/pull/200775