[clang] [llvm] [AMDGPU] Add async variants of tensor load/store LDS intrinsics. (PR #200775)

[Krzysztof Drewniak via cfe-commits]

krzysz00 wrote:

> There actually are two variants. There is an existing non-async variant which hides the counter and the compiler magically takes care of it. 

As far as I'm aware, this is incorrect. TDM has a complex enough aliasing relationship that, as far as I'm aware, there is no attempt to insert tensorcnt waits, nor is there any plan for one.

To be clear, this isn't about the gfx9 LDS DMAs - those have their "sync" variant for legacy / it uses vmcnt reasons.

None of the gfx1250 DMAs have this, and, as I recall previous discussion, they're not *supposed* to have this.

https://github.com/llvm/llvm-project/pull/200775