[clang] [llvm] [AArch64][TableGen] Use target memory locations for ZA and ZT0 intrinsics (PR #154144)

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CarolineConcatto wrote:

Hello,
Just a few notes for the reviewer:
I did not use upgrade, so older LLVM IR that does not use target memory will not benefit from the performance improvement.
 It would also be useful to document the target memory mappings. Should this be documented only in IntrinsicsAArch64.td, or is there somewhere else it should be added as well?

  - ZT0 is mapped to target_mem0
  - ZA is mapped to target_mem1

https://github.com/llvm/llvm-project/pull/154144