[clang] [llvm] [RISCV] Remove experimental XRivosVizip support (PR #200761)
Boyao Wang via cfe-commits
cfe-commits at lists.llvm.org
Mon Jun 1 03:34:48 PDT 2026
https://github.com/BoyaoWang430 updated https://github.com/llvm/llvm-project/pull/200761
>From e06507983c735619f242da6548fcc05c2325ae45 Mon Sep 17 00:00:00 2001
From: wangboyao <wangboyao at bytedance.com>
Date: Mon, 1 Jun 2026 16:57:11 +0800
Subject: [PATCH 1/2] [RISCV] Remove experimental XRivosVizip support
---
.../Driver/print-supported-extensions-riscv.c | 1 -
llvm/docs/RISCVUsage.rst | 3 -
llvm/docs/ReleaseNotes.md | 1 +
.../RISCV/Disassembler/RISCVDisassembler.cpp | 5 -
llvm/lib/Target/RISCV/RISCVFeatures.td | 9 -
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 143 +-
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 1 -
llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td | 116 -
llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 8 -
llvm/test/CodeGen/RISCV/features-info.ll | 1 -
llvm/test/CodeGen/RISCV/pr148084.ll | 2 +-
.../fixed-vectors-shuffle-deinterleave2.ll | 422 ----
.../fixed-vectors-shuffle-int-interleave.ll | 318 ---
.../fixed-vectors-shuffle-zipeven-zipodd.ll | 146 --
.../RISCV/rvv/vector-deinterleave-fixed.ll | 46 -
.../CodeGen/RISCV/rvv/vector-deinterleave.ll | 278 ---
.../RISCV/rvv/vector-interleave-fixed.ll | 682 ------
.../CodeGen/RISCV/rvv/vector-interleave.ll | 1898 -----------------
llvm/test/CodeGen/RISCV/rvv/vl-opt.mir | 104 -
llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll | 6 +-
llvm/test/MC/RISCV/xrivosvizip-invalid.s | 10 -
llvm/test/MC/RISCV/xrivosvizip-valid.s | 59 -
.../TargetParser/RISCVISAInfoTest.cpp | 1 -
23 files changed, 22 insertions(+), 4238 deletions(-)
delete mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
delete mode 100644 llvm/test/MC/RISCV/xrivosvizip-invalid.s
delete mode 100644 llvm/test/MC/RISCV/xrivosvizip-valid.s
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 6185b6a19d5e3..29731e565ecfc 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -265,7 +265,6 @@
// CHECK-NEXT: smpmpmt 0.6 'Smpmpmt' (PMP-based Memory Types Extension)
// CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
// CHECK-NEXT: xqccmt 0.1 'Xqccmt' (Qualcomm 16-bit Table Jump)
-// CHECK-NEXT: xrivosvizip 0.1 'XRivosVizip' (Rivos Vector Register Zips)
// CHECK-NEXT: xsfmclic 0.1 'XSfmclic' (SiFive CLIC Machine-mode CSRs)
// CHECK-NEXT: xsfsclic 0.1 'XSfsclic' (SiFive CLIC Supervisor-mode CSRs)
// CHECK-EMPTY:
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 103c9114c272d..166b5dd6352db 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -550,9 +550,6 @@ The current vendor extensions supported are:
``Xmipslsp``
LLVM implements load/store pair instructions for the `p8700 processor <https://mips.com/products/hardware/p8700/>`__ by MIPS.
-``experimental-XRivosVizip``
- LLVM implements `version 0.1 of the Rivos Vector Register Zips extension specification <https://github.com/rivosinc/rivos-custom-extensions>`__.
-
``XAndesPerf``
LLVM implements `version 5.0.0 of the Andes Performance Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 013b5d0a52067..5153c59fe9c61 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -221,6 +221,7 @@ Makes programs 10x faster by doing Special New Thing.
Reordering Structured Data) extension.
* `-mcpu=sifive-x160` and `-mcpu=sifive-x180` were added.
* Support for the experimental `XRivosVisni` vendor extension has been removed.
+* Support for the experimental `XRivosVizip` vendor extension has been removed.
* Adds experimental assembler support for the 'Zvvmm` (RISC-V Integer Matrix Multiply-Accumulate) extension.
* Adds experimental assembler support for the 'Zvvfmm` (RISC-V Floating-Point Matrix Multiply-Accumulate) extension.
* Adds support for 'Ziccid' (Instruction/Data Coherence and Consistency) extension.
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 8101bec143dda..70d40c2355f4f 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -486,10 +486,6 @@ static constexpr FeatureBitset XCVFeatureGroup = {
RISCV::FeatureVendorXCValu, RISCV::FeatureVendorXCVsimd,
RISCV::FeatureVendorXCVbi};
-static constexpr FeatureBitset XRivosFeatureGroup = {
- RISCV::FeatureVendorXRivosVizip,
-};
-
static constexpr FeatureBitset XqciFeatureGroup = {
RISCV::FeatureVendorXqcia, RISCV::FeatureVendorXqciac,
RISCV::FeatureVendorXqcibi, RISCV::FeatureVendorXqcibm,
@@ -542,7 +538,6 @@ static constexpr FeatureBitset XAIFGroup = {RISCV::FeatureVendorXAIFET};
static constexpr DecoderListEntry DecoderList32[]{
// Vendor Extensions
{DecoderTableXCV32, XCVFeatureGroup, "CORE-V extensions"},
- {DecoderTableXRivos32, XRivosFeatureGroup, "Rivos"},
{DecoderTableXqci32, XqciFeatureGroup, "Qualcomm uC Extensions"},
{DecoderTableXVentana32,
{RISCV::FeatureVendorXVentanaCondOps},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index ff875b745cb0e..93392c1b3d402 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1734,15 +1734,6 @@ def FeatureVendorXqci
FeatureVendorXqcilsm, FeatureVendorXqcisim,
FeatureVendorXqcisls, FeatureVendorXqcisync]>;
-// Rivos Extension(s)
-
-def FeatureVendorXRivosVizip
- : RISCVExperimentalExtension<0, 1, "Rivos Vector Register Zips">;
-def HasVendorXRivosVizip
- : Predicate<"Subtarget->hasVendorXRivosVizip()">,
- AssemblerPredicate<(all_of FeatureVendorXRivosVizip),
- "'XRivosVizip' (Rivos Vector Register Zips)">;
-
// Andes Extension(s)
def FeatureVendorXAndesPerf
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 99a20171ae635..272e9eef86833 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -5223,11 +5223,11 @@ static bool isLegalVTForZvzipOperand(MVT VT, const RISCVSubtarget &Subtarget) {
static bool isInterleaveShuffle(ArrayRef<int> Mask, MVT VT, int &EvenSrc,
int &OddSrc, const RISCVSubtarget &Subtarget) {
// We need to be able to widen elements to the next larger integer type or
- // use the zip2a/vzip instruction at e64.
+ // use the vzip instruction at e64.
if (VT.getScalarSizeInBits() >= Subtarget.getELen()) {
- if (!Subtarget.hasVendorXRivosVizip() && !Subtarget.hasStdExtZvzip())
+ if (!Subtarget.hasStdExtZvzip())
return false;
- if (Subtarget.hasStdExtZvzip() && !isLegalVTForZvzipOperand(VT, Subtarget))
+ if (!isLegalVTForZvzipOperand(VT, Subtarget))
return false;
}
@@ -5682,13 +5682,10 @@ bool RISCVTargetLowering::isSpreadMask(ArrayRef<int> Mask, unsigned Factor,
return true;
}
-static SDValue lowerVZIP(unsigned Opc, SDValue Op0, SDValue Op1,
- const SDLoc &DL, SelectionDAG &DAG,
- const RISCVSubtarget &Subtarget) {
- assert(RISCVISD::RI_VZIPEVEN_VL == Opc || RISCVISD::RI_VZIPODD_VL == Opc ||
- RISCVISD::RI_VZIP2A_VL == Opc || RISCVISD::RI_VZIP2B_VL == Opc ||
- RISCVISD::RI_VUNZIP2A_VL == Opc || RISCVISD::RI_VUNZIP2B_VL == Opc ||
- RISCVISD::VPAIRE_VL == Opc || RISCVISD::VPAIRO_VL == Opc);
+static SDValue lowerZvzipVPAIR(unsigned Opc, SDValue Op0, SDValue Op1,
+ const SDLoc &DL, SelectionDAG &DAG,
+ const RISCVSubtarget &Subtarget) {
+ assert(RISCVISD::VPAIRE_VL == Opc || RISCVISD::VPAIRO_VL == Opc);
assert(Op0.getSimpleValueType() == Op1.getSimpleValueType());
MVT VT = Op0.getSimpleValueType();
@@ -5705,22 +5702,9 @@ static SDValue lowerVZIP(unsigned Opc, SDValue Op0, SDValue Op1,
MVT InnerVT = ContainerVT;
auto [Mask, VL] = getDefaultVLOps(IntVT, InnerVT, DL, DAG, Subtarget);
- if (Op1.isUndef() &&
- ContainerVT.bitsGT(RISCVTargetLowering::getM1VT(ContainerVT)) &&
- (RISCVISD::RI_VUNZIP2A_VL == Opc || RISCVISD::RI_VUNZIP2B_VL == Opc)) {
- InnerVT = ContainerVT.getHalfNumVectorElementsVT();
- VL = DAG.getConstant(VT.getVectorNumElements() / 2, DL,
- Subtarget.getXLenVT());
- Mask = getAllOnesMask(InnerVT, VL, DL, DAG);
- unsigned HighIdx = InnerVT.getVectorElementCount().getKnownMinValue();
- Op1 = DAG.getExtractSubvector(DL, InnerVT, Op0, HighIdx);
- Op0 = DAG.getExtractSubvector(DL, InnerVT, Op0, 0);
- }
SDValue Passthru = DAG.getUNDEF(InnerVT);
SDValue Res = DAG.getNode(Opc, DL, InnerVT, Op0, Op1, Passthru, Mask, VL);
- if (InnerVT.bitsLT(ContainerVT))
- Res = DAG.getInsertSubvector(DL, DAG.getUNDEF(ContainerVT), Res, 0);
if (IntVT.isFixedLengthVector())
Res = convertFromScalableVector(IntVT, Res, DAG, Subtarget);
Res = DAG.getBitcast(VT, Res);
@@ -6479,10 +6463,10 @@ SDValue RISCVTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
}
}
- // If this is a deinterleave(2), try using vunzip{a,b} or vunzip{e,o}. This
- // mostly catches e64 which can't match above.
+ // If this is a deinterleave(2), try using vunzip{e,o}. This mostly catches
+ // e64 which can't match above.
unsigned Index = 0;
- if ((Subtarget.hasVendorXRivosVizip() || Subtarget.hasStdExtZvzip()) &&
+ if (Subtarget.hasStdExtZvzip() &&
ShuffleVectorInst::isDeInterleaveMaskOfFactor(Mask, 2, Index) &&
1 < count_if(Mask, [](int Idx) { return Idx != -1; })) {
bool UsesBothSources =
@@ -6491,7 +6475,7 @@ SDValue RISCVTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
1 < count_if(Mask,
[&Mask](int Idx) { return Idx >= (int)Mask.size(); });
- if (Subtarget.hasStdExtZvzip() && isLegalVTForZvzipOperand(VT, Subtarget)) {
+ if (isLegalVTForZvzipOperand(VT, Subtarget)) {
unsigned Opc = Index == 0 ? RISCVISD::VUNZIPE_VL : RISCVISD::VUNZIPO_VL;
MVT NewVT = VT.getDoubleNumVectorElementsVT();
if (isTypeLegal(NewVT)) {
@@ -6516,45 +6500,6 @@ SDValue RISCVTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
}
}
-
- if (Subtarget.hasVendorXRivosVizip()) {
- unsigned Opc =
- Index == 0 ? RISCVISD::RI_VUNZIP2A_VL : RISCVISD::RI_VUNZIP2B_VL;
- if (V2.isUndef())
- return lowerVZIP(Opc, V1, V2, DL, DAG, Subtarget);
- if (auto VLEN = Subtarget.getRealVLen();
- VLEN && VT.getSizeInBits().getKnownMinValue() % *VLEN == 0)
- return lowerVZIP(Opc, V1, V2, DL, DAG, Subtarget);
- if (SDValue Src = foldConcatVector(V1, V2)) {
- EVT NewVT = VT.getDoubleNumVectorElementsVT();
- Src = DAG.getExtractSubvector(DL, NewVT, Src, 0);
- SDValue Res =
- lowerVZIP(Opc, Src, DAG.getUNDEF(NewVT), DL, DAG, Subtarget);
- return DAG.getExtractSubvector(DL, VT, Res, 0);
- }
- // Deinterleave each source and concatenate them, or concat first, then
- // deinterleave.
- if (UsesBothSources) {
- const unsigned EltSize = VT.getScalarSizeInBits();
- const unsigned MinVLMAX = Subtarget.getRealMinVLen() / EltSize;
- if (NumElts < MinVLMAX) {
- MVT ConcatVT = VT.getDoubleNumVectorElementsVT();
- SDValue Concat =
- DAG.getNode(ISD::CONCAT_VECTORS, DL, ConcatVT, V1, V2);
- SDValue Res = lowerVZIP(Opc, Concat, DAG.getUNDEF(ConcatVT), DL, DAG,
- Subtarget);
- return DAG.getExtractSubvector(DL, VT, Res, 0);
- }
-
- SDValue Lo = lowerVZIP(Opc, V1, DAG.getUNDEF(VT), DL, DAG, Subtarget);
- SDValue Hi = lowerVZIP(Opc, V2, DAG.getUNDEF(VT), DL, DAG, Subtarget);
-
- MVT SubVT = VT.getHalfNumVectorElementsVT();
- return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
- DAG.getExtractSubvector(DL, SubVT, Lo, 0),
- DAG.getExtractSubvector(DL, SubVT, Hi, 0));
- }
- }
}
if (SDValue V =
@@ -6595,15 +6540,9 @@ SDValue RISCVTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
OddV = DAG.getExtractSubvector(DL, HalfVT, OddV, OddSrc % Size);
}
- // Prefer vzip2a or vzip if available.
- // TODO: Extend to matching ri.vzip2b or vzip if EvenSrc and OddSrc allow.
+ // Prefer vzip if available.
if (Subtarget.hasStdExtZvzip() && isLegalVTForZvzipOperand(VT, Subtarget))
return lowerZvzipVZIP(EvenV, OddV, DL, DAG, Subtarget);
- if (Subtarget.hasVendorXRivosVizip()) {
- EvenV = DAG.getInsertSubvector(DL, DAG.getUNDEF(VT), EvenV, 0);
- OddV = DAG.getInsertSubvector(DL, DAG.getUNDEF(VT), OddV, 0);
- return lowerVZIP(RISCVISD::RI_VZIP2A_VL, EvenV, OddV, DL, DAG, Subtarget);
- }
return getWideningInterleave(EvenV, OddV, DL, DAG, Subtarget);
}
@@ -6655,17 +6594,15 @@ SDValue RISCVTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
return convertFromScalableVector(VT, Res, DAG, Subtarget);
}
- if (Subtarget.hasVendorXRivosVizip() || Subtarget.hasStdExtZvzip()) {
+ if (Subtarget.hasStdExtZvzip()) {
bool TryWiden = false;
unsigned Factor;
if (isPairEven(SrcInfo, Mask, Factor)) {
if (Factor == 1) {
SDValue Src1 = SrcInfo[0].first == 0 ? V1 : V2;
SDValue Src2 = SrcInfo[1].first == 0 ? V1 : V2;
- unsigned int Opc = Subtarget.hasStdExtZvzip()
- ? RISCVISD::VPAIRE_VL
- : RISCVISD::RI_VZIPEVEN_VL;
- return lowerVZIP(Opc, Src1, Src2, DL, DAG, Subtarget);
+ return lowerZvzipVPAIR(RISCVISD::VPAIRE_VL, Src1, Src2, DL, DAG,
+ Subtarget);
}
TryWiden = true;
}
@@ -6673,10 +6610,8 @@ SDValue RISCVTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
if (Factor == 1) {
SDValue Src1 = SrcInfo[1].first == 0 ? V1 : V2;
SDValue Src2 = SrcInfo[0].first == 0 ? V1 : V2;
- unsigned int Opc = Subtarget.hasStdExtZvzip()
- ? RISCVISD::VPAIRO_VL
- : RISCVISD::RI_VZIPODD_VL;
- return lowerVZIP(Opc, Src1, Src2, DL, DAG, Subtarget);
+ return lowerZvzipVPAIR(RISCVISD::VPAIRO_VL, Src1, Src2, DL, DAG,
+ Subtarget);
}
TryWiden = true;
}
@@ -13098,38 +13033,6 @@ SDValue RISCVTargetLowering::lowerVECTOR_DEINTERLEAVE(SDValue Op,
}
}
- if (Subtarget.hasVendorXRivosVizip() && Factor == 2) {
- MVT VT = Op->getSimpleValueType(0);
- SDValue V1 = Op->getOperand(0);
- SDValue V2 = Op->getOperand(1);
-
- // For fractional LMUL, check if we can use a higher LMUL
- // instruction to avoid a vslidedown.
- if (SDValue Src = foldConcatVector(V1, V2);
- Src && RISCVTargetLowering::getM1VT(VT).bitsGT(VT)) {
- EVT NewVT = VT.getDoubleNumVectorElementsVT();
- Src = DAG.getExtractSubvector(DL, NewVT, Src, 0);
- // Freeze the source so we can increase its use count.
- Src = DAG.getFreeze(Src);
- SDValue Even = lowerVZIP(RISCVISD::RI_VUNZIP2A_VL, Src,
- DAG.getUNDEF(NewVT), DL, DAG, Subtarget);
- SDValue Odd = lowerVZIP(RISCVISD::RI_VUNZIP2B_VL, Src,
- DAG.getUNDEF(NewVT), DL, DAG, Subtarget);
- Even = DAG.getExtractSubvector(DL, VT, Even, 0);
- Odd = DAG.getExtractSubvector(DL, VT, Odd, 0);
- return DAG.getMergeValues({Even, Odd}, DL);
- }
-
- // Freeze the sources so we can increase their use count.
- V1 = DAG.getFreeze(V1);
- V2 = DAG.getFreeze(V2);
- SDValue Even =
- lowerVZIP(RISCVISD::RI_VUNZIP2A_VL, V1, V2, DL, DAG, Subtarget);
- SDValue Odd =
- lowerVZIP(RISCVISD::RI_VUNZIP2B_VL, V1, V2, DL, DAG, Subtarget);
- return DAG.getMergeValues({Even, Odd}, DL);
- }
-
SmallVector<SDValue, 8> Ops(Op->op_values());
// Concatenate the vectors as one vector to deinterleave
@@ -13374,18 +13277,6 @@ SDValue RISCVTargetLowering::lowerVECTOR_INTERLEAVE(SDValue Op,
}
}
- // Use ri.vzip2{a,b} if available
- // TODO: Figure out the best lowering for the spread variants
- if (Subtarget.hasVendorXRivosVizip() && !Op.getOperand(0).isUndef() &&
- !Op.getOperand(1).isUndef()) {
- // Freeze the sources so we can increase their use count.
- SDValue V1 = DAG.getFreeze(Op->getOperand(0));
- SDValue V2 = DAG.getFreeze(Op->getOperand(1));
- SDValue Lo = lowerVZIP(RISCVISD::RI_VZIP2A_VL, V1, V2, DL, DAG, Subtarget);
- SDValue Hi = lowerVZIP(RISCVISD::RI_VZIP2B_VL, V1, V2, DL, DAG, Subtarget);
- return DAG.getMergeValues({Lo, Hi}, DL);
- }
-
// If the element type is smaller than ELEN, then we can interleave with
// vwaddu.vv and vwmaccu.vx
if (VecVT.getScalarSizeInBits() < Subtarget.getELen()) {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 7160d2d5c4def..7400e3caec69f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2386,7 +2386,6 @@ include "RISCVInstrInfoXqci.td"
include "RISCVInstrInfoXqccmp.td"
include "RISCVInstrInfoXqccmt.td"
include "RISCVInstrInfoXMips.td"
-include "RISCVInstrInfoXRivos.td"
include "RISCVInstrInfoXAndes.td"
include "RISCVInstrInfoXSpacemiT.td"
include "RISCVInstrInfoXAIF.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
deleted file mode 100644
index c6b8fcdf605e6..0000000000000
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
+++ /dev/null
@@ -1,116 +0,0 @@
-//===-- RISCVInstrInfoXRivos.td ----------------------------*- tablegen -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file describes the vendor extensions defined by Rivos Inc.
-//
-//===----------------------------------------------------------------------===//
-
-class CustomRivosVXI<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
- string opcodestr, string argstr>
- : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
- bits<5> imm;
- bits<5> rs1;
- bits<5> vd;
- bit vm = 0;
-
- let Inst{31-26} = funct6;
- let Inst{25} = vm;
- let Inst{24-20} = imm;
- let Inst{19-15} = rs1;
- let Inst{14-12} = opv.Value;
- let Inst{11-7} = vd;
- let Inst{6-0} = OPC_CUSTOM_2.Value;
-
- let Uses = [VL, VTYPE];
- let VMConstraint = false;
- let Constraints = "$vd = $vd_wb";
-
- let UseNamedOperandTable = true;
-}
-
-class CustomRivosXVI<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
- string opcodestr, string argstr>
- : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
- bits<5> imm;
- bits<5> vs2;
- bits<5> rd;
- bit vm = 1;
-
- let Inst{31-26} = funct6;
- let Inst{25} = vm;
- let Inst{24-20} = vs2;
- let Inst{19-15} = imm;
- let Inst{14-12} = opv.Value;
- let Inst{11-7} = rd;
- let Inst{6-0} = OPC_CUSTOM_2.Value;
-
- let Uses = [VL, VTYPE];
- let VMConstraint = false;
-
- let UseNamedOperandTable = true;
-}
-
-//===----------------------------------------------------------------------===//
-// XRivosVizip
-//===----------------------------------------------------------------------===//
-
-
-let Predicates = [HasVendorXRivosVizip], DecoderNamespace = "XRivos",
- Constraints = "@earlyclobber $vd", VS1VS2Constraint = Vrgather,
- Inst{6-0} = OPC_CUSTOM_2.Value, ReadsPastVL = 1,
- ElementsDependOn = EltDepsNone in {
-defm RI_VZIPEVEN_V : VALU_IV_V<"ri.vzipeven", 0b001100>;
-defm RI_VZIPODD_V : VALU_IV_V<"ri.vzipodd", 0b011100>;
-defm RI_VZIP2A_V : VALU_IV_V<"ri.vzip2a", 0b000100>;
-defm RI_VZIP2B_V : VALU_IV_V<"ri.vzip2b", 0b010100>;
-defm RI_VUNZIP2A_V : VALU_IV_V<"ri.vunzip2a", 0b001000>;
-defm RI_VUNZIP2B_V : VALU_IV_V<"ri.vunzip2b", 0b011000>;
-}
-
-// These are modeled after the int binop VL nodes
-let HasMaskOp = true in {
- def ri_vzipeven_vl : RVSDNode<"RI_VZIPEVEN_VL", SDT_RISCVIntBinOp_VL>;
- def ri_vzipodd_vl : RVSDNode<"RI_VZIPODD_VL", SDT_RISCVIntBinOp_VL>;
- def ri_vzip2a_vl : RVSDNode<"RI_VZIP2A_VL", SDT_RISCVIntBinOp_VL>;
- def ri_vzip2b_vl : RVSDNode<"RI_VZIP2B_VL", SDT_RISCVIntBinOp_VL>;
- def ri_vunzip2a_vl : RVSDNode<"RI_VUNZIP2A_VL", SDT_RISCVIntBinOp_VL>;
- def ri_vunzip2b_vl : RVSDNode<"RI_VUNZIP2B_VL", SDT_RISCVIntBinOp_VL>;
-}
-
-multiclass RIVPseudoVALU_VV {
- foreach m = MxList in
- defm "" : VPseudoBinaryV_VV<m, Commutable=0>;
-}
-
-let Predicates = [HasVendorXRivosVizip],
- Constraints = "@earlyclobber $rd, $rd = $passthru" in {
-defm PseudoRI_VZIPEVEN : RIVPseudoVALU_VV;
-defm PseudoRI_VZIPODD : RIVPseudoVALU_VV;
-defm PseudoRI_VZIP2A : RIVPseudoVALU_VV;
-defm PseudoRI_VZIP2B : RIVPseudoVALU_VV;
-defm PseudoRI_VUNZIP2A : RIVPseudoVALU_VV;
-defm PseudoRI_VUNZIP2B : RIVPseudoVALU_VV;
-}
-
-multiclass RIVPatBinaryVL_VV<SDPatternOperator vop, string instruction_name,
- list<VTypeInfo> vtilist = AllIntegerVectors,
- bit isSEWAware = false> {
- foreach vti = vtilist in
- let Predicates = GetVTypePredicates<vti>.Predicates in
- def : VPatBinaryVL_V<vop, instruction_name, "VV",
- vti.Vector, vti.Vector, vti.Vector, vti.Mask,
- vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,
- vti.RegClass, isSEWAware>;
-}
-
-defm : RIVPatBinaryVL_VV<ri_vzipeven_vl, "PseudoRI_VZIPEVEN">;
-defm : RIVPatBinaryVL_VV<ri_vzipodd_vl, "PseudoRI_VZIPODD">;
-defm : RIVPatBinaryVL_VV<ri_vzip2a_vl, "PseudoRI_VZIP2A">;
-defm : RIVPatBinaryVL_VV<ri_vzip2b_vl, "PseudoRI_VZIP2B">;
-defm : RIVPatBinaryVL_VV<ri_vunzip2a_vl, "PseudoRI_VUNZIP2A">;
-defm : RIVPatBinaryVL_VV<ri_vunzip2b_vl, "PseudoRI_VUNZIP2B">;
\ No newline at end of file
diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index 229d4a83b1d89..8e038890d8347 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -592,14 +592,6 @@ static std::optional<unsigned> getOperandLog2EEW(const MachineOperand &MO) {
case RISCV::VABS_V:
case RISCV::VABD_VV:
case RISCV::VABDU_VV:
-
- // XRivosVizip
- case RISCV::RI_VZIPEVEN_VV:
- case RISCV::RI_VZIPODD_VV:
- case RISCV::RI_VZIP2A_VV:
- case RISCV::RI_VZIP2B_VV:
- case RISCV::RI_VUNZIP2A_VV:
- case RISCV::RI_VUNZIP2B_VV:
return MILog2SEW;
// Vector Widening Shift Left Logical (Zvbb)
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index 610152c3a1f22..92a514f932632 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -27,7 +27,6 @@
; CHECK-NEXT: experimental-smpmpmt - 'Smpmpmt' (PMP-based Memory Types Extension).
; CHECK-NEXT: experimental-svukte - 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses).
; CHECK-NEXT: experimental-xqccmt - 'Xqccmt' (Qualcomm 16-bit Table Jump).
-; CHECK-NEXT: experimental-xrivosvizip - 'XRivosVizip' (Rivos Vector Register Zips).
; CHECK-NEXT: experimental-xsfmclic - 'XSfmclic' (SiFive CLIC Machine-mode CSRs).
; CHECK-NEXT: experimental-xsfsclic - 'XSfsclic' (SiFive CLIC Supervisor-mode CSRs).
; CHECK-NEXT: experimental-y - 'Y' ('Base Y' (CHERI)).
diff --git a/llvm/test/CodeGen/RISCV/pr148084.ll b/llvm/test/CodeGen/RISCV/pr148084.ll
index 0c1d29f06b4a8..dcae5d6810eec 100644
--- a/llvm/test/CodeGen/RISCV/pr148084.ll
+++ b/llvm/test/CodeGen/RISCV/pr148084.ll
@@ -276,4 +276,4 @@ get_tx_mask.exit: ; preds = %._crit_edge.i, %bb
ret void
}
-attributes #0 = { noimplicitfloat nounwind sspstrong uwtable vscale_range(2,1024) "frame-pointer"="non-leaf" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+b,+c,+d,+f,+m,+relax,+unaligned-scalar-mem,+unaligned-vector-mem,+v,+zaamo,+zalrsc,+zba,+zbb,+zbs,+zca,+zcd,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-e,-experimental-p,-experimental-smctr,-experimental-ssctr,-experimental-svukte,-xqccmp,-xqcia,-xqciac,-xqcibi,-xqcibm,-xqcicli,-xqcicm,-xqcics,-xqcicsr,-xqciint,-xqciio,-xqcilb,-xqcili,-xqcilia,-xqcilo,-xqcilsm,-xqcisim,-xqcisls,-xqcisync,-experimental-xrivosvizip,-experimental-xsfmclic,-experimental-xsfsclic,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvkgs,-experimental-zvdot4a8i,-h,-q,-sdext,-sdtrig,-sha,-shcounterenw,-shgatpa,-shlcofideleg,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcntrpmf,-smcsrind,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-xandesperf,-xandesvbfhcvt,-xandesvdot,-xandesvpackfph,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscmov,-xmipslsp,-xsfcease,-xsfmm128t,-xsfmm16t,-xsfmm32a16f,-xsfmm32a32f,-xsfmm32a8f,-xsfmm32a8i,-xsfmm32t,-xsfmm64a64f,-xsfmm64t,-xsfmmbase,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zbc,-zbkb,-zbkc,-zbkx,-zcb,-zce,-zcf,-zclsd,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccamoc,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zilsd,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl4096b,-zvl512b,-zvl65536b,-zvl8192b" }
+attributes #0 = { noimplicitfloat nounwind sspstrong uwtable vscale_range(2,1024) "frame-pointer"="non-leaf" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+b,+c,+d,+f,+m,+relax,+unaligned-scalar-mem,+unaligned-vector-mem,+v,+zaamo,+zalrsc,+zba,+zbb,+zbs,+zca,+zcd,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-e,-experimental-p,-experimental-smctr,-experimental-ssctr,-experimental-svukte,-xqccmp,-xqcia,-xqciac,-xqcibi,-xqcibm,-xqcicli,-xqcicm,-xqcics,-xqcicsr,-xqciint,-xqciio,-xqcilb,-xqcili,-xqcilia,-xqcilo,-xqcilsm,-xqcisim,-xqcisls,-xqcisync,-experimental-xsfmclic,-experimental-xsfsclic,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvkgs,-experimental-zvdot4a8i,-h,-q,-sdext,-sdtrig,-sha,-shcounterenw,-shgatpa,-shlcofideleg,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcntrpmf,-smcsrind,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-xandesperf,-xandesvbfhcvt,-xandesvdot,-xandesvpackfph,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscmov,-xmipslsp,-xsfcease,-xsfmm128t,-xsfmm16t,-xsfmm32a16f,-xsfmm32a32f,-xsfmm32a8f,-xsfmm32a8i,-xsfmm32t,-xsfmm64a64f,-xsfmm64t,-xsfmmbase,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zbc,-zbkb,-zbkc,-zbkx,-zcb,-zce,-zcf,-zclsd,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccamoc,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zilsd,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl4096b,-zvl512b,-zvl65536b,-zvl8192b" }
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
index 5005876de9369..e6d9b8e6d93c0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
@@ -5,9 +5,6 @@
; RUN: llc < %s -mtriple=riscv64 -mattr=+f,+zve32f,+zvfh,+zvfbfmin,+zvl256b \
; RUN: -lower-interleaved-accesses=false -verify-machineinstrs \
; RUN: | FileCheck %s --check-prefixes=CHECK,ZVE32F
-; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+zvfbfmin,+zvl256b,+experimental-xrivosvizip \
-; RUN: -lower-interleaved-accesses=false -verify-machineinstrs \
-; RUN: | FileCheck %s --check-prefixes=CHECK,ZIP
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+zvfbfmin,+zvl256b,+experimental-zvzip \
; RUN: -lower-interleaved-accesses=false -verify-machineinstrs \
; RUN: | FileCheck %s --check-prefixes=CHECK,ZVZIP
@@ -63,15 +60,6 @@ define void @vnsrl_0_i16(ptr %in, ptr %out) {
; ZVE32F-NEXT: vse16.v v8, (a1)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_0_i16:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
-; ZIP-NEXT: vle16.v v8, (a0)
-; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZIP-NEXT: vnsrl.wi v8, v8, 0
-; ZIP-NEXT: vse16.v v8, (a1)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_0_i16:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
@@ -106,15 +94,6 @@ define void @vnsrl_16_i16(ptr %in, ptr %out) {
; ZVE32F-NEXT: vse16.v v8, (a1)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_16_i16:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
-; ZIP-NEXT: vle16.v v8, (a0)
-; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZIP-NEXT: vnsrl.wi v8, v8, 16
-; ZIP-NEXT: vse16.v v8, (a1)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_16_i16:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
@@ -149,15 +128,6 @@ define void @vnsrl_0_half(ptr %in, ptr %out) {
; ZVE32F-NEXT: vse16.v v8, (a1)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_0_half:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
-; ZIP-NEXT: vle16.v v8, (a0)
-; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZIP-NEXT: vnsrl.wi v8, v8, 0
-; ZIP-NEXT: vse16.v v8, (a1)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_0_half:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
@@ -192,15 +162,6 @@ define void @vnsrl_0_bfloat(ptr %in, ptr %out) {
; ZVE32F-NEXT: vse16.v v8, (a1)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_0_bfloat:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
-; ZIP-NEXT: vle16.v v8, (a0)
-; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZIP-NEXT: vnsrl.wi v8, v8, 0
-; ZIP-NEXT: vse16.v v8, (a1)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_0_bfloat:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
@@ -235,15 +196,6 @@ define void @vnsrl_16_half(ptr %in, ptr %out) {
; ZVE32F-NEXT: vse16.v v8, (a1)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_16_half:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
-; ZIP-NEXT: vle16.v v8, (a0)
-; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZIP-NEXT: vnsrl.wi v8, v8, 16
-; ZIP-NEXT: vse16.v v8, (a1)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_16_half:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
@@ -278,15 +230,6 @@ define void @vnsrl_16_bfloat(ptr %in, ptr %out) {
; ZVE32F-NEXT: vse16.v v8, (a1)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_16_bfloat:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
-; ZIP-NEXT: vle16.v v8, (a0)
-; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZIP-NEXT: vnsrl.wi v8, v8, 16
-; ZIP-NEXT: vse16.v v8, (a1)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_16_bfloat:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
@@ -322,15 +265,6 @@ define void @vnsrl_0_i32(ptr %in, ptr %out) {
; ZVE32F-NEXT: vse32.v v8, (a1)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_0_i32:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e32, mf2, ta, ma
-; ZIP-NEXT: vle32.v v8, (a0)
-; ZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZIP-NEXT: vnsrl.wi v8, v8, 0
-; ZIP-NEXT: vse32.v v8, (a1)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_0_i32:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e32, mf2, ta, ma
@@ -368,16 +302,6 @@ define void @vnsrl_32_i32(ptr %in, ptr %out) {
; ZVE32F-NEXT: vse32.v v9, (a1)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_32_i32:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e32, mf2, ta, ma
-; ZIP-NEXT: vle32.v v8, (a0)
-; ZIP-NEXT: li a0, 32
-; ZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZIP-NEXT: vnsrl.wx v8, v8, a0
-; ZIP-NEXT: vse32.v v8, (a1)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_32_i32:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e32, mf2, ta, ma
@@ -414,15 +338,6 @@ define void @vnsrl_0_float(ptr %in, ptr %out) {
; ZVE32F-NEXT: vse32.v v8, (a1)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_0_float:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e32, mf2, ta, ma
-; ZIP-NEXT: vle32.v v8, (a0)
-; ZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZIP-NEXT: vnsrl.wi v8, v8, 0
-; ZIP-NEXT: vse32.v v8, (a1)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_0_float:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e32, mf2, ta, ma
@@ -460,16 +375,6 @@ define void @vnsrl_32_float(ptr %in, ptr %out) {
; ZVE32F-NEXT: vse32.v v9, (a1)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_32_float:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e32, mf2, ta, ma
-; ZIP-NEXT: vle32.v v8, (a0)
-; ZIP-NEXT: li a0, 32
-; ZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZIP-NEXT: vnsrl.wx v8, v8, a0
-; ZIP-NEXT: vse32.v v8, (a1)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_32_float:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e32, mf2, ta, ma
@@ -505,15 +410,6 @@ define void @vnsrl_0_i64(ptr %in, ptr %out) {
; ZVE32F-NEXT: sd a0, 8(a1)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_0_i64:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
-; ZIP-NEXT: vle64.v v8, (a0)
-; ZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v10, v8, v9
-; ZIP-NEXT: vse64.v v10, (a1)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_0_i64:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
@@ -549,15 +445,6 @@ define void @vnsrl_64_i64(ptr %in, ptr %out) {
; ZVE32F-NEXT: sd a0, 8(a1)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_64_i64:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
-; ZIP-NEXT: vle64.v v8, (a0)
-; ZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; ZIP-NEXT: ri.vunzip2b.vv v10, v8, v9
-; ZIP-NEXT: vse64.v v10, (a1)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_64_i64:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
@@ -592,15 +479,6 @@ define void @vnsrl_0_double(ptr %in, ptr %out) {
; ZVE32F-NEXT: sd a0, 8(a1)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_0_double:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
-; ZIP-NEXT: vle64.v v8, (a0)
-; ZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v10, v8, v9
-; ZIP-NEXT: vse64.v v10, (a1)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_0_double:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
@@ -636,15 +514,6 @@ define void @vnsrl_64_double(ptr %in, ptr %out) {
; ZVE32F-NEXT: sd a0, 8(a1)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_64_double:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
-; ZIP-NEXT: vle64.v v8, (a0)
-; ZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; ZIP-NEXT: ri.vunzip2b.vv v10, v8, v9
-; ZIP-NEXT: vse64.v v10, (a1)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_64_double:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
@@ -757,15 +626,6 @@ define void @vnsrl_0_i8_single_src(ptr %in, ptr %out) {
; ZVE32F-NEXT: vse8.v v8, (a1)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_0_i8_single_src:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
-; ZIP-NEXT: vle8.v v8, (a0)
-; ZIP-NEXT: vsetivli zero, 4, e8, mf8, ta, ma
-; ZIP-NEXT: vnsrl.wi v8, v8, 0
-; ZIP-NEXT: vse8.v v8, (a1)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_0_i8_single_src:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
@@ -800,15 +660,6 @@ define void @vnsrl_8_i8_single_src(ptr %in, ptr %out) {
; ZVE32F-NEXT: vse8.v v8, (a1)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_8_i8_single_src:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
-; ZIP-NEXT: vle8.v v8, (a0)
-; ZIP-NEXT: vsetivli zero, 4, e8, mf8, ta, ma
-; ZIP-NEXT: vnsrl.wi v8, v8, 8
-; ZIP-NEXT: vse8.v v8, (a1)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_8_i8_single_src:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
@@ -845,16 +696,6 @@ define void @vnsrl_0_i8_single_wideuse(ptr %in, ptr %out) {
; ZVE32F-NEXT: vse8.v v8, (a1)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_0_i8_single_wideuse:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
-; ZIP-NEXT: vle8.v v8, (a0)
-; ZIP-NEXT: vsetivli zero, 4, e8, mf8, ta, ma
-; ZIP-NEXT: vnsrl.wi v8, v8, 0
-; ZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
-; ZIP-NEXT: vse8.v v8, (a1)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_0_i8_single_wideuse:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
@@ -900,18 +741,6 @@ define void @vnsrl_0_i32_single_src_m8(ptr %in, ptr %out) {
; ZVE32F-NEXT: vse32.v v16, (a1)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_0_i32_single_src_m8:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: li a2, 64
-; ZIP-NEXT: vsetvli zero, a2, e32, m8, ta, ma
-; ZIP-NEXT: vle32.v v8, (a0)
-; ZIP-NEXT: li a0, 32
-; ZIP-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; ZIP-NEXT: vnsrl.wi v16, v8, 0
-; ZIP-NEXT: vsetvli zero, a2, e32, m8, ta, ma
-; ZIP-NEXT: vse32.v v16, (a1)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_0_i32_single_src_m8:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: li a2, 64
@@ -957,18 +786,6 @@ define void @vnsrl_0_i32_single_src_m8_2(ptr %in, ptr %out) {
; ZVE32F-NEXT: vse32.v v16, (a1)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_0_i32_single_src_m8_2:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: li a2, 64
-; ZIP-NEXT: vsetvli zero, a2, e32, m8, ta, ma
-; ZIP-NEXT: vle32.v v8, (a0)
-; ZIP-NEXT: li a0, 32
-; ZIP-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; ZIP-NEXT: vnsrl.wi v16, v8, 0
-; ZIP-NEXT: vsetvli zero, a2, e32, m8, ta, ma
-; ZIP-NEXT: vse32.v v16, (a1)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_0_i32_single_src_m8_2:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: li a2, 64
@@ -1014,19 +831,6 @@ define void @vnsrl_0_i8_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZVE32F-NEXT: vse8.v v9, (a2)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_0_i8_two_source:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
-; ZIP-NEXT: vle8.v v8, (a1)
-; ZIP-NEXT: vle8.v v9, (a0)
-; ZIP-NEXT: vsetivli zero, 4, e8, mf8, ta, ma
-; ZIP-NEXT: vnsrl.wi v8, v8, 0
-; ZIP-NEXT: vnsrl.wi v9, v9, 0
-; ZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
-; ZIP-NEXT: vslideup.vi v9, v8, 4
-; ZIP-NEXT: vse8.v v9, (a2)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_0_i8_two_source:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
@@ -1074,19 +878,6 @@ define void @vnsrl_8_8_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZVE32F-NEXT: vse8.v v9, (a2)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_8_8_two_source:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
-; ZIP-NEXT: vle8.v v8, (a1)
-; ZIP-NEXT: vle8.v v9, (a0)
-; ZIP-NEXT: vsetivli zero, 4, e8, mf8, ta, ma
-; ZIP-NEXT: vnsrl.wi v8, v8, 8
-; ZIP-NEXT: vnsrl.wi v9, v9, 8
-; ZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
-; ZIP-NEXT: vslideup.vi v9, v8, 4
-; ZIP-NEXT: vse8.v v9, (a2)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_8_8_two_source:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
@@ -1134,19 +925,6 @@ define void @vnsrl_0_i16_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZVE32F-NEXT: vse16.v v9, (a2)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_0_i16_two_source:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZIP-NEXT: vle16.v v8, (a1)
-; ZIP-NEXT: vle16.v v9, (a0)
-; ZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZIP-NEXT: vnsrl.wi v8, v8, 0
-; ZIP-NEXT: vnsrl.wi v9, v9, 0
-; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZIP-NEXT: vslideup.vi v9, v8, 2
-; ZIP-NEXT: vse16.v v9, (a2)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_0_i16_two_source:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
@@ -1194,19 +972,6 @@ define void @vnsrl_16_i16_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZVE32F-NEXT: vse16.v v9, (a2)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_16_i16_two_source:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZIP-NEXT: vle16.v v8, (a1)
-; ZIP-NEXT: vle16.v v9, (a0)
-; ZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZIP-NEXT: vnsrl.wi v8, v8, 16
-; ZIP-NEXT: vnsrl.wi v9, v9, 16
-; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZIP-NEXT: vslideup.vi v9, v8, 2
-; ZIP-NEXT: vse16.v v9, (a2)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_16_i16_two_source:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
@@ -1254,19 +1019,6 @@ define void @vnsrl_0_half_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZVE32F-NEXT: vse16.v v9, (a2)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_0_half_two_source:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZIP-NEXT: vle16.v v8, (a1)
-; ZIP-NEXT: vle16.v v9, (a0)
-; ZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZIP-NEXT: vnsrl.wi v8, v8, 0
-; ZIP-NEXT: vnsrl.wi v9, v9, 0
-; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZIP-NEXT: vslideup.vi v9, v8, 2
-; ZIP-NEXT: vse16.v v9, (a2)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_0_half_two_source:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
@@ -1314,19 +1066,6 @@ define void @vnsrl_0_bfloat_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZVE32F-NEXT: vse16.v v9, (a2)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_0_bfloat_two_source:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZIP-NEXT: vle16.v v8, (a1)
-; ZIP-NEXT: vle16.v v9, (a0)
-; ZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZIP-NEXT: vnsrl.wi v8, v8, 0
-; ZIP-NEXT: vnsrl.wi v9, v9, 0
-; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZIP-NEXT: vslideup.vi v9, v8, 2
-; ZIP-NEXT: vse16.v v9, (a2)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_0_bfloat_two_source:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
@@ -1374,19 +1113,6 @@ define void @vnsrl_16_half_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZVE32F-NEXT: vse16.v v9, (a2)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_16_half_two_source:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZIP-NEXT: vle16.v v8, (a1)
-; ZIP-NEXT: vle16.v v9, (a0)
-; ZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZIP-NEXT: vnsrl.wi v8, v8, 16
-; ZIP-NEXT: vnsrl.wi v9, v9, 16
-; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZIP-NEXT: vslideup.vi v9, v8, 2
-; ZIP-NEXT: vse16.v v9, (a2)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_16_half_two_source:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
@@ -1434,19 +1160,6 @@ define void @vnsrl_16_bfloat_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZVE32F-NEXT: vse16.v v9, (a2)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_16_bfloat_two_source:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZIP-NEXT: vle16.v v8, (a1)
-; ZIP-NEXT: vle16.v v9, (a0)
-; ZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZIP-NEXT: vnsrl.wi v8, v8, 16
-; ZIP-NEXT: vnsrl.wi v9, v9, 16
-; ZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
-; ZIP-NEXT: vslideup.vi v9, v8, 2
-; ZIP-NEXT: vse16.v v9, (a2)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_16_bfloat_two_source:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
@@ -1486,15 +1199,6 @@ define void @vnsrl_0_i32_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZVE32F-NEXT: vse32.v v8, (a2)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_0_i32_two_source:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZIP-NEXT: vle32.v v8, (a0)
-; ZIP-NEXT: vle32.v v9, (a1)
-; ZIP-NEXT: vslideup.vi v8, v9, 1
-; ZIP-NEXT: vse32.v v8, (a2)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_0_i32_two_source:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
@@ -1532,15 +1236,6 @@ define void @vnsrl_32_i32_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZVE32F-NEXT: vse32.v v9, (a2)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_32_i32_two_source:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZIP-NEXT: vle32.v v8, (a0)
-; ZIP-NEXT: vle32.v v9, (a1)
-; ZIP-NEXT: ri.vzipodd.vv v10, v8, v9
-; ZIP-NEXT: vse32.v v10, (a2)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_32_i32_two_source:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
@@ -1576,15 +1271,6 @@ define void @vnsrl_0_float_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZVE32F-NEXT: vse32.v v8, (a2)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_0_float_two_source:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZIP-NEXT: vle32.v v8, (a0)
-; ZIP-NEXT: vle32.v v9, (a1)
-; ZIP-NEXT: vslideup.vi v8, v9, 1
-; ZIP-NEXT: vse32.v v8, (a2)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_0_float_two_source:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
@@ -1622,15 +1308,6 @@ define void @vnsrl_32_float_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZVE32F-NEXT: vse32.v v9, (a2)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_32_float_two_source:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; ZIP-NEXT: vle32.v v8, (a0)
-; ZIP-NEXT: vle32.v v9, (a1)
-; ZIP-NEXT: ri.vzipodd.vv v10, v8, v9
-; ZIP-NEXT: vse32.v v10, (a2)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_32_float_two_source:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
@@ -1666,15 +1343,6 @@ define void @vnsrl_0_i64_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZVE32F-NEXT: vse32.v v8, (a2)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_0_i64_two_source:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; ZIP-NEXT: vle64.v v8, (a0)
-; ZIP-NEXT: vle64.v v9, (a1)
-; ZIP-NEXT: vslideup.vi v8, v9, 1
-; ZIP-NEXT: vse64.v v8, (a2)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_0_i64_two_source:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
@@ -1712,15 +1380,6 @@ define void @vnsrl_64_i64_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZVE32F-NEXT: vse32.v v9, (a2)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_64_i64_two_source:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; ZIP-NEXT: vle64.v v8, (a0)
-; ZIP-NEXT: vle64.v v9, (a1)
-; ZIP-NEXT: ri.vzipodd.vv v10, v8, v9
-; ZIP-NEXT: vse64.v v10, (a2)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_64_i64_two_source:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
@@ -1755,15 +1414,6 @@ define void @vnsrl_0_double_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZVE32F-NEXT: sd a1, 8(a2)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_0_double_two_source:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; ZIP-NEXT: vle64.v v8, (a0)
-; ZIP-NEXT: vle64.v v9, (a1)
-; ZIP-NEXT: vslideup.vi v8, v9, 1
-; ZIP-NEXT: vse64.v v8, (a2)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_0_double_two_source:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
@@ -1799,15 +1449,6 @@ define void @vnsrl_64_double_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZVE32F-NEXT: sd a1, 8(a2)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: vnsrl_64_double_two_source:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; ZIP-NEXT: vle64.v v8, (a0)
-; ZIP-NEXT: vle64.v v9, (a1)
-; ZIP-NEXT: ri.vzipodd.vv v10, v8, v9
-; ZIP-NEXT: vse64.v v10, (a2)
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vnsrl_64_double_two_source:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
@@ -1836,12 +1477,6 @@ define <2 x i64> @unzip2a_dual_v2i64(<2 x i64> %a, <2 x i64> %b) {
; ZVE32F-NEXT: mv a1, a2
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: unzip2a_dual_v2i64:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v9, 1
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: unzip2a_dual_v2i64:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
@@ -1889,15 +1524,6 @@ define <4 x i64> @unzip2a_dual_v4i64(<4 x i64> %a, <4 x i64> %b) {
; ZVE32F-NEXT: vse32.v v8, (a0)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: unzip2a_dual_v4i64:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v11, v9, v10
-; ZIP-NEXT: ri.vunzip2a.vv v9, v8, v10
-; ZIP-NEXT: vslideup.vi v9, v11, 2
-; ZIP-NEXT: vmv.v.v v8, v9
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: unzip2a_dual_v4i64:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
@@ -2035,16 +1661,6 @@ define <16 x i64> @unzip2a_dual_v16i64(<16 x i64> %a, <16 x i64> %b) {
; ZVE32F-NEXT: .cfi_def_cfa_offset 0
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: unzip2a_dual_v16i64:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 8, e64, m2, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v16, v12, v14
-; ZIP-NEXT: ri.vunzip2a.vv v12, v8, v10
-; ZIP-NEXT: vsetivli zero, 16, e64, m4, ta, ma
-; ZIP-NEXT: vslideup.vi v12, v16, 8
-; ZIP-NEXT: vmv.v.v v8, v12
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: unzip2a_dual_v16i64:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 8, e64, m2, ta, ma
@@ -2096,13 +1712,6 @@ define <4 x i64> @unzip2a_dual_v4i64_exact(<4 x i64> %a, <4 x i64> %b) vscale_ra
; ZVE32F-NEXT: vs1r.v v8, (a0)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: unzip2a_dual_v4i64_exact:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v10, v8, v9
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: unzip2a_dual_v4i64_exact:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
@@ -2151,14 +1760,6 @@ define <4 x i64> @unzip2a_dual_v4i64_exact_nf2(<4 x i64> %a, <4 x i64> %b) vscal
; ZVE32F-NEXT: vse32.v v8, (a0)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: unzip2a_dual_v4i64_exact_nf2:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 8, e64, m1, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v9, 4
-; ZIP-NEXT: ri.vunzip2a.vv v9, v8, v10
-; ZIP-NEXT: vmv.v.v v8, v9
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: unzip2a_dual_v4i64_exact_nf2:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
@@ -2290,13 +1891,6 @@ define <16 x i64> @unzip2a_dual_v16i64_exact(<16 x i64> %a, <16 x i64> %b) vscal
; ZVE32F-NEXT: vs4r.v v8, (a0)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: unzip2a_dual_v16i64_exact:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 16, e64, m4, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v16, v8, v12
-; ZIP-NEXT: vmv.v.v v8, v16
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: unzip2a_dual_v16i64_exact:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 16, e64, m4, ta, ma
@@ -2346,15 +1940,6 @@ define <4 x i64> @unzip2b_dual_v4i64(<4 x i64> %a, <4 x i64> %b) {
; ZVE32F-NEXT: vse32.v v8, (a0)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: unzip2b_dual_v4i64:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
-; ZIP-NEXT: ri.vunzip2b.vv v11, v9, v10
-; ZIP-NEXT: ri.vunzip2b.vv v9, v8, v10
-; ZIP-NEXT: vslideup.vi v9, v11, 2
-; ZIP-NEXT: vmv.v.v v8, v9
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: unzip2b_dual_v4i64:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
@@ -2408,13 +1993,6 @@ define <4 x i64> @unzip2b_dual_v4i64_exact(<4 x i64> %a, <4 x i64> %b) vscale_ra
; ZVE32F-NEXT: vs1r.v v8, (a0)
; ZVE32F-NEXT: ret
;
-; ZIP-LABEL: unzip2b_dual_v4i64_exact:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
-; ZIP-NEXT: ri.vunzip2b.vv v10, v8, v9
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: unzip2b_dual_v4i64_exact:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
index 42ac72b671066..faf795f12cc1c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
@@ -3,8 +3,6 @@
; RUN: llc -mtriple=riscv64 -mattr=+v,+m,+zvl128b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,V128,RV64-V128
; RUN: llc -mtriple=riscv32 -mattr=+v,+m,+zvl512b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,V512,RV32-V512
; RUN: llc -mtriple=riscv64 -mattr=+v,+m,+zvl512b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,V512,RV64-V512
-; RUN: llc -mtriple=riscv32 -mattr=+v,+m,+experimental-xrivosvizip -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZIP,RV32-ZIP
-; RUN: llc -mtriple=riscv64 -mattr=+v,+m,+experimental-xrivosvizip -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZIP,RV64-ZIP
; RUN: llc -mtriple=riscv32 -mattr=+v,+m,+experimental-zvzip -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVZIP,RV32-ZVZIP
; RUN: llc -mtriple=riscv64 -mattr=+v,+m,+experimental-zvzip -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVZIP,RV64-ZVZIP
@@ -20,13 +18,6 @@ define <4 x i8> @interleave_v2i8(<2 x i8> %x, <2 x i8> %y) {
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
;
-; ZIP-LABEL: interleave_v2i8:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; ZIP-NEXT: ri.vzip2a.vv v10, v8, v9
-; ZIP-NEXT: vmv1r.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: interleave_v2i8:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
@@ -47,13 +38,6 @@ define <4 x i16> @interleave_v2i16(<2 x i16> %x, <2 x i16> %y) {
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
;
-; ZIP-LABEL: interleave_v2i16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZIP-NEXT: ri.vzip2a.vv v10, v8, v9
-; ZIP-NEXT: vmv1r.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: interleave_v2i16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
@@ -75,13 +59,6 @@ define <4 x i32> @interleave_v2i32(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
;
-; ZIP-LABEL: interleave_v2i32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZIP-NEXT: ri.vzip2a.vv v10, v9, v8
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: interleave_v2i32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
@@ -119,14 +96,6 @@ define <4 x i64> @interleave_v2i64(<2 x i64> %x, <2 x i64> %y) {
; V512-NEXT: vmerge.vvm v8, v11, v10, v0
; V512-NEXT: ret
;
-; ZIP-LABEL: interleave_v2i64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; ZIP-NEXT: vmv1r.v v12, v9
-; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: interleave_v2i64:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
@@ -158,13 +127,6 @@ define <8 x i8> @interleave_v4i8(<4 x i8> %x, <4 x i8> %y) {
; V512-NEXT: vmv1r.v v8, v10
; V512-NEXT: ret
;
-; ZIP-LABEL: interleave_v4i8:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; ZIP-NEXT: ri.vzip2a.vv v10, v9, v8
-; ZIP-NEXT: vmv1r.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: interleave_v4i8:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
@@ -195,13 +157,6 @@ define <8 x i16> @interleave_v4i16(<4 x i16> %x, <4 x i16> %y) {
; V512-NEXT: vmv1r.v v8, v10
; V512-NEXT: ret
;
-; ZIP-LABEL: interleave_v4i16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZIP-NEXT: ri.vzip2a.vv v10, v8, v9
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: interleave_v4i16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
@@ -232,14 +187,6 @@ define <8 x i32> @interleave_v4i32(<4 x i32> %x, <4 x i32> %y) {
; V512-NEXT: vmv1r.v v8, v10
; V512-NEXT: ret
;
-; ZIP-LABEL: interleave_v4i32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZIP-NEXT: vmv1r.v v12, v9
-; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: interleave_v4i32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
@@ -274,15 +221,6 @@ define <4 x i32> @interleave_v4i32_offset_2(<4 x i32> %x, <4 x i32> %y) {
; V512-NEXT: vmv1r.v v8, v9
; V512-NEXT: ret
;
-; ZIP-LABEL: interleave_v4i32_offset_2:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; ZIP-NEXT: vslidedown.vi v10, v9, 2
-; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZIP-NEXT: ri.vzip2a.vv v9, v8, v10
-; ZIP-NEXT: vmv.v.v v8, v9
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: interleave_v4i32_offset_2:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 2, e32, m1, ta, ma
@@ -323,17 +261,6 @@ define <4 x i32> @interleave_v4i32_offset_1(<4 x i32> %x, <4 x i32> %y) {
; V512-NEXT: vmerge.vvm v8, v9, v10, v0
; V512-NEXT: ret
;
-; ZIP-LABEL: interleave_v4i32_offset_1:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; ZIP-NEXT: vmv.v.i v0, 8
-; ZIP-NEXT: vmv1r.v v10, v9
-; ZIP-NEXT: vslideup.vi v10, v9, 1, v0.t
-; ZIP-NEXT: vmv.v.i v0, 10
-; ZIP-NEXT: ri.vzip2a.vv v11, v8, v9
-; ZIP-NEXT: vmerge.vvm v8, v11, v10, v0
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: interleave_v4i32_offset_1:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, mu
@@ -369,13 +296,6 @@ define <16 x i8> @interleave_v8i8(<8 x i8> %x, <8 x i8> %y) {
; V512-NEXT: vmv1r.v v8, v10
; V512-NEXT: ret
;
-; ZIP-LABEL: interleave_v8i8:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZIP-NEXT: ri.vzip2a.vv v10, v8, v9
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: interleave_v8i8:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
@@ -407,14 +327,6 @@ define <16 x i16> @interleave_v8i16(<8 x i16> %x, <8 x i16> %y) {
; V512-NEXT: vmv1r.v v8, v10
; V512-NEXT: ret
;
-; ZIP-LABEL: interleave_v8i16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZIP-NEXT: vmv1r.v v12, v9
-; ZIP-NEXT: ri.vzip2a.vv v10, v12, v8
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: interleave_v8i16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
@@ -446,14 +358,6 @@ define <16 x i32> @interleave_v8i32(<8 x i32> %x, <8 x i32> %y) {
; V512-NEXT: vmv1r.v v8, v10
; V512-NEXT: ret
;
-; ZIP-LABEL: interleave_v8i32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; ZIP-NEXT: vmv2r.v v16, v10
-; ZIP-NEXT: ri.vzip2a.vv v12, v8, v16
-; ZIP-NEXT: vmv.v.v v8, v12
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: interleave_v8i32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
@@ -485,15 +389,6 @@ define <32 x i8> @interleave_v16i8(<16 x i8> %x, <16 x i8> %y) {
; V512-NEXT: vmv1r.v v8, v10
; V512-NEXT: ret
;
-; ZIP-LABEL: interleave_v16i8:
-; ZIP: # %bb.0:
-; ZIP-NEXT: li a0, 32
-; ZIP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; ZIP-NEXT: vmv1r.v v12, v9
-; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: interleave_v16i8:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 16, e8, m1, ta, ma
@@ -525,15 +420,6 @@ define <32 x i16> @interleave_v16i16(<16 x i16> %x, <16 x i16> %y) {
; V512-NEXT: vmv1r.v v8, v10
; V512-NEXT: ret
;
-; ZIP-LABEL: interleave_v16i16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: li a0, 32
-; ZIP-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZIP-NEXT: vmv2r.v v16, v10
-; ZIP-NEXT: ri.vzip2a.vv v12, v8, v16
-; ZIP-NEXT: vmv.v.v v8, v12
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: interleave_v16i16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
@@ -566,15 +452,6 @@ define <32 x i32> @interleave_v16i32(<16 x i32> %x, <16 x i32> %y) {
; V512-NEXT: vwmaccu.vx v8, a0, v10
; V512-NEXT: ret
;
-; ZIP-LABEL: interleave_v16i32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: li a0, 32
-; ZIP-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZIP-NEXT: vmv4r.v v24, v12
-; ZIP-NEXT: ri.vzip2a.vv v16, v8, v24
-; ZIP-NEXT: vmv.v.v v8, v16
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: interleave_v16i32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 16, e32, m4, ta, ma
@@ -610,15 +487,6 @@ define <64 x i8> @interleave_v32i8(<32 x i8> %x, <32 x i8> %y) {
; V512-NEXT: vmv1r.v v8, v10
; V512-NEXT: ret
;
-; ZIP-LABEL: interleave_v32i8:
-; ZIP: # %bb.0:
-; ZIP-NEXT: li a0, 64
-; ZIP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; ZIP-NEXT: vmv2r.v v16, v10
-; ZIP-NEXT: ri.vzip2a.vv v12, v8, v16
-; ZIP-NEXT: vmv.v.v v8, v12
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: interleave_v32i8:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: li a0, 32
@@ -654,15 +522,6 @@ define <64 x i16> @interleave_v32i16(<32 x i16> %x, <32 x i16> %y) {
; V512-NEXT: vwmaccu.vx v8, a0, v10
; V512-NEXT: ret
;
-; ZIP-LABEL: interleave_v32i16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: li a0, 64
-; ZIP-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZIP-NEXT: vmv4r.v v24, v12
-; ZIP-NEXT: ri.vzip2a.vv v16, v8, v24
-; ZIP-NEXT: vmv.v.v v8, v16
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: interleave_v32i16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: li a0, 32
@@ -728,91 +587,6 @@ define <64 x i32> @interleave_v32i32(<32 x i32> %x, <32 x i32> %y) {
; V512-NEXT: vwmaccu.vx v8, a0, v12
; V512-NEXT: ret
;
-; ZIP-LABEL: interleave_v32i32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -16
-; ZIP-NEXT: .cfi_def_cfa_offset 16
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 40
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 5
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 16
-; ZIP-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; ZIP-NEXT: addi a0, sp, 16
-; ZIP-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; ZIP-NEXT: li a0, 32
-; ZIP-NEXT: vsetivli zero, 16, e32, m8, ta, ma
-; ZIP-NEXT: vslidedown.vi v16, v8, 16
-; ZIP-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZIP-NEXT: ri.vzip2a.vv v8, v16, v0
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a1, a1, 3
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 16
-; ZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a1, a1, 5
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 16
-; ZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; ZIP-NEXT: vsetivli zero, 16, e32, m8, ta, ma
-; ZIP-NEXT: vslidedown.vi v16, v16, 16
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: li a2, 24
-; ZIP-NEXT: mul a1, a1, a2
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 16
-; ZIP-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; ZIP-NEXT: lui a1, 699051
-; ZIP-NEXT: addi a1, a1, -1366
-; ZIP-NEXT: vmv.s.x v0, a1
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a1, a1, 4
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 16
-; ZIP-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: li a2, 24
-; ZIP-NEXT: mul a1, a1, a2
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 16
-; ZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a1, a1, 4
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 16
-; ZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a1, a1, 3
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 16
-; ZIP-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
-; ZIP-NEXT: vsetvli zero, a0, e32, m8, ta, mu
-; ZIP-NEXT: ri.vzip2a.vv v8, v24, v16, v0.t
-; ZIP-NEXT: vmv.v.v v24, v8
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 5
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 16
-; ZIP-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZIP-NEXT: addi a0, sp, 16
-; ZIP-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZIP-NEXT: ri.vzip2a.vv v0, v8, v16
-; ZIP-NEXT: vmv.v.v v8, v0
-; ZIP-NEXT: vmv.v.v v16, v24
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 40
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: add sp, sp, a0
-; ZIP-NEXT: .cfi_def_cfa sp, 16
-; ZIP-NEXT: addi sp, sp, 16
-; ZIP-NEXT: .cfi_def_cfa_offset 0
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: interleave_v32i32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -16
@@ -877,15 +651,6 @@ define <4 x i8> @unary_interleave_v4i8(<4 x i8> %x) {
; V512-NEXT: vmv1r.v v8, v9
; V512-NEXT: ret
;
-; ZIP-LABEL: unary_interleave_v4i8:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; ZIP-NEXT: vslidedown.vi v10, v8, 2
-; ZIP-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; ZIP-NEXT: ri.vzip2a.vv v9, v8, v10
-; ZIP-NEXT: vmv1r.v v8, v9
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: unary_interleave_v4i8:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
@@ -922,17 +687,6 @@ define <4 x i8> @unary_interleave_v4i8_invalid(<4 x i8> %x) {
; V512-NEXT: vmv1r.v v8, v9
; V512-NEXT: ret
;
-; ZIP-LABEL: unary_interleave_v4i8_invalid:
-; ZIP: # %bb.0:
-; ZIP-NEXT: lui a0, 16
-; ZIP-NEXT: addi a0, a0, 768
-; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZIP-NEXT: vmv.s.x v10, a0
-; ZIP-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
-; ZIP-NEXT: vrgather.vv v9, v8, v10
-; ZIP-NEXT: vmv1r.v v8, v9
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: unary_interleave_v4i8_invalid:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: lui a0, 16
@@ -969,15 +723,6 @@ define <4 x i16> @unary_interleave_v4i16(<4 x i16> %x) {
; V512-NEXT: vmv1r.v v8, v9
; V512-NEXT: ret
;
-; ZIP-LABEL: unary_interleave_v4i16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; ZIP-NEXT: vslidedown.vi v10, v8, 2
-; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZIP-NEXT: ri.vzip2a.vv v9, v8, v10
-; ZIP-NEXT: vmv1r.v v8, v9
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: unary_interleave_v4i16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
@@ -1012,15 +757,6 @@ define <4 x i32> @unary_interleave_v4i32(<4 x i32> %x) {
; V512-NEXT: vmv1r.v v8, v9
; V512-NEXT: ret
;
-; ZIP-LABEL: unary_interleave_v4i32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; ZIP-NEXT: vslidedown.vi v10, v8, 2
-; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZIP-NEXT: ri.vzip2a.vv v9, v8, v10
-; ZIP-NEXT: vmv.v.v v8, v9
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: unary_interleave_v4i32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 2, e32, m1, ta, ma
@@ -1072,15 +808,6 @@ define <4 x i64> @unary_interleave_v4i64(<4 x i64> %x) {
; RV64-V512-NEXT: vmv.v.v v8, v9
; RV64-V512-NEXT: ret
;
-; ZIP-LABEL: unary_interleave_v4i64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 2, e64, m2, ta, ma
-; ZIP-NEXT: vslidedown.vi v12, v8, 2
-; ZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: unary_interleave_v4i64:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 2, e64, m2, ta, ma
@@ -1115,15 +842,6 @@ define <8 x i8> @unary_interleave_v8i8(<8 x i8> %x) {
; V512-NEXT: vmv1r.v v8, v9
; V512-NEXT: ret
;
-; ZIP-LABEL: unary_interleave_v8i8:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; ZIP-NEXT: vslidedown.vi v10, v8, 4
-; ZIP-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; ZIP-NEXT: ri.vzip2a.vv v9, v8, v10
-; ZIP-NEXT: vmv1r.v v8, v9
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: unary_interleave_v8i8:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
@@ -1158,15 +876,6 @@ define <8 x i16> @unary_interleave_v8i16(<8 x i16> %x) {
; V512-NEXT: vmv1r.v v8, v9
; V512-NEXT: ret
;
-; ZIP-LABEL: unary_interleave_v8i16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; ZIP-NEXT: vslidedown.vi v10, v8, 4
-; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZIP-NEXT: ri.vzip2a.vv v9, v10, v8
-; ZIP-NEXT: vmv.v.v v8, v9
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: unary_interleave_v8i16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 4, e16, m1, ta, ma
@@ -1201,15 +910,6 @@ define <8 x i32> @unary_interleave_v8i32(<8 x i32> %x) {
; V512-NEXT: vmv1r.v v8, v9
; V512-NEXT: ret
;
-; ZIP-LABEL: unary_interleave_v8i32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 4, e32, m2, ta, ma
-; ZIP-NEXT: vslidedown.vi v12, v8, 4
-; ZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: unary_interleave_v8i32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 4, e32, m2, ta, ma
@@ -1233,14 +933,6 @@ define <4 x i8> @unary_interleave_10uu_v4i8(<4 x i8> %x) {
; CHECK-NEXT: vor.vv v8, v8, v9
; CHECK-NEXT: ret
;
-; ZIP-LABEL: unary_interleave_10uu_v4i8:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZIP-NEXT: vsrl.vi v9, v8, 8
-; ZIP-NEXT: vsll.vi v8, v8, 8
-; ZIP-NEXT: vor.vv v8, v8, v9
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: unary_interleave_10uu_v4i8:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
@@ -1272,14 +964,6 @@ define <16 x i16> @interleave_slp(<8 x i16> %v0, <8 x i16> %v1) {
; V512-NEXT: vmv1r.v v8, v10
; V512-NEXT: ret
;
-; ZIP-LABEL: interleave_slp:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZIP-NEXT: vmv1r.v v12, v9
-; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: interleave_slp:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
@@ -1296,8 +980,6 @@ entry:
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; RV32-V128: {{.*}}
-; RV32-ZIP: {{.*}}
; RV32-ZVZIP: {{.*}}
; RV64-V128: {{.*}}
-; RV64-ZIP: {{.*}}
; RV64-ZVZIP: {{.*}}
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll
index 150665d24e671..bba3f0269826f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll
@@ -1,8 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin,+experimental-xrivosvizip -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZIP,ZIP-RV32
-; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin,+experimental-xrivosvizip -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZIP,ZIP-RV64
; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin,+experimental-zvzip -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVZIP,ZVZIP-RV32
; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin,+experimental-zvzip -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVZIP,ZVZIP-RV64
@@ -14,13 +12,6 @@ define <4 x i32> @zipeven_v4i32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-NEXT: vslideup.vi v8, v9, 1, v0.t
; CHECK-NEXT: ret
;
-; ZIP-LABEL: zipeven_v4i32:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZIP-NEXT: ri.vzipeven.vv v10, v8, v9
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: zipeven_v4i32:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
@@ -41,13 +32,6 @@ define <4 x i32> @zipeven_v4i32_swapped(<4 x i32> %a, <4 x i32> %b) {
; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret
;
-; ZIP-LABEL: zipeven_v4i32_swapped:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZIP-NEXT: ri.vzipeven.vv v10, v9, v8
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: zipeven_v4i32_swapped:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
@@ -68,13 +52,6 @@ define <4 x i64> @zipeven_v4i64(<4 x i64> %a, <4 x i64> %b) {
; CHECK-NEXT: vslideup.vi v8, v10, 1, v0.t
; CHECK-NEXT: ret
;
-; ZIP-LABEL: zipeven_v4i64:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; ZIP-NEXT: ri.vzipeven.vv v12, v8, v10
-; ZIP-NEXT: vmv.v.v v8, v12
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: zipeven_v4i64:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
@@ -94,13 +71,6 @@ define <4 x half> @zipeven_v4f16(<4 x half> %a, <4 x half> %b) {
; CHECK-NEXT: vslideup.vi v8, v9, 1, v0.t
; CHECK-NEXT: ret
;
-; ZIP-LABEL: zipeven_v4f16:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZIP-NEXT: ri.vzipeven.vv v10, v8, v9
-; ZIP-NEXT: vmv1r.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: zipeven_v4f16:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
@@ -120,13 +90,6 @@ define <4 x bfloat> @zipeven_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) {
; CHECK-NEXT: vslideup.vi v8, v9, 1, v0.t
; CHECK-NEXT: ret
;
-; ZIP-LABEL: zipeven_v4bf16:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZIP-NEXT: ri.vzipeven.vv v10, v8, v9
-; ZIP-NEXT: vmv1r.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: zipeven_v4bf16:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
@@ -146,13 +109,6 @@ define <4 x float> @zipeven_v4f32(<4 x float> %a, <4 x float> %b) {
; CHECK-NEXT: vslideup.vi v8, v9, 1, v0.t
; CHECK-NEXT: ret
;
-; ZIP-LABEL: zipeven_v4f32:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZIP-NEXT: ri.vzipeven.vv v10, v8, v9
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: zipeven_v4f32:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
@@ -173,13 +129,6 @@ define <4 x double> @zipeven_v4f64(<4 x double> %a, <4 x double> %b) {
; CHECK-NEXT: vslideup.vi v8, v10, 1, v0.t
; CHECK-NEXT: ret
;
-; ZIP-LABEL: zipeven_v4f64:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; ZIP-NEXT: ri.vzipeven.vv v12, v8, v10
-; ZIP-NEXT: vmv.v.v v8, v12
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: zipeven_v4f64:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
@@ -201,13 +150,6 @@ define <4 x i32> @zipodd_v4i32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret
;
-; ZIP-LABEL: zipodd_v4i32:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZIP-NEXT: ri.vzipodd.vv v10, v8, v9
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: zipodd_v4i32:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
@@ -227,13 +169,6 @@ define <4 x i32> @zipodd_v4i32_swapped(<4 x i32> %a, <4 x i32> %b) {
; CHECK-NEXT: vslidedown.vi v8, v9, 1, v0.t
; CHECK-NEXT: ret
;
-; ZIP-LABEL: zipodd_v4i32_swapped:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZIP-NEXT: ri.vzipodd.vv v10, v9, v8
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: zipodd_v4i32_swapped:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
@@ -253,10 +188,6 @@ define <4 x i32> @zipeven_v4i32_single(<4 x i32> %a) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ret
;
-; ZIP-LABEL: zipeven_v4i32_single:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: zipeven_v4i32_single:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: ret
@@ -275,12 +206,6 @@ define <4 x i32> @zipodd_v4i32_single(<4 x i32> %a) {
; CHECK-NEXT: vslidedown.vi v8, v8, 1
; CHECK-NEXT: ret
;
-; ZIP-LABEL: zipodd_v4i32_single:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZIP-NEXT: vslidedown.vi v8, v8, 1
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: zipodd_v4i32_single:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
@@ -299,13 +224,6 @@ define <4 x i32> @zipodd_v4i32_both(<4 x i32> %a) {
; CHECK-NEXT: vslidedown.vi v8, v8, 1, v0.t
; CHECK-NEXT: ret
;
-; ZIP-LABEL: zipodd_v4i32_both:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZIP-NEXT: ri.vzipodd.vv v9, v8, v8
-; ZIP-NEXT: vmv.v.v v8, v9
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: zipodd_v4i32_both:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
@@ -327,13 +245,6 @@ define <4 x i32> @zipeven_v4i32_both(<4 x i32> %a) {
; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret
;
-; ZIP-LABEL: zipeven_v4i32_both:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZIP-NEXT: ri.vzipeven.vv v9, v8, v8
-; ZIP-NEXT: vmv.v.v v8, v9
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: zipeven_v4i32_both:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
@@ -352,12 +263,6 @@ define <4 x i32> @zipeven_v4i32_partial(<4 x i32> %a, <4 x i32> %b) {
; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: ret
;
-; ZIP-LABEL: zipeven_v4i32_partial:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 2, e32, m1, tu, ma
-; ZIP-NEXT: vslideup.vi v8, v9, 1
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: zipeven_v4i32_partial:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 2, e32, m1, tu, ma
@@ -377,13 +282,6 @@ define <4 x i32> @zipodd_v4i32_partial(<4 x i32> %a, <4 x i32> %b) {
; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret
;
-; ZIP-LABEL: zipodd_v4i32_partial:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZIP-NEXT: ri.vzipodd.vv v10, v8, v9
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: zipodd_v4i32_partial:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
@@ -404,13 +302,6 @@ define <8 x i32> @zipeven_v8i32(<8 x i32> %v1, <8 x i32> %v2) {
; CHECK-NEXT: vslideup.vi v8, v10, 1, v0.t
; CHECK-NEXT: ret
;
-; ZIP-LABEL: zipeven_v8i32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZIP-NEXT: ri.vzipeven.vv v12, v8, v10
-; ZIP-NEXT: vmv.v.v v8, v12
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: zipeven_v8i32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
@@ -431,13 +322,6 @@ define <8 x i32> @zipodd_v8i32(<8 x i32> %v1, <8 x i32> %v2) {
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
;
-; ZIP-LABEL: zipodd_v8i32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZIP-NEXT: ri.vzipodd.vv v12, v8, v10
-; ZIP-NEXT: vmv.v.v v8, v12
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: zipodd_v8i32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
@@ -458,13 +342,6 @@ define <16 x i64> @zipeven_v16i64(<16 x i64> %v1, <16 x i64> %v2) {
; CHECK-NEXT: vslideup.vi v8, v16, 1, v0.t
; CHECK-NEXT: ret
;
-; ZIP-LABEL: zipeven_v16i64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; ZIP-NEXT: ri.vzipeven.vv v24, v8, v16
-; ZIP-NEXT: vmv.v.v v8, v24
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: zipeven_v16i64:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 16, e64, m8, ta, ma
@@ -486,13 +363,6 @@ define <16 x i64> @zipodd_v16i64(<16 x i64> %v1, <16 x i64> %v2) {
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
;
-; ZIP-LABEL: zipodd_v16i64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; ZIP-NEXT: ri.vzipodd.vv v24, v8, v16
-; ZIP-NEXT: vmv.v.v v8, v24
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: zipodd_v16i64:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 16, e64, m8, ta, ma
@@ -512,13 +382,6 @@ define <8 x i32> @zipeven_v8i32_as_v4i64(<8 x i32> %v1, <8 x i32> %v2) {
; CHECK-NEXT: vslideup.vi v8, v10, 2, v0.t
; CHECK-NEXT: ret
;
-; ZIP-LABEL: zipeven_v8i32_as_v4i64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; ZIP-NEXT: ri.vzipeven.vv v12, v8, v10
-; ZIP-NEXT: vmv.v.v v8, v12
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: zipeven_v8i32_as_v4i64:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
@@ -539,13 +402,6 @@ define <8 x i32> @zipodd_v8i32_as_v4i64(<8 x i32> %v1, <8 x i32> %v2) {
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
;
-; ZIP-LABEL: zipodd_v8i32_as_v4i64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; ZIP-NEXT: ri.vzipodd.vv v12, v8, v10
-; ZIP-NEXT: vmv.v.v v8, v12
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: zipodd_v8i32_as_v4i64:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
@@ -559,7 +415,5 @@ define <8 x i32> @zipodd_v8i32_as_v4i64(<8 x i32> %v1, <8 x i32> %v2) {
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; RV32: {{.*}}
; RV64: {{.*}}
-; ZIP-RV32: {{.*}}
-; ZIP-RV64: {{.*}}
; ZVZIP-RV32: {{.*}}
; ZVZIP-RV64: {{.*}}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
index 77d06e53e172a..142e2361f6736 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+m,+zvfh,+zvfbfmin | FileCheck %s --check-prefixes=CHECK,V,RV32
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+m,+zvfh,+zvfbfmin | FileCheck %s --check-prefixes=CHECK,V,RV64
-; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+m,+zvfh,+zvfbfmin,+experimental-xrivosvizip | FileCheck %s --check-prefixes=CHECK,ZIP
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+m,+zvfh,+zvfbfmin,+experimental-zvzip | FileCheck %s --check-prefixes=CHECK,ZVZIP
; Integers
@@ -84,15 +83,6 @@ define {<2 x i64>, <2 x i64>} @vector_deinterleave_v2i64_v4i64(<4 x i64> %vec) {
; V-NEXT: vslideup.vi v8, v10, 1
; V-NEXT: ret
;
-; ZIP-LABEL: vector_deinterleave_v2i64_v4i64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v10, v8, v9
-; ZIP-NEXT: ri.vunzip2b.vv v11, v8, v9
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: vmv.v.v v9, v11
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_deinterleave_v2i64_v4i64:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
@@ -136,15 +126,6 @@ define {<4 x i64>, <4 x i64>} @vector_deinterleave_v4i64_v8i64(<8 x i64> %vec) {
; V-NEXT: vmv2r.v v8, v12
; V-NEXT: ret
;
-; ZIP-LABEL: vector_deinterleave_v4i64_v8i64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v12, v8, v10
-; ZIP-NEXT: ri.vunzip2b.vv v14, v8, v10
-; ZIP-NEXT: vmv.v.v v8, v12
-; ZIP-NEXT: vmv.v.v v10, v14
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_deinterleave_v4i64_v8i64:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
@@ -183,15 +164,6 @@ define {<8 x i64>, <8 x i64>} @vector_deinterleave_v8i64_v16i64(<16 x i64> %vec)
; V-NEXT: vmv.v.v v8, v16
; V-NEXT: ret
;
-; ZIP-LABEL: vector_deinterleave_v8i64_v16i64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v16, v8, v12
-; ZIP-NEXT: ri.vunzip2b.vv v20, v8, v12
-; ZIP-NEXT: vmv.v.v v8, v16
-; ZIP-NEXT: vmv.v.v v12, v20
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_deinterleave_v8i64_v16i64:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 8, e64, m4, ta, ma
@@ -532,15 +504,6 @@ define {<2 x double>, <2 x double>} @vector_deinterleave_v2f64_v4f64(<4 x double
; V-NEXT: vslideup.vi v8, v10, 1
; V-NEXT: ret
;
-; ZIP-LABEL: vector_deinterleave_v2f64_v4f64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v10, v8, v9
-; ZIP-NEXT: ri.vunzip2b.vv v12, v8, v9
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: vmv.v.v v9, v12
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_deinterleave_v2f64_v4f64:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
@@ -584,15 +547,6 @@ define {<4 x double>, <4 x double>} @vector_deinterleave_v4f64_v8f64(<8 x double
; V-NEXT: vmv2r.v v8, v12
; V-NEXT: ret
;
-; ZIP-LABEL: vector_deinterleave_v4f64_v8f64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v12, v8, v10
-; ZIP-NEXT: ri.vunzip2b.vv v16, v8, v10
-; ZIP-NEXT: vmv.v.v v8, v12
-; ZIP-NEXT: vmv.v.v v10, v16
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_deinterleave_v4f64_v8f64:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
index 0e691600fd238..9ba25e330a084 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+zvfhmin,+zvfbfmin | FileCheck %s --check-prefixes=CHECK,V
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin | FileCheck %s --check-prefixes=CHECK,V
-; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin,+experimental-xrivosvizip | FileCheck %s --check-prefixes=CHECK,ZIP
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin,+experimental-zvzip | FileCheck %s --check-prefixes=CHECK,ZVZIP
; Integers
@@ -24,23 +23,6 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>} @vector_deinterleave_nxv16i1_nxv
; V-NEXT: vmsne.vi v8, v14, 0
; V-NEXT: ret
;
-; ZIP-LABEL: vector_deinterleave_nxv16i1_nxv32i1:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; ZIP-NEXT: vmv.v.i v8, 0
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: vmerge.vim v10, v8, 1, v0
-; ZIP-NEXT: srli a0, a0, 2
-; ZIP-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; ZIP-NEXT: vslidedown.vx v0, v0, a0
-; ZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; ZIP-NEXT: vmerge.vim v8, v8, 1, v0
-; ZIP-NEXT: ri.vunzip2a.vv v12, v10, v8
-; ZIP-NEXT: ri.vunzip2b.vv v14, v10, v8
-; ZIP-NEXT: vmsne.vi v0, v12, 0
-; ZIP-NEXT: vmsne.vi v8, v14, 0
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_deinterleave_nxv16i1_nxv32i1:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
@@ -71,15 +53,6 @@ define {<vscale x 16 x i8>, <vscale x 16 x i8>} @vector_deinterleave_nxv16i8_nxv
; V-NEXT: vmv.v.v v10, v14
; V-NEXT: ret
;
-; ZIP-LABEL: vector_deinterleave_nxv16i8_nxv32i8:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v12, v8, v10
-; ZIP-NEXT: ri.vunzip2b.vv v14, v8, v10
-; ZIP-NEXT: vmv.v.v v8, v12
-; ZIP-NEXT: vmv.v.v v10, v14
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_deinterleave_nxv16i8_nxv32i8:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
@@ -102,15 +75,6 @@ define {<vscale x 8 x i16>, <vscale x 8 x i16>} @vector_deinterleave_nxv8i16_nxv
; V-NEXT: vmv.v.v v10, v14
; V-NEXT: ret
;
-; ZIP-LABEL: vector_deinterleave_nxv8i16_nxv16i16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v12, v8, v10
-; ZIP-NEXT: ri.vunzip2b.vv v14, v8, v10
-; ZIP-NEXT: vmv.v.v v8, v12
-; ZIP-NEXT: vmv.v.v v10, v14
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_deinterleave_nxv8i16_nxv16i16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
@@ -134,15 +98,6 @@ define {<vscale x 4 x i32>, <vscale x 4 x i32>} @vector_deinterleave_nxv4i32_nxv
; V-NEXT: vmv.v.v v10, v12
; V-NEXT: ret
;
-; ZIP-LABEL: vector_deinterleave_nxv4i32_nxvv8i32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v12, v8, v10
-; ZIP-NEXT: ri.vunzip2b.vv v14, v8, v10
-; ZIP-NEXT: vmv.v.v v8, v12
-; ZIP-NEXT: vmv.v.v v10, v14
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_deinterleave_nxv4i32_nxvv8i32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e32, m2, ta, ma
@@ -170,15 +125,6 @@ define {<vscale x 2 x i64>, <vscale x 2 x i64>} @vector_deinterleave_nxv2i64_nxv
; V-NEXT: vmv2r.v v10, v16
; V-NEXT: ret
;
-; ZIP-LABEL: vector_deinterleave_nxv2i64_nxv4i64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e64, m2, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v12, v8, v10
-; ZIP-NEXT: ri.vunzip2b.vv v14, v8, v10
-; ZIP-NEXT: vmv.v.v v8, v12
-; ZIP-NEXT: vmv.v.v v10, v14
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_deinterleave_nxv2i64_nxv4i64:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e64, m2, ta, ma
@@ -206,15 +152,6 @@ define {<vscale x 4 x i64>, <vscale x 4 x i64>} @vector_deinterleave_nxv4i64_nxv
; V-NEXT: vmv4r.v v12, v24
; V-NEXT: ret
;
-; ZIP-LABEL: vector_deinterleave_nxv4i64_nxv8i64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v16, v8, v12
-; ZIP-NEXT: ri.vunzip2b.vv v20, v8, v12
-; ZIP-NEXT: vmv.v.v v8, v16
-; ZIP-NEXT: vmv.v.v v12, v20
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_deinterleave_nxv4i64_nxv8i64:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e64, m4, ta, ma
@@ -247,26 +184,6 @@ define {<vscale x 64 x i1>, <vscale x 64 x i1>} @vector_deinterleave_nxv64i1_nxv
; V-NEXT: vmv1r.v v0, v16
; V-NEXT: ret
;
-; ZIP-LABEL: vector_deinterleave_nxv64i1_nxv128i1:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; ZIP-NEXT: vmv1r.v v9, v0
-; ZIP-NEXT: vmv1r.v v0, v8
-; ZIP-NEXT: vmv.v.i v24, 0
-; ZIP-NEXT: vmerge.vim v16, v24, 1, v0
-; ZIP-NEXT: vmv1r.v v0, v9
-; ZIP-NEXT: vmerge.vim v24, v24, 1, v0
-; ZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v12, v16, v20
-; ZIP-NEXT: ri.vunzip2b.vv v4, v16, v20
-; ZIP-NEXT: ri.vunzip2a.vv v8, v24, v28
-; ZIP-NEXT: ri.vunzip2b.vv v0, v24, v28
-; ZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; ZIP-NEXT: vmsne.vi v16, v8, 0
-; ZIP-NEXT: vmsne.vi v8, v0, 0
-; ZIP-NEXT: vmv1r.v v0, v16
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_deinterleave_nxv64i1_nxv128i1:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
@@ -300,17 +217,6 @@ define {<vscale x 64 x i8>, <vscale x 64 x i8>} @vector_deinterleave_nxv64i8_nxv
; V-NEXT: vmv8r.v v16, v0
; V-NEXT: ret
;
-; ZIP-LABEL: vector_deinterleave_nxv64i8_nxv128i8:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v28, v16, v20
-; ZIP-NEXT: ri.vunzip2b.vv v4, v16, v20
-; ZIP-NEXT: ri.vunzip2a.vv v24, v8, v12
-; ZIP-NEXT: ri.vunzip2b.vv v0, v8, v12
-; ZIP-NEXT: vmv8r.v v8, v24
-; ZIP-NEXT: vmv8r.v v16, v0
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_deinterleave_nxv64i8_nxv128i8:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
@@ -337,17 +243,6 @@ define {<vscale x 32 x i16>, <vscale x 32 x i16>} @vector_deinterleave_nxv32i16_
; V-NEXT: vmv8r.v v16, v0
; V-NEXT: ret
;
-; ZIP-LABEL: vector_deinterleave_nxv32i16_nxv64i16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v28, v16, v20
-; ZIP-NEXT: ri.vunzip2b.vv v4, v16, v20
-; ZIP-NEXT: ri.vunzip2a.vv v24, v8, v12
-; ZIP-NEXT: ri.vunzip2b.vv v0, v8, v12
-; ZIP-NEXT: vmv8r.v v8, v24
-; ZIP-NEXT: vmv8r.v v16, v0
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_deinterleave_nxv32i16_nxv64i16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
@@ -375,17 +270,6 @@ define {<vscale x 16 x i32>, <vscale x 16 x i32>} @vector_deinterleave_nxv16i32_
; V-NEXT: vmv8r.v v8, v0
; V-NEXT: ret
;
-; ZIP-LABEL: vector_deinterleave_nxv16i32_nxvv32i32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v28, v16, v20
-; ZIP-NEXT: ri.vunzip2b.vv v4, v16, v20
-; ZIP-NEXT: ri.vunzip2a.vv v24, v8, v12
-; ZIP-NEXT: ri.vunzip2b.vv v0, v8, v12
-; ZIP-NEXT: vmv8r.v v8, v24
-; ZIP-NEXT: vmv8r.v v16, v0
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_deinterleave_nxv16i32_nxvv32i32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e32, m4, ta, ma
@@ -447,17 +331,6 @@ define {<vscale x 8 x i64>, <vscale x 8 x i64>} @vector_deinterleave_nxv8i64_nxv
; V-NEXT: .cfi_def_cfa_offset 0
; V-NEXT: ret
;
-; ZIP-LABEL: vector_deinterleave_nxv8i64_nxv16i64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v28, v16, v20
-; ZIP-NEXT: ri.vunzip2b.vv v4, v16, v20
-; ZIP-NEXT: ri.vunzip2a.vv v24, v8, v12
-; ZIP-NEXT: ri.vunzip2b.vv v0, v8, v12
-; ZIP-NEXT: vmv8r.v v8, v24
-; ZIP-NEXT: vmv8r.v v16, v0
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_deinterleave_nxv8i64_nxv16i64:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e64, m4, ta, ma
@@ -1710,14 +1583,6 @@ define {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @vector_deinterleave_nxv2b
; V-NEXT: vmv1r.v v8, v10
; V-NEXT: ret
;
-; ZIP-LABEL: vector_deinterleave_nxv2bf16_nxv4bf16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v10, v8, v9
-; ZIP-NEXT: ri.vunzip2b.vv v9, v8, v11
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_deinterleave_nxv2bf16_nxv4bf16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
@@ -1738,14 +1603,6 @@ define {<vscale x 2 x half>, <vscale x 2 x half>} @vector_deinterleave_nxv2f16_n
; V-NEXT: vmv1r.v v8, v10
; V-NEXT: ret
;
-; ZIP-LABEL: vector_deinterleave_nxv2f16_nxv4f16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v10, v8, v9
-; ZIP-NEXT: ri.vunzip2b.vv v9, v8, v11
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_deinterleave_nxv2f16_nxv4f16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
@@ -1767,15 +1624,6 @@ define {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>} @vector_deinterleave_nxv4b
; V-NEXT: vmv.v.v v9, v11
; V-NEXT: ret
;
-; ZIP-LABEL: vector_deinterleave_nxv4bf16_nxv8bf16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v10, v8, v9
-; ZIP-NEXT: ri.vunzip2b.vv v11, v8, v9
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: vmv.v.v v9, v11
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_deinterleave_nxv4bf16_nxv8bf16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
@@ -1798,15 +1646,6 @@ define {<vscale x 4 x half>, <vscale x 4 x half>} @vector_deinterleave_nxv4f16_n
; V-NEXT: vmv.v.v v9, v11
; V-NEXT: ret
;
-; ZIP-LABEL: vector_deinterleave_nxv4f16_nxv8f16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v10, v8, v9
-; ZIP-NEXT: ri.vunzip2b.vv v11, v8, v9
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: vmv.v.v v9, v11
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_deinterleave_nxv4f16_nxv8f16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
@@ -1830,15 +1669,6 @@ define {<vscale x 2 x float>, <vscale x 2 x float>} @vector_deinterleave_nxv2f32
; V-NEXT: vmv.v.v v9, v10
; V-NEXT: ret
;
-; ZIP-LABEL: vector_deinterleave_nxv2f32_nxv4f32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v10, v8, v9
-; ZIP-NEXT: ri.vunzip2b.vv v11, v8, v9
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: vmv.v.v v9, v11
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_deinterleave_nxv2f32_nxv4f32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
@@ -1861,15 +1691,6 @@ define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @vector_deinterleave_nxv8b
; V-NEXT: vmv.v.v v10, v14
; V-NEXT: ret
;
-; ZIP-LABEL: vector_deinterleave_nxv8bf16_nxv16bf16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v12, v8, v10
-; ZIP-NEXT: ri.vunzip2b.vv v14, v8, v10
-; ZIP-NEXT: vmv.v.v v8, v12
-; ZIP-NEXT: vmv.v.v v10, v14
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_deinterleave_nxv8bf16_nxv16bf16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
@@ -1892,15 +1713,6 @@ define {<vscale x 8 x half>, <vscale x 8 x half>} @vector_deinterleave_nxv8f16_n
; V-NEXT: vmv.v.v v10, v14
; V-NEXT: ret
;
-; ZIP-LABEL: vector_deinterleave_nxv8f16_nxv16f16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v12, v8, v10
-; ZIP-NEXT: ri.vunzip2b.vv v14, v8, v10
-; ZIP-NEXT: vmv.v.v v8, v12
-; ZIP-NEXT: vmv.v.v v10, v14
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_deinterleave_nxv8f16_nxv16f16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
@@ -1924,15 +1736,6 @@ define {<vscale x 4 x float>, <vscale x 4 x float>} @vector_deinterleave_nxv4f32
; V-NEXT: vmv.v.v v10, v12
; V-NEXT: ret
;
-; ZIP-LABEL: vector_deinterleave_nxv4f32_nxv8f32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v12, v8, v10
-; ZIP-NEXT: ri.vunzip2b.vv v14, v8, v10
-; ZIP-NEXT: vmv.v.v v8, v12
-; ZIP-NEXT: vmv.v.v v10, v14
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_deinterleave_nxv4f32_nxv8f32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e32, m2, ta, ma
@@ -1960,15 +1763,6 @@ define {<vscale x 2 x double>, <vscale x 2 x double>} @vector_deinterleave_nxv2f
; V-NEXT: vmv2r.v v10, v16
; V-NEXT: ret
;
-; ZIP-LABEL: vector_deinterleave_nxv2f64_nxv4f64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e64, m2, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v12, v8, v10
-; ZIP-NEXT: ri.vunzip2b.vv v14, v8, v10
-; ZIP-NEXT: vmv.v.v v8, v12
-; ZIP-NEXT: vmv.v.v v10, v14
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_deinterleave_nxv2f64_nxv4f64:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e64, m2, ta, ma
@@ -1994,17 +1788,6 @@ define {<vscale x 32 x bfloat>, <vscale x 32 x bfloat>} @vector_deinterleave_nxv
; V-NEXT: vmv8r.v v16, v0
; V-NEXT: ret
;
-; ZIP-LABEL: vector_deinterleave_nxv32bf16_nxv64bf16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v28, v16, v20
-; ZIP-NEXT: ri.vunzip2b.vv v4, v16, v20
-; ZIP-NEXT: ri.vunzip2a.vv v24, v8, v12
-; ZIP-NEXT: ri.vunzip2b.vv v0, v8, v12
-; ZIP-NEXT: vmv8r.v v8, v24
-; ZIP-NEXT: vmv8r.v v16, v0
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_deinterleave_nxv32bf16_nxv64bf16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
@@ -2031,17 +1814,6 @@ define {<vscale x 32 x half>, <vscale x 32 x half>} @vector_deinterleave_nxv32f1
; V-NEXT: vmv8r.v v16, v0
; V-NEXT: ret
;
-; ZIP-LABEL: vector_deinterleave_nxv32f16_nxv64f16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v28, v16, v20
-; ZIP-NEXT: ri.vunzip2b.vv v4, v16, v20
-; ZIP-NEXT: ri.vunzip2a.vv v24, v8, v12
-; ZIP-NEXT: ri.vunzip2b.vv v0, v8, v12
-; ZIP-NEXT: vmv8r.v v8, v24
-; ZIP-NEXT: vmv8r.v v16, v0
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_deinterleave_nxv32f16_nxv64f16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
@@ -2069,17 +1841,6 @@ define {<vscale x 16 x float>, <vscale x 16 x float>} @vector_deinterleave_nxv16
; V-NEXT: vmv8r.v v8, v0
; V-NEXT: ret
;
-; ZIP-LABEL: vector_deinterleave_nxv16f32_nxv32f32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v28, v16, v20
-; ZIP-NEXT: ri.vunzip2b.vv v4, v16, v20
-; ZIP-NEXT: ri.vunzip2a.vv v24, v8, v12
-; ZIP-NEXT: ri.vunzip2b.vv v0, v8, v12
-; ZIP-NEXT: vmv8r.v v8, v24
-; ZIP-NEXT: vmv8r.v v16, v0
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_deinterleave_nxv16f32_nxv32f32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e32, m4, ta, ma
@@ -2141,17 +1902,6 @@ define {<vscale x 8 x double>, <vscale x 8 x double>} @vector_deinterleave_nxv8f
; V-NEXT: .cfi_def_cfa_offset 0
; V-NEXT: ret
;
-; ZIP-LABEL: vector_deinterleave_nxv8f64_nxv16f64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v28, v16, v20
-; ZIP-NEXT: ri.vunzip2b.vv v4, v16, v20
-; ZIP-NEXT: ri.vunzip2a.vv v24, v8, v12
-; ZIP-NEXT: ri.vunzip2b.vv v0, v8, v12
-; ZIP-NEXT: vmv8r.v v8, v24
-; ZIP-NEXT: vmv8r.v v16, v0
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_deinterleave_nxv8f64_nxv16f64:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e64, m4, ta, ma
@@ -3940,13 +3690,6 @@ define <vscale x 16 x i8> @vector_deinterleave_nxv16i8_nxv32i8_oneactive(<vscale
; V-NEXT: vmv.v.v v8, v12
; V-NEXT: ret
;
-; ZIP-LABEL: vector_deinterleave_nxv16i8_nxv32i8_oneactive:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v12, v8, v10
-; ZIP-NEXT: vmv.v.v v8, v12
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_deinterleave_nxv16i8_nxv32i8_oneactive:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
@@ -4016,17 +3759,6 @@ define { <8 x float>, <8 x float> } @interleave_deinterleave2(<8 x float> %a, <8
; V-NEXT: vnsrl.wi v8, v12, 0
; V-NEXT: ret
;
-; ZIP-LABEL: interleave_deinterleave2:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; ZIP-NEXT: vmv2r.v v12, v10
-; ZIP-NEXT: li a0, 32
-; ZIP-NEXT: ri.vzip2a.vv v16, v8, v12
-; ZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZIP-NEXT: vnsrl.wx v10, v16, a0
-; ZIP-NEXT: vnsrl.wi v8, v16, 0
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: interleave_deinterleave2:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
@@ -4053,16 +3785,6 @@ define <16 x float> @deinterleave_interleave2(<16 x float> %arg) {
; V-NEXT: vwmaccu.vx v8, a0, v14
; V-NEXT: ret
;
-; ZIP-LABEL: deinterleave_interleave2:
-; ZIP: # %bb.0: # %entry
-; ZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZIP-NEXT: vnsrl.wi v12, v8, 0
-; ZIP-NEXT: li a0, 32
-; ZIP-NEXT: vnsrl.wx v16, v8, a0
-; ZIP-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; ZIP-NEXT: ri.vzip2a.vv v8, v12, v16
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: deinterleave_interleave2:
; ZVZIP: # %bb.0: # %entry
; ZVZIP-NEXT: li a0, 32
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
index 30dd84c008f81..0fc7b5b2187b5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
@@ -3,8 +3,6 @@
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+zvfbfmin | FileCheck -check-prefixes=CHECK %s
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvbb,+zvfh,+zvfbfmin | FileCheck %s --check-prefix=ZVBB
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvbb,+zvfh,+zvfbfmin | FileCheck %s --check-prefix=ZVBB
-; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvbb,+zvfh,+zvfbfmin,+experimental-xrivosvizip | FileCheck %s --check-prefix=ZIP
-; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvbb,+zvfh,+zvfbfmin,+experimental-xrivosvizip | FileCheck %s --check-prefix=ZIP
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvbb,+zvfh,+zvfbfmin,+experimental-zvzip | FileCheck %s --check-prefix=ZVZIP
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvbb,+zvfh,+zvfbfmin,+experimental-zvzip | FileCheck %s --check-prefix=ZVZIP
@@ -46,21 +44,6 @@ define <32 x i1> @vector_interleave_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b) {
; ZVBB-NEXT: vmsne.vi v0, v12, 0
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_v32i1_v16i1:
-; ZIP: # %bb.0:
-; ZIP-NEXT: li a0, 32
-; ZIP-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; ZIP-NEXT: vslideup.vi v0, v8, 2
-; ZIP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; ZIP-NEXT: vmv.v.i v8, 0
-; ZIP-NEXT: vmerge.vim v8, v8, 1, v0
-; ZIP-NEXT: vsetivli zero, 16, e8, m2, ta, ma
-; ZIP-NEXT: vslidedown.vi v10, v8, 16
-; ZIP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; ZIP-NEXT: ri.vzip2a.vv v12, v8, v10
-; ZIP-NEXT: vmsne.vi v0, v12, 0
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_v32i1_v16i1:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: li a0, 32
@@ -100,14 +83,6 @@ define <16 x i16> @vector_interleave_v16i16_v8i16(<8 x i16> %a, <8 x i16> %b) {
; ZVBB-NEXT: vwaddu.wv v8, v8, v11
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_v16i16_v8i16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZIP-NEXT: vmv1r.v v12, v9
-; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_v16i16_v8i16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
@@ -140,14 +115,6 @@ define <8 x i32> @vector_interleave_v8i32_v4i32(<4 x i32> %a, <4 x i32> %b) {
; ZVBB-NEXT: vwaddu.wv v8, v8, v11
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_v8i32_v4i32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZIP-NEXT: vmv1r.v v12, v9
-; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_v8i32_v4i32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
@@ -190,14 +157,6 @@ define <4 x i64> @vector_interleave_v4i64_v2i64(<2 x i64> %a, <2 x i64> %b) {
; ZVBB-NEXT: vmv.v.v v8, v10
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_v4i64_v2i64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; ZIP-NEXT: vmv1r.v v12, v9
-; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_v4i64_v2i64:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
@@ -262,32 +221,6 @@ define <6 x i32> @vector_interleave3_v6i32_v2i32(<2 x i32> %a, <2 x i32> %b, <2
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave3_v6i32_v2i32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -16
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: addi a0, sp, 16
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: srli a1, a1, 1
-; ZIP-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
-; ZIP-NEXT: vsseg3e32.v v8, (a0)
-; ZIP-NEXT: add a2, a0, a1
-; ZIP-NEXT: vle32.v v9, (a2)
-; ZIP-NEXT: vle32.v v8, (a0)
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: vle32.v v10, (a1)
-; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v9, 2
-; ZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v10, 4
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: add sp, sp, a0
-; ZIP-NEXT: addi sp, sp, 16
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave3_v6i32_v2i32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -16
@@ -376,35 +309,6 @@ define <8 x i32> @vector_interleave4_v8i32_v2i32(<2 x i32> %a, <2 x i32> %b, <2
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave4_v8i32_v2i32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -16
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: addi a0, sp, 16
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: srli a1, a1, 1
-; ZIP-NEXT: add a2, a0, a1
-; ZIP-NEXT: vsetvli a3, zero, e32, mf2, ta, ma
-; ZIP-NEXT: vsseg4e32.v v8, (a0)
-; ZIP-NEXT: add a3, a2, a1
-; ZIP-NEXT: add a1, a3, a1
-; ZIP-NEXT: vle32.v v10, (a3)
-; ZIP-NEXT: vle32.v v9, (a2)
-; ZIP-NEXT: vle32.v v11, (a1)
-; ZIP-NEXT: vle32.v v8, (a0)
-; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZIP-NEXT: vslideup.vi v10, v11, 2
-; ZIP-NEXT: vslideup.vi v8, v9, 2
-; ZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v10, 4
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: add sp, sp, a0
-; ZIP-NEXT: addi sp, sp, 16
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave4_v8i32_v2i32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -16
@@ -504,39 +408,6 @@ define <10 x i16> @vector_interleave5_v10i16_v2i16(<2 x i16> %a, <2 x i16> %b, <
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave5_v10i16_v2i16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -16
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: addi a0, sp, 16
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: srli a1, a1, 2
-; ZIP-NEXT: add a2, a0, a1
-; ZIP-NEXT: add a3, a2, a1
-; ZIP-NEXT: vsetvli a4, zero, e16, mf4, ta, ma
-; ZIP-NEXT: vsseg5e16.v v8, (a0)
-; ZIP-NEXT: add a4, a3, a1
-; ZIP-NEXT: vle16.v v9, (a2)
-; ZIP-NEXT: vle16.v v11, (a4)
-; ZIP-NEXT: vle16.v v12, (a3)
-; ZIP-NEXT: vle16.v v8, (a0)
-; ZIP-NEXT: add a1, a4, a1
-; ZIP-NEXT: vle16.v v10, (a1)
-; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZIP-NEXT: vslideup.vi v12, v11, 2
-; ZIP-NEXT: vslideup.vi v8, v9, 2
-; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v12, 4
-; ZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v10, 8
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: add sp, sp, a0
-; ZIP-NEXT: addi sp, sp, 16
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave5_v10i16_v2i16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -16
@@ -646,42 +517,6 @@ define <12 x i16> @vector_interleave6_v12i16_v2i16(<2 x i16> %a, <2 x i16> %b, <
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave6_v12i16_v2i16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -16
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: addi a0, sp, 16
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: srli a1, a1, 2
-; ZIP-NEXT: add a2, a0, a1
-; ZIP-NEXT: add a3, a2, a1
-; ZIP-NEXT: vsetvli a4, zero, e16, mf4, ta, ma
-; ZIP-NEXT: vsseg6e16.v v8, (a0)
-; ZIP-NEXT: vle16.v v9, (a2)
-; ZIP-NEXT: add a2, a3, a1
-; ZIP-NEXT: vle16.v v11, (a2)
-; ZIP-NEXT: add a2, a2, a1
-; ZIP-NEXT: vle16.v v12, (a3)
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: vle16.v v10, (a2)
-; ZIP-NEXT: vle16.v v8, (a0)
-; ZIP-NEXT: vle16.v v13, (a1)
-; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZIP-NEXT: vslideup.vi v12, v11, 2
-; ZIP-NEXT: vslideup.vi v8, v9, 2
-; ZIP-NEXT: vslideup.vi v10, v13, 2
-; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v12, 4
-; ZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v10, 8
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: add sp, sp, a0
-; ZIP-NEXT: addi sp, sp, 16
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave6_v12i16_v2i16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -16
@@ -798,44 +633,6 @@ define <14 x i8> @vector_interleave7_v14i8_v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave7_v14i8_v2i8:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -16
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: addi a0, sp, 16
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: srli a1, a1, 3
-; ZIP-NEXT: add a2, a0, a1
-; ZIP-NEXT: add a3, a2, a1
-; ZIP-NEXT: add a4, a3, a1
-; ZIP-NEXT: vsetvli a5, zero, e8, mf8, ta, ma
-; ZIP-NEXT: vsseg7e8.v v8, (a0)
-; ZIP-NEXT: vle8.v v9, (a4)
-; ZIP-NEXT: add a4, a4, a1
-; ZIP-NEXT: vle8.v v10, (a2)
-; ZIP-NEXT: add a2, a4, a1
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: vle8.v v11, (a2)
-; ZIP-NEXT: vle8.v v12, (a4)
-; ZIP-NEXT: vle8.v v8, (a0)
-; ZIP-NEXT: vle8.v v13, (a1)
-; ZIP-NEXT: vle8.v v14, (a3)
-; ZIP-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
-; ZIP-NEXT: vslideup.vi v12, v11, 2
-; ZIP-NEXT: vslideup.vi v8, v10, 2
-; ZIP-NEXT: vsetivli zero, 6, e8, mf2, tu, ma
-; ZIP-NEXT: vslideup.vi v12, v13, 4
-; ZIP-NEXT: vslideup.vi v8, v14, 4
-; ZIP-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v9, 6
-; ZIP-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v12, 8
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: add sp, sp, a0
-; ZIP-NEXT: addi sp, sp, 16
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave7_v14i8_v2i8:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -16
@@ -960,47 +757,6 @@ define <16 x i8> @vector_interleave8_v16i8_v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave8_v16i8_v2i8:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -16
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: addi a0, sp, 16
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: srli a1, a1, 3
-; ZIP-NEXT: add a2, a0, a1
-; ZIP-NEXT: add a3, a2, a1
-; ZIP-NEXT: add a4, a3, a1
-; ZIP-NEXT: add a5, a4, a1
-; ZIP-NEXT: add a6, a5, a1
-; ZIP-NEXT: vsetvli a7, zero, e8, mf8, ta, ma
-; ZIP-NEXT: vsseg8e8.v v8, (a0)
-; ZIP-NEXT: vle8.v v9, (a6)
-; ZIP-NEXT: add a6, a6, a1
-; ZIP-NEXT: vle8.v v10, (a5)
-; ZIP-NEXT: vle8.v v11, (a6)
-; ZIP-NEXT: add a1, a6, a1
-; ZIP-NEXT: vle8.v v12, (a2)
-; ZIP-NEXT: vle8.v v8, (a0)
-; ZIP-NEXT: vle8.v v13, (a3)
-; ZIP-NEXT: vle8.v v14, (a4)
-; ZIP-NEXT: vle8.v v15, (a1)
-; ZIP-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
-; ZIP-NEXT: vslideup.vi v10, v9, 2
-; ZIP-NEXT: vslideup.vi v8, v12, 2
-; ZIP-NEXT: vsetivli zero, 6, e8, mf2, tu, ma
-; ZIP-NEXT: vslideup.vi v10, v11, 4
-; ZIP-NEXT: vslideup.vi v8, v13, 4
-; ZIP-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; ZIP-NEXT: vslideup.vi v10, v15, 6
-; ZIP-NEXT: vslideup.vi v8, v14, 6
-; ZIP-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v10, 8
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: add sp, sp, a0
-; ZIP-NEXT: addi sp, sp, 16
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave8_v16i8_v2i8:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -16
@@ -1065,13 +821,6 @@ define <4 x half> @vector_interleave_v4f16_v2f16(<2 x half> %a, <2 x half> %b) {
; ZVBB-NEXT: vmv1r.v v8, v10
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_v4f16_v2f16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZIP-NEXT: ri.vzip2a.vv v10, v8, v9
-; ZIP-NEXT: vmv1r.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_v4f16_v2f16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
@@ -1100,13 +849,6 @@ define <4 x bfloat> @vector_interleave_v4bf16_v2bf16(<2 x bfloat> %a, <2 x bfloa
; ZVBB-NEXT: vmv1r.v v8, v10
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_v4bf16_v2bf16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZIP-NEXT: ri.vzip2a.vv v10, v8, v9
-; ZIP-NEXT: vmv1r.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_v4bf16_v2bf16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
@@ -1135,13 +877,6 @@ define <8 x half> @vector_interleave_v8f16_v4f16(<4 x half> %a, <4 x half> %b) {
; ZVBB-NEXT: vmv1r.v v8, v10
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_v8f16_v4f16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZIP-NEXT: ri.vzip2a.vv v10, v8, v9
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_v8f16_v4f16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
@@ -1170,13 +905,6 @@ define <8 x bfloat> @vector_interleave_v8bf16_v4bf16(<4 x bfloat> %a, <4 x bfloa
; ZVBB-NEXT: vmv1r.v v8, v10
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_v8bf16_v4bf16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZIP-NEXT: ri.vzip2a.vv v10, v8, v9
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_v8bf16_v4bf16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
@@ -1206,13 +934,6 @@ define <4 x float> @vector_interleave_v4f32_v2f32(<2 x float> %a, <2 x float> %b
; ZVBB-NEXT: vmv1r.v v8, v10
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_v4f32_v2f32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZIP-NEXT: ri.vzip2a.vv v10, v8, v9
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_v4f32_v2f32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
@@ -1243,14 +964,6 @@ define <16 x half> @vector_interleave_v16f16_v8f16(<8 x half> %a, <8 x half> %b)
; ZVBB-NEXT: vwaddu.wv v8, v8, v11
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_v16f16_v8f16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZIP-NEXT: vmv1r.v v12, v9
-; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_v16f16_v8f16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
@@ -1282,14 +995,6 @@ define <16 x bfloat> @vector_interleave_v16bf16_v8bf16(<8 x bfloat> %a, <8 x bfl
; ZVBB-NEXT: vwaddu.wv v8, v8, v11
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_v16bf16_v8bf16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZIP-NEXT: vmv1r.v v12, v9
-; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_v16bf16_v8bf16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
@@ -1322,14 +1027,6 @@ define <8 x float> @vector_interleave_v8f32_v4f32(<4 x float> %a, <4 x float> %b
; ZVBB-NEXT: vwaddu.wv v8, v8, v11
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_v8f32_v4f32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZIP-NEXT: vmv1r.v v12, v9
-; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_v8f32_v4f32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
@@ -1372,14 +1069,6 @@ define <4 x double> @vector_interleave_v4f64_v2f64(<2 x double> %a, <2 x double>
; ZVBB-NEXT: vmv.v.v v8, v10
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_v4f64_v2f64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; ZIP-NEXT: vmv1r.v v12, v9
-; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_v4f64_v2f64:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
@@ -1444,32 +1133,6 @@ define <6 x float> @vector_interleave3_v6f32_v2f32(<2 x float> %a, <2 x float> %
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave3_v6f32_v2f32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -16
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: addi a0, sp, 16
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: srli a1, a1, 1
-; ZIP-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
-; ZIP-NEXT: vsseg3e32.v v8, (a0)
-; ZIP-NEXT: add a2, a0, a1
-; ZIP-NEXT: vle32.v v9, (a2)
-; ZIP-NEXT: vle32.v v8, (a0)
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: vle32.v v10, (a1)
-; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v9, 2
-; ZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v10, 4
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: add sp, sp, a0
-; ZIP-NEXT: addi sp, sp, 16
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave3_v6f32_v2f32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -16
@@ -1558,35 +1221,6 @@ define <8 x float> @vector_interleave4_v8f32_v2f32(<2 x float> %a, <2 x float> %
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave4_v8f32_v2f32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -16
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: addi a0, sp, 16
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: srli a1, a1, 1
-; ZIP-NEXT: add a2, a0, a1
-; ZIP-NEXT: vsetvli a3, zero, e32, mf2, ta, ma
-; ZIP-NEXT: vsseg4e32.v v8, (a0)
-; ZIP-NEXT: add a3, a2, a1
-; ZIP-NEXT: add a1, a3, a1
-; ZIP-NEXT: vle32.v v10, (a3)
-; ZIP-NEXT: vle32.v v9, (a2)
-; ZIP-NEXT: vle32.v v11, (a1)
-; ZIP-NEXT: vle32.v v8, (a0)
-; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; ZIP-NEXT: vslideup.vi v10, v11, 2
-; ZIP-NEXT: vslideup.vi v8, v9, 2
-; ZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v10, 4
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: add sp, sp, a0
-; ZIP-NEXT: addi sp, sp, 16
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave4_v8f32_v2f32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -16
@@ -1686,39 +1320,6 @@ define <10 x half> @vector_interleave5_v10f16_v2f16(<2 x half> %a, <2 x half> %b
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave5_v10f16_v2f16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -16
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: addi a0, sp, 16
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: srli a1, a1, 2
-; ZIP-NEXT: add a2, a0, a1
-; ZIP-NEXT: add a3, a2, a1
-; ZIP-NEXT: vsetvli a4, zero, e16, mf4, ta, ma
-; ZIP-NEXT: vsseg5e16.v v8, (a0)
-; ZIP-NEXT: add a4, a3, a1
-; ZIP-NEXT: vle16.v v9, (a2)
-; ZIP-NEXT: vle16.v v11, (a4)
-; ZIP-NEXT: vle16.v v12, (a3)
-; ZIP-NEXT: vle16.v v8, (a0)
-; ZIP-NEXT: add a1, a4, a1
-; ZIP-NEXT: vle16.v v10, (a1)
-; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZIP-NEXT: vslideup.vi v12, v11, 2
-; ZIP-NEXT: vslideup.vi v8, v9, 2
-; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v12, 4
-; ZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v10, 8
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: add sp, sp, a0
-; ZIP-NEXT: addi sp, sp, 16
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave5_v10f16_v2f16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -16
@@ -1822,39 +1423,6 @@ define <10 x bfloat> @vector_interleave5_v10bf16_v2bf16(<2 x bfloat> %a, <2 x bf
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave5_v10bf16_v2bf16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -16
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: addi a0, sp, 16
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: srli a1, a1, 2
-; ZIP-NEXT: add a2, a0, a1
-; ZIP-NEXT: add a3, a2, a1
-; ZIP-NEXT: vsetvli a4, zero, e16, mf4, ta, ma
-; ZIP-NEXT: vsseg5e16.v v8, (a0)
-; ZIP-NEXT: add a4, a3, a1
-; ZIP-NEXT: vle16.v v9, (a2)
-; ZIP-NEXT: vle16.v v11, (a4)
-; ZIP-NEXT: vle16.v v12, (a3)
-; ZIP-NEXT: vle16.v v8, (a0)
-; ZIP-NEXT: add a1, a4, a1
-; ZIP-NEXT: vle16.v v10, (a1)
-; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZIP-NEXT: vslideup.vi v12, v11, 2
-; ZIP-NEXT: vslideup.vi v8, v9, 2
-; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v12, 4
-; ZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v10, 8
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: add sp, sp, a0
-; ZIP-NEXT: addi sp, sp, 16
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave5_v10bf16_v2bf16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -16
@@ -1964,42 +1532,6 @@ define <12 x half> @vector_interleave6_v12f16_v2f16(<2 x half> %a, <2 x half> %b
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave6_v12f16_v2f16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -16
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: addi a0, sp, 16
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: srli a1, a1, 2
-; ZIP-NEXT: add a2, a0, a1
-; ZIP-NEXT: add a3, a2, a1
-; ZIP-NEXT: vsetvli a4, zero, e16, mf4, ta, ma
-; ZIP-NEXT: vsseg6e16.v v8, (a0)
-; ZIP-NEXT: vle16.v v9, (a2)
-; ZIP-NEXT: add a2, a3, a1
-; ZIP-NEXT: vle16.v v11, (a2)
-; ZIP-NEXT: add a2, a2, a1
-; ZIP-NEXT: vle16.v v12, (a3)
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: vle16.v v10, (a2)
-; ZIP-NEXT: vle16.v v8, (a0)
-; ZIP-NEXT: vle16.v v13, (a1)
-; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZIP-NEXT: vslideup.vi v12, v11, 2
-; ZIP-NEXT: vslideup.vi v8, v9, 2
-; ZIP-NEXT: vslideup.vi v10, v13, 2
-; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v12, 4
-; ZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v10, 8
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: add sp, sp, a0
-; ZIP-NEXT: addi sp, sp, 16
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave6_v12f16_v2f16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -16
@@ -2112,42 +1644,6 @@ define <12 x bfloat> @vector_interleave6_v12bf16_v2bf16(<2 x bfloat> %a, <2 x bf
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave6_v12bf16_v2bf16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -16
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: addi a0, sp, 16
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: srli a1, a1, 2
-; ZIP-NEXT: add a2, a0, a1
-; ZIP-NEXT: add a3, a2, a1
-; ZIP-NEXT: vsetvli a4, zero, e16, mf4, ta, ma
-; ZIP-NEXT: vsseg6e16.v v8, (a0)
-; ZIP-NEXT: vle16.v v9, (a2)
-; ZIP-NEXT: add a2, a3, a1
-; ZIP-NEXT: vle16.v v11, (a2)
-; ZIP-NEXT: add a2, a2, a1
-; ZIP-NEXT: vle16.v v12, (a3)
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: vle16.v v10, (a2)
-; ZIP-NEXT: vle16.v v8, (a0)
-; ZIP-NEXT: vle16.v v13, (a1)
-; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZIP-NEXT: vslideup.vi v12, v11, 2
-; ZIP-NEXT: vslideup.vi v8, v9, 2
-; ZIP-NEXT: vslideup.vi v10, v13, 2
-; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v12, 4
-; ZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v10, 8
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: add sp, sp, a0
-; ZIP-NEXT: addi sp, sp, 16
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave6_v12bf16_v2bf16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -16
@@ -2268,46 +1764,6 @@ define <7 x half> @vector_interleave7_v7f16_v1f16(<1 x half> %a, <1 x half> %b,
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave7_v7f16_v1f16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -16
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: addi a0, sp, 16
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: srli a1, a1, 2
-; ZIP-NEXT: add a2, a0, a1
-; ZIP-NEXT: add a3, a2, a1
-; ZIP-NEXT: add a4, a3, a1
-; ZIP-NEXT: vsetvli a5, zero, e16, mf4, ta, ma
-; ZIP-NEXT: vsseg7e16.v v8, (a0)
-; ZIP-NEXT: vle16.v v9, (a4)
-; ZIP-NEXT: add a4, a4, a1
-; ZIP-NEXT: vle16.v v10, (a2)
-; ZIP-NEXT: add a2, a4, a1
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: vle16.v v11, (a2)
-; ZIP-NEXT: vle16.v v12, (a4)
-; ZIP-NEXT: vle16.v v8, (a0)
-; ZIP-NEXT: vle16.v v13, (a1)
-; ZIP-NEXT: vle16.v v14, (a3)
-; ZIP-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; ZIP-NEXT: vslideup.vi v12, v11, 1
-; ZIP-NEXT: vslideup.vi v8, v10, 1
-; ZIP-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
-; ZIP-NEXT: vslideup.vi v12, v13, 2
-; ZIP-NEXT: vslideup.vi v8, v14, 2
-; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v9, 3
-; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v12, 4
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: add sp, sp, a0
-; ZIP-NEXT: addi sp, sp, 16
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave7_v7f16_v1f16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -16
@@ -2432,46 +1888,6 @@ define <7 x bfloat> @vector_interleave7_v7bf16_v1bf16(<1 x bfloat> %a, <1 x bflo
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave7_v7bf16_v1bf16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -16
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: addi a0, sp, 16
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: srli a1, a1, 2
-; ZIP-NEXT: add a2, a0, a1
-; ZIP-NEXT: add a3, a2, a1
-; ZIP-NEXT: add a4, a3, a1
-; ZIP-NEXT: vsetvli a5, zero, e16, mf4, ta, ma
-; ZIP-NEXT: vsseg7e16.v v8, (a0)
-; ZIP-NEXT: vle16.v v9, (a4)
-; ZIP-NEXT: add a4, a4, a1
-; ZIP-NEXT: vle16.v v10, (a2)
-; ZIP-NEXT: add a2, a4, a1
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: vle16.v v11, (a2)
-; ZIP-NEXT: vle16.v v12, (a4)
-; ZIP-NEXT: vle16.v v8, (a0)
-; ZIP-NEXT: vle16.v v13, (a1)
-; ZIP-NEXT: vle16.v v14, (a3)
-; ZIP-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; ZIP-NEXT: vslideup.vi v12, v11, 1
-; ZIP-NEXT: vslideup.vi v8, v10, 1
-; ZIP-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
-; ZIP-NEXT: vslideup.vi v12, v13, 2
-; ZIP-NEXT: vslideup.vi v8, v14, 2
-; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v9, 3
-; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v12, 4
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: add sp, sp, a0
-; ZIP-NEXT: addi sp, sp, 16
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave7_v7bf16_v1bf16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -16
@@ -2602,49 +2018,6 @@ define <8 x half> @vector_interleave8_v8f16_v1f16(<1 x half> %a, <1 x half> %b,
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave8_v8f16_v1f16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -16
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: addi a0, sp, 16
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: srli a1, a1, 2
-; ZIP-NEXT: add a2, a0, a1
-; ZIP-NEXT: add a3, a2, a1
-; ZIP-NEXT: add a4, a3, a1
-; ZIP-NEXT: add a5, a4, a1
-; ZIP-NEXT: add a6, a5, a1
-; ZIP-NEXT: vsetvli a7, zero, e16, mf4, ta, ma
-; ZIP-NEXT: vsseg8e16.v v8, (a0)
-; ZIP-NEXT: vle16.v v9, (a6)
-; ZIP-NEXT: add a6, a6, a1
-; ZIP-NEXT: vle16.v v10, (a5)
-; ZIP-NEXT: vle16.v v11, (a6)
-; ZIP-NEXT: add a1, a6, a1
-; ZIP-NEXT: vle16.v v12, (a2)
-; ZIP-NEXT: vle16.v v8, (a0)
-; ZIP-NEXT: vle16.v v13, (a3)
-; ZIP-NEXT: vle16.v v14, (a4)
-; ZIP-NEXT: vle16.v v15, (a1)
-; ZIP-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; ZIP-NEXT: vslideup.vi v10, v9, 1
-; ZIP-NEXT: vslideup.vi v8, v12, 1
-; ZIP-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
-; ZIP-NEXT: vslideup.vi v10, v11, 2
-; ZIP-NEXT: vslideup.vi v8, v13, 2
-; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZIP-NEXT: vslideup.vi v10, v15, 3
-; ZIP-NEXT: vslideup.vi v8, v14, 3
-; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v10, 4
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: add sp, sp, a0
-; ZIP-NEXT: addi sp, sp, 16
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave8_v8f16_v1f16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -16
@@ -2778,49 +2151,6 @@ define <8 x bfloat> @vector_interleave8_v8bf16_v1bf16(<1 x bfloat> %a, <1 x bflo
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave8_v8bf16_v1bf16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -16
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: addi a0, sp, 16
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: srli a1, a1, 2
-; ZIP-NEXT: add a2, a0, a1
-; ZIP-NEXT: add a3, a2, a1
-; ZIP-NEXT: add a4, a3, a1
-; ZIP-NEXT: add a5, a4, a1
-; ZIP-NEXT: add a6, a5, a1
-; ZIP-NEXT: vsetvli a7, zero, e16, mf4, ta, ma
-; ZIP-NEXT: vsseg8e16.v v8, (a0)
-; ZIP-NEXT: vle16.v v9, (a6)
-; ZIP-NEXT: add a6, a6, a1
-; ZIP-NEXT: vle16.v v10, (a5)
-; ZIP-NEXT: vle16.v v11, (a6)
-; ZIP-NEXT: add a1, a6, a1
-; ZIP-NEXT: vle16.v v12, (a2)
-; ZIP-NEXT: vle16.v v8, (a0)
-; ZIP-NEXT: vle16.v v13, (a3)
-; ZIP-NEXT: vle16.v v14, (a4)
-; ZIP-NEXT: vle16.v v15, (a1)
-; ZIP-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
-; ZIP-NEXT: vslideup.vi v10, v9, 1
-; ZIP-NEXT: vslideup.vi v8, v12, 1
-; ZIP-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
-; ZIP-NEXT: vslideup.vi v10, v11, 2
-; ZIP-NEXT: vslideup.vi v8, v13, 2
-; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZIP-NEXT: vslideup.vi v10, v15, 3
-; ZIP-NEXT: vslideup.vi v8, v14, 3
-; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZIP-NEXT: vslideup.vi v8, v10, 4
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 1
-; ZIP-NEXT: add sp, sp, a0
-; ZIP-NEXT: addi sp, sp, 16
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave8_v8bf16_v1bf16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -16
@@ -2880,12 +2210,6 @@ define <8 x i16> @interleave4_const_splat_v8i16(<2 x i16> %a) {
; ZVBB-NEXT: vmv.v.i v8, 3
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: interleave4_const_splat_v8i16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZIP-NEXT: vmv.v.i v8, 3
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: interleave4_const_splat_v8i16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
@@ -2908,12 +2232,6 @@ define <8 x i16> @interleave4_same_nonconst_splat_v8i16(i16 %a) {
; ZVBB-NEXT: vmv.v.x v8, a0
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: interleave4_same_nonconst_splat_v8i16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZIP-NEXT: vmv.v.x v8, a0
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: interleave4_same_nonconst_splat_v8i16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
index 736217a090c93..323031f59a88f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
@@ -5,7 +5,6 @@
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin | FileCheck %s --check-prefixes=CHECK,V,RV64
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+zvbb,+zvfh,+zvfbfmin | FileCheck %s --check-prefixes=ZVBB,ZVBB-RV32
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvbb,+zvfh,+zvfbfmin | FileCheck %s --check-prefixes=ZVBB,ZVBB-RV64
-; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin,+experimental-xrivosvizip | FileCheck %s --check-prefixes=CHECK,ZIP
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin,+experimental-zvzip | FileCheck %s --check-prefixes=CHECK,ZVZIP
; Integers
@@ -50,25 +49,6 @@ define <vscale x 32 x i1> @vector_interleave_nxv32i1_nxv16i1(<vscale x 16 x i1>
; ZVBB-NEXT: vslideup.vx v0, v8, a0
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv32i1_nxv16i1:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; ZIP-NEXT: vmv1r.v v9, v0
-; ZIP-NEXT: vmv1r.v v0, v8
-; ZIP-NEXT: vmv.v.i v10, 0
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: vmerge.vim v12, v10, 1, v0
-; ZIP-NEXT: vmv1r.v v0, v9
-; ZIP-NEXT: vmerge.vim v8, v10, 1, v0
-; ZIP-NEXT: ri.vzip2b.vv v10, v8, v12
-; ZIP-NEXT: ri.vzip2a.vv v14, v8, v12
-; ZIP-NEXT: vmsne.vi v8, v10, 0
-; ZIP-NEXT: vmsne.vi v0, v14, 0
-; ZIP-NEXT: srli a0, a0, 2
-; ZIP-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; ZIP-NEXT: vslideup.vx v0, v8, a0
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv32i1_nxv16i1:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
@@ -110,15 +90,6 @@ define <vscale x 32 x i8> @vector_interleave_nxv32i8_nxv16i8(<vscale x 16 x i8>
; ZVBB-NEXT: vwaddu.wv v8, v8, v14
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv32i8_nxv16i8:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; ZIP-NEXT: vmv2r.v v12, v10
-; ZIP-NEXT: vmv2r.v v14, v8
-; ZIP-NEXT: ri.vzip2b.vv v10, v8, v12
-; ZIP-NEXT: ri.vzip2a.vv v8, v14, v12
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv32i8_nxv16i8:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
@@ -150,15 +121,6 @@ define <vscale x 16 x i16> @vector_interleave_nxv16i16_nxv8i16(<vscale x 8 x i16
; ZVBB-NEXT: vwaddu.wv v8, v8, v14
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv16i16_nxv8i16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; ZIP-NEXT: vmv2r.v v12, v10
-; ZIP-NEXT: vmv2r.v v14, v8
-; ZIP-NEXT: ri.vzip2b.vv v10, v8, v12
-; ZIP-NEXT: ri.vzip2a.vv v8, v14, v12
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv16i16_nxv8i16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
@@ -191,15 +153,6 @@ define <vscale x 8 x i32> @vector_interleave_nxv8i32_nxv4i32(<vscale x 4 x i32>
; ZVBB-NEXT: vwaddu.wv v8, v8, v14
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv8i32_nxv4i32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; ZIP-NEXT: vmv2r.v v12, v10
-; ZIP-NEXT: vmv2r.v v14, v8
-; ZIP-NEXT: ri.vzip2b.vv v10, v8, v12
-; ZIP-NEXT: ri.vzip2a.vv v8, v14, v12
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv8i32_nxv4i32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e32, m2, ta, ma
@@ -242,15 +195,6 @@ define <vscale x 4 x i64> @vector_interleave_nxv4i64_nxv2i64(<vscale x 2 x i64>
; ZVBB-NEXT: vmv.v.v v8, v12
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv4i64_nxv2i64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e64, m2, ta, ma
-; ZIP-NEXT: vmv2r.v v12, v10
-; ZIP-NEXT: vmv2r.v v14, v8
-; ZIP-NEXT: ri.vzip2b.vv v10, v8, v12
-; ZIP-NEXT: ri.vzip2a.vv v8, v14, v12
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv4i64_nxv2i64:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e64, m2, ta, ma
@@ -303,26 +247,6 @@ define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv64i1(<vscale x 64 x i1
; ZVBB-NEXT: vmv1r.v v0, v16
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv128i1_nxv64i1:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; ZIP-NEXT: vmv1r.v v9, v0
-; ZIP-NEXT: vmv1r.v v0, v8
-; ZIP-NEXT: vmv.v.i v24, 0
-; ZIP-NEXT: vmerge.vim v16, v24, 1, v0
-; ZIP-NEXT: vmv1r.v v0, v9
-; ZIP-NEXT: vmerge.vim v8, v24, 1, v0
-; ZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; ZIP-NEXT: ri.vzip2b.vv v4, v8, v16
-; ZIP-NEXT: ri.vzip2b.vv v28, v12, v20
-; ZIP-NEXT: ri.vzip2a.vv v0, v8, v16
-; ZIP-NEXT: ri.vzip2a.vv v24, v12, v20
-; ZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; ZIP-NEXT: vmsne.vi v9, v0, 0
-; ZIP-NEXT: vmsne.vi v8, v24, 0
-; ZIP-NEXT: vmv1r.v v0, v9
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv128i1_nxv64i1:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
@@ -368,17 +292,6 @@ define <vscale x 128 x i8> @vector_interleave_nxv128i8_nxv64i8(<vscale x 64 x i8
; ZVBB-NEXT: vmv8r.v v16, v0
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv128i8_nxv64i8:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; ZIP-NEXT: ri.vzip2b.vv v28, v8, v16
-; ZIP-NEXT: ri.vzip2b.vv v4, v12, v20
-; ZIP-NEXT: ri.vzip2a.vv v24, v8, v16
-; ZIP-NEXT: ri.vzip2a.vv v0, v12, v20
-; ZIP-NEXT: vmv8r.v v8, v24
-; ZIP-NEXT: vmv8r.v v16, v0
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv128i8_nxv64i8:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
@@ -415,17 +328,6 @@ define <vscale x 64 x i16> @vector_interleave_nxv64i16_nxv32i16(<vscale x 32 x i
; ZVBB-NEXT: vmv8r.v v16, v0
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv64i16_nxv32i16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZIP-NEXT: ri.vzip2b.vv v28, v8, v16
-; ZIP-NEXT: ri.vzip2b.vv v4, v12, v20
-; ZIP-NEXT: ri.vzip2a.vv v24, v8, v16
-; ZIP-NEXT: ri.vzip2a.vv v0, v12, v20
-; ZIP-NEXT: vmv8r.v v8, v24
-; ZIP-NEXT: vmv8r.v v16, v0
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv64i16_nxv32i16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
@@ -463,17 +365,6 @@ define <vscale x 32 x i32> @vector_interleave_nxv32i32_nxv16i32(<vscale x 16 x i
; ZVBB-NEXT: vmv8r.v v16, v0
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv32i32_nxv16i32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; ZIP-NEXT: ri.vzip2b.vv v28, v8, v16
-; ZIP-NEXT: ri.vzip2b.vv v4, v12, v20
-; ZIP-NEXT: ri.vzip2a.vv v24, v8, v16
-; ZIP-NEXT: ri.vzip2a.vv v0, v12, v20
-; ZIP-NEXT: vmv8r.v v8, v24
-; ZIP-NEXT: vmv8r.v v16, v0
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv32i32_nxv16i32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e32, m4, ta, ma
@@ -525,17 +416,6 @@ define <vscale x 16 x i64> @vector_interleave_nxv16i64_nxv8i64(<vscale x 8 x i64
; ZVBB-NEXT: vmv.v.v v16, v24
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv16i64_nxv8i64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; ZIP-NEXT: ri.vzip2b.vv v28, v8, v16
-; ZIP-NEXT: ri.vzip2b.vv v4, v12, v20
-; ZIP-NEXT: ri.vzip2a.vv v24, v8, v16
-; ZIP-NEXT: ri.vzip2a.vv v0, v12, v20
-; ZIP-NEXT: vmv8r.v v8, v24
-; ZIP-NEXT: vmv8r.v v16, v0
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv16i64_nxv8i64:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e64, m4, ta, ma
@@ -1606,72 +1486,6 @@ define <vscale x 80 x i8> @vector_interleave_nxv80i8_nxv16i8(<vscale x 16 x i8>
; ZVBB-RV64-NEXT: addi sp, sp, 80
; ZVBB-RV64-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv80i8_nxv16i8:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 28
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v20, v16
-; ZIP-NEXT: addi a0, sp, 64
-; ZIP-NEXT: vmv2r.v v18, v12
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a2, a1, 2
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: vmv2r.v v16, v8
-; ZIP-NEXT: vmv2r.v v22, v16
-; ZIP-NEXT: vmv2r.v v24, v18
-; ZIP-NEXT: vmv1r.v v26, v20
-; ZIP-NEXT: add a3, a0, a2
-; ZIP-NEXT: vmv1r.v v23, v10
-; ZIP-NEXT: add a4, a1, a2
-; ZIP-NEXT: add a5, a4, a2
-; ZIP-NEXT: vmv1r.v v25, v14
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vmv1r.v v18, v11
-; ZIP-NEXT: vsseg5e8.v v22, (a0)
-; ZIP-NEXT: vmv1r.v v20, v15
-; ZIP-NEXT: vsseg5e8.v v17, (a1)
-; ZIP-NEXT: vl1r.v v16, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1r.v v17, (a6)
-; ZIP-NEXT: add a6, a3, a2
-; ZIP-NEXT: vl1r.v v10, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1r.v v11, (a6)
-; ZIP-NEXT: vl1r.v v8, (a0)
-; ZIP-NEXT: vl1r.v v9, (a3)
-; ZIP-NEXT: vl1r.v v14, (a4)
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a3, 10
-; ZIP-NEXT: mul a0, a0, a3
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1r.v v15, (a5)
-; ZIP-NEXT: vl1r.v v12, (a6)
-; ZIP-NEXT: vl1r.v v13, (a1)
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: add a2, a0, a2
-; ZIP-NEXT: vs2r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a0)
-; ZIP-NEXT: vl8r.v v16, (a2)
-; ZIP-NEXT: vl8r.v v8, (a0)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv80i8_nxv16i8:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -80
@@ -2067,72 +1881,6 @@ define <vscale x 20 x i32> @vector_interleave_nxv20i32_nxv4i32(<vscale x 4 x i32
; ZVBB-RV64-NEXT: addi sp, sp, 80
; ZVBB-RV64-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv20i32_nxv4i32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 28
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v20, v16
-; ZIP-NEXT: addi a0, sp, 64
-; ZIP-NEXT: vmv2r.v v18, v12
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a2, a1, 2
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: vmv2r.v v16, v8
-; ZIP-NEXT: vmv2r.v v22, v16
-; ZIP-NEXT: vmv2r.v v24, v18
-; ZIP-NEXT: vmv1r.v v26, v20
-; ZIP-NEXT: add a3, a0, a2
-; ZIP-NEXT: vmv1r.v v23, v10
-; ZIP-NEXT: add a4, a1, a2
-; ZIP-NEXT: add a5, a4, a2
-; ZIP-NEXT: vmv1r.v v25, v14
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vmv1r.v v18, v11
-; ZIP-NEXT: vsseg5e32.v v22, (a0)
-; ZIP-NEXT: vmv1r.v v20, v15
-; ZIP-NEXT: vsseg5e32.v v17, (a1)
-; ZIP-NEXT: vl1re32.v v16, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re32.v v17, (a6)
-; ZIP-NEXT: add a6, a3, a2
-; ZIP-NEXT: vl1re32.v v10, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re32.v v11, (a6)
-; ZIP-NEXT: vl1re32.v v8, (a0)
-; ZIP-NEXT: vl1re32.v v9, (a3)
-; ZIP-NEXT: vl1re32.v v14, (a4)
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a3, 10
-; ZIP-NEXT: mul a0, a0, a3
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re32.v v15, (a5)
-; ZIP-NEXT: vl1re32.v v12, (a6)
-; ZIP-NEXT: vl1re32.v v13, (a1)
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: add a2, a0, a2
-; ZIP-NEXT: vs2r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a0)
-; ZIP-NEXT: vl8re32.v v16, (a2)
-; ZIP-NEXT: vl8re32.v v8, (a0)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv20i32_nxv4i32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -80
@@ -2469,72 +2217,6 @@ define <vscale x 10 x i64> @vector_interleave_nxv10i64_nxv2i64(<vscale x 2 x i64
; ZVBB-RV64-NEXT: addi sp, sp, 80
; ZVBB-RV64-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv10i64_nxv2i64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 28
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e64, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v20, v16
-; ZIP-NEXT: addi a0, sp, 64
-; ZIP-NEXT: vmv2r.v v18, v12
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a2, a1, 2
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: vmv2r.v v16, v8
-; ZIP-NEXT: vmv2r.v v22, v16
-; ZIP-NEXT: vmv2r.v v24, v18
-; ZIP-NEXT: vmv1r.v v26, v20
-; ZIP-NEXT: add a3, a0, a2
-; ZIP-NEXT: vmv1r.v v23, v10
-; ZIP-NEXT: add a4, a1, a2
-; ZIP-NEXT: add a5, a4, a2
-; ZIP-NEXT: vmv1r.v v25, v14
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vmv1r.v v18, v11
-; ZIP-NEXT: vsseg5e64.v v22, (a0)
-; ZIP-NEXT: vmv1r.v v20, v15
-; ZIP-NEXT: vsseg5e64.v v17, (a1)
-; ZIP-NEXT: vl1re64.v v16, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re64.v v17, (a6)
-; ZIP-NEXT: add a6, a3, a2
-; ZIP-NEXT: vl1re64.v v10, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re64.v v11, (a6)
-; ZIP-NEXT: vl1re64.v v8, (a0)
-; ZIP-NEXT: vl1re64.v v9, (a3)
-; ZIP-NEXT: vl1re64.v v14, (a4)
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a3, 10
-; ZIP-NEXT: mul a0, a0, a3
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re64.v v15, (a5)
-; ZIP-NEXT: vl1re64.v v12, (a6)
-; ZIP-NEXT: vl1re64.v v13, (a1)
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: add a2, a0, a2
-; ZIP-NEXT: vs2r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a0)
-; ZIP-NEXT: vl8re64.v v16, (a2)
-; ZIP-NEXT: vl8re64.v v8, (a0)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv10i64_nxv2i64:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -80
@@ -3072,79 +2754,6 @@ define <vscale x 96 x i8> @vector_interleave_nxv96i8_nxv16i8(<vscale x 16 x i8>
; ZVBB-RV64-NEXT: addi sp, sp, 80
; ZVBB-RV64-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv96i8_nxv16i8:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 28
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v20, v14
-; ZIP-NEXT: vmv2r.v v22, v12
-; ZIP-NEXT: vmv2r.v v24, v10
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: li a0, 6
-; ZIP-NEXT: mul a1, a1, a0
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
-; ZIP-NEXT: vmv1r.v v10, v25
-; ZIP-NEXT: vmv1r.v v11, v23
-; ZIP-NEXT: vmv1r.v v12, v21
-; ZIP-NEXT: addi a0, sp, 64
-; ZIP-NEXT: vmv1r.v v13, v17
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: vmv1r.v v14, v19
-; ZIP-NEXT: vsseg6e8.v v9, (a1)
-; ZIP-NEXT: vmv1r.v v9, v24
-; ZIP-NEXT: add a5, a1, a2
-; ZIP-NEXT: vmv1r.v v10, v22
-; ZIP-NEXT: add a3, a0, a2
-; ZIP-NEXT: vmv1r.v v11, v20
-; ZIP-NEXT: add a4, a3, a2
-; ZIP-NEXT: vmv1r.v v12, v16
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vmv1r.v v13, v18
-; ZIP-NEXT: vsseg6e8.v v8, (a0)
-; ZIP-NEXT: vl1r.v v14, (a1)
-; ZIP-NEXT: add a1, a6, a2
-; ZIP-NEXT: vl1r.v v15, (a5)
-; ZIP-NEXT: add a5, a1, a2
-; ZIP-NEXT: vl1r.v v18, (a5)
-; ZIP-NEXT: add a5, a5, a2
-; ZIP-NEXT: vl1r.v v19, (a5)
-; ZIP-NEXT: add a5, a4, a2
-; ZIP-NEXT: vl1r.v v16, (a6)
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vl1r.v v12, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1r.v v13, (a6)
-; ZIP-NEXT: csrr a6, vlenb
-; ZIP-NEXT: li a7, 12
-; ZIP-NEXT: mul a6, a6, a7
-; ZIP-NEXT: add a6, sp, a6
-; ZIP-NEXT: addi a6, a6, 64
-; ZIP-NEXT: vl1r.v v17, (a1)
-; ZIP-NEXT: vl1r.v v10, (a4)
-; ZIP-NEXT: vl1r.v v11, (a5)
-; ZIP-NEXT: vl1r.v v8, (a0)
-; ZIP-NEXT: vl1r.v v9, (a3)
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: add a2, a6, a2
-; ZIP-NEXT: vs4r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a6)
-; ZIP-NEXT: vl8r.v v16, (a2)
-; ZIP-NEXT: vl8r.v v8, (a6)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv96i8_nxv16i8:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -80
@@ -3577,79 +3186,6 @@ define <vscale x 24 x i32> @vector_interleave_nxv24i32_nxv4i32(<vscale x 4 x i32
; ZVBB-RV64-NEXT: addi sp, sp, 80
; ZVBB-RV64-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv24i32_nxv4i32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 28
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v20, v14
-; ZIP-NEXT: vmv2r.v v22, v12
-; ZIP-NEXT: vmv2r.v v24, v10
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: li a0, 6
-; ZIP-NEXT: mul a1, a1, a0
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
-; ZIP-NEXT: vmv1r.v v10, v25
-; ZIP-NEXT: vmv1r.v v11, v23
-; ZIP-NEXT: vmv1r.v v12, v21
-; ZIP-NEXT: addi a0, sp, 64
-; ZIP-NEXT: vmv1r.v v13, v17
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: vmv1r.v v14, v19
-; ZIP-NEXT: vsseg6e32.v v9, (a1)
-; ZIP-NEXT: vmv1r.v v9, v24
-; ZIP-NEXT: add a5, a1, a2
-; ZIP-NEXT: vmv1r.v v10, v22
-; ZIP-NEXT: add a3, a0, a2
-; ZIP-NEXT: vmv1r.v v11, v20
-; ZIP-NEXT: add a4, a3, a2
-; ZIP-NEXT: vmv1r.v v12, v16
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vmv1r.v v13, v18
-; ZIP-NEXT: vsseg6e32.v v8, (a0)
-; ZIP-NEXT: vl1re32.v v14, (a1)
-; ZIP-NEXT: add a1, a6, a2
-; ZIP-NEXT: vl1re32.v v15, (a5)
-; ZIP-NEXT: add a5, a1, a2
-; ZIP-NEXT: vl1re32.v v18, (a5)
-; ZIP-NEXT: add a5, a5, a2
-; ZIP-NEXT: vl1re32.v v19, (a5)
-; ZIP-NEXT: add a5, a4, a2
-; ZIP-NEXT: vl1re32.v v16, (a6)
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vl1re32.v v12, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re32.v v13, (a6)
-; ZIP-NEXT: csrr a6, vlenb
-; ZIP-NEXT: li a7, 12
-; ZIP-NEXT: mul a6, a6, a7
-; ZIP-NEXT: add a6, sp, a6
-; ZIP-NEXT: addi a6, a6, 64
-; ZIP-NEXT: vl1re32.v v17, (a1)
-; ZIP-NEXT: vl1re32.v v10, (a4)
-; ZIP-NEXT: vl1re32.v v11, (a5)
-; ZIP-NEXT: vl1re32.v v8, (a0)
-; ZIP-NEXT: vl1re32.v v9, (a3)
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: add a2, a6, a2
-; ZIP-NEXT: vs4r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a6)
-; ZIP-NEXT: vl8re32.v v16, (a2)
-; ZIP-NEXT: vl8re32.v v8, (a6)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv24i32_nxv4i32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -80
@@ -4020,79 +3556,6 @@ define <vscale x 12 x i64> @vector_interleave_nxv12i64_nxv2i64(<vscale x 2 x i64
; ZVBB-RV64-NEXT: addi sp, sp, 80
; ZVBB-RV64-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv12i64_nxv2i64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 28
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e64, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v20, v14
-; ZIP-NEXT: vmv2r.v v22, v12
-; ZIP-NEXT: vmv2r.v v24, v10
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: li a0, 6
-; ZIP-NEXT: mul a1, a1, a0
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
-; ZIP-NEXT: vmv1r.v v10, v25
-; ZIP-NEXT: vmv1r.v v11, v23
-; ZIP-NEXT: vmv1r.v v12, v21
-; ZIP-NEXT: addi a0, sp, 64
-; ZIP-NEXT: vmv1r.v v13, v17
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: vmv1r.v v14, v19
-; ZIP-NEXT: vsseg6e64.v v9, (a1)
-; ZIP-NEXT: vmv1r.v v9, v24
-; ZIP-NEXT: add a5, a1, a2
-; ZIP-NEXT: vmv1r.v v10, v22
-; ZIP-NEXT: add a3, a0, a2
-; ZIP-NEXT: vmv1r.v v11, v20
-; ZIP-NEXT: add a4, a3, a2
-; ZIP-NEXT: vmv1r.v v12, v16
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vmv1r.v v13, v18
-; ZIP-NEXT: vsseg6e64.v v8, (a0)
-; ZIP-NEXT: vl1re64.v v14, (a1)
-; ZIP-NEXT: add a1, a6, a2
-; ZIP-NEXT: vl1re64.v v15, (a5)
-; ZIP-NEXT: add a5, a1, a2
-; ZIP-NEXT: vl1re64.v v18, (a5)
-; ZIP-NEXT: add a5, a5, a2
-; ZIP-NEXT: vl1re64.v v19, (a5)
-; ZIP-NEXT: add a5, a4, a2
-; ZIP-NEXT: vl1re64.v v16, (a6)
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vl1re64.v v12, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re64.v v13, (a6)
-; ZIP-NEXT: csrr a6, vlenb
-; ZIP-NEXT: li a7, 12
-; ZIP-NEXT: mul a6, a6, a7
-; ZIP-NEXT: add a6, sp, a6
-; ZIP-NEXT: addi a6, a6, 64
-; ZIP-NEXT: vl1re64.v v17, (a1)
-; ZIP-NEXT: vl1re64.v v10, (a4)
-; ZIP-NEXT: vl1re64.v v11, (a5)
-; ZIP-NEXT: vl1re64.v v8, (a0)
-; ZIP-NEXT: vl1re64.v v9, (a3)
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: add a2, a6, a2
-; ZIP-NEXT: vs4r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a6)
-; ZIP-NEXT: vl8re64.v v16, (a2)
-; ZIP-NEXT: vl8re64.v v8, (a6)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv12i64_nxv2i64:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -80
@@ -4684,87 +4147,6 @@ define <vscale x 112 x i8> @vector_interleave_nxv112i8_nxv16i8(<vscale x 16 x i8
; ZVBB-RV64-NEXT: addi sp, sp, 80
; ZVBB-RV64-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv112i8_nxv16i8:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 5
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v26, v20
-; ZIP-NEXT: addi a0, sp, 64
-; ZIP-NEXT: vmv2r.v v24, v16
-; ZIP-NEXT: vmv2r.v v22, v12
-; ZIP-NEXT: vmv2r.v v20, v8
-; ZIP-NEXT: vmv1r.v v1, v20
-; ZIP-NEXT: vmv1r.v v3, v22
-; ZIP-NEXT: vmv1r.v v5, v24
-; ZIP-NEXT: vmv1r.v v7, v26
-; ZIP-NEXT: vmv1r.v v2, v10
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a2, a1, 3
-; ZIP-NEXT: sub a1, a2, a1
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: vmv1r.v v4, v14
-; ZIP-NEXT: add a3, a0, a2
-; ZIP-NEXT: add a4, a1, a2
-; ZIP-NEXT: vmv1r.v v6, v18
-; ZIP-NEXT: add a5, a4, a2
-; ZIP-NEXT: vmv1r.v v22, v11
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vmv1r.v v24, v15
-; ZIP-NEXT: vsseg7e8.v v1, (a0)
-; ZIP-NEXT: vmv1r.v v26, v19
-; ZIP-NEXT: vsseg7e8.v v21, (a1)
-; ZIP-NEXT: vl1r.v v18, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1r.v v19, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1r.v v20, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1r.v v21, (a6)
-; ZIP-NEXT: add a6, a3, a2
-; ZIP-NEXT: vl1r.v v10, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1r.v v11, (a6)
-; ZIP-NEXT: vl1r.v v8, (a0)
-; ZIP-NEXT: vl1r.v v16, (a4)
-; ZIP-NEXT: vl1r.v v9, (a3)
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a3, 14
-; ZIP-NEXT: mul a0, a0, a3
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: vl1r.v v17, (a5)
-; ZIP-NEXT: slli a3, a2, 2
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1r.v v12, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1r.v v13, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: add a3, a2, a3
-; ZIP-NEXT: add a2, a0, a2
-; ZIP-NEXT: vl1r.v v14, (a6)
-; ZIP-NEXT: vl1r.v v15, (a1)
-; ZIP-NEXT: add a3, a0, a3
-; ZIP-NEXT: vs2r.v v20, (a3)
-; ZIP-NEXT: vs4r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a0)
-; ZIP-NEXT: vl8r.v v16, (a2)
-; ZIP-NEXT: vl8r.v v8, (a0)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv112i8_nxv16i8:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -80
@@ -5176,87 +4558,6 @@ define <vscale x 56 x i16> @vector_interleave_nxv56i16_nxv8i16(<vscale x 8 x i16
; ZVBB-RV64-NEXT: addi sp, sp, 80
; ZVBB-RV64-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv56i16_nxv8i16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 5
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v26, v20
-; ZIP-NEXT: addi a0, sp, 64
-; ZIP-NEXT: vmv2r.v v24, v16
-; ZIP-NEXT: vmv2r.v v22, v12
-; ZIP-NEXT: vmv2r.v v20, v8
-; ZIP-NEXT: vmv1r.v v1, v20
-; ZIP-NEXT: vmv1r.v v3, v22
-; ZIP-NEXT: vmv1r.v v5, v24
-; ZIP-NEXT: vmv1r.v v7, v26
-; ZIP-NEXT: vmv1r.v v2, v10
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a2, a1, 3
-; ZIP-NEXT: sub a1, a2, a1
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: vmv1r.v v4, v14
-; ZIP-NEXT: add a3, a0, a2
-; ZIP-NEXT: add a4, a1, a2
-; ZIP-NEXT: vmv1r.v v6, v18
-; ZIP-NEXT: add a5, a4, a2
-; ZIP-NEXT: vmv1r.v v22, v11
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vmv1r.v v24, v15
-; ZIP-NEXT: vsseg7e16.v v1, (a0)
-; ZIP-NEXT: vmv1r.v v26, v19
-; ZIP-NEXT: vsseg7e16.v v21, (a1)
-; ZIP-NEXT: vl1re16.v v18, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re16.v v19, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re16.v v20, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re16.v v21, (a6)
-; ZIP-NEXT: add a6, a3, a2
-; ZIP-NEXT: vl1re16.v v10, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re16.v v11, (a6)
-; ZIP-NEXT: vl1re16.v v8, (a0)
-; ZIP-NEXT: vl1re16.v v16, (a4)
-; ZIP-NEXT: vl1re16.v v9, (a3)
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a3, 14
-; ZIP-NEXT: mul a0, a0, a3
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: vl1re16.v v17, (a5)
-; ZIP-NEXT: slli a3, a2, 2
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re16.v v12, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re16.v v13, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: add a3, a2, a3
-; ZIP-NEXT: add a2, a0, a2
-; ZIP-NEXT: vl1re16.v v14, (a6)
-; ZIP-NEXT: vl1re16.v v15, (a1)
-; ZIP-NEXT: add a3, a0, a3
-; ZIP-NEXT: vs2r.v v20, (a3)
-; ZIP-NEXT: vs4r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a0)
-; ZIP-NEXT: vl8re16.v v16, (a2)
-; ZIP-NEXT: vl8re16.v v8, (a0)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv56i16_nxv8i16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -80
@@ -5668,87 +4969,6 @@ define <vscale x 28 x i32> @vector_interleave_nxv28i32_nxv4i32(<vscale x 4 x i32
; ZVBB-RV64-NEXT: addi sp, sp, 80
; ZVBB-RV64-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv28i32_nxv4i32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 5
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v26, v20
-; ZIP-NEXT: addi a0, sp, 64
-; ZIP-NEXT: vmv2r.v v24, v16
-; ZIP-NEXT: vmv2r.v v22, v12
-; ZIP-NEXT: vmv2r.v v20, v8
-; ZIP-NEXT: vmv1r.v v1, v20
-; ZIP-NEXT: vmv1r.v v3, v22
-; ZIP-NEXT: vmv1r.v v5, v24
-; ZIP-NEXT: vmv1r.v v7, v26
-; ZIP-NEXT: vmv1r.v v2, v10
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a2, a1, 3
-; ZIP-NEXT: sub a1, a2, a1
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: vmv1r.v v4, v14
-; ZIP-NEXT: add a3, a0, a2
-; ZIP-NEXT: add a4, a1, a2
-; ZIP-NEXT: vmv1r.v v6, v18
-; ZIP-NEXT: add a5, a4, a2
-; ZIP-NEXT: vmv1r.v v22, v11
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vmv1r.v v24, v15
-; ZIP-NEXT: vsseg7e32.v v1, (a0)
-; ZIP-NEXT: vmv1r.v v26, v19
-; ZIP-NEXT: vsseg7e32.v v21, (a1)
-; ZIP-NEXT: vl1re32.v v18, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re32.v v19, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re32.v v20, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re32.v v21, (a6)
-; ZIP-NEXT: add a6, a3, a2
-; ZIP-NEXT: vl1re32.v v10, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re32.v v11, (a6)
-; ZIP-NEXT: vl1re32.v v8, (a0)
-; ZIP-NEXT: vl1re32.v v16, (a4)
-; ZIP-NEXT: vl1re32.v v9, (a3)
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a3, 14
-; ZIP-NEXT: mul a0, a0, a3
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: vl1re32.v v17, (a5)
-; ZIP-NEXT: slli a3, a2, 2
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re32.v v12, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re32.v v13, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: add a3, a2, a3
-; ZIP-NEXT: add a2, a0, a2
-; ZIP-NEXT: vl1re32.v v14, (a6)
-; ZIP-NEXT: vl1re32.v v15, (a1)
-; ZIP-NEXT: add a3, a0, a3
-; ZIP-NEXT: vs2r.v v20, (a3)
-; ZIP-NEXT: vs4r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a0)
-; ZIP-NEXT: vl8re32.v v16, (a2)
-; ZIP-NEXT: vl8re32.v v8, (a0)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv28i32_nxv4i32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -80
@@ -6159,87 +5379,6 @@ define <vscale x 14 x i64> @vector_interleave_nxv14i64_nxv2i64(<vscale x 2 x i64
; ZVBB-RV64-NEXT: addi sp, sp, 80
; ZVBB-RV64-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv14i64_nxv2i64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 5
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e64, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v26, v20
-; ZIP-NEXT: addi a0, sp, 64
-; ZIP-NEXT: vmv2r.v v24, v16
-; ZIP-NEXT: vmv2r.v v22, v12
-; ZIP-NEXT: vmv2r.v v20, v8
-; ZIP-NEXT: vmv1r.v v1, v20
-; ZIP-NEXT: vmv1r.v v3, v22
-; ZIP-NEXT: vmv1r.v v5, v24
-; ZIP-NEXT: vmv1r.v v7, v26
-; ZIP-NEXT: vmv1r.v v2, v10
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a2, a1, 3
-; ZIP-NEXT: sub a1, a2, a1
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: vmv1r.v v4, v14
-; ZIP-NEXT: add a3, a0, a2
-; ZIP-NEXT: add a4, a1, a2
-; ZIP-NEXT: vmv1r.v v6, v18
-; ZIP-NEXT: add a5, a4, a2
-; ZIP-NEXT: vmv1r.v v22, v11
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vmv1r.v v24, v15
-; ZIP-NEXT: vsseg7e64.v v1, (a0)
-; ZIP-NEXT: vmv1r.v v26, v19
-; ZIP-NEXT: vsseg7e64.v v21, (a1)
-; ZIP-NEXT: vl1re64.v v18, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re64.v v19, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re64.v v20, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re64.v v21, (a6)
-; ZIP-NEXT: add a6, a3, a2
-; ZIP-NEXT: vl1re64.v v10, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re64.v v11, (a6)
-; ZIP-NEXT: vl1re64.v v8, (a0)
-; ZIP-NEXT: vl1re64.v v16, (a4)
-; ZIP-NEXT: vl1re64.v v9, (a3)
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a3, 14
-; ZIP-NEXT: mul a0, a0, a3
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: vl1re64.v v17, (a5)
-; ZIP-NEXT: slli a3, a2, 2
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re64.v v12, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re64.v v13, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: add a3, a2, a3
-; ZIP-NEXT: add a2, a0, a2
-; ZIP-NEXT: vl1re64.v v14, (a6)
-; ZIP-NEXT: vl1re64.v v15, (a1)
-; ZIP-NEXT: add a3, a0, a3
-; ZIP-NEXT: vs2r.v v20, (a3)
-; ZIP-NEXT: vs4r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a0)
-; ZIP-NEXT: vl8re64.v v16, (a2)
-; ZIP-NEXT: vl8re64.v v8, (a0)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv14i64_nxv2i64:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -80
@@ -7115,18 +6254,6 @@ define <vscale x 4 x bfloat> @vector_interleave_nxv4bf16_nxv2bf16(<vscale x 2 x
; ZVBB-NEXT: vmv.v.v v8, v10
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv4bf16_nxv2bf16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; ZIP-NEXT: ri.vzip2b.vv v11, v8, v9
-; ZIP-NEXT: ri.vzip2a.vv v10, v8, v9
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: srli a0, a0, 2
-; ZIP-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; ZIP-NEXT: vslideup.vx v10, v11, a0
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv4bf16_nxv2bf16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
@@ -7162,15 +6289,6 @@ define <vscale x 8 x bfloat> @vector_interleave_nxv8bf16_nxv4bf16(<vscale x 4 x
; ZVBB-NEXT: vwaddu.wv v8, v8, v11
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv8bf16_nxv4bf16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZIP-NEXT: vmv1r.v v10, v9
-; ZIP-NEXT: vmv1r.v v11, v8
-; ZIP-NEXT: ri.vzip2b.vv v9, v8, v10
-; ZIP-NEXT: ri.vzip2a.vv v8, v11, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv8bf16_nxv4bf16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
@@ -7210,18 +6328,6 @@ define <vscale x 4 x half> @vector_interleave_nxv4f16_nxv2f16(<vscale x 2 x half
; ZVBB-NEXT: vmv.v.v v8, v10
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv4f16_nxv2f16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; ZIP-NEXT: ri.vzip2b.vv v11, v8, v9
-; ZIP-NEXT: ri.vzip2a.vv v10, v8, v9
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: srli a0, a0, 2
-; ZIP-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; ZIP-NEXT: vslideup.vx v10, v11, a0
-; ZIP-NEXT: vmv.v.v v8, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv4f16_nxv2f16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
@@ -7257,15 +6363,6 @@ define <vscale x 8 x half> @vector_interleave_nxv8f16_nxv4f16(<vscale x 4 x half
; ZVBB-NEXT: vwaddu.wv v8, v8, v11
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv8f16_nxv4f16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZIP-NEXT: vmv1r.v v10, v9
-; ZIP-NEXT: vmv1r.v v11, v8
-; ZIP-NEXT: ri.vzip2b.vv v9, v8, v10
-; ZIP-NEXT: ri.vzip2a.vv v8, v11, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv8f16_nxv4f16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
@@ -7298,15 +6395,6 @@ define <vscale x 4 x float> @vector_interleave_nxv4f32_nxv2f32(<vscale x 2 x flo
; ZVBB-NEXT: vwaddu.wv v8, v8, v11
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv4f32_nxv2f32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; ZIP-NEXT: vmv1r.v v10, v9
-; ZIP-NEXT: vmv1r.v v11, v8
-; ZIP-NEXT: ri.vzip2b.vv v9, v8, v10
-; ZIP-NEXT: ri.vzip2a.vv v8, v11, v10
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv4f32_nxv2f32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
@@ -7338,15 +6426,6 @@ define <vscale x 16 x bfloat> @vector_interleave_nxv16bf16_nxv8bf16(<vscale x 8
; ZVBB-NEXT: vwaddu.wv v8, v8, v14
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv16bf16_nxv8bf16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; ZIP-NEXT: vmv2r.v v12, v10
-; ZIP-NEXT: vmv2r.v v14, v8
-; ZIP-NEXT: ri.vzip2b.vv v10, v8, v12
-; ZIP-NEXT: ri.vzip2a.vv v8, v14, v12
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv16bf16_nxv8bf16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
@@ -7378,15 +6457,6 @@ define <vscale x 16 x half> @vector_interleave_nxv16f16_nxv8f16(<vscale x 8 x ha
; ZVBB-NEXT: vwaddu.wv v8, v8, v14
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv16f16_nxv8f16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; ZIP-NEXT: vmv2r.v v12, v10
-; ZIP-NEXT: vmv2r.v v14, v8
-; ZIP-NEXT: ri.vzip2b.vv v10, v8, v12
-; ZIP-NEXT: ri.vzip2a.vv v8, v14, v12
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv16f16_nxv8f16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
@@ -7419,15 +6489,6 @@ define <vscale x 8 x float> @vector_interleave_nxv8f32_nxv4f32(<vscale x 4 x flo
; ZVBB-NEXT: vwaddu.wv v8, v8, v14
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv8f32_nxv4f32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; ZIP-NEXT: vmv2r.v v12, v10
-; ZIP-NEXT: vmv2r.v v14, v8
-; ZIP-NEXT: ri.vzip2b.vv v10, v8, v12
-; ZIP-NEXT: ri.vzip2a.vv v8, v14, v12
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv8f32_nxv4f32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e32, m2, ta, ma
@@ -7470,15 +6531,6 @@ define <vscale x 4 x double> @vector_interleave_nxv4f64_nxv2f64(<vscale x 2 x do
; ZVBB-NEXT: vmv.v.v v8, v12
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv4f64_nxv2f64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e64, m2, ta, ma
-; ZIP-NEXT: vmv2r.v v12, v10
-; ZIP-NEXT: vmv2r.v v14, v8
-; ZIP-NEXT: ri.vzip2b.vv v10, v8, v12
-; ZIP-NEXT: ri.vzip2a.vv v8, v14, v12
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv4f64_nxv2f64:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e64, m2, ta, ma
@@ -7516,17 +6568,6 @@ define <vscale x 64 x bfloat> @vector_interleave_nxv64bf16_nxv32bf16(<vscale x 3
; ZVBB-NEXT: vmv8r.v v16, v0
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv64bf16_nxv32bf16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZIP-NEXT: ri.vzip2b.vv v28, v8, v16
-; ZIP-NEXT: ri.vzip2b.vv v4, v12, v20
-; ZIP-NEXT: ri.vzip2a.vv v24, v8, v16
-; ZIP-NEXT: ri.vzip2a.vv v0, v12, v20
-; ZIP-NEXT: vmv8r.v v8, v24
-; ZIP-NEXT: vmv8r.v v16, v0
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv64bf16_nxv32bf16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
@@ -7563,17 +6604,6 @@ define <vscale x 64 x half> @vector_interleave_nxv64f16_nxv32f16(<vscale x 32 x
; ZVBB-NEXT: vmv8r.v v16, v0
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv64f16_nxv32f16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZIP-NEXT: ri.vzip2b.vv v28, v8, v16
-; ZIP-NEXT: ri.vzip2b.vv v4, v12, v20
-; ZIP-NEXT: ri.vzip2a.vv v24, v8, v16
-; ZIP-NEXT: ri.vzip2a.vv v0, v12, v20
-; ZIP-NEXT: vmv8r.v v8, v24
-; ZIP-NEXT: vmv8r.v v16, v0
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv64f16_nxv32f16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
@@ -7611,17 +6641,6 @@ define <vscale x 32 x float> @vector_interleave_nxv32f32_nxv16f32(<vscale x 16 x
; ZVBB-NEXT: vmv8r.v v16, v0
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv32f32_nxv16f32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; ZIP-NEXT: ri.vzip2b.vv v28, v8, v16
-; ZIP-NEXT: ri.vzip2b.vv v4, v12, v20
-; ZIP-NEXT: ri.vzip2a.vv v24, v8, v16
-; ZIP-NEXT: ri.vzip2a.vv v0, v12, v20
-; ZIP-NEXT: vmv8r.v v8, v24
-; ZIP-NEXT: vmv8r.v v16, v0
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv32f32_nxv16f32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e32, m4, ta, ma
@@ -7673,17 +6692,6 @@ define <vscale x 16 x double> @vector_interleave_nxv16f64_nxv8f64(<vscale x 8 x
; ZVBB-NEXT: vmv.v.v v16, v24
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv16f64_nxv8f64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; ZIP-NEXT: ri.vzip2b.vv v28, v8, v16
-; ZIP-NEXT: ri.vzip2b.vv v4, v12, v20
-; ZIP-NEXT: ri.vzip2a.vv v24, v8, v16
-; ZIP-NEXT: ri.vzip2a.vv v0, v12, v20
-; ZIP-NEXT: vmv8r.v v8, v24
-; ZIP-NEXT: vmv8r.v v16, v0
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv16f64_nxv8f64:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e64, m4, ta, ma
@@ -9269,72 +8277,6 @@ define <vscale x 40 x half> @vector_interleave_nxv40f16_nxv8f16(<vscale x 8 x ha
; ZVBB-RV64-NEXT: addi sp, sp, 80
; ZVBB-RV64-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv40f16_nxv8f16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 28
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v20, v16
-; ZIP-NEXT: addi a0, sp, 64
-; ZIP-NEXT: vmv2r.v v18, v12
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a2, a1, 2
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: vmv2r.v v16, v8
-; ZIP-NEXT: vmv2r.v v22, v16
-; ZIP-NEXT: vmv2r.v v24, v18
-; ZIP-NEXT: vmv1r.v v26, v20
-; ZIP-NEXT: add a3, a0, a2
-; ZIP-NEXT: vmv1r.v v23, v10
-; ZIP-NEXT: add a4, a1, a2
-; ZIP-NEXT: add a5, a4, a2
-; ZIP-NEXT: vmv1r.v v25, v14
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vmv1r.v v18, v11
-; ZIP-NEXT: vsseg5e16.v v22, (a0)
-; ZIP-NEXT: vmv1r.v v20, v15
-; ZIP-NEXT: vsseg5e16.v v17, (a1)
-; ZIP-NEXT: vl1re16.v v16, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re16.v v17, (a6)
-; ZIP-NEXT: add a6, a3, a2
-; ZIP-NEXT: vl1re16.v v10, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re16.v v11, (a6)
-; ZIP-NEXT: vl1re16.v v8, (a0)
-; ZIP-NEXT: vl1re16.v v9, (a3)
-; ZIP-NEXT: vl1re16.v v14, (a4)
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a3, 10
-; ZIP-NEXT: mul a0, a0, a3
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re16.v v15, (a5)
-; ZIP-NEXT: vl1re16.v v12, (a6)
-; ZIP-NEXT: vl1re16.v v13, (a1)
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: add a2, a0, a2
-; ZIP-NEXT: vs2r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a0)
-; ZIP-NEXT: vl8re16.v v16, (a2)
-; ZIP-NEXT: vl8re16.v v8, (a0)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv40f16_nxv8f16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -80
@@ -9801,72 +8743,6 @@ define <vscale x 40 x bfloat> @vector_interleave_nxv40bf16_nxv8bf16(<vscale x 8
; ZVBB-RV64-NEXT: addi sp, sp, 80
; ZVBB-RV64-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv40bf16_nxv8bf16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 28
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v20, v16
-; ZIP-NEXT: addi a0, sp, 64
-; ZIP-NEXT: vmv2r.v v18, v12
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a2, a1, 2
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: vmv2r.v v16, v8
-; ZIP-NEXT: vmv2r.v v22, v16
-; ZIP-NEXT: vmv2r.v v24, v18
-; ZIP-NEXT: vmv1r.v v26, v20
-; ZIP-NEXT: add a3, a0, a2
-; ZIP-NEXT: vmv1r.v v23, v10
-; ZIP-NEXT: add a4, a1, a2
-; ZIP-NEXT: add a5, a4, a2
-; ZIP-NEXT: vmv1r.v v25, v14
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vmv1r.v v18, v11
-; ZIP-NEXT: vsseg5e16.v v22, (a0)
-; ZIP-NEXT: vmv1r.v v20, v15
-; ZIP-NEXT: vsseg5e16.v v17, (a1)
-; ZIP-NEXT: vl1re16.v v16, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re16.v v17, (a6)
-; ZIP-NEXT: add a6, a3, a2
-; ZIP-NEXT: vl1re16.v v10, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re16.v v11, (a6)
-; ZIP-NEXT: vl1re16.v v8, (a0)
-; ZIP-NEXT: vl1re16.v v9, (a3)
-; ZIP-NEXT: vl1re16.v v14, (a4)
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a3, 10
-; ZIP-NEXT: mul a0, a0, a3
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re16.v v15, (a5)
-; ZIP-NEXT: vl1re16.v v12, (a6)
-; ZIP-NEXT: vl1re16.v v13, (a1)
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: add a2, a0, a2
-; ZIP-NEXT: vs2r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a0)
-; ZIP-NEXT: vl8re16.v v16, (a2)
-; ZIP-NEXT: vl8re16.v v8, (a0)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv40bf16_nxv8bf16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -80
@@ -10333,72 +9209,6 @@ define <vscale x 20 x float> @vector_interleave_nxv20f32_nxv4f32(<vscale x 4 x f
; ZVBB-RV64-NEXT: addi sp, sp, 80
; ZVBB-RV64-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv20f32_nxv4f32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 28
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v20, v16
-; ZIP-NEXT: addi a0, sp, 64
-; ZIP-NEXT: vmv2r.v v18, v12
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a2, a1, 2
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: vmv2r.v v16, v8
-; ZIP-NEXT: vmv2r.v v22, v16
-; ZIP-NEXT: vmv2r.v v24, v18
-; ZIP-NEXT: vmv1r.v v26, v20
-; ZIP-NEXT: add a3, a0, a2
-; ZIP-NEXT: vmv1r.v v23, v10
-; ZIP-NEXT: add a4, a1, a2
-; ZIP-NEXT: add a5, a4, a2
-; ZIP-NEXT: vmv1r.v v25, v14
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vmv1r.v v18, v11
-; ZIP-NEXT: vsseg5e32.v v22, (a0)
-; ZIP-NEXT: vmv1r.v v20, v15
-; ZIP-NEXT: vsseg5e32.v v17, (a1)
-; ZIP-NEXT: vl1re32.v v16, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re32.v v17, (a6)
-; ZIP-NEXT: add a6, a3, a2
-; ZIP-NEXT: vl1re32.v v10, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re32.v v11, (a6)
-; ZIP-NEXT: vl1re32.v v8, (a0)
-; ZIP-NEXT: vl1re32.v v9, (a3)
-; ZIP-NEXT: vl1re32.v v14, (a4)
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a3, 10
-; ZIP-NEXT: mul a0, a0, a3
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re32.v v15, (a5)
-; ZIP-NEXT: vl1re32.v v12, (a6)
-; ZIP-NEXT: vl1re32.v v13, (a1)
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: add a2, a0, a2
-; ZIP-NEXT: vs2r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a0)
-; ZIP-NEXT: vl8re32.v v16, (a2)
-; ZIP-NEXT: vl8re32.v v8, (a0)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv20f32_nxv4f32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -80
@@ -10791,72 +9601,6 @@ define <vscale x 10 x double> @vector_interleave_nxv10f64_nxv2f64(<vscale x 2 x
; ZVBB-RV64-NEXT: addi sp, sp, 80
; ZVBB-RV64-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv10f64_nxv2f64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 28
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e64, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v20, v16
-; ZIP-NEXT: addi a0, sp, 64
-; ZIP-NEXT: vmv2r.v v18, v12
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a2, a1, 2
-; ZIP-NEXT: add a1, a2, a1
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: vmv2r.v v16, v8
-; ZIP-NEXT: vmv2r.v v22, v16
-; ZIP-NEXT: vmv2r.v v24, v18
-; ZIP-NEXT: vmv1r.v v26, v20
-; ZIP-NEXT: add a3, a0, a2
-; ZIP-NEXT: vmv1r.v v23, v10
-; ZIP-NEXT: add a4, a1, a2
-; ZIP-NEXT: add a5, a4, a2
-; ZIP-NEXT: vmv1r.v v25, v14
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vmv1r.v v18, v11
-; ZIP-NEXT: vsseg5e64.v v22, (a0)
-; ZIP-NEXT: vmv1r.v v20, v15
-; ZIP-NEXT: vsseg5e64.v v17, (a1)
-; ZIP-NEXT: vl1re64.v v16, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re64.v v17, (a6)
-; ZIP-NEXT: add a6, a3, a2
-; ZIP-NEXT: vl1re64.v v10, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re64.v v11, (a6)
-; ZIP-NEXT: vl1re64.v v8, (a0)
-; ZIP-NEXT: vl1re64.v v9, (a3)
-; ZIP-NEXT: vl1re64.v v14, (a4)
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a3, 10
-; ZIP-NEXT: mul a0, a0, a3
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re64.v v15, (a5)
-; ZIP-NEXT: vl1re64.v v12, (a6)
-; ZIP-NEXT: vl1re64.v v13, (a1)
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: add a2, a0, a2
-; ZIP-NEXT: vs2r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a0)
-; ZIP-NEXT: vl8re64.v v16, (a2)
-; ZIP-NEXT: vl8re64.v v8, (a0)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv10f64_nxv2f64:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -80
@@ -11363,79 +10107,6 @@ define <vscale x 48 x half> @vector_interleave_nxv48f16_nxv8f16(<vscale x 8 x ha
; ZVBB-RV64-NEXT: addi sp, sp, 80
; ZVBB-RV64-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv48f16_nxv8f16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 28
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v20, v14
-; ZIP-NEXT: vmv2r.v v22, v12
-; ZIP-NEXT: vmv2r.v v24, v10
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: li a0, 6
-; ZIP-NEXT: mul a1, a1, a0
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
-; ZIP-NEXT: vmv1r.v v10, v25
-; ZIP-NEXT: vmv1r.v v11, v23
-; ZIP-NEXT: vmv1r.v v12, v21
-; ZIP-NEXT: addi a0, sp, 64
-; ZIP-NEXT: vmv1r.v v13, v17
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: vmv1r.v v14, v19
-; ZIP-NEXT: vsseg6e16.v v9, (a1)
-; ZIP-NEXT: vmv1r.v v9, v24
-; ZIP-NEXT: add a5, a1, a2
-; ZIP-NEXT: vmv1r.v v10, v22
-; ZIP-NEXT: add a3, a0, a2
-; ZIP-NEXT: vmv1r.v v11, v20
-; ZIP-NEXT: add a4, a3, a2
-; ZIP-NEXT: vmv1r.v v12, v16
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vmv1r.v v13, v18
-; ZIP-NEXT: vsseg6e16.v v8, (a0)
-; ZIP-NEXT: vl1re16.v v14, (a1)
-; ZIP-NEXT: add a1, a6, a2
-; ZIP-NEXT: vl1re16.v v15, (a5)
-; ZIP-NEXT: add a5, a1, a2
-; ZIP-NEXT: vl1re16.v v18, (a5)
-; ZIP-NEXT: add a5, a5, a2
-; ZIP-NEXT: vl1re16.v v19, (a5)
-; ZIP-NEXT: add a5, a4, a2
-; ZIP-NEXT: vl1re16.v v16, (a6)
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vl1re16.v v12, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re16.v v13, (a6)
-; ZIP-NEXT: csrr a6, vlenb
-; ZIP-NEXT: li a7, 12
-; ZIP-NEXT: mul a6, a6, a7
-; ZIP-NEXT: add a6, sp, a6
-; ZIP-NEXT: addi a6, a6, 64
-; ZIP-NEXT: vl1re16.v v17, (a1)
-; ZIP-NEXT: vl1re16.v v10, (a4)
-; ZIP-NEXT: vl1re16.v v11, (a5)
-; ZIP-NEXT: vl1re16.v v8, (a0)
-; ZIP-NEXT: vl1re16.v v9, (a3)
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: add a2, a6, a2
-; ZIP-NEXT: vs4r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a6)
-; ZIP-NEXT: vl8re16.v v16, (a2)
-; ZIP-NEXT: vl8re16.v v8, (a6)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv48f16_nxv8f16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -80
@@ -11949,79 +10620,6 @@ define <vscale x 48 x bfloat> @vector_interleave_nxv48bf16_nxv8bf16(<vscale x 8
; ZVBB-RV64-NEXT: addi sp, sp, 80
; ZVBB-RV64-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv48bf16_nxv8bf16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 28
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v20, v14
-; ZIP-NEXT: vmv2r.v v22, v12
-; ZIP-NEXT: vmv2r.v v24, v10
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: li a0, 6
-; ZIP-NEXT: mul a1, a1, a0
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
-; ZIP-NEXT: vmv1r.v v10, v25
-; ZIP-NEXT: vmv1r.v v11, v23
-; ZIP-NEXT: vmv1r.v v12, v21
-; ZIP-NEXT: addi a0, sp, 64
-; ZIP-NEXT: vmv1r.v v13, v17
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: vmv1r.v v14, v19
-; ZIP-NEXT: vsseg6e16.v v9, (a1)
-; ZIP-NEXT: vmv1r.v v9, v24
-; ZIP-NEXT: add a5, a1, a2
-; ZIP-NEXT: vmv1r.v v10, v22
-; ZIP-NEXT: add a3, a0, a2
-; ZIP-NEXT: vmv1r.v v11, v20
-; ZIP-NEXT: add a4, a3, a2
-; ZIP-NEXT: vmv1r.v v12, v16
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vmv1r.v v13, v18
-; ZIP-NEXT: vsseg6e16.v v8, (a0)
-; ZIP-NEXT: vl1re16.v v14, (a1)
-; ZIP-NEXT: add a1, a6, a2
-; ZIP-NEXT: vl1re16.v v15, (a5)
-; ZIP-NEXT: add a5, a1, a2
-; ZIP-NEXT: vl1re16.v v18, (a5)
-; ZIP-NEXT: add a5, a5, a2
-; ZIP-NEXT: vl1re16.v v19, (a5)
-; ZIP-NEXT: add a5, a4, a2
-; ZIP-NEXT: vl1re16.v v16, (a6)
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vl1re16.v v12, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re16.v v13, (a6)
-; ZIP-NEXT: csrr a6, vlenb
-; ZIP-NEXT: li a7, 12
-; ZIP-NEXT: mul a6, a6, a7
-; ZIP-NEXT: add a6, sp, a6
-; ZIP-NEXT: addi a6, a6, 64
-; ZIP-NEXT: vl1re16.v v17, (a1)
-; ZIP-NEXT: vl1re16.v v10, (a4)
-; ZIP-NEXT: vl1re16.v v11, (a5)
-; ZIP-NEXT: vl1re16.v v8, (a0)
-; ZIP-NEXT: vl1re16.v v9, (a3)
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: add a2, a6, a2
-; ZIP-NEXT: vs4r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a6)
-; ZIP-NEXT: vl8re16.v v16, (a2)
-; ZIP-NEXT: vl8re16.v v8, (a6)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv48bf16_nxv8bf16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -80
@@ -12535,79 +11133,6 @@ define <vscale x 24 x float> @vector_interleave_nxv24f32_nxv4f32(<vscale x 4 x f
; ZVBB-RV64-NEXT: addi sp, sp, 80
; ZVBB-RV64-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv24f32_nxv4f32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 28
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v20, v14
-; ZIP-NEXT: vmv2r.v v22, v12
-; ZIP-NEXT: vmv2r.v v24, v10
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: li a0, 6
-; ZIP-NEXT: mul a1, a1, a0
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
-; ZIP-NEXT: vmv1r.v v10, v25
-; ZIP-NEXT: vmv1r.v v11, v23
-; ZIP-NEXT: vmv1r.v v12, v21
-; ZIP-NEXT: addi a0, sp, 64
-; ZIP-NEXT: vmv1r.v v13, v17
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: vmv1r.v v14, v19
-; ZIP-NEXT: vsseg6e32.v v9, (a1)
-; ZIP-NEXT: vmv1r.v v9, v24
-; ZIP-NEXT: add a5, a1, a2
-; ZIP-NEXT: vmv1r.v v10, v22
-; ZIP-NEXT: add a3, a0, a2
-; ZIP-NEXT: vmv1r.v v11, v20
-; ZIP-NEXT: add a4, a3, a2
-; ZIP-NEXT: vmv1r.v v12, v16
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vmv1r.v v13, v18
-; ZIP-NEXT: vsseg6e32.v v8, (a0)
-; ZIP-NEXT: vl1re32.v v14, (a1)
-; ZIP-NEXT: add a1, a6, a2
-; ZIP-NEXT: vl1re32.v v15, (a5)
-; ZIP-NEXT: add a5, a1, a2
-; ZIP-NEXT: vl1re32.v v18, (a5)
-; ZIP-NEXT: add a5, a5, a2
-; ZIP-NEXT: vl1re32.v v19, (a5)
-; ZIP-NEXT: add a5, a4, a2
-; ZIP-NEXT: vl1re32.v v16, (a6)
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vl1re32.v v12, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re32.v v13, (a6)
-; ZIP-NEXT: csrr a6, vlenb
-; ZIP-NEXT: li a7, 12
-; ZIP-NEXT: mul a6, a6, a7
-; ZIP-NEXT: add a6, sp, a6
-; ZIP-NEXT: addi a6, a6, 64
-; ZIP-NEXT: vl1re32.v v17, (a1)
-; ZIP-NEXT: vl1re32.v v10, (a4)
-; ZIP-NEXT: vl1re32.v v11, (a5)
-; ZIP-NEXT: vl1re32.v v8, (a0)
-; ZIP-NEXT: vl1re32.v v9, (a3)
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: add a2, a6, a2
-; ZIP-NEXT: vs4r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a6)
-; ZIP-NEXT: vl8re32.v v16, (a2)
-; ZIP-NEXT: vl8re32.v v8, (a6)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv24f32_nxv4f32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -80
@@ -13039,79 +11564,6 @@ define <vscale x 12 x double> @vector_interleave_nxv12f64_nxv2f64(<vscale x 2 x
; ZVBB-RV64-NEXT: addi sp, sp, 80
; ZVBB-RV64-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv12f64_nxv2f64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 28
-; ZIP-NEXT: mul a0, a0, a1
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e64, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v20, v14
-; ZIP-NEXT: vmv2r.v v22, v12
-; ZIP-NEXT: vmv2r.v v24, v10
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: li a0, 6
-; ZIP-NEXT: mul a1, a1, a0
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
-; ZIP-NEXT: vmv1r.v v10, v25
-; ZIP-NEXT: vmv1r.v v11, v23
-; ZIP-NEXT: vmv1r.v v12, v21
-; ZIP-NEXT: addi a0, sp, 64
-; ZIP-NEXT: vmv1r.v v13, v17
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: vmv1r.v v14, v19
-; ZIP-NEXT: vsseg6e64.v v9, (a1)
-; ZIP-NEXT: vmv1r.v v9, v24
-; ZIP-NEXT: add a5, a1, a2
-; ZIP-NEXT: vmv1r.v v10, v22
-; ZIP-NEXT: add a3, a0, a2
-; ZIP-NEXT: vmv1r.v v11, v20
-; ZIP-NEXT: add a4, a3, a2
-; ZIP-NEXT: vmv1r.v v12, v16
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vmv1r.v v13, v18
-; ZIP-NEXT: vsseg6e64.v v8, (a0)
-; ZIP-NEXT: vl1re64.v v14, (a1)
-; ZIP-NEXT: add a1, a6, a2
-; ZIP-NEXT: vl1re64.v v15, (a5)
-; ZIP-NEXT: add a5, a1, a2
-; ZIP-NEXT: vl1re64.v v18, (a5)
-; ZIP-NEXT: add a5, a5, a2
-; ZIP-NEXT: vl1re64.v v19, (a5)
-; ZIP-NEXT: add a5, a4, a2
-; ZIP-NEXT: vl1re64.v v16, (a6)
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vl1re64.v v12, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re64.v v13, (a6)
-; ZIP-NEXT: csrr a6, vlenb
-; ZIP-NEXT: li a7, 12
-; ZIP-NEXT: mul a6, a6, a7
-; ZIP-NEXT: add a6, sp, a6
-; ZIP-NEXT: addi a6, a6, 64
-; ZIP-NEXT: vl1re64.v v17, (a1)
-; ZIP-NEXT: vl1re64.v v10, (a4)
-; ZIP-NEXT: vl1re64.v v11, (a5)
-; ZIP-NEXT: vl1re64.v v8, (a0)
-; ZIP-NEXT: vl1re64.v v9, (a3)
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: add a2, a6, a2
-; ZIP-NEXT: vs4r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a6)
-; ZIP-NEXT: vl8re64.v v16, (a2)
-; ZIP-NEXT: vl8re64.v v8, (a6)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv12f64_nxv2f64:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -80
@@ -13661,87 +12113,6 @@ define <vscale x 56 x half> @vector_interleave_nxv56f16_nxv8f16(<vscale x 8 x ha
; ZVBB-RV64-NEXT: addi sp, sp, 80
; ZVBB-RV64-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv56f16_nxv8f16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 5
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v26, v20
-; ZIP-NEXT: addi a0, sp, 64
-; ZIP-NEXT: vmv2r.v v24, v16
-; ZIP-NEXT: vmv2r.v v22, v12
-; ZIP-NEXT: vmv2r.v v20, v8
-; ZIP-NEXT: vmv1r.v v1, v20
-; ZIP-NEXT: vmv1r.v v3, v22
-; ZIP-NEXT: vmv1r.v v5, v24
-; ZIP-NEXT: vmv1r.v v7, v26
-; ZIP-NEXT: vmv1r.v v2, v10
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a2, a1, 3
-; ZIP-NEXT: sub a1, a2, a1
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: vmv1r.v v4, v14
-; ZIP-NEXT: add a3, a0, a2
-; ZIP-NEXT: add a4, a1, a2
-; ZIP-NEXT: vmv1r.v v6, v18
-; ZIP-NEXT: add a5, a4, a2
-; ZIP-NEXT: vmv1r.v v22, v11
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vmv1r.v v24, v15
-; ZIP-NEXT: vsseg7e16.v v1, (a0)
-; ZIP-NEXT: vmv1r.v v26, v19
-; ZIP-NEXT: vsseg7e16.v v21, (a1)
-; ZIP-NEXT: vl1re16.v v18, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re16.v v19, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re16.v v20, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re16.v v21, (a6)
-; ZIP-NEXT: add a6, a3, a2
-; ZIP-NEXT: vl1re16.v v10, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re16.v v11, (a6)
-; ZIP-NEXT: vl1re16.v v8, (a0)
-; ZIP-NEXT: vl1re16.v v16, (a4)
-; ZIP-NEXT: vl1re16.v v9, (a3)
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a3, 14
-; ZIP-NEXT: mul a0, a0, a3
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: vl1re16.v v17, (a5)
-; ZIP-NEXT: slli a3, a2, 2
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re16.v v12, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re16.v v13, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: add a3, a2, a3
-; ZIP-NEXT: add a2, a0, a2
-; ZIP-NEXT: vl1re16.v v14, (a6)
-; ZIP-NEXT: vl1re16.v v15, (a1)
-; ZIP-NEXT: add a3, a0, a3
-; ZIP-NEXT: vs2r.v v20, (a3)
-; ZIP-NEXT: vs4r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a0)
-; ZIP-NEXT: vl8re16.v v16, (a2)
-; ZIP-NEXT: vl8re16.v v8, (a0)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv56f16_nxv8f16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -80
@@ -14299,87 +12670,6 @@ define <vscale x 56 x bfloat> @vector_interleave_nxv56bf16_nxv8bf16(<vscale x 8
; ZVBB-RV64-NEXT: addi sp, sp, 80
; ZVBB-RV64-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv56bf16_nxv8bf16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 5
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v26, v20
-; ZIP-NEXT: addi a0, sp, 64
-; ZIP-NEXT: vmv2r.v v24, v16
-; ZIP-NEXT: vmv2r.v v22, v12
-; ZIP-NEXT: vmv2r.v v20, v8
-; ZIP-NEXT: vmv1r.v v1, v20
-; ZIP-NEXT: vmv1r.v v3, v22
-; ZIP-NEXT: vmv1r.v v5, v24
-; ZIP-NEXT: vmv1r.v v7, v26
-; ZIP-NEXT: vmv1r.v v2, v10
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a2, a1, 3
-; ZIP-NEXT: sub a1, a2, a1
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: vmv1r.v v4, v14
-; ZIP-NEXT: add a3, a0, a2
-; ZIP-NEXT: add a4, a1, a2
-; ZIP-NEXT: vmv1r.v v6, v18
-; ZIP-NEXT: add a5, a4, a2
-; ZIP-NEXT: vmv1r.v v22, v11
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vmv1r.v v24, v15
-; ZIP-NEXT: vsseg7e16.v v1, (a0)
-; ZIP-NEXT: vmv1r.v v26, v19
-; ZIP-NEXT: vsseg7e16.v v21, (a1)
-; ZIP-NEXT: vl1re16.v v18, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re16.v v19, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re16.v v20, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re16.v v21, (a6)
-; ZIP-NEXT: add a6, a3, a2
-; ZIP-NEXT: vl1re16.v v10, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re16.v v11, (a6)
-; ZIP-NEXT: vl1re16.v v8, (a0)
-; ZIP-NEXT: vl1re16.v v16, (a4)
-; ZIP-NEXT: vl1re16.v v9, (a3)
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a3, 14
-; ZIP-NEXT: mul a0, a0, a3
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: vl1re16.v v17, (a5)
-; ZIP-NEXT: slli a3, a2, 2
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re16.v v12, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re16.v v13, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: add a3, a2, a3
-; ZIP-NEXT: add a2, a0, a2
-; ZIP-NEXT: vl1re16.v v14, (a6)
-; ZIP-NEXT: vl1re16.v v15, (a1)
-; ZIP-NEXT: add a3, a0, a3
-; ZIP-NEXT: vs2r.v v20, (a3)
-; ZIP-NEXT: vs4r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a0)
-; ZIP-NEXT: vl8re16.v v16, (a2)
-; ZIP-NEXT: vl8re16.v v8, (a0)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv56bf16_nxv8bf16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -80
@@ -14937,87 +13227,6 @@ define <vscale x 28 x float> @vector_interleave_nxv28f32_nxv4f32(<vscale x 4 x f
; ZVBB-RV64-NEXT: addi sp, sp, 80
; ZVBB-RV64-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv28f32_nxv4f32:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 5
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v26, v20
-; ZIP-NEXT: addi a0, sp, 64
-; ZIP-NEXT: vmv2r.v v24, v16
-; ZIP-NEXT: vmv2r.v v22, v12
-; ZIP-NEXT: vmv2r.v v20, v8
-; ZIP-NEXT: vmv1r.v v1, v20
-; ZIP-NEXT: vmv1r.v v3, v22
-; ZIP-NEXT: vmv1r.v v5, v24
-; ZIP-NEXT: vmv1r.v v7, v26
-; ZIP-NEXT: vmv1r.v v2, v10
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a2, a1, 3
-; ZIP-NEXT: sub a1, a2, a1
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: vmv1r.v v4, v14
-; ZIP-NEXT: add a3, a0, a2
-; ZIP-NEXT: add a4, a1, a2
-; ZIP-NEXT: vmv1r.v v6, v18
-; ZIP-NEXT: add a5, a4, a2
-; ZIP-NEXT: vmv1r.v v22, v11
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vmv1r.v v24, v15
-; ZIP-NEXT: vsseg7e32.v v1, (a0)
-; ZIP-NEXT: vmv1r.v v26, v19
-; ZIP-NEXT: vsseg7e32.v v21, (a1)
-; ZIP-NEXT: vl1re32.v v18, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re32.v v19, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re32.v v20, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re32.v v21, (a6)
-; ZIP-NEXT: add a6, a3, a2
-; ZIP-NEXT: vl1re32.v v10, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re32.v v11, (a6)
-; ZIP-NEXT: vl1re32.v v8, (a0)
-; ZIP-NEXT: vl1re32.v v16, (a4)
-; ZIP-NEXT: vl1re32.v v9, (a3)
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a3, 14
-; ZIP-NEXT: mul a0, a0, a3
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: vl1re32.v v17, (a5)
-; ZIP-NEXT: slli a3, a2, 2
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re32.v v12, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re32.v v13, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: add a3, a2, a3
-; ZIP-NEXT: add a2, a0, a2
-; ZIP-NEXT: vl1re32.v v14, (a6)
-; ZIP-NEXT: vl1re32.v v15, (a1)
-; ZIP-NEXT: add a3, a0, a3
-; ZIP-NEXT: vs2r.v v20, (a3)
-; ZIP-NEXT: vs4r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a0)
-; ZIP-NEXT: vl8re32.v v16, (a2)
-; ZIP-NEXT: vl8re32.v v8, (a0)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv28f32_nxv4f32:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -80
@@ -15493,87 +13702,6 @@ define <vscale x 14 x double> @vector_interleave_nxv14f64_nxv2f64(<vscale x 2 x
; ZVBB-RV64-NEXT: addi sp, sp, 80
; ZVBB-RV64-NEXT: ret
;
-; ZIP-LABEL: vector_interleave_nxv14f64_nxv2f64:
-; ZIP: # %bb.0:
-; ZIP-NEXT: addi sp, sp, -80
-; ZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
-; ZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
-; ZIP-NEXT: addi s0, sp, 80
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 5
-; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: andi sp, sp, -64
-; ZIP-NEXT: vsetvli a0, zero, e64, m1, ta, ma
-; ZIP-NEXT: vmv2r.v v26, v20
-; ZIP-NEXT: addi a0, sp, 64
-; ZIP-NEXT: vmv2r.v v24, v16
-; ZIP-NEXT: vmv2r.v v22, v12
-; ZIP-NEXT: vmv2r.v v20, v8
-; ZIP-NEXT: vmv1r.v v1, v20
-; ZIP-NEXT: vmv1r.v v3, v22
-; ZIP-NEXT: vmv1r.v v5, v24
-; ZIP-NEXT: vmv1r.v v7, v26
-; ZIP-NEXT: vmv1r.v v2, v10
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a2, a1, 3
-; ZIP-NEXT: sub a1, a2, a1
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 64
-; ZIP-NEXT: csrr a2, vlenb
-; ZIP-NEXT: vmv1r.v v4, v14
-; ZIP-NEXT: add a3, a0, a2
-; ZIP-NEXT: add a4, a1, a2
-; ZIP-NEXT: vmv1r.v v6, v18
-; ZIP-NEXT: add a5, a4, a2
-; ZIP-NEXT: vmv1r.v v22, v11
-; ZIP-NEXT: add a6, a5, a2
-; ZIP-NEXT: vmv1r.v v24, v15
-; ZIP-NEXT: vsseg7e64.v v1, (a0)
-; ZIP-NEXT: vmv1r.v v26, v19
-; ZIP-NEXT: vsseg7e64.v v21, (a1)
-; ZIP-NEXT: vl1re64.v v18, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re64.v v19, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re64.v v20, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re64.v v21, (a6)
-; ZIP-NEXT: add a6, a3, a2
-; ZIP-NEXT: vl1re64.v v10, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re64.v v11, (a6)
-; ZIP-NEXT: vl1re64.v v8, (a0)
-; ZIP-NEXT: vl1re64.v v16, (a4)
-; ZIP-NEXT: vl1re64.v v9, (a3)
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a3, 14
-; ZIP-NEXT: mul a0, a0, a3
-; ZIP-NEXT: add a0, sp, a0
-; ZIP-NEXT: addi a0, a0, 64
-; ZIP-NEXT: vl1re64.v v17, (a5)
-; ZIP-NEXT: slli a3, a2, 2
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re64.v v12, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: vl1re64.v v13, (a6)
-; ZIP-NEXT: add a6, a6, a2
-; ZIP-NEXT: slli a2, a2, 3
-; ZIP-NEXT: add a3, a2, a3
-; ZIP-NEXT: add a2, a0, a2
-; ZIP-NEXT: vl1re64.v v14, (a6)
-; ZIP-NEXT: vl1re64.v v15, (a1)
-; ZIP-NEXT: add a3, a0, a3
-; ZIP-NEXT: vs2r.v v20, (a3)
-; ZIP-NEXT: vs4r.v v16, (a2)
-; ZIP-NEXT: vs8r.v v8, (a0)
-; ZIP-NEXT: vl8re64.v v16, (a2)
-; ZIP-NEXT: vl8re64.v v8, (a0)
-; ZIP-NEXT: addi sp, s0, -80
-; ZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
-; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
-; ZIP-NEXT: addi sp, sp, 80
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: vector_interleave_nxv14f64_nxv2f64:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: addi sp, sp, -80
@@ -16796,19 +14924,6 @@ define <vscale x 4 x i16> @interleave2_diff_const_splat_nxv4i16() {
; ZVBB-NEXT: vslideup.vx v8, v9, a0
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: interleave2_diff_const_splat_nxv4i16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; ZIP-NEXT: vmv.v.i v9, 4
-; ZIP-NEXT: vmv.v.i v10, 3
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: ri.vzip2b.vv v11, v10, v9
-; ZIP-NEXT: ri.vzip2a.vv v8, v10, v9
-; ZIP-NEXT: srli a0, a0, 2
-; ZIP-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; ZIP-NEXT: vslideup.vx v8, v11, a0
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: interleave2_diff_const_splat_nxv4i16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
@@ -16871,19 +14986,6 @@ define <vscale x 4 x i16> @interleave2_diff_nonconst_splat_nxv4i16(i16 %a, i16 %
; ZVBB-NEXT: vslideup.vx v8, v9, a1
; ZVBB-NEXT: ret
;
-; ZIP-LABEL: interleave2_diff_nonconst_splat_nxv4i16:
-; ZIP: # %bb.0:
-; ZIP-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
-; ZIP-NEXT: vmv.v.x v9, a0
-; ZIP-NEXT: vmv.v.x v10, a1
-; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: ri.vzip2b.vv v11, v9, v10
-; ZIP-NEXT: ri.vzip2a.vv v8, v9, v10
-; ZIP-NEXT: srli a0, a0, 2
-; ZIP-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; ZIP-NEXT: vslideup.vx v8, v11, a0
-; ZIP-NEXT: ret
-;
; ZVZIP-LABEL: interleave2_diff_nonconst_splat_nxv4i16:
; ZVZIP: # %bb.0:
; ZVZIP-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
index 83ef29c469c5c..d2b6ba33e5982 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
@@ -1075,110 +1075,6 @@ body: |
%y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */
$v8 = COPY %y
...
----
-# XRivosVizip: these should't reduce the vl of their inputs.
-name: ri_vzipeven_vv
-body: |
- bb.0:
- liveins: $x8
- ; CHECK-LABEL: name: ri_vzipeven_vv
- ; CHECK: liveins: $x8
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */
- ; CHECK-NEXT: early-clobber %y:vr = PseudoRI_VZIPEVEN_VV_M1 $noreg, %x, %x, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */
- ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */
- ; CHECK-NEXT: $v8 = COPY %z
- %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */
- %y:vr = PseudoRI_VZIPEVEN_VV_M1 $noreg, %x, %x, -1, 5 /* e32 */, 0 /* tu, mu */
- %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */
- $v8 = COPY %z
-...
----
-name: ri_vzipodd_vv
-body: |
- bb.0:
- liveins: $x8
- ; CHECK-LABEL: name: ri_vzipodd_vv
- ; CHECK: liveins: $x8
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */
- ; CHECK-NEXT: early-clobber %y:vr = PseudoRI_VZIPODD_VV_M1 $noreg, %x, %x, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */
- ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */
- ; CHECK-NEXT: $v8 = COPY %z
- %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */
- %y:vr = PseudoRI_VZIPODD_VV_M1 $noreg, %x, %x, -1, 5 /* e32 */, 0 /* tu, mu */
- %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */
- $v8 = COPY %z
-...
----
-name: ri_vzip2a_vv
-body: |
- bb.0:
- liveins: $x8
- ; CHECK-LABEL: name: ri_vzip2a_vv
- ; CHECK: liveins: $x8
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */
- ; CHECK-NEXT: early-clobber %y:vr = PseudoRI_VZIP2A_VV_M1 $noreg, %x, %x, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */
- ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */
- ; CHECK-NEXT: $v8 = COPY %z
- %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */
- %y:vr = PseudoRI_VZIP2A_VV_M1 $noreg, %x, %x, -1, 5 /* e32 */, 0 /* tu, mu */
- %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */
- $v8 = COPY %z
-...
----
-name: ri_vzip2b_vv
-body: |
- bb.0:
- liveins: $x8
- ; CHECK-LABEL: name: ri_vzip2b_vv
- ; CHECK: liveins: $x8
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */
- ; CHECK-NEXT: early-clobber %y:vr = PseudoRI_VZIP2B_VV_M1 $noreg, %x, %x, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */
- ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */
- ; CHECK-NEXT: $v8 = COPY %z
- %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */
- %y:vr = PseudoRI_VZIP2B_VV_M1 $noreg, %x, %x, -1, 5 /* e32 */, 0 /* tu, mu */
- %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */
- $v8 = COPY %z
-...
----
-name: ri_vunzip2a_vv
-body: |
- bb.0:
- liveins: $x8
- ; CHECK-LABEL: name: ri_vunzip2a_vv
- ; CHECK: liveins: $x8
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */
- ; CHECK-NEXT: early-clobber %y:vr = PseudoRI_VUNZIP2A_VV_M1 $noreg, %x, %x, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */
- ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */
- ; CHECK-NEXT: $v8 = COPY %z
- %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */
- %y:vr = PseudoRI_VUNZIP2A_VV_M1 $noreg, %x, %x, -1, 5 /* e32 */, 0 /* tu, mu */
- %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */
- $v8 = COPY %z
-...
----
-name: ri_vunzip2b_vv
-body: |
- bb.0:
- liveins: $x8
- ; CHECK-LABEL: name: ri_vunzip2b_vv
- ; CHECK: liveins: $x8
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */
- ; CHECK-NEXT: early-clobber %y:vr = PseudoRI_VUNZIP2B_VV_M1 $noreg, %x, %x, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */
- ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */
- ; CHECK-NEXT: $v8 = COPY %z
- %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */
- %y:vr = PseudoRI_VUNZIP2B_VV_M1 $noreg, %x, %x, -1, 5 /* e32 */, 0 /* tu, mu */
- %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */
- $v8 = COPY %z
-...
----
name: vl_sink_end_of_bb
body: |
; CHECK-LABEL: name: vl_sink_end_of_bb
diff --git a/llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll b/llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
index 41c71da2bebb6..f7e0d06163619 100644
--- a/llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
+++ b/llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
@@ -158,9 +158,9 @@ define dso_local noundef signext i32 @main() #2 !dbg !28 {
ret i32 %6, !dbg !36
}
-attributes #0 = { mustprogress noinline optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+i,+m,+relax,+zaamo,+zalrsc,+zca,+zcd,+zicsr,+zifencei,+zmmul,-b,-e,-experimental-p,-experimental-svukte,-xqccmp,-xqcia,-xqciac,-xqcibi,-xqcibm,-xqcicli,-xqcicm,-xqcics,-xqcicsr,-xqciint,-xqciio,-xqcilb,-xqcili,-xqcilia,-xqcilo,-xqcilsm,-xqcisim,-xqcisls,-xqcisync,-experimental-xrivosvizip,-experimental-xsfmclic,-experimental-xsfsclic,-experimental-zalasr,-experimental-zibi,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvfbfa,-experimental-zvfofp8min,-experimental-zvkgs,-experimental-zvdot4a8i,-h,-q,-sdext,-sdtrig,-sha,-shcounterenw,-shgatpa,-shlcofideleg,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcntrpmf,-smcsrind,-smctr,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssctr,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xandesbfhcvt,-xandesperf,-xandesvbfhcvt,-xandesvdot,-xandesvpackfph,-xandesvsinth,-xandesvsintload,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscbop,-xmipscmov,-xmipsexectl,-xmipslsp,-xsfcease,-xsfmm128t,-xsfmm16t,-xsfmm32a16f,-xsfmm32a32f,-xsfmm32a8f,-xsfmm32a8i,-xsfmm32t,-xsfmm64a64f,-xsfmm64t,-xsfmmbase,-xsfvcp,-xsfvfbfexp16e,-xsfvfexp16e,-xsfvfexp32e,-xsfvfexpa,-xsfvfexpa64e,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xsmtvdot,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zcb,-zce,-zcf,-zclsd,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccamoc,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zilsd,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }
-attributes #1 = { mustprogress noinline nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+i,+m,+relax,+zaamo,+zalrsc,+zca,+zcd,+zicsr,+zifencei,+zmmul,-b,-e,-experimental-p,-experimental-svukte,-xqccmp,-xqcia,-xqciac,-xqcibi,-xqcibm,-xqcicli,-xqcicm,-xqcics,-xqcicsr,-xqciint,-xqciio,-xqcilb,-xqcili,-xqcilia,-xqcilo,-xqcilsm,-xqcisim,-xqcisls,-xqcisync,-experimental-xrivosvizip,-experimental-xsfmclic,-experimental-xsfsclic,-experimental-zalasr,-experimental-zibi,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvfbfa,-experimental-zvfofp8min,-experimental-zvkgs,-experimental-zvdot4a8i,-h,-q,-sdext,-sdtrig,-sha,-shcounterenw,-shgatpa,-shlcofideleg,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcntrpmf,-smcsrind,-smctr,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssctr,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xandesbfhcvt,-xandesperf,-xandesvbfhcvt,-xandesvdot,-xandesvpackfph,-xandesvsinth,-xandesvsintload,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscbop,-xmipscmov,-xmipsexectl,-xmipslsp,-xsfcease,-xsfmm128t,-xsfmm16t,-xsfmm32a16f,-xsfmm32a32f,-xsfmm32a8f,-xsfmm32a8i,-xsfmm32t,-xsfmm64a64f,-xsfmm64t,-xsfmmbase,-xsfvcp,-xsfvfbfexp16e,-xsfvfexp16e,-xsfvfexp32e,-xsfvfexpa,-xsfvfexpa64e,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xsmtvdot,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zcb,-zce,-zcf,-zclsd,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccamoc,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zilsd,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }
-attributes #2 = { mustprogress noinline norecurse optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+i,+m,+relax,+zaamo,+zalrsc,+zca,+zcd,+zicsr,+zifencei,+zmmul,-b,-e,-experimental-p,-experimental-svukte,-xqccmp,-xqcia,-xqciac,-xqcibi,-xqcibm,-xqcicli,-xqcicm,-xqcics,-xqcicsr,-xqciint,-xqciio,-xqcilb,-xqcili,-xqcilia,-xqcilo,-xqcilsm,-xqcisim,-xqcisls,-xqcisync,-experimental-xrivosvizip,-experimental-xsfmclic,-experimental-xsfsclic,-experimental-zalasr,-experimental-zibi,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvfbfa,-experimental-zvfofp8min,-experimental-zvkgs,-experimental-zvdot4a8i,-h,-q,-sdext,-sdtrig,-sha,-shcounterenw,-shgatpa,-shlcofideleg,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcntrpmf,-smcsrind,-smctr,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssctr,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xandesbfhcvt,-xandesperf,-xandesvbfhcvt,-xandesvdot,-xandesvpackfph,-xandesvsinth,-xandesvsintload,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscbop,-xmipscmov,-xmipsexectl,-xmipslsp,-xsfcease,-xsfmm128t,-xsfmm16t,-xsfmm32a16f,-xsfmm32a32f,-xsfmm32a8f,-xsfmm32a8i,-xsfmm32t,-xsfmm64a64f,-xsfmm64t,-xsfmmbase,-xsfvcp,-xsfvfbfexp16e,-xsfvfexp16e,-xsfvfexp32e,-xsfvfexpa,-xsfvfexpa64e,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xsmtvdot,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zcb,-zce,-zcf,-zclsd,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccamoc,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zilsd,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }
+attributes #0 = { mustprogress noinline optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+i,+m,+relax,+zaamo,+zalrsc,+zca,+zcd,+zicsr,+zifencei,+zmmul,-b,-e,-experimental-p,-experimental-svukte,-xqccmp,-xqcia,-xqciac,-xqcibi,-xqcibm,-xqcicli,-xqcicm,-xqcics,-xqcicsr,-xqciint,-xqciio,-xqcilb,-xqcili,-xqcilia,-xqcilo,-xqcilsm,-xqcisim,-xqcisls,-xqcisync,-experimental-xsfmclic,-experimental-xsfsclic,-experimental-zalasr,-experimental-zibi,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvfbfa,-experimental-zvfofp8min,-experimental-zvkgs,-experimental-zvdot4a8i,-h,-q,-sdext,-sdtrig,-sha,-shcounterenw,-shgatpa,-shlcofideleg,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcntrpmf,-smcsrind,-smctr,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssctr,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xandesbfhcvt,-xandesperf,-xandesvbfhcvt,-xandesvdot,-xandesvpackfph,-xandesvsinth,-xandesvsintload,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscbop,-xmipscmov,-xmipsexectl,-xmipslsp,-xsfcease,-xsfmm128t,-xsfmm16t,-xsfmm32a16f,-xsfmm32a32f,-xsfmm32a8f,-xsfmm32a8i,-xsfmm32t,-xsfmm64a64f,-xsfmm64t,-xsfmmbase,-xsfvcp,-xsfvfbfexp16e,-xsfvfexp16e,-xsfvfexp32e,-xsfvfexpa,-xsfvfexpa64e,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xsmtvdot,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zcb,-zce,-zcf,-zclsd,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccamoc,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zilsd,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }
+attributes #1 = { mustprogress noinline nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+i,+m,+relax,+zaamo,+zalrsc,+zca,+zcd,+zicsr,+zifencei,+zmmul,-b,-e,-experimental-p,-experimental-svukte,-xqccmp,-xqcia,-xqciac,-xqcibi,-xqcibm,-xqcicli,-xqcicm,-xqcics,-xqcicsr,-xqciint,-xqciio,-xqcilb,-xqcili,-xqcilia,-xqcilo,-xqcilsm,-xqcisim,-xqcisls,-xqcisync,-experimental-xsfmclic,-experimental-xsfsclic,-experimental-zalasr,-experimental-zibi,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvfbfa,-experimental-zvfofp8min,-experimental-zvkgs,-experimental-zvdot4a8i,-h,-q,-sdext,-sdtrig,-sha,-shcounterenw,-shgatpa,-shlcofideleg,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcntrpmf,-smcsrind,-smctr,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssctr,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xandesbfhcvt,-xandesperf,-xandesvbfhcvt,-xandesvdot,-xandesvpackfph,-xandesvsinth,-xandesvsintload,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscbop,-xmipscmov,-xmipsexectl,-xmipslsp,-xsfcease,-xsfmm128t,-xsfmm16t,-xsfmm32a16f,-xsfmm32a32f,-xsfmm32a8f,-xsfmm32a8i,-xsfmm32t,-xsfmm64a64f,-xsfmm64t,-xsfmmbase,-xsfvcp,-xsfvfbfexp16e,-xsfvfexp16e,-xsfvfexp32e,-xsfvfexpa,-xsfvfexpa64e,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xsmtvdot,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zcb,-zce,-zcf,-zclsd,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccamoc,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zilsd,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }
+attributes #2 = { mustprogress noinline norecurse optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+i,+m,+relax,+zaamo,+zalrsc,+zca,+zcd,+zicsr,+zifencei,+zmmul,-b,-e,-experimental-p,-experimental-svukte,-xqccmp,-xqcia,-xqciac,-xqcibi,-xqcibm,-xqcicli,-xqcicm,-xqcics,-xqcicsr,-xqciint,-xqciio,-xqcilb,-xqcili,-xqcilia,-xqcilo,-xqcilsm,-xqcisim,-xqcisls,-xqcisync,-experimental-xsfmclic,-experimental-xsfsclic,-experimental-zalasr,-experimental-zibi,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvfbfa,-experimental-zvfofp8min,-experimental-zvkgs,-experimental-zvdot4a8i,-h,-q,-sdext,-sdtrig,-sha,-shcounterenw,-shgatpa,-shlcofideleg,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcntrpmf,-smcsrind,-smctr,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssctr,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xandesbfhcvt,-xandesperf,-xandesvbfhcvt,-xandesvdot,-xandesvpackfph,-xandesvsinth,-xandesvsintload,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscbop,-xmipscmov,-xmipsexectl,-xmipslsp,-xsfcease,-xsfmm128t,-xsfmm16t,-xsfmm32a16f,-xsfmm32a32f,-xsfmm32a8f,-xsfmm32a8i,-xsfmm32t,-xsfmm64a64f,-xsfmm64t,-xsfmmbase,-xsfvcp,-xsfvfbfexp16e,-xsfvfexp16e,-xsfvfexp32e,-xsfvfexpa,-xsfvfexpa64e,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xsmtvdot,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zcb,-zce,-zcf,-zclsd,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccamoc,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zilsd,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }
!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!2, !3, !4, !5, !6, !8, !9}
diff --git a/llvm/test/MC/RISCV/xrivosvizip-invalid.s b/llvm/test/MC/RISCV/xrivosvizip-invalid.s
deleted file mode 100644
index 6d8737899931f..0000000000000
--- a/llvm/test/MC/RISCV/xrivosvizip-invalid.s
+++ /dev/null
@@ -1,10 +0,0 @@
-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-xrivosvizip < %s 2>&1 | \
-# RUN: FileCheck %s
-
-# Disallowed source/dest overlap cases
-# CHECK: error: the destination vector register group cannot overlap the source vector register group
-ri.vzipeven.vv v2, v2, v3
-# CHECK: error: the destination vector register group cannot overlap the source vector register group
-ri.vzipeven.vv v3, v2, v3
-# CHECK: error: the destination vector register group cannot overlap the mask register
-ri.vzipeven.vv v0, v2, v3, v0.t
diff --git a/llvm/test/MC/RISCV/xrivosvizip-valid.s b/llvm/test/MC/RISCV/xrivosvizip-valid.s
deleted file mode 100644
index 55b51a05c023e..0000000000000
--- a/llvm/test/MC/RISCV/xrivosvizip-valid.s
+++ /dev/null
@@ -1,59 +0,0 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xrivosvizip -M no-aliases -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-xrivosvizip < %s \
-# RUN: | llvm-objdump --mattr=+experimental-xrivosvizip -M no-aliases -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-xrivosvizip -M no-aliases -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-xrivosvizip < %s \
-# RUN: | llvm-objdump --mattr=+experimental-xrivosvizip -M no-aliases -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-
-# CHECK-ASM-AND-OBJ: ri.vzipeven.vv v1, v2, v3
-# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x32]
-ri.vzipeven.vv v1, v2, v3
-# CHECK-ASM-AND-OBJ: ri.vzipeven.vv v1, v2, v3, v0.t
-# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x30]
-ri.vzipeven.vv v1, v2, v3, v0.t
-# CHECK-ASM-AND-OBJ: ri.vzipodd.vv v1, v2, v3
-# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x72]
-ri.vzipodd.vv v1, v2, v3
-# CHECK-ASM-AND-OBJ: ri.vzipodd.vv v1, v2, v3, v0.t
-# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x70]
-ri.vzipodd.vv v1, v2, v3, v0.t
-
-# CHECK-ASM-AND-OBJ: ri.vzip2a.vv v1, v2, v3
-# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x12]
-ri.vzip2a.vv v1, v2, v3
-# CHECK-ASM-AND-OBJ: ri.vzip2a.vv v1, v2, v3, v0.t
-# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x10]
-ri.vzip2a.vv v1, v2, v3, v0.t
-# CHECK-ASM-AND-OBJ: ri.vzip2b.vv v1, v2, v3
-# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x52]
-ri.vzip2b.vv v1, v2, v3
-# CHECK-ASM-AND-OBJ: ri.vzip2b.vv v1, v2, v3, v0.t
-# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x50]
-ri.vzip2b.vv v1, v2, v3, v0.t
-
-# CHECK-ASM-AND-OBJ: ri.vunzip2a.vv v1, v2, v3
-# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x22]
-ri.vunzip2a.vv v1, v2, v3
-# CHECK-ASM-AND-OBJ: ri.vunzip2a.vv v1, v2, v3, v0.t
-# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x20]
-ri.vunzip2a.vv v1, v2, v3, v0.t
-# CHECK-ASM-AND-OBJ: ri.vunzip2b.vv v1, v2, v3
-# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x62]
-ri.vunzip2b.vv v1, v2, v3
-# CHECK-ASM-AND-OBJ: ri.vunzip2b.vv v1, v2, v3, v0.t
-# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x60]
-ri.vunzip2b.vv v1, v2, v3, v0.t
-
-# Overlap between source registers *is* allowed
-
-# CHECK-ASM-AND-OBJ: ri.vzipeven.vv v1, v2, v2
-# CHECK-ASM: encoding: [0xdb,0x00,0x21,0x32]
-ri.vzipeven.vv v1, v2, v2
-
-# CHECK-ASM-AND-OBJ: ri.vzipeven.vv v1, v2, v0, v0.t
-# CHECK-ASM: encoding: [0xdb,0x00,0x20,0x30]
-ri.vzipeven.vv v1, v2, v0, v0.t
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index a1702af0f5325..9e7f23e2b4f76 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1401,7 +1401,6 @@ Experimental extensions
smpmpmt 0.6
svukte 0.3
xqccmt 0.1
- xrivosvizip 0.1
xsfmclic 0.1
xsfsclic 0.1
>From 1fc2502eddc6809995fd16fa8f56acdd132b00be Mon Sep 17 00:00:00 2001
From: wangboyao <wangboyao at bytedance.com>
Date: Mon, 1 Jun 2026 17:50:48 +0800
Subject: [PATCH 2/2] [RISCV] Keep vzip shuffle TODO
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 272e9eef86833..cba2f7dd406ac 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -6541,6 +6541,7 @@ SDValue RISCVTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
}
// Prefer vzip if available.
+ // TODO: Extend to matching vzip if EvenSrc and OddSrc allow.
if (Subtarget.hasStdExtZvzip() && isLegalVTForZvzipOperand(VT, Subtarget))
return lowerZvzipVZIP(EvenV, OddV, DL, DAG, Subtarget);
return getWideningInterleave(EvenV, OddV, DL, DAG, Subtarget);
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