[clang] [llvm] [RISCV] Remove experimental XRivosVizip support (PR #200761)
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Mon Jun 1 02:08:26 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Boyao Wang (BoyaoWang430)
<details>
<summary>Changes</summary>
Remove experimental XRivosVizip support which is no longer needed.
---
Patch is 236.16 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/200761.diff
23 Files Affected:
- (modified) clang/test/Driver/print-supported-extensions-riscv.c (-1)
- (modified) llvm/docs/RISCVUsage.rst (-3)
- (modified) llvm/docs/ReleaseNotes.md (+1)
- (modified) llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp (-5)
- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (-9)
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+17-126)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (-1)
- (removed) llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td (-116)
- (modified) llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp (-8)
- (modified) llvm/test/CodeGen/RISCV/features-info.ll (-1)
- (modified) llvm/test/CodeGen/RISCV/pr148084.ll (+1-1)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll (-422)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll (-318)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll (-146)
- (modified) llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll (-46)
- (modified) llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll (-278)
- (modified) llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll (-682)
- (modified) llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll (-1898)
- (modified) llvm/test/CodeGen/RISCV/rvv/vl-opt.mir (-104)
- (modified) llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll (+3-3)
- (removed) llvm/test/MC/RISCV/xrivosvizip-invalid.s (-10)
- (removed) llvm/test/MC/RISCV/xrivosvizip-valid.s (-59)
- (modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (-1)
``````````diff
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 6185b6a19d5e3..29731e565ecfc 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -265,7 +265,6 @@
// CHECK-NEXT: smpmpmt 0.6 'Smpmpmt' (PMP-based Memory Types Extension)
// CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
// CHECK-NEXT: xqccmt 0.1 'Xqccmt' (Qualcomm 16-bit Table Jump)
-// CHECK-NEXT: xrivosvizip 0.1 'XRivosVizip' (Rivos Vector Register Zips)
// CHECK-NEXT: xsfmclic 0.1 'XSfmclic' (SiFive CLIC Machine-mode CSRs)
// CHECK-NEXT: xsfsclic 0.1 'XSfsclic' (SiFive CLIC Supervisor-mode CSRs)
// CHECK-EMPTY:
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 103c9114c272d..166b5dd6352db 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -550,9 +550,6 @@ The current vendor extensions supported are:
``Xmipslsp``
LLVM implements load/store pair instructions for the `p8700 processor <https://mips.com/products/hardware/p8700/>`__ by MIPS.
-``experimental-XRivosVizip``
- LLVM implements `version 0.1 of the Rivos Vector Register Zips extension specification <https://github.com/rivosinc/rivos-custom-extensions>`__.
-
``XAndesPerf``
LLVM implements `version 5.0.0 of the Andes Performance Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 013b5d0a52067..5153c59fe9c61 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -221,6 +221,7 @@ Makes programs 10x faster by doing Special New Thing.
Reordering Structured Data) extension.
* `-mcpu=sifive-x160` and `-mcpu=sifive-x180` were added.
* Support for the experimental `XRivosVisni` vendor extension has been removed.
+* Support for the experimental `XRivosVizip` vendor extension has been removed.
* Adds experimental assembler support for the 'Zvvmm` (RISC-V Integer Matrix Multiply-Accumulate) extension.
* Adds experimental assembler support for the 'Zvvfmm` (RISC-V Floating-Point Matrix Multiply-Accumulate) extension.
* Adds support for 'Ziccid' (Instruction/Data Coherence and Consistency) extension.
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 8101bec143dda..70d40c2355f4f 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -486,10 +486,6 @@ static constexpr FeatureBitset XCVFeatureGroup = {
RISCV::FeatureVendorXCValu, RISCV::FeatureVendorXCVsimd,
RISCV::FeatureVendorXCVbi};
-static constexpr FeatureBitset XRivosFeatureGroup = {
- RISCV::FeatureVendorXRivosVizip,
-};
-
static constexpr FeatureBitset XqciFeatureGroup = {
RISCV::FeatureVendorXqcia, RISCV::FeatureVendorXqciac,
RISCV::FeatureVendorXqcibi, RISCV::FeatureVendorXqcibm,
@@ -542,7 +538,6 @@ static constexpr FeatureBitset XAIFGroup = {RISCV::FeatureVendorXAIFET};
static constexpr DecoderListEntry DecoderList32[]{
// Vendor Extensions
{DecoderTableXCV32, XCVFeatureGroup, "CORE-V extensions"},
- {DecoderTableXRivos32, XRivosFeatureGroup, "Rivos"},
{DecoderTableXqci32, XqciFeatureGroup, "Qualcomm uC Extensions"},
{DecoderTableXVentana32,
{RISCV::FeatureVendorXVentanaCondOps},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index ff875b745cb0e..93392c1b3d402 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1734,15 +1734,6 @@ def FeatureVendorXqci
FeatureVendorXqcilsm, FeatureVendorXqcisim,
FeatureVendorXqcisls, FeatureVendorXqcisync]>;
-// Rivos Extension(s)
-
-def FeatureVendorXRivosVizip
- : RISCVExperimentalExtension<0, 1, "Rivos Vector Register Zips">;
-def HasVendorXRivosVizip
- : Predicate<"Subtarget->hasVendorXRivosVizip()">,
- AssemblerPredicate<(all_of FeatureVendorXRivosVizip),
- "'XRivosVizip' (Rivos Vector Register Zips)">;
-
// Andes Extension(s)
def FeatureVendorXAndesPerf
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 99a20171ae635..272e9eef86833 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -5223,11 +5223,11 @@ static bool isLegalVTForZvzipOperand(MVT VT, const RISCVSubtarget &Subtarget) {
static bool isInterleaveShuffle(ArrayRef<int> Mask, MVT VT, int &EvenSrc,
int &OddSrc, const RISCVSubtarget &Subtarget) {
// We need to be able to widen elements to the next larger integer type or
- // use the zip2a/vzip instruction at e64.
+ // use the vzip instruction at e64.
if (VT.getScalarSizeInBits() >= Subtarget.getELen()) {
- if (!Subtarget.hasVendorXRivosVizip() && !Subtarget.hasStdExtZvzip())
+ if (!Subtarget.hasStdExtZvzip())
return false;
- if (Subtarget.hasStdExtZvzip() && !isLegalVTForZvzipOperand(VT, Subtarget))
+ if (!isLegalVTForZvzipOperand(VT, Subtarget))
return false;
}
@@ -5682,13 +5682,10 @@ bool RISCVTargetLowering::isSpreadMask(ArrayRef<int> Mask, unsigned Factor,
return true;
}
-static SDValue lowerVZIP(unsigned Opc, SDValue Op0, SDValue Op1,
- const SDLoc &DL, SelectionDAG &DAG,
- const RISCVSubtarget &Subtarget) {
- assert(RISCVISD::RI_VZIPEVEN_VL == Opc || RISCVISD::RI_VZIPODD_VL == Opc ||
- RISCVISD::RI_VZIP2A_VL == Opc || RISCVISD::RI_VZIP2B_VL == Opc ||
- RISCVISD::RI_VUNZIP2A_VL == Opc || RISCVISD::RI_VUNZIP2B_VL == Opc ||
- RISCVISD::VPAIRE_VL == Opc || RISCVISD::VPAIRO_VL == Opc);
+static SDValue lowerZvzipVPAIR(unsigned Opc, SDValue Op0, SDValue Op1,
+ const SDLoc &DL, SelectionDAG &DAG,
+ const RISCVSubtarget &Subtarget) {
+ assert(RISCVISD::VPAIRE_VL == Opc || RISCVISD::VPAIRO_VL == Opc);
assert(Op0.getSimpleValueType() == Op1.getSimpleValueType());
MVT VT = Op0.getSimpleValueType();
@@ -5705,22 +5702,9 @@ static SDValue lowerVZIP(unsigned Opc, SDValue Op0, SDValue Op1,
MVT InnerVT = ContainerVT;
auto [Mask, VL] = getDefaultVLOps(IntVT, InnerVT, DL, DAG, Subtarget);
- if (Op1.isUndef() &&
- ContainerVT.bitsGT(RISCVTargetLowering::getM1VT(ContainerVT)) &&
- (RISCVISD::RI_VUNZIP2A_VL == Opc || RISCVISD::RI_VUNZIP2B_VL == Opc)) {
- InnerVT = ContainerVT.getHalfNumVectorElementsVT();
- VL = DAG.getConstant(VT.getVectorNumElements() / 2, DL,
- Subtarget.getXLenVT());
- Mask = getAllOnesMask(InnerVT, VL, DL, DAG);
- unsigned HighIdx = InnerVT.getVectorElementCount().getKnownMinValue();
- Op1 = DAG.getExtractSubvector(DL, InnerVT, Op0, HighIdx);
- Op0 = DAG.getExtractSubvector(DL, InnerVT, Op0, 0);
- }
SDValue Passthru = DAG.getUNDEF(InnerVT);
SDValue Res = DAG.getNode(Opc, DL, InnerVT, Op0, Op1, Passthru, Mask, VL);
- if (InnerVT.bitsLT(ContainerVT))
- Res = DAG.getInsertSubvector(DL, DAG.getUNDEF(ContainerVT), Res, 0);
if (IntVT.isFixedLengthVector())
Res = convertFromScalableVector(IntVT, Res, DAG, Subtarget);
Res = DAG.getBitcast(VT, Res);
@@ -6479,10 +6463,10 @@ SDValue RISCVTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
}
}
- // If this is a deinterleave(2), try using vunzip{a,b} or vunzip{e,o}. This
- // mostly catches e64 which can't match above.
+ // If this is a deinterleave(2), try using vunzip{e,o}. This mostly catches
+ // e64 which can't match above.
unsigned Index = 0;
- if ((Subtarget.hasVendorXRivosVizip() || Subtarget.hasStdExtZvzip()) &&
+ if (Subtarget.hasStdExtZvzip() &&
ShuffleVectorInst::isDeInterleaveMaskOfFactor(Mask, 2, Index) &&
1 < count_if(Mask, [](int Idx) { return Idx != -1; })) {
bool UsesBothSources =
@@ -6491,7 +6475,7 @@ SDValue RISCVTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
1 < count_if(Mask,
[&Mask](int Idx) { return Idx >= (int)Mask.size(); });
- if (Subtarget.hasStdExtZvzip() && isLegalVTForZvzipOperand(VT, Subtarget)) {
+ if (isLegalVTForZvzipOperand(VT, Subtarget)) {
unsigned Opc = Index == 0 ? RISCVISD::VUNZIPE_VL : RISCVISD::VUNZIPO_VL;
MVT NewVT = VT.getDoubleNumVectorElementsVT();
if (isTypeLegal(NewVT)) {
@@ -6516,45 +6500,6 @@ SDValue RISCVTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
}
}
-
- if (Subtarget.hasVendorXRivosVizip()) {
- unsigned Opc =
- Index == 0 ? RISCVISD::RI_VUNZIP2A_VL : RISCVISD::RI_VUNZIP2B_VL;
- if (V2.isUndef())
- return lowerVZIP(Opc, V1, V2, DL, DAG, Subtarget);
- if (auto VLEN = Subtarget.getRealVLen();
- VLEN && VT.getSizeInBits().getKnownMinValue() % *VLEN == 0)
- return lowerVZIP(Opc, V1, V2, DL, DAG, Subtarget);
- if (SDValue Src = foldConcatVector(V1, V2)) {
- EVT NewVT = VT.getDoubleNumVectorElementsVT();
- Src = DAG.getExtractSubvector(DL, NewVT, Src, 0);
- SDValue Res =
- lowerVZIP(Opc, Src, DAG.getUNDEF(NewVT), DL, DAG, Subtarget);
- return DAG.getExtractSubvector(DL, VT, Res, 0);
- }
- // Deinterleave each source and concatenate them, or concat first, then
- // deinterleave.
- if (UsesBothSources) {
- const unsigned EltSize = VT.getScalarSizeInBits();
- const unsigned MinVLMAX = Subtarget.getRealMinVLen() / EltSize;
- if (NumElts < MinVLMAX) {
- MVT ConcatVT = VT.getDoubleNumVectorElementsVT();
- SDValue Concat =
- DAG.getNode(ISD::CONCAT_VECTORS, DL, ConcatVT, V1, V2);
- SDValue Res = lowerVZIP(Opc, Concat, DAG.getUNDEF(ConcatVT), DL, DAG,
- Subtarget);
- return DAG.getExtractSubvector(DL, VT, Res, 0);
- }
-
- SDValue Lo = lowerVZIP(Opc, V1, DAG.getUNDEF(VT), DL, DAG, Subtarget);
- SDValue Hi = lowerVZIP(Opc, V2, DAG.getUNDEF(VT), DL, DAG, Subtarget);
-
- MVT SubVT = VT.getHalfNumVectorElementsVT();
- return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
- DAG.getExtractSubvector(DL, SubVT, Lo, 0),
- DAG.getExtractSubvector(DL, SubVT, Hi, 0));
- }
- }
}
if (SDValue V =
@@ -6595,15 +6540,9 @@ SDValue RISCVTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
OddV = DAG.getExtractSubvector(DL, HalfVT, OddV, OddSrc % Size);
}
- // Prefer vzip2a or vzip if available.
- // TODO: Extend to matching ri.vzip2b or vzip if EvenSrc and OddSrc allow.
+ // Prefer vzip if available.
if (Subtarget.hasStdExtZvzip() && isLegalVTForZvzipOperand(VT, Subtarget))
return lowerZvzipVZIP(EvenV, OddV, DL, DAG, Subtarget);
- if (Subtarget.hasVendorXRivosVizip()) {
- EvenV = DAG.getInsertSubvector(DL, DAG.getUNDEF(VT), EvenV, 0);
- OddV = DAG.getInsertSubvector(DL, DAG.getUNDEF(VT), OddV, 0);
- return lowerVZIP(RISCVISD::RI_VZIP2A_VL, EvenV, OddV, DL, DAG, Subtarget);
- }
return getWideningInterleave(EvenV, OddV, DL, DAG, Subtarget);
}
@@ -6655,17 +6594,15 @@ SDValue RISCVTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
return convertFromScalableVector(VT, Res, DAG, Subtarget);
}
- if (Subtarget.hasVendorXRivosVizip() || Subtarget.hasStdExtZvzip()) {
+ if (Subtarget.hasStdExtZvzip()) {
bool TryWiden = false;
unsigned Factor;
if (isPairEven(SrcInfo, Mask, Factor)) {
if (Factor == 1) {
SDValue Src1 = SrcInfo[0].first == 0 ? V1 : V2;
SDValue Src2 = SrcInfo[1].first == 0 ? V1 : V2;
- unsigned int Opc = Subtarget.hasStdExtZvzip()
- ? RISCVISD::VPAIRE_VL
- : RISCVISD::RI_VZIPEVEN_VL;
- return lowerVZIP(Opc, Src1, Src2, DL, DAG, Subtarget);
+ return lowerZvzipVPAIR(RISCVISD::VPAIRE_VL, Src1, Src2, DL, DAG,
+ Subtarget);
}
TryWiden = true;
}
@@ -6673,10 +6610,8 @@ SDValue RISCVTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
if (Factor == 1) {
SDValue Src1 = SrcInfo[1].first == 0 ? V1 : V2;
SDValue Src2 = SrcInfo[0].first == 0 ? V1 : V2;
- unsigned int Opc = Subtarget.hasStdExtZvzip()
- ? RISCVISD::VPAIRO_VL
- : RISCVISD::RI_VZIPODD_VL;
- return lowerVZIP(Opc, Src1, Src2, DL, DAG, Subtarget);
+ return lowerZvzipVPAIR(RISCVISD::VPAIRO_VL, Src1, Src2, DL, DAG,
+ Subtarget);
}
TryWiden = true;
}
@@ -13098,38 +13033,6 @@ SDValue RISCVTargetLowering::lowerVECTOR_DEINTERLEAVE(SDValue Op,
}
}
- if (Subtarget.hasVendorXRivosVizip() && Factor == 2) {
- MVT VT = Op->getSimpleValueType(0);
- SDValue V1 = Op->getOperand(0);
- SDValue V2 = Op->getOperand(1);
-
- // For fractional LMUL, check if we can use a higher LMUL
- // instruction to avoid a vslidedown.
- if (SDValue Src = foldConcatVector(V1, V2);
- Src && RISCVTargetLowering::getM1VT(VT).bitsGT(VT)) {
- EVT NewVT = VT.getDoubleNumVectorElementsVT();
- Src = DAG.getExtractSubvector(DL, NewVT, Src, 0);
- // Freeze the source so we can increase its use count.
- Src = DAG.getFreeze(Src);
- SDValue Even = lowerVZIP(RISCVISD::RI_VUNZIP2A_VL, Src,
- DAG.getUNDEF(NewVT), DL, DAG, Subtarget);
- SDValue Odd = lowerVZIP(RISCVISD::RI_VUNZIP2B_VL, Src,
- DAG.getUNDEF(NewVT), DL, DAG, Subtarget);
- Even = DAG.getExtractSubvector(DL, VT, Even, 0);
- Odd = DAG.getExtractSubvector(DL, VT, Odd, 0);
- return DAG.getMergeValues({Even, Odd}, DL);
- }
-
- // Freeze the sources so we can increase their use count.
- V1 = DAG.getFreeze(V1);
- V2 = DAG.getFreeze(V2);
- SDValue Even =
- lowerVZIP(RISCVISD::RI_VUNZIP2A_VL, V1, V2, DL, DAG, Subtarget);
- SDValue Odd =
- lowerVZIP(RISCVISD::RI_VUNZIP2B_VL, V1, V2, DL, DAG, Subtarget);
- return DAG.getMergeValues({Even, Odd}, DL);
- }
-
SmallVector<SDValue, 8> Ops(Op->op_values());
// Concatenate the vectors as one vector to deinterleave
@@ -13374,18 +13277,6 @@ SDValue RISCVTargetLowering::lowerVECTOR_INTERLEAVE(SDValue Op,
}
}
- // Use ri.vzip2{a,b} if available
- // TODO: Figure out the best lowering for the spread variants
- if (Subtarget.hasVendorXRivosVizip() && !Op.getOperand(0).isUndef() &&
- !Op.getOperand(1).isUndef()) {
- // Freeze the sources so we can increase their use count.
- SDValue V1 = DAG.getFreeze(Op->getOperand(0));
- SDValue V2 = DAG.getFreeze(Op->getOperand(1));
- SDValue Lo = lowerVZIP(RISCVISD::RI_VZIP2A_VL, V1, V2, DL, DAG, Subtarget);
- SDValue Hi = lowerVZIP(RISCVISD::RI_VZIP2B_VL, V1, V2, DL, DAG, Subtarget);
- return DAG.getMergeValues({Lo, Hi}, DL);
- }
-
// If the element type is smaller than ELEN, then we can interleave with
// vwaddu.vv and vwmaccu.vx
if (VecVT.getScalarSizeInBits() < Subtarget.getELen()) {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 7160d2d5c4def..7400e3caec69f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2386,7 +2386,6 @@ include "RISCVInstrInfoXqci.td"
include "RISCVInstrInfoXqccmp.td"
include "RISCVInstrInfoXqccmt.td"
include "RISCVInstrInfoXMips.td"
-include "RISCVInstrInfoXRivos.td"
include "RISCVInstrInfoXAndes.td"
include "RISCVInstrInfoXSpacemiT.td"
include "RISCVInstrInfoXAIF.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
deleted file mode 100644
index c6b8fcdf605e6..0000000000000
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
+++ /dev/null
@@ -1,116 +0,0 @@
-//===-- RISCVInstrInfoXRivos.td ----------------------------*- tablegen -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file describes the vendor extensions defined by Rivos Inc.
-//
-//===----------------------------------------------------------------------===//
-
-class CustomRivosVXI<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
- string opcodestr, string argstr>
- : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
- bits<5> imm;
- bits<5> rs1;
- bits<5> vd;
- bit vm = 0;
-
- let Inst{31-26} = funct6;
- let Inst{25} = vm;
- let Inst{24-20} = imm;
- let Inst{19-15} = rs1;
- let Inst{14-12} = opv.Value;
- let Inst{11-7} = vd;
- let Inst{6-0} = OPC_CUSTOM_2.Value;
-
- let Uses = [VL, VTYPE];
- let VMConstraint = false;
- let Constraints = "$vd = $vd_wb";
-
- let UseNamedOperandTable = true;
-}
-
-class CustomRivosXVI<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
- string opcodestr, string argstr>
- : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
- bits<5> imm;
- bits<5> vs2;
- bits<5> rd;
- bit vm = 1;
-
- let Inst{31-26} = funct6;
- let Inst{25} = vm;
- let Inst{24-20} = vs2;
- let Inst{19-15} = imm;
- let Inst{14-12} = opv.Value;
- let Inst{11-7} = rd;
- let Inst{6-0} = OPC_CUSTOM_2.Value;
-
- let Uses = [VL, VTYPE];
- let VMConstraint = false;
-
- let UseNamedOperandTable = true;
-}
-
-//===----------------------------------------------------------------------===//
-// XRivosVizip
-//===----------------------------------------------------------------------===//
-
-
-let Predicates = [HasVendorXRivosVizip], DecoderNamespace = "XRivos",
- Constraints = "@earlyclobber $vd", VS1VS2Constraint = Vrgather,
- Inst{6-0} = OPC_CUSTOM_2.Value, ReadsPastVL = 1,
- ElementsDependOn = EltDepsNone in {
-defm RI_VZIPEVEN_V : VALU_IV_V<"ri.vzipeven", 0b001100>;
-defm RI_VZIPODD_V : VALU_IV_V<"ri.vzipodd", 0b011100>;
-defm RI_VZIP2A_V : VALU_IV_V<"ri.vzip2a", 0b000100>;
-defm RI_VZIP2B_V : VALU_IV_V<"ri.vzip2b", 0b010100>;
-defm RI_VUNZIP2A_V : VALU_IV_V<"ri.vunzip2a", 0b001000>;
-defm RI_VUNZIP2B_V : VALU_IV_V<"ri.vunzip2b", 0b011000>;
-}
-
-// These are modeled after the int binop VL nodes
-let HasMaskOp = true in {
- def ri_vzipeven_vl : RVSDNode<"RI_VZIPEVEN_VL", SDT_RISCVIntBinOp_VL>;
- def ri_vzipodd_vl : RVSDNode<"RI_VZIPODD_VL", SDT_RISCVIntBinOp_VL>;
- def ri_vzip2a_vl : RVSDNode<"RI_VZIP2A_VL", SDT_RISCVIntBinOp_VL>;
- def ri_vzip2b_vl : RVSDNode<"RI_VZIP2B_VL", SDT_RISCVIntBinOp_VL>;
- def ri_vunzip2a_vl : RVSDNode<"RI_VUNZIP2A_VL", SDT_RISCVIntBinOp_VL>;
- def ri_vunzip2b_vl : RVSDNode<"RI_VUNZIP2B_VL", SDT_RISCVIntBinOp_VL>;
-}
-
-multiclass RIVPseudoVALU_VV {
- foreach m = MxList in
- defm "" : VPseudoBinaryV_VV<m, Commutable=0>;
-}
-
-let Predicates = [HasVendorXRivosVizip],
- Constraints = "@earlyclobber $rd, $rd = $passthru" in {
-defm PseudoRI_VZIPEVEN : RIVPseudoVALU_VV;
-defm PseudoRI_VZIPODD : RIVPseudoVALU_VV;
-defm PseudoRI_VZIP2A : RIVPseudoVALU_VV;
-defm PseudoRI_VZIP2B : RIVPseudoVALU_VV;
-defm PseudoRI_VUNZIP2A : RIVPseudoVALU_VV;
-defm PseudoRI_VUNZIP2B : RIVPseudoVALU_VV;
-}
-
-multiclass RIVPatBinaryVL_VV<SDPatternOperator vop, string instruction_name,
- list<VTypeInfo> vtilist = AllIntegerVectors,
- bit isSEWAware = false> {
- foreach vti = vtilist in
- let Predicates = GetVTypePredicates<vti>.Predicates in
- def : VPatBinaryVL_V<vop, instruction_name, "VV",
- vti.Vector, vti.Vector, vti.Vector, vti....
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/200761
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