[clang] [CIR] Maximum across vector (IEEE754) (PR #199779)

[Kartik Ohlan via cfe-commits]

https://github.com/Ko496-glitch created https://github.com/llvm/llvm-project/pull/199779

Part of https://github.com/llvm/llvm-project/issues/185382

Move the test cases to
[intrinsics.c](https://github.com/llvm/llvmproject/pull/clang/test/CodeGen/AArch64/neon/intrinsics.c)
Removed the test cases from
[neon-intrinsics.c](https://github.com/llvm/llvmproject/pull/clang/test/CodeGen/AArch64/neon/intrinsics.c)

Removed [neon-across.c](clang/test/CodeGen/AArch64/neon-across.c)

>From 40bb27396a15c47d1e110692eb24438f0d860f39 Mon Sep 17 00:00:00 2001
From: Kartik Ohlan <kartik7ohlan at gmail.com>
Date: Tue, 26 May 2026 17:53:48 -0400
Subject: [PATCH] IEEE754

---
 .../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp  |  3 ++
 clang/test/CodeGen/AArch64/neon-across.c      | 18 ----------
 clang/test/CodeGen/AArch64/neon/intrinsics.c  | 36 +++++++++++++++++++
 3 files changed, 39 insertions(+), 18 deletions(-)
 delete mode 100644 clang/test/CodeGen/AArch64/neon-across.c

diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index ca5a4680ee79f..a956a4dddb57f 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -372,6 +372,9 @@ static mlir::Value emitCommonNeonSISDBuiltinExpr(
   case NEON::BI__builtin_neon_vqrshrund_n_s64:
   case NEON::BI__builtin_neon_vqrshrnd_n_s64:
   case NEON::BI__builtin_neon_vqrshrnd_n_u64:
+  case NEON::BI__builtin_neon_vmaxnmv_f32:
+  case NEON::BI__builtin_neon_vmaxnmvq_f32:
+  case NEON::BI__builtin_neon_vmaxnmvq_f64:
     return emitNeonCall(cgf.cgm, cgf.getBuilder(),
                         {cgf.convertType(expr->getArg(0)->getType())}, ops,
                         llvmIntrName, cgf.convertType(expr->getType()), loc);
diff --git a/clang/test/CodeGen/AArch64/neon-across.c b/clang/test/CodeGen/AArch64/neon-across.c
deleted file mode 100644
index f248e31b374ba..0000000000000
--- a/clang/test/CodeGen/AArch64/neon-across.c
+++ /dev/null
@@ -1,18 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature
-// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
-// RUN:  -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s
-
-// REQUIRES: aarch64-registered-target || arm-registered-target
-
-#include <arm_neon.h>
-
-
-// CHECK-LABEL: define {{[^@]+}}@test_vmaxnmvq_f32
-// CHECK-SAME: (<4 x float> noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] {
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[VMAXNMVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float> [[A]])
-// CHECK-NEXT:    ret float [[VMAXNMVQ_F32_I]]
-//
-float32_t test_vmaxnmvq_f32(float32x4_t a) {
-  return vmaxnmvq_f32(a);
-}
diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c
index b07f61a712f90..8b5c495d9cc2a 100644
--- a/clang/test/CodeGen/AArch64/neon/intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c
@@ -24,6 +24,42 @@
 
 #include <arm_neon.h>
 
+//===------------------------------------------------------===//
+// 2.1.1.13.5  Maximum across vector (IEEE754)
+
+//===------------------------------------------------------===//
+
+
+//ALL-LABEL: @test_vmaxnmv_f32(
+float32_t test_vmaxnmv_f32(float32x2_t a) {
+    //CIR: cir.call_llvm_intrinsic "aarch64.neon.fmaxnmv"
+    // 
+    // LLVM-SAME:<2 x float> {{.*}} [[A:%.*]])
+    // LLVM:  [[VMAXNMV_F32_I:%.*]] = call float @llvm.aarch64.neon.fmaxnmv.f32.v2f32(<2 x float> [[A]])
+    // LLVM: ret float [[VMAXNMV_F32_I]]
+  return vmaxnmv_f32(a);
+}
+
+//ALL-LABEL: @test_vmaxnmvq_f32(
+float32_t test_vmaxnmvq_f32(float32x4_t a) {
+    //CIR: cir.call_llvm_intrinsic "aarch64.neon.fmaxnmv"
+    // 
+    // LLVM-SAME: (<4 x float> {{.*}}[[A:%.*]])
+    // LLVM:  [[VMAXNMVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float> [[A]])
+    // LLVM: ret float [[VMAXNMVQ_F32_I]]
+  return vmaxnmvq_f32(a);
+}
+
+//ALL-LABEL: @test_vmaxnmvq_f64(
+float64_t test_vmaxnmvq_f64(float64x2_t a) {
+    //CIR: cir.call_llvm_intrinsic "aarch64.neon.fmaxnmv"
+    // 
+    // LLVM-SAME:  <2 x double> {{.*}} [[A:%.*]])
+    // LLVM:  [[VMAXNMVQ_F64_I:%.*]] = call double @llvm.aarch64.neon.fmaxnmv.f64.v2f64(<2 x double> [[A]])
+    // LLVM:  ret double [[VMAXNMVQ_F64_I]]
+  return vmaxnmvq_f64(a);
+}
+
 //===------------------------------------------------------===//
 // 2.1.3.2.7  Vector saturating rounding shift right and narrow
 // TODO: Implement SISD variants