[clang] 07d0ff1 - [RISCV] Add assembler and disassembler support for Xqccmt extension (#197673)
via cfe-commits
cfe-commits at lists.llvm.org
Mon May 18 22:20:33 PDT 2026
Author: Garvit Gupta
Date: 2026-05-19T10:50:27+05:30
New Revision: 07d0ff1cab1ae6831d9138a04efe704e19c8c9ec
URL: https://github.com/llvm/llvm-project/commit/07d0ff1cab1ae6831d9138a04efe704e19c8c9ec
DIFF: https://github.com/llvm/llvm-project/commit/07d0ff1cab1ae6831d9138a04efe704e19c8c9ec.diff
LOG: [RISCV] Add assembler and disassembler support for Xqccmt extension (#197673)
Xqccmt is Qualcomm's vendor extension providing compressed (16-bit) jump
table instructions, equivalent to (and mutually exclusive with) the
standard Zcmt extension.
Two instructions are added:
- qc.cm.jt (index 0-31): jump via table, no link register written
- qc.cm.jalt (index 32-255): jump via table with link; bit 0 of the jump
table entry selects the link register at runtime: 0 = ra (x1), 1 = t0
(x5)
The encoding is identical to cm.jt/cm.jalt from Zcmt. Xqccmt and Zcmt
are mutually exclusive and cannot be combined. Xqccmt is also
incompatible with Zcd (overlapping encoding space).
Spec: https://github.com/riscv/riscv-unified-db/pull/1788
Added:
llvm/lib/Target/RISCV/RISCVInstrInfoXqccmt.td
llvm/test/MC/RISCV/xqccmt-invalid.s
llvm/test/MC/RISCV/xqccmt-user-csr-name.s
llvm/test/MC/RISCV/xqccmt-valid.s
Modified:
clang/test/Driver/print-supported-extensions-riscv.c
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/docs/ReleaseNotes.md
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/TargetParser/RISCVISAInfo.cpp
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/CodeGen/RISCV/features-info.ll
llvm/test/MC/RISCV/attribute-arch.s
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Removed:
################################################################################
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 82ef3e54dab29..ebee9f3c11910 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -259,6 +259,7 @@
// CHECK-NEXT: zvzip 0.1 'Zvzip' (Vector Reordering Structured Data)
// CHECK-NEXT: smpmpmt 0.6 'Smpmpmt' (PMP-based Memory Types Extension)
// CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
+// CHECK-NEXT: xqccmt 0.1 'Xqccmt' (Qualcomm 16-bit Table Jump)
// CHECK-NEXT: xrivosvizip 0.1 'XRivosVizip' (Rivos Vector Register Zips)
// CHECK-NEXT: xsfmclic 0.1 'XSfmclic' (SiFive CLIC Machine-mode CSRs)
// CHECK-NEXT: xsfsclic 0.1 'XSfsclic' (SiFive CLIC Supervisor-mode CSRs)
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 6682948869f94..4880e02dc2e74 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -101,6 +101,7 @@
// CHECK-NOT: __riscv_zcmop {{.*$}}
// CHECK-NOT: __riscv_zcmp {{.*$}}
// CHECK-NOT: __riscv_zcmt {{.*$}}
+// CHECK-NOT: __riscv_xqccmt {{.*$}}
// CHECK-NOT: __riscv_zdinx {{.*$}}
// CHECK-NOT: __riscv_zfa {{.*$}}
// CHECK-NOT: __riscv_zfbfmin {{.*$}}
@@ -792,6 +793,19 @@
// CHECK-ZCMT-EXT: __riscv_zca 1000000{{$}}
// CHECK-ZCMT-EXT: __riscv_zcmt 1000000{{$}}
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -menable-experimental-extensions \
+// RUN: -march=rv32i_xqccmt0p1 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-XQCCMT-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -menable-experimental-extensions \
+// RUN: -march=rv64i_xqccmt0p1 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-XQCCMT-EXT %s
+// CHECK-XQCCMT-EXT: __riscv_c 2000000{{$}}
+// CHECK-XQCCMT-EXT: __riscv_xqccmt 1000{{$}}
+// CHECK-XQCCMT-EXT: __riscv_zca 1000000{{$}}
+// CHECK-XQCCMT-EXT: __riscv_zicsr 2000000{{$}}
+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32izdinx1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZDINX-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 71d91f73383b5..389f15227d470 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -478,6 +478,9 @@ The current vendor extensions supported are:
``Xqccmp``
LLVM implements `version 0.3 of the 16-bit Push/Pop instructions and double-moves extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqccmp_extension-0.3.0>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification.
+``experimental-Xqccmt``
+ LLVM implements `version 0.1 of the Qualcomm 16-bit Table Jump extension specification <https://github.com/riscv/riscv-unified-db/pull/1788>`__ by Qualcomm. All instructions are prefixed with ``qc.`` as described in the specification.
+
``Xqci``
LLVM implements `version 0.13 of the Qualcomm uC extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 0939c4478fbb5..aa0b158c8a73b 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -212,6 +212,7 @@ Makes programs 10x faster by doing Special New Thing.
* Adds experimental assembler support for the 'Zvvmm` (RISC-V Integer Matrix Multiply-Accumulate) extension.
* Adds experimental assembler support for the 'Zvvfmm` (RISC-V Floating-Point Matrix Multiply-Accumulate) extension.
* Adds support for 'Ziccid' (Instruction/Data Coherence and Consistency) extension.
+* Adds experimental assembler support for the `Xqccmt` (Qualcomm 16-bit Table Jump) vendor extension.
### Changes to the WebAssembly Backend
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 30a5d65a901d3..c1ba344f6edaf 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -579,6 +579,9 @@ static constexpr DecoderListEntry DecoderList16[]{
{DecoderTableXqccmp16,
{RISCV::FeatureVendorXqccmp},
"Xqccmp (Qualcomm 16-bit Push/Pop & Double Move Instructions)"},
+ {DecoderTableXqccmt16,
+ {RISCV::FeatureVendorXqccmt},
+ "Xqccmt (Qualcomm 16-bit Table Jump Instructions)"},
{DecoderTableXwchc16, {RISCV::FeatureVendorXwchc}, "WCH QingKe XW"},
// Standard Extensions
// DecoderTableZicfiss16 must be checked before DecoderTable16.
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 199ac77bef72f..82d67c6e646a1 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1535,6 +1535,14 @@ def HasVendorXqccmp
AssemblerPredicate<(all_of FeatureVendorXqccmp),
"'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)">;
+def FeatureVendorXqccmt
+ : RISCVExperimentalExtension<0, 1, "Qualcomm 16-bit Table Jump",
+ [FeatureStdExtZca, FeatureStdExtZicsr]>;
+def HasVendorXqccmt
+ : Predicate<"Subtarget->hasVendorXqccmt()">,
+ AssemblerPredicate<(all_of FeatureVendorXqccmt),
+ "'Xqccmt' (Qualcomm 16-bit Table Jump)">;
+
def FeatureVendorXqcia
: RISCVExtension<0, 7, "Qualcomm uC Arithmetic Extension">;
def HasVendorXqcia
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index df897357be8eb..4f60a367b711a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2380,6 +2380,7 @@ include "RISCVInstrInfoXCV.td"
include "RISCVInstrInfoXwch.td"
include "RISCVInstrInfoXqci.td"
include "RISCVInstrInfoXqccmp.td"
+include "RISCVInstrInfoXqccmt.td"
include "RISCVInstrInfoXMips.td"
include "RISCVInstrInfoXRivos.td"
include "RISCVInstrInfoXAndes.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqccmt.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqccmt.td
new file mode 100644
index 0000000000000..1ff23e2dddd13
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqccmt.td
@@ -0,0 +1,51 @@
+//===-- RISCVInstrInfoXqccmt.td ----------------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes Qualcomm's Xqccmt extension.
+//
+// Xqccmt is broadly equivalent to (and incompatible with) Zcmt except the
+// following change:
+//
+// - qc.cm.jalt uses bit 0 of the jump table entry as metadata to select the
+// link register: bit 0 = 0 saves the return address in ra (x1), bit 0 = 1
+// saves it in t0 (x5), the alternate link register. The jump target always
+// has bit 0 cleared.
+//
+// The instruction encoding is identical to cm.jt / cm.jalt from Zcmt.
+// Xqccmt and Zcmt are mutually exclusive and cannot both be enabled.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let DecoderNamespace = "Xqccmt", Predicates = [HasVendorXqccmt],
+ hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+
+def QC_CM_JT : RVInst16CJ<0b101, OPC_C2, (outs), (ins uimm5:$index),
+ "qc.cm.jt", "$index"> {
+ bits<5> index;
+
+ let Inst{12-7} = 0b000000;
+ let Inst{6-2} = index;
+}
+
+// qc.cm.jalt may write to either ra (x1) or t0 (x5) at runtime, depending
+// on bit 0 of the jump table entry. Both registers are listed as Defs for
+// conservative correctness.
+let Defs = [X1, X5] in
+def QC_CM_JALT : RVInst16CJ<0b101, OPC_C2, (outs), (ins uimm8ge32:$index),
+ "qc.cm.jalt", "$index"> {
+ bits<8> index;
+
+ let Inst{12-10} = 0b000;
+ let Inst{9-2} = index;
+}
+
+} // DecoderNamespace = "Xqccmt", Predicates = [HasVendorXqccmt]
diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index 973f81d25b321..7b04b42f8d000 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -745,9 +745,11 @@ Error RISCVISAInfo::checkDependency() {
bool HasZvl = MinVLen != 0;
bool HasZcmp = Exts.count("zcmp") != 0;
bool HasXqccmp = Exts.count("xqccmp") != 0;
+ bool HasZcmt = Exts.count("zcmt") != 0;
+ bool HasXqccmt = Exts.count("xqccmt") != 0;
static constexpr StringLiteral ZcdOverlaps[] = {
- {"zcmt"}, {"zcmp"}, {"xqccmp"}, {"xqciac"}, {"xqcicm"},
+ {"zcmt"}, {"zcmp"}, {"xqccmp"}, {"xqccmt"}, {"xqciac"}, {"xqcicm"},
};
static constexpr StringLiteral RV32Only[] = {
{"zcf"}, {"zclsd"}, {"zilsd"}, {"xwchc"}, {"xqci"},
@@ -796,6 +798,9 @@ Error RISCVISAInfo::checkDependency() {
if (HasZcmp && HasXqccmp)
return getIncompatibleError("zcmp", "xqccmp");
+ if (HasZcmt && HasXqccmt)
+ return getIncompatibleError("zcmt", "xqccmt");
+
return Error::success();
}
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 2c1ae20ee44c1..fb2d4e37bb08a 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -78,6 +78,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+xcvmem %s -o - | FileCheck --check-prefix=RV32XCVMEM %s
; RUN: llc -mtriple=riscv32 -mattr=+xcvsimd %s -o - | FileCheck --check-prefix=RV32XCVSIMD %s
; RUN: llc -mtriple=riscv32 -mattr=+xcvbi %s -o - | FileCheck --check-prefix=RV32XCVBI %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqccmt %s -o - | FileCheck --check-prefixes=CHECK,RV32XQCCMT %s
; RUN: llc -mtriple=riscv32 -mattr=+xwchc %s -o - | FileCheck --check-prefix=RV32XWCHC %s
; RUN: llc -mtriple=riscv32 -mattr=+zaamo %s -o - | FileCheck --check-prefix=RV32ZAAMO %s
; RUN: llc -mtriple=riscv32 -mattr=+zalrsc %s -o - | FileCheck --check-prefix=RV32ZALRSC %s
@@ -226,6 +227,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+svrsw60t59b %s -o - | FileCheck --check-prefixes=CHECK,RV64SVRSW60T59B %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-svukte %s -o - | FileCheck --check-prefixes=CHECK,RV64SVUKTE %s
; RUN: llc -mtriple=riscv64 -mattr=+svvptc %s -o - | FileCheck --check-prefixes=CHECK,RV64SVVPTC %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-xqccmt %s -o - | FileCheck --check-prefixes=CHECK,RV64XQCCMT %s
; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops %s -o - | FileCheck --check-prefixes=CHECK,RV64XVENTANACONDOPS %s
; RUN: llc -mtriple=riscv64 -mattr=+za64rs %s -o - | FileCheck --check-prefixes=CHECK,RV64ZA64RS %s
; RUN: llc -mtriple=riscv64 -mattr=+za128rs %s -o - | FileCheck --check-prefixes=CHECK,RV64ZA128RS %s
@@ -404,6 +406,7 @@
; RV32XCVSIMD: .attribute 5, "rv32i2p1_xcvsimd1p0"
; RV32XCVBI: .attribute 5, "rv32i2p1_xcvbi1p0"
; RV32XWCHC: .attribute 5, "rv32i2p1_c2p0_zca1p0_xwchc2p2"
+; RV32XQCCMT: .attribute 5, "rv32i2p1_c2p0_zicsr2p0_zca1p0_xqccmt0p1"
; RV32ZAAMO: .attribute 5, "rv32i2p1_zaamo1p0"
; RV32ZALRSC: .attribute 5, "rv32i2p1_zalrsc1p0"
; RV32COMBINEINTOA: .attribute 5, "rv32i2p1_a2p1_zaamo1p0_zalrsc1p0"
@@ -552,6 +555,7 @@
; RV64SVVPTC: .attribute 5, "rv64i2p1_svvptc1p0"
; RV64SVRSW60T59B: .attribute 5, "rv64i2p1_svrsw60t59b1p0"
; RV64SVINVAL: .attribute 5, "rv64i2p1_svinval1p0"
+; RV64XQCCMT: .attribute 5, "rv64i2p1_c2p0_zicsr2p0_zca1p0_xqccmt0p1"
; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p1_xventanacondops1p0"
; RV64ZTSO: .attribute 5, "rv64i2p1_ztso1p0"
; RV64ZAAMO: .attribute 5, "rv64i2p1_zaamo1p0"
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index 96f193a2633f5..aadbabbbb92db 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -26,6 +26,7 @@
; CHECK-NEXT: experimental-rvm23u32 - RISC-V experimental-rvm23u32 profile.
; CHECK-NEXT: experimental-smpmpmt - 'Smpmpmt' (PMP-based Memory Types Extension).
; CHECK-NEXT: experimental-svukte - 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses).
+; CHECK-NEXT: experimental-xqccmt - 'Xqccmt' (Qualcomm 16-bit Table Jump).
; CHECK-NEXT: experimental-xrivosvizip - 'XRivosVizip' (Rivos Vector Register Zips).
; CHECK-NEXT: experimental-xsfmclic - 'XSfmclic' (SiFive CLIC Machine-mode CSRs).
; CHECK-NEXT: experimental-xsfsclic - 'XSfsclic' (SiFive CLIC Supervisor-mode CSRs).
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index ef5e091e7e41e..5bd0546016e3d 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -276,6 +276,9 @@
.attribute arch, "rv32izcmt1p0"
# CHECK: attribute 5, "rv32i2p1_c2p0_zicsr2p0_zca1p0_zcmt1p0"
+.attribute arch, "rv32i_xqccmt0p1"
+# CHECK: attribute 5, "rv32i2p1_c2p0_zicsr2p0_zca1p0_xqccmt0p1"
+
.attribute arch, "rv64i_xsfvcp"
# CHECK: attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfvcp1p0"
diff --git a/llvm/test/MC/RISCV/xqccmt-invalid.s b/llvm/test/MC/RISCV/xqccmt-invalid.s
new file mode 100644
index 0000000000000..75067b1f26b4f
--- /dev/null
+++ b/llvm/test/MC/RISCV/xqccmt-invalid.s
@@ -0,0 +1,13 @@
+# RUN: not llvm-mc -triple=riscv32 -mattr=+experimental-xqccmt -M no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-ERROR %s
+# RUN: not llvm-mc -triple=riscv64 -mattr=+experimental-xqccmt -M no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-ERROR %s
+
+# CHECK-ERROR: error: immediate must be an integer in the range [0, 31]
+qc.cm.jt 32
+
+# CHECK-ERROR: error: immediate must be an integer in the range [32, 255]
+qc.cm.jalt 256
+
+# CHECK-ERROR: error: immediate must be an integer in the range [32, 255]
+qc.cm.jalt 31
diff --git a/llvm/test/MC/RISCV/xqccmt-user-csr-name.s b/llvm/test/MC/RISCV/xqccmt-user-csr-name.s
new file mode 100644
index 0000000000000..d52e226a794c3
--- /dev/null
+++ b/llvm/test/MC/RISCV/xqccmt-user-csr-name.s
@@ -0,0 +1,29 @@
+# RUN: llvm-mc %s -triple=riscv32 -M no-aliases -mattr=+experimental-xqccmt -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqccmt < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-xqccmt - \
+# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
+#
+# RUN: llvm-mc %s -triple=riscv64 -M no-aliases -mattr=+experimental-xqccmt -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-xqccmt < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-xqccmt - \
+# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
+
+##################################
+# Jump Vector Table CSR
+##################################
+
+# jvt
+# name
+# CHECK-INST: csrrs t1, jvt, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x70,0x01]
+# CHECK-INST-ALIAS: csrr t1, jvt
+# uimm12
+# CHECK-INST: csrrs t2, jvt, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x70,0x01]
+# CHECK-INST-ALIAS: csrr t2, jvt
+# name
+csrrs t1, jvt, zero
+# uimm12
+csrrs t2, 0x017, zero
diff --git a/llvm/test/MC/RISCV/xqccmt-valid.s b/llvm/test/MC/RISCV/xqccmt-valid.s
new file mode 100644
index 0000000000000..4d00ea78bae9c
--- /dev/null
+++ b/llvm/test/MC/RISCV/xqccmt-valid.s
@@ -0,0 +1,45 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqccmt \
+# RUN: -M no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-xqccmt < %s \
+# RUN: | llvm-objdump --mattr=-c,+experimental-xqccmt --no-print-imm-hex \
+# RUN: -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-xqccmt \
+# RUN: -M no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-xqccmt < %s \
+# RUN: | llvm-objdump --mattr=-c,+experimental-xqccmt --no-print-imm-hex \
+# RUN: -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 \
+# RUN: -M no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 \
+# RUN: -M no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# qc.cm.jt
+# CHECK-ASM-AND-OBJ: qc.cm.jt 1
+# CHECK-ASM: encoding: [0x06,0xa0]
+# CHECK-NO-EXT: error: instruction requires the following: 'Xqccmt' (Qualcomm 16-bit Table Jump){{$}}
+qc.cm.jt 1
+
+# CHECK-ASM-AND-OBJ: qc.cm.jt 0
+# CHECK-ASM: encoding: [0x02,0xa0]
+qc.cm.jt 0
+
+# CHECK-ASM-AND-OBJ: qc.cm.jt 31
+# CHECK-ASM: encoding: [0x7e,0xa0]
+qc.cm.jt 31
+
+# qc.cm.jalt
+# CHECK-ASM-AND-OBJ: qc.cm.jalt 32
+# CHECK-ASM: encoding: [0x82,0xa0]
+# CHECK-NO-EXT: error: instruction requires the following: 'Xqccmt' (Qualcomm 16-bit Table Jump){{$}}
+qc.cm.jalt 32
+
+# CHECK-ASM-AND-OBJ: qc.cm.jalt 255
+# CHECK-ASM: encoding: [0xfe,0xa3]
+qc.cm.jalt 255
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index cd0dcf98f50de..2e37a3d70c9da 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -701,6 +701,11 @@ TEST(ParseArchString, RejectsConflictingExtensions) {
EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
"'zcmp' and 'xqccmp' extensions are incompatible");
}
+
+ for (StringRef Input : {"rv32i_zcmt_xqccmt0p1", "rv64i_zcmt_xqccmt0p1"}) {
+ EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
+ "'zcmt' and 'xqccmt' extensions are incompatible");
+ }
}
TEST(ParseArchString, MissingDepency) {
@@ -1390,6 +1395,7 @@ Experimental extensions
zvzip 0.1
smpmpmt 0.6
svukte 0.3
+ xqccmt 0.1
xrivosvizip 0.1
xsfmclic 0.1
xsfsclic 0.1
More information about the cfe-commits
mailing list