[clang] [llvm] [RISCV] Add assembler and disassembler support for Xqccmt extension (PR #197673)
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cfe-commits at lists.llvm.org
Thu May 14 21:51:31 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-clang-driver
Author: Garvit Gupta (quic-garvgupt)
<details>
<summary>Changes</summary>
Xqccmt is Qualcomm's vendor extension providing compressed (16-bit) jump table instructions, equivalent to (and mutually exclusive with) the standard Zcmt extension.
Two instructions are added:
- qc.cm.jt (index 0-31): jump via table, no link register written
- qc.cm.jalt (index 32-255): jump via table with link; bit 0 of the jump table entry selects the link register at runtime: 0 = ra (x1), 1 = t0 (x5)
The encoding is identical to cm.jt/cm.jalt from Zcmt. Xqccmt and Zcmt are mutually exclusive and cannot be combined. Xqccmt is also incompatible with Zcd (overlapping encoding space).
Spec: https://github.com/riscv/riscv-unified-db/pull/1788
---
Full diff: https://github.com/llvm/llvm-project/pull/197673.diff
14 Files Affected:
- (modified) clang/test/Driver/print-supported-extensions-riscv.c (+1)
- (modified) clang/test/Preprocessor/riscv-target-features.c (+12)
- (modified) llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp (+3)
- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+8)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (+1)
- (added) llvm/lib/Target/RISCV/RISCVInstrInfoXqccmt.td (+51)
- (modified) llvm/lib/TargetParser/RISCVISAInfo.cpp (+6-1)
- (modified) llvm/test/CodeGen/RISCV/attributes.ll (+4)
- (modified) llvm/test/CodeGen/RISCV/features-info.ll (+1)
- (modified) llvm/test/MC/RISCV/attribute-arch.s (+3)
- (added) llvm/test/MC/RISCV/xqccmt-invalid.s (+13)
- (added) llvm/test/MC/RISCV/xqccmt-user-csr-name.s (+29)
- (added) llvm/test/MC/RISCV/xqccmt-valid.s (+45)
- (modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+8)
``````````diff
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 82ef3e54dab29..6628d1bd47a4b 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -184,6 +184,7 @@
// CHECK-NEXT: xmipsexectl 1.0 'XMIPSEXECTL' (MIPS execution control)
// CHECK-NEXT: xmipslsp 1.0 'XMIPSLSP' (MIPS optimization for hardware load-store bonding)
// CHECK-NEXT: xqccmp 0.3 'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)
+// CHECK-NEXT: xqccmt 0.1 'Xqccmt' (Qualcomm 16-bit Table Jump)
// CHECK-NEXT: xqci 0.13 'Xqci' (Qualcomm uC Extension)
// CHECK-NEXT: xqcia 0.7 'Xqcia' (Qualcomm uC Arithmetic Extension)
// CHECK-NEXT: xqciac 0.3 'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension)
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 6682948869f94..e7efff2b3f440 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -101,6 +101,7 @@
// CHECK-NOT: __riscv_zcmop {{.*$}}
// CHECK-NOT: __riscv_zcmp {{.*$}}
// CHECK-NOT: __riscv_zcmt {{.*$}}
+// CHECK-NOT: __riscv_xqccmt {{.*$}}
// CHECK-NOT: __riscv_zdinx {{.*$}}
// CHECK-NOT: __riscv_zfa {{.*$}}
// CHECK-NOT: __riscv_zfbfmin {{.*$}}
@@ -792,6 +793,17 @@
// CHECK-ZCMT-EXT: __riscv_zca 1000000{{$}}
// CHECK-ZCMT-EXT: __riscv_zcmt 1000000{{$}}
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32i_xqccmt0p1 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-XQCCMT-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64i_xqccmt0p1 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-XQCCMT-EXT %s
+// CHECK-XQCCMT-EXT: __riscv_c 2000000{{$}}
+// CHECK-XQCCMT-EXT: __riscv_xqccmt 1000{{$}}
+// CHECK-XQCCMT-EXT: __riscv_zca 1000000{{$}}
+// CHECK-XQCCMT-EXT: __riscv_zicsr 2000000{{$}}
+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32izdinx1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZDINX-EXT %s
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 30a5d65a901d3..c1ba344f6edaf 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -579,6 +579,9 @@ static constexpr DecoderListEntry DecoderList16[]{
{DecoderTableXqccmp16,
{RISCV::FeatureVendorXqccmp},
"Xqccmp (Qualcomm 16-bit Push/Pop & Double Move Instructions)"},
+ {DecoderTableXqccmt16,
+ {RISCV::FeatureVendorXqccmt},
+ "Xqccmt (Qualcomm 16-bit Table Jump Instructions)"},
{DecoderTableXwchc16, {RISCV::FeatureVendorXwchc}, "WCH QingKe XW"},
// Standard Extensions
// DecoderTableZicfiss16 must be checked before DecoderTable16.
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 199ac77bef72f..5a8cb5f1e227f 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1535,6 +1535,14 @@ def HasVendorXqccmp
AssemblerPredicate<(all_of FeatureVendorXqccmp),
"'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)">;
+def FeatureVendorXqccmt
+ : RISCVExtension<0, 1, "Qualcomm 16-bit Table Jump",
+ [FeatureStdExtZca, FeatureStdExtZicsr]>;
+def HasVendorXqccmt
+ : Predicate<"Subtarget->hasVendorXqccmt()">,
+ AssemblerPredicate<(all_of FeatureVendorXqccmt),
+ "'Xqccmt' (Qualcomm 16-bit Table Jump)">;
+
def FeatureVendorXqcia
: RISCVExtension<0, 7, "Qualcomm uC Arithmetic Extension">;
def HasVendorXqcia
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 541bf302bf8e5..a535c02e86114 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2385,6 +2385,7 @@ include "RISCVInstrInfoXCV.td"
include "RISCVInstrInfoXwch.td"
include "RISCVInstrInfoXqci.td"
include "RISCVInstrInfoXqccmp.td"
+include "RISCVInstrInfoXqccmt.td"
include "RISCVInstrInfoXMips.td"
include "RISCVInstrInfoXRivos.td"
include "RISCVInstrInfoXAndes.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqccmt.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqccmt.td
new file mode 100644
index 0000000000000..aab2f244f2a22
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqccmt.td
@@ -0,0 +1,51 @@
+//===-- RISCVInstrInfoXqccmt.td ----------------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes Qualcomm's Xqccmt extension.
+//
+// Xqccmt is broadly equivalent to (and incompatible with) Zcmt except the
+// following change:
+//
+// - qc.cm.jalt uses bit 0 of the jump table entry as metadata to select the
+// link register: bit 0 = 0 saves the return address in ra (x1), bit 0 = 1
+// saves it in t0 (x5), the alternate link register. The jump target always
+// has bit 0 cleared.
+//
+// The instruction encoding is identical to cm.jt / cm.jalt from Zcmt.
+// Xqccmt and Zcmt are mutually exclusive and cannot both be enabled.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let DecoderNamespace = "Xqccmt", Predicates = [HasVendorXqccmt],
+ hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+
+def QC_CM_JT : RVInst16CJ<0b101, OPC_C2, (outs), (ins uimm5:$index),
+ "qc.cm.jt", "$index"> {
+ bits<5> index;
+
+ let Inst{12-7} = 0b000000;
+ let Inst{6-2} = index;
+}
+
+// qc.cm.jalt may write to either ra (x1) or t0 (x5) at runtime, depending
+// on bit 0 of the jump table entry. Both registers are listed as Defs for
+// conservative correctness.
+let Defs = [X1, X5] in
+def QC_CM_JALT : RVInst16CJ<0b101, OPC_C2, (outs), (ins uimm8ge32:$index),
+ "qc.cm.jalt", "$index"> {
+ bits<8> index;
+
+ let Inst{12-10} = 0b000;
+ let Inst{9-2} = index;
+}
+
+} // DecoderNamespace = "Xqccmt", Predicates = [HasVendorXqccmt]
diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index 973f81d25b321..7b04b42f8d000 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -745,9 +745,11 @@ Error RISCVISAInfo::checkDependency() {
bool HasZvl = MinVLen != 0;
bool HasZcmp = Exts.count("zcmp") != 0;
bool HasXqccmp = Exts.count("xqccmp") != 0;
+ bool HasZcmt = Exts.count("zcmt") != 0;
+ bool HasXqccmt = Exts.count("xqccmt") != 0;
static constexpr StringLiteral ZcdOverlaps[] = {
- {"zcmt"}, {"zcmp"}, {"xqccmp"}, {"xqciac"}, {"xqcicm"},
+ {"zcmt"}, {"zcmp"}, {"xqccmp"}, {"xqccmt"}, {"xqciac"}, {"xqcicm"},
};
static constexpr StringLiteral RV32Only[] = {
{"zcf"}, {"zclsd"}, {"zilsd"}, {"xwchc"}, {"xqci"},
@@ -796,6 +798,9 @@ Error RISCVISAInfo::checkDependency() {
if (HasZcmp && HasXqccmp)
return getIncompatibleError("zcmp", "xqccmp");
+ if (HasZcmt && HasXqccmt)
+ return getIncompatibleError("zcmt", "xqccmt");
+
return Error::success();
}
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 2c1ae20ee44c1..db0aa8353e2c9 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -88,6 +88,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+zcf %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCF %s
; RUN: llc -mtriple=riscv32 -mattr=+zcmp %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCMP %s
; RUN: llc -mtriple=riscv32 -mattr=+zcmt %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCMT %s
+; RUN: llc -mtriple=riscv32 -mattr=+xqccmt %s -o - | FileCheck --check-prefixes=CHECK,RV32XQCCMT %s
; RUN: llc -mtriple=riscv32 -mattr=+zicsr %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICSR %s
; RUN: llc -mtriple=riscv32 -mattr=+zifencei %s -o - | FileCheck --check-prefixes=CHECK,RV32ZIFENCEI %s
; RUN: llc -mtriple=riscv32 -mattr=+zicntr %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICNTR %s
@@ -240,6 +241,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+zcd %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCD %s
; RUN: llc -mtriple=riscv64 -mattr=+zcmp %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCMP %s
; RUN: llc -mtriple=riscv64 -mattr=+zcmt %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCMT %s
+; RUN: llc -mtriple=riscv64 -mattr=+xqccmt %s -o - | FileCheck --check-prefixes=CHECK,RV64XQCCMT %s
; RUN: llc -mtriple=riscv64 -mattr=+ziccamoa %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICCAMOA %s
; RUN: llc -mtriple=riscv64 -mattr=+ziccamoc %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICCAMOC %s
; RUN: llc -mtriple=riscv64 -mattr=+ziccid %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICCID %s
@@ -413,6 +415,7 @@
; RV32ZCF: .attribute 5, "rv32i2p1_f2p2_c2p0_zicsr2p0_zca1p0_zcf1p0"
; RV32ZCMP: .attribute 5, "rv32i2p1_c2p0_zca1p0_zcmp1p0"
; RV32ZCMT: .attribute 5, "rv32i2p1_c2p0_zicsr2p0_zca1p0_zcmt1p0"
+; RV32XQCCMT: .attribute 5, "rv32i2p1_c2p0_zicsr2p0_zca1p0_xqccmt0p1"
; RV32ZICSR: .attribute 5, "rv32i2p1_zicsr2p0"
; RV32ZIFENCEI: .attribute 5, "rv32i2p1_zifencei2p0"
; RV32ZICNTR: .attribute 5, "rv32i2p1_zicntr2p0_zicsr2p0"
@@ -562,6 +565,7 @@
; RV64ZCD: .attribute 5, "rv64i2p1_f2p2_d2p2_c2p0_zicsr2p0_zca1p0_zcd1p0"
; RV64ZCMP: .attribute 5, "rv64i2p1_c2p0_zca1p0_zcmp1p0"
; RV64ZCMT: .attribute 5, "rv64i2p1_c2p0_zicsr2p0_zca1p0_zcmt1p0"
+; RV64XQCCMT: .attribute 5, "rv64i2p1_c2p0_zicsr2p0_zca1p0_xqccmt0p1"
; RV64ZICCAMOA: .attribute 5, "rv64i2p1_ziccamoa1p0"
; RV64ZICCAMOC: .attribute 5, "rv64i2p1_ziccamoc1p0"
; RV64ZICCID: .attribute 5, "rv64i2p1_ziccid1p0_ziccif1p0"
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index 96f193a2633f5..c90c98d0af914 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -210,6 +210,7 @@
; CHECK-NEXT: xmipsexectl - 'XMIPSEXECTL' (MIPS execution control).
; CHECK-NEXT: xmipslsp - 'XMIPSLSP' (MIPS optimization for hardware load-store bonding).
; CHECK-NEXT: xqccmp - 'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves).
+; CHECK-NEXT: xqccmt - 'Xqccmt' (Qualcomm 16-bit Table Jump).
; CHECK-NEXT: xqci - 'Xqci' (Qualcomm uC Extension).
; CHECK-NEXT: xqcia - 'Xqcia' (Qualcomm uC Arithmetic Extension).
; CHECK-NEXT: xqciac - 'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension).
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index ef5e091e7e41e..5bd0546016e3d 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -276,6 +276,9 @@
.attribute arch, "rv32izcmt1p0"
# CHECK: attribute 5, "rv32i2p1_c2p0_zicsr2p0_zca1p0_zcmt1p0"
+.attribute arch, "rv32i_xqccmt0p1"
+# CHECK: attribute 5, "rv32i2p1_c2p0_zicsr2p0_zca1p0_xqccmt0p1"
+
.attribute arch, "rv64i_xsfvcp"
# CHECK: attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfvcp1p0"
diff --git a/llvm/test/MC/RISCV/xqccmt-invalid.s b/llvm/test/MC/RISCV/xqccmt-invalid.s
new file mode 100644
index 0000000000000..dff8804807987
--- /dev/null
+++ b/llvm/test/MC/RISCV/xqccmt-invalid.s
@@ -0,0 +1,13 @@
+# RUN: not llvm-mc -triple=riscv32 -mattr=+xqccmt -M no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-ERROR %s
+# RUN: not llvm-mc -triple=riscv64 -mattr=+xqccmt -M no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-ERROR %s
+
+# CHECK-ERROR: error: immediate must be an integer in the range [0, 31]
+qc.cm.jt 32
+
+# CHECK-ERROR: error: immediate must be an integer in the range [32, 255]
+qc.cm.jalt 256
+
+# CHECK-ERROR: error: immediate must be an integer in the range [32, 255]
+qc.cm.jalt 31
diff --git a/llvm/test/MC/RISCV/xqccmt-user-csr-name.s b/llvm/test/MC/RISCV/xqccmt-user-csr-name.s
new file mode 100644
index 0000000000000..c7ebbfdb4777f
--- /dev/null
+++ b/llvm/test/MC/RISCV/xqccmt-user-csr-name.s
@@ -0,0 +1,29 @@
+# RUN: llvm-mc %s -triple=riscv32 -M no-aliases -mattr=+xqccmt -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqccmt < %s \
+# RUN: | llvm-objdump -d --mattr=+xqccmt - \
+# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
+#
+# RUN: llvm-mc %s -triple=riscv64 -M no-aliases -mattr=+xqccmt -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xqccmt < %s \
+# RUN: | llvm-objdump -d --mattr=+xqccmt - \
+# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
+
+##################################
+# Jump Vector Table CSR
+##################################
+
+# jvt
+# name
+# CHECK-INST: csrrs t1, jvt, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x70,0x01]
+# CHECK-INST-ALIAS: csrr t1, jvt
+# uimm12
+# CHECK-INST: csrrs t2, jvt, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x70,0x01]
+# CHECK-INST-ALIAS: csrr t2, jvt
+# name
+csrrs t1, jvt, zero
+# uimm12
+csrrs t2, 0x017, zero
diff --git a/llvm/test/MC/RISCV/xqccmt-valid.s b/llvm/test/MC/RISCV/xqccmt-valid.s
new file mode 100644
index 0000000000000..331df395d9c53
--- /dev/null
+++ b/llvm/test/MC/RISCV/xqccmt-valid.s
@@ -0,0 +1,45 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqccmt \
+# RUN: -M no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+xqccmt < %s \
+# RUN: | llvm-objdump --mattr=-c,+xqccmt --no-print-imm-hex \
+# RUN: -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+xqccmt \
+# RUN: -M no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+xqccmt < %s \
+# RUN: | llvm-objdump --mattr=-c,+xqccmt --no-print-imm-hex \
+# RUN: -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 \
+# RUN: -M no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 \
+# RUN: -M no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# qc.cm.jt
+# CHECK-ASM-AND-OBJ: qc.cm.jt 1
+# CHECK-ASM: encoding: [0x06,0xa0]
+# CHECK-NO-EXT: error: instruction requires the following: 'Xqccmt' (Qualcomm 16-bit Table Jump){{$}}
+qc.cm.jt 1
+
+# CHECK-ASM-AND-OBJ: qc.cm.jt 0
+# CHECK-ASM: encoding: [0x02,0xa0]
+qc.cm.jt 0
+
+# CHECK-ASM-AND-OBJ: qc.cm.jt 31
+# CHECK-ASM: encoding: [0x7e,0xa0]
+qc.cm.jt 31
+
+# qc.cm.jalt
+# CHECK-ASM-AND-OBJ: qc.cm.jalt 32
+# CHECK-ASM: encoding: [0x82,0xa0]
+# CHECK-NO-EXT: error: instruction requires the following: 'Xqccmt' (Qualcomm 16-bit Table Jump){{$}}
+qc.cm.jalt 32
+
+# CHECK-ASM-AND-OBJ: qc.cm.jalt 255
+# CHECK-ASM: encoding: [0xfe,0xa3]
+qc.cm.jalt 255
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index cd0dcf98f50de..17cb4d4de0629 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -684,6 +684,8 @@ TEST(ParseArchString, RejectsConflictingExtensions) {
"rv32i_zcd_xqcicm",
"rv32idc_xqccmp",
"rv32i_zcd_xqccmp",
+ "rv32idc_xqccmt",
+ "rv32i_zcd_xqccmt",
"rv32idc_xqci",
"rv32i_zcd_xqci",
}) {
@@ -701,6 +703,11 @@ TEST(ParseArchString, RejectsConflictingExtensions) {
EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
"'zcmp' and 'xqccmp' extensions are incompatible");
}
+
+ for (StringRef Input : {"rv32i_zcmt_xqccmt0p1", "rv64i_zcmt_xqccmt0p1"}) {
+ EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
+ "'zcmt' and 'xqccmt' extensions are incompatible");
+ }
}
TEST(ParseArchString, MissingDepency) {
@@ -1315,6 +1322,7 @@ R"(All available -march extensions for RISC-V
xmipsexectl 1.0
xmipslsp 1.0
xqccmp 0.3
+ xqccmt 0.1
xqci 0.13
xqcia 0.7
xqciac 0.3
``````````
</details>
https://github.com/llvm/llvm-project/pull/197673
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