[clang] [CIR][AArch64] Upstream Neon vget_lane/vgetq_lane builtins (PR #186119)
Ayush Kumar Gaur via cfe-commits
cfe-commits at lists.llvm.org
Sat May 9 12:55:11 PDT 2026
https://github.com/Ayush3941 updated https://github.com/llvm/llvm-project/pull/186119
>From 2745d339bc2eec3d3dc9a548d2cf70c49cd9215f Mon Sep 17 00:00:00 2001
From: Ayush3941 <ayushkgaur1 at gmail.com>
Date: Thu, 12 Mar 2026 09:31:43 -0400
Subject: [PATCH 01/17] [CIR][AArch64] Upstream Neon vget_lane/vgetq_lane
builtins
---
.../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 82 +++++
clang/test/CodeGen/AArch64/neon/neon-vget.c | 302 ++++++++++++++++++
2 files changed, 384 insertions(+)
create mode 100644 clang/test/CodeGen/AArch64/neon/neon-vget.c
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index 5534e69b5f8bc..107271893844d 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -2724,33 +2724,115 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
case NEON::BI__builtin_neon_vset_lane_mf8:
case NEON::BI__builtin_neon_vsetq_lane_mf8:
case NEON::BI__builtin_neon_vsetq_lane_f64:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
+
case NEON::BI__builtin_neon_vget_lane_i8:
+ ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt8Ty, 8));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupb_lane_i8:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
+
case NEON::BI__builtin_neon_vgetq_lane_i8:
+ ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt8Ty, 16));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupb_laneq_i8:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_mf8:
case NEON::BI__builtin_neon_vdupb_lane_mf8:
case NEON::BI__builtin_neon_vgetq_lane_mf8:
case NEON::BI__builtin_neon_vdupb_laneq_mf8:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_i16:
+ ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt16Ty, 4));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vduph_lane_i16:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
case NEON::BI__builtin_neon_vgetq_lane_i16:
+ ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt16Ty, 8));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vduph_laneq_i16:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_i32:
+ ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt32Ty, 2));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdups_lane_i32:
case NEON::BI__builtin_neon_vdups_lane_f32:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
case NEON::BI__builtin_neon_vgetq_lane_i32:
+ ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt32Ty, 4));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdups_laneq_i32:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_i64:
+ ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt64Ty, 1));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupd_lane_i64:
case NEON::BI__builtin_neon_vdupd_lane_f64:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
case NEON::BI__builtin_neon_vgetq_lane_i64:
+ ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt64Ty, 2));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupd_laneq_i64:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_f32:
+ ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(floatTy, 2));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vget_lane_f64:
+ ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(doubleTy, 1));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vgetq_lane_f32:
+ ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(floatTy, 4));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdups_laneq_f32:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
case NEON::BI__builtin_neon_vgetq_lane_f64:
+ ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(doubleTy, 2));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupd_laneq_f64:
case NEON::BI__builtin_neon_vaddh_f16:
case NEON::BI__builtin_neon_vsubh_f16:
diff --git a/clang/test/CodeGen/AArch64/neon/neon-vget.c b/clang/test/CodeGen/AArch64/neon/neon-vget.c
new file mode 100644
index 0000000000000..297a07ced2f41
--- /dev/null
+++ b/clang/test/CodeGen/AArch64/neon/neon-vget.c
@@ -0,0 +1,302 @@
+// REQUIRES: aarch64-registered-target || arm-registered-target
+
+// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=LLVM
+// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -fclangir -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=LLVM %}
+// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -fclangir -emit-cir -o - %s | FileCheck %s --check-prefixes=CIR %}
+
+//=============================================================================
+// NOTES
+//
+// This file contains tests that were originally located in
+// * clang/test/CodeGen/AArch64/neon-vget.c
+// * clang/test/CodeGen/AArch64/poly64.c
+// The main difference is the use of RUN lines that enable ClangIR lowering;
+// therefore only builtins currently supported by ClangIR are tested here.
+//
+// The half-precision extract variants are intentionally omitted here because
+// they lower through the vduph_* builtin IDs, which are still unsupported in
+// CIR for this patch.
+//
+//=============================================================================
+
+#include <arm_neon.h>
+
+//===------------------------------------------------------===//
+// Extract one element from vector
+//===------------------------------------------------------===//
+
+// LLVM-LABEL: @test_vget_lane_u8(
+// CIR-LABEL: @test_vget_lane_u8(
+uint8_t test_vget_lane_u8(uint8x8_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<8 x !u8i>
+
+// LLVM: [[VGET_LANE:%.*]] = extractelement <8 x i8> %{{.*}}, i32 7
+// LLVM: ret i8 [[VGET_LANE]]
+ return vget_lane_u8(a, 7);
+}
+
+// LLVM-LABEL: @test_vget_lane_u16(
+// CIR-LABEL: @test_vget_lane_u16(
+uint16_t test_vget_lane_u16(uint16x4_t a) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !u16i>
+// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u16i>
+
+// LLVM: [[VGET_LANE:%.*]] = extractelement <4 x i16> %{{.*}}, i32 3
+// LLVM: ret i16 [[VGET_LANE]]
+ return vget_lane_u16(a, 3);
+}
+
+// LLVM-LABEL: @test_vget_lane_u32(
+// CIR-LABEL: @test_vget_lane_u32(
+uint32_t test_vget_lane_u32(uint32x2_t a) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<2 x !u32i>
+// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<2 x !u32i>
+
+// LLVM: [[VGET_LANE:%.*]] = extractelement <2 x i32> %{{.*}}, i32 1
+// LLVM: ret i32 [[VGET_LANE]]
+ return vget_lane_u32(a, 1);
+}
+
+// LLVM-LABEL: @test_vget_lane_s8(
+// CIR-LABEL: @test_vget_lane_s8(
+int8_t test_vget_lane_s8(int8x8_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<8 x !u8i>
+
+// LLVM: [[VGET_LANE:%.*]] = extractelement <8 x i8> %{{.*}}, i32 7
+// LLVM: ret i8 [[VGET_LANE]]
+ return vget_lane_s8(a, 7);
+}
+
+// LLVM-LABEL: @test_vget_lane_s16(
+// CIR-LABEL: @test_vget_lane_s16(
+int16_t test_vget_lane_s16(int16x4_t a) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !u16i>
+// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u16i>
+
+// LLVM: [[VGET_LANE:%.*]] = extractelement <4 x i16> %{{.*}}, i32 3
+// LLVM: ret i16 [[VGET_LANE]]
+ return vget_lane_s16(a, 3);
+}
+
+// LLVM-LABEL: @test_vget_lane_s32(
+// CIR-LABEL: @test_vget_lane_s32(
+int32_t test_vget_lane_s32(int32x2_t a) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<2 x !u32i>
+// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<2 x !u32i>
+
+// LLVM: [[VGET_LANE:%.*]] = extractelement <2 x i32> %{{.*}}, i32 1
+// LLVM: ret i32 [[VGET_LANE]]
+ return vget_lane_s32(a, 1);
+}
+
+// LLVM-LABEL: @test_vget_lane_p8(
+// CIR-LABEL: @test_vget_lane_p8(
+poly8_t test_vget_lane_p8(poly8x8_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<8 x !u8i>
+
+// LLVM: [[VGET_LANE:%.*]] = extractelement <8 x i8> %{{.*}}, i32 7
+// LLVM: ret i8 [[VGET_LANE]]
+ return vget_lane_p8(a, 7);
+}
+
+// LLVM-LABEL: @test_vget_lane_p16(
+// CIR-LABEL: @test_vget_lane_p16(
+poly16_t test_vget_lane_p16(poly16x4_t a) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !u16i>
+// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u16i>
+
+// LLVM: [[VGET_LANE:%.*]] = extractelement <4 x i16> %{{.*}}, i32 3
+// LLVM: ret i16 [[VGET_LANE]]
+ return vget_lane_p16(a, 3);
+}
+
+// LLVM-LABEL: @test_vget_lane_f32(
+// CIR-LABEL: @test_vget_lane_f32(
+float32_t test_vget_lane_f32(float32x2_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<2 x !cir.float>
+
+// LLVM: [[VGET_LANE:%.*]] = extractelement <2 x float> %{{.*}}, i32 1
+// LLVM: ret float [[VGET_LANE]]
+ return vget_lane_f32(a, 1);
+}
+
+// LLVM-LABEL: @test_vget_lane_f64(
+// CIR-LABEL: @test_vget_lane_f64(
+float64_t test_vget_lane_f64(float64x1_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<1 x !cir.double>
+
+// LLVM: [[VGET_LANE:%.*]] = extractelement <1 x double> %{{.*}}, i32 0
+// LLVM: ret double [[VGET_LANE]]
+ return vget_lane_f64(a, 0);
+}
+
+// LLVM-LABEL: @test_vgetq_lane_u8(
+// CIR-LABEL: @test_vgetq_lane_u8(
+uint8_t test_vgetq_lane_u8(uint8x16_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<16 x !u8i>
+
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %{{.*}}, i32 15
+// LLVM: ret i8 [[VGETQ_LANE]]
+ return vgetq_lane_u8(a, 15);
+}
+
+// LLVM-LABEL: @test_vgetq_lane_u16(
+// CIR-LABEL: @test_vgetq_lane_u16(
+uint16_t test_vgetq_lane_u16(uint16x8_t a) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<8 x !u16i>
+// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<8 x !u16i>
+
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %{{.*}}, i32 7
+// LLVM: ret i16 [[VGETQ_LANE]]
+ return vgetq_lane_u16(a, 7);
+}
+
+// LLVM-LABEL: @test_vgetq_lane_u32(
+// CIR-LABEL: @test_vgetq_lane_u32(
+uint32_t test_vgetq_lane_u32(uint32x4_t a) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !u32i>
+// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u32i>
+
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %{{.*}}, i32 3
+// LLVM: ret i32 [[VGETQ_LANE]]
+ return vgetq_lane_u32(a, 3);
+}
+
+// LLVM-LABEL: @test_vgetq_lane_s8(
+// CIR-LABEL: @test_vgetq_lane_s8(
+int8_t test_vgetq_lane_s8(int8x16_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<16 x !u8i>
+
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %{{.*}}, i32 15
+// LLVM: ret i8 [[VGETQ_LANE]]
+ return vgetq_lane_s8(a, 15);
+}
+
+// LLVM-LABEL: @test_vgetq_lane_s16(
+// CIR-LABEL: @test_vgetq_lane_s16(
+int16_t test_vgetq_lane_s16(int16x8_t a) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<8 x !u16i>
+// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<8 x !u16i>
+
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %{{.*}}, i32 7
+// LLVM: ret i16 [[VGETQ_LANE]]
+ return vgetq_lane_s16(a, 7);
+}
+
+// LLVM-LABEL: @test_vgetq_lane_s32(
+// CIR-LABEL: @test_vgetq_lane_s32(
+int32_t test_vgetq_lane_s32(int32x4_t a) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !u32i>
+// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u32i>
+
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %{{.*}}, i32 3
+// LLVM: ret i32 [[VGETQ_LANE]]
+ return vgetq_lane_s32(a, 3);
+}
+
+// LLVM-LABEL: @test_vgetq_lane_p8(
+// CIR-LABEL: @test_vgetq_lane_p8(
+poly8_t test_vgetq_lane_p8(poly8x16_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<16 x !u8i>
+
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %{{.*}}, i32 15
+// LLVM: ret i8 [[VGETQ_LANE]]
+ return vgetq_lane_p8(a, 15);
+}
+
+// LLVM-LABEL: @test_vgetq_lane_p16(
+// CIR-LABEL: @test_vgetq_lane_p16(
+poly16_t test_vgetq_lane_p16(poly16x8_t a) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<8 x !u16i>
+// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<8 x !u16i>
+
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %{{.*}}, i32 7
+// LLVM: ret i16 [[VGETQ_LANE]]
+ return vgetq_lane_p16(a, 7);
+}
+
+// LLVM-LABEL: @test_vgetq_lane_f32(
+// CIR-LABEL: @test_vgetq_lane_f32(
+float32_t test_vgetq_lane_f32(float32x4_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<4 x !cir.float>
+
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <4 x float> %{{.*}}, i32 3
+// LLVM: ret float [[VGETQ_LANE]]
+ return vgetq_lane_f32(a, 3);
+}
+
+// LLVM-LABEL: @test_vgetq_lane_f64(
+// CIR-LABEL: @test_vgetq_lane_f64(
+float64_t test_vgetq_lane_f64(float64x2_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<2 x !cir.double>
+
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <2 x double> %{{.*}}, i32 1
+// LLVM: ret double [[VGETQ_LANE]]
+ return vgetq_lane_f64(a, 1);
+}
+
+// LLVM-LABEL: @test_vget_lane_s64(
+// CIR-LABEL: @test_vget_lane_s64(
+int64_t test_vget_lane_s64(int64x1_t a) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<1 x !u64i>
+// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<1 x !u64i>
+
+// LLVM: [[VGET_LANE:%.*]] = extractelement <1 x i64> %{{.*}}, i32 0
+// LLVM: ret i64 [[VGET_LANE]]
+ return vget_lane_s64(a, 0);
+}
+
+// LLVM-LABEL: @test_vget_lane_u64(
+// CIR-LABEL: @test_vget_lane_u64(
+uint64_t test_vget_lane_u64(uint64x1_t a) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<1 x !u64i>
+// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<1 x !u64i>
+
+// LLVM: [[VGET_LANE:%.*]] = extractelement <1 x i64> %{{.*}}, i32 0
+// LLVM: ret i64 [[VGET_LANE]]
+ return vget_lane_u64(a, 0);
+}
+
+// LLVM-LABEL: @test_vget_lane_p64(
+// CIR-LABEL: @test_vget_lane_p64(
+poly64_t test_vget_lane_p64(poly64x1_t v) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<1 x !u64i>
+// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<1 x !u64i>
+
+// LLVM: [[VGET_LANE:%.*]] = extractelement <1 x i64> %{{.*}}, i32 0
+// LLVM: ret i64 [[VGET_LANE]]
+ return vget_lane_p64(v, 0);
+}
+
+// LLVM-LABEL: @test_vgetq_lane_s64(
+// CIR-LABEL: @test_vgetq_lane_s64(
+int64_t test_vgetq_lane_s64(int64x2_t a) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<2 x !u64i>
+// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<2 x !u64i>
+
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %{{.*}}, i32 1
+// LLVM: ret i64 [[VGETQ_LANE]]
+ return vgetq_lane_s64(a, 1);
+}
+
+// LLVM-LABEL: @test_vgetq_lane_u64(
+// CIR-LABEL: @test_vgetq_lane_u64(
+uint64_t test_vgetq_lane_u64(uint64x2_t a) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<2 x !u64i>
+// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<2 x !u64i>
+
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %{{.*}}, i32 1
+// LLVM: ret i64 [[VGETQ_LANE]]
+ return vgetq_lane_u64(a, 1);
+}
+
+// LLVM-LABEL: @test_vgetq_lane_p64(
+// CIR-LABEL: @test_vgetq_lane_p64(
+poly64_t test_vgetq_lane_p64(poly64x2_t v) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<2 x !u64i>
+// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<2 x !u64i>
+
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %{{.*}}, i32 1
+// LLVM: ret i64 [[VGETQ_LANE]]
+ return vgetq_lane_p64(v, 1);
+}
>From 42e2e3e20b7921fb7d79c6fea2522314e0ffd3d7 Mon Sep 17 00:00:00 2001
From: Ayush3941 <ayushkgaur1 at gmail.com>
Date: Thu, 12 Mar 2026 09:45:55 -0400
Subject: [PATCH 02/17] [CIR][AArch64] Upstream Neon vget_lane/vgetq_lane
builtins v2
---
clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 4 ----
1 file changed, 4 deletions(-)
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index 107271893844d..275bf56411d87 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -2744,10 +2744,6 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupb_laneq_i8:
- cgm.errorNYI(expr->getSourceRange(),
- std::string("unimplemented AArch64 builtin call: ") +
- getContext().BuiltinInfo.getName(builtinID));
- return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_mf8:
case NEON::BI__builtin_neon_vdupb_lane_mf8:
case NEON::BI__builtin_neon_vgetq_lane_mf8:
>From 7f74a5a352a414752a16aa49f0f10c56fdafe664 Mon Sep 17 00:00:00 2001
From: Ayush3941 <ayushkgaur1 at gmail.com>
Date: Thu, 12 Mar 2026 09:58:24 -0400
Subject: [PATCH 03/17] [CIR][AArch64] Upstream Neon vget_lane/vgetq_lane
builtins v2 fixed format
---
.../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 48 +++++++++----------
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index 275bf56411d87..d7347c55de6cd 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -2731,8 +2731,8 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
case NEON::BI__builtin_neon_vget_lane_i8:
ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt8Ty, 8));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
- emitScalarExpr(expr->getArg(1)));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupb_lane_i8:
cgm.errorNYI(expr->getSourceRange(),
std::string("unimplemented AArch64 builtin call: ") +
@@ -2741,8 +2741,8 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
case NEON::BI__builtin_neon_vgetq_lane_i8:
ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt8Ty, 16));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
- emitScalarExpr(expr->getArg(1)));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupb_laneq_i8:
case NEON::BI__builtin_neon_vget_lane_mf8:
case NEON::BI__builtin_neon_vdupb_lane_mf8:
@@ -2754,8 +2754,8 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_i16:
ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt16Ty, 4));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
- emitScalarExpr(expr->getArg(1)));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vduph_lane_i16:
cgm.errorNYI(expr->getSourceRange(),
std::string("unimplemented AArch64 builtin call: ") +
@@ -2763,8 +2763,8 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
return mlir::Value{};
case NEON::BI__builtin_neon_vgetq_lane_i16:
ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt16Ty, 8));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
- emitScalarExpr(expr->getArg(1)));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vduph_laneq_i16:
cgm.errorNYI(expr->getSourceRange(),
std::string("unimplemented AArch64 builtin call: ") +
@@ -2772,8 +2772,8 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_i32:
ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt32Ty, 2));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
- emitScalarExpr(expr->getArg(1)));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdups_lane_i32:
case NEON::BI__builtin_neon_vdups_lane_f32:
cgm.errorNYI(expr->getSourceRange(),
@@ -2782,8 +2782,8 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
return mlir::Value{};
case NEON::BI__builtin_neon_vgetq_lane_i32:
ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt32Ty, 4));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
- emitScalarExpr(expr->getArg(1)));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdups_laneq_i32:
cgm.errorNYI(expr->getSourceRange(),
std::string("unimplemented AArch64 builtin call: ") +
@@ -2791,8 +2791,8 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_i64:
ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt64Ty, 1));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
- emitScalarExpr(expr->getArg(1)));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupd_lane_i64:
case NEON::BI__builtin_neon_vdupd_lane_f64:
cgm.errorNYI(expr->getSourceRange(),
@@ -2801,8 +2801,8 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
return mlir::Value{};
case NEON::BI__builtin_neon_vgetq_lane_i64:
ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt64Ty, 2));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
- emitScalarExpr(expr->getArg(1)));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupd_laneq_i64:
cgm.errorNYI(expr->getSourceRange(),
std::string("unimplemented AArch64 builtin call: ") +
@@ -2810,16 +2810,16 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_f32:
ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(floatTy, 2));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
- emitScalarExpr(expr->getArg(1)));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vget_lane_f64:
ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(doubleTy, 1));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
- emitScalarExpr(expr->getArg(1)));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vgetq_lane_f32:
ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(floatTy, 4));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
- emitScalarExpr(expr->getArg(1)));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdups_laneq_f32:
cgm.errorNYI(expr->getSourceRange(),
std::string("unimplemented AArch64 builtin call: ") +
@@ -2827,8 +2827,8 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
return mlir::Value{};
case NEON::BI__builtin_neon_vgetq_lane_f64:
ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(doubleTy, 2));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()), ops[0],
- emitScalarExpr(expr->getArg(1)));
+ return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupd_laneq_f64:
case NEON::BI__builtin_neon_vaddh_f16:
case NEON::BI__builtin_neon_vsubh_f16:
>From 171931ff99d17d4008d1ec665ef69866fcfa394b Mon Sep 17 00:00:00 2001
From: Ayush3941 <ayushkgaur1 at gmail.com>
Date: Fri, 20 Mar 2026 09:15:18 -0400
Subject: [PATCH 04/17] [CIR][AArch64] Upstream Neon vget_lane/vgetq_lane
builtins v3
---
clang/test/CodeGen/AArch64/neon-vget.c | 155 ------------------
.../AArch64/neon/{neon-vget.c => getset.c} | 84 ++++------
clang/test/CodeGen/AArch64/poly64.c | 20 ---
3 files changed, 29 insertions(+), 230 deletions(-)
rename clang/test/CodeGen/AArch64/neon/{neon-vget.c => getset.c} (82%)
diff --git a/clang/test/CodeGen/AArch64/neon-vget.c b/clang/test/CodeGen/AArch64/neon-vget.c
index ebc8c2f9228ed..df399b3901f74 100644
--- a/clang/test/CodeGen/AArch64/neon-vget.c
+++ b/clang/test/CodeGen/AArch64/neon-vget.c
@@ -6,69 +6,6 @@
#include <arm_neon.h>
-// CHECK-LABEL: define{{.*}} i8 @test_vget_lane_u8(<8 x i8> noundef %a) #0 {
-// CHECK: [[VGET_LANE:%.*]] = extractelement <8 x i8> %a, i32 7
-// CHECK: ret i8 [[VGET_LANE]]
-uint8_t test_vget_lane_u8(uint8x8_t a) {
- return vget_lane_u8(a, 7);
-}
-
-// CHECK-LABEL: define{{.*}} i16 @test_vget_lane_u16(<4 x i16> noundef %a) #0 {
-// CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> %a, i32 3
-// CHECK: ret i16 [[VGET_LANE]]
-uint16_t test_vget_lane_u16(uint16x4_t a) {
- return vget_lane_u16(a, 3);
-}
-
-// CHECK-LABEL: define{{.*}} i32 @test_vget_lane_u32(<2 x i32> noundef %a) #0 {
-// CHECK: [[VGET_LANE:%.*]] = extractelement <2 x i32> %a, i32 1
-// CHECK: ret i32 [[VGET_LANE]]
-uint32_t test_vget_lane_u32(uint32x2_t a) {
- return vget_lane_u32(a, 1);
-}
-
-// CHECK-LABEL: define{{.*}} i8 @test_vget_lane_s8(<8 x i8> noundef %a) #0 {
-// CHECK: [[VGET_LANE:%.*]] = extractelement <8 x i8> %a, i32 7
-// CHECK: ret i8 [[VGET_LANE]]
-int8_t test_vget_lane_s8(int8x8_t a) {
- return vget_lane_s8(a, 7);
-}
-
-// CHECK-LABEL: define{{.*}} i16 @test_vget_lane_s16(<4 x i16> noundef %a) #0 {
-// CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> %a, i32 3
-// CHECK: ret i16 [[VGET_LANE]]
-int16_t test_vget_lane_s16(int16x4_t a) {
- return vget_lane_s16(a, 3);
-}
-
-// CHECK-LABEL: define{{.*}} i32 @test_vget_lane_s32(<2 x i32> noundef %a) #0 {
-// CHECK: [[VGET_LANE:%.*]] = extractelement <2 x i32> %a, i32 1
-// CHECK: ret i32 [[VGET_LANE]]
-int32_t test_vget_lane_s32(int32x2_t a) {
- return vget_lane_s32(a, 1);
-}
-
-// CHECK-LABEL: define{{.*}} i8 @test_vget_lane_p8(<8 x i8> noundef %a) #0 {
-// CHECK: [[VGET_LANE:%.*]] = extractelement <8 x i8> %a, i32 7
-// CHECK: ret i8 [[VGET_LANE]]
-poly8_t test_vget_lane_p8(poly8x8_t a) {
- return vget_lane_p8(a, 7);
-}
-
-// CHECK-LABEL: define{{.*}} i16 @test_vget_lane_p16(<4 x i16> noundef %a) #0 {
-// CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> %a, i32 3
-// CHECK: ret i16 [[VGET_LANE]]
-poly16_t test_vget_lane_p16(poly16x4_t a) {
- return vget_lane_p16(a, 3);
-}
-
-// CHECK-LABEL: define{{.*}} float @test_vget_lane_f32(<2 x float> noundef %a) #0 {
-// CHECK: [[VGET_LANE:%.*]] = extractelement <2 x float> %a, i32 1
-// CHECK: ret float [[VGET_LANE]]
-float32_t test_vget_lane_f32(float32x2_t a) {
- return vget_lane_f32(a, 1);
-}
-
// CHECK-LABEL: define{{.*}} float @test_vget_lane_f16(<4 x half> noundef %a) #0 {
// CHECK: [[__REINT_242:%.*]] = alloca <4 x half>, align 8
// CHECK: [[__REINT1_242:%.*]] = alloca i16, align 2
@@ -83,69 +20,6 @@ float32_t test_vget_lane_f16(float16x4_t a) {
return vget_lane_f16(a, 1);
}
-// CHECK-LABEL: define{{.*}} i8 @test_vgetq_lane_u8(<16 x i8> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %a, i32 15
-// CHECK: ret i8 [[VGETQ_LANE]]
-uint8_t test_vgetq_lane_u8(uint8x16_t a) {
- return vgetq_lane_u8(a, 15);
-}
-
-// CHECK-LABEL: define{{.*}} i16 @test_vgetq_lane_u16(<8 x i16> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %a, i32 7
-// CHECK: ret i16 [[VGETQ_LANE]]
-uint16_t test_vgetq_lane_u16(uint16x8_t a) {
- return vgetq_lane_u16(a, 7);
-}
-
-// CHECK-LABEL: define{{.*}} i32 @test_vgetq_lane_u32(<4 x i32> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %a, i32 3
-// CHECK: ret i32 [[VGETQ_LANE]]
-uint32_t test_vgetq_lane_u32(uint32x4_t a) {
- return vgetq_lane_u32(a, 3);
-}
-
-// CHECK-LABEL: define{{.*}} i8 @test_vgetq_lane_s8(<16 x i8> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %a, i32 15
-// CHECK: ret i8 [[VGETQ_LANE]]
-int8_t test_vgetq_lane_s8(int8x16_t a) {
- return vgetq_lane_s8(a, 15);
-}
-
-// CHECK-LABEL: define{{.*}} i16 @test_vgetq_lane_s16(<8 x i16> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %a, i32 7
-// CHECK: ret i16 [[VGETQ_LANE]]
-int16_t test_vgetq_lane_s16(int16x8_t a) {
- return vgetq_lane_s16(a, 7);
-}
-
-// CHECK-LABEL: define{{.*}} i32 @test_vgetq_lane_s32(<4 x i32> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %a, i32 3
-// CHECK: ret i32 [[VGETQ_LANE]]
-int32_t test_vgetq_lane_s32(int32x4_t a) {
- return vgetq_lane_s32(a, 3);
-}
-
-// CHECK-LABEL: define{{.*}} i8 @test_vgetq_lane_p8(<16 x i8> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %a, i32 15
-// CHECK: ret i8 [[VGETQ_LANE]]
-poly8_t test_vgetq_lane_p8(poly8x16_t a) {
- return vgetq_lane_p8(a, 15);
-}
-
-// CHECK-LABEL: define{{.*}} i16 @test_vgetq_lane_p16(<8 x i16> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %a, i32 7
-// CHECK: ret i16 [[VGETQ_LANE]]
-poly16_t test_vgetq_lane_p16(poly16x8_t a) {
- return vgetq_lane_p16(a, 7);
-}
-
-// CHECK-LABEL: define{{.*}} float @test_vgetq_lane_f32(<4 x float> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x float> %a, i32 3
-// CHECK: ret float [[VGETQ_LANE]]
-float32_t test_vgetq_lane_f32(float32x4_t a) {
- return vgetq_lane_f32(a, 3);
-}
-
// CHECK-LABEL: define{{.*}} float @test_vgetq_lane_f16(<8 x half> noundef %a) #0 {
// CHECK: [[__REINT_244:%.*]] = alloca <8 x half>, align 16
// CHECK: [[__REINT1_244:%.*]] = alloca i16, align 2
@@ -160,35 +34,6 @@ float32_t test_vgetq_lane_f16(float16x8_t a) {
return vgetq_lane_f16(a, 3);
}
-// CHECK-LABEL: define{{.*}} i64 @test_vget_lane_s64(<1 x i64> noundef %a) #0 {
-// CHECK: [[VGET_LANE:%.*]] = extractelement <1 x i64> %a, i32 0
-// CHECK: ret i64 [[VGET_LANE]]
-int64_t test_vget_lane_s64(int64x1_t a) {
- return vget_lane_s64(a, 0);
-}
-
-// CHECK-LABEL: define{{.*}} i64 @test_vget_lane_u64(<1 x i64> noundef %a) #0 {
-// CHECK: [[VGET_LANE:%.*]] = extractelement <1 x i64> %a, i32 0
-// CHECK: ret i64 [[VGET_LANE]]
-uint64_t test_vget_lane_u64(uint64x1_t a) {
- return vget_lane_u64(a, 0);
-}
-
-// CHECK-LABEL: define{{.*}} i64 @test_vgetq_lane_s64(<2 x i64> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %a, i32 1
-// CHECK: ret i64 [[VGETQ_LANE]]
-int64_t test_vgetq_lane_s64(int64x2_t a) {
- return vgetq_lane_s64(a, 1);
-}
-
-// CHECK-LABEL: define{{.*}} i64 @test_vgetq_lane_u64(<2 x i64> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %a, i32 1
-// CHECK: ret i64 [[VGETQ_LANE]]
-uint64_t test_vgetq_lane_u64(uint64x2_t a) {
- return vgetq_lane_u64(a, 1);
-}
-
-
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vset_lane_u8(i8 noundef %a, <8 x i8> noundef %b) #0 {
// CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i8> %b, i8 %a, i32 7
// CHECK: ret <8 x i8> [[VSET_LANE]]
diff --git a/clang/test/CodeGen/AArch64/neon/neon-vget.c b/clang/test/CodeGen/AArch64/neon/getset.c
similarity index 82%
rename from clang/test/CodeGen/AArch64/neon/neon-vget.c
rename to clang/test/CodeGen/AArch64/neon/getset.c
index 297a07ced2f41..0f697cbcf87e0 100644
--- a/clang/test/CodeGen/AArch64/neon/neon-vget.c
+++ b/clang/test/CodeGen/AArch64/neon/getset.c
@@ -1,8 +1,8 @@
// REQUIRES: aarch64-registered-target || arm-registered-target
-// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=LLVM
-// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -fclangir -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=LLVM %}
-// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -fclangir -emit-cir -o - %s | FileCheck %s --check-prefixes=CIR %}
+// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM
+// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -fclangir -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM %}
+// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -fclangir -emit-cir -o - %s | FileCheck %s --check-prefixes=ALL,CIR %}
//=============================================================================
// NOTES
@@ -25,8 +25,7 @@
// Extract one element from vector
//===------------------------------------------------------===//
-// LLVM-LABEL: @test_vget_lane_u8(
-// CIR-LABEL: @test_vget_lane_u8(
+// ALL-LABEL: @test_vget_lane_u8(
uint8_t test_vget_lane_u8(uint8x8_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<8 x !u8i>
@@ -35,8 +34,7 @@ uint8_t test_vget_lane_u8(uint8x8_t a) {
return vget_lane_u8(a, 7);
}
-// LLVM-LABEL: @test_vget_lane_u16(
-// CIR-LABEL: @test_vget_lane_u16(
+// ALL-LABEL: @test_vget_lane_u16(
uint16_t test_vget_lane_u16(uint16x4_t a) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !u16i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u16i>
@@ -46,8 +44,7 @@ uint16_t test_vget_lane_u16(uint16x4_t a) {
return vget_lane_u16(a, 3);
}
-// LLVM-LABEL: @test_vget_lane_u32(
-// CIR-LABEL: @test_vget_lane_u32(
+// ALL-LABEL: @test_vget_lane_u32(
uint32_t test_vget_lane_u32(uint32x2_t a) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<2 x !u32i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<2 x !u32i>
@@ -57,8 +54,7 @@ uint32_t test_vget_lane_u32(uint32x2_t a) {
return vget_lane_u32(a, 1);
}
-// LLVM-LABEL: @test_vget_lane_s8(
-// CIR-LABEL: @test_vget_lane_s8(
+// ALL-LABEL: @test_vget_lane_s8(
int8_t test_vget_lane_s8(int8x8_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<8 x !u8i>
@@ -67,8 +63,7 @@ int8_t test_vget_lane_s8(int8x8_t a) {
return vget_lane_s8(a, 7);
}
-// LLVM-LABEL: @test_vget_lane_s16(
-// CIR-LABEL: @test_vget_lane_s16(
+// ALL-LABEL: @test_vget_lane_s16(
int16_t test_vget_lane_s16(int16x4_t a) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !u16i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u16i>
@@ -78,8 +73,7 @@ int16_t test_vget_lane_s16(int16x4_t a) {
return vget_lane_s16(a, 3);
}
-// LLVM-LABEL: @test_vget_lane_s32(
-// CIR-LABEL: @test_vget_lane_s32(
+// ALL-LABEL: @test_vget_lane_s32(
int32_t test_vget_lane_s32(int32x2_t a) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<2 x !u32i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<2 x !u32i>
@@ -89,8 +83,7 @@ int32_t test_vget_lane_s32(int32x2_t a) {
return vget_lane_s32(a, 1);
}
-// LLVM-LABEL: @test_vget_lane_p8(
-// CIR-LABEL: @test_vget_lane_p8(
+// ALL-LABEL: @test_vget_lane_p8(
poly8_t test_vget_lane_p8(poly8x8_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<8 x !u8i>
@@ -99,8 +92,7 @@ poly8_t test_vget_lane_p8(poly8x8_t a) {
return vget_lane_p8(a, 7);
}
-// LLVM-LABEL: @test_vget_lane_p16(
-// CIR-LABEL: @test_vget_lane_p16(
+// ALL-LABEL: @test_vget_lane_p16(
poly16_t test_vget_lane_p16(poly16x4_t a) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !u16i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u16i>
@@ -110,8 +102,7 @@ poly16_t test_vget_lane_p16(poly16x4_t a) {
return vget_lane_p16(a, 3);
}
-// LLVM-LABEL: @test_vget_lane_f32(
-// CIR-LABEL: @test_vget_lane_f32(
+// ALL-LABEL: @test_vget_lane_f32(
float32_t test_vget_lane_f32(float32x2_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<2 x !cir.float>
@@ -120,8 +111,7 @@ float32_t test_vget_lane_f32(float32x2_t a) {
return vget_lane_f32(a, 1);
}
-// LLVM-LABEL: @test_vget_lane_f64(
-// CIR-LABEL: @test_vget_lane_f64(
+// ALL-LABEL: @test_vget_lane_f64(
float64_t test_vget_lane_f64(float64x1_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<1 x !cir.double>
@@ -130,8 +120,7 @@ float64_t test_vget_lane_f64(float64x1_t a) {
return vget_lane_f64(a, 0);
}
-// LLVM-LABEL: @test_vgetq_lane_u8(
-// CIR-LABEL: @test_vgetq_lane_u8(
+// ALL-LABEL: @test_vgetq_lane_u8(
uint8_t test_vgetq_lane_u8(uint8x16_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<16 x !u8i>
@@ -140,8 +129,7 @@ uint8_t test_vgetq_lane_u8(uint8x16_t a) {
return vgetq_lane_u8(a, 15);
}
-// LLVM-LABEL: @test_vgetq_lane_u16(
-// CIR-LABEL: @test_vgetq_lane_u16(
+// ALL-LABEL: @test_vgetq_lane_u16(
uint16_t test_vgetq_lane_u16(uint16x8_t a) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<8 x !u16i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<8 x !u16i>
@@ -151,8 +139,7 @@ uint16_t test_vgetq_lane_u16(uint16x8_t a) {
return vgetq_lane_u16(a, 7);
}
-// LLVM-LABEL: @test_vgetq_lane_u32(
-// CIR-LABEL: @test_vgetq_lane_u32(
+// ALL-LABEL: @test_vgetq_lane_u32(
uint32_t test_vgetq_lane_u32(uint32x4_t a) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !u32i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u32i>
@@ -162,8 +149,7 @@ uint32_t test_vgetq_lane_u32(uint32x4_t a) {
return vgetq_lane_u32(a, 3);
}
-// LLVM-LABEL: @test_vgetq_lane_s8(
-// CIR-LABEL: @test_vgetq_lane_s8(
+// ALL-LABEL: @test_vgetq_lane_s8(
int8_t test_vgetq_lane_s8(int8x16_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<16 x !u8i>
@@ -172,8 +158,7 @@ int8_t test_vgetq_lane_s8(int8x16_t a) {
return vgetq_lane_s8(a, 15);
}
-// LLVM-LABEL: @test_vgetq_lane_s16(
-// CIR-LABEL: @test_vgetq_lane_s16(
+// ALL-LABEL: @test_vgetq_lane_s16(
int16_t test_vgetq_lane_s16(int16x8_t a) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<8 x !u16i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<8 x !u16i>
@@ -183,8 +168,7 @@ int16_t test_vgetq_lane_s16(int16x8_t a) {
return vgetq_lane_s16(a, 7);
}
-// LLVM-LABEL: @test_vgetq_lane_s32(
-// CIR-LABEL: @test_vgetq_lane_s32(
+// ALL-LABEL: @test_vgetq_lane_s32(
int32_t test_vgetq_lane_s32(int32x4_t a) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !u32i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u32i>
@@ -194,8 +178,7 @@ int32_t test_vgetq_lane_s32(int32x4_t a) {
return vgetq_lane_s32(a, 3);
}
-// LLVM-LABEL: @test_vgetq_lane_p8(
-// CIR-LABEL: @test_vgetq_lane_p8(
+// ALL-LABEL: @test_vgetq_lane_p8(
poly8_t test_vgetq_lane_p8(poly8x16_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<16 x !u8i>
@@ -204,8 +187,7 @@ poly8_t test_vgetq_lane_p8(poly8x16_t a) {
return vgetq_lane_p8(a, 15);
}
-// LLVM-LABEL: @test_vgetq_lane_p16(
-// CIR-LABEL: @test_vgetq_lane_p16(
+// ALL-LABEL: @test_vgetq_lane_p16(
poly16_t test_vgetq_lane_p16(poly16x8_t a) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<8 x !u16i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<8 x !u16i>
@@ -215,8 +197,7 @@ poly16_t test_vgetq_lane_p16(poly16x8_t a) {
return vgetq_lane_p16(a, 7);
}
-// LLVM-LABEL: @test_vgetq_lane_f32(
-// CIR-LABEL: @test_vgetq_lane_f32(
+// ALL-LABEL: @test_vgetq_lane_f32(
float32_t test_vgetq_lane_f32(float32x4_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<4 x !cir.float>
@@ -225,8 +206,7 @@ float32_t test_vgetq_lane_f32(float32x4_t a) {
return vgetq_lane_f32(a, 3);
}
-// LLVM-LABEL: @test_vgetq_lane_f64(
-// CIR-LABEL: @test_vgetq_lane_f64(
+// ALL-LABEL: @test_vgetq_lane_f64(
float64_t test_vgetq_lane_f64(float64x2_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<2 x !cir.double>
@@ -235,8 +215,7 @@ float64_t test_vgetq_lane_f64(float64x2_t a) {
return vgetq_lane_f64(a, 1);
}
-// LLVM-LABEL: @test_vget_lane_s64(
-// CIR-LABEL: @test_vget_lane_s64(
+// ALL-LABEL: @test_vget_lane_s64(
int64_t test_vget_lane_s64(int64x1_t a) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<1 x !u64i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<1 x !u64i>
@@ -246,8 +225,7 @@ int64_t test_vget_lane_s64(int64x1_t a) {
return vget_lane_s64(a, 0);
}
-// LLVM-LABEL: @test_vget_lane_u64(
-// CIR-LABEL: @test_vget_lane_u64(
+// ALL-LABEL: @test_vget_lane_u64(
uint64_t test_vget_lane_u64(uint64x1_t a) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<1 x !u64i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<1 x !u64i>
@@ -257,8 +235,7 @@ uint64_t test_vget_lane_u64(uint64x1_t a) {
return vget_lane_u64(a, 0);
}
-// LLVM-LABEL: @test_vget_lane_p64(
-// CIR-LABEL: @test_vget_lane_p64(
+// ALL-LABEL: @test_vget_lane_p64(
poly64_t test_vget_lane_p64(poly64x1_t v) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<1 x !u64i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<1 x !u64i>
@@ -268,8 +245,7 @@ poly64_t test_vget_lane_p64(poly64x1_t v) {
return vget_lane_p64(v, 0);
}
-// LLVM-LABEL: @test_vgetq_lane_s64(
-// CIR-LABEL: @test_vgetq_lane_s64(
+// ALL-LABEL: @test_vgetq_lane_s64(
int64_t test_vgetq_lane_s64(int64x2_t a) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<2 x !u64i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<2 x !u64i>
@@ -279,8 +255,7 @@ int64_t test_vgetq_lane_s64(int64x2_t a) {
return vgetq_lane_s64(a, 1);
}
-// LLVM-LABEL: @test_vgetq_lane_u64(
-// CIR-LABEL: @test_vgetq_lane_u64(
+// ALL-LABEL: @test_vgetq_lane_u64(
uint64_t test_vgetq_lane_u64(uint64x2_t a) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<2 x !u64i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<2 x !u64i>
@@ -290,8 +265,7 @@ uint64_t test_vgetq_lane_u64(uint64x2_t a) {
return vgetq_lane_u64(a, 1);
}
-// LLVM-LABEL: @test_vgetq_lane_p64(
-// CIR-LABEL: @test_vgetq_lane_p64(
+// ALL-LABEL: @test_vgetq_lane_p64(
poly64_t test_vgetq_lane_p64(poly64x2_t v) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<2 x !u64i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<2 x !u64i>
diff --git a/clang/test/CodeGen/AArch64/poly64.c b/clang/test/CodeGen/AArch64/poly64.c
index 00838b648dfe6..67c9afd188381 100644
--- a/clang/test/CodeGen/AArch64/poly64.c
+++ b/clang/test/CodeGen/AArch64/poly64.c
@@ -99,26 +99,6 @@ poly64x2_t test_vbslq_p64(poly64x2_t a, poly64x2_t b, poly64x2_t c) {
return vbslq_p64(a, b, c);
}
-// CHECK-LABEL: define dso_local i64 @test_vget_lane_p64(
-// CHECK-SAME: <1 x i64> noundef [[V:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <1 x i64> [[V]], i32 0
-// CHECK-NEXT: ret i64 [[VGET_LANE]]
-//
-poly64_t test_vget_lane_p64(poly64x1_t v) {
- return vget_lane_p64(v, 0);
-}
-
-// CHECK-LABEL: define dso_local i64 @test_vgetq_lane_p64(
-// CHECK-SAME: <2 x i64> noundef [[V:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> [[V]], i32 1
-// CHECK-NEXT: ret i64 [[VGETQ_LANE]]
-//
-poly64_t test_vgetq_lane_p64(poly64x2_t v) {
- return vgetq_lane_p64(v, 1);
-}
-
// CHECK-LABEL: define dso_local <1 x i64> @test_vset_lane_p64(
// CHECK-SAME: i64 noundef [[A:%.*]], <1 x i64> noundef [[V:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
>From 45f3d2135eeeb55825068d3e455495c3a8a6045a Mon Sep 17 00:00:00 2001
From: Ayush3941 <ayushkgaur1 at gmail.com>
Date: Fri, 20 Mar 2026 10:04:39 -0400
Subject: [PATCH 05/17] [CIR][AArch64] Upstream Neon vget_lane/vgetq_lane
builtins v3.5
---
clang/test/CodeGen/AArch64/neon-vget.c | 28 ------------------
clang/test/CodeGen/AArch64/neon/getset.c | 37 ++++++++++++++++++++----
2 files changed, 32 insertions(+), 33 deletions(-)
diff --git a/clang/test/CodeGen/AArch64/neon-vget.c b/clang/test/CodeGen/AArch64/neon-vget.c
index df399b3901f74..9d5c5e61a2dcd 100644
--- a/clang/test/CodeGen/AArch64/neon-vget.c
+++ b/clang/test/CodeGen/AArch64/neon-vget.c
@@ -6,34 +6,6 @@
#include <arm_neon.h>
-// CHECK-LABEL: define{{.*}} float @test_vget_lane_f16(<4 x half> noundef %a) #0 {
-// CHECK: [[__REINT_242:%.*]] = alloca <4 x half>, align 8
-// CHECK: [[__REINT1_242:%.*]] = alloca i16, align 2
-// CHECK: store <4 x half> %a, ptr [[__REINT_242]], align 8
-// CHECK: [[TMP1:%.*]] = load <4 x i16>, ptr [[__REINT_242]], align 8
-// CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> [[TMP1]], i32 1
-// CHECK: store i16 [[VGET_LANE]], ptr [[__REINT1_242]], align 2
-// CHECK: [[TMP5:%.*]] = load half, ptr [[__REINT1_242]], align 2
-// CHECK: [[CONV:%.*]] = fpext half [[TMP5]] to float
-// CHECK: ret float [[CONV]]
-float32_t test_vget_lane_f16(float16x4_t a) {
- return vget_lane_f16(a, 1);
-}
-
-// CHECK-LABEL: define{{.*}} float @test_vgetq_lane_f16(<8 x half> noundef %a) #0 {
-// CHECK: [[__REINT_244:%.*]] = alloca <8 x half>, align 16
-// CHECK: [[__REINT1_244:%.*]] = alloca i16, align 2
-// CHECK: store <8 x half> %a, ptr [[__REINT_244]], align 16
-// CHECK: [[TMP1:%.*]] = load <8 x i16>, ptr [[__REINT_244]], align 16
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> [[TMP1]], i32 3
-// CHECK: store i16 [[VGETQ_LANE]], ptr [[__REINT1_244]], align 2
-// CHECK: [[TMP5:%.*]] = load half, ptr [[__REINT1_244]], align 2
-// CHECK: [[CONV:%.*]] = fpext half [[TMP5]] to float
-// CHECK: ret float [[CONV]]
-float32_t test_vgetq_lane_f16(float16x8_t a) {
- return vgetq_lane_f16(a, 3);
-}
-
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vset_lane_u8(i8 noundef %a, <8 x i8> noundef %b) #0 {
// CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i8> %b, i8 %a, i32 7
// CHECK: ret <8 x i8> [[VSET_LANE]]
diff --git a/clang/test/CodeGen/AArch64/neon/getset.c b/clang/test/CodeGen/AArch64/neon/getset.c
index 0f697cbcf87e0..b7d5870581caf 100644
--- a/clang/test/CodeGen/AArch64/neon/getset.c
+++ b/clang/test/CodeGen/AArch64/neon/getset.c
@@ -12,11 +12,6 @@
// * clang/test/CodeGen/AArch64/poly64.c
// The main difference is the use of RUN lines that enable ClangIR lowering;
// therefore only builtins currently supported by ClangIR are tested here.
-//
-// The half-precision extract variants are intentionally omitted here because
-// they lower through the vduph_* builtin IDs, which are still unsupported in
-// CIR for this patch.
-//
//=============================================================================
#include <arm_neon.h>
@@ -102,6 +97,22 @@ poly16_t test_vget_lane_p16(poly16x4_t a) {
return vget_lane_p16(a, 3);
}
+// ALL-LABEL: @test_vget_lane_f16(
+float32_t test_vget_lane_f16(float16x4_t a) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !u16i>
+// CIR: [[ELEM:%.*]] = cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u16i>
+// CIR: [[HALF:%.*]] = cir.cast bitcast [[ELEM]] : !u16i -> !cir.f16
+// CIR: [[RES:%.*]] = cir.cast floating [[HALF]] : !cir.f16 -> !cir.float
+// CIR: cir.return [[RES]] : !cir.float
+
+// LLVM: [[TMP:%.*]] = bitcast <4 x half> %{{.*}} to <4 x i16>
+// LLVM: [[VGET_LANE:%.*]] = extractelement <4 x i16> [[TMP]], i32 1
+// LLVM: [[HALF:%.*]] = bitcast i16 [[VGET_LANE]] to half
+// LLVM: [[RES:%.*]] = fpext half [[HALF]] to float
+// LLVM: ret float [[RES]]
+ return vget_lane_f16(a, 1);
+}
+
// ALL-LABEL: @test_vget_lane_f32(
float32_t test_vget_lane_f32(float32x2_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<2 x !cir.float>
@@ -197,6 +208,22 @@ poly16_t test_vgetq_lane_p16(poly16x8_t a) {
return vgetq_lane_p16(a, 7);
}
+// ALL-LABEL: @test_vgetq_lane_f16(
+float32_t test_vgetq_lane_f16(float16x8_t a) {
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<8 x !u16i>
+// CIR: [[ELEM:%.*]] = cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<8 x !u16i>
+// CIR: [[HALF:%.*]] = cir.cast bitcast [[ELEM]] : !u16i -> !cir.f16
+// CIR: [[RES:%.*]] = cir.cast floating [[HALF]] : !cir.f16 -> !cir.float
+// CIR: cir.return [[RES]] : !cir.float
+
+// LLVM: [[TMP:%.*]] = bitcast <8 x half> %{{.*}} to <8 x i16>
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> [[TMP]], i32 3
+// LLVM: [[HALF:%.*]] = bitcast i16 [[VGETQ_LANE]] to half
+// LLVM: [[RES:%.*]] = fpext half [[HALF]] to float
+// LLVM: ret float [[RES]]
+ return vgetq_lane_f16(a, 3);
+}
+
// ALL-LABEL: @test_vgetq_lane_f32(
float32_t test_vgetq_lane_f32(float32x4_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<4 x !cir.float>
>From fea714fe8587b7bfbdb47b2878b62ce6767084fa Mon Sep 17 00:00:00 2001
From: Ayush3941 <ayushkgaur1 at gmail.com>
Date: Fri, 20 Mar 2026 13:08:46 -0400
Subject: [PATCH 06/17] [CIR][AArch64] Upstream Neon vget_lane/vgetq_lane
builtins v3.5 fixed test
---
clang/test/CodeGen/AArch64/neon/getset.c | 20 ++++++++++++++------
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/clang/test/CodeGen/AArch64/neon/getset.c b/clang/test/CodeGen/AArch64/neon/getset.c
index b7d5870581caf..ad628f5553256 100644
--- a/clang/test/CodeGen/AArch64/neon/getset.c
+++ b/clang/test/CodeGen/AArch64/neon/getset.c
@@ -101,9 +101,13 @@ poly16_t test_vget_lane_p16(poly16x4_t a) {
float32_t test_vget_lane_f16(float16x4_t a) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !u16i>
// CIR: [[ELEM:%.*]] = cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u16i>
-// CIR: [[HALF:%.*]] = cir.cast bitcast [[ELEM]] : !u16i -> !cir.f16
-// CIR: [[RES:%.*]] = cir.cast floating [[HALF]] : !cir.f16 -> !cir.float
-// CIR: cir.return [[RES]] : !cir.float
+// CIR: cir.store align(2) [[ELEM]], %{{.*}} : !u16i, !cir.ptr<!u16i>
+// CIR: [[S16PTR:%.*]] = cir.cast bitcast %{{.*}} : !cir.ptr<!u16i> -> !cir.ptr<!s16i>
+// CIR: %{{.*}} = cir.load align(2) [[S16PTR]] : !cir.ptr<!s16i>, !s16i
+// CIR: [[F16PTR:%.*]] = cir.cast bitcast %{{.*}} : !cir.ptr<!s16i> -> !cir.ptr<!cir.f16>
+// CIR: [[HALF:%.*]] = cir.load align(2) [[F16PTR]] : !cir.ptr<!cir.f16>, !cir.f16
+// CIR: %{{.*}} = cir.cast floating %{{.*}} : !cir.f16 -> !cir.float
+// CIR: cir.return %{{.*}} : !cir.float
// LLVM: [[TMP:%.*]] = bitcast <4 x half> %{{.*}} to <4 x i16>
// LLVM: [[VGET_LANE:%.*]] = extractelement <4 x i16> [[TMP]], i32 1
@@ -212,9 +216,13 @@ poly16_t test_vgetq_lane_p16(poly16x8_t a) {
float32_t test_vgetq_lane_f16(float16x8_t a) {
// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<8 x !u16i>
// CIR: [[ELEM:%.*]] = cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<8 x !u16i>
-// CIR: [[HALF:%.*]] = cir.cast bitcast [[ELEM]] : !u16i -> !cir.f16
-// CIR: [[RES:%.*]] = cir.cast floating [[HALF]] : !cir.f16 -> !cir.float
-// CIR: cir.return [[RES]] : !cir.float
+// CIR: cir.store align(2) [[ELEM]], %{{.*}} : !u16i, !cir.ptr<!u16i>
+// CIR: [[S16PTR:%.*]] = cir.cast bitcast %{{.*}} : !cir.ptr<!u16i> -> !cir.ptr<!s16i>
+// CIR: %{{.*}} = cir.load align(2) [[S16PTR]] : !cir.ptr<!s16i>, !s16i
+// CIR: [[F16PTR:%.*]] = cir.cast bitcast %{{.*}} : !cir.ptr<!s16i> -> !cir.ptr<!cir.f16>
+// CIR: [[HALF:%.*]] = cir.load align(2) [[F16PTR]] : !cir.ptr<!cir.f16>, !cir.f16
+// CIR: %{{.*}} = cir.cast floating %{{.*}} : !cir.f16 -> !cir.float
+// CIR: cir.return %{{.*}} : !cir.float
// LLVM: [[TMP:%.*]] = bitcast <8 x half> %{{.*}} to <8 x i16>
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> [[TMP]], i32 3
>From a9871eeb77d41c21081c9840f61656764fc59faf Mon Sep 17 00:00:00 2001
From: Ayush3941 <ayushkgaur1 at gmail.com>
Date: Sat, 21 Mar 2026 15:23:18 -0400
Subject: [PATCH 07/17] [CIR][AArch64] Upstream Neon vget_lane/vgetq_lane
builtins v4 fixed test
---
clang/test/CodeGen/AArch64/neon/getset.c | 36 ++++++++++++------------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/clang/test/CodeGen/AArch64/neon/getset.c b/clang/test/CodeGen/AArch64/neon/getset.c
index ad628f5553256..a4a684a316efa 100644
--- a/clang/test/CodeGen/AArch64/neon/getset.c
+++ b/clang/test/CodeGen/AArch64/neon/getset.c
@@ -31,7 +31,7 @@ uint8_t test_vget_lane_u8(uint8x8_t a) {
// ALL-LABEL: @test_vget_lane_u16(
uint16_t test_vget_lane_u16(uint16x4_t a) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !u16i>
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<4 x !s16i> -> !cir.vector<4 x !u16i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u16i>
// LLVM: [[VGET_LANE:%.*]] = extractelement <4 x i16> %{{.*}}, i32 3
@@ -41,7 +41,7 @@ uint16_t test_vget_lane_u16(uint16x4_t a) {
// ALL-LABEL: @test_vget_lane_u32(
uint32_t test_vget_lane_u32(uint32x2_t a) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<2 x !u32i>
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<2 x !s32i> -> !cir.vector<2 x !u32i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<2 x !u32i>
// LLVM: [[VGET_LANE:%.*]] = extractelement <2 x i32> %{{.*}}, i32 1
@@ -60,7 +60,7 @@ int8_t test_vget_lane_s8(int8x8_t a) {
// ALL-LABEL: @test_vget_lane_s16(
int16_t test_vget_lane_s16(int16x4_t a) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !u16i>
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<4 x !s16i> -> !cir.vector<4 x !u16i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u16i>
// LLVM: [[VGET_LANE:%.*]] = extractelement <4 x i16> %{{.*}}, i32 3
@@ -70,7 +70,7 @@ int16_t test_vget_lane_s16(int16x4_t a) {
// ALL-LABEL: @test_vget_lane_s32(
int32_t test_vget_lane_s32(int32x2_t a) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<2 x !u32i>
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<2 x !s32i> -> !cir.vector<2 x !u32i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<2 x !u32i>
// LLVM: [[VGET_LANE:%.*]] = extractelement <2 x i32> %{{.*}}, i32 1
@@ -89,7 +89,7 @@ poly8_t test_vget_lane_p8(poly8x8_t a) {
// ALL-LABEL: @test_vget_lane_p16(
poly16_t test_vget_lane_p16(poly16x4_t a) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !u16i>
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<4 x !s16i> -> !cir.vector<4 x !u16i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u16i>
// LLVM: [[VGET_LANE:%.*]] = extractelement <4 x i16> %{{.*}}, i32 3
@@ -99,7 +99,7 @@ poly16_t test_vget_lane_p16(poly16x4_t a) {
// ALL-LABEL: @test_vget_lane_f16(
float32_t test_vget_lane_f16(float16x4_t a) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !u16i>
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<4 x !s16i> -> !cir.vector<4 x !u16i>
// CIR: [[ELEM:%.*]] = cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u16i>
// CIR: cir.store align(2) [[ELEM]], %{{.*}} : !u16i, !cir.ptr<!u16i>
// CIR: [[S16PTR:%.*]] = cir.cast bitcast %{{.*}} : !cir.ptr<!u16i> -> !cir.ptr<!s16i>
@@ -146,7 +146,7 @@ uint8_t test_vgetq_lane_u8(uint8x16_t a) {
// ALL-LABEL: @test_vgetq_lane_u16(
uint16_t test_vgetq_lane_u16(uint16x8_t a) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<8 x !u16i>
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<8 x !s16i> -> !cir.vector<8 x !u16i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<8 x !u16i>
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %{{.*}}, i32 7
@@ -156,7 +156,7 @@ uint16_t test_vgetq_lane_u16(uint16x8_t a) {
// ALL-LABEL: @test_vgetq_lane_u32(
uint32_t test_vgetq_lane_u32(uint32x4_t a) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !u32i>
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<4 x !s32i> -> !cir.vector<4 x !u32i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u32i>
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %{{.*}}, i32 3
@@ -175,7 +175,7 @@ int8_t test_vgetq_lane_s8(int8x16_t a) {
// ALL-LABEL: @test_vgetq_lane_s16(
int16_t test_vgetq_lane_s16(int16x8_t a) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<8 x !u16i>
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<8 x !s16i> -> !cir.vector<8 x !u16i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<8 x !u16i>
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %{{.*}}, i32 7
@@ -185,7 +185,7 @@ int16_t test_vgetq_lane_s16(int16x8_t a) {
// ALL-LABEL: @test_vgetq_lane_s32(
int32_t test_vgetq_lane_s32(int32x4_t a) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !u32i>
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<4 x !s32i> -> !cir.vector<4 x !u32i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u32i>
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %{{.*}}, i32 3
@@ -204,7 +204,7 @@ poly8_t test_vgetq_lane_p8(poly8x16_t a) {
// ALL-LABEL: @test_vgetq_lane_p16(
poly16_t test_vgetq_lane_p16(poly16x8_t a) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<8 x !u16i>
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<8 x !s16i> -> !cir.vector<8 x !u16i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<8 x !u16i>
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %{{.*}}, i32 7
@@ -214,7 +214,7 @@ poly16_t test_vgetq_lane_p16(poly16x8_t a) {
// ALL-LABEL: @test_vgetq_lane_f16(
float32_t test_vgetq_lane_f16(float16x8_t a) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<8 x !u16i>
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<8 x !s16i> -> !cir.vector<8 x !u16i>
// CIR: [[ELEM:%.*]] = cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<8 x !u16i>
// CIR: cir.store align(2) [[ELEM]], %{{.*}} : !u16i, !cir.ptr<!u16i>
// CIR: [[S16PTR:%.*]] = cir.cast bitcast %{{.*}} : !cir.ptr<!u16i> -> !cir.ptr<!s16i>
@@ -252,7 +252,7 @@ float64_t test_vgetq_lane_f64(float64x2_t a) {
// ALL-LABEL: @test_vget_lane_s64(
int64_t test_vget_lane_s64(int64x1_t a) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<1 x !u64i>
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<1 x !s64i> -> !cir.vector<1 x !u64i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<1 x !u64i>
// LLVM: [[VGET_LANE:%.*]] = extractelement <1 x i64> %{{.*}}, i32 0
@@ -262,7 +262,7 @@ int64_t test_vget_lane_s64(int64x1_t a) {
// ALL-LABEL: @test_vget_lane_u64(
uint64_t test_vget_lane_u64(uint64x1_t a) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<1 x !u64i>
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<1 x !s64i> -> !cir.vector<1 x !u64i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<1 x !u64i>
// LLVM: [[VGET_LANE:%.*]] = extractelement <1 x i64> %{{.*}}, i32 0
@@ -272,7 +272,7 @@ uint64_t test_vget_lane_u64(uint64x1_t a) {
// ALL-LABEL: @test_vget_lane_p64(
poly64_t test_vget_lane_p64(poly64x1_t v) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<1 x !u64i>
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<1 x !s64i> -> !cir.vector<1 x !u64i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<1 x !u64i>
// LLVM: [[VGET_LANE:%.*]] = extractelement <1 x i64> %{{.*}}, i32 0
@@ -282,7 +282,7 @@ poly64_t test_vget_lane_p64(poly64x1_t v) {
// ALL-LABEL: @test_vgetq_lane_s64(
int64_t test_vgetq_lane_s64(int64x2_t a) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<2 x !u64i>
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<2 x !s64i> -> !cir.vector<2 x !u64i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<2 x !u64i>
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %{{.*}}, i32 1
@@ -292,7 +292,7 @@ int64_t test_vgetq_lane_s64(int64x2_t a) {
// ALL-LABEL: @test_vgetq_lane_u64(
uint64_t test_vgetq_lane_u64(uint64x2_t a) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<2 x !u64i>
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<2 x !s64i> -> !cir.vector<2 x !u64i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<2 x !u64i>
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %{{.*}}, i32 1
@@ -302,7 +302,7 @@ uint64_t test_vgetq_lane_u64(uint64x2_t a) {
// ALL-LABEL: @test_vgetq_lane_p64(
poly64_t test_vgetq_lane_p64(poly64x2_t v) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<2 x !u64i>
+// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<2 x !s64i> -> !cir.vector<2 x !u64i>
// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<2 x !u64i>
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %{{.*}}, i32 1
>From bccf84b73c810e620699cefa50f580d598ac7d10 Mon Sep 17 00:00:00 2001
From: Ayush3941 <ayushkgaur1 at gmail.com>
Date: Mon, 23 Mar 2026 15:03:13 -0400
Subject: [PATCH 08/17] [CIR][AArch64] Upstream Neon vget_lane/vgetq_lane
builtins v5 fixed test
---
.../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 104 ++++++++++++------
1 file changed, 68 insertions(+), 36 deletions(-)
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index d7347c55de6cd..da5473394c4ea 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -1298,6 +1298,50 @@ static bool hasExtraNeonArgument(unsigned builtinID) {
return mask != 0;
}
+static cir::VectorType getAArch64GetLaneVectorType(CIRGenFunction &cgf,
+ unsigned builtinID) {
+ switch (builtinID) {
+ case NEON::BI__builtin_neon_vget_lane_i8:
+ return cir::VectorType::get(cgf.uInt8Ty, 8);
+ case NEON::BI__builtin_neon_vgetq_lane_i8:
+ return cir::VectorType::get(cgf.uInt8Ty, 16);
+ case NEON::BI__builtin_neon_vget_lane_i16:
+ return cir::VectorType::get(cgf.uInt16Ty, 4);
+ case NEON::BI__builtin_neon_vgetq_lane_i16:
+ return cir::VectorType::get(cgf.uInt16Ty, 8);
+ case NEON::BI__builtin_neon_vget_lane_i32:
+ return cir::VectorType::get(cgf.uInt32Ty, 2);
+ case NEON::BI__builtin_neon_vgetq_lane_i32:
+ return cir::VectorType::get(cgf.uInt32Ty, 4);
+ case NEON::BI__builtin_neon_vget_lane_i64:
+ return cir::VectorType::get(cgf.uInt64Ty, 1);
+ case NEON::BI__builtin_neon_vgetq_lane_i64:
+ return cir::VectorType::get(cgf.uInt64Ty, 2);
+ case NEON::BI__builtin_neon_vget_lane_f32:
+ return cir::VectorType::get(cgf.floatTy, 2);
+ case NEON::BI__builtin_neon_vget_lane_f64:
+ return cir::VectorType::get(cgf.doubleTy, 1);
+ case NEON::BI__builtin_neon_vgetq_lane_f32:
+ return cir::VectorType::get(cgf.floatTy, 4);
+ case NEON::BI__builtin_neon_vgetq_lane_f64:
+ return cir::VectorType::get(cgf.doubleTy, 2);
+ default:
+ return {};
+ }
+}
+
+static mlir::Value emitAArch64GetLaneBuiltinExpr(CIRGenFunction &cgf,
+ CIRGenBuilderTy &builder,
+ mlir::Location loc,
+ unsigned builtinID,
+ mlir::Value vec,
+ mlir::Value lane) {
+ cir::VectorType castTy = getAArch64GetLaneVectorType(cgf, builtinID);
+ assert(castTy && "unexpected AArch64 vget_lane builtin");
+ vec = builder.createBitcast(vec, castTy);
+ return cir::VecExtractOp::create(builder, loc, vec, lane);
+}
+
// TODO(cir): Remove `cgm` from the list of arguments once all NYI(s) are gone.
template <typename Operation>
static mlir::Value
@@ -2730,9 +2774,8 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_i8:
- ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt8Ty, 8));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
- ops[0], emitScalarExpr(expr->getArg(1)));
+ return emitAArch64GetLaneBuiltinExpr(*this, builder, loc, builtinID,
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupb_lane_i8:
cgm.errorNYI(expr->getSourceRange(),
std::string("unimplemented AArch64 builtin call: ") +
@@ -2740,9 +2783,8 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
return mlir::Value{};
case NEON::BI__builtin_neon_vgetq_lane_i8:
- ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt8Ty, 16));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
- ops[0], emitScalarExpr(expr->getArg(1)));
+ return emitAArch64GetLaneBuiltinExpr(*this, builder, loc, builtinID,
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupb_laneq_i8:
case NEON::BI__builtin_neon_vget_lane_mf8:
case NEON::BI__builtin_neon_vdupb_lane_mf8:
@@ -2753,27 +2795,24 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
getContext().BuiltinInfo.getName(builtinID));
return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_i16:
- ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt16Ty, 4));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
- ops[0], emitScalarExpr(expr->getArg(1)));
+ return emitAArch64GetLaneBuiltinExpr(*this, builder, loc, builtinID,
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vduph_lane_i16:
cgm.errorNYI(expr->getSourceRange(),
std::string("unimplemented AArch64 builtin call: ") +
getContext().BuiltinInfo.getName(builtinID));
return mlir::Value{};
case NEON::BI__builtin_neon_vgetq_lane_i16:
- ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt16Ty, 8));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
- ops[0], emitScalarExpr(expr->getArg(1)));
+ return emitAArch64GetLaneBuiltinExpr(*this, builder, loc, builtinID,
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vduph_laneq_i16:
cgm.errorNYI(expr->getSourceRange(),
std::string("unimplemented AArch64 builtin call: ") +
getContext().BuiltinInfo.getName(builtinID));
return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_i32:
- ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt32Ty, 2));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
- ops[0], emitScalarExpr(expr->getArg(1)));
+ return emitAArch64GetLaneBuiltinExpr(*this, builder, loc, builtinID,
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdups_lane_i32:
case NEON::BI__builtin_neon_vdups_lane_f32:
cgm.errorNYI(expr->getSourceRange(),
@@ -2781,18 +2820,16 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
getContext().BuiltinInfo.getName(builtinID));
return mlir::Value{};
case NEON::BI__builtin_neon_vgetq_lane_i32:
- ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt32Ty, 4));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
- ops[0], emitScalarExpr(expr->getArg(1)));
+ return emitAArch64GetLaneBuiltinExpr(*this, builder, loc, builtinID,
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdups_laneq_i32:
cgm.errorNYI(expr->getSourceRange(),
std::string("unimplemented AArch64 builtin call: ") +
getContext().BuiltinInfo.getName(builtinID));
return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_i64:
- ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt64Ty, 1));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
- ops[0], emitScalarExpr(expr->getArg(1)));
+ return emitAArch64GetLaneBuiltinExpr(*this, builder, loc, builtinID,
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupd_lane_i64:
case NEON::BI__builtin_neon_vdupd_lane_f64:
cgm.errorNYI(expr->getSourceRange(),
@@ -2800,35 +2837,30 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
getContext().BuiltinInfo.getName(builtinID));
return mlir::Value{};
case NEON::BI__builtin_neon_vgetq_lane_i64:
- ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(uInt64Ty, 2));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
- ops[0], emitScalarExpr(expr->getArg(1)));
+ return emitAArch64GetLaneBuiltinExpr(*this, builder, loc, builtinID,
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupd_laneq_i64:
cgm.errorNYI(expr->getSourceRange(),
std::string("unimplemented AArch64 builtin call: ") +
getContext().BuiltinInfo.getName(builtinID));
return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_f32:
- ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(floatTy, 2));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
- ops[0], emitScalarExpr(expr->getArg(1)));
+ return emitAArch64GetLaneBuiltinExpr(*this, builder, loc, builtinID,
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vget_lane_f64:
- ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(doubleTy, 1));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
- ops[0], emitScalarExpr(expr->getArg(1)));
+ return emitAArch64GetLaneBuiltinExpr(*this, builder, loc, builtinID,
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vgetq_lane_f32:
- ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(floatTy, 4));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
- ops[0], emitScalarExpr(expr->getArg(1)));
+ return emitAArch64GetLaneBuiltinExpr(*this, builder, loc, builtinID,
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdups_laneq_f32:
cgm.errorNYI(expr->getSourceRange(),
std::string("unimplemented AArch64 builtin call: ") +
getContext().BuiltinInfo.getName(builtinID));
return mlir::Value{};
case NEON::BI__builtin_neon_vgetq_lane_f64:
- ops[0] = builder.createBitcast(ops[0], cir::VectorType::get(doubleTy, 2));
- return cir::VecExtractOp::create(builder, getLoc(expr->getExprLoc()),
- ops[0], emitScalarExpr(expr->getArg(1)));
+ return emitAArch64GetLaneBuiltinExpr(*this, builder, loc, builtinID,
+ ops[0], emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupd_laneq_f64:
case NEON::BI__builtin_neon_vaddh_f16:
case NEON::BI__builtin_neon_vsubh_f16:
>From 6e51c01eb4e2ee3216dd7e5947bbf59f1c4ec437 Mon Sep 17 00:00:00 2001
From: Ayush Kumar Gaur <ayushkgaur1 at gmail.com>
Date: Wed, 1 Apr 2026 04:51:30 -0400
Subject: [PATCH 09/17] Update clang/test/CodeGen/AArch64/neon/getset.c
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Co-authored-by: Andrzej Warzyński <andrzej.warzynski at gmail.com>
---
clang/test/CodeGen/AArch64/neon/getset.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/clang/test/CodeGen/AArch64/neon/getset.c b/clang/test/CodeGen/AArch64/neon/getset.c
index ad628f5553256..3ef74116677cc 100644
--- a/clang/test/CodeGen/AArch64/neon/getset.c
+++ b/clang/test/CodeGen/AArch64/neon/getset.c
@@ -23,8 +23,8 @@
// ALL-LABEL: @test_vget_lane_u8(
uint8_t test_vget_lane_u8(uint8x8_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<8 x !u8i>
-
-// LLVM: [[VGET_LANE:%.*]] = extractelement <8 x i8> %{{.*}}, i32 7
+// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]])
+// LLVM: [[VGET_LANE:%.*]] = extractelement <8 x i8> [[A]], i32 7
// LLVM: ret i8 [[VGET_LANE]]
return vget_lane_u8(a, 7);
}
>From 325101e00173ec72817e9810c87b051f9405105b Mon Sep 17 00:00:00 2001
From: Ayush Kumar Gaur <ayushkgaur1 at gmail.com>
Date: Wed, 1 Apr 2026 04:51:48 -0400
Subject: [PATCH 10/17] Update clang/test/CodeGen/AArch64/neon/getset.c
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Co-authored-by: Andrzej Warzyński <andrzej.warzynski at gmail.com>
---
clang/test/CodeGen/AArch64/neon/getset.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/test/CodeGen/AArch64/neon/getset.c b/clang/test/CodeGen/AArch64/neon/getset.c
index 3ef74116677cc..8068f054d7370 100644
--- a/clang/test/CodeGen/AArch64/neon/getset.c
+++ b/clang/test/CodeGen/AArch64/neon/getset.c
@@ -17,7 +17,7 @@
#include <arm_neon.h>
//===------------------------------------------------------===//
-// Extract one element from vector
+// 2.1.9.7 Extract one element from vector
//===------------------------------------------------------===//
// ALL-LABEL: @test_vget_lane_u8(
>From dcbb1135ea8369e55de47fadb0e2356ce6caab10 Mon Sep 17 00:00:00 2001
From: Ayush3941 <ayushkgaur1 at gmail.com>
Date: Wed, 1 Apr 2026 05:24:44 -0400
Subject: [PATCH 11/17] [CIR][AArch64] Upstream Neon vget_lane/vgetq_lane
builtins v6
---
clang/test/CodeGen/AArch64/neon/getset.c | 24 ++++++------------------
1 file changed, 6 insertions(+), 18 deletions(-)
diff --git a/clang/test/CodeGen/AArch64/neon/getset.c b/clang/test/CodeGen/AArch64/neon/getset.c
index 4e1bd671e19c8..a6d3a43100649 100644
--- a/clang/test/CodeGen/AArch64/neon/getset.c
+++ b/clang/test/CodeGen/AArch64/neon/getset.c
@@ -99,15 +99,9 @@ poly16_t test_vget_lane_p16(poly16x4_t a) {
// ALL-LABEL: @test_vget_lane_f16(
float32_t test_vget_lane_f16(float16x4_t a) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<4 x !s16i> -> !cir.vector<4 x !u16i>
-// CIR: [[ELEM:%.*]] = cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u16i>
-// CIR: cir.store align(2) [[ELEM]], %{{.*}} : !u16i, !cir.ptr<!u16i>
-// CIR: [[S16PTR:%.*]] = cir.cast bitcast %{{.*}} : !cir.ptr<!u16i> -> !cir.ptr<!s16i>
-// CIR: %{{.*}} = cir.load align(2) [[S16PTR]] : !cir.ptr<!s16i>, !s16i
-// CIR: [[F16PTR:%.*]] = cir.cast bitcast %{{.*}} : !cir.ptr<!s16i> -> !cir.ptr<!cir.f16>
-// CIR: [[HALF:%.*]] = cir.load align(2) [[F16PTR]] : !cir.ptr<!cir.f16>, !cir.f16
-// CIR: %{{.*}} = cir.cast floating %{{.*}} : !cir.f16 -> !cir.float
-// CIR: cir.return %{{.*}} : !cir.float
+// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<4 x !cir.f16>> -> !cir.ptr<!cir.vector<4 x !s16i>>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !u16i>
+// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!s16i> -> !cir.ptr<!cir.f16>
// LLVM: [[TMP:%.*]] = bitcast <4 x half> %{{.*}} to <4 x i16>
// LLVM: [[VGET_LANE:%.*]] = extractelement <4 x i16> [[TMP]], i32 1
@@ -214,15 +208,9 @@ poly16_t test_vgetq_lane_p16(poly16x8_t a) {
// ALL-LABEL: @test_vgetq_lane_f16(
float32_t test_vgetq_lane_f16(float16x8_t a) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<8 x !s16i> -> !cir.vector<8 x !u16i>
-// CIR: [[ELEM:%.*]] = cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<8 x !u16i>
-// CIR: cir.store align(2) [[ELEM]], %{{.*}} : !u16i, !cir.ptr<!u16i>
-// CIR: [[S16PTR:%.*]] = cir.cast bitcast %{{.*}} : !cir.ptr<!u16i> -> !cir.ptr<!s16i>
-// CIR: %{{.*}} = cir.load align(2) [[S16PTR]] : !cir.ptr<!s16i>, !s16i
-// CIR: [[F16PTR:%.*]] = cir.cast bitcast %{{.*}} : !cir.ptr<!s16i> -> !cir.ptr<!cir.f16>
-// CIR: [[HALF:%.*]] = cir.load align(2) [[F16PTR]] : !cir.ptr<!cir.f16>, !cir.f16
-// CIR: %{{.*}} = cir.cast floating %{{.*}} : !cir.f16 -> !cir.float
-// CIR: cir.return %{{.*}} : !cir.float
+// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<8 x !cir.f16>> -> !cir.ptr<!cir.vector<8 x !s16i>>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !u16i>
+// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!s16i> -> !cir.ptr<!cir.f16>
// LLVM: [[TMP:%.*]] = bitcast <8 x half> %{{.*}} to <8 x i16>
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> [[TMP]], i32 3
>From afe1f6334ee200e65eda506d7160e74cdcc77572 Mon Sep 17 00:00:00 2001
From: Ayush3941 <ayushkgaur1 at gmail.com>
Date: Wed, 1 Apr 2026 13:35:48 -0400
Subject: [PATCH 12/17] [CIR][AArch64] Upstream Neon vget_lane/vgetq_lane
builtins v7
---
.../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 87 ++++++-------------
clang/test/CodeGen/AArch64/neon/getset.c | 78 ++++++++---------
2 files changed, 63 insertions(+), 102 deletions(-)
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index da5473394c4ea..c46821452c9d1 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -1298,47 +1298,10 @@ static bool hasExtraNeonArgument(unsigned builtinID) {
return mask != 0;
}
-static cir::VectorType getAArch64GetLaneVectorType(CIRGenFunction &cgf,
- unsigned builtinID) {
- switch (builtinID) {
- case NEON::BI__builtin_neon_vget_lane_i8:
- return cir::VectorType::get(cgf.uInt8Ty, 8);
- case NEON::BI__builtin_neon_vgetq_lane_i8:
- return cir::VectorType::get(cgf.uInt8Ty, 16);
- case NEON::BI__builtin_neon_vget_lane_i16:
- return cir::VectorType::get(cgf.uInt16Ty, 4);
- case NEON::BI__builtin_neon_vgetq_lane_i16:
- return cir::VectorType::get(cgf.uInt16Ty, 8);
- case NEON::BI__builtin_neon_vget_lane_i32:
- return cir::VectorType::get(cgf.uInt32Ty, 2);
- case NEON::BI__builtin_neon_vgetq_lane_i32:
- return cir::VectorType::get(cgf.uInt32Ty, 4);
- case NEON::BI__builtin_neon_vget_lane_i64:
- return cir::VectorType::get(cgf.uInt64Ty, 1);
- case NEON::BI__builtin_neon_vgetq_lane_i64:
- return cir::VectorType::get(cgf.uInt64Ty, 2);
- case NEON::BI__builtin_neon_vget_lane_f32:
- return cir::VectorType::get(cgf.floatTy, 2);
- case NEON::BI__builtin_neon_vget_lane_f64:
- return cir::VectorType::get(cgf.doubleTy, 1);
- case NEON::BI__builtin_neon_vgetq_lane_f32:
- return cir::VectorType::get(cgf.floatTy, 4);
- case NEON::BI__builtin_neon_vgetq_lane_f64:
- return cir::VectorType::get(cgf.doubleTy, 2);
- default:
- return {};
- }
-}
-
-static mlir::Value emitAArch64GetLaneBuiltinExpr(CIRGenFunction &cgf,
- CIRGenBuilderTy &builder,
+static mlir::Value emitAArch64GetLaneBuiltinExpr(CIRGenBuilderTy &builder,
mlir::Location loc,
- unsigned builtinID,
mlir::Value vec,
mlir::Value lane) {
- cir::VectorType castTy = getAArch64GetLaneVectorType(cgf, builtinID);
- assert(castTy && "unexpected AArch64 vget_lane builtin");
- vec = builder.createBitcast(vec, castTy);
return cir::VecExtractOp::create(builder, loc, vec, lane);
}
@@ -2774,8 +2737,8 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_i8:
- return emitAArch64GetLaneBuiltinExpr(*this, builder, loc, builtinID,
- ops[0], emitScalarExpr(expr->getArg(1)));
+ return emitAArch64GetLaneBuiltinExpr(builder, loc, ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupb_lane_i8:
cgm.errorNYI(expr->getSourceRange(),
std::string("unimplemented AArch64 builtin call: ") +
@@ -2783,8 +2746,8 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
return mlir::Value{};
case NEON::BI__builtin_neon_vgetq_lane_i8:
- return emitAArch64GetLaneBuiltinExpr(*this, builder, loc, builtinID,
- ops[0], emitScalarExpr(expr->getArg(1)));
+ return emitAArch64GetLaneBuiltinExpr(builder, loc, ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupb_laneq_i8:
case NEON::BI__builtin_neon_vget_lane_mf8:
case NEON::BI__builtin_neon_vdupb_lane_mf8:
@@ -2795,24 +2758,24 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
getContext().BuiltinInfo.getName(builtinID));
return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_i16:
- return emitAArch64GetLaneBuiltinExpr(*this, builder, loc, builtinID,
- ops[0], emitScalarExpr(expr->getArg(1)));
+ return emitAArch64GetLaneBuiltinExpr(builder, loc, ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vduph_lane_i16:
cgm.errorNYI(expr->getSourceRange(),
std::string("unimplemented AArch64 builtin call: ") +
getContext().BuiltinInfo.getName(builtinID));
return mlir::Value{};
case NEON::BI__builtin_neon_vgetq_lane_i16:
- return emitAArch64GetLaneBuiltinExpr(*this, builder, loc, builtinID,
- ops[0], emitScalarExpr(expr->getArg(1)));
+ return emitAArch64GetLaneBuiltinExpr(builder, loc, ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vduph_laneq_i16:
cgm.errorNYI(expr->getSourceRange(),
std::string("unimplemented AArch64 builtin call: ") +
getContext().BuiltinInfo.getName(builtinID));
return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_i32:
- return emitAArch64GetLaneBuiltinExpr(*this, builder, loc, builtinID,
- ops[0], emitScalarExpr(expr->getArg(1)));
+ return emitAArch64GetLaneBuiltinExpr(builder, loc, ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdups_lane_i32:
case NEON::BI__builtin_neon_vdups_lane_f32:
cgm.errorNYI(expr->getSourceRange(),
@@ -2820,16 +2783,16 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
getContext().BuiltinInfo.getName(builtinID));
return mlir::Value{};
case NEON::BI__builtin_neon_vgetq_lane_i32:
- return emitAArch64GetLaneBuiltinExpr(*this, builder, loc, builtinID,
- ops[0], emitScalarExpr(expr->getArg(1)));
+ return emitAArch64GetLaneBuiltinExpr(builder, loc, ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdups_laneq_i32:
cgm.errorNYI(expr->getSourceRange(),
std::string("unimplemented AArch64 builtin call: ") +
getContext().BuiltinInfo.getName(builtinID));
return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_i64:
- return emitAArch64GetLaneBuiltinExpr(*this, builder, loc, builtinID,
- ops[0], emitScalarExpr(expr->getArg(1)));
+ return emitAArch64GetLaneBuiltinExpr(builder, loc, ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupd_lane_i64:
case NEON::BI__builtin_neon_vdupd_lane_f64:
cgm.errorNYI(expr->getSourceRange(),
@@ -2837,30 +2800,30 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
getContext().BuiltinInfo.getName(builtinID));
return mlir::Value{};
case NEON::BI__builtin_neon_vgetq_lane_i64:
- return emitAArch64GetLaneBuiltinExpr(*this, builder, loc, builtinID,
- ops[0], emitScalarExpr(expr->getArg(1)));
+ return emitAArch64GetLaneBuiltinExpr(builder, loc, ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupd_laneq_i64:
cgm.errorNYI(expr->getSourceRange(),
std::string("unimplemented AArch64 builtin call: ") +
getContext().BuiltinInfo.getName(builtinID));
return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_f32:
- return emitAArch64GetLaneBuiltinExpr(*this, builder, loc, builtinID,
- ops[0], emitScalarExpr(expr->getArg(1)));
+ return emitAArch64GetLaneBuiltinExpr(builder, loc, ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vget_lane_f64:
- return emitAArch64GetLaneBuiltinExpr(*this, builder, loc, builtinID,
- ops[0], emitScalarExpr(expr->getArg(1)));
+ return emitAArch64GetLaneBuiltinExpr(builder, loc, ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vgetq_lane_f32:
- return emitAArch64GetLaneBuiltinExpr(*this, builder, loc, builtinID,
- ops[0], emitScalarExpr(expr->getArg(1)));
+ return emitAArch64GetLaneBuiltinExpr(builder, loc, ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdups_laneq_f32:
cgm.errorNYI(expr->getSourceRange(),
std::string("unimplemented AArch64 builtin call: ") +
getContext().BuiltinInfo.getName(builtinID));
return mlir::Value{};
case NEON::BI__builtin_neon_vgetq_lane_f64:
- return emitAArch64GetLaneBuiltinExpr(*this, builder, loc, builtinID,
- ops[0], emitScalarExpr(expr->getArg(1)));
+ return emitAArch64GetLaneBuiltinExpr(builder, loc, ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupd_laneq_f64:
case NEON::BI__builtin_neon_vaddh_f16:
case NEON::BI__builtin_neon_vsubh_f16:
diff --git a/clang/test/CodeGen/AArch64/neon/getset.c b/clang/test/CodeGen/AArch64/neon/getset.c
index a6d3a43100649..6940a8b5bdfda 100644
--- a/clang/test/CodeGen/AArch64/neon/getset.c
+++ b/clang/test/CodeGen/AArch64/neon/getset.c
@@ -22,7 +22,8 @@
// ALL-LABEL: @test_vget_lane_u8(
uint8_t test_vget_lane_u8(uint8x8_t a) {
-// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<8 x !u8i>
+// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<8 x !u8i>> -> !cir.ptr<!cir.vector<8 x !s8i>>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !s8i>
// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]])
// LLVM: [[VGET_LANE:%.*]] = extractelement <8 x i8> [[A]], i32 7
// LLVM: ret i8 [[VGET_LANE]]
@@ -31,8 +32,8 @@ uint8_t test_vget_lane_u8(uint8x8_t a) {
// ALL-LABEL: @test_vget_lane_u16(
uint16_t test_vget_lane_u16(uint16x4_t a) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<4 x !s16i> -> !cir.vector<4 x !u16i>
-// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u16i>
+// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<4 x !u16i>> -> !cir.ptr<!cir.vector<4 x !s16i>>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !s16i>
// LLVM: [[VGET_LANE:%.*]] = extractelement <4 x i16> %{{.*}}, i32 3
// LLVM: ret i16 [[VGET_LANE]]
@@ -41,8 +42,8 @@ uint16_t test_vget_lane_u16(uint16x4_t a) {
// ALL-LABEL: @test_vget_lane_u32(
uint32_t test_vget_lane_u32(uint32x2_t a) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<2 x !s32i> -> !cir.vector<2 x !u32i>
-// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<2 x !u32i>
+// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<2 x !u32i>> -> !cir.ptr<!cir.vector<2 x !s32i>>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x !s32i>
// LLVM: [[VGET_LANE:%.*]] = extractelement <2 x i32> %{{.*}}, i32 1
// LLVM: ret i32 [[VGET_LANE]]
@@ -51,7 +52,7 @@ uint32_t test_vget_lane_u32(uint32x2_t a) {
// ALL-LABEL: @test_vget_lane_s8(
int8_t test_vget_lane_s8(int8x8_t a) {
-// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<8 x !u8i>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !s8i>
// LLVM: [[VGET_LANE:%.*]] = extractelement <8 x i8> %{{.*}}, i32 7
// LLVM: ret i8 [[VGET_LANE]]
@@ -60,8 +61,7 @@ int8_t test_vget_lane_s8(int8x8_t a) {
// ALL-LABEL: @test_vget_lane_s16(
int16_t test_vget_lane_s16(int16x4_t a) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<4 x !s16i> -> !cir.vector<4 x !u16i>
-// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u16i>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !s16i>
// LLVM: [[VGET_LANE:%.*]] = extractelement <4 x i16> %{{.*}}, i32 3
// LLVM: ret i16 [[VGET_LANE]]
@@ -70,8 +70,7 @@ int16_t test_vget_lane_s16(int16x4_t a) {
// ALL-LABEL: @test_vget_lane_s32(
int32_t test_vget_lane_s32(int32x2_t a) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<2 x !s32i> -> !cir.vector<2 x !u32i>
-// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<2 x !u32i>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x !s32i>
// LLVM: [[VGET_LANE:%.*]] = extractelement <2 x i32> %{{.*}}, i32 1
// LLVM: ret i32 [[VGET_LANE]]
@@ -80,7 +79,8 @@ int32_t test_vget_lane_s32(int32x2_t a) {
// ALL-LABEL: @test_vget_lane_p8(
poly8_t test_vget_lane_p8(poly8x8_t a) {
-// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<8 x !u8i>
+// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<8 x !u8i>> -> !cir.ptr<!cir.vector<8 x !s8i>>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !s8i>
// LLVM: [[VGET_LANE:%.*]] = extractelement <8 x i8> %{{.*}}, i32 7
// LLVM: ret i8 [[VGET_LANE]]
@@ -89,8 +89,8 @@ poly8_t test_vget_lane_p8(poly8x8_t a) {
// ALL-LABEL: @test_vget_lane_p16(
poly16_t test_vget_lane_p16(poly16x4_t a) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<4 x !s16i> -> !cir.vector<4 x !u16i>
-// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u16i>
+// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<4 x !u16i>> -> !cir.ptr<!cir.vector<4 x !s16i>>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !s16i>
// LLVM: [[VGET_LANE:%.*]] = extractelement <4 x i16> %{{.*}}, i32 3
// LLVM: ret i16 [[VGET_LANE]]
@@ -100,7 +100,7 @@ poly16_t test_vget_lane_p16(poly16x4_t a) {
// ALL-LABEL: @test_vget_lane_f16(
float32_t test_vget_lane_f16(float16x4_t a) {
// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<4 x !cir.f16>> -> !cir.ptr<!cir.vector<4 x !s16i>>
-// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !u16i>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !s16i>
// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!s16i> -> !cir.ptr<!cir.f16>
// LLVM: [[TMP:%.*]] = bitcast <4 x half> %{{.*}} to <4 x i16>
@@ -131,7 +131,8 @@ float64_t test_vget_lane_f64(float64x1_t a) {
// ALL-LABEL: @test_vgetq_lane_u8(
uint8_t test_vgetq_lane_u8(uint8x16_t a) {
-// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<16 x !u8i>
+// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<16 x !u8i>> -> !cir.ptr<!cir.vector<16 x !s8i>>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<16 x !s8i>
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %{{.*}}, i32 15
// LLVM: ret i8 [[VGETQ_LANE]]
@@ -140,8 +141,8 @@ uint8_t test_vgetq_lane_u8(uint8x16_t a) {
// ALL-LABEL: @test_vgetq_lane_u16(
uint16_t test_vgetq_lane_u16(uint16x8_t a) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<8 x !s16i> -> !cir.vector<8 x !u16i>
-// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<8 x !u16i>
+// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<8 x !u16i>> -> !cir.ptr<!cir.vector<8 x !s16i>>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !s16i>
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %{{.*}}, i32 7
// LLVM: ret i16 [[VGETQ_LANE]]
@@ -150,8 +151,8 @@ uint16_t test_vgetq_lane_u16(uint16x8_t a) {
// ALL-LABEL: @test_vgetq_lane_u32(
uint32_t test_vgetq_lane_u32(uint32x4_t a) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<4 x !s32i> -> !cir.vector<4 x !u32i>
-// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u32i>
+// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<4 x !u32i>> -> !cir.ptr<!cir.vector<4 x !s32i>>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !s32i>
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %{{.*}}, i32 3
// LLVM: ret i32 [[VGETQ_LANE]]
@@ -160,7 +161,7 @@ uint32_t test_vgetq_lane_u32(uint32x4_t a) {
// ALL-LABEL: @test_vgetq_lane_s8(
int8_t test_vgetq_lane_s8(int8x16_t a) {
-// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<16 x !u8i>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<16 x !s8i>
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %{{.*}}, i32 15
// LLVM: ret i8 [[VGETQ_LANE]]
@@ -169,8 +170,7 @@ int8_t test_vgetq_lane_s8(int8x16_t a) {
// ALL-LABEL: @test_vgetq_lane_s16(
int16_t test_vgetq_lane_s16(int16x8_t a) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<8 x !s16i> -> !cir.vector<8 x !u16i>
-// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<8 x !u16i>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !s16i>
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %{{.*}}, i32 7
// LLVM: ret i16 [[VGETQ_LANE]]
@@ -179,8 +179,7 @@ int16_t test_vgetq_lane_s16(int16x8_t a) {
// ALL-LABEL: @test_vgetq_lane_s32(
int32_t test_vgetq_lane_s32(int32x4_t a) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<4 x !s32i> -> !cir.vector<4 x !u32i>
-// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<4 x !u32i>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !s32i>
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %{{.*}}, i32 3
// LLVM: ret i32 [[VGETQ_LANE]]
@@ -189,7 +188,8 @@ int32_t test_vgetq_lane_s32(int32x4_t a) {
// ALL-LABEL: @test_vgetq_lane_p8(
poly8_t test_vgetq_lane_p8(poly8x16_t a) {
-// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<16 x !u8i>
+// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<16 x !u8i>> -> !cir.ptr<!cir.vector<16 x !s8i>>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<16 x !s8i>
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %{{.*}}, i32 15
// LLVM: ret i8 [[VGETQ_LANE]]
@@ -198,8 +198,8 @@ poly8_t test_vgetq_lane_p8(poly8x16_t a) {
// ALL-LABEL: @test_vgetq_lane_p16(
poly16_t test_vgetq_lane_p16(poly16x8_t a) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<8 x !s16i> -> !cir.vector<8 x !u16i>
-// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<8 x !u16i>
+// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<8 x !u16i>> -> !cir.ptr<!cir.vector<8 x !s16i>>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !s16i>
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %{{.*}}, i32 7
// LLVM: ret i16 [[VGETQ_LANE]]
@@ -209,7 +209,7 @@ poly16_t test_vgetq_lane_p16(poly16x8_t a) {
// ALL-LABEL: @test_vgetq_lane_f16(
float32_t test_vgetq_lane_f16(float16x8_t a) {
// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<8 x !cir.f16>> -> !cir.ptr<!cir.vector<8 x !s16i>>
-// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !u16i>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !s16i>
// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!s16i> -> !cir.ptr<!cir.f16>
// LLVM: [[TMP:%.*]] = bitcast <8 x half> %{{.*}} to <8 x i16>
@@ -240,8 +240,7 @@ float64_t test_vgetq_lane_f64(float64x2_t a) {
// ALL-LABEL: @test_vget_lane_s64(
int64_t test_vget_lane_s64(int64x1_t a) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<1 x !s64i> -> !cir.vector<1 x !u64i>
-// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<1 x !u64i>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<1 x !s64i>
// LLVM: [[VGET_LANE:%.*]] = extractelement <1 x i64> %{{.*}}, i32 0
// LLVM: ret i64 [[VGET_LANE]]
@@ -250,8 +249,8 @@ int64_t test_vget_lane_s64(int64x1_t a) {
// ALL-LABEL: @test_vget_lane_u64(
uint64_t test_vget_lane_u64(uint64x1_t a) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<1 x !s64i> -> !cir.vector<1 x !u64i>
-// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<1 x !u64i>
+// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<1 x !u64i>> -> !cir.ptr<!cir.vector<1 x !s64i>>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<1 x !s64i>
// LLVM: [[VGET_LANE:%.*]] = extractelement <1 x i64> %{{.*}}, i32 0
// LLVM: ret i64 [[VGET_LANE]]
@@ -260,8 +259,8 @@ uint64_t test_vget_lane_u64(uint64x1_t a) {
// ALL-LABEL: @test_vget_lane_p64(
poly64_t test_vget_lane_p64(poly64x1_t v) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<1 x !s64i> -> !cir.vector<1 x !u64i>
-// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<1 x !u64i>
+// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<1 x !u64i>> -> !cir.ptr<!cir.vector<1 x !s64i>>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<1 x !s64i>
// LLVM: [[VGET_LANE:%.*]] = extractelement <1 x i64> %{{.*}}, i32 0
// LLVM: ret i64 [[VGET_LANE]]
@@ -270,8 +269,7 @@ poly64_t test_vget_lane_p64(poly64x1_t v) {
// ALL-LABEL: @test_vgetq_lane_s64(
int64_t test_vgetq_lane_s64(int64x2_t a) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<2 x !s64i> -> !cir.vector<2 x !u64i>
-// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<2 x !u64i>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x !s64i>
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %{{.*}}, i32 1
// LLVM: ret i64 [[VGETQ_LANE]]
@@ -280,8 +278,8 @@ int64_t test_vgetq_lane_s64(int64x2_t a) {
// ALL-LABEL: @test_vgetq_lane_u64(
uint64_t test_vgetq_lane_u64(uint64x2_t a) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<2 x !s64i> -> !cir.vector<2 x !u64i>
-// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<2 x !u64i>
+// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<2 x !u64i>> -> !cir.ptr<!cir.vector<2 x !s64i>>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x !s64i>
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %{{.*}}, i32 1
// LLVM: ret i64 [[VGETQ_LANE]]
@@ -290,8 +288,8 @@ uint64_t test_vgetq_lane_u64(uint64x2_t a) {
// ALL-LABEL: @test_vgetq_lane_p64(
poly64_t test_vgetq_lane_p64(poly64x2_t v) {
-// CIR: [[V:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<2 x !s64i> -> !cir.vector<2 x !u64i>
-// CIR: cir.vec.extract [[V]][%{{.*}} : {{.*}}] : !cir.vector<2 x !u64i>
+// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<2 x !u64i>> -> !cir.ptr<!cir.vector<2 x !s64i>>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x !s64i>
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %{{.*}}, i32 1
// LLVM: ret i64 [[VGETQ_LANE]]
>From d0bde5404ebbeddd8c2ae5486f7a4201ad8a1da4 Mon Sep 17 00:00:00 2001
From: Ayush3941 <ayushkgaur1 at gmail.com>
Date: Mon, 13 Apr 2026 01:15:50 -0400
Subject: [PATCH 13/17] [CIR][AArch64] Upstream Neon vget_lane/vgetq_lane
builtins v8
---
clang/test/CodeGen/AArch64/neon/getset.c | 44 +++++++++---------------
1 file changed, 16 insertions(+), 28 deletions(-)
diff --git a/clang/test/CodeGen/AArch64/neon/getset.c b/clang/test/CodeGen/AArch64/neon/getset.c
index 6940a8b5bdfda..1f5cd70440979 100644
--- a/clang/test/CodeGen/AArch64/neon/getset.c
+++ b/clang/test/CodeGen/AArch64/neon/getset.c
@@ -19,11 +19,12 @@
//===------------------------------------------------------===//
// 2.1.9.7 Extract one element from vector
//===------------------------------------------------------===//
+// TODO(cir): Add mf8 vget_lane/vgetq_lane coverage once NEON MFloat8 support
+// is available in ClangIR.
// ALL-LABEL: @test_vget_lane_u8(
uint8_t test_vget_lane_u8(uint8x8_t a) {
-// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<8 x !u8i>> -> !cir.ptr<!cir.vector<8 x !s8i>>
-// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !s8i>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x {{.*}}>
// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]])
// LLVM: [[VGET_LANE:%.*]] = extractelement <8 x i8> [[A]], i32 7
// LLVM: ret i8 [[VGET_LANE]]
@@ -32,8 +33,7 @@ uint8_t test_vget_lane_u8(uint8x8_t a) {
// ALL-LABEL: @test_vget_lane_u16(
uint16_t test_vget_lane_u16(uint16x4_t a) {
-// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<4 x !u16i>> -> !cir.ptr<!cir.vector<4 x !s16i>>
-// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !s16i>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x {{.*}}>
// LLVM: [[VGET_LANE:%.*]] = extractelement <4 x i16> %{{.*}}, i32 3
// LLVM: ret i16 [[VGET_LANE]]
@@ -42,8 +42,7 @@ uint16_t test_vget_lane_u16(uint16x4_t a) {
// ALL-LABEL: @test_vget_lane_u32(
uint32_t test_vget_lane_u32(uint32x2_t a) {
-// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<2 x !u32i>> -> !cir.ptr<!cir.vector<2 x !s32i>>
-// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x !s32i>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x {{.*}}>
// LLVM: [[VGET_LANE:%.*]] = extractelement <2 x i32> %{{.*}}, i32 1
// LLVM: ret i32 [[VGET_LANE]]
@@ -79,8 +78,7 @@ int32_t test_vget_lane_s32(int32x2_t a) {
// ALL-LABEL: @test_vget_lane_p8(
poly8_t test_vget_lane_p8(poly8x8_t a) {
-// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<8 x !u8i>> -> !cir.ptr<!cir.vector<8 x !s8i>>
-// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !s8i>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x {{.*}}>
// LLVM: [[VGET_LANE:%.*]] = extractelement <8 x i8> %{{.*}}, i32 7
// LLVM: ret i8 [[VGET_LANE]]
@@ -89,8 +87,7 @@ poly8_t test_vget_lane_p8(poly8x8_t a) {
// ALL-LABEL: @test_vget_lane_p16(
poly16_t test_vget_lane_p16(poly16x4_t a) {
-// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<4 x !u16i>> -> !cir.ptr<!cir.vector<4 x !s16i>>
-// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !s16i>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x {{.*}}>
// LLVM: [[VGET_LANE:%.*]] = extractelement <4 x i16> %{{.*}}, i32 3
// LLVM: ret i16 [[VGET_LANE]]
@@ -131,8 +128,7 @@ float64_t test_vget_lane_f64(float64x1_t a) {
// ALL-LABEL: @test_vgetq_lane_u8(
uint8_t test_vgetq_lane_u8(uint8x16_t a) {
-// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<16 x !u8i>> -> !cir.ptr<!cir.vector<16 x !s8i>>
-// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<16 x !s8i>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<16 x {{.*}}>
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %{{.*}}, i32 15
// LLVM: ret i8 [[VGETQ_LANE]]
@@ -141,8 +137,7 @@ uint8_t test_vgetq_lane_u8(uint8x16_t a) {
// ALL-LABEL: @test_vgetq_lane_u16(
uint16_t test_vgetq_lane_u16(uint16x8_t a) {
-// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<8 x !u16i>> -> !cir.ptr<!cir.vector<8 x !s16i>>
-// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !s16i>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x {{.*}}>
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %{{.*}}, i32 7
// LLVM: ret i16 [[VGETQ_LANE]]
@@ -151,8 +146,7 @@ uint16_t test_vgetq_lane_u16(uint16x8_t a) {
// ALL-LABEL: @test_vgetq_lane_u32(
uint32_t test_vgetq_lane_u32(uint32x4_t a) {
-// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<4 x !u32i>> -> !cir.ptr<!cir.vector<4 x !s32i>>
-// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !s32i>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x {{.*}}>
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %{{.*}}, i32 3
// LLVM: ret i32 [[VGETQ_LANE]]
@@ -188,8 +182,7 @@ int32_t test_vgetq_lane_s32(int32x4_t a) {
// ALL-LABEL: @test_vgetq_lane_p8(
poly8_t test_vgetq_lane_p8(poly8x16_t a) {
-// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<16 x !u8i>> -> !cir.ptr<!cir.vector<16 x !s8i>>
-// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<16 x !s8i>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<16 x {{.*}}>
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %{{.*}}, i32 15
// LLVM: ret i8 [[VGETQ_LANE]]
@@ -198,8 +191,7 @@ poly8_t test_vgetq_lane_p8(poly8x16_t a) {
// ALL-LABEL: @test_vgetq_lane_p16(
poly16_t test_vgetq_lane_p16(poly16x8_t a) {
-// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<8 x !u16i>> -> !cir.ptr<!cir.vector<8 x !s16i>>
-// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !s16i>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x {{.*}}>
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %{{.*}}, i32 7
// LLVM: ret i16 [[VGETQ_LANE]]
@@ -249,8 +241,7 @@ int64_t test_vget_lane_s64(int64x1_t a) {
// ALL-LABEL: @test_vget_lane_u64(
uint64_t test_vget_lane_u64(uint64x1_t a) {
-// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<1 x !u64i>> -> !cir.ptr<!cir.vector<1 x !s64i>>
-// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<1 x !s64i>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<1 x {{.*}}>
// LLVM: [[VGET_LANE:%.*]] = extractelement <1 x i64> %{{.*}}, i32 0
// LLVM: ret i64 [[VGET_LANE]]
@@ -259,8 +250,7 @@ uint64_t test_vget_lane_u64(uint64x1_t a) {
// ALL-LABEL: @test_vget_lane_p64(
poly64_t test_vget_lane_p64(poly64x1_t v) {
-// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<1 x !u64i>> -> !cir.ptr<!cir.vector<1 x !s64i>>
-// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<1 x !s64i>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<1 x {{.*}}>
// LLVM: [[VGET_LANE:%.*]] = extractelement <1 x i64> %{{.*}}, i32 0
// LLVM: ret i64 [[VGET_LANE]]
@@ -278,8 +268,7 @@ int64_t test_vgetq_lane_s64(int64x2_t a) {
// ALL-LABEL: @test_vgetq_lane_u64(
uint64_t test_vgetq_lane_u64(uint64x2_t a) {
-// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<2 x !u64i>> -> !cir.ptr<!cir.vector<2 x !s64i>>
-// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x !s64i>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x {{.*}}>
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %{{.*}}, i32 1
// LLVM: ret i64 [[VGETQ_LANE]]
@@ -288,8 +277,7 @@ uint64_t test_vgetq_lane_u64(uint64x2_t a) {
// ALL-LABEL: @test_vgetq_lane_p64(
poly64_t test_vgetq_lane_p64(poly64x2_t v) {
-// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<2 x !u64i>> -> !cir.ptr<!cir.vector<2 x !s64i>>
-// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x !s64i>
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x {{.*}}>
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %{{.*}}, i32 1
// LLVM: ret i64 [[VGETQ_LANE]]
>From ec65c6077d03e2a941e05409864678238e1ecf82 Mon Sep 17 00:00:00 2001
From: Ayush3941 <ayushkgaur1 at gmail.com>
Date: Mon, 13 Apr 2026 02:08:03 -0400
Subject: [PATCH 14/17] [CIR][AArch64] Upstream Neon vget_lane/vgetq_lane
builtins v8
---
clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index 1e51b2ced2df2..38b95130bbcfe 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -763,6 +763,13 @@ static mlir::Value emitCommonNeonBuiltinExpr(
}
}
+static mlir::Value emitAArch64GetLaneBuiltinExpr(CIRGenBuilderTy &builder,
+ mlir::Location loc,
+ mlir::Value vec,
+ mlir::Value lane) {
+ return cir::VecExtractOp::create(builder, loc, vec, lane);
+}
+
// Emit an intrinsic where all operands are of the same type as the result.
// Depending on mode, this may be a constrained floating-point intrinsic.
static mlir::Value
>From bb3e7890b209fc0ce90c8b33332bf39b6792d39a Mon Sep 17 00:00:00 2001
From: Ayush3941 <ayushkgaur1 at gmail.com>
Date: Fri, 24 Apr 2026 17:08:32 -0400
Subject: [PATCH 15/17] [CIR][AArch64] Upstream Neon vget_lane/vgetq_lane
builtins v7
---
clang/test/CodeGen/AArch64/neon/getset.c | 108 +++++++++++------------
1 file changed, 54 insertions(+), 54 deletions(-)
diff --git a/clang/test/CodeGen/AArch64/neon/getset.c b/clang/test/CodeGen/AArch64/neon/getset.c
index 1f5cd70440979..3aa5f18a7160c 100644
--- a/clang/test/CodeGen/AArch64/neon/getset.c
+++ b/clang/test/CodeGen/AArch64/neon/getset.c
@@ -34,8 +34,8 @@ uint8_t test_vget_lane_u8(uint8x8_t a) {
// ALL-LABEL: @test_vget_lane_u16(
uint16_t test_vget_lane_u16(uint16x4_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x {{.*}}>
-
-// LLVM: [[VGET_LANE:%.*]] = extractelement <4 x i16> %{{.*}}, i32 3
+// LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]])
+// LLVM: [[VGET_LANE:%.*]] = extractelement <4 x i16> [[A]], i32 3
// LLVM: ret i16 [[VGET_LANE]]
return vget_lane_u16(a, 3);
}
@@ -43,8 +43,8 @@ uint16_t test_vget_lane_u16(uint16x4_t a) {
// ALL-LABEL: @test_vget_lane_u32(
uint32_t test_vget_lane_u32(uint32x2_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x {{.*}}>
-
-// LLVM: [[VGET_LANE:%.*]] = extractelement <2 x i32> %{{.*}}, i32 1
+// LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]])
+// LLVM: [[VGET_LANE:%.*]] = extractelement <2 x i32> [[A]], i32 1
// LLVM: ret i32 [[VGET_LANE]]
return vget_lane_u32(a, 1);
}
@@ -52,8 +52,8 @@ uint32_t test_vget_lane_u32(uint32x2_t a) {
// ALL-LABEL: @test_vget_lane_s8(
int8_t test_vget_lane_s8(int8x8_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !s8i>
-
-// LLVM: [[VGET_LANE:%.*]] = extractelement <8 x i8> %{{.*}}, i32 7
+// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]])
+// LLVM: [[VGET_LANE:%.*]] = extractelement <8 x i8> [[A]], i32 7
// LLVM: ret i8 [[VGET_LANE]]
return vget_lane_s8(a, 7);
}
@@ -61,8 +61,8 @@ int8_t test_vget_lane_s8(int8x8_t a) {
// ALL-LABEL: @test_vget_lane_s16(
int16_t test_vget_lane_s16(int16x4_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !s16i>
-
-// LLVM: [[VGET_LANE:%.*]] = extractelement <4 x i16> %{{.*}}, i32 3
+// LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]])
+// LLVM: [[VGET_LANE:%.*]] = extractelement <4 x i16> [[A]], i32 3
// LLVM: ret i16 [[VGET_LANE]]
return vget_lane_s16(a, 3);
}
@@ -70,8 +70,8 @@ int16_t test_vget_lane_s16(int16x4_t a) {
// ALL-LABEL: @test_vget_lane_s32(
int32_t test_vget_lane_s32(int32x2_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x !s32i>
-
-// LLVM: [[VGET_LANE:%.*]] = extractelement <2 x i32> %{{.*}}, i32 1
+// LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]])
+// LLVM: [[VGET_LANE:%.*]] = extractelement <2 x i32> [[A]], i32 1
// LLVM: ret i32 [[VGET_LANE]]
return vget_lane_s32(a, 1);
}
@@ -79,8 +79,8 @@ int32_t test_vget_lane_s32(int32x2_t a) {
// ALL-LABEL: @test_vget_lane_p8(
poly8_t test_vget_lane_p8(poly8x8_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x {{.*}}>
-
-// LLVM: [[VGET_LANE:%.*]] = extractelement <8 x i8> %{{.*}}, i32 7
+// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]])
+// LLVM: [[VGET_LANE:%.*]] = extractelement <8 x i8> [[A]], i32 7
// LLVM: ret i8 [[VGET_LANE]]
return vget_lane_p8(a, 7);
}
@@ -88,8 +88,8 @@ poly8_t test_vget_lane_p8(poly8x8_t a) {
// ALL-LABEL: @test_vget_lane_p16(
poly16_t test_vget_lane_p16(poly16x4_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x {{.*}}>
-
-// LLVM: [[VGET_LANE:%.*]] = extractelement <4 x i16> %{{.*}}, i32 3
+// LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]])
+// LLVM: [[VGET_LANE:%.*]] = extractelement <4 x i16> [[A]], i32 3
// LLVM: ret i16 [[VGET_LANE]]
return vget_lane_p16(a, 3);
}
@@ -99,8 +99,8 @@ float32_t test_vget_lane_f16(float16x4_t a) {
// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<4 x !cir.f16>> -> !cir.ptr<!cir.vector<4 x !s16i>>
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !s16i>
// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!s16i> -> !cir.ptr<!cir.f16>
-
-// LLVM: [[TMP:%.*]] = bitcast <4 x half> %{{.*}} to <4 x i16>
+// LLVM-SAME: <4 x half> {{.*}} [[A:%.*]])
+// LLVM: [[TMP:%.*]] = bitcast <4 x half> [[A]] to <4 x i16>
// LLVM: [[VGET_LANE:%.*]] = extractelement <4 x i16> [[TMP]], i32 1
// LLVM: [[HALF:%.*]] = bitcast i16 [[VGET_LANE]] to half
// LLVM: [[RES:%.*]] = fpext half [[HALF]] to float
@@ -111,8 +111,8 @@ float32_t test_vget_lane_f16(float16x4_t a) {
// ALL-LABEL: @test_vget_lane_f32(
float32_t test_vget_lane_f32(float32x2_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<2 x !cir.float>
-
-// LLVM: [[VGET_LANE:%.*]] = extractelement <2 x float> %{{.*}}, i32 1
+// LLVM-SAME: <2 x float> {{.*}} [[A:%.*]])
+// LLVM: [[VGET_LANE:%.*]] = extractelement <2 x float> [[A]], i32 1
// LLVM: ret float [[VGET_LANE]]
return vget_lane_f32(a, 1);
}
@@ -120,8 +120,8 @@ float32_t test_vget_lane_f32(float32x2_t a) {
// ALL-LABEL: @test_vget_lane_f64(
float64_t test_vget_lane_f64(float64x1_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<1 x !cir.double>
-
-// LLVM: [[VGET_LANE:%.*]] = extractelement <1 x double> %{{.*}}, i32 0
+// LLVM-SAME: <1 x double> {{.*}} [[A:%.*]])
+// LLVM: [[VGET_LANE:%.*]] = extractelement <1 x double> [[A]], i32 0
// LLVM: ret double [[VGET_LANE]]
return vget_lane_f64(a, 0);
}
@@ -129,8 +129,8 @@ float64_t test_vget_lane_f64(float64x1_t a) {
// ALL-LABEL: @test_vgetq_lane_u8(
uint8_t test_vgetq_lane_u8(uint8x16_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<16 x {{.*}}>
-
-// LLVM: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %{{.*}}, i32 15
+// LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]])
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> [[A]], i32 15
// LLVM: ret i8 [[VGETQ_LANE]]
return vgetq_lane_u8(a, 15);
}
@@ -138,8 +138,8 @@ uint8_t test_vgetq_lane_u8(uint8x16_t a) {
// ALL-LABEL: @test_vgetq_lane_u16(
uint16_t test_vgetq_lane_u16(uint16x8_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x {{.*}}>
-
-// LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %{{.*}}, i32 7
+// LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]])
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> [[A]], i32 7
// LLVM: ret i16 [[VGETQ_LANE]]
return vgetq_lane_u16(a, 7);
}
@@ -147,8 +147,8 @@ uint16_t test_vgetq_lane_u16(uint16x8_t a) {
// ALL-LABEL: @test_vgetq_lane_u32(
uint32_t test_vgetq_lane_u32(uint32x4_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x {{.*}}>
-
-// LLVM: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %{{.*}}, i32 3
+// LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]])
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> [[A]], i32 3
// LLVM: ret i32 [[VGETQ_LANE]]
return vgetq_lane_u32(a, 3);
}
@@ -156,8 +156,8 @@ uint32_t test_vgetq_lane_u32(uint32x4_t a) {
// ALL-LABEL: @test_vgetq_lane_s8(
int8_t test_vgetq_lane_s8(int8x16_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<16 x !s8i>
-
-// LLVM: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %{{.*}}, i32 15
+// LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]])
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> [[A]], i32 15
// LLVM: ret i8 [[VGETQ_LANE]]
return vgetq_lane_s8(a, 15);
}
@@ -165,8 +165,8 @@ int8_t test_vgetq_lane_s8(int8x16_t a) {
// ALL-LABEL: @test_vgetq_lane_s16(
int16_t test_vgetq_lane_s16(int16x8_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !s16i>
-
-// LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %{{.*}}, i32 7
+// LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]])
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> [[A]], i32 7
// LLVM: ret i16 [[VGETQ_LANE]]
return vgetq_lane_s16(a, 7);
}
@@ -174,8 +174,8 @@ int16_t test_vgetq_lane_s16(int16x8_t a) {
// ALL-LABEL: @test_vgetq_lane_s32(
int32_t test_vgetq_lane_s32(int32x4_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !s32i>
-
-// LLVM: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %{{.*}}, i32 3
+// LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]])
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> [[A]], i32 3
// LLVM: ret i32 [[VGETQ_LANE]]
return vgetq_lane_s32(a, 3);
}
@@ -183,8 +183,8 @@ int32_t test_vgetq_lane_s32(int32x4_t a) {
// ALL-LABEL: @test_vgetq_lane_p8(
poly8_t test_vgetq_lane_p8(poly8x16_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<16 x {{.*}}>
-
-// LLVM: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %{{.*}}, i32 15
+// LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]])
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> [[A]], i32 15
// LLVM: ret i8 [[VGETQ_LANE]]
return vgetq_lane_p8(a, 15);
}
@@ -192,8 +192,8 @@ poly8_t test_vgetq_lane_p8(poly8x16_t a) {
// ALL-LABEL: @test_vgetq_lane_p16(
poly16_t test_vgetq_lane_p16(poly16x8_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x {{.*}}>
-
-// LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %{{.*}}, i32 7
+// LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]])
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> [[A]], i32 7
// LLVM: ret i16 [[VGETQ_LANE]]
return vgetq_lane_p16(a, 7);
}
@@ -203,8 +203,8 @@ float32_t test_vgetq_lane_f16(float16x8_t a) {
// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<8 x !cir.f16>> -> !cir.ptr<!cir.vector<8 x !s16i>>
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !s16i>
// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!s16i> -> !cir.ptr<!cir.f16>
-
-// LLVM: [[TMP:%.*]] = bitcast <8 x half> %{{.*}} to <8 x i16>
+// LLVM-SAME: <8 x half> {{.*}} [[A:%.*]])
+// LLVM: [[TMP:%.*]] = bitcast <8 x half> [[A]] to <8 x i16>
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> [[TMP]], i32 3
// LLVM: [[HALF:%.*]] = bitcast i16 [[VGETQ_LANE]] to half
// LLVM: [[RES:%.*]] = fpext half [[HALF]] to float
@@ -215,8 +215,8 @@ float32_t test_vgetq_lane_f16(float16x8_t a) {
// ALL-LABEL: @test_vgetq_lane_f32(
float32_t test_vgetq_lane_f32(float32x4_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<4 x !cir.float>
-
-// LLVM: [[VGETQ_LANE:%.*]] = extractelement <4 x float> %{{.*}}, i32 3
+// LLVM-SAME: <4 x float> {{.*}} [[A:%.*]])
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <4 x float> [[A]], i32 3
// LLVM: ret float [[VGETQ_LANE]]
return vgetq_lane_f32(a, 3);
}
@@ -224,8 +224,8 @@ float32_t test_vgetq_lane_f32(float32x4_t a) {
// ALL-LABEL: @test_vgetq_lane_f64(
float64_t test_vgetq_lane_f64(float64x2_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<2 x !cir.double>
-
-// LLVM: [[VGETQ_LANE:%.*]] = extractelement <2 x double> %{{.*}}, i32 1
+// LLVM-SAME: <2 x double> {{.*}} [[A:%.*]])
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <2 x double> [[A]], i32 1
// LLVM: ret double [[VGETQ_LANE]]
return vgetq_lane_f64(a, 1);
}
@@ -233,8 +233,8 @@ float64_t test_vgetq_lane_f64(float64x2_t a) {
// ALL-LABEL: @test_vget_lane_s64(
int64_t test_vget_lane_s64(int64x1_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<1 x !s64i>
-
-// LLVM: [[VGET_LANE:%.*]] = extractelement <1 x i64> %{{.*}}, i32 0
+// LLVM-SAME: <1 x i64> {{.*}} [[A:%.*]])
+// LLVM: [[VGET_LANE:%.*]] = extractelement <1 x i64> [[A]], i32 0
// LLVM: ret i64 [[VGET_LANE]]
return vget_lane_s64(a, 0);
}
@@ -242,8 +242,8 @@ int64_t test_vget_lane_s64(int64x1_t a) {
// ALL-LABEL: @test_vget_lane_u64(
uint64_t test_vget_lane_u64(uint64x1_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<1 x {{.*}}>
-
-// LLVM: [[VGET_LANE:%.*]] = extractelement <1 x i64> %{{.*}}, i32 0
+// LLVM-SAME: <1 x i64> {{.*}} [[A:%.*]])
+// LLVM: [[VGET_LANE:%.*]] = extractelement <1 x i64> [[A]], i32 0
// LLVM: ret i64 [[VGET_LANE]]
return vget_lane_u64(a, 0);
}
@@ -251,8 +251,8 @@ uint64_t test_vget_lane_u64(uint64x1_t a) {
// ALL-LABEL: @test_vget_lane_p64(
poly64_t test_vget_lane_p64(poly64x1_t v) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<1 x {{.*}}>
-
-// LLVM: [[VGET_LANE:%.*]] = extractelement <1 x i64> %{{.*}}, i32 0
+// LLVM-SAME: <1 x i64> {{.*}} [[V:%.*]])
+// LLVM: [[VGET_LANE:%.*]] = extractelement <1 x i64> [[V]], i32 0
// LLVM: ret i64 [[VGET_LANE]]
return vget_lane_p64(v, 0);
}
@@ -260,8 +260,8 @@ poly64_t test_vget_lane_p64(poly64x1_t v) {
// ALL-LABEL: @test_vgetq_lane_s64(
int64_t test_vgetq_lane_s64(int64x2_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x !s64i>
-
-// LLVM: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %{{.*}}, i32 1
+// LLVM-SAME: <2 x i64> {{.*}} [[A:%.*]])
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> [[A]], i32 1
// LLVM: ret i64 [[VGETQ_LANE]]
return vgetq_lane_s64(a, 1);
}
@@ -269,8 +269,8 @@ int64_t test_vgetq_lane_s64(int64x2_t a) {
// ALL-LABEL: @test_vgetq_lane_u64(
uint64_t test_vgetq_lane_u64(uint64x2_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x {{.*}}>
-
-// LLVM: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %{{.*}}, i32 1
+// LLVM-SAME: <2 x i64> {{.*}} [[A:%.*]])
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> [[A]], i32 1
// LLVM: ret i64 [[VGETQ_LANE]]
return vgetq_lane_u64(a, 1);
}
@@ -278,8 +278,8 @@ uint64_t test_vgetq_lane_u64(uint64x2_t a) {
// ALL-LABEL: @test_vgetq_lane_p64(
poly64_t test_vgetq_lane_p64(poly64x2_t v) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x {{.*}}>
-
-// LLVM: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %{{.*}}, i32 1
+// LLVM-SAME: <2 x i64> {{.*}} [[V:%.*]])
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> [[V]], i32 1
// LLVM: ret i64 [[VGETQ_LANE]]
return vgetq_lane_p64(v, 1);
}
>From 510b2b9040c39dfd3411472530259177829dbd01 Mon Sep 17 00:00:00 2001
From: Ayush3941 <ayushkgaur1 at gmail.com>
Date: Fri, 1 May 2026 18:37:24 -0400
Subject: [PATCH 16/17] [CIR][AArch64] Upstream Neon vget_lane/vgetq_lane
builtins v9
---
.../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 71 +-----
clang/test/CodeGen/AArch64/neon-scalar-copy.c | 192 ---------------
clang/test/CodeGen/AArch64/neon/getset.c | 227 +++++++++++++++++-
3 files changed, 231 insertions(+), 259 deletions(-)
delete mode 100644 clang/test/CodeGen/AArch64/neon-scalar-copy.c
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index 38b95130bbcfe..ed191e9a21141 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -2225,94 +2225,35 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_i8:
- return emitAArch64GetLaneBuiltinExpr(builder, loc, ops[0],
- emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupb_lane_i8:
- cgm.errorNYI(expr->getSourceRange(),
- std::string("unimplemented AArch64 builtin call: ") +
- getContext().BuiltinInfo.getName(builtinID));
- return mlir::Value{};
-
case NEON::BI__builtin_neon_vgetq_lane_i8:
- return emitAArch64GetLaneBuiltinExpr(builder, loc, ops[0],
- emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupb_laneq_i8:
- case NEON::BI__builtin_neon_vget_lane_mf8:
- case NEON::BI__builtin_neon_vdupb_lane_mf8:
- case NEON::BI__builtin_neon_vgetq_lane_mf8:
- case NEON::BI__builtin_neon_vdupb_laneq_mf8:
- cgm.errorNYI(expr->getSourceRange(),
- std::string("unimplemented AArch64 builtin call: ") +
- getContext().BuiltinInfo.getName(builtinID));
- return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_i16:
- return emitAArch64GetLaneBuiltinExpr(builder, loc, ops[0],
- emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vduph_lane_i16:
- cgm.errorNYI(expr->getSourceRange(),
- std::string("unimplemented AArch64 builtin call: ") +
- getContext().BuiltinInfo.getName(builtinID));
- return mlir::Value{};
case NEON::BI__builtin_neon_vgetq_lane_i16:
- return emitAArch64GetLaneBuiltinExpr(builder, loc, ops[0],
- emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vduph_laneq_i16:
- cgm.errorNYI(expr->getSourceRange(),
- std::string("unimplemented AArch64 builtin call: ") +
- getContext().BuiltinInfo.getName(builtinID));
- return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_i32:
- return emitAArch64GetLaneBuiltinExpr(builder, loc, ops[0],
- emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdups_lane_i32:
case NEON::BI__builtin_neon_vdups_lane_f32:
- cgm.errorNYI(expr->getSourceRange(),
- std::string("unimplemented AArch64 builtin call: ") +
- getContext().BuiltinInfo.getName(builtinID));
- return mlir::Value{};
case NEON::BI__builtin_neon_vgetq_lane_i32:
- return emitAArch64GetLaneBuiltinExpr(builder, loc, ops[0],
- emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdups_laneq_i32:
- cgm.errorNYI(expr->getSourceRange(),
- std::string("unimplemented AArch64 builtin call: ") +
- getContext().BuiltinInfo.getName(builtinID));
- return mlir::Value{};
+ case NEON::BI__builtin_neon_vdups_laneq_f32:
case NEON::BI__builtin_neon_vget_lane_i64:
- return emitAArch64GetLaneBuiltinExpr(builder, loc, ops[0],
- emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupd_lane_i64:
case NEON::BI__builtin_neon_vdupd_lane_f64:
- cgm.errorNYI(expr->getSourceRange(),
- std::string("unimplemented AArch64 builtin call: ") +
- getContext().BuiltinInfo.getName(builtinID));
- return mlir::Value{};
case NEON::BI__builtin_neon_vgetq_lane_i64:
- return emitAArch64GetLaneBuiltinExpr(builder, loc, ops[0],
- emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vdupd_laneq_i64:
- cgm.errorNYI(expr->getSourceRange(),
- std::string("unimplemented AArch64 builtin call: ") +
- getContext().BuiltinInfo.getName(builtinID));
- return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_f32:
- return emitAArch64GetLaneBuiltinExpr(builder, loc, ops[0],
- emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vget_lane_f64:
- return emitAArch64GetLaneBuiltinExpr(builder, loc, ops[0],
- emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vgetq_lane_f32:
- return emitAArch64GetLaneBuiltinExpr(builder, loc, ops[0],
- emitScalarExpr(expr->getArg(1)));
- case NEON::BI__builtin_neon_vdups_laneq_f32:
- cgm.errorNYI(expr->getSourceRange(),
- std::string("unimplemented AArch64 builtin call: ") +
- getContext().BuiltinInfo.getName(builtinID));
- return mlir::Value{};
case NEON::BI__builtin_neon_vgetq_lane_f64:
+ case NEON::BI__builtin_neon_vdupd_laneq_f64:
return emitAArch64GetLaneBuiltinExpr(builder, loc, ops[0],
emitScalarExpr(expr->getArg(1)));
- case NEON::BI__builtin_neon_vdupd_laneq_f64:
+ case NEON::BI__builtin_neon_vget_lane_mf8:
+ case NEON::BI__builtin_neon_vdupb_lane_mf8:
+ case NEON::BI__builtin_neon_vgetq_lane_mf8:
+ case NEON::BI__builtin_neon_vdupb_laneq_mf8:
cgm.errorNYI(expr->getSourceRange(),
std::string("unimplemented AArch64 builtin call: ") +
getContext().BuiltinInfo.getName(builtinID));
diff --git a/clang/test/CodeGen/AArch64/neon-scalar-copy.c b/clang/test/CodeGen/AArch64/neon-scalar-copy.c
deleted file mode 100644
index bd80068e5bf85..0000000000000
--- a/clang/test/CodeGen/AArch64/neon-scalar-copy.c
+++ /dev/null
@@ -1,192 +0,0 @@
-// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -flax-vector-conversions=none\
-// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s
-
-// REQUIRES: aarch64-registered-target || arm-registered-target
-
-#include <arm_neon.h>
-
-// CHECK-LABEL: define{{.*}} float @test_vdups_lane_f32(<2 x float> noundef %a) #0 {
-// CHECK: [[VDUPS_LANE:%.*]] = extractelement <2 x float> %a, i32 1
-// CHECK: ret float [[VDUPS_LANE]]
-float32_t test_vdups_lane_f32(float32x2_t a) {
- return vdups_lane_f32(a, 1);
-}
-
-
-// CHECK-LABEL: define{{.*}} double @test_vdupd_lane_f64(<1 x double> noundef %a) #0 {
-// CHECK: [[VDUPD_LANE:%.*]] = extractelement <1 x double> %a, i32 0
-// CHECK: ret double [[VDUPD_LANE]]
-float64_t test_vdupd_lane_f64(float64x1_t a) {
- return vdupd_lane_f64(a, 0);
-}
-
-
-// CHECK-LABEL: define{{.*}} float @test_vdups_laneq_f32(<4 x float> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x float> %a, i32 3
-// CHECK: ret float [[VGETQ_LANE]]
-float32_t test_vdups_laneq_f32(float32x4_t a) {
- return vdups_laneq_f32(a, 3);
-}
-
-
-// CHECK-LABEL: define{{.*}} double @test_vdupd_laneq_f64(<2 x double> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x double> %a, i32 1
-// CHECK: ret double [[VGETQ_LANE]]
-float64_t test_vdupd_laneq_f64(float64x2_t a) {
- return vdupd_laneq_f64(a, 1);
-}
-
-
-// CHECK-LABEL: define{{.*}} i8 @test_vdupb_lane_s8(<8 x i8> noundef %a) #0 {
-// CHECK: [[VGET_LANE:%.*]] = extractelement <8 x i8> %a, i32 7
-// CHECK: ret i8 [[VGET_LANE]]
-int8_t test_vdupb_lane_s8(int8x8_t a) {
- return vdupb_lane_s8(a, 7);
-}
-
-
-// CHECK-LABEL: define{{.*}} i16 @test_vduph_lane_s16(<4 x i16> noundef %a) #0 {
-// CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> %a, i32 3
-// CHECK: ret i16 [[VGET_LANE]]
-int16_t test_vduph_lane_s16(int16x4_t a) {
- return vduph_lane_s16(a, 3);
-}
-
-
-// CHECK-LABEL: define{{.*}} i32 @test_vdups_lane_s32(<2 x i32> noundef %a) #0 {
-// CHECK: [[VGET_LANE:%.*]] = extractelement <2 x i32> %a, i32 1
-// CHECK: ret i32 [[VGET_LANE]]
-int32_t test_vdups_lane_s32(int32x2_t a) {
- return vdups_lane_s32(a, 1);
-}
-
-
-// CHECK-LABEL: define{{.*}} i64 @test_vdupd_lane_s64(<1 x i64> noundef %a) #0 {
-// CHECK: [[VGET_LANE:%.*]] = extractelement <1 x i64> %a, i32 0
-// CHECK: ret i64 [[VGET_LANE]]
-int64_t test_vdupd_lane_s64(int64x1_t a) {
- return vdupd_lane_s64(a, 0);
-}
-
-
-// CHECK-LABEL: define{{.*}} i8 @test_vdupb_lane_u8(<8 x i8> noundef %a) #0 {
-// CHECK: [[VGET_LANE:%.*]] = extractelement <8 x i8> %a, i32 7
-// CHECK: ret i8 [[VGET_LANE]]
-uint8_t test_vdupb_lane_u8(uint8x8_t a) {
- return vdupb_lane_u8(a, 7);
-}
-
-
-// CHECK-LABEL: define{{.*}} i16 @test_vduph_lane_u16(<4 x i16> noundef %a) #0 {
-// CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> %a, i32 3
-// CHECK: ret i16 [[VGET_LANE]]
-uint16_t test_vduph_lane_u16(uint16x4_t a) {
- return vduph_lane_u16(a, 3);
-}
-
-
-// CHECK-LABEL: define{{.*}} i32 @test_vdups_lane_u32(<2 x i32> noundef %a) #0 {
-// CHECK: [[VGET_LANE:%.*]] = extractelement <2 x i32> %a, i32 1
-// CHECK: ret i32 [[VGET_LANE]]
-uint32_t test_vdups_lane_u32(uint32x2_t a) {
- return vdups_lane_u32(a, 1);
-}
-
-
-// CHECK-LABEL: define{{.*}} i64 @test_vdupd_lane_u64(<1 x i64> noundef %a) #0 {
-// CHECK: [[VGET_LANE:%.*]] = extractelement <1 x i64> %a, i32 0
-// CHECK: ret i64 [[VGET_LANE]]
-uint64_t test_vdupd_lane_u64(uint64x1_t a) {
- return vdupd_lane_u64(a, 0);
-}
-
-// CHECK-LABEL: define{{.*}} i8 @test_vdupb_laneq_s8(<16 x i8> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %a, i32 15
-// CHECK: ret i8 [[VGETQ_LANE]]
-int8_t test_vdupb_laneq_s8(int8x16_t a) {
- return vdupb_laneq_s8(a, 15);
-}
-
-
-// CHECK-LABEL: define{{.*}} i16 @test_vduph_laneq_s16(<8 x i16> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %a, i32 7
-// CHECK: ret i16 [[VGETQ_LANE]]
-int16_t test_vduph_laneq_s16(int16x8_t a) {
- return vduph_laneq_s16(a, 7);
-}
-
-
-// CHECK-LABEL: define{{.*}} i32 @test_vdups_laneq_s32(<4 x i32> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %a, i32 3
-// CHECK: ret i32 [[VGETQ_LANE]]
-int32_t test_vdups_laneq_s32(int32x4_t a) {
- return vdups_laneq_s32(a, 3);
-}
-
-
-// CHECK-LABEL: define{{.*}} i64 @test_vdupd_laneq_s64(<2 x i64> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %a, i32 1
-// CHECK: ret i64 [[VGETQ_LANE]]
-int64_t test_vdupd_laneq_s64(int64x2_t a) {
- return vdupd_laneq_s64(a, 1);
-}
-
-
-// CHECK-LABEL: define{{.*}} i8 @test_vdupb_laneq_u8(<16 x i8> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %a, i32 15
-// CHECK: ret i8 [[VGETQ_LANE]]
-uint8_t test_vdupb_laneq_u8(uint8x16_t a) {
- return vdupb_laneq_u8(a, 15);
-}
-
-
-// CHECK-LABEL: define{{.*}} i16 @test_vduph_laneq_u16(<8 x i16> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %a, i32 7
-// CHECK: ret i16 [[VGETQ_LANE]]
-uint16_t test_vduph_laneq_u16(uint16x8_t a) {
- return vduph_laneq_u16(a, 7);
-}
-
-
-// CHECK-LABEL: define{{.*}} i32 @test_vdups_laneq_u32(<4 x i32> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %a, i32 3
-// CHECK: ret i32 [[VGETQ_LANE]]
-uint32_t test_vdups_laneq_u32(uint32x4_t a) {
- return vdups_laneq_u32(a, 3);
-}
-
-
-// CHECK-LABEL: define{{.*}} i64 @test_vdupd_laneq_u64(<2 x i64> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %a, i32 1
-// CHECK: ret i64 [[VGETQ_LANE]]
-uint64_t test_vdupd_laneq_u64(uint64x2_t a) {
- return vdupd_laneq_u64(a, 1);
-}
-
-// CHECK-LABEL: define{{.*}} i8 @test_vdupb_lane_p8(<8 x i8> noundef %a) #0 {
-// CHECK: [[VGET_LANE:%.*]] = extractelement <8 x i8> %a, i32 7
-// CHECK: ret i8 [[VGET_LANE]]
-poly8_t test_vdupb_lane_p8(poly8x8_t a) {
- return vdupb_lane_p8(a, 7);
-}
-
-// CHECK-LABEL: define{{.*}} i16 @test_vduph_lane_p16(<4 x i16> noundef %a) #0 {
-// CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> %a, i32 3
-// CHECK: ret i16 [[VGET_LANE]]
-poly16_t test_vduph_lane_p16(poly16x4_t a) {
- return vduph_lane_p16(a, 3);
-}
-
-// CHECK-LABEL: define{{.*}} i8 @test_vdupb_laneq_p8(<16 x i8> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %a, i32 15
-// CHECK: ret i8 [[VGETQ_LANE]]
-poly8_t test_vdupb_laneq_p8(poly8x16_t a) {
- return vdupb_laneq_p8(a, 15);
-}
-
-// CHECK-LABEL: define{{.*}} i16 @test_vduph_laneq_p16(<8 x i16> noundef %a) #0 {
-// CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %a, i32 7
-// CHECK: ret i16 [[VGETQ_LANE]]
-poly16_t test_vduph_laneq_p16(poly16x8_t a) {
- return vduph_laneq_p16(a, 7);
-}
diff --git a/clang/test/CodeGen/AArch64/neon/getset.c b/clang/test/CodeGen/AArch64/neon/getset.c
index 3aa5f18a7160c..90dcd0f53209a 100644
--- a/clang/test/CodeGen/AArch64/neon/getset.c
+++ b/clang/test/CodeGen/AArch64/neon/getset.c
@@ -9,6 +9,7 @@
//
// This file contains tests that were originally located in
// * clang/test/CodeGen/AArch64/neon-vget.c
+// * clang/test/CodeGen/AArch64/neon-scalar-copy.c
// * clang/test/CodeGen/AArch64/poly64.c
// The main difference is the use of RUN lines that enable ClangIR lowering;
// therefore only builtins currently supported by ClangIR are tested here.
@@ -19,8 +20,12 @@
//===------------------------------------------------------===//
// 2.1.9.7 Extract one element from vector
//===------------------------------------------------------===//
-// TODO(cir): Add mf8 vget_lane/vgetq_lane coverage once NEON MFloat8 support
-// is available in ClangIR.
+// TODO(cir): Add mf8 extract-lane coverage once NEON MFloat8 support is
+// available in ClangIR.
+//
+// This section covers both vget_lane/vgetq_lane and the scalar
+// vdup[b/h/s/d]_(lane|laneq)_* builtins.
+// The vector-broadcast vdup_lane/vdupq_lane family is covered elsewhere.
// ALL-LABEL: @test_vget_lane_u8(
uint8_t test_vget_lane_u8(uint8x8_t a) {
@@ -283,3 +288,221 @@ poly64_t test_vgetq_lane_p64(poly64x2_t v) {
// LLVM: ret i64 [[VGETQ_LANE]]
return vgetq_lane_p64(v, 1);
}
+
+// Scalar vdup lane builtins are modeled as extract-one-element operations too.
+
+// ALL-LABEL: @test_vdups_lane_f32(
+float32_t test_vdups_lane_f32(float32x2_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<2 x !cir.float>
+// LLVM-SAME: <2 x float> {{.*}} [[A:%.*]])
+// LLVM: [[VDUP_LANE:%.*]] = extractelement <2 x float> [[A]], i32 1
+// LLVM: ret float [[VDUP_LANE]]
+ return vdups_lane_f32(a, 1);
+}
+
+// ALL-LABEL: @test_vdupd_lane_f64(
+float64_t test_vdupd_lane_f64(float64x1_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<1 x !cir.double>
+// LLVM-SAME: <1 x double> {{.*}} [[A:%.*]])
+// LLVM: [[VDUP_LANE:%.*]] = extractelement <1 x double> [[A]], i32 0
+// LLVM: ret double [[VDUP_LANE]]
+ return vdupd_lane_f64(a, 0);
+}
+
+// ALL-LABEL: @test_vdups_laneq_f32(
+float32_t test_vdups_laneq_f32(float32x4_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<4 x !cir.float>
+// LLVM-SAME: <4 x float> {{.*}} [[A:%.*]])
+// LLVM: [[VDUPQ_LANE:%.*]] = extractelement <4 x float> [[A]], i32 3
+// LLVM: ret float [[VDUPQ_LANE]]
+ return vdups_laneq_f32(a, 3);
+}
+
+// ALL-LABEL: @test_vdupd_laneq_f64(
+float64_t test_vdupd_laneq_f64(float64x2_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<2 x !cir.double>
+// LLVM-SAME: <2 x double> {{.*}} [[A:%.*]])
+// LLVM: [[VDUPQ_LANE:%.*]] = extractelement <2 x double> [[A]], i32 1
+// LLVM: ret double [[VDUPQ_LANE]]
+ return vdupd_laneq_f64(a, 1);
+}
+
+// ALL-LABEL: @test_vdupb_lane_s8(
+int8_t test_vdupb_lane_s8(int8x8_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !s8i>
+// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]])
+// LLVM: [[VDUP_LANE:%.*]] = extractelement <8 x i8> [[A]], i32 7
+// LLVM: ret i8 [[VDUP_LANE]]
+ return vdupb_lane_s8(a, 7);
+}
+
+// ALL-LABEL: @test_vduph_lane_s16(
+int16_t test_vduph_lane_s16(int16x4_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !s16i>
+// LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]])
+// LLVM: [[VDUP_LANE:%.*]] = extractelement <4 x i16> [[A]], i32 3
+// LLVM: ret i16 [[VDUP_LANE]]
+ return vduph_lane_s16(a, 3);
+}
+
+// ALL-LABEL: @test_vdups_lane_s32(
+int32_t test_vdups_lane_s32(int32x2_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x !s32i>
+// LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]])
+// LLVM: [[VDUP_LANE:%.*]] = extractelement <2 x i32> [[A]], i32 1
+// LLVM: ret i32 [[VDUP_LANE]]
+ return vdups_lane_s32(a, 1);
+}
+
+// ALL-LABEL: @test_vdupd_lane_s64(
+int64_t test_vdupd_lane_s64(int64x1_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<1 x !s64i>
+// LLVM-SAME: <1 x i64> {{.*}} [[A:%.*]])
+// LLVM: [[VDUP_LANE:%.*]] = extractelement <1 x i64> [[A]], i32 0
+// LLVM: ret i64 [[VDUP_LANE]]
+ return vdupd_lane_s64(a, 0);
+}
+
+// ALL-LABEL: @test_vdupb_lane_u8(
+uint8_t test_vdupb_lane_u8(uint8x8_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x {{.*}}>
+// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]])
+// LLVM: [[VDUP_LANE:%.*]] = extractelement <8 x i8> [[A]], i32 7
+// LLVM: ret i8 [[VDUP_LANE]]
+ return vdupb_lane_u8(a, 7);
+}
+
+// ALL-LABEL: @test_vduph_lane_u16(
+uint16_t test_vduph_lane_u16(uint16x4_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x {{.*}}>
+// LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]])
+// LLVM: [[VDUP_LANE:%.*]] = extractelement <4 x i16> [[A]], i32 3
+// LLVM: ret i16 [[VDUP_LANE]]
+ return vduph_lane_u16(a, 3);
+}
+
+// ALL-LABEL: @test_vdups_lane_u32(
+uint32_t test_vdups_lane_u32(uint32x2_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x {{.*}}>
+// LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]])
+// LLVM: [[VDUP_LANE:%.*]] = extractelement <2 x i32> [[A]], i32 1
+// LLVM: ret i32 [[VDUP_LANE]]
+ return vdups_lane_u32(a, 1);
+}
+
+// ALL-LABEL: @test_vdupd_lane_u64(
+uint64_t test_vdupd_lane_u64(uint64x1_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<1 x {{.*}}>
+// LLVM-SAME: <1 x i64> {{.*}} [[A:%.*]])
+// LLVM: [[VDUP_LANE:%.*]] = extractelement <1 x i64> [[A]], i32 0
+// LLVM: ret i64 [[VDUP_LANE]]
+ return vdupd_lane_u64(a, 0);
+}
+
+// ALL-LABEL: @test_vdupb_laneq_s8(
+int8_t test_vdupb_laneq_s8(int8x16_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<16 x !s8i>
+// LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]])
+// LLVM: [[VDUPQ_LANE:%.*]] = extractelement <16 x i8> [[A]], i32 15
+// LLVM: ret i8 [[VDUPQ_LANE]]
+ return vdupb_laneq_s8(a, 15);
+}
+
+// ALL-LABEL: @test_vduph_laneq_s16(
+int16_t test_vduph_laneq_s16(int16x8_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !s16i>
+// LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]])
+// LLVM: [[VDUPQ_LANE:%.*]] = extractelement <8 x i16> [[A]], i32 7
+// LLVM: ret i16 [[VDUPQ_LANE]]
+ return vduph_laneq_s16(a, 7);
+}
+
+// ALL-LABEL: @test_vdups_laneq_s32(
+int32_t test_vdups_laneq_s32(int32x4_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !s32i>
+// LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]])
+// LLVM: [[VDUPQ_LANE:%.*]] = extractelement <4 x i32> [[A]], i32 3
+// LLVM: ret i32 [[VDUPQ_LANE]]
+ return vdups_laneq_s32(a, 3);
+}
+
+// ALL-LABEL: @test_vdupd_laneq_s64(
+int64_t test_vdupd_laneq_s64(int64x2_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x !s64i>
+// LLVM-SAME: <2 x i64> {{.*}} [[A:%.*]])
+// LLVM: [[VDUPQ_LANE:%.*]] = extractelement <2 x i64> [[A]], i32 1
+// LLVM: ret i64 [[VDUPQ_LANE]]
+ return vdupd_laneq_s64(a, 1);
+}
+
+// ALL-LABEL: @test_vdupb_laneq_u8(
+uint8_t test_vdupb_laneq_u8(uint8x16_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<16 x {{.*}}>
+// LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]])
+// LLVM: [[VDUPQ_LANE:%.*]] = extractelement <16 x i8> [[A]], i32 15
+// LLVM: ret i8 [[VDUPQ_LANE]]
+ return vdupb_laneq_u8(a, 15);
+}
+
+// ALL-LABEL: @test_vduph_laneq_u16(
+uint16_t test_vduph_laneq_u16(uint16x8_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x {{.*}}>
+// LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]])
+// LLVM: [[VDUPQ_LANE:%.*]] = extractelement <8 x i16> [[A]], i32 7
+// LLVM: ret i16 [[VDUPQ_LANE]]
+ return vduph_laneq_u16(a, 7);
+}
+
+// ALL-LABEL: @test_vdups_laneq_u32(
+uint32_t test_vdups_laneq_u32(uint32x4_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x {{.*}}>
+// LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]])
+// LLVM: [[VDUPQ_LANE:%.*]] = extractelement <4 x i32> [[A]], i32 3
+// LLVM: ret i32 [[VDUPQ_LANE]]
+ return vdups_laneq_u32(a, 3);
+}
+
+// ALL-LABEL: @test_vdupd_laneq_u64(
+uint64_t test_vdupd_laneq_u64(uint64x2_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x {{.*}}>
+// LLVM-SAME: <2 x i64> {{.*}} [[A:%.*]])
+// LLVM: [[VDUPQ_LANE:%.*]] = extractelement <2 x i64> [[A]], i32 1
+// LLVM: ret i64 [[VDUPQ_LANE]]
+ return vdupd_laneq_u64(a, 1);
+}
+
+// ALL-LABEL: @test_vdupb_lane_p8(
+poly8_t test_vdupb_lane_p8(poly8x8_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x {{.*}}>
+// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]])
+// LLVM: [[VDUP_LANE:%.*]] = extractelement <8 x i8> [[A]], i32 7
+// LLVM: ret i8 [[VDUP_LANE]]
+ return vdupb_lane_p8(a, 7);
+}
+
+// ALL-LABEL: @test_vduph_lane_p16(
+poly16_t test_vduph_lane_p16(poly16x4_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x {{.*}}>
+// LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]])
+// LLVM: [[VDUP_LANE:%.*]] = extractelement <4 x i16> [[A]], i32 3
+// LLVM: ret i16 [[VDUP_LANE]]
+ return vduph_lane_p16(a, 3);
+}
+
+// ALL-LABEL: @test_vdupb_laneq_p8(
+poly8_t test_vdupb_laneq_p8(poly8x16_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<16 x {{.*}}>
+// LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]])
+// LLVM: [[VDUPQ_LANE:%.*]] = extractelement <16 x i8> [[A]], i32 15
+// LLVM: ret i8 [[VDUPQ_LANE]]
+ return vdupb_laneq_p8(a, 15);
+}
+
+// ALL-LABEL: @test_vduph_laneq_p16(
+poly16_t test_vduph_laneq_p16(poly16x8_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x {{.*}}>
+// LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]])
+// LLVM: [[VDUPQ_LANE:%.*]] = extractelement <8 x i16> [[A]], i32 7
+// LLVM: ret i16 [[VDUPQ_LANE]]
+ return vduph_laneq_p16(a, 7);
+}
>From 9fd1bf8e4235337d712a8bea68121907b4c7a75d Mon Sep 17 00:00:00 2001
From: Ayush3941 <ayushkgaur1 at gmail.com>
Date: Sat, 9 May 2026 15:50:51 -0400
Subject: [PATCH 17/17] [CIR][AArch64] Upstream Neon vget_lane/vgetq_lane
builtins v10
---
.../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 37 ++++++------
clang/test/CodeGen/AArch64/neon/getset.c | 57 ++++++++++++++++++-
clang/test/CodeGen/AArch64/poly64.c | 20 -------
3 files changed, 73 insertions(+), 41 deletions(-)
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index ed191e9a21141..f16adc086daea 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -763,13 +763,6 @@ static mlir::Value emitCommonNeonBuiltinExpr(
}
}
-static mlir::Value emitAArch64GetLaneBuiltinExpr(CIRGenBuilderTy &builder,
- mlir::Location loc,
- mlir::Value vec,
- mlir::Value lane) {
- return cir::VecExtractOp::create(builder, loc, vec, lane);
-}
-
// Emit an intrinsic where all operands are of the same type as the result.
// Depending on mode, this may be a constrained floating-point intrinsic.
static mlir::Value
@@ -2228,36 +2221,44 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
case NEON::BI__builtin_neon_vdupb_lane_i8:
case NEON::BI__builtin_neon_vgetq_lane_i8:
case NEON::BI__builtin_neon_vdupb_laneq_i8:
+ return cir::VecExtractOp::create(builder, loc, ops[0],
+ emitScalarExpr(expr->getArg(1)));
+ case NEON::BI__builtin_neon_vget_lane_mf8:
+ case NEON::BI__builtin_neon_vdupb_lane_mf8:
+ case NEON::BI__builtin_neon_vgetq_lane_mf8:
+ case NEON::BI__builtin_neon_vdupb_laneq_mf8:
+ cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+ return mlir::Value{};
case NEON::BI__builtin_neon_vget_lane_i16:
case NEON::BI__builtin_neon_vduph_lane_i16:
case NEON::BI__builtin_neon_vgetq_lane_i16:
case NEON::BI__builtin_neon_vduph_laneq_i16:
+ return cir::VecExtractOp::create(builder, loc, ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vget_lane_i32:
case NEON::BI__builtin_neon_vdups_lane_i32:
case NEON::BI__builtin_neon_vdups_lane_f32:
case NEON::BI__builtin_neon_vgetq_lane_i32:
case NEON::BI__builtin_neon_vdups_laneq_i32:
- case NEON::BI__builtin_neon_vdups_laneq_f32:
+ return cir::VecExtractOp::create(builder, loc, ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vget_lane_i64:
case NEON::BI__builtin_neon_vdupd_lane_i64:
case NEON::BI__builtin_neon_vdupd_lane_f64:
case NEON::BI__builtin_neon_vgetq_lane_i64:
case NEON::BI__builtin_neon_vdupd_laneq_i64:
+ return cir::VecExtractOp::create(builder, loc, ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vget_lane_f32:
case NEON::BI__builtin_neon_vget_lane_f64:
case NEON::BI__builtin_neon_vgetq_lane_f32:
+ case NEON::BI__builtin_neon_vdups_laneq_f32:
case NEON::BI__builtin_neon_vgetq_lane_f64:
case NEON::BI__builtin_neon_vdupd_laneq_f64:
- return emitAArch64GetLaneBuiltinExpr(builder, loc, ops[0],
- emitScalarExpr(expr->getArg(1)));
- case NEON::BI__builtin_neon_vget_lane_mf8:
- case NEON::BI__builtin_neon_vdupb_lane_mf8:
- case NEON::BI__builtin_neon_vgetq_lane_mf8:
- case NEON::BI__builtin_neon_vdupb_laneq_mf8:
- cgm.errorNYI(expr->getSourceRange(),
- std::string("unimplemented AArch64 builtin call: ") +
- getContext().BuiltinInfo.getName(builtinID));
- return mlir::Value{};
+ return cir::VecExtractOp::create(builder, loc, ops[0],
+ emitScalarExpr(expr->getArg(1)));
case NEON::BI__builtin_neon_vaddh_f16:
return builder.createFAdd(loc, ops[0], ops[1]);
case NEON::BI__builtin_neon_vsubh_f16:
diff --git a/clang/test/CodeGen/AArch64/neon/getset.c b/clang/test/CodeGen/AArch64/neon/getset.c
index 90dcd0f53209a..974b0e1a7f88c 100644
--- a/clang/test/CodeGen/AArch64/neon/getset.c
+++ b/clang/test/CodeGen/AArch64/neon/getset.c
@@ -20,16 +20,16 @@
//===------------------------------------------------------===//
// 2.1.9.7 Extract one element from vector
//===------------------------------------------------------===//
-// TODO(cir): Add mf8 extract-lane coverage once NEON MFloat8 support is
-// available in ClangIR.
+// TODO(cir): Once the mf8 extract-lane builtins are implemented in ClangIR,
+// migrate their coverage from fp8-intrinsics/acle_neon_fp8_untyped.c.
//
// This section covers both vget_lane/vgetq_lane and the scalar
// vdup[b/h/s/d]_(lane|laneq)_* builtins.
-// The vector-broadcast vdup_lane/vdupq_lane family is covered elsewhere.
// ALL-LABEL: @test_vget_lane_u8(
uint8_t test_vget_lane_u8(uint8x8_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x {{.*}}>
+
// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]])
// LLVM: [[VGET_LANE:%.*]] = extractelement <8 x i8> [[A]], i32 7
// LLVM: ret i8 [[VGET_LANE]]
@@ -39,6 +39,7 @@ uint8_t test_vget_lane_u8(uint8x8_t a) {
// ALL-LABEL: @test_vget_lane_u16(
uint16_t test_vget_lane_u16(uint16x4_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x {{.*}}>
+
// LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]])
// LLVM: [[VGET_LANE:%.*]] = extractelement <4 x i16> [[A]], i32 3
// LLVM: ret i16 [[VGET_LANE]]
@@ -48,6 +49,7 @@ uint16_t test_vget_lane_u16(uint16x4_t a) {
// ALL-LABEL: @test_vget_lane_u32(
uint32_t test_vget_lane_u32(uint32x2_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x {{.*}}>
+
// LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]])
// LLVM: [[VGET_LANE:%.*]] = extractelement <2 x i32> [[A]], i32 1
// LLVM: ret i32 [[VGET_LANE]]
@@ -57,6 +59,7 @@ uint32_t test_vget_lane_u32(uint32x2_t a) {
// ALL-LABEL: @test_vget_lane_s8(
int8_t test_vget_lane_s8(int8x8_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !s8i>
+
// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]])
// LLVM: [[VGET_LANE:%.*]] = extractelement <8 x i8> [[A]], i32 7
// LLVM: ret i8 [[VGET_LANE]]
@@ -66,6 +69,7 @@ int8_t test_vget_lane_s8(int8x8_t a) {
// ALL-LABEL: @test_vget_lane_s16(
int16_t test_vget_lane_s16(int16x4_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !s16i>
+
// LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]])
// LLVM: [[VGET_LANE:%.*]] = extractelement <4 x i16> [[A]], i32 3
// LLVM: ret i16 [[VGET_LANE]]
@@ -75,6 +79,7 @@ int16_t test_vget_lane_s16(int16x4_t a) {
// ALL-LABEL: @test_vget_lane_s32(
int32_t test_vget_lane_s32(int32x2_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x !s32i>
+
// LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]])
// LLVM: [[VGET_LANE:%.*]] = extractelement <2 x i32> [[A]], i32 1
// LLVM: ret i32 [[VGET_LANE]]
@@ -84,6 +89,7 @@ int32_t test_vget_lane_s32(int32x2_t a) {
// ALL-LABEL: @test_vget_lane_p8(
poly8_t test_vget_lane_p8(poly8x8_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x {{.*}}>
+
// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]])
// LLVM: [[VGET_LANE:%.*]] = extractelement <8 x i8> [[A]], i32 7
// LLVM: ret i8 [[VGET_LANE]]
@@ -93,6 +99,7 @@ poly8_t test_vget_lane_p8(poly8x8_t a) {
// ALL-LABEL: @test_vget_lane_p16(
poly16_t test_vget_lane_p16(poly16x4_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x {{.*}}>
+
// LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]])
// LLVM: [[VGET_LANE:%.*]] = extractelement <4 x i16> [[A]], i32 3
// LLVM: ret i16 [[VGET_LANE]]
@@ -104,6 +111,7 @@ float32_t test_vget_lane_f16(float16x4_t a) {
// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<4 x !cir.f16>> -> !cir.ptr<!cir.vector<4 x !s16i>>
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !s16i>
// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!s16i> -> !cir.ptr<!cir.f16>
+
// LLVM-SAME: <4 x half> {{.*}} [[A:%.*]])
// LLVM: [[TMP:%.*]] = bitcast <4 x half> [[A]] to <4 x i16>
// LLVM: [[VGET_LANE:%.*]] = extractelement <4 x i16> [[TMP]], i32 1
@@ -116,6 +124,7 @@ float32_t test_vget_lane_f16(float16x4_t a) {
// ALL-LABEL: @test_vget_lane_f32(
float32_t test_vget_lane_f32(float32x2_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<2 x !cir.float>
+
// LLVM-SAME: <2 x float> {{.*}} [[A:%.*]])
// LLVM: [[VGET_LANE:%.*]] = extractelement <2 x float> [[A]], i32 1
// LLVM: ret float [[VGET_LANE]]
@@ -125,6 +134,7 @@ float32_t test_vget_lane_f32(float32x2_t a) {
// ALL-LABEL: @test_vget_lane_f64(
float64_t test_vget_lane_f64(float64x1_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<1 x !cir.double>
+
// LLVM-SAME: <1 x double> {{.*}} [[A:%.*]])
// LLVM: [[VGET_LANE:%.*]] = extractelement <1 x double> [[A]], i32 0
// LLVM: ret double [[VGET_LANE]]
@@ -134,6 +144,7 @@ float64_t test_vget_lane_f64(float64x1_t a) {
// ALL-LABEL: @test_vgetq_lane_u8(
uint8_t test_vgetq_lane_u8(uint8x16_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<16 x {{.*}}>
+
// LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]])
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> [[A]], i32 15
// LLVM: ret i8 [[VGETQ_LANE]]
@@ -143,6 +154,7 @@ uint8_t test_vgetq_lane_u8(uint8x16_t a) {
// ALL-LABEL: @test_vgetq_lane_u16(
uint16_t test_vgetq_lane_u16(uint16x8_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x {{.*}}>
+
// LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]])
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> [[A]], i32 7
// LLVM: ret i16 [[VGETQ_LANE]]
@@ -152,6 +164,7 @@ uint16_t test_vgetq_lane_u16(uint16x8_t a) {
// ALL-LABEL: @test_vgetq_lane_u32(
uint32_t test_vgetq_lane_u32(uint32x4_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x {{.*}}>
+
// LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]])
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> [[A]], i32 3
// LLVM: ret i32 [[VGETQ_LANE]]
@@ -161,6 +174,7 @@ uint32_t test_vgetq_lane_u32(uint32x4_t a) {
// ALL-LABEL: @test_vgetq_lane_s8(
int8_t test_vgetq_lane_s8(int8x16_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<16 x !s8i>
+
// LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]])
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> [[A]], i32 15
// LLVM: ret i8 [[VGETQ_LANE]]
@@ -170,6 +184,7 @@ int8_t test_vgetq_lane_s8(int8x16_t a) {
// ALL-LABEL: @test_vgetq_lane_s16(
int16_t test_vgetq_lane_s16(int16x8_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !s16i>
+
// LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]])
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> [[A]], i32 7
// LLVM: ret i16 [[VGETQ_LANE]]
@@ -179,6 +194,7 @@ int16_t test_vgetq_lane_s16(int16x8_t a) {
// ALL-LABEL: @test_vgetq_lane_s32(
int32_t test_vgetq_lane_s32(int32x4_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !s32i>
+
// LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]])
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> [[A]], i32 3
// LLVM: ret i32 [[VGETQ_LANE]]
@@ -188,6 +204,7 @@ int32_t test_vgetq_lane_s32(int32x4_t a) {
// ALL-LABEL: @test_vgetq_lane_p8(
poly8_t test_vgetq_lane_p8(poly8x16_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<16 x {{.*}}>
+
// LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]])
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> [[A]], i32 15
// LLVM: ret i8 [[VGETQ_LANE]]
@@ -197,6 +214,7 @@ poly8_t test_vgetq_lane_p8(poly8x16_t a) {
// ALL-LABEL: @test_vgetq_lane_p16(
poly16_t test_vgetq_lane_p16(poly16x8_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x {{.*}}>
+
// LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]])
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> [[A]], i32 7
// LLVM: ret i16 [[VGETQ_LANE]]
@@ -208,6 +226,7 @@ float32_t test_vgetq_lane_f16(float16x8_t a) {
// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!cir.vector<8 x !cir.f16>> -> !cir.ptr<!cir.vector<8 x !s16i>>
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !s16i>
// CIR: cir.cast bitcast %{{.*}} : !cir.ptr<!s16i> -> !cir.ptr<!cir.f16>
+
// LLVM-SAME: <8 x half> {{.*}} [[A:%.*]])
// LLVM: [[TMP:%.*]] = bitcast <8 x half> [[A]] to <8 x i16>
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> [[TMP]], i32 3
@@ -220,6 +239,7 @@ float32_t test_vgetq_lane_f16(float16x8_t a) {
// ALL-LABEL: @test_vgetq_lane_f32(
float32_t test_vgetq_lane_f32(float32x4_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<4 x !cir.float>
+
// LLVM-SAME: <4 x float> {{.*}} [[A:%.*]])
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <4 x float> [[A]], i32 3
// LLVM: ret float [[VGETQ_LANE]]
@@ -229,6 +249,7 @@ float32_t test_vgetq_lane_f32(float32x4_t a) {
// ALL-LABEL: @test_vgetq_lane_f64(
float64_t test_vgetq_lane_f64(float64x2_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<2 x !cir.double>
+
// LLVM-SAME: <2 x double> {{.*}} [[A:%.*]])
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <2 x double> [[A]], i32 1
// LLVM: ret double [[VGETQ_LANE]]
@@ -238,6 +259,7 @@ float64_t test_vgetq_lane_f64(float64x2_t a) {
// ALL-LABEL: @test_vget_lane_s64(
int64_t test_vget_lane_s64(int64x1_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<1 x !s64i>
+
// LLVM-SAME: <1 x i64> {{.*}} [[A:%.*]])
// LLVM: [[VGET_LANE:%.*]] = extractelement <1 x i64> [[A]], i32 0
// LLVM: ret i64 [[VGET_LANE]]
@@ -247,6 +269,7 @@ int64_t test_vget_lane_s64(int64x1_t a) {
// ALL-LABEL: @test_vget_lane_u64(
uint64_t test_vget_lane_u64(uint64x1_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<1 x {{.*}}>
+
// LLVM-SAME: <1 x i64> {{.*}} [[A:%.*]])
// LLVM: [[VGET_LANE:%.*]] = extractelement <1 x i64> [[A]], i32 0
// LLVM: ret i64 [[VGET_LANE]]
@@ -256,6 +279,7 @@ uint64_t test_vget_lane_u64(uint64x1_t a) {
// ALL-LABEL: @test_vget_lane_p64(
poly64_t test_vget_lane_p64(poly64x1_t v) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<1 x {{.*}}>
+
// LLVM-SAME: <1 x i64> {{.*}} [[V:%.*]])
// LLVM: [[VGET_LANE:%.*]] = extractelement <1 x i64> [[V]], i32 0
// LLVM: ret i64 [[VGET_LANE]]
@@ -265,6 +289,7 @@ poly64_t test_vget_lane_p64(poly64x1_t v) {
// ALL-LABEL: @test_vgetq_lane_s64(
int64_t test_vgetq_lane_s64(int64x2_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x !s64i>
+
// LLVM-SAME: <2 x i64> {{.*}} [[A:%.*]])
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> [[A]], i32 1
// LLVM: ret i64 [[VGETQ_LANE]]
@@ -274,6 +299,7 @@ int64_t test_vgetq_lane_s64(int64x2_t a) {
// ALL-LABEL: @test_vgetq_lane_u64(
uint64_t test_vgetq_lane_u64(uint64x2_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x {{.*}}>
+
// LLVM-SAME: <2 x i64> {{.*}} [[A:%.*]])
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> [[A]], i32 1
// LLVM: ret i64 [[VGETQ_LANE]]
@@ -283,6 +309,7 @@ uint64_t test_vgetq_lane_u64(uint64x2_t a) {
// ALL-LABEL: @test_vgetq_lane_p64(
poly64_t test_vgetq_lane_p64(poly64x2_t v) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x {{.*}}>
+
// LLVM-SAME: <2 x i64> {{.*}} [[V:%.*]])
// LLVM: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> [[V]], i32 1
// LLVM: ret i64 [[VGETQ_LANE]]
@@ -294,6 +321,7 @@ poly64_t test_vgetq_lane_p64(poly64x2_t v) {
// ALL-LABEL: @test_vdups_lane_f32(
float32_t test_vdups_lane_f32(float32x2_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<2 x !cir.float>
+
// LLVM-SAME: <2 x float> {{.*}} [[A:%.*]])
// LLVM: [[VDUP_LANE:%.*]] = extractelement <2 x float> [[A]], i32 1
// LLVM: ret float [[VDUP_LANE]]
@@ -303,6 +331,7 @@ float32_t test_vdups_lane_f32(float32x2_t a) {
// ALL-LABEL: @test_vdupd_lane_f64(
float64_t test_vdupd_lane_f64(float64x1_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<1 x !cir.double>
+
// LLVM-SAME: <1 x double> {{.*}} [[A:%.*]])
// LLVM: [[VDUP_LANE:%.*]] = extractelement <1 x double> [[A]], i32 0
// LLVM: ret double [[VDUP_LANE]]
@@ -312,6 +341,7 @@ float64_t test_vdupd_lane_f64(float64x1_t a) {
// ALL-LABEL: @test_vdups_laneq_f32(
float32_t test_vdups_laneq_f32(float32x4_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<4 x !cir.float>
+
// LLVM-SAME: <4 x float> {{.*}} [[A:%.*]])
// LLVM: [[VDUPQ_LANE:%.*]] = extractelement <4 x float> [[A]], i32 3
// LLVM: ret float [[VDUPQ_LANE]]
@@ -321,6 +351,7 @@ float32_t test_vdups_laneq_f32(float32x4_t a) {
// ALL-LABEL: @test_vdupd_laneq_f64(
float64_t test_vdupd_laneq_f64(float64x2_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<2 x !cir.double>
+
// LLVM-SAME: <2 x double> {{.*}} [[A:%.*]])
// LLVM: [[VDUPQ_LANE:%.*]] = extractelement <2 x double> [[A]], i32 1
// LLVM: ret double [[VDUPQ_LANE]]
@@ -330,6 +361,7 @@ float64_t test_vdupd_laneq_f64(float64x2_t a) {
// ALL-LABEL: @test_vdupb_lane_s8(
int8_t test_vdupb_lane_s8(int8x8_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !s8i>
+
// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]])
// LLVM: [[VDUP_LANE:%.*]] = extractelement <8 x i8> [[A]], i32 7
// LLVM: ret i8 [[VDUP_LANE]]
@@ -339,6 +371,7 @@ int8_t test_vdupb_lane_s8(int8x8_t a) {
// ALL-LABEL: @test_vduph_lane_s16(
int16_t test_vduph_lane_s16(int16x4_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !s16i>
+
// LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]])
// LLVM: [[VDUP_LANE:%.*]] = extractelement <4 x i16> [[A]], i32 3
// LLVM: ret i16 [[VDUP_LANE]]
@@ -348,6 +381,7 @@ int16_t test_vduph_lane_s16(int16x4_t a) {
// ALL-LABEL: @test_vdups_lane_s32(
int32_t test_vdups_lane_s32(int32x2_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x !s32i>
+
// LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]])
// LLVM: [[VDUP_LANE:%.*]] = extractelement <2 x i32> [[A]], i32 1
// LLVM: ret i32 [[VDUP_LANE]]
@@ -357,6 +391,7 @@ int32_t test_vdups_lane_s32(int32x2_t a) {
// ALL-LABEL: @test_vdupd_lane_s64(
int64_t test_vdupd_lane_s64(int64x1_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<1 x !s64i>
+
// LLVM-SAME: <1 x i64> {{.*}} [[A:%.*]])
// LLVM: [[VDUP_LANE:%.*]] = extractelement <1 x i64> [[A]], i32 0
// LLVM: ret i64 [[VDUP_LANE]]
@@ -366,6 +401,7 @@ int64_t test_vdupd_lane_s64(int64x1_t a) {
// ALL-LABEL: @test_vdupb_lane_u8(
uint8_t test_vdupb_lane_u8(uint8x8_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x {{.*}}>
+
// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]])
// LLVM: [[VDUP_LANE:%.*]] = extractelement <8 x i8> [[A]], i32 7
// LLVM: ret i8 [[VDUP_LANE]]
@@ -375,6 +411,7 @@ uint8_t test_vdupb_lane_u8(uint8x8_t a) {
// ALL-LABEL: @test_vduph_lane_u16(
uint16_t test_vduph_lane_u16(uint16x4_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x {{.*}}>
+
// LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]])
// LLVM: [[VDUP_LANE:%.*]] = extractelement <4 x i16> [[A]], i32 3
// LLVM: ret i16 [[VDUP_LANE]]
@@ -384,6 +421,7 @@ uint16_t test_vduph_lane_u16(uint16x4_t a) {
// ALL-LABEL: @test_vdups_lane_u32(
uint32_t test_vdups_lane_u32(uint32x2_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x {{.*}}>
+
// LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]])
// LLVM: [[VDUP_LANE:%.*]] = extractelement <2 x i32> [[A]], i32 1
// LLVM: ret i32 [[VDUP_LANE]]
@@ -393,6 +431,7 @@ uint32_t test_vdups_lane_u32(uint32x2_t a) {
// ALL-LABEL: @test_vdupd_lane_u64(
uint64_t test_vdupd_lane_u64(uint64x1_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<1 x {{.*}}>
+
// LLVM-SAME: <1 x i64> {{.*}} [[A:%.*]])
// LLVM: [[VDUP_LANE:%.*]] = extractelement <1 x i64> [[A]], i32 0
// LLVM: ret i64 [[VDUP_LANE]]
@@ -402,6 +441,7 @@ uint64_t test_vdupd_lane_u64(uint64x1_t a) {
// ALL-LABEL: @test_vdupb_laneq_s8(
int8_t test_vdupb_laneq_s8(int8x16_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<16 x !s8i>
+
// LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]])
// LLVM: [[VDUPQ_LANE:%.*]] = extractelement <16 x i8> [[A]], i32 15
// LLVM: ret i8 [[VDUPQ_LANE]]
@@ -411,6 +451,7 @@ int8_t test_vdupb_laneq_s8(int8x16_t a) {
// ALL-LABEL: @test_vduph_laneq_s16(
int16_t test_vduph_laneq_s16(int16x8_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !s16i>
+
// LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]])
// LLVM: [[VDUPQ_LANE:%.*]] = extractelement <8 x i16> [[A]], i32 7
// LLVM: ret i16 [[VDUPQ_LANE]]
@@ -420,6 +461,7 @@ int16_t test_vduph_laneq_s16(int16x8_t a) {
// ALL-LABEL: @test_vdups_laneq_s32(
int32_t test_vdups_laneq_s32(int32x4_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !s32i>
+
// LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]])
// LLVM: [[VDUPQ_LANE:%.*]] = extractelement <4 x i32> [[A]], i32 3
// LLVM: ret i32 [[VDUPQ_LANE]]
@@ -429,6 +471,7 @@ int32_t test_vdups_laneq_s32(int32x4_t a) {
// ALL-LABEL: @test_vdupd_laneq_s64(
int64_t test_vdupd_laneq_s64(int64x2_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x !s64i>
+
// LLVM-SAME: <2 x i64> {{.*}} [[A:%.*]])
// LLVM: [[VDUPQ_LANE:%.*]] = extractelement <2 x i64> [[A]], i32 1
// LLVM: ret i64 [[VDUPQ_LANE]]
@@ -438,6 +481,7 @@ int64_t test_vdupd_laneq_s64(int64x2_t a) {
// ALL-LABEL: @test_vdupb_laneq_u8(
uint8_t test_vdupb_laneq_u8(uint8x16_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<16 x {{.*}}>
+
// LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]])
// LLVM: [[VDUPQ_LANE:%.*]] = extractelement <16 x i8> [[A]], i32 15
// LLVM: ret i8 [[VDUPQ_LANE]]
@@ -447,6 +491,7 @@ uint8_t test_vdupb_laneq_u8(uint8x16_t a) {
// ALL-LABEL: @test_vduph_laneq_u16(
uint16_t test_vduph_laneq_u16(uint16x8_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x {{.*}}>
+
// LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]])
// LLVM: [[VDUPQ_LANE:%.*]] = extractelement <8 x i16> [[A]], i32 7
// LLVM: ret i16 [[VDUPQ_LANE]]
@@ -456,6 +501,7 @@ uint16_t test_vduph_laneq_u16(uint16x8_t a) {
// ALL-LABEL: @test_vdups_laneq_u32(
uint32_t test_vdups_laneq_u32(uint32x4_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x {{.*}}>
+
// LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]])
// LLVM: [[VDUPQ_LANE:%.*]] = extractelement <4 x i32> [[A]], i32 3
// LLVM: ret i32 [[VDUPQ_LANE]]
@@ -465,6 +511,7 @@ uint32_t test_vdups_laneq_u32(uint32x4_t a) {
// ALL-LABEL: @test_vdupd_laneq_u64(
uint64_t test_vdupd_laneq_u64(uint64x2_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<2 x {{.*}}>
+
// LLVM-SAME: <2 x i64> {{.*}} [[A:%.*]])
// LLVM: [[VDUPQ_LANE:%.*]] = extractelement <2 x i64> [[A]], i32 1
// LLVM: ret i64 [[VDUPQ_LANE]]
@@ -474,6 +521,7 @@ uint64_t test_vdupd_laneq_u64(uint64x2_t a) {
// ALL-LABEL: @test_vdupb_lane_p8(
poly8_t test_vdupb_lane_p8(poly8x8_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x {{.*}}>
+
// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]])
// LLVM: [[VDUP_LANE:%.*]] = extractelement <8 x i8> [[A]], i32 7
// LLVM: ret i8 [[VDUP_LANE]]
@@ -483,6 +531,7 @@ poly8_t test_vdupb_lane_p8(poly8x8_t a) {
// ALL-LABEL: @test_vduph_lane_p16(
poly16_t test_vduph_lane_p16(poly16x4_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x {{.*}}>
+
// LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]])
// LLVM: [[VDUP_LANE:%.*]] = extractelement <4 x i16> [[A]], i32 3
// LLVM: ret i16 [[VDUP_LANE]]
@@ -492,6 +541,7 @@ poly16_t test_vduph_lane_p16(poly16x4_t a) {
// ALL-LABEL: @test_vdupb_laneq_p8(
poly8_t test_vdupb_laneq_p8(poly8x16_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<16 x {{.*}}>
+
// LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]])
// LLVM: [[VDUPQ_LANE:%.*]] = extractelement <16 x i8> [[A]], i32 15
// LLVM: ret i8 [[VDUPQ_LANE]]
@@ -501,6 +551,7 @@ poly8_t test_vdupb_laneq_p8(poly8x16_t a) {
// ALL-LABEL: @test_vduph_laneq_p16(
poly16_t test_vduph_laneq_p16(poly16x8_t a) {
// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x {{.*}}>
+
// LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]])
// LLVM: [[VDUPQ_LANE:%.*]] = extractelement <8 x i16> [[A]], i32 7
// LLVM: ret i16 [[VDUPQ_LANE]]
diff --git a/clang/test/CodeGen/AArch64/poly64.c b/clang/test/CodeGen/AArch64/poly64.c
index b1eb6f249ac90..3ccb02a3a14c6 100644
--- a/clang/test/CodeGen/AArch64/poly64.c
+++ b/clang/test/CodeGen/AArch64/poly64.c
@@ -61,26 +61,6 @@ uint64x2_t test_vtstq_p64(poly64x2_t a, poly64x2_t b) {
return vtstq_p64(a, b);
}
-// CHECK-LABEL: define dso_local i64 @test_vget_lane_p64(
-// CHECK-SAME: <1 x i64> noundef [[V:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <1 x i64> [[V]], i32 0
-// CHECK-NEXT: ret i64 [[VGET_LANE]]
-//
-poly64_t test_vget_lane_p64(poly64x1_t v) {
- return vget_lane_p64(v, 0);
-}
-
-// CHECK-LABEL: define dso_local i64 @test_vgetq_lane_p64(
-// CHECK-SAME: <2 x i64> noundef [[V:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> [[V]], i32 1
-// CHECK-NEXT: ret i64 [[VGETQ_LANE]]
-//
-poly64_t test_vgetq_lane_p64(poly64x2_t v) {
- return vgetq_lane_p64(v, 1);
-}
-
// CHECK-LABEL: define dso_local <1 x i64> @test_vset_lane_p64(
// CHECK-SAME: i64 noundef [[A:%.*]], <1 x i64> noundef [[V:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
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