[clang] [CIR][AArch64] Upstream for vector vector shl (PR #191655)
via cfe-commits
cfe-commits at lists.llvm.org
Sun May 10 01:45:53 PDT 2026
https://github.com/albertbolt1 updated https://github.com/llvm/llvm-project/pull/191655
>From 9e883bc77477ec5d3e676d137273c7182b2ac733 Mon Sep 17 00:00:00 2001
From: albertbolt <albertboltinfinity at gmail.com>
Date: Sat, 11 Apr 2026 23:04:13 +0530
Subject: [PATCH 01/10] added vector vector shl
---
clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index 75dd19d880444..7c0395b225fc8 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -740,6 +740,12 @@ static mlir::Value emitCommonNeonBuiltinExpr(
std::string("unimplemented AArch64 builtin call: ") +
ctx.BuiltinInfo.getName(builtinID));
return mlir::Value{};
+ case NEON::BI__builtin_neon_vshl_v:
+ case NEON::BI__builtin_neon_vshlq_v:
+ return cir::ShiftOp::create(cgf.getBuilder(), loc, vTy,
+ cgf.getBuilder().createBitcast(ops[0], vTy),
+ cgf.getBuilder().createBitcast(ops[1], vTy),
+ true);
case NEON::BI__builtin_neon_vmul_v:
case NEON::BI__builtin_neon_vmulq_v:
return cgf.getBuilder().emitIntrinsicCallOp(loc, "aarch64.neon.pmul", vTy,
>From 096f5a68283c06e29855bdfd7a05ff3caf58e4d3 Mon Sep 17 00:00:00 2001
From: albertbolt <albertboltinfinity at gmail.com>
Date: Sat, 25 Apr 2026 17:06:49 +0530
Subject: [PATCH 02/10] added code for vshl_v vshlq_v types
---
.../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 18 +-
clang/test/CodeGen/AArch64/neon-intrinsics.c | 234 ----------------
clang/test/CodeGen/AArch64/neon/intrinsics.c | 254 ++++++++++++++++++
3 files changed, 266 insertions(+), 240 deletions(-)
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index 7c0395b225fc8..121f5123f2a55 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -741,11 +741,17 @@ static mlir::Value emitCommonNeonBuiltinExpr(
ctx.BuiltinInfo.getName(builtinID));
return mlir::Value{};
case NEON::BI__builtin_neon_vshl_v:
- case NEON::BI__builtin_neon_vshlq_v:
- return cir::ShiftOp::create(cgf.getBuilder(), loc, vTy,
- cgf.getBuilder().createBitcast(ops[0], vTy),
- cgf.getBuilder().createBitcast(ops[1], vTy),
- true);
+ case NEON::BI__builtin_neon_vshlq_v: {
+ llvm::StringRef llvmIntrName =
+ getLLVMIntrNameNoPrefix(static_cast<llvm::Intrinsic::ID>(
+ usgn ? llvmIntrinsic : altLLVMIntrinsic));
+ mlir::Value result = emitNeonCall(cgf.getCIRGenModule(), cgf.getBuilder(),
+ /*argTypes=*/{vTy, vTy}, ops,
+ llvmIntrName,
+ /*funcResTy=*/vTy, loc);
+ mlir::Type resultType = cgf.convertType(expr->getType());
+ return cgf.getBuilder().createBitcast(result, resultType);
+ }
case NEON::BI__builtin_neon_vmul_v:
case NEON::BI__builtin_neon_vmulq_v:
return cgf.getBuilder().emitIntrinsicCallOp(loc, "aarch64.neon.pmul", vTy,
@@ -2085,7 +2091,7 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
// Not all intrinsics handled by the common case work for AArch64 yet, so only
// defer to common code if it's been added to our special map.
builtin = findARMVectorIntrinsicInMap(AArch64SIMDIntrinsicMap, builtinID,
- aarch64SIMDIntrinsicsProvenSorted);
+ aarch64SIMDIntrinsicsProvenSorted);
if (builtin)
return emitCommonNeonBuiltinExpr(
*this, builtin->BuiltinID, builtin->LLVMIntrinsic,
diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c
index 82a10b626c223..4e3ceb85977f5 100644
--- a/clang/test/CodeGen/AArch64/neon-intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c
@@ -3798,240 +3798,6 @@ uint64x2_t test_vqsubq_u64(uint64x2_t a, uint64x2_t b) {
return vqsubq_u64(a, b);
}
-// CHECK-LABEL: define dso_local <8 x i8> @test_vshl_s8(
-// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VSHL_V_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.sshl.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])
-// CHECK-NEXT: ret <8 x i8> [[VSHL_V_I]]
-//
-int8x8_t test_vshl_s8(int8x8_t a, int8x8_t b) {
- return vshl_s8(a, b);
-}
-
-// CHECK-LABEL: define dso_local <4 x i16> @test_vshl_s16(
-// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>
-// CHECK-NEXT: [[VSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[VSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
-// CHECK-NEXT: [[VSHL_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sshl.v4i16(<4 x i16> [[VSHL_V_I]], <4 x i16> [[VSHL_V1_I]])
-// CHECK-NEXT: [[VSHL_V3_I:%.*]] = bitcast <4 x i16> [[VSHL_V2_I]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VSHL_V3_I]] to <4 x i16>
-// CHECK-NEXT: ret <4 x i16> [[TMP2]]
-//
-int16x4_t test_vshl_s16(int16x4_t a, int16x4_t b) {
- return vshl_s16(a, b);
-}
-
-// CHECK-LABEL: define dso_local <2 x i32> @test_vshl_s32(
-// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>
-// CHECK-NEXT: [[VSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
-// CHECK-NEXT: [[VSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
-// CHECK-NEXT: [[VSHL_V2_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.sshl.v2i32(<2 x i32> [[VSHL_V_I]], <2 x i32> [[VSHL_V1_I]])
-// CHECK-NEXT: [[VSHL_V3_I:%.*]] = bitcast <2 x i32> [[VSHL_V2_I]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VSHL_V3_I]] to <2 x i32>
-// CHECK-NEXT: ret <2 x i32> [[TMP2]]
-//
-int32x2_t test_vshl_s32(int32x2_t a, int32x2_t b) {
- return vshl_s32(a, b);
-}
-
-// CHECK-LABEL: define dso_local <1 x i64> @test_vshl_s64(
-// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>
-// CHECK-NEXT: [[VSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: [[VSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
-// CHECK-NEXT: [[VSHL_V2_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.sshl.v1i64(<1 x i64> [[VSHL_V_I]], <1 x i64> [[VSHL_V1_I]])
-// CHECK-NEXT: [[VSHL_V3_I:%.*]] = bitcast <1 x i64> [[VSHL_V2_I]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VSHL_V3_I]] to i64
-// CHECK-NEXT: [[REF_TMP_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i32 0
-// CHECK-NEXT: ret <1 x i64> [[REF_TMP_I_SROA_0_0_VEC_INSERT]]
-//
-int64x1_t test_vshl_s64(int64x1_t a, int64x1_t b) {
- return vshl_s64(a, b);
-}
-
-// CHECK-LABEL: define dso_local <8 x i8> @test_vshl_u8(
-// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VSHL_V_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.ushl.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])
-// CHECK-NEXT: ret <8 x i8> [[VSHL_V_I]]
-//
-uint8x8_t test_vshl_u8(uint8x8_t a, int8x8_t b) {
- return vshl_u8(a, b);
-}
-
-// CHECK-LABEL: define dso_local <4 x i16> @test_vshl_u16(
-// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>
-// CHECK-NEXT: [[VSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
-// CHECK-NEXT: [[VSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
-// CHECK-NEXT: [[VSHL_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.ushl.v4i16(<4 x i16> [[VSHL_V_I]], <4 x i16> [[VSHL_V1_I]])
-// CHECK-NEXT: [[VSHL_V3_I:%.*]] = bitcast <4 x i16> [[VSHL_V2_I]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VSHL_V3_I]] to <4 x i16>
-// CHECK-NEXT: ret <4 x i16> [[TMP2]]
-//
-uint16x4_t test_vshl_u16(uint16x4_t a, int16x4_t b) {
- return vshl_u16(a, b);
-}
-
-// CHECK-LABEL: define dso_local <2 x i32> @test_vshl_u32(
-// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>
-// CHECK-NEXT: [[VSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
-// CHECK-NEXT: [[VSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
-// CHECK-NEXT: [[VSHL_V2_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.ushl.v2i32(<2 x i32> [[VSHL_V_I]], <2 x i32> [[VSHL_V1_I]])
-// CHECK-NEXT: [[VSHL_V3_I:%.*]] = bitcast <2 x i32> [[VSHL_V2_I]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VSHL_V3_I]] to <2 x i32>
-// CHECK-NEXT: ret <2 x i32> [[TMP2]]
-//
-uint32x2_t test_vshl_u32(uint32x2_t a, int32x2_t b) {
- return vshl_u32(a, b);
-}
-
-// CHECK-LABEL: define dso_local <1 x i64> @test_vshl_u64(
-// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>
-// CHECK-NEXT: [[VSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
-// CHECK-NEXT: [[VSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
-// CHECK-NEXT: [[VSHL_V2_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.ushl.v1i64(<1 x i64> [[VSHL_V_I]], <1 x i64> [[VSHL_V1_I]])
-// CHECK-NEXT: [[VSHL_V3_I:%.*]] = bitcast <1 x i64> [[VSHL_V2_I]] to <8 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VSHL_V3_I]] to i64
-// CHECK-NEXT: [[REF_TMP_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i32 0
-// CHECK-NEXT: ret <1 x i64> [[REF_TMP_I_SROA_0_0_VEC_INSERT]]
-//
-uint64x1_t test_vshl_u64(uint64x1_t a, int64x1_t b) {
- return vshl_u64(a, b);
-}
-
-// CHECK-LABEL: define dso_local <16 x i8> @test_vshlq_s8(
-// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VSHLQ_V_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.sshl.v16i8(<16 x i8> [[A]], <16 x i8> [[B]])
-// CHECK-NEXT: ret <16 x i8> [[VSHLQ_V_I]]
-//
-int8x16_t test_vshlq_s8(int8x16_t a, int8x16_t b) {
- return vshlq_s8(a, b);
-}
-
-// CHECK-LABEL: define dso_local <8 x i16> @test_vshlq_s16(
-// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>
-// CHECK-NEXT: [[VSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[VSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>
-// CHECK-NEXT: [[VSHLQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.sshl.v8i16(<8 x i16> [[VSHLQ_V_I]], <8 x i16> [[VSHLQ_V1_I]])
-// CHECK-NEXT: [[VSHLQ_V3_I:%.*]] = bitcast <8 x i16> [[VSHLQ_V2_I]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VSHLQ_V3_I]] to <8 x i16>
-// CHECK-NEXT: ret <8 x i16> [[TMP2]]
-//
-int16x8_t test_vshlq_s16(int16x8_t a, int16x8_t b) {
- return vshlq_s16(a, b);
-}
-
-// CHECK-LABEL: define dso_local <4 x i32> @test_vshlq_s32(
-// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>
-// CHECK-NEXT: [[VSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
-// CHECK-NEXT: [[VSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
-// CHECK-NEXT: [[VSHLQ_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> [[VSHLQ_V_I]], <4 x i32> [[VSHLQ_V1_I]])
-// CHECK-NEXT: [[VSHLQ_V3_I:%.*]] = bitcast <4 x i32> [[VSHLQ_V2_I]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VSHLQ_V3_I]] to <4 x i32>
-// CHECK-NEXT: ret <4 x i32> [[TMP2]]
-//
-int32x4_t test_vshlq_s32(int32x4_t a, int32x4_t b) {
- return vshlq_s32(a, b);
-}
-
-// CHECK-LABEL: define dso_local <2 x i64> @test_vshlq_s64(
-// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>
-// CHECK-NEXT: [[VSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[VSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
-// CHECK-NEXT: [[VSHLQ_V2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sshl.v2i64(<2 x i64> [[VSHLQ_V_I]], <2 x i64> [[VSHLQ_V1_I]])
-// CHECK-NEXT: [[VSHLQ_V3_I:%.*]] = bitcast <2 x i64> [[VSHLQ_V2_I]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VSHLQ_V3_I]] to <2 x i64>
-// CHECK-NEXT: ret <2 x i64> [[TMP2]]
-//
-int64x2_t test_vshlq_s64(int64x2_t a, int64x2_t b) {
- return vshlq_s64(a, b);
-}
-
-// CHECK-LABEL: define dso_local <16 x i8> @test_vshlq_u8(
-// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[VSHLQ_V_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.ushl.v16i8(<16 x i8> [[A]], <16 x i8> [[B]])
-// CHECK-NEXT: ret <16 x i8> [[VSHLQ_V_I]]
-//
-uint8x16_t test_vshlq_u8(uint8x16_t a, int8x16_t b) {
- return vshlq_u8(a, b);
-}
-
-// CHECK-LABEL: define dso_local <8 x i16> @test_vshlq_u16(
-// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>
-// CHECK-NEXT: [[VSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
-// CHECK-NEXT: [[VSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>
-// CHECK-NEXT: [[VSHLQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.ushl.v8i16(<8 x i16> [[VSHLQ_V_I]], <8 x i16> [[VSHLQ_V1_I]])
-// CHECK-NEXT: [[VSHLQ_V3_I:%.*]] = bitcast <8 x i16> [[VSHLQ_V2_I]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VSHLQ_V3_I]] to <8 x i16>
-// CHECK-NEXT: ret <8 x i16> [[TMP2]]
-//
-uint16x8_t test_vshlq_u16(uint16x8_t a, int16x8_t b) {
- return vshlq_u16(a, b);
-}
-
-// CHECK-LABEL: define dso_local <4 x i32> @test_vshlq_u32(
-// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>
-// CHECK-NEXT: [[VSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
-// CHECK-NEXT: [[VSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
-// CHECK-NEXT: [[VSHLQ_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.ushl.v4i32(<4 x i32> [[VSHLQ_V_I]], <4 x i32> [[VSHLQ_V1_I]])
-// CHECK-NEXT: [[VSHLQ_V3_I:%.*]] = bitcast <4 x i32> [[VSHLQ_V2_I]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VSHLQ_V3_I]] to <4 x i32>
-// CHECK-NEXT: ret <4 x i32> [[TMP2]]
-//
-uint32x4_t test_vshlq_u32(uint32x4_t a, int32x4_t b) {
- return vshlq_u32(a, b);
-}
-
-// CHECK-LABEL: define dso_local <2 x i64> @test_vshlq_u64(
-// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT: [[ENTRY:.*:]]
-// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>
-// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>
-// CHECK-NEXT: [[VSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
-// CHECK-NEXT: [[VSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
-// CHECK-NEXT: [[VSHLQ_V2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.ushl.v2i64(<2 x i64> [[VSHLQ_V_I]], <2 x i64> [[VSHLQ_V1_I]])
-// CHECK-NEXT: [[VSHLQ_V3_I:%.*]] = bitcast <2 x i64> [[VSHLQ_V2_I]] to <16 x i8>
-// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VSHLQ_V3_I]] to <2 x i64>
-// CHECK-NEXT: ret <2 x i64> [[TMP2]]
-//
-uint64x2_t test_vshlq_u64(uint64x2_t a, int64x2_t b) {
- return vshlq_u64(a, b);
-}
-
// CHECK-LABEL: define dso_local <8 x i8> @test_vqshl_s8(
// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c
index 241ddce6fe978..45630b128ab64 100644
--- a/clang/test/CodeGen/AArch64/neon/intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c
@@ -2010,6 +2010,260 @@ uint64x1_t test_vshl_n_u64(uint64x1_t a) {
return vshl_n_u64(a, 1);
}
+// LLVM-LABEL: test_vshl_s8
+// CIR-LABEL: vshl_s8
+int8x8_t test_vshl_s8(int8x8_t a, int8x8_t b) {
+// CIR: [[RES:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.sshl" %{{.*}}, %{{.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>) -> !cir.vector<8 x !s8i>
+
+// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]], <8 x i8> {{.*}} [[B:%.*]]) #{{.*}} {
+// LLVM: [[VSHL_V_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.sshl.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])
+// LLVM: ret <8 x i8> [[VSHL_V_I]]
+ return vshl_s8(a, b);
+}
+
+// LLVM-LABEL: test_vshl_s16
+// CIR-LABEL: vshl_s16
+int16x4_t test_vshl_s16(int16x4_t a, int16x4_t b) {
+// CIR: [[RES:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.sshl" %{{.*}}, %{{.*}} : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>) -> !cir.vector<4 x !s16i>
+
+// LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]], <4 x i16> {{.*}} [[B:%.*]]) #{{.*}} {
+// LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
+// LLVM: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>
+// LLVM: [[VSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
+// LLVM: [[VSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
+// LLVM: [[VSHL_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sshl.v4i16(<4 x i16> [[VSHL_V_I]], <4 x i16> [[VSHL_V1_I]])
+// LLVM: [[VSHL_V3_I:%.*]] = bitcast <4 x i16> [[VSHL_V2_I]] to <8 x i8>
+// LLVM: [[TMP2:%.*]] = bitcast <8 x i8> [[VSHL_V3_I]] to <4 x i16>
+// LLVM: ret <4 x i16> [[TMP2]]
+ return vshl_s16(a, b);
+}
+
+// LLVM-LABEL: test_vshl_s32
+// CIR-LABEL: vshl_s32
+int32x2_t test_vshl_s32(int32x2_t a, int32x2_t b) {
+// CIR: [[RES:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.sshl" %{{.*}}, %{{.*}} : (!cir.vector<2 x !s32i>, !cir.vector<2 x !s32i>) -> !cir.vector<2 x !s32i>
+
+// LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]], <2 x i32> {{.*}} [[B:%.*]]) #{{.*}} {
+// LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>
+// LLVM: [[VSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
+// LLVM: [[VSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
+// LLVM: [[VSHL_V2_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.sshl.v2i32(<2 x i32> [[VSHL_V_I]], <2 x i32> [[VSHL_V1_I]])
+// LLVM: [[VSHL_V3_I:%.*]] = bitcast <2 x i32> [[VSHL_V2_I]] to <8 x i8>
+// LLVM: [[TMP2:%.*]] = bitcast <8 x i8> [[VSHL_V3_I]] to <2 x i32>
+// LLVM: ret <2 x i32> [[TMP2]]
+ return vshl_s32(a, b);
+}
+
+// LLVM-LABEL: test_vshl_s64
+// CIR-LABEL: vshl_s64
+int64x1_t test_vshl_s64(int64x1_t a, int64x1_t b) {
+// CIR: [[RES:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.sshl" %{{.*}}, %{{.*}} : (!cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>) -> !cir.vector<1 x !s64i>
+
+// LLVM: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>
+// LLVM: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>
+// LLVM: [[VSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
+// LLVM: [[VSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
+// LLVM: [[VSHL_V2_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.sshl.v1i64(<1 x i64> [[VSHL_V_I]], <1 x i64> [[VSHL_V1_I]])
+// LLVM: [[VSHL_V3_I:%.*]] = bitcast <1 x i64> [[VSHL_V2_I]] to <8 x i8>
+// LLVM: [[TMP2:%.*]] = bitcast <8 x i8> [[VSHL_V3_I]] to i64
+// LLVM: [[REF_TMP_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i32 0
+// LLVM-NEXT: ret <1 x i64> [[REF_TMP_I_SROA_0_0_VEC_INSERT]]
+ return vshl_s64(a, b);
+}
+
+// LLVM-LABEL: test_vshl_u8
+// CIR-LABEL: vshl_u8
+uint8x8_t test_vshl_u8(uint8x8_t a, int8x8_t b) {
+// CIR: [[RES:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ushl" %{{.*}}, %{{.*}} : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>) -> !cir.vector<8 x !u8i>
+
+// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]], <8 x i8> {{.*}} [[B:%.*]]) #[[ATTR0]] {
+// LLVM: [[VSHL_V_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.ushl.v8i8(<8 x i8> [[A]], <8 x i8> [[B]])
+// LLVM: ret <8 x i8> [[VSHL_V_I]]
+ return vshl_u8(a, b);
+}
+
+// LLVM-LABEL: test_vshl_u16
+// CIR-LABEL: vshl_u16
+uint16x4_t test_vshl_u16(uint16x4_t a, int16x4_t b) {
+// CIR: [[RES:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ushl" %{{.*}}, %{{.*}} : (!cir.vector<4 x !u16i>, !cir.vector<4 x !u16i>) -> !cir.vector<4 x !u16i>
+
+// LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]], <4 x i16> {{.*}} [[B:%.*]]) #{{.*}} {
+// LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8>
+// LLVM: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8>
+// LLVM: [[VSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
+// LLVM: [[VSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
+// LLVM: [[VSHL_V2_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.ushl.v4i16(<4 x i16> [[VSHL_V_I]], <4 x i16> [[VSHL_V1_I]])
+// LLVM: [[VSHL_V3_I:%.*]] = bitcast <4 x i16> [[VSHL_V2_I]] to <8 x i8>
+// LLVM: [[TMP2:%.*]] = bitcast <8 x i8> [[VSHL_V3_I]] to <4 x i16>
+// LLVM: ret <4 x i16> [[TMP2]]
+ return vshl_u16(a, b);
+}
+
+// LLVM-LABEL: test_vshl_u32
+// CIR-LABEL: vshl_u32
+uint32x2_t test_vshl_u32(uint32x2_t a, int32x2_t b) {
+// CIR: [[RES:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ushl" %{{.*}}, %{{.*}} : (!cir.vector<2 x !u32i>, !cir.vector<2 x !u32i>) -> !cir.vector<2 x !u32i>
+
+// LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]], <2 x i32> {{.*}} [[B:%.*]]) #{{.*}} {
+// LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8>
+// LLVM: [[VSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
+// LLVM: [[VSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
+// LLVM: [[VSHL_V2_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.ushl.v2i32(<2 x i32> [[VSHL_V_I]], <2 x i32> [[VSHL_V1_I]])
+// LLVM: [[VSHL_V3_I:%.*]] = bitcast <2 x i32> [[VSHL_V2_I]] to <8 x i8>
+// LLVM: [[TMP2:%.*]] = bitcast <8 x i8> [[VSHL_V3_I]] to <2 x i32>
+// LLVM: ret <2 x i32> [[TMP2]]
+ return vshl_u32(a, b);
+}
+
+// LLVM-LABEL: test_vshl_u64
+// CIR-LABEL: vshl_u64
+uint64x1_t test_vshl_u64(uint64x1_t a, int64x1_t b) {
+// CIR: [[RES:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ushl" %{{.*}}, %{{.*}} : (!cir.vector<1 x !u64i>, !cir.vector<1 x !u64i>) -> !cir.vector<1 x !u64i>
+
+// LLVM-SAME: <1 x i64> {{.*}} [[A:%.*]], <1 x i64> {{.*}} [[B:%.*]]) #{{.*}} {
+// LLVM: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>
+// LLVM: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8>
+// LLVM: [[VSHL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
+// LLVM: [[VSHL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
+// LLVM: [[VSHL_V2_I:%.*]] = call <1 x i64> @llvm.aarch64.neon.ushl.v1i64(<1 x i64> [[VSHL_V_I]], <1 x i64> [[VSHL_V1_I]])
+// LLVM: [[VSHL_V3_I:%.*]] = bitcast <1 x i64> [[VSHL_V2_I]] to <8 x i8>
+// LLVM: [[TMP2:%.*]] = bitcast <8 x i8> [[VSHL_V3_I]] to i64
+// LLVM: [[REF_TMP_I_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP2]], i32 0
+// LLVM: ret <1 x i64> [[REF_TMP_I_SROA_0_0_VEC_INSERT]]
+ return vshl_u64(a, b);
+}
+
+// LLVM-LABEL: test_vshlq_s8
+// CIR-LABEL: vshlq_s8
+int8x16_t test_vshlq_s8(int8x16_t a, int8x16_t b) {
+// CIR: [[RES:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.sshl" %{{.*}}, %{{.*}} : (!cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>) -> !cir.vector<16 x !s8i>
+
+// LLVM: <16 x i8> {{.*}} [[A:%.*]], <16 x i8> {{.*}} [[B:%.*]]) #{{.*}} {
+// LLVM: [[VSHLQ_V_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.sshl.v16i8(<16 x i8> [[A]], <16 x i8> [[B]])
+// LLVM: ret <16 x i8> [[VSHLQ_V_I]]
+ return vshlq_s8(a, b);
+}
+
+// LLVM-LABEL: test_vshlq_s16
+// CIR-LABEL: vshlq_s16
+int16x8_t test_vshlq_s16(int16x8_t a, int16x8_t b) {
+// CIR: [[RES:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.sshl" %{{.*}}, %{{.*}} : (!cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>) -> !cir.vector<8 x !s16i>
+
+
+// LLVM: <8 x i16> {{.*}} [[A:%.*]], <8 x i16> {{.*}} [[B:%.*]]) #{{.*}} {
+// LLVM: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
+// LLVM: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>
+// LLVM: [[VSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
+// LLVM: [[VSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>
+// LLVM: [[VSHLQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.sshl.v8i16(<8 x i16> [[VSHLQ_V_I]], <8 x i16> [[VSHLQ_V1_I]])
+// LLVM: [[VSHLQ_V3_I:%.*]] = bitcast <8 x i16> [[VSHLQ_V2_I]] to <16 x i8>
+// LLVM: [[TMP2:%.*]] = bitcast <16 x i8> [[VSHLQ_V3_I]] to <8 x i16>
+// LLVM: ret <8 x i16> [[TMP2]]
+//
+ return vshlq_s16(a, b);
+}
+
+// LLVM-LABEL: test_vshlq_s32
+// CIR-LABEL: vshlq_s32
+int32x4_t test_vshlq_s32(int32x4_t a, int32x4_t b) {
+// CIR: [[RES:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.sshl" %{{.*}}, %{{.*}} : (!cir.vector<4 x !s32i>, !cir.vector<4 x !s32i>) -> !cir.vector<4 x !s32i>
+
+// LLVM: <4 x i32> {{.*}} [[A:%.*]], <4 x i32> {{.*}} [[B:%.*]]) #{{.*}} {
+// LLVM: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>
+// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>
+// LLVM: [[VSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
+// LLVM: [[VSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
+// LLVM: [[VSHLQ_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> [[VSHLQ_V_I]], <4 x i32> [[VSHLQ_V1_I]])
+// LLVM: [[VSHLQ_V3_I:%.*]] = bitcast <4 x i32> [[VSHLQ_V2_I]] to <16 x i8>
+// LLVM: [[TMP2:%.*]] = bitcast <16 x i8> [[VSHLQ_V3_I]] to <4 x i32>
+// LLVM: ret <4 x i32> [[TMP2]]
+ return vshlq_s32(a, b);
+}
+
+// LLVM-LABEL: test_vshlq_s64
+// CIR-LABEL: vshlq_s64
+int64x2_t test_vshlq_s64(int64x2_t a, int64x2_t b) {
+// CIR: [[RES:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.sshl" %{{.*}}, %{{.*}} : (!cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>) -> !cir.vector<2 x !s64i>
+
+// LLVM: <2 x i64> {{.*}} [[A:%.*]], <2 x i64> {{.*}} [[B:%.*]]) #{{.*}} {
+// LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>
+// LLVM: [[VSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
+// LLVM: [[VSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
+// LLVM: [[VSHLQ_V2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.sshl.v2i64(<2 x i64> [[VSHLQ_V_I]], <2 x i64> [[VSHLQ_V1_I]])
+// LLVM: [[VSHLQ_V3_I:%.*]] = bitcast <2 x i64> [[VSHLQ_V2_I]] to <16 x i8>
+// LLVM: [[TMP2:%.*]] = bitcast <16 x i8> [[VSHLQ_V3_I]] to <2 x i64>
+// LLVM: ret <2 x i64> [[TMP2]]
+ return vshlq_s64(a, b);
+}
+
+// LLVM-LABEL: test_vshlq_u8
+// CIR-LABEL: vshlq_u8
+uint8x16_t test_vshlq_u8(uint8x16_t a, int8x16_t b) {
+// CIR: [[RES:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ushl" %{{.*}}, %{{.*}} : (!cir.vector<16 x !u8i>, !cir.vector<16 x !u8i>) -> !cir.vector<16 x !u8i>
+
+// LLVM: <16 x i8> {{.*}} [[A:%.*]], <16 x i8> {{.*}} [[B:%.*]]) #{{.*}} {
+// LLVM: [[VSHLQ_V_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.ushl.v16i8(<16 x i8> [[A]], <16 x i8> [[B]])
+// LLVM: ret <16 x i8> [[VSHLQ_V_I]]
+ return vshlq_u8(a, b);
+}
+
+// LLVM-LABEL: test_vshlq_u16
+// CIR-LABEL: vshlq_u16
+uint16x8_t test_vshlq_u16(uint16x8_t a, int16x8_t b) {
+// CIR: [[RES:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ushl" %{{.*}}, %{{.*}} : (!cir.vector<8 x !u16i>, !cir.vector<8 x !u16i>) -> !cir.vector<8 x !u16i>
+
+
+// LLVM: <8 x i16> {{.*}} [[A:%.*]], <8 x i16> {{.*}} [[B:%.*]]) #{{.*}} {
+// LLVM: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
+// LLVM: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8>
+// LLVM: [[VSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
+// LLVM: [[VSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>
+// LLVM: [[VSHLQ_V2_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.ushl.v8i16(<8 x i16> [[VSHLQ_V_I]], <8 x i16> [[VSHLQ_V1_I]])
+// LLVM: [[VSHLQ_V3_I:%.*]] = bitcast <8 x i16> [[VSHLQ_V2_I]] to <16 x i8>
+// LLVM: [[TMP2:%.*]] = bitcast <16 x i8> [[VSHLQ_V3_I]] to <8 x i16>
+// LLVM: ret <8 x i16> [[TMP2]]
+//
+ return vshlq_u16(a, b);
+}
+
+
+// LLVM-LABEL: test_vshlq_u32
+// CIR-LABEL: vshlq_u32
+uint32x4_t test_vshlq_u32(uint32x4_t a, int32x4_t b) {
+// CIR: [[RES:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ushl" %{{.*}}, %{{.*}} : (!cir.vector<4 x !u32i>, !cir.vector<4 x !u32i>) -> !cir.vector<4 x !u32i>
+
+// LLVM: <4 x i32> {{.*}} [[A:%.*]], <4 x i32> {{.*}} [[B:%.*]]) #{{.*}} {
+// LLVM: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>
+// LLVM: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8>
+// LLVM: [[VSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
+// LLVM: [[VSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
+// LLVM: [[VSHLQ_V2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.ushl.v4i32(<4 x i32> [[VSHLQ_V_I]], <4 x i32> [[VSHLQ_V1_I]])
+// LLVM: [[VSHLQ_V3_I:%.*]] = bitcast <4 x i32> [[VSHLQ_V2_I]] to <16 x i8>
+// LLVM: [[TMP2:%.*]] = bitcast <16 x i8> [[VSHLQ_V3_I]] to <4 x i32>
+// LLVM: ret <4 x i32> [[TMP2]]
+ return vshlq_u32(a, b);
+}
+
+// LLVM-LABEL: test_vshlq_u64
+// CIR-LABEL: vshlq_u64
+uint64x2_t test_vshlq_u64(uint64x2_t a, int64x2_t b) {
+// CIR: [[RES:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ushl" %{{.*}}, %{{.*}} : (!cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>) -> !cir.vector<2 x !u64i>
+
+// LLVM: <2 x i64> {{.*}} [[A:%.*]], <2 x i64> {{.*}} [[B:%.*]]) #{{.*}} {
+// LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>
+// LLVM: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8>
+// LLVM: [[VSHLQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
+// LLVM: [[VSHLQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
+// LLVM: [[VSHLQ_V2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.ushl.v2i64(<2 x i64> [[VSHLQ_V_I]], <2 x i64> [[VSHLQ_V1_I]])
+// LLVM: [[VSHLQ_V3_I:%.*]] = bitcast <2 x i64> [[VSHLQ_V2_I]] to <16 x i8>
+// LLVM: [[TMP2:%.*]] = bitcast <16 x i8> [[VSHLQ_V3_I]] to <2 x i64>
+// LLVM: ret <2 x i64> [[TMP2]]
+ return vshlq_u64(a, b);
+}
+
//===------------------------------------------------------===//
// 2.1.3.2.1 Vector shift right
//===------------------------------------------------------===//
>From 39d53a04efab8fad44c0cfac9a5b78cac3894dc1 Mon Sep 17 00:00:00 2001
From: albertbolt <albertboltinfinity at gmail.com>
Date: Sat, 25 Apr 2026 18:06:23 +0530
Subject: [PATCH 03/10] added code for vshl_v vshlq_v types
---
clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index 121f5123f2a55..613599c034208 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -745,13 +745,13 @@ static mlir::Value emitCommonNeonBuiltinExpr(
llvm::StringRef llvmIntrName =
getLLVMIntrNameNoPrefix(static_cast<llvm::Intrinsic::ID>(
usgn ? llvmIntrinsic : altLLVMIntrinsic));
- mlir::Value result = emitNeonCall(cgf.getCIRGenModule(), cgf.getBuilder(),
- /*argTypes=*/{vTy, vTy}, ops,
- llvmIntrName,
- /*funcResTy=*/vTy, loc);
+ mlir::Value result =
+ emitNeonCall(cgf.getCIRGenModule(), cgf.getBuilder(),
+ /*argTypes=*/{vTy, vTy}, ops, llvmIntrName,
+ /*funcResTy=*/vTy, loc);
mlir::Type resultType = cgf.convertType(expr->getType());
return cgf.getBuilder().createBitcast(result, resultType);
- }
+ }
case NEON::BI__builtin_neon_vmul_v:
case NEON::BI__builtin_neon_vmulq_v:
return cgf.getBuilder().emitIntrinsicCallOp(loc, "aarch64.neon.pmul", vTy,
>From 3096c92063d30722dcb07425bbbca946f1a184ea Mon Sep 17 00:00:00 2001
From: albertbolt <albertboltinfinity at gmail.com>
Date: Sat, 25 Apr 2026 18:40:10 +0530
Subject: [PATCH 04/10] added code for vshl_v vshlq_v types
---
clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index 613599c034208..254ea98a7c151 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -745,7 +745,7 @@ static mlir::Value emitCommonNeonBuiltinExpr(
llvm::StringRef llvmIntrName =
getLLVMIntrNameNoPrefix(static_cast<llvm::Intrinsic::ID>(
usgn ? llvmIntrinsic : altLLVMIntrinsic));
- mlir::Value result =
+ mlir::Value result =
emitNeonCall(cgf.getCIRGenModule(), cgf.getBuilder(),
/*argTypes=*/{vTy, vTy}, ops, llvmIntrName,
/*funcResTy=*/vTy, loc);
@@ -2091,8 +2091,7 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
// Not all intrinsics handled by the common case work for AArch64 yet, so only
// defer to common code if it's been added to our special map.
builtin = findARMVectorIntrinsicInMap(AArch64SIMDIntrinsicMap, builtinID,
- aarch64SIMDIntrinsicsProvenSorted);
- if (builtin)
+ aarch64SIMDIntrinsicsProvenSorted);
return emitCommonNeonBuiltinExpr(
*this, builtin->BuiltinID, builtin->LLVMIntrinsic,
builtin->AltLLVMIntrinsic, builtin->NameHint, builtin->TypeModifier,
>From 07a0cf8fdd8ea661e337edec11f7f97eb544ddba Mon Sep 17 00:00:00 2001
From: albertbolt <albertboltinfinity at gmail.com>
Date: Sat, 25 Apr 2026 18:47:24 +0530
Subject: [PATCH 05/10] added code for vshl_v vshlq_v types
---
clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index 254ea98a7c151..66811271d32d2 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -2092,6 +2092,7 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
// defer to common code if it's been added to our special map.
builtin = findARMVectorIntrinsicInMap(AArch64SIMDIntrinsicMap, builtinID,
aarch64SIMDIntrinsicsProvenSorted);
+ if (builtin)
return emitCommonNeonBuiltinExpr(
*this, builtin->BuiltinID, builtin->LLVMIntrinsic,
builtin->AltLLVMIntrinsic, builtin->NameHint, builtin->TypeModifier,
>From dfa0021ec9396b029b96ed8bea76ca64246a1b27 Mon Sep 17 00:00:00 2001
From: albertbolt <albertboltinfinity at gmail.com>
Date: Sun, 3 May 2026 10:43:01 +0530
Subject: [PATCH 06/10] updated code as per review
---
.../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 29 +++++++------------
1 file changed, 11 insertions(+), 18 deletions(-)
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index 66811271d32d2..c2528fb9bf99f 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -740,18 +740,6 @@ static mlir::Value emitCommonNeonBuiltinExpr(
std::string("unimplemented AArch64 builtin call: ") +
ctx.BuiltinInfo.getName(builtinID));
return mlir::Value{};
- case NEON::BI__builtin_neon_vshl_v:
- case NEON::BI__builtin_neon_vshlq_v: {
- llvm::StringRef llvmIntrName =
- getLLVMIntrNameNoPrefix(static_cast<llvm::Intrinsic::ID>(
- usgn ? llvmIntrinsic : altLLVMIntrinsic));
- mlir::Value result =
- emitNeonCall(cgf.getCIRGenModule(), cgf.getBuilder(),
- /*argTypes=*/{vTy, vTy}, ops, llvmIntrName,
- /*funcResTy=*/vTy, loc);
- mlir::Type resultType = cgf.convertType(expr->getType());
- return cgf.getBuilder().createBitcast(result, resultType);
- }
case NEON::BI__builtin_neon_vmul_v:
case NEON::BI__builtin_neon_vmulq_v:
return cgf.getBuilder().emitIntrinsicCallOp(loc, "aarch64.neon.pmul", vTy,
@@ -762,17 +750,22 @@ static mlir::Value emitCommonNeonBuiltinExpr(
case NEON::BI__builtin_neon_vbfdot_f32:
case NEON::BI__builtin_neon_vbfdotq_f32:
case NEON::BI__builtin_neon___a32_vcvt_bf16_f32:
- default:
- cgf.cgm.errorNYI(expr->getSourceRange(),
- std::string("unimplemented AArch64 builtin call: ") +
- ctx.BuiltinInfo.getName(builtinID));
- return mlir::Value{};
-
cgf.cgm.errorNYI(expr->getSourceRange(),
std::string("unimplemented AArch64 builtin call: ") +
ctx.BuiltinInfo.getName(builtinID));
return mlir::Value{};
}
+
+ llvm::StringRef llvmIntrName =
+ getLLVMIntrNameNoPrefix(static_cast<llvm::Intrinsic::ID>(
+ usgn ? llvmIntrinsic : altLLVMIntrinsic));
+
+ mlir::Value result =
+ emitNeonCall(cgf.getCIRGenModule(), cgf.getBuilder(),
+ /*argTypes=*/{vTy, vTy}, ops, llvmIntrName,
+ /*funcResTy=*/vTy, loc);
+ mlir::Type resultType = cgf.convertType(expr->getType());
+ return cgf.getBuilder().createBitcast(result, resultType);
}
// Emit an intrinsic where all operands are of the same type as the result.
>From b6972ce4db741f5a118645590170f45933d6ca8a Mon Sep 17 00:00:00 2001
From: albertbolt <albertboltinfinity at gmail.com>
Date: Mon, 4 May 2026 13:17:41 +0530
Subject: [PATCH 07/10] updated code as per review
---
clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index 22751961ec080..939ffa402387f 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -842,16 +842,16 @@ static mlir::Value emitCommonNeonBuiltinExpr(
return mlir::Value{};
}
- llvm::StringRef llvmIntrName =
- getLLVMIntrNameNoPrefix(static_cast<llvm::Intrinsic::ID>(
- usgn ? llvmIntrinsic : altLLVMIntrinsic));
+ llvm::StringRef llvmIntrName =
+ getLLVMIntrNameNoPrefix(static_cast<llvm::Intrinsic::ID>(
+ usgn ? llvmIntrinsic : altLLVMIntrinsic));
- mlir::Value result =
- emitNeonCall(cgf.getCIRGenModule(), cgf.getBuilder(),
- /*argTypes=*/{vTy, vTy}, ops, llvmIntrName,
- /*funcResTy=*/vTy, loc);
- mlir::Type resultType = cgf.convertType(expr->getType());
- return cgf.getBuilder().createBitcast(result, resultType);
+ mlir::Value result =
+ emitNeonCall(cgf.getCIRGenModule(), cgf.getBuilder(),
+ /*argTypes=*/{vTy, vTy}, ops, llvmIntrName,
+ /*funcResTy=*/vTy, loc);
+ mlir::Type resultType = cgf.convertType(expr->getType());
+ return cgf.getBuilder().createBitcast(result, resultType);
}
// Emit an intrinsic where all operands are of the same type as the result.
>From cd8177c6928438b929af70a5a8913d9a59755c59 Mon Sep 17 00:00:00 2001
From: albertbolt <albertboltinfinity at gmail.com>
Date: Mon, 4 May 2026 15:21:18 +0530
Subject: [PATCH 08/10] updated code as per review
---
clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index 970a91bfe93b7..18c320d997886 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -857,12 +857,11 @@ static mlir::Value emitCommonNeonBuiltinExpr(
llvm::StringRef llvmIntrName =
getLLVMIntrNameNoPrefix(static_cast<llvm::Intrinsic::ID>(
- usgn ? llvmIntrinsic : altLLVMIntrinsic));
+ usgn ? llvmIntrinsic : altLLVMIntrinsic));
- mlir::Value result =
- emitNeonCall(cgf.getCIRGenModule(), cgf.getBuilder(),
- /*argTypes=*/{vTy, vTy}, ops, llvmIntrName,
- /*funcResTy=*/vTy, loc);
+ mlir::Value result = emitNeonCall(cgf.getCIRGenModule(), cgf.getBuilder(),
+ /*argTypes=*/{vTy, vTy}, ops, llvmIntrName,
+ /*funcResTy=*/vTy, loc);
mlir::Type resultType = cgf.convertType(expr->getType());
return cgf.getBuilder().createBitcast(result, resultType);
}
>From 38ac2088e20a196b694bd55fd626a215aee58bb8 Mon Sep 17 00:00:00 2001
From: albertbolt <albertboltinfinity at gmail.com>
Date: Mon, 4 May 2026 21:10:39 +0530
Subject: [PATCH 09/10] updated code as per review
---
clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index 18c320d997886..6ea7196cc0ee4 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -858,7 +858,7 @@ static mlir::Value emitCommonNeonBuiltinExpr(
llvm::StringRef llvmIntrName =
getLLVMIntrNameNoPrefix(static_cast<llvm::Intrinsic::ID>(
usgn ? llvmIntrinsic : altLLVMIntrinsic));
-
+
mlir::Value result = emitNeonCall(cgf.getCIRGenModule(), cgf.getBuilder(),
/*argTypes=*/{vTy, vTy}, ops, llvmIntrName,
/*funcResTy=*/vTy, loc);
>From 6e4ead9a19300e5459b090e276f2fa0e35a3fddf Mon Sep 17 00:00:00 2001
From: albertbolt <albertboltinfinity at gmail.com>
Date: Sun, 10 May 2026 14:12:02 +0530
Subject: [PATCH 10/10] review comments considered
---
.../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 35 ++++++++++++++-----
1 file changed, 26 insertions(+), 9 deletions(-)
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index 6ea7196cc0ee4..67af78139ced4 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -855,15 +855,32 @@ static mlir::Value emitCommonNeonBuiltinExpr(
return mlir::Value{};
}
- llvm::StringRef llvmIntrName =
- getLLVMIntrNameNoPrefix(static_cast<llvm::Intrinsic::ID>(
- usgn ? llvmIntrinsic : altLLVMIntrinsic));
-
- mlir::Value result = emitNeonCall(cgf.getCIRGenModule(), cgf.getBuilder(),
- /*argTypes=*/{vTy, vTy}, ops, llvmIntrName,
- /*funcResTy=*/vTy, loc);
- mlir::Type resultType = cgf.convertType(expr->getType());
- return cgf.getBuilder().createBitcast(result, resultType);
+ // The switch stmt is intended to help catch NYI cases and will be removed
+ // once the CIR implementation is complete. Avoid adding specialized
+ // code in cases - that should only be required for a handful of examples.
+ switch (builtinID) {
+ default:
+ cgf.cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented AArch64 builtin call: ") +
+ cgf.getContext().BuiltinInfo.getName(builtinID));
+ break;
+ case NEON::BI__builtin_neon_vshl_v:
+ case NEON::BI__builtin_neon_vshlq_v: {
+ llvm::StringRef llvmIntrName =
+ getLLVMIntrNameNoPrefix(static_cast<llvm::Intrinsic::ID>(
+ usgn ? llvmIntrinsic : altLLVMIntrinsic));
+
+ mlir::Value result =
+ emitNeonCall(cgf.getCIRGenModule(), cgf.getBuilder(),
+ /*argTypes=*/{vTy, vTy}, ops, llvmIntrName,
+ /*funcResTy=*/vTy, loc);
+ mlir::Type resultType = cgf.convertType(expr->getType());
+ return cgf.getBuilder().createBitcast(result, resultType);
+ }
+ }
+
+ // NYI
+ return nullptr;
}
// Emit an intrinsic where all operands are of the same type as the result.
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